[PATCH] ata: pata_pdc2027x: fix division by zero in pdc_adjust_pll

[Yang Zi <2959243019@qq.com>]

pdc_adjust_pll() divides pout_required by pll_clock_khz before checking
that pll_clock_khz is within the valid range. If the PLL input clock is
less than 1000 Hz, pll_clock_khz is 0 and the division triggers a
divide-by-zero error.

Move the sanity check ahead of the division so the invalid input is
rejected before the ratio is computed.

Signed-off-by: Yang Zi <2959243019@qq.com>
---
diff --git a/drivers/ata/pata_pdc2027x.c b/drivers/ata/pata_pdc2027x.c
index d1d1cfb22e27..c4cff4eafbe8 100644
--- a/drivers/ata/pata_pdc2027x.c
+++ b/drivers/ata/pata_pdc2027x.c
@@ -517,7 +517,7 @@ static void pdc_adjust_pll(struct ata_host *host, long pll_clock, unsigned int b
     u16 pll_ctl;
     long pll_clock_khz = pll_clock / 1000;
     long pout_required = board_idx? PDC_133_MHZ:PDC_100_MHZ;
-    long ratio = pout_required / pll_clock_khz;
+    long ratio;
     int F, R;
 
     /* Sanity check */
@@ -527,6 +527,8 @@ static void pdc_adjust_pll(struct ata_host *host, long pll_clock, unsigned int b
         return;
     }
 
+    ratio = pout_required / pll_clock_khz;
+
     dev_dbg(host->dev, "pout_required is %ld\n", pout_required);
 
     /* Show the current clock value of PLL control register