Re: [PATCH 3/6] spi: add multi_bus_mode field to struct spi_transfer

["Nuno Sá" <noname.nuno@gmail.com>]

On Wed, 2025-10-15 at 13:01 +0100, Mark Brown wrote:
> On Wed, Oct 15, 2025 at 11:16:01AM +0100, Nuno Sá wrote:
> > On Tue, 2025-10-14 at 17:02 -0500, David Lechner wrote:
> 
> > >         controller    < data bits <     peripheral
> > >         ----------   ----------------   ----------
> > >             SDI 0    0-0-0-1-0-0-0-1    SDO 0
> > >             SDI 1    1-0-0-0-1-0-0-0    SDO 1
> 
> > Out of curiosity, how does this work for devices like AD4030 where the same
> > word
> > is kind of interleaved between SDO lines? I guess it works the same (in
> > terms of
> > SW) and is up to some IP core (typically in the FPGA) to "re-assemble" the
> > word?
> 
> So combined with the existing parallel SPI support?

Not sure if this is meant for me :). parallel SPI is for parallel memories and
the spi_device multi cs support stuff right? I tried to track it down but it's
not clear if there are any users already upstream (qspi zynqmp and the nor
flashes). It looks like it's not in yet but not sure.

Anyways, IIUC, it seems we could indeed see the device I mentioned as a parallel
kind of thing as we have one bit per lane per sclk. However, the multi_cs
concept does not apply (so I think it would be misleading to try and hack it
around with tweaking cs_index_mask and related APIs).

Given the current API, maybe it makes sense to add (in the future) a
SPI_MULTI_BUS_MODE_PARALLEL or David already intends to support it in the
current STRIPE mode and I'm misunderstanding.

- Nuno Sá