From: Caesar Wang <wxt@rock-chips.com>
To: jic23@kernel.org
Cc: heiko@sntech.de, robh+dt@kernel.org, linux-iio@vger.kernel.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux@roeck-us.net,
dianders@chromium.org, Caesar Wang <wxt@rock-chips.com>
Subject: [PATCH 3/4] arm64: dts: rockchip: add reset saradc node for rk3368 SoCs
Date: Tue, 26 Jul 2016 14:11:49 +0800 [thread overview]
Message-ID: <1469513510-1516-3-git-send-email-wxt@rock-chips.com> (raw)
In-Reply-To: <1469513510-1516-1-git-send-email-wxt@rock-chips.com>
SARADC controller needs to be reset before programming it, otherwise
it will not function properly.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---
arch/arm64/boot/dts/rockchip/rk3368.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index d02a9003..4f44d11 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -270,6 +270,8 @@
#io-channel-cells = <1>;
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
clock-names = "saradc", "apb_pclk";
+ resets = <&cru SRST_SARADC>;
+ reset-names = "saradc-apb";
status = "disabled";
};
--
1.9.1
next prev parent reply other threads:[~2016-07-26 6:12 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-26 6:11 [PATCH 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it Caesar Wang
2016-07-26 6:11 ` [PATCH 2/4] arm64: dts: rockchip: add the saradc for rk3399 Caesar Wang
2016-07-26 6:11 ` Caesar Wang [this message]
2016-07-26 6:11 ` [PATCH 4/4] arm: dts: rockchip: add reset node for the exist saradc SoCs Caesar Wang
2016-07-26 9:00 ` [PATCH 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it John Keeping
2016-07-26 10:49 ` Caesar Wang
2016-07-26 11:16 ` John Keeping
2016-07-26 9:17 ` Heiko Stübner
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