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[2003:f6:ef03:6f00:5de6:a4d0:d791:ed01]) by smtp.gmail.com with ESMTPSA id e25-20020ac86719000000b0031ec38da567sm12661680qtp.0.2022.07.20.02.24.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Jul 2022 02:24:41 -0700 (PDT) Message-ID: <1fa1dda81b17cc9d40d9916bed68ea4eab7dfcdf.camel@gmail.com> Subject: Re: [PATCH v2 1/3] iio: adc: add max11410 adc driver From: Nuno =?ISO-8859-1?Q?S=E1?= To: Ibrahim Tilki , jic23@kernel.org Cc: linux-iio@vger.kernel.org, Nuno.Sa@analog.com, Nurettin.Bolucu@analog.com, andy.shevchenko@gmail.com Date: Wed, 20 Jul 2022 11:25:39 +0200 In-Reply-To: <20220719145932.96-2-Ibrahim.Tilki@analog.com> References: <20220707174739.21fe67ea@jic23-huawei> <20220719145932.96-2-Ibrahim.Tilki@analog.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.44.3 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org On Tue, 2022-07-19 at 14:59 +0000, Ibrahim Tilki wrote: > > On Thu, 7 Jul 2022 08:31:24 +0000 > > Ibrahim Tilki wrote: > >=20 > > > Adding support for max11410 24-bit, 1.9ksps delta-sigma adc which > > > has 3 differential reference and 10 differential channel inputs. > > > Inputs and references can be buffered internally. Inputs can also > > > be amplified with internal PGA. > > >=20 > > > Device has a digital filter that is controlled by a custom sysfs > > > attribute. > > > User has four options to choose from: fir50/60, fir50, fir60 and > > > sinc4. > > > Digital filter selection affects sampling frequency range so > > > driver > > > has to consider the configured filter when configuring sampling > > > frequency. > > >=20 > > > Signed-off-by: Ibrahim Tilki > > > Reviewed-by: Nurettin Bolucu > >=20 > > Hi Ibrahim, > >=20 > > As you probably expect, quite a bit of the feedback inline is about > > the > > custom sysfs attribute. I think we need to fit that more closely to > > the current > > filter ABI.=C2=A0 It's not a perfect fit however, but I make some > > suggestions inline. > >=20 > > thanks, > >=20 > > Jonathan > >=20 >=20 > Hi Jonathan, >=20 > Thanks for the review, I've resolved most of the items and will send > v3 soon after > I perform some more tests with the hardware. In the meantime I have > some questions inline. >=20 > Regards, > Ibrahim >=20 > ... >=20 > > > +static int max11410_read_reg(struct max11410_state *st, > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 unsigned int reg, > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 int *val) > > > +{ > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0u8 data[3]; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0int ret; > > > + > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0if (max11410_reg_size(reg)= =3D=3D 3) { > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0ret =3D regmap_bulk_read(st->regmap, reg, data, 3); > >=20 > > Ah. There is a fun corner here.=C2=A0 SPI bulk reads in general > > require DMA safe buffers (basically they need to be on the heap, > > not the > > stack and we need to enforce that nothing else shares a cacheline > > with them). > > Now, last time I checked regmap happens to always end up using a > > safe bounce > > buffer, but it's not documented as such and there is no guarantee > > it will continue > > to do so.=C2=A0 We checked this with the maintainer a while back and th= e > > answer > > was to always use DMA safe buffers with bulk accesses. > > Whilst that might have changed, I've not heard anything about it > > doing so. > >=20 >=20 > So I guess having this would solve dma alignment and the leak issue > in max11410_trigger_handler > and the data field can be shared between? >=20 > struct max11410_state { > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0// ... > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0struct { > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0int data ____cacheline_aligned; > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0s64 ts __aligned(8); > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0} scan; > }; >=20 Just a note on this one... You want to use 'IIO_DMA_MINALIGN' and not ____cacheline_aligned. https://lore.kernel.org/linux-iio/20220508175712.647246-1-jic23@kernel.org/ - Nuno S=C3=A1