Re: [PATCH v2] iio: imu: st_lsm6dsx: disable I3C support during device reset

[Lorenzo Bianconi <lorenzo@kernel.org>]

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> From: Lorenzo Bianconi <lorenzo@kernel.org>
> Date: Mon, Mar 09, 2020 at 15:01:01
> 
> > > Hi Lorenzo,
> > > 
> > > From: Lorenzo Bianconi <lorenzo@kernel.org>
> > > Date: Sun, Mar 08, 2020 at 00:06:03
> > > 
> > > > Disable MIPI I3C during device reset in order to avoid
> > > > possible races on interrupt line 1. If the first interrupt
> > > > line is asserted during hw reset the device will work in
> > > > I3C-only mode
> > > > 
> > 
> > [...]
> > 
> > > > +
> > > 
> > > After disable the i3c interface the dynamic address is no more accessible 
> > > and fails the initialization.
> > > 
> > 
> > Hi Vitor,
> > 
> > thx for testing it. What do you mean here?
> > Is int1 set to vdd in your test?
> > 
> > Regards,
> > Lorenzo
> 
> Yes, according with figure 14 of lsm6dso datasheet.

uhm..probably we should do this configuration if the device is not in I3C-only
mode. Are you able to test it without setting the int1 to vdd?
Unfortunately I have no devices with an I3C controller yet.

Regards,
Lorenzo

> 
> Is there any way to clear the INT1 before the hw reset?
> 
> Best regards,
> Vitor Soares
> 
> > 
> > > Best regards,
> > > Vitor Soares
> > > 
> > > >  	/* device sw reset */
> > > >  	reg = &hw->settings->reset;
> > > >  	err = regmap_update_bits(hw->regmap, reg->addr, reg->mask,
> > > > @@ -2059,6 +2081,15 @@ static int st_lsm6dsx_init_device(struct st_lsm6dsx_hw *hw)
> > > >  
> > > >  	msleep(50);
> > > >  
> > > > +	/* enable MIPI I3C */
> > > > +	if (hw->settings->i3c_disable.addr) {
> > > > +		reg = &hw->settings->i3c_disable;
> > > > +		err = regmap_update_bits(hw->regmap, reg->addr, reg->mask,
> > > > +					 ST_LSM6DSX_SHIFT_VAL(0, reg->mask));
> > > > +		if (err < 0)
> > > > +			return err;
> > > > +	}
> > > > +
> > > >  	/* enable Block Data Update */
> > > >  	reg = &hw->settings->bdu;
> > > >  	err = regmap_update_bits(hw->regmap, reg->addr, reg->mask,
> > > > -- 
> > > > 2.24.1
> > > 
> > > 
> 
> 

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