From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8BFC0C7EE24 for ; Tue, 30 May 2023 17:24:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233420AbjE3RYr (ORCPT ); Tue, 30 May 2023 13:24:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51040 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232951AbjE3RYX (ORCPT ); Tue, 30 May 2023 13:24:23 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 723D91A2; Tue, 30 May 2023 10:23:39 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id BFF9863127; Tue, 30 May 2023 17:22:11 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id DD3DCC433D2; Tue, 30 May 2023 17:22:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1685467331; bh=QewfULGDzQw9U8Sjf5XkcO2JdMdAuFaRZdNueC5s0yU=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=fn1PZNRTwL8dtH+YSdMWiNxKTQgLI4jjWZPrXGNCw2bmxXzetvhdi9uvapssaeNjy PUrqQse5a27RfWC7mwGnoRmLnCWHKKUZvu/SFHvbUG37WakyZdMohzKouEQyHHfHhJ ZSbBbqLMmyrTkkZ8TXpZNzLEtl73JaPbMr1QJ5Pnu6z1Ch3bOVgJtlFNx5N+RXEo6g RkxZ935caiXca5SPQMLraZ2jZeGfO7fLcobwhwkvIVeY7Khm2/Ab2kb4rlbU8nR5Wv UfCqBJ3I/pH4qW34pbsYZkdcyequfJKYDDvqj7d7uHGZ4YSYJAC4B3rl+/5DZdqajx M84uaqqx+gPYw== Date: Tue, 30 May 2023 18:22:06 +0100 From: Conor Dooley To: fl.scratchpad@gmail.com Cc: jic23@kernel.org, Lars-Peter Clausen , Michael Hennerich , Alexandru Tachici , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v3 5/5] dt-bindings: iio: ad7192: Allow selection of clock modes Message-ID: <20230530-cannabis-headstone-883c5b891dd3@spud> References: <20230530075311.400686-1-fl.scratchpad@gmail.com> <20230530075311.400686-6-fl.scratchpad@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="GOC40fJ/cBBzzJa4" Content-Disposition: inline In-Reply-To: <20230530075311.400686-6-fl.scratchpad@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org --GOC40fJ/cBBzzJa4 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, May 30, 2023 at 09:53:11AM +0200, fl.scratchpad@gmail.com wrote: > From: Fabrizio Lamarque >=20 > AD7192 supports external clock sources, generated by a digital clock > source or a crystal oscillator, or internally generated clock option > without external components. >=20 > Describe choice between internal and external clock, crystal or external > oscillator, and internal clock output enable. >=20 > Signed-off-by: Fabrizio Lamarque > --- > .../bindings/iio/adc/adi,ad7192.yaml | 27 ++++++++++++++++--- > 1 file changed, 24 insertions(+), 3 deletions(-) >=20 > diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml b/= Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml > index 16def2985ab4..f7ecfd65ad80 100644 > --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml > +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml > @@ -32,7 +32,8 @@ properties: > =20 > clocks: > maxItems: 1 > - description: phandle to the master clock (mclk) > + description: | > + Master clock (mclk). If not set, internal clock is used. > =20 > clock-names: > items: > @@ -50,6 +51,17 @@ properties: > vref-supply: > description: VRef voltage supply > =20 > + adi,clock-xtal: > + description: | > + Select whether an external crystal oscillator or an external > + clock is applied as master (mclk) clock. > + type: boolean Am I being daft, or are these the same thing? If they are not, and use different input pins, I think it should be explained as it not clear. Could you explain why we actually care that the source is a xtal versus it being mclk, and why just having master clock is not sufficient? > + adi,int-clock-output-enable: > + description: | > + When internal clock is selected, this bit enables clock out pin. > + type: boolean And this one makes you a clock provider, so the devices advocate position would be that you know that this bit should be set if "clocks" is not present and a consumer requests a clock. I don't seem to have got the driver patches (at least not in this mailbox), so I have got no information on how you've actually implemented this. Cheers, Conor. > + > adi,rejection-60-Hz-enable: > description: | > This bit enables a notch at 60 Hz when the first notch of the sinc > @@ -84,11 +96,12 @@ properties: > description: see Documentation/devicetree/bindings/iio/adc/adc.yaml > type: boolean > =20 > +dependencies: > + adi,clock-xtal: ['clocks', 'clock-names'] > + > required: > - compatible > - reg > - - clocks > - - clock-names > - interrupts > - dvdd-supply > - avdd-supply > @@ -98,6 +111,13 @@ required: > =20 > allOf: > - $ref: /schemas/spi/spi-peripheral-props.yaml# > + - if: > + required: > + - clocks > + - clock-names > + then: > + properties: > + adi,int-clock-output-enable: false > =20 > unevaluatedProperties: false > =20 > @@ -115,6 +135,7 @@ examples: > spi-cpha; > clocks =3D <&ad7192_mclk>; > clock-names =3D "mclk"; > + adi,clock-xtal; > interrupts =3D <25 0x2>; > interrupt-parent =3D <&gpio>; > dvdd-supply =3D <&dvdd>; > --=20 > 2.34.1 >=20 --GOC40fJ/cBBzzJa4 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZHYwvgAKCRB4tDGHoIJi 0qkFAP9uZ1N8bFxZsXbgW8kQo1+vlYKpinjPWQHQw4vNab1QdAEAiMZn03LxwMx2 /4Q9ctSo9xBk9Le4GVYdC0z4WQRcWgs= =KNs6 -----END PGP SIGNATURE----- --GOC40fJ/cBBzzJa4--