Re: [PATCH v2 17/22] iio: accel: adxl345: push FIFO data to iio

[Jonathan Cameron <jic23@kernel.org>]

On Sun, 17 Nov 2024 18:26:46 +0000
Lothar Rubusch <l.rubusch@gmail.com> wrote:

> Add FIFO and hwfifo handling. Add some functions to deal with FIFO
> entries and configuration. This feature will be needed for e.g.
> watermark setting.
> 
> Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
> ---
>  drivers/iio/accel/adxl345_core.c | 38 ++++++++++++++++++++++++++++++++
>  1 file changed, 38 insertions(+)
> 
> diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_core.c
> index d58e1994ff..a653774db8 100644
> --- a/drivers/iio/accel/adxl345_core.c
> +++ b/drivers/iio/accel/adxl345_core.c
> @@ -437,6 +437,41 @@ static int adxl345_get_status(struct adxl34x_state *st, u8 *int_stat)
>  	return 0;
>  }
>  
> +static int adxl345_push_fifo_data(struct iio_dev *indio_dev,
> +				  u8 status,
> +				  int fifo_entries)
> +{
> +	struct adxl34x_state *st = iio_priv(indio_dev);
> +	int ndirs = 3; /* 3 directions */
It's const. Maybe a define is appropriate instead?
> +	int i, ret;
> +
> +	if (fifo_entries <= 0)
> +		return true;
It returns an int. Also how did you get in here with negative fifo
entries?  That rather suggests something went wrong at the caller.

> +
> +	ret = adxl345_read_fifo_elements(st, fifo_entries);
> +	if (ret)
> +		return false;
> +
> +	for (i = 0; i < ndirs * fifo_entries; i += ndirs) {
> +		/* To ensure that the FIFO has completely popped, there must be at least 5
Comment format.

> +		 * us between the end of reading the data registers, signified by the
> +		 * transition to register 0x38 from 0x37 or the CS pin going high, and the
> +		 * start of new reads of the FIFO or reading the FIFO_STATUS register. For
> +		 * SPI operation at 1.5 MHz or lower, the register addressing portion of the
> +		 * transmission is sufficient delay to ensure the FIFO has completely
> +		 * popped. It is necessary for SPI operation greater than 1.5 MHz to
> +		 * de-assert the CS pin to ensure a total of 5 us, which is at most 3.4 us
> +		 * at 5 MHz operation.
> +		 */
> +		if (st->fifo_delay && (fifo_entries > 1))
> +			udelay(3);
> +
> +		iio_push_to_buffers(indio_dev, &st->fifo_buf[i]);
> +	}
> +
> +	return true;
> +}
> +