From: Jonathan Cameron <jic23@kernel.org>
To: Andy Shevchenko <andriy.shevchenko@intel.com>
Cc: Lothar Rubusch <l.rubusch@gmail.com>,
lars@metafoo.de, Michael.Hennerich@analog.com,
dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org,
corbet@lwn.net, linux-iio@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org,
eraretuya@gmail.com
Subject: Re: [PATCH v11 4/8] iio: accel: adxl345: add inactivity feature
Date: Sun, 6 Jul 2025 13:08:08 +0100 [thread overview]
Message-ID: <20250706130808.2b6a1161@jic23-huawei> (raw)
In-Reply-To: <aGalkb42uRQ12Wr0@smile.fi.intel.com>
On Thu, 3 Jul 2025 18:45:21 +0300
Andy Shevchenko <andriy.shevchenko@intel.com> wrote:
> On Thu, Jul 03, 2025 at 04:59:50PM +0200, Lothar Rubusch wrote:
> > On Thu, Jul 3, 2025 at 4:26 PM Andy Shevchenko
> > <andriy.shevchenko@intel.com> wrote:
> > > On Wed, Jul 02, 2025 at 11:03:11PM +0000, Lothar Rubusch wrote:
>
> ...
>
> > > > #define ADXL345_REG_TAP_SUPPRESS_MSK BIT(3)
> > > > #define ADXL345_REG_TAP_SUPPRESS BIT(3)
> > > > #define ADXL345_REG_ACT_AXIS_MSK GENMASK(6, 4)
> > > > +#define ADXL345_REG_INACT_AXIS_MSK GENMASK(2, 0)
> > > > +#define ADXL345_POWER_CTL_INACT_MSK (ADXL345_POWER_CTL_AUTO_SLEEP | ADXL345_POWER_CTL_LINK)
> > > >
> > > > #define ADXL345_TAP_Z_EN BIT(0)
> > > > #define ADXL345_TAP_Y_EN BIT(1)
> > > > #define ADXL345_TAP_X_EN BIT(2)
> > > >
> > > > +#define ADXL345_INACT_Z_EN BIT(0)
> > > > +#define ADXL345_INACT_Y_EN BIT(1)
> > > > +#define ADXL345_INACT_X_EN BIT(2)
> > > > +#define ADXL345_INACT_XYZ_EN (ADXL345_INACT_Z_EN | ADXL345_INACT_Y_EN | ADXL345_INACT_X_EN)
> > > > +
> > > > #define ADXL345_ACT_Z_EN BIT(4)
> > > > #define ADXL345_ACT_Y_EN BIT(5)
> > > > #define ADXL345_ACT_X_EN BIT(6)
> > >
> > > Now it's even more mess. I am lost in understanding which bits/masks are from
> > > the same offset and which are not.
> > >
> >
> > I'm sorry for that. I mean, while the above is supposed to make it
> > clear where the "values" are coming from, I also could setup something
> > like the following which is shorter.
> > +#define ADXL345_INACT_XYZ_EN GENMASK(2,0)
> > +#define ADXL345_ACT_XYZ_EN GENMASK(6,4)
Definitely not for those. They aren't a mask, but rather 3 only somewhat
related bits.
> >
> > As I understand you, you'd rather prefer to see the latter one in the kernel?
>
> My personal preference can be found, for example, in
> drivers/pinctrl/intel/pinctrl-intel.c. But I'm not insisting to use
> _my_ schema. Just find a way how to group them semantically.
>
next prev parent reply other threads:[~2025-07-06 12:08 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-02 23:03 [PATCH v11 0/8] iio: accel: adxl345: add interrupt based sensor events Lothar Rubusch
2025-07-02 23:03 ` [PATCH v11 1/8] iio: accel: adxl345: simplify interrupt mapping Lothar Rubusch
2025-07-06 16:10 ` Jonathan Cameron
2025-07-02 23:03 ` [PATCH v11 2/8] iio: accel: adxl345: simplify reading the FIFO Lothar Rubusch
2025-07-06 16:11 ` Jonathan Cameron
2025-07-02 23:03 ` [PATCH v11 3/8] iio: accel: adxl345: add activity event feature Lothar Rubusch
2025-07-03 14:24 ` Andy Shevchenko
2025-07-06 16:09 ` Jonathan Cameron
2025-07-20 18:36 ` Lothar Rubusch
2025-07-24 13:43 ` Jonathan Cameron
2025-07-02 23:03 ` [PATCH v11 4/8] iio: accel: adxl345: add inactivity feature Lothar Rubusch
2025-07-03 14:26 ` Andy Shevchenko
2025-07-03 14:59 ` Lothar Rubusch
2025-07-03 15:45 ` Andy Shevchenko
2025-07-06 12:08 ` Jonathan Cameron [this message]
2025-07-02 23:03 ` [PATCH v11 5/8] iio: accel: adxl345: add coupling detection for activity/inactivity Lothar Rubusch
2025-07-02 23:03 ` [PATCH v11 6/8] iio: accel: adxl345: extend inactivity time for less than 1s Lothar Rubusch
2025-07-02 23:03 ` [PATCH v11 7/8] docs: iio: add documentation for adxl345 driver Lothar Rubusch
2025-07-02 23:03 ` [PATCH v11 8/8] docs: iio: describe inactivity and free-fall detection on the ADXL345 Lothar Rubusch
2025-07-06 16:16 ` Jonathan Cameron
2025-07-20 18:49 ` Lothar Rubusch
2025-07-24 13:47 ` Jonathan Cameron
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