Re: [PATCH] iio/adc/pac1934: fix channel disable configuration

[Jonathan Cameron <jic23@kernel.org>]

On Mon, 11 Aug 2025 13:09:04 +0000
Aleksandar Gerasimovski <aleksandar.gerasimovski@belden.com> wrote:

> There are two problems with the chip configuration in this driver:
> - First, is that writing 12 bytes (ARRAY_SIZE(regs)) would anyhow
>   lead to a config overflow due to HW auto increment implementation
>   in the chip.
> - Second, the i2c_smbus_write_block_data write ends up in writing
>   unexpected value to the channel_dis register, this is because
>   the smbus size that is 0x03 in this case gets written to the
>   register. The PAC1931/2/3/4 data sheet does not really specify
>   that block write is indeed supported.
> 
> This problem is probably not visible on PAC1934 version where all
> channels are used as the chip is properly configured by luck,
> but in our case whenusing PAC1931 this leads to nonfunctional device.
> 
> Signed-off-by: Rene Straub <rene.straub@belden.com>
> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@belden.com>

Hi, Thanks for the patch.

Needs a fixes tag so we know how far to back port it.
You can just reply with one to this thread rather than sending a new
version.

Thanks,

Jonathan

> ---
>  drivers/iio/adc/pac1934.c | 20 ++++++++++++++++++--
>  1 file changed, 18 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/iio/adc/pac1934.c b/drivers/iio/adc/pac1934.c
> index 09fe88eb3fb0..2e442e46f679 100644
> --- a/drivers/iio/adc/pac1934.c
> +++ b/drivers/iio/adc/pac1934.c
> @@ -88,6 +88,7 @@
>  #define PAC1934_VPOWER_3_ADDR			0x19
>  #define PAC1934_VPOWER_4_ADDR			0x1A
>  #define PAC1934_REFRESH_V_REG_ADDR		0x1F
> +#define PAC1934_SLOW_REG_ADDR			0x20
>  #define PAC1934_CTRL_STAT_REGS_ADDR		0x1C
>  #define PAC1934_PID_REG_ADDR			0xFD
>  #define PAC1934_MID_REG_ADDR			0xFE
> @@ -1265,8 +1266,23 @@ static int pac1934_chip_configure(struct pac1934_chip_info *info)
>  	/* no SLOW triggered REFRESH, clear POR */
>  	regs[PAC1934_SLOW_REG_OFF] = 0;
>  
> -	ret =  i2c_smbus_write_block_data(client, PAC1934_CTRL_STAT_REGS_ADDR,
> -					  ARRAY_SIZE(regs), (u8 *)regs);
> +	/*
> +	 * Write the three bytes sequentially, as the device does not support
> +	 * block write.
> +	 */
> +	ret = i2c_smbus_write_byte_data(client, PAC1934_CTRL_STAT_REGS_ADDR,
> +					regs[PAC1934_CHANNEL_DIS_REG_OFF]);
> +	if (ret)
> +		return ret;
> +
> +	ret = i2c_smbus_write_byte_data(client,
> +					PAC1934_CTRL_STAT_REGS_ADDR + PAC1934_NEG_PWR_REG_OFF,
> +					regs[PAC1934_NEG_PWR_REG_OFF]);
> +	if (ret)
> +		return ret;
> +
> +	ret = i2c_smbus_write_byte_data(client, PAC1934_SLOW_REG_ADDR,
> +					regs[PAC1934_SLOW_REG_OFF]);
>  	if (ret)
>  		return ret;
>