From: Akshay Jindal <akshayaj.lkd@gmail.com>
To: dan@dlrobertson.com, jic23@kernel.org, dlechner@baylibre.com,
nuno.sa@analog.com, andy@kernel.org
Cc: Akshay Jindal <akshayaj.lkd@gmail.com>,
shuah@kernel.org, linux-iio@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v5 2/6] iio: accel: bma400: Use macros for generic event configuration values
Date: Sun, 12 Oct 2025 23:36:09 +0530 [thread overview]
Message-ID: <20251012180619.195244-3-akshayaj.lkd@gmail.com> (raw)
In-Reply-To: <20251012180619.195244-1-akshayaj.lkd@gmail.com>
Add macros and enums for configuration values used in generic event
handling for activity and inactivity detection. Replace hard-coded
values in activity_event_en() with the new definitions to make the
configuration explicit.
No functional changes are intended.
Signed-off-by: Akshay Jindal <akshayaj.lkd@gmail.com>
---
Changes since v3:
- Assigned explicit values to reg field enums introduced.
drivers/iio/accel/bma400.h | 30 ++++++++++++++++++++++++++++++
drivers/iio/accel/bma400_core.c | 14 +++++++++++---
2 files changed, 41 insertions(+), 3 deletions(-)
diff --git a/drivers/iio/accel/bma400.h b/drivers/iio/accel/bma400.h
index fcafd1fba57a..12e7bf5fe647 100644
--- a/drivers/iio/accel/bma400.h
+++ b/drivers/iio/accel/bma400.h
@@ -113,8 +113,38 @@
#define BMA400_GEN1INT_CONFIG0_REG 0x3f
#define BMA400_GEN2INT_CONFIG0_REG 0x4A
#define BMA400_GENINT_CONFIG0_HYST_MASK GENMASK(1, 0)
+#define BMA400_GENINT_CONFIG0_REF_UPD_MODE_MASK GENMASK(3, 2)
+#define BMA400_GENINT_CONFIG0_DATA_SRC_MASK BIT(4)
+#define BMA400_GENINT_CONFIG0_X_EN_MASK BIT(5)
+#define BMA400_GENINT_CONFIG0_Y_EN_MASK BIT(6)
+#define BMA400_GENINT_CONFIG0_Z_EN_MASK BIT(7)
+
+enum bma400_accel_data_src {
+ ACCEL_FILT1 = 0x0,
+ ACCEL_FILT2 = 0x1,
+};
+
+enum bma400_ref_updt_mode {
+ BMA400_REF_MANUAL_UPDT_MODE = 0x0,
+ BMA400_REF_ONETIME_UPDT_MODE = 0x1,
+ BMA400_REF_EVERYTIME_UPDT_MODE = 0x2,
+ BMA400_REF_EVERYTIME_LP_UPDT_MODE = 0x3,
+};
#define BMA400_GEN_CONFIG1_OFF 0x01
+#define BMA400_GENINT_CONFIG1_AXES_COMB_MASK BIT(0)
+#define BMA400_GENINT_CONFIG1_DETCT_CRIT_MASK BIT(1)
+
+enum bma400_genintr_acceleval_axescomb {
+ BMA400_EVAL_X_OR_Y_OR_Z = 0x0,
+ BMA400_EVAL_X_AND_Y_AND_Z = 0x1,
+};
+
+enum bma400_detect_criterion {
+ BMA400_DETECT_INACTIVITY = 0x0,
+ BMA400_DETECT_ACTIVITY = 0x1,
+};
+
#define BMA400_GEN_CONFIG2_OFF 0x02
#define BMA400_GEN_CONFIG3_OFF 0x03
#define BMA400_GEN_CONFIG31_OFF 0x04
diff --git a/drivers/iio/accel/bma400_core.c b/drivers/iio/accel/bma400_core.c
index 2324c4ef645c..46855073ce3a 100644
--- a/drivers/iio/accel/bma400_core.c
+++ b/drivers/iio/accel/bma400_core.c
@@ -1166,14 +1166,16 @@ static int bma400_activity_event_en(struct bma400_data *data,
case IIO_EV_DIR_RISING:
reg = BMA400_GEN1INT_CONFIG0_REG;
msk = BMA400_INT_CONFIG0_GEN1_MASK;
- value = 2;
+ value = FIELD_PREP(BMA400_GENINT_CONFIG1_AXES_COMB_MASK, BMA400_EVAL_X_OR_Y_OR_Z) |
+ FIELD_PREP(BMA400_GENINT_CONFIG1_DETCT_CRIT_MASK, BMA400_DETECT_ACTIVITY);
set_mask_bits(&field_value, BMA400_INT_CONFIG0_GEN1_MASK,
FIELD_PREP(BMA400_INT_CONFIG0_GEN1_MASK, state));
break;
case IIO_EV_DIR_FALLING:
reg = BMA400_GEN2INT_CONFIG0_REG;
msk = BMA400_INT_CONFIG0_GEN2_MASK;
- value = 0;
+ value = FIELD_PREP(BMA400_GENINT_CONFIG1_AXES_COMB_MASK, BMA400_EVAL_X_OR_Y_OR_Z) |
+ FIELD_PREP(BMA400_GENINT_CONFIG1_DETCT_CRIT_MASK, BMA400_DETECT_INACTIVITY);
set_mask_bits(&field_value, BMA400_INT_CONFIG0_GEN2_MASK,
FIELD_PREP(BMA400_INT_CONFIG0_GEN2_MASK, state));
break;
@@ -1182,7 +1184,13 @@ static int bma400_activity_event_en(struct bma400_data *data,
}
/* Enabling all axis for interrupt evaluation */
- ret = regmap_write(data->regmap, reg, 0xF8);
+ ret = regmap_write(data->regmap, reg,
+ BMA400_GENINT_CONFIG0_X_EN_MASK |
+ BMA400_GENINT_CONFIG0_Y_EN_MASK |
+ BMA400_GENINT_CONFIG0_Z_EN_MASK|
+ FIELD_PREP(BMA400_GENINT_CONFIG0_DATA_SRC_MASK, ACCEL_FILT2)|
+ FIELD_PREP(BMA400_GENINT_CONFIG0_REF_UPD_MODE_MASK,
+ BMA400_REF_EVERYTIME_UPDT_MODE));
if (ret)
return ret;
--
2.43.0
next prev parent reply other threads:[~2025-10-12 18:07 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-12 18:06 [PATCH v5 0/6] iio: accel: bma400: Refactor GENINTR config and register macros Akshay Jindal
2025-10-12 18:06 ` [PATCH v5 1/6] iio: accel: bma400: Reorganize and rename register and field macros Akshay Jindal
2025-10-12 18:06 ` Akshay Jindal [this message]
2025-10-12 18:06 ` [PATCH v5 3/6] iio: accel: bma400: Use index-based register addressing and lookup Akshay Jindal
2025-10-12 18:06 ` [PATCH v5 4/6] iio: accel: bma400: Replace bit shifts with FIELD_PREP() and FIELD_GET() Akshay Jindal
2025-10-12 18:06 ` [PATCH v5 5/6] iio: accel: bma400: Rename activity_event_en() to generic_event_en() Akshay Jindal
2025-10-12 18:06 ` [PATCH v5 6/6] iio: accel: bma400: Add detail to comments in GEN INTR configuration Akshay Jindal
2025-10-18 15:06 ` [PATCH v5 0/6] iio: accel: bma400: Refactor GENINTR config and register macros Jonathan Cameron
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20251012180619.195244-3-akshayaj.lkd@gmail.com \
--to=akshayaj.lkd@gmail.com \
--cc=andy@kernel.org \
--cc=dan@dlrobertson.com \
--cc=dlechner@baylibre.com \
--cc=jic23@kernel.org \
--cc=linux-iio@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=nuno.sa@analog.com \
--cc=shuah@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).