Re: [PATCH v9 0/2] NXP SAR ADC IIO driver for s32g2/3 platforms

[Jonathan Cameron <jic23@kernel.org>]

On Mon,  8 Dec 2025 03:08:17 +0100
Daniel Lezcano <daniel.lezcano@linaro.org> wrote:

> The S32G2 and S32G3 platforms have a couple of successive
> approximation register (SAR) ADCs with eight channels and 12-bit
> resolution. These changes provide the driver support for these ADCs
> and the bindings describing them.
> 
> The driver is derived from the BSP driver version. It has been partly
> rewritten to conform to upstream criteria.
> 
> https://github.com/nxp-auto-linux/linux/blob/release/bsp44.0-6.6.85-rt/drivers/iio/adc/s32cc_adc.c
> 
> After the V1 posting there were some discussions around the DMA code
> to be converted to use the IIO DMA API [1]. Unfortunately this one is
> not yet fully implemented and merged in the framework to support the
> cyclic DMA. The current DMA code in the driver has been used in
> production since several years and even if I agree it can be improved
> with a dedicated IIO DMA API in the future, IMO, it sounds reasonable
> to keep it as is until the IIO DMA API supporting the cyclic DMA is
> merged. I'll be glad to convert the driver code if such an API exists
> and allows to remove code inside the driver.
> 
> [1] https://lore.kernel.org/all/c30bb4b6328d15a9c213c0fa64b909035dc7bf40.camel@gmail.com/
> [2] https://lore.kernel.org/all/aRyBKH4KOQ1L8lA4@black.igk.intel.com/
Series applied to the testing branch of iio.git. It will go out as togreg once
I have rebased on rc1.

Thanks,

Jonathan