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From: Jonathan Cameron <jic23@kernel.org>
To: David Lechner <dlechner@baylibre.com>
Cc: "Antoniu Miclaus" <antoniu.miclaus@analog.com>,
	"Lars-Peter Clausen" <lars@metafoo.de>,
	"Michael Hennerich" <Michael.Hennerich@analog.com>,
	"Ramona Gradinariu" <ramona.gradinariu@analog.com>,
	"Nuno Sá" <nuno.sa@analog.com>,
	"Andy Shevchenko" <andy@kernel.org>,
	linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] iio: accel: adxl380: fix FIFO watermark bit 8 always written as 0
Date: Sun, 1 Mar 2026 12:02:36 +0000	[thread overview]
Message-ID: <20260301120236.385519a2@jic23-huawei> (raw)
In-Reply-To: <84fae6b8-d188-4e5c-af06-b342f3d27514@baylibre.com>

On Sat, 28 Feb 2026 10:50:00 -0600
David Lechner <dlechner@baylibre.com> wrote:

> On 2/27/26 6:43 AM, Antoniu Miclaus wrote:
> > FIELD_PREP(BIT(0), fifo_samples & BIT(8)) produces either 0 or 256,
> > and since FIELD_PREP masks to bit 0, 256 & 1 evaluates to 0. Use !!
> > to convert the result to a proper 0-or-1 value.
> > 
> > Fixes: df36de13677a ("iio: accel: add ADXL380 driver")
> > Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
> > ---
> >  drivers/iio/accel/adxl380.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/iio/accel/adxl380.c b/drivers/iio/accel/adxl380.c
> > index 8fab2fdbe147..a51d1d61c412 100644
> > --- a/drivers/iio/accel/adxl380.c
> > +++ b/drivers/iio/accel/adxl380.c
> > @@ -877,7 +877,7 @@ static int adxl380_set_fifo_samples(struct adxl380_state *st)  
> 
> Some relevant context...
> 
> 	u16 fifo_samples = st->watermark * st->fifo_set_size;
> 
> >  	ret = regmap_update_bits(st->regmap, ADXL380_FIFO_CONFIG_0_REG,
> >  				 ADXL380_FIFO_SAMPLES_8_MSK,
> >  				 FIELD_PREP(ADXL380_FIFO_SAMPLES_8_MSK,
> > -					    (fifo_samples & BIT(8))));
> > +					    !!(fifo_samples & BIT(8))));  
> 
> Technically, this works, but in terms of understanding the code I think
> fifo_samples >= BIT(8) would make more sense.
> 
> fifo_samples is a count, not bit flags.
It's an odd bit of code, but then it's unusual hardware too.
To me it is about bit 8 not the value being big enough to have a bit 8 because
if there were yet another register that was for BIT(9) then
 >= BIT(8) would give the wrong value if BIT(9) was set and BIT(8) was not.

We could express this what is going on in a bit more explicit detail maybe?

	FIELD_PREP(ADXL380_FIFO_SAMPLES_8_MSK,
		   FIELD_GET(BIT(8), fifo_samples));

So there we are extracting the 8th bit and writing to the location for the 8th
bit.
> 
> 
> >  	if (ret)
> >  		return ret;
> >    
> 


  reply	other threads:[~2026-03-01 12:02 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-27 12:43 [PATCH] iio: accel: adxl380: fix FIFO watermark bit 8 always written as 0 Antoniu Miclaus
2026-02-28 12:03 ` Jonathan Cameron
2026-02-28 16:50 ` David Lechner
2026-03-01 12:02   ` Jonathan Cameron [this message]
2026-03-02  7:56   ` Andy Shevchenko
2026-03-02 14:54     ` David Lechner
2026-03-02 15:03       ` Andy Shevchenko

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