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charset=US-ASCII Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYwNzE3MDE5MCBTYWx0ZWRfX2ECKx7pZRwIW 2ExkCHXsYJOVlv1eTOkhQIJbCmwwJ5JPsI1OcDcLVZB8GvPCw877f/beoHGERROKFfu8q3bhOhK /xgZYsaX5ltFX4akW0wyeIWOGNbD6VA= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzE3MDE5MCBTYWx0ZWRfX5L+7ZBVmRszv hTh8PyFUpcoUTC9gpb7rZ0I5rqwt019zYUXC0sUKx3eEyqeWMqFezu1IPDT9tGVZj4+GW6W8bkc S0apXWJefhO+YY88B0xFVxc0qN7/ZKPzfL5gfc/AwIp3NqHT+PkBAJ6LzQO3IW6QkmIPaxaLr+e tSDC7Jv0R374ItZVgiwjbroUlfC+JGg/tGpKruahEgaCOTtq7XtJkJBG8HHxoXiysno7CEAh4qh 1l9+0UIVs7GltzCrJJ8NOvraKQfI81yUOeA+MPxQJioQVEkcHSF4MilF48FN4X0oD8jKr4PZXvW t3x9YwlinL1AYWNzfjDVm5QbSEh86mQZgiEl8XMR5wLdlX7y8s9d/lLvP+EUEYTqzVRvyjxARFG BMu01s9iRW0rcpTcjHsl16txJPNmb9U9463REOIRt324QTRZajm4WekQ6LjKHkJOqvCxzuv+M/3 5gJpOhVm13Pu3N7wrIQ== X-Proofpoint-GUID: dZcTIwSa_Sh_kxF4osS7XKWWP2hDaMAB X-Proofpoint-ORIG-GUID: dZcTIwSa_Sh_kxF4osS7XKWWP2hDaMAB X-Authority-Analysis: v=2.4 cv=e/M2j6p/ c=1 sm=1 tr=0 ts=6a5a76ac cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=qC1CW/w66vtJz1P9yTJxNA==:17 a=kj9zAlcOel0A:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=QyXUC8HyAAAA:8 a=p1EoV59dKfn0TkCHIRwA:9 a=CjuIK1q_8ugA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-17_05,2026-07-17_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 impostorscore=0 suspectscore=0 phishscore=0 priorityscore=1501 spamscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607170190 On Fri, 17 Jul 2026 20:58:41 +0300 Andy Shevchenko wrote: > On Fri, Jul 17, 2026 at 03:38:49PM +0300, Stefan Popa wrote: > > The MAX40080 is a bidirectional current-sense amplifier with an > > integrated 12-bit ADC and an I2C/SMBus interface. It measures the > > voltage across an external shunt resistor and the input bus voltage, > > storing the results in an internal FIFO. > > > > No existing IIO driver covers this device or a register-compatible part. > > The closest relatives target different silicon with incompatible register > > maps and feature sets: max9611 is a unidirectional high-side sensor with a > > die-temperature channel and MUX-selected gain and no FIFO/PEC, while > > max34408 is an 8-bit multi-channel current monitor. The MAX40080 has a > > device-specific register map with bidirectional 13-bit current, a 64-entry > > FIFO, PEC, a single-measurement mode triggered by an SMBus Quick Command, > > and two selectable input ranges, so it warrants its own driver. > > > > Add a direct-mode IIO driver exposing the current and voltage channels > > with raw and scale attributes, a configurable oversampling (digital > > averaging) ratio, and PEC-protected register access. The two selectable > > current-sense ranges are exposed through scale/scale_available; the > > current scale is derived from the shunt-resistor-micro-ohms device-tree > > property. > > ... > > > +struct max40080_state { > > + struct i2c_client *client; > > + /* Serializes read-modify-write access to the CFG register. */ > > + struct mutex lock; > > + u32 shunt_resistor_uOhm; > > + /* > > + * Cached configuration, also used to restore the device on resume after > > + * a suspend that may have cut its power: the selected RANGE index and > > + * the oversampling ratio. > > + */ > > + unsigned int range; > > + int oversampling_ratio; > > + /* > > + * Precomputed current scale (mA per code) for each RANGE setting, as > > + * {integer, nano} pairs for IIO_VAL_INT_PLUS_NANO. The range is > > + * selected by writing the corresponding scale. > > + */ > > + int current_scale[ARRAY_SIZE(max40080_csa_gain)][2]; > > > + /* DMA-safe buffer for i2c_smbus_read_i2c_block_data(). */ > > + u8 buf[4] ____cacheline_aligned; > > Why don't you use the specific IIO macro for this? > Do you have internal reviews for this patch series? This is also wrong. Despite the naming ___cacheline_aligned is not sufficient on some architectures. It's a performance hint, not a correctness statement so can often be the size for say the l2 cache but the l3 cache line is higher and the lack of coherency is beyond that point. ARCH_DMA_MINALIGN is probably sufficient. The IIO_DMA_MINALIGN defintion predates that being available on all architectures + ensures the buffers are always aligned to at least 8 bytes which makes a few other things simpler for very little cost. Jonathan > > > +}; >