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Mon, 31 Aug 2026 04:31:47 -0400 From: Antoniu Miclaus To: Marcelo Schmitt , Antoniu Miclaus , =?UTF-8?q?Nuno=20S=C3=A1?= , Michael Hennerich , Jonathan Cameron , David Lechner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Subject: [PATCH v4 4/4] iio: accel: adxl367: add support for INT2 interrupt pin Date: Mon, 31 Aug 2026 11:31:22 +0300 Message-ID: <20260831083122.3486-5-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260831083122.3486-1-antoniu.miclaus@analog.com> References: <20260831083122.3486-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDA3MiBTYWx0ZWRfXw5k5n6yzcEV8 JRaOuNn1f7dfwcZhHuacIjzfI5kpVhp3BONjOnA1HnpBvKEsf4oO0fCjORfIL0w7VfSNnnPjfPR aM3JFvJmTIkO42mvuKyoZGYzsy4qXpRZ+zo3n6il2cWHB9/A7qcr X-Authority-Analysis: v=2.4 cv=feSdDUQF c=1 sm=1 tr=0 ts=6a953bfb cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=0sLvza09kfJOxVLZPwjg:22 a=N--XFCr6TIEc_64PeIT2:22 a=gAnH3GRIAAAA:8 a=OEf6KZoglCvnwJEIrVQA:9 X-Proofpoint-ORIG-GUID: VSLAjuX5qYbb9Dm2XmcrDwhG2CWA7lEh X-Proofpoint-GUID: VSLAjuX5qYbb9Dm2XmcrDwhG2CWA7lEh X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDA3MiBTYWx0ZWRfX1rPVYTtroKdL TFRA1/pBspI1BzclxH7BmGwqzdZEsGxapyrc1N627Z0L9yIW5m/Jf1tZrXh5MECwBJi/LmzltGC TqicECn78EblqXPZ9RhnP4WWkkirirHMxdWt09Bc4Z7rmzETBfX/jtYUxHPXLcJf/79q6Y/9AFY YRkxoa76u0uGGoIu0QNn1mjlQwTwfwWuvKJjm/1lhQURZEF/u1hO+0g6sff2Lc4HQogi6BU73RL zJnxHl7WYktogGqOOXpcz8mk4XGtGObJuLgJyYx42BlvoRBF5y/iI3214ErngLrA7cCl+wCq2a6 cIwe8DxaZdO9X8H6HQK+RiEl+GXHw2HaDP86UPWgNgcO4WJAWx66yQpsTcc3ibYVKz8iDDC7Uxc OHYgM1e7npCjbnHs6fwpzfLzaDucHzm5XAISiPdSf1jDhWMbWD7p8yEbXOrWwKquq+9sJiiUPpy 4I4Vz1i3uqstU5qORbQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_03,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 phishscore=0 suspectscore=0 spamscore=0 adultscore=0 bulkscore=0 clxscore=1015 malwarescore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310072 The ADXL367 provides two independent interrupt output pins, INT1 and INT2, each with its own event mapping register (INTMAP1_LOWER at 0x2A and INTMAP2_LOWER at 0x2B) sharing an identical bit layout. Until now the driver hardcoded INT1 for all interrupt mappings, so a board that routes only INT2 to the host could never receive activity, inactivity or FIFO watermark interrupts. Determine the connected pin from the interrupt-names device tree property using fwnode_irq_get_byname(), and route the interrupt mappings to the matching register. Use the interrupt number returned by the lookup for devm_request_threaded_irq() so the requested line always matches the routed INTMAP register, regardless of the order in which the interrupts are listed. When no interrupt-names are present, default to INT1 and the bus-provided interrupt to preserve the existing behaviour. Signed-off-by: Antoniu Miclaus --- Changes in v4: - Propagate errors from fwnode_irq_get_byname() instead of silently falling back: only -EINVAL (no interrupt-names) and -ENODATA (requested name not listed) select the INT1 default, so -EPROBE_DEFER and other errors are returned to the caller. drivers/iio/accel/adxl367.c | 45 ++++++++++++++++++++++++++++++++++--- 1 file changed, 42 insertions(+), 3 deletions(-) diff --git a/drivers/iio/accel/adxl367.c b/drivers/iio/accel/adxl367.c index 54c4d1226790..9a2312da6238 100644 --- a/drivers/iio/accel/adxl367.c +++ b/drivers/iio/accel/adxl367.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -81,6 +82,7 @@ #define ADXL367_SAMPLES_L_MASK GENMASK(7, 0) #define ADXL367_REG_INT1_MAP 0x2A +#define ADXL367_REG_INT2_MAP 0x2B #define ADXL367_INT_INACT_MASK BIT(5) #define ADXL367_INT_ACT_MASK BIT(4) #define ADXL367_INT_FIFO_WATERMARK_MASK BIT(2) @@ -168,6 +170,8 @@ struct adxl367_state { enum adxl367_odr odr; enum adxl367_range range; + u8 int_map_reg; + unsigned int act_threshold; unsigned int act_time_ms; unsigned int inact_threshold; @@ -366,7 +370,7 @@ static int adxl367_set_act_interrupt_en(struct adxl367_state *st, { unsigned int mask = adxl367_act_int_mask_tbl[act]; - return regmap_assign_bits(st->regmap, ADXL367_REG_INT1_MAP, mask, en); + return regmap_assign_bits(st->regmap, st->int_map_reg, mask, en); } static int adxl367_get_act_interrupt_en(struct adxl367_state *st, @@ -377,7 +381,7 @@ static int adxl367_get_act_interrupt_en(struct adxl367_state *st, unsigned int val; int ret; - ret = regmap_read(st->regmap, ADXL367_REG_INT1_MAP, &val); + ret = regmap_read(st->regmap, st->int_map_reg, &val); if (ret) return ret; @@ -400,7 +404,7 @@ static int adxl367_set_act_en(struct adxl367_state *st, static int adxl367_set_fifo_watermark_interrupt_en(struct adxl367_state *st, bool en) { - return regmap_assign_bits(st->regmap, ADXL367_REG_INT1_MAP, + return regmap_assign_bits(st->regmap, st->int_map_reg, ADXL367_INT_FIFO_WATERMARK_MASK, en); } @@ -1423,6 +1427,36 @@ static int adxl367_setup(struct adxl367_state *st) return adxl367_set_measure_en(st, true); } +static int adxl367_set_int_map_reg(struct adxl367_state *st, int irq) +{ + int ret; + + /* + * Route the mappings to whichever of INT1/INT2 is named in the + * interrupt-names property. -EINVAL (property absent) and -ENODATA + * (name not listed) are not errors; anything else is. + */ + ret = fwnode_irq_get_byname(dev_fwnode(st->dev), "INT1"); + if (ret > 0) { + st->int_map_reg = ADXL367_REG_INT1_MAP; + return ret; + } + if (ret != -ENODATA && ret != -EINVAL) + return ret; + + ret = fwnode_irq_get_byname(dev_fwnode(st->dev), "INT2"); + if (ret > 0) { + st->int_map_reg = ADXL367_REG_INT2_MAP; + return ret; + } + if (ret != -ENODATA && ret != -EINVAL) + return ret; + + /* No INT1/INT2 named: default to INT1 and the bus interrupt. */ + st->int_map_reg = ADXL367_REG_INT1_MAP; + return irq; +} + int adxl367_probe(struct device *dev, const struct adxl367_ops *ops, void *context, struct regmap *regmap, int irq) { @@ -1479,6 +1513,11 @@ int adxl367_probe(struct device *dev, const struct adxl367_ops *ops, if (ret) return ret; + ret = adxl367_set_int_map_reg(st, irq); + if (ret < 0) + return dev_err_probe(st->dev, ret, "Failed to get interrupt\n"); + irq = ret; + ret = devm_request_threaded_irq(st->dev, irq, NULL, adxl367_irq_handler, IRQF_ONESHOT, indio_dev->name, indio_dev); -- 2.43.0