[PATCH v3 2/3] counter: rz-mtu3-cnt: check pm_runtime_resume_and_get() return values

["Li Youhong" <dayou5941@163.com>]

From: Li Youhong <liyouhong@kylinos.cn>

The driver ignored runtime PM get failures and continued with register
accesses after a failed resume. Switch all call sites to
pm_runtime_resume_and_get() and propagate errors to the caller. That
API already drops the usage count on failure, so the explicit
pm_runtime_put_noidle() pairing used with pm_runtime_get_sync() is
unnecessary.

Fixes: 0be8907359df ("counter: Add Renesas RZ/G2L MTU3a counter driver")
Suggested-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Li Youhong <liyouhong@kylinos.cn>
---
--- a/drivers/counter/rz-mtu3-cnt.c
+++ b/drivers/counter/rz-mtu3-cnt.c
@@ -102,22 +102,25 @@
 	return &priv->ch[ch_id];
 }
 
-static bool rz_mtu3_is_counter_invalid(struct counter_device *counter, int id)
+static int rz_mtu3_validate_counter(struct counter_device *counter, int id)
 {
 	struct rz_mtu3_cnt *const priv = counter_priv(counter);
 	unsigned long tmdr;
+	int ret;
 
-	pm_runtime_get_sync(counter->parent);
+	ret = pm_runtime_resume_and_get(counter->parent);
+	if (ret < 0)
+		return ret;
 	tmdr = rz_mtu3_shared_reg_read(priv->ch, RZ_MTU3_TMDR3);
 	pm_runtime_put(counter->parent);
 
 	if (id == RZ_MTU3_32_BIT_CH && test_bit(RZ_MTU3_TMDR3_LWA, &tmdr))
-		return false;
+		return 0;
 
 	if (id != RZ_MTU3_32_BIT_CH && !test_bit(RZ_MTU3_TMDR3_LWA, &tmdr))
-		return false;
+		return 0;
 
-	return true;
+	return -EBUSY;
 }
 
 static int rz_mtu3_lock_if_counter_is_valid(struct counter_device *counter,
@@ -125,6 +128,8 @@
 					    struct rz_mtu3_cnt *const priv,
 					    int id)
 {
+	int ret;
+
 	mutex_lock(&priv->lock);
 
 	if (ch->is_busy && !priv->count_is_enabled[id]) {
@@ -132,9 +137,10 @@
 		return -EINVAL;
 	}
 
-	if (rz_mtu3_is_counter_invalid(counter, id)) {
+	ret = rz_mtu3_validate_counter(counter, id);
+	if (ret) {
 		mutex_unlock(&priv->lock);
-		return -EBUSY;
+		return ret;
 	}
 
 	return 0;
@@ -165,7 +171,11 @@
 	if (ret)
 		return ret;
 
-	pm_runtime_get_sync(counter->parent);
+	ret = pm_runtime_resume_and_get(counter->parent);
+	if (ret < 0) {
+		mutex_unlock(&priv->lock);
+		return ret;
+	}
 	if (count->id == RZ_MTU3_32_BIT_CH)
 		*val = rz_mtu3_32bit_ch_read(ch, RZ_MTU3_TCNTLW);
 	else
@@ -187,7 +197,11 @@
 	if (ret)
 		return ret;
 
-	pm_runtime_get_sync(counter->parent);
+	ret = pm_runtime_resume_and_get(counter->parent);
+	if (ret < 0) {
+		mutex_unlock(&priv->lock);
+		return ret;
+	}
 	if (count->id == RZ_MTU3_32_BIT_CH)
 		rz_mtu3_32bit_ch_write(ch, RZ_MTU3_TCNTLW, val);
 	else
@@ -203,8 +217,11 @@
 					      enum counter_function *function)
 {
 	u8 timer_mode;
+	int ret;
 
-	pm_runtime_get_sync(counter->parent);
+	ret = pm_runtime_resume_and_get(counter->parent);
+	if (ret < 0)
+		return ret;
 	timer_mode = rz_mtu3_8bit_ch_read(ch, RZ_MTU3_TMDR1);
 	pm_runtime_put(counter->parent);
 
@@ -279,7 +296,11 @@
 		return -EINVAL;
 	}
 
-	pm_runtime_get_sync(counter->parent);
+	ret = pm_runtime_resume_and_get(counter->parent);
+	if (ret < 0) {
+		mutex_unlock(&priv->lock);
+		return ret;
+	}
 	rz_mtu3_8bit_ch_write(ch, RZ_MTU3_TMDR1, timer_mode);
 	pm_runtime_put(counter->parent);
 	mutex_unlock(&priv->lock);
@@ -300,7 +321,11 @@
 	if (ret)
 		return ret;
 
-	pm_runtime_get_sync(counter->parent);
+	ret = pm_runtime_resume_and_get(counter->parent);
+	if (ret < 0) {
+		mutex_unlock(&priv->lock);
+		return ret;
+	}
 	tsr = rz_mtu3_8bit_ch_read(ch, RZ_MTU3_TSR);
 	pm_runtime_put(counter->parent);
 
@@ -377,7 +402,11 @@
 		return -EINVAL;
 	}
 
-	pm_runtime_get_sync(counter->parent);
+	ret = pm_runtime_resume_and_get(counter->parent);
+	if (ret < 0) {
+		mutex_unlock(&priv->lock);
+		return ret;
+	}
 	if (count->id == RZ_MTU3_32_BIT_CH)
 		rz_mtu3_32bit_ch_write(ch, RZ_MTU3_TGRALW, ceiling);
 	else
@@ -504,7 +533,9 @@
 		goto exit;
 
 	if (enable) {
-		pm_runtime_get_sync(counter->parent);
+		ret = pm_runtime_resume_and_get(counter->parent);
+		if (ret < 0)
+			goto exit;
 		ret = rz_mtu3_initialize_counter(counter, count->id);
 		if (ret == 0)
 			priv->count_is_enabled[count->id] = true;
@@ -543,7 +574,11 @@
 	if (ret)
 		return ret;
 
-	pm_runtime_get_sync(counter->parent);
+	ret = pm_runtime_resume_and_get(counter->parent);
+	if (ret < 0) {
+		mutex_unlock(&priv->lock);
+		return ret;
+	}
 	tmdr = rz_mtu3_shared_reg_read(priv->ch, RZ_MTU3_TMDR3);
 	pm_runtime_put(counter->parent);
 	*cascade_enable = test_bit(RZ_MTU3_TMDR3_LWA, &tmdr);
@@ -562,7 +597,11 @@
 	if (ret)
 		return ret;
 
-	pm_runtime_get_sync(counter->parent);
+	ret = pm_runtime_resume_and_get(counter->parent);
+	if (ret < 0) {
+		mutex_unlock(&priv->lock);
+		return ret;
+	}
 	rz_mtu3_shared_reg_update_bit(priv->ch, RZ_MTU3_TMDR3,
 				      RZ_MTU3_TMDR3_LWA, cascade_enable);
 	pm_runtime_put(counter->parent);
@@ -582,7 +621,11 @@
 	if (ret)
 		return ret;
 
-	pm_runtime_get_sync(counter->parent);
+	ret = pm_runtime_resume_and_get(counter->parent);
+	if (ret < 0) {
+		mutex_unlock(&priv->lock);
+		return ret;
+	}
 	tmdr = rz_mtu3_shared_reg_read(priv->ch, RZ_MTU3_TMDR3);
 	pm_runtime_put(counter->parent);
 	*ext_input_phase_clock_select = test_bit(RZ_MTU3_TMDR3_PHCKSEL, &tmdr);
@@ -601,7 +644,11 @@
 	if (ret)
 		return ret;
 
-	pm_runtime_get_sync(counter->parent);
+	ret = pm_runtime_resume_and_get(counter->parent);
+	if (ret < 0) {
+		mutex_unlock(&priv->lock);
+		return ret;
+	}
 	rz_mtu3_shared_reg_update_bit(priv->ch, RZ_MTU3_TMDR3,
 				      RZ_MTU3_TMDR3_PHCKSEL,
 				      ext_input_phase_clock_select);