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[88.193.135.236]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5b8c270ea53sm398549e87.12.2026.09.18.05.25.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Sep 2026 05:25:19 -0700 (PDT) From: Rupesh Majhi To: Andy Shevchenko , Bill Wendling , David Lechner , Eddie James , Joel Stanley , Jonathan Cameron , Justin Stitt , Nathan Chancellor , Nick Desaulniers , =?UTF-8?q?Nuno=20S=C3=A1?= Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Rupesh Majhi , stable@vger.kernel.org Subject: [PATCH v7 01/10] iio: pressure: dps310: fix CFG_REG bit definitions Date: Fri, 18 Sep 2026 15:25:08 +0300 Message-ID: <20260918122517.377565-2-zoone.rupert@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260918122517.377565-1-zoone.rupert@gmail.com> References: <20260918122517.377565-1-zoone.rupert@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Driver defines them as BIT(4), BIT(5) and BIT(6). Per datasheet P_SHIFT is bit 2, FIFO_EN is bit 1 and SPI_MODE is bit 0. Only P_SHIFT has a user. dps310_set_pres_precision() sets it at oversampling 16 or above, so with wrong bit the result register is never shifted and stops matching the scale factor compensation divides by. in_pressure_input returns -ERANGE at oversampling 16, 32 and 64. FIFO_EN needed by FIFO support later in this series. Fixes: ba6ec48e76bc ("iio: Add driver for Infineon DPS310") Fixes: d711a3c7dc82 ("iio: dps310: Add pressure sensing capability") Cc: stable@vger.kernel.org Assisted-by: LLM Signed-off-by: Rupesh Majhi --- drivers/iio/pressure/dps310.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/iio/pressure/dps310.c b/drivers/iio/pressure/dps310.c index 45bdb8c7670f..35260b399390 100644 --- a/drivers/iio/pressure/dps310.c +++ b/drivers/iio/pressure/dps310.c @@ -50,9 +50,9 @@ #define DPS310_CFG_REG 0x09 #define DPS310_INT_HL BIT(7) #define DPS310_TMP_SHIFT_EN BIT(3) -#define DPS310_PRS_SHIFT_EN BIT(4) -#define DPS310_FIFO_EN BIT(5) -#define DPS310_SPI_EN BIT(6) +#define DPS310_PRS_SHIFT_EN BIT(2) +#define DPS310_FIFO_EN BIT(1) +#define DPS310_SPI_EN BIT(0) #define DPS310_RESET 0x0c #define DPS310_RESET_MAGIC 0x09 #define DPS310_COEF_BASE 0x10 -- 2.43.0