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Tue, 25 Feb 2025 17:22:30 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 88F5240046; Tue, 25 Feb 2025 17:21:13 +0100 (CET) Received: from Webmail-eu.st.com (eqndag1node6.st.com [10.75.129.135]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 2597C5C0CD7; Tue, 25 Feb 2025 15:57:51 +0100 (CET) Received: from SAFDAG1NODE1.st.com (10.75.90.17) by EQNDAG1NODE6.st.com (10.75.129.135) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 25 Feb 2025 15:57:50 +0100 Received: from [10.48.86.222] (10.48.86.222) by SAFDAG1NODE1.st.com (10.75.90.17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 25 Feb 2025 15:57:50 +0100 Message-ID: <2df7bdd9-5072-4a9a-b142-1e1e3f20130c@foss.st.com> Date: Tue, 25 Feb 2025 15:57:49 +0100 Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/8] clocksource: stm32-lptimer: add stm32mp25 support To: Krzysztof Kozlowski CC: , , , , , , , , , , , , , , , , , , References: <20250224180150.3689638-1-fabrice.gasnier@foss.st.com> <20250224180150.3689638-5-fabrice.gasnier@foss.st.com> <20250225-purring-herring-of-reputation-1aed2f@krzk-bin> Content-Language: en-US From: Fabrice Gasnier In-Reply-To: <20250225-purring-herring-of-reputation-1aed2f@krzk-bin> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SAFDAG1NODE1.st.com (10.75.90.17) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-25_05,2025-02-25_03,2024-11-22_01 On 2/25/25 13:02, Krzysztof Kozlowski wrote: > On Mon, Feb 24, 2025 at 07:01:46PM +0100, Fabrice Gasnier wrote: >> From: Patrick Delaunay >> >> Add the support of the new compatible for STM32MP25 SoC in driver, as >> described in Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml >> and used in arch/arm64/boot/dts/st/stm32mp251.dtsi. >> >> Signed-off-by: Patrick Delaunay >> Signed-off-by: Fabrice Gasnier >> --- >> drivers/clocksource/timer-stm32-lp.c | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/drivers/clocksource/timer-stm32-lp.c b/drivers/clocksource/timer-stm32-lp.c >> index a4c95161cb22..db055348e2cc 100644 >> --- a/drivers/clocksource/timer-stm32-lp.c >> +++ b/drivers/clocksource/timer-stm32-lp.c >> @@ -197,6 +197,7 @@ static int stm32_clkevent_lp_probe(struct platform_device *pdev) >> >> static const struct of_device_id stm32_clkevent_lp_of_match[] = { >> { .compatible = "st,stm32-lptimer-timer", }, >> + { .compatible = "st,stm32mp25-lptimer-timer", }, >> {}, > > Same question. Oops, I just figured out I have missed a change to this driver, to enable interrupts, in order to comply with the LPTimer spec, starting with STM32MP25. E.g. with earlier STM32MP13, STM32MP15 or even STM32H7: * The LPTIM_IER register must only be modified when the LPTIM is disabled (ENABLE bit reset to ‘0’) On STM32MP25: * The LPTIMx_DIER register must only be modified when the LPTIM is enabled (ENABLE bit set to 1) I'll add this as compatible data in next revision. Best regards, Fabrice > > Best regards, > Krzysztof >