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Wed, 15 Oct 2025 03:30:06 -0700 (PDT) Message-ID: <3180475bd51e1e057d6aa7e1b62f564cb57a117e.camel@gmail.com> Subject: Re: [PATCH 4/6] spi: axi-spi-engine: support SPI_MULTI_BUS_MODE_STRIPE From: Nuno =?ISO-8859-1?Q?S=E1?= To: David Lechner , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , Nuno =?ISO-8859-1?Q?S=E1?= , Jonathan Cameron , Andy Shevchenko Cc: Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org Date: Wed, 15 Oct 2025 11:30:39 +0100 In-Reply-To: <20251014-spi-add-multi-bus-support-v1-4-2098c12d6f5f@baylibre.com> References: <20251014-spi-add-multi-bus-support-v1-0-2098c12d6f5f@baylibre.com> <20251014-spi-add-multi-bus-support-v1-4-2098c12d6f5f@baylibre.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.58.0 Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Tue, 2025-10-14 at 17:02 -0500, David Lechner wrote: > Add support for SPI_MULTI_BUS_MODE_STRIPE to the AXI SPI engine driver. >=20 > The v2.0.0 version of the AXI SPI Engine IP core supports multiple > buses. This can be used with SPI_MULTI_BUS_MODE_STRIPE to support > reading from simultaneous sampling ADCs that have a separate SDO line > for each analog channel. This allows reading all channels at the same > time to increase throughput. >=20 > Signed-off-by: David Lechner > --- > =C2=A0drivers/spi/spi-axi-spi-engine.c | 128 ++++++++++++++++++++++++++++= +++++++++- > - > =C2=A01 file changed, 124 insertions(+), 4 deletions(-) >=20 > diff --git a/drivers/spi/spi-axi-spi-engine.c b/drivers/spi/spi-axi-spi- > engine.c > index > e06f412190fd243161a0b3df992f26157531f6a1..707e5108efec41f7eff608a09fcebd9= d28fa > 2d70 100644 > --- a/drivers/spi/spi-axi-spi-engine.c > +++ b/drivers/spi/spi-axi-spi-engine.c > @@ -23,6 +23,9 @@ > =C2=A0#include > =C2=A0#include > =C2=A0 > +#define SPI_ENGINE_REG_DATA_WIDTH 0x0C > +#define=C2=A0=C2=A0 SPI_ENGINE_REG_DATA_WIDTH_NUM_OF_SDIO_MASK GENMASK(2= 4, 16) > +#define=C2=A0=C2=A0 SPI_ENGINE_REG_DATA_WIDTH_MASK GENMASK(15, 0) > =C2=A0#define SPI_ENGINE_REG_OFFLOAD_MEM_ADDR_WIDTH 0x10 > =C2=A0#define SPI_ENGINE_REG_RESET 0x40 > =C2=A0 > @@ -75,6 +78,8 @@ > =C2=A0#define SPI_ENGINE_CMD_REG_CLK_DIV 0x0 > =C2=A0#define SPI_ENGINE_CMD_REG_CONFIG 0x1 > =C2=A0#define SPI_ENGINE_CMD_REG_XFER_BITS 0x2 > +#define SPI_ENGINE_CMD_REG_SDI_MASK 0x3 > +#define SPI_ENGINE_CMD_REG_SDO_MASK 0x4 > =C2=A0 > =C2=A0#define SPI_ENGINE_MISC_SYNC 0x0 > =C2=A0#define SPI_ENGINE_MISC_SLEEP 0x1 > @@ -105,6 +110,10 @@ > =C2=A0#define SPI_ENGINE_OFFLOAD_CMD_FIFO_SIZE 16 > =C2=A0#define SPI_ENGINE_OFFLOAD_SDO_FIFO_SIZE 16 > =C2=A0 > +/* Extending SPI_MULTI_BUS_MODE values for optimizing messages. */ > +#define SPI_ENGINE_MULTI_BUS_MODE_UNKNOWN -1 > +#define SPI_ENGINE_MULTI_BUS_MODE_CONFLICTING -2 > + > =C2=A0struct spi_engine_program { > =C2=A0 unsigned int length; > =C2=A0 uint16_t instructions[] __counted_by(length); > @@ -142,6 +151,9 @@ struct spi_engine_offload { > =C2=A0 unsigned long flags; > =C2=A0 unsigned int offload_num; > =C2=A0 unsigned int spi_mode_config; > + unsigned int multi_bus_mode; > + u8 primary_bus_mask; > + u8 all_bus_mask; > =C2=A0 u8 bits_per_word; > =C2=A0}; > =C2=A0 > @@ -165,6 +177,22 @@ struct spi_engine { > =C2=A0 bool offload_requires_sync; > =C2=A0}; > =C2=A0 > +static u8 spi_engine_primary_bus_flag(struct spi_device *spi) > +{ > + return BIT(spi->data_bus[0]); > +} > + > +static u8 spi_engine_all_bus_flags(struct spi_device *spi) > +{ > + u8 flags =3D 0; > + int i; > + > + for (i =3D 0; i < spi->num_data_bus; i++) > + flags |=3D BIT(spi->data_bus[i]); > + > + return flags; > +} > + > =C2=A0static void spi_engine_program_add_cmd(struct spi_engine_program *p= , > =C2=A0 bool dry, uint16_t cmd) > =C2=A0{ > @@ -193,7 +221,7 @@ static unsigned int spi_engine_get_config(struct > spi_device *spi) > =C2=A0} > =C2=A0 > =C2=A0static void spi_engine_gen_xfer(struct spi_engine_program *p, bool = dry, > - struct spi_transfer *xfer) > + struct spi_transfer *xfer, u32 num_lanes) > =C2=A0{ > =C2=A0 unsigned int len; > =C2=A0 > @@ -204,6 +232,9 @@ static void spi_engine_gen_xfer(struct spi_engine_pro= gram > *p, bool dry, > =C2=A0 else > =C2=A0 len =3D xfer->len / 4; > =C2=A0 > + if (xfer->multi_bus_mode =3D=3D SPI_MULTI_BUS_MODE_STRIPE) > + len /=3D num_lanes; > + > =C2=A0 while (len) { > =C2=A0 unsigned int n =3D min(len, 256U); > =C2=A0 unsigned int flags =3D 0; > @@ -269,6 +300,7 @@ static int spi_engine_precompile_message(struct > spi_message *msg) > =C2=A0{ > =C2=A0 unsigned int clk_div, max_hz =3D msg->spi->controller->max_speed_h= z; > =C2=A0 struct spi_transfer *xfer; > + int multi_bus_mode =3D SPI_ENGINE_MULTI_BUS_MODE_UNKNOWN; > =C2=A0 u8 min_bits_per_word =3D U8_MAX; > =C2=A0 u8 max_bits_per_word =3D 0; > =C2=A0 > @@ -284,6 +316,24 @@ static int spi_engine_precompile_message(struct > spi_message *msg) > =C2=A0 min_bits_per_word =3D min(min_bits_per_word, xfer- > >bits_per_word); > =C2=A0 max_bits_per_word =3D max(max_bits_per_word, xfer- > >bits_per_word); > =C2=A0 } > + > + if (xfer->rx_buf || xfer->offload_flags & > SPI_OFFLOAD_XFER_RX_STREAM || > + =C2=A0=C2=A0=C2=A0 xfer->tx_buf || xfer->offload_flags & > SPI_OFFLOAD_XFER_TX_STREAM) { I'm a bit confused by this condition. It looks like setting priv->multi_bus= _mode (and the other fields) only matters for msg->offload but the above will be = true for regular rx/tx messages, right? Or am i missing something? If so, I wonder why doing this for all transfers if we only care about multi_bus_mode for offload messages. I guess you want to validate xfer->multi_bus_mode? I would then just take the switch() out of the condit= ion (I mean trying to setup a no data xfer with an invalid bus_mode should also= be seen as invalid IMO) and then use the offload conditions (or maybe simply m= sg- >offload?) for the multi_bus_mode handling. To me, it makes the intent more clear. =20 - Nuno S=C3=A1