Re: ZIO wiki analysis of IIO and why it doesn't meet there requirements [was Re: Industrial Input Output analysis]

[Michael Hennerich <michael.hennerich@analog.com>]

On 11/29/2011 12:00 PM, Alessandro Rubini wrote:
>
> Hello Lars-Peter, sorry for the delay.
>> We do use IIO for high speed data conversion.
> May I know how high?
>

Hi Alessandro,

Right now we use IIO to capture single work loads at 250MSPS.
User space requests - let's say 1M samples, the IIO driver captures and 
returns data to user space.
(sounds a bit similar to your use case)

Hardware is a Virtex6 FPGA, microblaze softcore running Linux and the 
converter is a AD9467
on an FMC-LPC card.

The per-sample buffer implementations in IIO are purely optional!
You can build your own buffer implementation by using the 
INDIO_BUFFER_HARDWARE flag.

For now the full rate capture is only used for hardware validation 
purposes.
Later it is assumed that there will be data decimation inside the FPGA 
fabric,
so that only a few MSPS sustained data is DMAed into the processor core 
system.
Right now it's not decided whether double buffering or a larger chain is 
required in order
to solve the producer-consumer and latency problems.

But I'm pretty optimistic that there is nothing in IIO which prevents me 
from getting the
right solution in place.

Ideally there is only one subsytem, and not one targeting low-speed and 
another for high speed.


-- 
Greetings,
Michael

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