From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from saturn.retrosnub.co.uk ([178.18.118.26]:47970 "EHLO saturn.retrosnub.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750878AbbFGQ4d (ORCPT ); Sun, 7 Jun 2015 12:56:33 -0400 Message-ID: <557477BE.5050108@kernel.org> Date: Sun, 07 Jun 2015 17:56:30 +0100 From: Jonathan Cameron MIME-Version: 1.0 To: Stefan Agner , shawn.guo@linaro.org, kernel@pengutronix.de CC: knaack.h@gmx.de, lars@metafoo.de, pmeerw@pmeerw.net, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, B38611@freescale.com, maitysanchayan@gmail.com, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v5 2/2] ARM: dts: add property for maximum ADC clock frequencies References: <1432730872-14325-1-git-send-email-stefan@agner.ch> <1432730872-14325-3-git-send-email-stefan@agner.ch> In-Reply-To: <1432730872-14325-3-git-send-email-stefan@agner.ch> Content-Type: text/plain; charset=windows-1252 Sender: linux-iio-owner@vger.kernel.org List-Id: linux-iio@vger.kernel.org On 27/05/15 13:47, Stefan Agner wrote: > The ADC clock frequency is limited depending on modes used. Add > device tree property which allow to set the mode used and the > maximum frequency ratings for the instance. These allows to > set the ADC clock to a frequency which is within specification > according to the actual mode used. > > Acked-by: Fugang Duan > Signed-off-by: Stefan Agner I'm happy to take this via IIO if people want me to, otherwise give it's connection to the previous patch that I just applied, Acked-by: Jonathan Cameron > --- > arch/arm/boot/dts/vfxxx.dtsi | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi > index a29c7ce..c6609bd 100644 > --- a/arch/arm/boot/dts/vfxxx.dtsi > +++ b/arch/arm/boot/dts/vfxxx.dtsi > @@ -189,6 +189,8 @@ > clocks = <&clks VF610_CLK_ADC0>; > clock-names = "adc"; > status = "disabled"; > + fsl,adck-max-frequency = <30000000>, <40000000>, > + <20000000>; > }; > > wdoga5: wdog@4003e000 { > @@ -387,6 +389,8 @@ > clocks = <&clks VF610_CLK_ADC1>; > clock-names = "adc"; > status = "disabled"; > + fsl,adck-max-frequency = <30000000>, <40000000>, > + <20000000>; > }; > > esdhc1: esdhc@400b2000 { >