Re: [PATCH 1/2] dt-bindings: iio: frequency: Add ADF4382

[Javier Carrasco <javier.carrasco.cruz@gmail.com>]

On 14/11/2024 14:03, Ciprian Hegbeli wrote:
> The ADF4382A is a high performance, ultralow jitter, Frac-N PLL
> with integrated VCO ideally suited for LO generation for 5G applications
> or data converter clock applications. The high performance
> PLL has a figure of merit of -239 dBc/Hz, low 1/f Noise and
> high PFD frequency of 625MHz in integer mode that can achieve
> ultralow in-band noise and integrated jitter. The ADF4382A can
> generate frequencies in a fundamental octave range of 11.5 GHz to
> 21 GHz, thereby eliminating the need for sub-harmonic filters. The
> divide by 2 and 4 output dividers on the part allow frequencies to
> be generated from 5.75GHz to 10.5GHz and 2.875GHz to 5.25GHz
> respectively.
> 
> Signed-off-by: Ciprian Hegbeli <ciprian.hegbeli@analog.com>
> ---

...

> +
> +  adi,cmos-3v3:
> +    description:

A nitpick I overlooked: default.

> +      Sets the SPI logic to 3.3V, by defautl it uses 1,8V.
> +    type: boolean
> +    maxItems: 1
> +