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Sat, 30 Aug 2025 00:46:48 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <47b2cf01555c31126bc2133526317c7829cb59ab.1756511030.git.marcelo.schmitt@analog.com> In-Reply-To: <47b2cf01555c31126bc2133526317c7829cb59ab.1756511030.git.marcelo.schmitt@analog.com> From: Andy Shevchenko Date: Sat, 30 Aug 2025 10:46:12 +0300 X-Gm-Features: Ac12FXw8gqRcCqiIz6LmDFBy64KDow5ZwkmjjRFsNp6APgoSqzFOQB-UC1Pp9Fo Message-ID: Subject: Re: [PATCH 13/15] iio: adc: ad4030: Enable dual data rate To: Marcelo Schmitt Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, devicetree@vger.kernel.org, linux-spi@vger.kernel.org, jic23@kernel.org, Michael.Hennerich@analog.com, nuno.sa@analog.com, eblanc@baylibre.com, dlechner@baylibre.com, andy@kernel.org, corbet@lwn.net, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, broonie@kernel.org, Jonathan.Cameron@huawei.com, andriy.shevchenko@linux.intel.com, ahaslam@baylibre.com, sergiu.cuciurean@analog.com, marcelo.schmitt1@gmail.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Sat, Aug 30, 2025 at 3:45=E2=80=AFAM Marcelo Schmitt wrote: > > Set AD4030 series device to do two data bit transitions per clock cycle p= er > active lane when specified by firmware. The dual data rate (DDR) feature = is > available only for host clock mode and echo clock mode. ... > struct ad4030_state { > enum ad4030_out_mode mode; > enum ad4030_lane_mode lane_mode; > enum ad4030_clock_mode clock_mode; > + bool ddr; I believe you run `pahole` each time you modify the data type like this. > /* offload sampling spi message */ > struct spi_transfer offload_xfer; > struct spi_message offload_msg; ... > else > offload_bpw =3D data_width / (1 << st->lane_mode); With the previous comment WRT right shift... > + if (st->ddr) > + offload_bpw /=3D 2; ...this also can use right shift, but I understand that 2 is more explicit to show the point of DDR (as "double"). ... > + /* DDR is only valid for echo clock and host clock modes */ > + if (ret =3D=3D AD4030_ECHO_CLOCK_MODE || ret =3D=3D AD4030_CLOCK_= HOST_MODE) { > + st->ddr =3D device_property_read_bool(dev, "adi,dual-data= -rate"); > + reg_modes |=3D FIELD_PREP(AD4030_REG_MODES_MASK_DDR_MODE,= st->ddr); FIELD_MODIFY()? > + } --=20 With Best Regards, Andy Shevchenko