[PATCH 0/4] staging: iio: DMA alignment fixes.

[PATCH 0/4] staging: iio: DMA alignment fixes.

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

When I introduced IIO_DMA_MINALIGN and applied it to all the drivers
in drivers/iio I said I'd swing by the few remaining staging drivers
at a later date. This set fixes those staging/iio drivers.

Note that no one has been very active on these drivers for some time.
They do however support parts that are still available (and I have
at least one of them) so I think it's worth keeping them around for now.
Perhaps the necessary cleanup work can be done against emulation or
road test or we can get parts for anyone interested in doing the necessary
work.

Anyhow, upshot is that it's unlikely anyone will feel ownership of these
drivers enough to review this series so if anyone has time a quick
glance over it would be much appreciated!

Thanks,

Jonathan

Jonathan Cameron (4):
  staging: iio: frequency: ad9832: Fix alignment for DMA safety
  staging: iio: frequency: ad9834: Fix alignment for DMA safety
  staging: iio: meter: ade7854: Fix alignment for DMA safety
  staging: iio: resolver: ad2s1210: Fix alignment for DMA safety

 drivers/staging/iio/frequency/ad9832.c  | 2 +-
 drivers/staging/iio/frequency/ad9834.c  | 2 +-
 drivers/staging/iio/meter/ade7854.h     | 2 +-
 drivers/staging/iio/resolver/ad2s1210.c | 4 ++--
 4 files changed, 5 insertions(+), 5 deletions(-)

-- 
2.37.1

[PATCH 1/4] staging: iio: frequency: ad9832: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/staging/iio/frequency/ad9832.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/staging/iio/frequency/ad9832.c b/drivers/staging/iio/frequency/ad9832.c
index f43464db618a..ce9fcba6bc5c 100644
--- a/drivers/staging/iio/frequency/ad9832.c
+++ b/drivers/staging/iio/frequency/ad9832.c
@@ -112,7 +112,7 @@ struct ad9832_state {
 	 * transfer buffers to live in their own cache lines.
 	 */
 	union {
-		__be16			freq_data[4]____cacheline_aligned;
+		__be16			freq_data[4] __aligned(IIO_DMA_MINALIGN);
 		__be16			phase_data[2];
 		__be16			data;
 	};
-- 
2.37.1

Re: [PATCH 1/4] staging: iio: frequency: ad9832: Fix alignment for DMA safety

[Andy Shevchenko]

On Sun, Aug 7, 2022 at 5:26 PM Jonathan Cameron <jic23@kernel.org> wrote:
>
> From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
> ____cacheline_aligned is an insufficient guarantee for non-coherent DMA
> on platforms with 128 byte cachelines above L1.  Switch to the updated
> IIO_DMA_MINALIGN definition.

...

>         union {
> -               __be16                  freq_data[4]____cacheline_aligned;
> +               __be16                  freq_data[4] __aligned(IIO_DMA_MINALIGN);
>                 __be16                  phase_data[2];
>                 __be16                  data;
>         };

Hmm... Can we rather mark the entire union with it?

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH 1/4] staging: iio: frequency: ad9832: Fix alignment for DMA safety

[Jonathan Cameron]

On Mon, 8 Aug 2022 11:18:34 +0200
Andy Shevchenko <andy.shevchenko@gmail.com> wrote:

> On Sun, Aug 7, 2022 at 5:26 PM Jonathan Cameron <jic23@kernel.org> wrote:
> >
> > From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> >
> > ____cacheline_aligned is an insufficient guarantee for non-coherent DMA
> > on platforms with 128 byte cachelines above L1.  Switch to the updated
> > IIO_DMA_MINALIGN definition.  
> 
> ...
> 
> >         union {
> > -               __be16                  freq_data[4]____cacheline_aligned;
> > +               __be16                  freq_data[4] __aligned(IIO_DMA_MINALIGN);
> >                 __be16                  phase_data[2];
> >                 __be16                  data;
> >         };  
> 
> Hmm... Can we rather mark the entire union with it?
> 

ah. I'd not even registered it was a union ;)  Anyhow, yes, that would make
sense.

[PATCH 2/4] staging: iio: frequency: ad9834: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/staging/iio/frequency/ad9834.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/staging/iio/frequency/ad9834.c b/drivers/staging/iio/frequency/ad9834.c
index 94b131ef8a22..2b4267a87e65 100644
--- a/drivers/staging/iio/frequency/ad9834.c
+++ b/drivers/staging/iio/frequency/ad9834.c
@@ -83,7 +83,7 @@ struct ad9834_state {
 	 * DMA (thus cache coherency maintenance) requires the
 	 * transfer buffers to live in their own cache lines.
 	 */
-	__be16				data ____cacheline_aligned;
+	__be16				data __aligned(IIO_DMA_MINALIGN);
 	__be16				freq_data[2];
 };
 
-- 
2.37.1

[PATCH 3/4] staging: iio: meter: ade7854: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Rodrigo Siqueira <rodrigosiqueiramelo@gmail.com>
---
 drivers/staging/iio/meter/ade7854.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/staging/iio/meter/ade7854.h b/drivers/staging/iio/meter/ade7854.h
index a51e6e3183d3..7a49f8f1016f 100644
--- a/drivers/staging/iio/meter/ade7854.h
+++ b/drivers/staging/iio/meter/ade7854.h
@@ -162,7 +162,7 @@ struct ade7854_state {
 			 int bits);
 	int irq;
 	struct mutex buf_lock;
-	u8 tx[ADE7854_MAX_TX] ____cacheline_aligned;
+	u8 tx[ADE7854_MAX_TX] __aligned(IIO_DMA_MINALIGN);
 	u8 rx[ADE7854_MAX_RX];
 
 };
-- 
2.37.1

[PATCH 4/4] staging: iio: resolver: ad2s1210: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.  As the tx[] an rx[] buffers are only used
in the same SPI exchanges, we should be safe with them on the same cacheline.
Hence only mark the first one __aligned(IIO_DMA_MINALIGN).

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/staging/iio/resolver/ad2s1210.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/staging/iio/resolver/ad2s1210.c b/drivers/staging/iio/resolver/ad2s1210.c
index c0b2716d0511..e4cf42438487 100644
--- a/drivers/staging/iio/resolver/ad2s1210.c
+++ b/drivers/staging/iio/resolver/ad2s1210.c
@@ -94,8 +94,8 @@ struct ad2s1210_state {
 	bool hysteresis;
 	u8 resolution;
 	enum ad2s1210_mode mode;
-	u8 rx[2] ____cacheline_aligned;
-	u8 tx[2] ____cacheline_aligned;
+	u8 rx[2] __aligned(IIO_DMA_MINALIGN);
+	u8 tx[2];
 };
 
 static const int ad2s1210_mode_vals[4][2] = {
-- 
2.37.1

Re: [PATCH 0/4] staging: iio: DMA alignment fixes.

[Andy Shevchenko]

On Sun, Aug 7, 2022 at 5:37 PM Jonathan Cameron <jic23@kernel.org> wrote:
>
> From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
> When I introduced IIO_DMA_MINALIGN and applied it to all the drivers
> in drivers/iio I said I'd swing by the few remaining staging drivers
> at a later date. This set fixes those staging/iio drivers.
>
> Note that no one has been very active on these drivers for some time.
> They do however support parts that are still available (and I have
> at least one of them) so I think it's worth keeping them around for now.
> Perhaps the necessary cleanup work can be done against emulation or
> road test or we can get parts for anyone interested in doing the necessary
> work.
>
> Anyhow, upshot is that it's unlikely anyone will feel ownership of these
> drivers enough to review this series so if anyone has time a quick
> glance over it would be much appreciated!

Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>

for non-commented patches.

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH 0/4] staging: iio: DMA alignment fixes.

[Jonathan Cameron]

On Mon, 8 Aug 2022 11:20:32 +0200
Andy Shevchenko <andy.shevchenko@gmail.com> wrote:

> On Sun, Aug 7, 2022 at 5:37 PM Jonathan Cameron <jic23@kernel.org> wrote:
> >
> > From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> >
> > When I introduced IIO_DMA_MINALIGN and applied it to all the drivers
> > in drivers/iio I said I'd swing by the few remaining staging drivers
> > at a later date. This set fixes those staging/iio drivers.
> >
> > Note that no one has been very active on these drivers for some time.
> > They do however support parts that are still available (and I have
> > at least one of them) so I think it's worth keeping them around for now.
> > Perhaps the necessary cleanup work can be done against emulation or
> > road test or we can get parts for anyone interested in doing the necessary
> > work.
> >
> > Anyhow, upshot is that it's unlikely anyone will feel ownership of these
> > drivers enough to review this series so if anyone has time a quick
> > glance over it would be much appreciated!  
> 
> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
> 
> for non-commented patches.
> 
Thanks, patches 2-4 applied. v2 of patch one to be posted shortly.

Jonathan