From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: MIME-Version: 1.0 In-Reply-To: <55F3F49D.9000201@kernel.org> References: <1441902761-11190-1-git-send-email-shraddha.6596@gmail.com> <55F3F49D.9000201@kernel.org> Date: Sat, 12 Sep 2015 16:47:23 +0530 Message-ID: Subject: Re: [PATCH 4/6] Staging: iio: cdc: Prefer using the BIT macro From: Shraddha Barke To: Jonathan Cameron Cc: Greg Kroah-Hartman , Julia Lawall , Hartmut Knaack , Andreas Dilger , Ian Abbott , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Content-Type: multipart/alternative; boundary=089e0111d1befbceb3051f8af9ae List-ID: --089e0111d1befbceb3051f8af9ae Content-Type: text/plain; charset=UTF-8 On Sat, Sep 12, 2015 at 3:17 PM, Jonathan Cameron wrote: > On 10/09/15 17:32, Shraddha Barke wrote: > > This patch replaces bit shifting on 1 with the BIT(x) macro > > > > This was done with coccinelle: > > @@ int g; @@ > > > > -(1 << g) > > +BIT(g) > > > > Signed-off-by: Shraddha Barke > Something odd happened here as this is only a small proportion of the cases > that should be updated in this file. There's one at the bottom of the > patch for starters! > > I didn't apply BIT(x) for mixed cases.I think I should drop this patch altogether but Greg has added it. Will it cause problems ? :( > This driver also uses a lot of cases of 0 shifted to represent > the opposite state for a given bit in the register. The effective > documentation provided by that is lost if we convert the bit set ones > over like this. Might seem odd, but perhaps we need a ZERO(X) macro > as well (which is of course always 0) to cover that approach. > > Jonathan > > --- > > drivers/staging/iio/cdc/ad7746.c | 8 ++++---- > > 1 file changed, 4 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/staging/iio/cdc/ad7746.c > b/drivers/staging/iio/cdc/ad7746.c > > index e6e9eaa..10fa372 100644 > > --- a/drivers/staging/iio/cdc/ad7746.c > > +++ b/drivers/staging/iio/cdc/ad7746.c > > @@ -46,10 +46,10 @@ > > #define AD7746_REG_VOLT_GAINL 18 > > > > /* Status Register Bit Designations (AD7746_REG_STATUS) */ > > -#define AD7746_STATUS_EXCERR (1 << 3) > > -#define AD7746_STATUS_RDY (1 << 2) > > -#define AD7746_STATUS_RDYVT (1 << 1) > > -#define AD7746_STATUS_RDYCAP (1 << 0) > > +#define AD7746_STATUS_EXCERR BIT(3) > > +#define AD7746_STATUS_RDY BIT(2) > > +#define AD7746_STATUS_RDYVT BIT(1) > > +#define AD7746_STATUS_RDYCAP BIT(0) > > > > /* Capacitive Channel Setup Register Bit Designations > (AD7746_REG_CAP_SETUP) */ > > #define AD7746_CAPSETUP_CAPEN (1 << 7) > > > > --089e0111d1befbceb3051f8af9ae Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable


On Sat, Sep 12, 2015 at 3:17 PM, Jonathan Cameron <= ;jic23@kernel.org= > wrote:
On 10/09/15 17:32, Shr= addha Barke wrote:
> This patch replaces bit shifting on 1 with the BIT(x) macro
>
> This was done with coccinelle:
> @@ int g; @@
>
> -(1 << g)
> +BIT(g)
>
> Signed-off-by: Shraddha Barke <shraddha.6596@gmail.com>
Something odd happened here as this is only a small proportion of the cases=
that should be updated in this file.=C2=A0 There's one at the bottom of= the
patch for starters!

I didn't apply BIT(x) for mixed cases.I think I s= hould drop this patch altogether but
Greg has added it. Will= it cause problems ? :(
=C2=A0
This driver also uses=C2=A0 a lot of cases of 0 shifted to represent
the opposite state for a given bit in the register.=C2=A0 The effective
documentation provided by that is lost if we convert the bit set ones
over like this.=C2=A0 Might seem odd, but perhaps we need a ZERO(X) macro as well (which is of course always 0) to cover that approach.

Jonathan
> ---
>=C2=A0 drivers/staging/iio/cdc/ad7746.c | 8 ++++----
>=C2=A0 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/staging/iio/cdc/ad7746.c b/drivers/staging/iio/cd= c/ad7746.c
> index e6e9eaa..10fa372 100644
> --- a/drivers/staging/iio/cdc/ad7746.c
> +++ b/drivers/staging/iio/cdc/ad7746.c
> @@ -46,10 +46,10 @@
>=C2=A0 #define AD7746_REG_VOLT_GAINL=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 18
>
>=C2=A0 /* Status Register Bit Designations (AD7746_REG_STATUS) */
> -#define AD7746_STATUS_EXCERR=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(1 <= < 3)
> -#define AD7746_STATUS_RDY=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (1= << 2)
> -#define AD7746_STATUS_RDYVT=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 <= < 1)
> -#define AD7746_STATUS_RDYCAP=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(1 <= < 0)
> +#define AD7746_STATUS_EXCERR=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0BIT(3)<= br> > +#define AD7746_STATUS_RDY=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 BI= T(2)
> +#define AD7746_STATUS_RDYVT=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 BIT(1)<= br> > +#define AD7746_STATUS_RDYCAP=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0BIT(0)<= br> >
>=C2=A0 /* Capacitive Channel Setup Register Bit Designations (AD7746_RE= G_CAP_SETUP) */
>=C2=A0 #define AD7746_CAPSETUP_CAPEN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 (1 << 7)
>


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