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[69.109.179.158]) by smtp.gmail.com with ESMTPSA id c3-20020a05620a268300b006fa9d101775sm4517640qkp.33.2022.12.11.11.36.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Dec 2022 11:36:28 -0800 (PST) Date: Sun, 11 Dec 2022 10:46:04 -0500 From: William Breathitt Gray To: Biju Das Cc: "linux-iio@vger.kernel.org" , Geert Uytterhoeven , Chris Paterson , Prabhakar Mahadev Lad , "linux-renesas-soc@vger.kernel.org" Subject: Re: [PATCH v8 3/5] Documentation: ABI: sysfs-bus-counter: add cascade_counts_enable and external_input_phase_clock_select Message-ID: References: <20221210102110.443043-1-biju.das.jz@bp.renesas.com> <20221210102110.443043-4-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="W3m6LQdzAdvdmkuw" Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org --W3m6LQdzAdvdmkuw Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sun, Dec 11, 2022 at 04:12:51PM +0000, Biju Das wrote: > Hi William Breathitt Gray, >=20 > Thanks for the feedback. >=20 > > Subject: Re: [PATCH v8 3/5] Documentation: ABI: sysfs-bus-counter: add > > cascade_counts_enable and external_input_phase_clock_select > >=20 > > On Sat, Dec 10, 2022 at 10:21:08AM +0000, Biju Das wrote: > > > +What: > > /sys/bus/counter/devices/counterX/external_input_phase_clock_select > > > +KernelVersion: 6.3 > > > +Contact: linux-iio@vger.kernel.org > > > +Description: > > > + This attribute selects the external clock pin for phase > > > + counting mode of counter X. > >=20 > > Hi Biju, > >=20 > > Remove the "This attribute" from the description, and capitalize the wo= rd > > "counter": "Selects the external clock pin for phase counting mode of > > Counter X." > >=20 > > > +What: > > /sys/bus/counter/devices/counterX/external_input_phase_clock_select_ > > available > >=20 > > At some point in the future I should combine the *_available blocks, but > > right now they're separated between Count and Signal configurations. > > This external_input_phase_clock_select_available is a device-level > > configuration so it'll need its own block as well, such as the followin= g. >=20 > Since it is device-level configuration, I will move the below 3 blocks > to the top of file. I hope it is ok to you. That's okay with me, so go ahead. I think at one point I was trying to keep the attributes listed in alphabetical order, but I haven't really minded lately as long as the information in this file is clear. William Breathitt Gray >=20 > +What: /sys/bus/counter/devices/counterX/cascade_counts_enable > +KernelVersion: 6.3 > +Contact: linux-iio@vger.kernel.org > +Description: > + Indicates the cascading of Counts on Counter X. > + > + Valid attribute values are boolean. > + > +What: /sys/bus/counter/devices/counterX/external_input_phase_cl= ock_select > +KernelVersion: 6.3 > +Contact: linux-iio@vger.kernel.org > +Description: > + Selects the external clock pin for phase counting mode of > + Counter X. > + > + MTCLKA-MTCLKB: > + MTCLKA and MTCLKB pins are selected for the exter= nal > + phase clock. > + > + MTCLKC-MTCLKD: > + MTCLKC and MTCLKD pins are selected for the exter= nal > + phase clock. > + > +What: /sys/bus/counter/devices/counterX/external_input_phase_cl= ock_select_available > +KernelVersion: 6.3 > +Contact: linux-iio@vger.kernel.org > +Description: > + Discrete set of available values for the respective devi= ce > + configuration are listed in this file. >=20 > Cheers, > Biju --W3m6LQdzAdvdmkuw Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEARYKAB0WIQSNN83d4NIlKPjon7a1SFbKvhIjKwUCY5X7PAAKCRC1SFbKvhIj K4urAP0RW9JiO8Gm3RgCrCv3SFp7BOm9Qw5iCmCzUNY2turI9AD/Zs1ONvGwfY3x bIvCh1WlOeR5aT5vj57ymPQdWmlpGgU= =PX+K -----END PGP SIGNATURE----- --W3m6LQdzAdvdmkuw--