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[69.109.179.158]) by smtp.gmail.com with ESMTPSA id i11-20020a056808030b00b0035468f2d410sm839940oie.55.2022.12.16.08.07.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Dec 2022 08:07:43 -0800 (PST) Date: Fri, 16 Dec 2022 11:01:58 -0500 From: William Breathitt Gray To: Biju Das Cc: linux-iio@vger.kernel.org, Geert Uytterhoeven , Chris Paterson , Prabhakar Mahadev Lad , linux-renesas-soc@vger.kernel.org Subject: Re: [PATCH v9 4/5] counter: Add Renesas RZ/G2L MTU3a counter driver Message-ID: References: <20221214103136.2493474-1-biju.das.jz@bp.renesas.com> <20221214103136.2493474-5-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="m7L7RCD2atf4o9Ml" Content-Disposition: inline In-Reply-To: <20221214103136.2493474-5-biju.das.jz@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org --m7L7RCD2atf4o9Ml Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Dec 14, 2022 at 10:31:35AM +0000, Biju Das wrote: > Add RZ/G2L MTU3a counter driver. This IP supports the following > phase counting modes on MTU1 and MTU2 channels >=20 > 1) 16-bit phase counting modes on MTU1 and MTU2 channels. > 2) 32-bit phase counting mode by cascading MTU1 and MTU2 channels. >=20 > This patch adds 3 counter value channels. > count0: 16-bit phase counter value channel on MTU1 > count1: 16-bit phase counter value channel on MTU2 > count2: 32-bit phase counter value channel by cascading > MTU1 and MTU2 channels. >=20 > The external input phase clock pin for the counter value channels > are as follows: > count0: "MTCLKA-MTCLKB" > count1: "MTCLKA-MTCLKB" or "MTCLKC-MTCLKD" > count2: "MTCLKA-MTCLKB" or "MTCLKC-MTCLKD" >=20 > Use the sysfs variable "external_input_phase_clock_select" to select the > external input phase clock pin and "cascade_counts_enable" to enable/ > disable cascading of channels. >=20 > Signed-off-by: Biju Das Hello Biju, Do you need to take the ch->lock before checking ch->is_busy to ensure it does not change? Regardless, I have some race comments below. > +static int rz_mtu3_count_function_read(struct counter_device *counter, > + struct counter_count *count, > + enum counter_function *function) > +{ > + struct rz_mtu3_channel *const ch =3D rz_mtu3_get_ch(counter, count->id); > + struct rz_mtu3_cnt *const priv =3D counter_priv(counter); > + u8 timer_mode; > + > + if (ch->is_busy && !priv->count_is_enabled[count->id]) > + return -EINVAL; The priv->lock must be taken because count_is_enabled could change after it's checked here. However, you'll need to spin up a helper function because you're currently calling rz_mtu3_count_function_read() in rz_mtu3_action_read(). So move the implementation of this function to a new helper function and call that here with the appropriate locks. > +static int rz_mtu3_count_direction_read(struct counter_device *counter, > + struct counter_count *count, > + enum counter_count_direction *direction) > +{ > + struct rz_mtu3_channel *const ch =3D rz_mtu3_get_ch(counter, count->id); > + struct rz_mtu3_cnt *const priv =3D counter_priv(counter); > + u8 tsr; > + > + if (ch->is_busy && !priv->count_is_enabled[count->id]) > + return -EINVAL; This needs to be locked for the same reason as above. William Breathitt Gray --m7L7RCD2atf4o9Ml Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEARYKAB0WIQSNN83d4NIlKPjon7a1SFbKvhIjKwUCY5yWdgAKCRC1SFbKvhIj K3qaAQDWDwcdhlK4JJVaRqFOAWS842v0/JYaKZthvt3sNcfBQgD/UT4oONxz4fCX E7zGBTjeipaBtM0U44jFiv9jPj2mDAI= =fYL/ -----END PGP SIGNATURE----- --m7L7RCD2atf4o9Ml--