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[69.109.179.158]) by smtp.gmail.com with ESMTPSA id h5-20020ac87145000000b003a69225c2cdsm1964770qtp.56.2022.12.16.13.46.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Dec 2022 13:46:57 -0800 (PST) Date: Fri, 16 Dec 2022 16:45:19 -0500 From: William Breathitt Gray To: Biju Das Cc: linux-iio@vger.kernel.org, Geert Uytterhoeven , Chris Paterson , Prabhakar Mahadev Lad , linux-renesas-soc@vger.kernel.org Subject: Re: [PATCH v10 4/5] counter: Add Renesas RZ/G2L MTU3a counter driver Message-ID: References: <20221216205028.340795-1-biju.das.jz@bp.renesas.com> <20221216205028.340795-5-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="riS0ngB9t/Qpq7S3" Content-Disposition: inline In-Reply-To: <20221216205028.340795-5-biju.das.jz@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org --riS0ngB9t/Qpq7S3 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Dec 16, 2022 at 08:50:27PM +0000, Biju Das wrote: > Add RZ/G2L MTU3a counter driver. This IP supports the following > phase counting modes on MTU1 and MTU2 channels >=20 > 1) 16-bit phase counting modes on MTU1 and MTU2 channels. > 2) 32-bit phase counting mode by cascading MTU1 and MTU2 channels. >=20 > This patch adds 3 counter value channels. > count0: 16-bit phase counter value channel on MTU1 > count1: 16-bit phase counter value channel on MTU2 > count2: 32-bit phase counter value channel by cascading > MTU1 and MTU2 channels. >=20 > The external input phase clock pin for the counter value channels > are as follows: > count0: "MTCLKA-MTCLKB" > count1: "MTCLKA-MTCLKB" or "MTCLKC-MTCLKD" > count2: "MTCLKA-MTCLKB" or "MTCLKC-MTCLKD" >=20 > Use the sysfs variable "external_input_phase_clock_select" to select the > external input phase clock pin and "cascade_counts_enable" to enable/ > disable cascading of channels. >=20 > Signed-off-by: Biju Das Hi Biju, You're missing an entry for this driver in the MAINTAINERS file so please add one. The code for this version looks good so you're welcome to add my Rb line. Reviewed-by: William Breathitt Gray I do have a minor suggestion below. > +static struct counter_count rz_mtu3_counts[] =3D { > + { > + .id =3D RZ_MTU3_16_BIT_MTU1_CH, > + .name =3D "Channel 1 Count", > + .functions_list =3D rz_mtu3_count_functions, > + .num_functions =3D ARRAY_SIZE(rz_mtu3_count_functions), > + .synapses =3D rz_mtu3_mtu1_count_synapses, > + .num_synapses =3D ARRAY_SIZE(rz_mtu3_mtu1_count_synapses), > + .ext =3D rz_mtu3_count_ext, > + .num_ext =3D ARRAY_SIZE(rz_mtu3_count_ext), > + }, > + { > + .id =3D RZ_MTU3_16_BIT_MTU2_CH, > + .name =3D "Channel 2 Count", > + .functions_list =3D rz_mtu3_count_functions, > + .num_functions =3D ARRAY_SIZE(rz_mtu3_count_functions), > + .synapses =3D rz_mtu3_mtu2_count_synapses, > + .num_synapses =3D ARRAY_SIZE(rz_mtu3_mtu2_count_synapses), > + .ext =3D rz_mtu3_count_ext, > + .num_ext =3D ARRAY_SIZE(rz_mtu3_count_ext), > + }, > + { > + .id =3D RZ_MTU3_32_BIT_CH, > + .name =3D "Channel 1 and 2 (combined) Count", These channels are actually cascaded, so replacing "combined" with "cascaded" here would be better. William Breathitt Gray --riS0ngB9t/Qpq7S3 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEARYKAB0WIQSNN83d4NIlKPjon7a1SFbKvhIjKwUCY5zm7wAKCRC1SFbKvhIj K49yAP9awI8QZ+IehAEM+ZvyGlK1CwT7qbO6U3bZs8V9UJMhcgEAkOs4CPLYEJFj PFabwNpN7aaDnRCf/eNIdiueNpIjyg4= =mBm0 -----END PGP SIGNATURE----- --riS0ngB9t/Qpq7S3--