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[69.109.179.158]) by smtp.gmail.com with ESMTPSA id c82-20020a251c55000000b00b9a7f23c2b8sm2658208ybc.24.2023.05.02.17.12.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 May 2023 17:12:58 -0700 (PDT) Date: Tue, 2 May 2023 20:12:56 -0400 From: William Breathitt Gray To: Pavel Machek Cc: Greg Kroah-Hartman , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Cameron , stable@vger.kernel.org Subject: Re: [RESEND PATCH 5.15 v3 5/5] counter: 104-quad-8: Fix race condition between FLAG and CNTR reads Message-ID: References: <20230411155220.9754-1-william.gray@linaro.org> <20230411155220.9754-5-william.gray@linaro.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="4aIilrXIIJYE6/fg" Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org --4aIilrXIIJYE6/fg Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, May 02, 2023 at 10:19:07AM +0200, Pavel Machek wrote: > Hi! >=20 > > On Tue, Apr 11, 2023 at 11:52:20AM -0400, William Breathitt Gray wrote: > > > commit 4aa3b75c74603c3374877d5fd18ad9cc3a9a62ed upstream. > > >=20 > > > The Counter (CNTR) register is 24 bits wide, but we can have an > > > effective 25-bit count value by setting bit 24 to the XOR of the Borr= ow > > > flag and Carry flag. The flags can be read from the FLAG register, bu= t a > > > race condition exists: the Borrow flag and Carry flag are instantaneo= us > > > and could change by the time the count value is read from the CNTR > > > register. >=20 > > > Since the race condition could result in an incorrect 25-bit count > > > value, remove support for 25-bit count values from this driver. >=20 > I believe usual solution is to read the carry, read the counter, and > read the carry again. If old_carry =3D new_carry, we are pretty sure we > did not hit the race, and can use 25 bit value. >=20 > Best regards, > Pavel > --=20 > People of Russia, stop Putin before his war on Ukraine escalates. That solution might work if the counter only increases, but if the counter is straddling the zero threshold then the Carry bit will toggle as the count overflows, underflows, and overflows again. For example: * START * Carry=3D0,Count=3DMAX * > Counting up... * Carry=3D1,Count=3D0 * DRIVER READS Carry=3D1 * > Counting down... * Carry=3D1,Count=3DMAX * > Counting up... * Carry=3D0,Count=3D0 * > Counting up... * Carry=3D0,Count=3D42 * DRIVER READS Count=3D42 * > Counting down... * Carry=3D1,Count=3DMAX * DRIVER READS Carry=3D1 * old_carry =3D new_carry * FINAL COUNT: Carry=3D1,Count=3D42 * This was never a state the counter actually reported Ultimately, the issue is that we have no way to get both Carry and Count atomically from the device. As long as there's a race condition there, we can't prevent possibly misinterpreting the Carry and Count values, so we unfortunately cannot ensure that our 25-bit Count value is an actual state the counter reported. William Breathitt Gray --4aIilrXIIJYE6/fg Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEARYKAB0WIQSNN83d4NIlKPjon7a1SFbKvhIjKwUCZFGnCAAKCRC1SFbKvhIj KwBgAQDGGMzTRsI9z7a069Eb50Vdm0UUKd5QReSBVCHZCJ0l3gEAq4lqY0R935IJ rMzdfqgEfGs/j+7TB1AMIqXxcWcLQgA= =m5Zn -----END PGP SIGNATURE----- --4aIilrXIIJYE6/fg--