From: Andy Shevchenko <andriy.shevchenko@intel.com>
To: Rodrigo Gobbi <rodrigo.gobbi.7@gmail.com>
Cc: jic23@kernel.org, dlechner@baylibre.com, nuno.sa@analog.com,
andy@kernel.org, ~lkcamp/patches@lists.sr.ht,
linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3] iio: adc: spear_adc: mask SPEAR_ADC_STATUS channel and avg sample before setting register
Date: Wed, 23 Jul 2025 16:49:24 +0300 [thread overview]
Message-ID: <aIDoZHBjO4tU3Gkh@smile.fi.intel.com> (raw)
In-Reply-To: <20250717221559.158872-1-rodrigo.gobbi.7@gmail.com>
On Thu, Jul 17, 2025 at 07:13:49PM -0300, Rodrigo Gobbi wrote:
> avg sample info is a bit field coded inside the following
> bits: 5,6,7 and 8 of a device status register.
>
> channel num info the same, but over bits: 1, 2 and 3.
>
> mask both values in order to avoid touching other register bits,
> since the first info (avg sample), came from dt.
Is there any issue with a Shift key?
> Signed-off-by: Rodrigo Gobbi <rodrigo.gobbi.7@gmail.com>
...
> #include <linux/clk.h>
> #include <linux/err.h>
> #include <linux/completion.h>
> +#include <linux/bitfield.h>
While it looks unordered, it's still better to squeeze a new header to the
place which organises a longest (but sparse) group of ordered headers. This
will reduce churn in the future for the ordering changes.
> #include <linux/iio/iio.h>
> #include <linux/iio/sysfs.h>
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2025-07-23 13:49 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-17 22:13 [PATCH v3] iio: adc: spear_adc: mask SPEAR_ADC_STATUS channel and avg sample before setting register Rodrigo Gobbi
2025-07-17 22:49 ` David Lechner
2025-07-19 12:10 ` Jonathan Cameron
2025-07-23 13:49 ` Andy Shevchenko [this message]
2025-07-24 12:47 ` Jonathan Cameron
2025-07-28 0:45 ` Rodrigo Gobbi
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