[PATCH v5 6/9] spi: dt-bindings: adi,axi-spi-engine: add multi-lane support

David Lechner
2026-01-12T17:46:37Z

Extend the ADI AXI SPI engine binding for multiple data lanes. This SPI
controller has a capability to read multiple data words at the same
time (e.g. for use with simultaneous sampling ADCs). The current FPGA
implementation can support up to 8 data lanes at a time (depending on a
compile-time configuration option).

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
v4 changes:
- Update to use spi-{tx,rx}-bus-width properties.
---
.../devicetree/bindings/spi/adi,axi-spi-engine.yaml | 15 +++++++++++++++
1 file changed, 15 insertions(+)

diff --git a/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml b/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml
index 4b3828eda6cb..0f2448371f17 100644
--- a/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml
+++ b/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml
@@ -70,6 +70,21 @@ required:

unevaluatedProperties: false

+patternProperties:
+ "^.*@[0-9a-f]+":
+ type: object
+
+ properties:
+ spi-rx-bus-width:
+ maxItems: 8
+ items:
+ enum: [0, 1]
+
+ spi-tx-bus-width:
+ maxItems: 8
+ items:
+ enum: [0, 1]
+
examples:
- |
spi@44a00000 {

--
2.43.0