[PATCH v5 0/9] spi: add multi-lane support

David Lechner
2026-01-12T17:46:28Z

This series is adding support for SPI controllers and peripherals that
have multiple SPI data lanes (data lanes being independent sets of
SDI/SDO lines, each with their own serializer/deserializer).

This series covers this specific use case:

+--------------+ +---------+
| SPI | | SPI |
| Controller | | ADC |
| | | |
| CS0 |--->| CS |
| SCLK |--->| SCLK |
| SDO |--->| SDI |
| SDI0 |<---| SDOA |
| SDI1 |<---| SDOB |
| SDI2 |<---| SDOC |
| SDI3 |<---| SDOD |
+--------------+ +--------+

The ADC is a simultaneous sampling ADC that can convert 4 samples at the
same time. It has 4 data output lines (SDOA-D) that each contain the
data of one of the 4 channels. So it requires a SPI controller with 4
separate deserializers in order to receive all of the information at the
same time.

This should also work for the use case in [1] as well. (Some of the
patches in this series were already submitted there). In that case the
SPI controller is used kind of like it is two separate SPI controllers,
each with its own chip select, clock, and data lines.

[1]: https://lore.kernel.org/linux-spi/20250616220054.3968946-1-sean.anderson@linux.dev/

The DT bindings are a fairly straight-forward mapping of which pins on
the peripheral are connected to which pins on the controller. The SPI
core code parses this and makes the information available to drivers.
When a peripheral driver sees that multiple data lanes are wired up, it
can chose to use them when sending messages.

The SPI message API is a bit higher-level than just specifying the
number of data lines for a SPI transfer though. I did some research on
other SPI controllers that have this feature. They tend to be the kind
meant for connecting to two flash memory chips at the same time but can
be used more generically as well. They generally have the option to
either use one lane at a time (Sean's use case), or can mirror the same
data on multiple lanes (no users of this yet) or can perform striping
of a single data FIFO/DMA stream to/from the two lanes (our use case).

For now, the API assumes that if you want to do mirror/striping, then
you want to use all available data lanes. Otherwise, it just uses the
first data lane for "normal" SPI transfers.

Signed-off-by: David Lechner <dlechner@baylibre.com>
---
Maintainer coordination:

Jonathan has requested an immutable branch from the SPI tree containing
the SPI patches from this series (all but the last two patches) so that
he can pick up the IIO patches.

Changes in v5:
- Fixed up affected dt-bindings for a new SPI controller that was added
recently.
- Made some clarification and fixes in the documentation in several
places.
- Fixed parsing of mapping properties.
- Link to v4: https://lore.kernel.org/r/20251219-spi-add-multi-bus-support-v4-0-145dc5204cd8@baylibre.com

Changes in v4:
- New patch to change spi-{rx,tx}-bus-width to array. This will cover
most use cases.
- Split data-lanes property into spi-{rx,tx}-lane-map. These properties
are now only needed for special cases instead of being the primary
property for multi-lane support.
- Didn't pick up Rob's acks since all DT bindings are significantly changed.
- Rework other code to accommodate the above changes.
- New documentation patch.
- Link to v3: https://lore.kernel.org/r/20251201-spi-add-multi-bus-support-v3-0-34e05791de83@baylibre.com

Changes in v3:
- Use existing data-lanes devicetree property name instead of creating a
new one.
- Renamed "buses" to "lanes" everywhere to match the devicetree property
name.
- Clarified bindings description about how to specify data lanes.
- Link to v2: https://lore.kernel.org/r/20251107-spi-add-multi-bus-support-v2-0-8a92693314d9@baylibre.com

Changes in v2:
- Renamed devicetree property spi-buses to spi-data-buses. (Driver code
was already using spi->data_buses, so it matches).
- Fixed a small bug in the AXI ADC driver changes.
- Moved one line of code in the ADC driver changes.
- Link to v1: https://lore.kernel.org/r/20251014-spi-add-multi-bus-support-v1-0-2098c12d6f5f@baylibre.com

---
David Lechner (9):
spi: dt-bindings: change spi-{rx,tx}-bus-width to arrays
spi: dt-bindings: add spi-{tx,rx}-lane-map properties
spi: support controllers with multiple data lanes
spi: add multi_lane_mode field to struct spi_transfer
spi: Documentation: add page on multi-lane support
spi: dt-bindings: adi,axi-spi-engine: add multi-lane support
spi: axi-spi-engine: support SPI_MULTI_LANE_MODE_STRIPE
dt-bindings: iio: adc: adi,ad7380: add spi-rx-bus-width property
iio: adc: ad7380: add support for multiple SPI lanes

.../bindings/display/panel/sitronix,st7789v.yaml | 5 +-
.../devicetree/bindings/iio/adc/adi,ad4030.yaml | 42 +++-
.../devicetree/bindings/iio/adc/adi,ad4695.yaml | 5 +-
.../devicetree/bindings/iio/adc/adi,ad7380.yaml | 23 +++
.../bindings/spi/adi,axi-spi-engine.yaml | 15 ++
.../bindings/spi/allwinner,sun4i-a10-spi.yaml | 6 +-
.../bindings/spi/allwinner,sun6i-a31-spi.yaml | 6 +-
.../bindings/spi/andestech,ae350-spi.yaml | 6 +-
.../bindings/spi/nvidia,tegra210-quad.yaml | 6 +-
.../bindings/spi/spi-peripheral-props.yaml | 40 +++-
Documentation/spi/index.rst | 1 +
Documentation/spi/multiple-data-lanes.rst | 217 +++++++++++++++++++++
drivers/iio/adc/ad7380.c | 51 +++--
drivers/spi/spi-axi-spi-engine.c | 145 +++++++++++++-
drivers/spi/spi.c | 116 ++++++++++-
include/linux/spi/spi.h | 30 +++
16 files changed, 676 insertions(+), 38 deletions(-)
---
base-commit: f417b7ffcbef7d76b0d8860518f50dae0e7e5eda
change-id: 20250815-spi-add-multi-bus-support-1b35d05c54f6

Best regards,
--
David Lechner <dlechner@baylibre.com>