[PATCH v5 1/9] spi: dt-bindings: change spi-{rx,tx}-bus-width to arrays

David Lechner
2026-01-12T17:46:29Z

Change spi-rx-bus-width and spi-tx-bus-width properties from single
uint32 values to arrays of uint32 values. This allows describing SPI
peripherals connected to controllers that have multiple data lanes for
receiving or transmitting two or more words in parallel.

Each index in the array corresponds to a physical data lane (one or more
wires depending on the bus width). Additional mapping properties will be
needed in cases where a lane on the controller or peripheral is skipped.

Bindings that make use of this property are updated in the same commit
to avoid validation errors.

The adi,ad4030 binding can now better describe the chips multi-lane
capabilities, so that binding is refined and gets a new example.

Converting from single uint32 to array of uint32 does not break .dts/
.dtb files since there is no difference between specifying a single
uint32 value and an array with a single uint32 value in devicetree.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Signed-off-by: David Lechner <dlechner@baylibre.com>
---

v5 changes:
- Added change for andestech,ae350-spi.yaml (recently new file).

v4 changes:
- New patch to replace data-lanes property patch.

In v3, Rob suggested possibly splitting the spi-controller.yaml file
to have a way to make most SPI controllers have maxItems: 1 for these
properties. I would like to avoid that because it doesn't seem scalable,
e.g. if we need another similar split in the future, the number of
combinations would grow exponentially (factorially?). I have an idea to
instead do this using $dynamicAnchor and $dynamicRef, but dt-schema
doesn't currently support that. So I propose we do the best we can for
now with the current dt-schema and make further improvements later.

Also, in v3, I suggested that we could have leading 0s in the arrays
to indicate unused lanes. But after further consideration, I think it's
better to have separate lane-mapping properties for that purpose. It
will be easier to explain and parse and be a bit more flexible that way.
---
.../bindings/display/panel/sitronix,st7789v.yaml | 5 +--
.../devicetree/bindings/iio/adc/adi,ad4030.yaml | 42 +++++++++++++++++++++-
.../devicetree/bindings/iio/adc/adi,ad4695.yaml | 5 +--
.../bindings/spi/allwinner,sun4i-a10-spi.yaml | 6 ++--
.../bindings/spi/allwinner,sun6i-a31-spi.yaml | 6 ++--
.../bindings/spi/andestech,ae350-spi.yaml | 6 ++--
.../bindings/spi/nvidia,tegra210-quad.yaml | 6 ++--
.../bindings/spi/spi-peripheral-props.yaml | 26 ++++++++++----
8 files changed, 83 insertions(+), 19 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/panel/sitronix,st7789v.yaml b/Documentation/devicetree/bindings/display/panel/sitronix,st7789v.yaml
index 0ce2ea13583d..c35d4f2ab9a4 100644
--- a/Documentation/devicetree/bindings/display/panel/sitronix,st7789v.yaml
+++ b/Documentation/devicetree/bindings/display/panel/sitronix,st7789v.yaml
@@ -34,8 +34,9 @@ properties:
spi-cpol: true

spi-rx-bus-width:
- minimum: 0
- maximum: 1
+ items:
+ minimum: 0
+ maximum: 1

dc-gpios:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml
index 54e7349317b7..e22d518135f2 100644
--- a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml
@@ -37,7 +37,15 @@ properties:
maximum: 102040816

spi-rx-bus-width:
- enum: [1, 2, 4]
+ maxItems: 2
+ # all lanes must have the same width
+ oneOf:
+ - contains:
+ const: 1
+ - contains:
+ const: 2
+ - contains:
+ const: 4

vdd-5v-supply: true
vdd-1v8-supply: true
@@ -88,6 +96,18 @@ oneOf:

unevaluatedProperties: false

+allOf:
+ - if:
+ properties:
+ compatible:
+ enum:
+ - adi,ad4030-24
+ - adi,ad4032-24
+ then:
+ properties:
+ spi-rx-bus-width:
+ maxItems: 1
+
examples:
- |
#include <dt-bindings/gpio/gpio.h>
@@ -108,3 +128,23 @@ examples:
reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
};
};
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "adi,ad4630-24";
+ reg = <0>;
+ spi-max-frequency = <80000000>;
+ spi-rx-bus-width = <4>, <4>;
+ vdd-5v-supply = <&supply_5V>;
+ vdd-1v8-supply = <&supply_1_8V>;
+ vio-supply = <&supply_1_8V>;
+ ref-supply = <&supply_5V>;
+ cnv-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4695.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4695.yaml
index cbde7a0505d2..ae8d0b5f328b 100644
--- a/Documentation/devicetree/bindings/iio/adc/adi,ad4695.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4695.yaml
@@ -38,8 +38,9 @@ properties:
spi-cpha: true

spi-rx-bus-width:
- minimum: 1
- maximum: 4
+ items:
+ minimum: 1
+ maximum: 4

avdd-supply:
description: Analog power supply.
diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun4i-a10-spi.yaml b/Documentation/devicetree/bindings/spi/allwinner,sun4i-a10-spi.yaml
index e1ab3f523ad6..a34e6471dbe8 100644
--- a/Documentation/devicetree/bindings/spi/allwinner,sun4i-a10-spi.yaml
+++ b/Documentation/devicetree/bindings/spi/allwinner,sun4i-a10-spi.yaml
@@ -55,10 +55,12 @@ patternProperties:
maximum: 4

spi-rx-bus-width:
- const: 1
+ items:
+ - const: 1

spi-tx-bus-width:
- const: 1
+ items:
+ - const: 1

required:
- compatible
diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
index 1b91d1566c95..a6067030c5ed 100644
--- a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
+++ b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
@@ -81,10 +81,12 @@ patternProperties:
maximum: 4

spi-rx-bus-width:
- const: 1
+ items:
+ - const: 1

spi-tx-bus-width:
- const: 1
+ items:
+ - const: 1

required:
- compatible
diff --git a/Documentation/devicetree/bindings/spi/andestech,ae350-spi.yaml b/Documentation/devicetree/bindings/spi/andestech,ae350-spi.yaml
index 78093468dd5e..8e441742cee6 100644
--- a/Documentation/devicetree/bindings/spi/andestech,ae350-spi.yaml
+++ b/Documentation/devicetree/bindings/spi/andestech,ae350-spi.yaml
@@ -45,10 +45,12 @@ patternProperties:

properties:
spi-rx-bus-width:
- enum: [1, 4]
+ items:
+ - enum: [1, 4]

spi-tx-bus-width:
- enum: [1, 4]
+ items:
+ - enum: [1, 4]

allOf:
- $ref: spi-controller.yaml#
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
index 8b3640280559..909c204b8adf 100644
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
@@ -54,10 +54,12 @@ patternProperties:

properties:
spi-rx-bus-width:
- enum: [1, 2, 4]
+ items:
+ - enum: [1, 2, 4]

spi-tx-bus-width:
- enum: [1, 2, 4]
+ items:
+ - enum: [1, 2, 4]

required:
- compatible
diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
index 8b6e8fc009db..59ddead7da14 100644
--- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
+++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
@@ -64,9 +64,16 @@ properties:
description:
Bus width to the SPI bus used for read transfers.
If 0 is provided, then no RX will be possible on this device.
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [0, 1, 2, 4, 8]
- default: 1
+
+ Some SPI peripherals and controllers may have multiple data lanes for
+ receiving two or more words at the same time. If this is the case, each
+ index in the array represents the lane on both the SPI peripheral and
+ controller. Additional mapping properties may be needed if a lane is
+ skipped on either side.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ enum: [0, 1, 2, 4, 8]
+ default: [1]

spi-rx-delay-us:
description:
@@ -81,9 +88,16 @@ properties:
description:
Bus width to the SPI bus used for write transfers.
If 0 is provided, then no TX will be possible on this device.
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [0, 1, 2, 4, 8]
- default: 1
+
+ Some SPI peripherals and controllers may have multiple data lanes for
+ transmitting two or more words at the same time. If this is the case, each
+ index in the array represents the lane on both the SPI peripheral and
+ controller. Additional mapping properties may be needed if a lane is
+ skipped on either side.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ enum: [0, 1, 2, 4, 8]
+ default: [1]

spi-tx-delay-us:
description:

--
2.43.0