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X-CSE-ConnectionGUID: QzidEKrCQqywFoEvvMIDaQ== X-CSE-MsgGUID: hHxC7f/QT9qE4H8kD+6Z6w== X-IronPort-AV: E=McAfee;i="6800,10657,11670"; a="79977251" X-IronPort-AV: E=Sophos;i="6.21,225,1763452800"; d="scan'208";a="79977251" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jan 2026 02:09:23 -0800 X-CSE-ConnectionGUID: nCgo7y7nS+SB6ivhyZ/2wA== X-CSE-MsgGUID: 9QmYMU7TQKK9zutJt+nHog== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,225,1763452800"; d="scan'208";a="209484837" Received: from pgcooper-mobl3.ger.corp.intel.com (HELO localhost) ([10.245.244.83]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jan 2026 02:09:17 -0800 Date: Wed, 14 Jan 2026 12:09:15 +0200 From: Andy Shevchenko To: Konrad Dybcio Cc: AngeloGioacchino Del Regno , jic23@kernel.org, dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org, srini@kernel.org, vkoul@kernel.org, neil.armstrong@linaro.org, sre@kernel.org, sboyd@kernel.org, krzk@kernel.org, dmitry.baryshkov@oss.qualcomm.com, quic_wcheng@quicinc.com, melody.olvera@oss.qualcomm.com, quic_nsekar@quicinc.com, ivo.ivanov.ivanov1@gmail.com, abelvesa@kernel.org, luca.weiss@fairphone.com, mitltlatltl@gmail.com, krishna.kurapati@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-pm@vger.kernel.org, kernel@collabora.com Subject: Re: [PATCH v7 05/10] nvmem: qcom-spmi-sdam: Migrate to devm_spmi_subdevice_alloc_and_add() Message-ID: References: <8bf79979-0946-4ed9-b8d4-c442a6e54833@collabora.com> <401c5e7b-ff33-44e8-98a5-8cc6af4f2a87@collabora.com> <647b4acc-3310-4329-ac7a-77e86bab74a3@collabora.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo On Wed, Jan 14, 2026 at 11:04:30AM +0100, Konrad Dybcio wrote: > On 1/14/26 10:55 AM, Andy Shevchenko wrote: > > On Wed, Jan 14, 2026 at 10:47:20AM +0100, Konrad Dybcio wrote: > >> On 1/14/26 10:42 AM, Andy Shevchenko wrote: > >>> On Wed, Jan 14, 2026 at 10:09:45AM +0100, AngeloGioacchino Del Regno wrote: > >>>> Il 14/01/26 10:07, Andy Shevchenko ha scritto: > >>>>> On Wed, Jan 14, 2026 at 10:03:57AM +0100, AngeloGioacchino Del Regno wrote: > >>>>>> Il 14/01/26 10:00, Andy Shevchenko ha scritto: > >>>>>>> On Wed, Jan 14, 2026 at 09:59:40AM +0100, AngeloGioacchino Del Regno wrote: > >>>>>>>> Il 14/01/26 09:56, Andy Shevchenko ha scritto: > >>>>>>>>> On Wed, Jan 14, 2026 at 09:39:52AM +0100, AngeloGioacchino Del Regno wrote: ... > >>>>>>>>>> + struct regmap_config sdam_regmap_config = { > >>>>>>>>>> + .reg_bits = 16, > >>>>>>>>>> + .val_bits = 8, > >>>>>>>>> > >>>>>>>>>> + .max_register = 0x100, > >>>>>>>>> > >>>>>>>>> Are you sure? This might be a bad naming, but here max == the last accessible. > >>>>>>>>> I bet it has to be 0xff (but since the address is 16-bit it might be actually > >>>>>>>>> 257 registers, but sounds very weird). > >>>>>>>> > >>>>>>>> Yes, I'm sure. > >>>>>>> > >>>>>>> So, what is resided on address 0x100 ? > >>>>>> > >>>>>> I don't remember, this is research from around 5 months ago, when I've sent > >>>>>> the v1 of this. > >>>>>> > >>>>>> If you really want though, I can incorrectly set max_register to 0xff. > >>>>> > >>>>> Why incorrectly? Can you dig into the datasheet and check, please? We don't > >>>>> know what is the 0x100 address means. > >>>> > >>>> I don't have any datasheets for Qualcomm IPs. > >>> > >>> Hmm... Can we have somebody from QC to check on this? > >>> Perhaps Dmitry? > >> > >> 0xe6 is the last usable register today > > > > Thanks for checking! > > > >> But I wouldn't mind either 0xff or 0x100 because I don't want > >> anyone to pull their hair out if a regmap access is dropped some day.. > > > > There is actually about the exact window size where registers are belong to the > > same entity (subdevice). As in the HW world most of the things are stuck with > > power-of-two numbers, and taking into account the naming of the field, I do not > > believe one provides a 257 (256 + 1 = 2⁸ + 1) register _windows_ ("s" is also > > important here, as it points out to the pattern) for the subdevices. I bet the > > 0xff, i.e. 256, is the *correct* window from the HW perspective. > > Right, [0x100n, 0x100n + 0xff] inclusive is the reserved register window > for all Qualcomm PMIC peripherals, so I guess 0xff is the correct choice > here Thanks for the clarification, v8 addresses that, so seems to me good to go. > If a peripheral is more complex, it's split into a couple of these > same-sized blocks Right. -- With Best Regards, Andy Shevchenko