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X-CSE-ConnectionGUID: BVxXfiViS6SOA04aDbv7yw== X-CSE-MsgGUID: ZCFESVImQaC+Dgxl8IeXFQ== X-IronPort-AV: E=McAfee;i="6800,10657,11727"; a="78356748" X-IronPort-AV: E=Sophos;i="6.23,118,1770624000"; d="scan'208";a="78356748" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Mar 2026 04:14:48 -0700 X-CSE-ConnectionGUID: 29XU/dBMSeKiinHG2o/jWQ== X-CSE-MsgGUID: v5c8/l0YRmiK7epatjCS9Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,118,1770624000"; d="scan'208";a="225255649" Received: from pgcooper-mobl3.ger.corp.intel.com (HELO localhost) ([10.245.245.246]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Mar 2026 04:14:44 -0700 Date: Fri, 13 Mar 2026 13:14:41 +0200 From: Andy Shevchenko To: radu.sabau@analog.com Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , Nuno =?iso-8859-1?Q?S=E1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= , Liam Girdwood , Mark Brown , Linus Walleij , Bartosz Golaszewski , Philipp Zabel , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, linux-gpio@vger.kernel.org Subject: Re: [PATCH v3 0/4] iio: adc: ad4691: add driver for AD4691 multichannel SAR ADC family Message-ID: References: <20260313-ad4692-multichannel-sar-adc-driver-v3-0-b4d14d81a181@analog.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20260313-ad4692-multichannel-sar-adc-driver-v3-0-b4d14d81a181@analog.com> Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo On Fri, Mar 13, 2026 at 12:07:24PM +0200, Radu Sabau via B4 Relay wrote: > This series adds support for the Analog Devices AD4691 family of > high-speed, low-power multichannel successive approximation register > (SAR) ADCs with an SPI-compatible serial interface. > > The family includes: > - AD4691: 16-channel, 500 kSPS > - AD4692: 16-channel, 1 MSPS > - AD4693: 8-channel, 500 kSPS > - AD4694: 8-channel, 1 MSPS > > The devices support two operating modes, auto-detected from the device > tree: > - CNV Clock Mode: external PWM drives CNV independently of SPI; > DATA_READY on GP0 signals end of conversion > - Manual Mode: CNV tied to SPI CS; each SPI transfer reads > the previous conversion result and starts the > next (pipelined N+1 scheme) > > A new driver is warranted rather than extending ad4695: the AD4691 > data path uses an accumulator-register model — results are read from > AVG_IN registers, with ACC_MASK, ADC_SETUP, DEVICE_SETUP, and > GPIO_MODE registers controlling the sequencer — none of which exist > in AD4695. CNV Clock Mode (PWM drives CNV independently of SPI) and > Manual Mode (pipelined N+1 transfers) also have no equivalent in > AD4695's command-embedded single-cycle protocol. > > The series is structured as follows: > 1/4 - DT bindings (YAML schema + dt-bindings header) and > MAINTAINERS entry > 2/4 - Initial driver: register map via custom regmap callbacks, > IIO read_raw/write_raw, both operating modes, single-channel > reads via internal oscillator (Autonomous Mode) > 3/4 - Triggered buffer support: IRQ-driven (DATA_READY on GP0) for > CNV Clock Mode; hrtimer-based trigger for Manual Mode to > handle the pipelined N+1 SPI protocol > 4/4 - SPI Engine offload support: DMA-backed high-throughput > capture path using the SPI offload subsystem I stopped review where I stopped because I have a feeling that you ignored some of my comments from the previous version. Why? What's going on? -- With Best Regards, Andy Shevchenko