From: Andy Shevchenko <andriy.shevchenko@intel.com>
To: Stepan Ionichev <sozdayvek@gmail.com>
Cc: jic23@kernel.org, lars@metafoo.de, Michael.Hennerich@analog.com,
alisa.roman@analog.com, dlechner@baylibre.com,
nuno.sa@analog.com, andy@kernel.org, linux-iio@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] iio: adc: ad7192: fix GPOCON register access annotation
Date: Wed, 13 May 2026 16:35:30 +0300 [thread overview]
Message-ID: <agR-Is0LLtfvhUne@ashevche-desk.local> (raw)
In-Reply-To: <20260513101332.8699-1-sozdayvek@gmail.com>
On Wed, May 13, 2026 at 03:13:32PM +0500, Stepan Ionichev wrote:
> The comment next to AD7192_REG_GPOCON marks the register as RO,
> but the AD7192 datasheet (Rev. A, page 24, GPOCON REGISTER) says:
> "The GPOCON register is an 8-bit register from which data can be
> read or to which data can be written."
>
> The driver itself uses ad_sd_write_reg() against this register in
> ad7192_show_scale() / write paths to control the bridge power-down
> switch and digital outputs, which matches the RW datasheet
> description. Update the comment to RW so it does not mislead
> future readers.
Makes sense,
Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
--
With Best Regards,
Andy Shevchenko
prev parent reply other threads:[~2026-05-13 13:35 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-13 10:13 [PATCH] iio: adc: ad7192: fix GPOCON register access annotation Stepan Ionichev
2026-05-13 13:35 ` Andy Shevchenko [this message]
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