Re: [PATCH RFC 2/3] dmaengine: dma-axi-dmac: Switch to bitmap-based address width masks

[Frank Li <Frank.li@oss.nxp.com>]

On Mon, Jun 22, 2026 at 05:09:10PM +0100, Nuno Sá wrote:
> On Mon, Jun 22, 2026 at 09:51:46AM -0500, Frank Li wrote:
> > On Mon, Jun 22, 2026 at 10:26:41AM +0100, Nuno Sá wrote:
> > > On Fri, Jun 19, 2026 at 03:02:53PM -0400, Frank Li wrote:
> > > > On Fri, Jun 19, 2026 at 11:22:54AM -0500, Frank Li wrote:
> > > > > On Thu, Jun 18, 2026 at 06:10:52PM +0100, Nuno Sá wrote:
> > > > > > [You don't often get email from noname.nuno@gmail.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> > > > > >
> > > > > > On Tue, Jun 16, 2026 at 11:23:39AM -0500, Frank Li wrote:
> > > > > > > On Tue, Jun 16, 2026 at 04:40:53PM +0100, Nuno Sá via B4 Relay wrote:
> > > > > > > > [You don't often get email from devnull+nuno.sa.analog.com@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> > > > > > > >
> > > > > > > > From: Nuno Sá <nuno.sa@analog.com>
> > > > > > > >
> > > > > > > > Advertise the source and destination bus widths through the new
> > > > > > > > dma_set_{src,dst}_addr_mask() helpers instead of open-coding the legacy
> > > > > > > > BIT() mask. This moves the driver onto the representation that can
> > > > > > > > express widths of 32 bytes and above and allows the legacy u32 field to
> > > > > > > > be removed once all users are converted.
> > > > > > > >
> > > > > > > > While at it, give the channel width members their proper
> > > > > > > > enum dma_slave_buswidth type.
> > > > > > > >
> > > > > > > > Signed-off-by: Nuno Sá <nuno.sa@analog.com>
> > > > > > > > ---
> > > > > > > >  drivers/dma/dma-axi-dmac.c | 12 ++++++++----
> > > > > > > >  1 file changed, 8 insertions(+), 4 deletions(-)
> > > > > > > >
> > > > > > > > diff --git a/drivers/dma/dma-axi-dmac.c b/drivers/dma/dma-axi-dmac.c
> > > > > > > > index d47ff27e1408..19c258d511ca 100644
> > > > > > > > --- a/drivers/dma/dma-axi-dmac.c
> > > > > > > > +++ b/drivers/dma/dma-axi-dmac.c
> > > > > > > > @@ -152,8 +152,8 @@ struct axi_dmac_chan {
> > > > > > > >         struct list_head active_descs;
> > > > > > > >         enum dma_transfer_direction direction;
> > > > > > > >
> > > > > > > > -       unsigned int src_width;
> > > > > > > > -       unsigned int dest_width;
> > > > > > > > +       enum dma_slave_buswidth src_width;
> > > > > > > > +       enum dma_slave_buswidth dest_width;
> > > > > > > >         unsigned int src_type;
> > > > > > > >         unsigned int dest_type;
> > > > > > > >
> > > > > > > > @@ -1262,8 +1262,12 @@ static int axi_dmac_probe(struct platform_device *pdev)
> > > > > > > >         dma_dev->device_terminate_all = axi_dmac_terminate_all;
> > > > > > > >         dma_dev->device_synchronize = axi_dmac_synchronize;
> > > > > > > >         dma_dev->dev = &pdev->dev;
> > > > > > > > -       dma_dev->src_addr_widths = BIT(dmac->chan.src_width);
> > > > > > > > -       dma_dev->dst_addr_widths = BIT(dmac->chan.dest_width);
> > > > > > > > +       ret = dma_set_src_addr_mask(dma_dev, &dmac->chan.src_width, 1);
> > > > > > > > +       if (ret)
> > > > > > > > +               return ret;
> > > > > > > > +       ret = dma_set_dst_addr_mask(dma_dev, &dmac->chan.dest_width, 1);
> > > > > > > > +       if (ret)
> > > > > > > > +               return ret;
> > > > > > >
> > > > > > >
> > > > > > > This patch is okay.  I think most system only set one width once, do we
> > > > > > > really need pass down arrary.
> > > > > >
> > > > > > I think so. See:
> > > > > >
> > > > > > https://elixir.bootlin.com/linux/v7.1/source/drivers/dma/st_fdma.c#L723
> > > > > > https://elixir.bootlin.com/linux/v7.1/source/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c#L1565
> > > > > > https://elixir.bootlin.com/linux/v7.1/source/drivers/dma/hsu/hsu.c#L475
> > > > > >
> > > > > > And likely there are more. To fully support all widths I'm not seeing
> > > > > > any other obvious way.
> > > > >
> > > > > I need more time to understand why need src_addr_width, which looks like
> > > > > address alignmenet requirment.
> > > > >
> > > > > If it is address alginment requirement, only need lowest one, like suport
> > > > > byte, must be support other alignments.
> > > > >
> > > > > if it is total address space, which should be controller by dma-ranges.
> > > >
> > > > I grep kernel code, only sound/core/pcm_dmaegine.c check src/dst_addr_width.
> > > > (I think src/dsk_bus_width is more reasonable). because the name is the
> > > > same as dma_slave_cfg, it is easy to cause confuse.
> > >
> > > No complains for the new naming. If everyone agrees on that, I'm fine.
> > >
> > > >
> > > > So far, still have not seen user case, which more than 8byte for cap.
> > >
> > > On the consumer side the IIO dmaengine will use more than that (we have
> > > designs for that - that's how I found the issue). But yeah, it just uses the
> > > min value (it is just that dma-axi-dmac only sets one).
> > >
> > > >
> > > > Add it should only set min value should be enougth, if update only user
> > > > sound/core/pcm_dmaegine.c
> > > >
> > >
> > > Not sure how that works on the pcm_dmaegine.c. It sets more 'hw->formats' than the minimum.
> > > And IIRC, this ends up being configurable from userspace so we might
> > > really want all the available options.
> > >
> > > Hence, given that we do need more than 32bytes and some users (seems
> > > like 1 only) do look for more than the minimum width,
> >
> > If FIFO space require 32bytes data bus width,  4Bytes DMA engine should be
> > match requirmment, cap just help filter dma channel.
>
> I'm not sure I'm getting your point but on dma caps, the src/dst addr
> widths is a mask. So for 32bytes widths, we need to set bit 32 (which
> currently is an open path for undefined behavior)

Bitmask does make sense, I don't think DMAEngine only support 32byte bus
width for slave FIFO.

If support 4Byte, it native supportted any N*4Byte.

So needn't bit mask to indicate all support bytes.

> >
> > each transfer, dma_slave_cfg should set specific bus width requirement.
> >
> > If memory have requirement for 32bytes, typical cache line length for
> > hardwaer coherence transfer, it should use dmaengine_alignment.
> >
> > So I think only need set min value should be enough if fix pcm_dmaegine.c.
> >
>
> What fix for pcm_dmaegine.c? Not sure there's anything to be fixed in
> there... The code seems to use the dma bus width to match against PCM
> formats supported and filter only the ones we can support (per dma cap).

if cap is one byte, it should support 8, 16, 24, 32, 64
if cap is two byte, it should support 16, 32, 64
if cap is 4 byte,  it only support 32 and 64.

Needn't mask each bit.

Frank

> If we only set the min, that means the PCM code all of the sudden only
> supports one format and I'm not sure that should be always the case or
> that we won't break any user.
>
> I mean the dmaengine src/dst_addr_widths must be a mask for a reason,
> no?
>
> - Nuno Sá
>
> > Frank
> >
> > > I would say the
> > > array is fine. IMHO, it's also safer (from a "support all" point of view  and really not
> > > complicated at all so I would just not risk it.
> >
> >
> >
> > >
> > > (we can also have one liner helpers for the case where only width is
> > > set).
> > >
> > > - Nuno Sá
> > >
> > > >
> > > > >
> > > > > Frank
> > > > >
> > > > > >
> > > > > > - Nuno Sá
> > > > > > >
> > > > > > > Frank
> > > > > > >
> > > > > > > >         dma_dev->directions = BIT(dmac->chan.direction);
> > > > > > > >         dma_dev->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
> > > > > > > >         dma_dev->max_sg_burst = 31; /* 31 SGs maximum in one burst */
> > > > > > > >
> > > > > > > > --
> > > > > > > > 2.54.0
> > > > > > > >
> > > > > > > >