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Thu, 25 Jun 2026 01:53:43 -0700 (PDT) Date: Thu, 25 Jun 2026 09:54:46 +0100 From: Nuno =?utf-8?B?U8Oh?= To: Frank Li Cc: Andy Shevchenko , nuno.sa@analog.com, dmaengine@vger.kernel.org, linux-iio@vger.kernel.org, Vinod Koul , Frank Li , Lars-Peter Clausen , Jonathan Cameron , David Lechner , Andy Shevchenko Subject: Re: [PATCH RFC 2/3] dmaengine: dma-axi-dmac: Switch to bitmap-based address width masks Message-ID: References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Wed, Jun 24, 2026 at 11:49:47AM -0500, Frank Li wrote: > On Wed, Jun 24, 2026 at 04:33:53PM +0100, Nuno Sá wrote: > > On Tue, Jun 23, 2026 at 01:27:37PM +0300, Andy Shevchenko wrote: > > > On Tue, Jun 23, 2026 at 11:14:51AM +0100, Nuno Sá wrote: > > > > On Mon, Jun 22, 2026 at 01:34:39PM -0500, Frank Li wrote: > > > > > On Mon, Jun 22, 2026 at 05:09:10PM +0100, Nuno Sá wrote: > > > > > > On Mon, Jun 22, 2026 at 09:51:46AM -0500, Frank Li wrote: > > > > > > > On Mon, Jun 22, 2026 at 10:26:41AM +0100, Nuno Sá wrote: > > > > > > ... > > > > > > > > If support 4Byte, it native supportted any N*4Byte. > > > > > > > > > > So needn't bit mask to indicate all support bytes. > > > > > > > > > > > each transfer, dma_slave_cfg should set specific bus width requirement. > > > > > > > > > > > > > > If memory have requirement for 32bytes, typical cache line length for > > > > > > > hardwaer coherence transfer, it should use dmaengine_alignment. > > > > > > > > > > > > > > So I think only need set min value should be enough if fix pcm_dmaegine.c. > > > > > > > > > > > > What fix for pcm_dmaegine.c? Not sure there's anything to be fixed in > > > > > > there... The code seems to use the dma bus width to match against PCM > > > > > > formats supported and filter only the ones we can support (per dma cap). > > > > > > > > > > if cap is one byte, it should support 8, 16, 24, 32, 64 > > > > > if cap is two byte, it should support 16, 32, 64 > > > > > if cap is 4 byte, it only support 32 and 64. > > > > > > > > Well, Now I see your point but not exactly. Because we do have > > > > > > > > DMA_SLAVE_BUSWIDTH_3_BYTES > > > > > > > > and it might be used by the pcm_dmaengine code, > > > > > > > > There are also some controllers that set it. But it looks like all that > > > > set it also set 1byte. > > > > > > But this might be not true for all HW in the world. In previous reply I made > > > a comparison with MMIO accesses where not all HW that needs 1-byte read can > > > cope with that. If there is some proof that this is the case when 1-byte > > > DMA bus implies 3-bytes (or other odd number), I would like to see it. > > > > True. I'm also not too keen in making the above assumption and have no > > proof that it will work for the controllers we support. > > Okay, I think it is fine by use bitmask. suggest change name to > src_bus_widths, addr_wdiths is quite confused. Ack > > And since not much place use it. suggest change all consumers and cleanup > original u32 src_addr_widths in followup patches. > Alright! Will include all consumers conversion in followups of the initial patchset! Thx! - Nuno Sá > > > > > > - Nuno Sá > > > > > > > > > So your suggestion might still hold and work but I'm not too convinced > > > > that having the array complicates things that bad when compared with the > > > > risk of breaking existing code. > > > > > > > > Needn't mask each bit. > > > > > > -- > > > With Best Regards, > > > Andy Shevchenko > > > > > >