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Mon, 20 Jul 2026 06:41:56 -0700 (PDT) Date: Mon, 20 Jul 2026 14:43:03 +0100 From: Nuno =?utf-8?B?U8Oh?= To: Jonathan Cameron Cc: Andy Shevchenko , nuno.sa@analog.com, linux-iio@vger.kernel.org, David Lechner , Andy Shevchenko Subject: Re: [PATCH v2] iio: buffer-dmaengine: Add support for cyclic DMA transfers Message-ID: References: <20260715-iio-dma-cyclic-v2-1-268a3a28ff84@analog.com> <56f7bzba56atwu4qvgxpm4p7k347m4oqqdy3336rsy7xi3e7oq@jzoj2jtu3qu7> <20260719030057.1c1be07c@jic23-huawei> <20260719030346.6fb9670e@jic23-huawei> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20260719030346.6fb9670e@jic23-huawei> On Sun, Jul 19, 2026 at 03:03:46AM +0100, Jonathan Cameron wrote: > On Sun, 19 Jul 2026 03:00:57 +0100 > Jonathan Cameron wrote: > > > On Wed, 15 Jul 2026 19:09:42 +0300 > > Andy Shevchenko wrote: > > > > > On Wed, Jul 15, 2026 at 05:13:32PM +0200, Nuno Sá wrote: > > > > On Wed, Jul 15, 2026 at 05:23:13PM +0300, Andy Shevchenko wrote: > > > > > On Wed, Jul 15, 2026 at 01:24:53PM +0200, Nuno Sá via B4 Relay wrote: > > > > > > ... > > > > > > > > > static int iio_dmaengine_buffer_submit_block(struct iio_dma_buffer_queue *queue, > > > > > > struct iio_dma_buffer_block *block) > > > > > > > > > > > + if (block->cyclic) > > > > > > + flags = DMA_PREP_REPEAT; > > > > > > + else > > > > > > + flags = DMA_PREP_INTERRUPT; > > > > > > + > > > > > > + /* > > > > > > + * A new transfer may need to end an already active cyclic transfer > > > > > > + * before it can run, so always set the EOT flag. > > > > > > + */ > > > > > > desc = dmaengine_prep_peripheral_dma_vec(dmaengine_buffer->chan, > > > > > > vecs, nents, dma_dir, > > > > > > - DMA_PREP_INTERRUPT); > > > > > > + flags | DMA_PREP_LOAD_EOT); > > > > > > > > > > Logically I would expect this to be a separate line with the above comment. > > > > > > > > Hmm I can agree to some extent. I guess it makes sense, yes. OTOH, it´s close > > > > enough to be clear what's happening. > > > > > > Close, but not enough in my opinion. This currently is spread over pure flags > > > manipulation and API calls. > > > > > > > Anyways, can spin v3 if you feel > > > > strong about it (will anyways wait for Jonathan to take a look to make > > > > sure this the only pending concern). > > > > > > Not so strong, but lean towards my version. Let's wait for his review and > > > decide if it will be tweaked whilst applying or next version. > > > > > Applied with this tweak. Hopefully I didn't mess it up! > > I'll leave it on tree for now but I forgot to check sashiko and > it asks about plausible sounding races. Please take a look and > let me know if they are real and an update is needed: > https://sashiko.dev/#/patchset/20260715-iio-dma-cyclic-v2-1-268a3a28ff84%40analog.com " Does this check allow a non-cyclic transfer to be submitted while a cyclic transfer is already active? Since block->cyclic is false for a non-cyclic transfer, this safety check is bypassed." The above is the whole point of DMA_PREP_LOAD_EOT (so we can gracefully "terminate" a cyclic transfer) I now see that our current cap will never allow for a new cyclic to be submitted (unless we disable + enable the buffer) but I would keep things simple for now (it was also the whole point of having a cyclic cap in the first place). "If a non-cyclic file I/O transfer is submitted instead, it lacks the DMA_PREP_LOAD_EOT flag, which could cause it to hang forever while the DMA engine continuously repeats the preceding cyclic transfer." Not sure where AI got the above from. The DMA_PREP_LOAD_EOT is always set (even for the file IO based approach). So unless I'm missing nothing, I think we are fine. - Nuno Sá > > > > > diff --git a/drivers/iio/buffer/industrialio-buffer-dmaengine.c b/drivers/iio/buffer/industrialio-buffer-dmaengine.c > > index 639bac135539..ecc02a427b92 100644 > > --- a/drivers/iio/buffer/industrialio-buffer-dmaengine.c > > +++ b/drivers/iio/buffer/industrialio-buffer-dmaengine.c > > @@ -132,9 +132,10 @@ static int iio_dmaengine_buffer_submit_block(struct iio_dma_buffer_queue *queue, > > * A new transfer may need to end an already active cyclic transfer > > * before it can run, so always set the EOT flag. > > */ > > + flags |= DMA_PREP_LOAD_EOT; > > desc = dmaengine_prep_peripheral_dma_vec(dmaengine_buffer->chan, > > vecs, nents, dma_dir, > > - flags | DMA_PREP_LOAD_EOT); > > + flags); > > kfree(vecs); > > } else { > > max_size = min(block->size, dmaengine_buffer->max_size); > > > > > > > /* > > > > > * ...comment... > > > > > */ > > > > > flags |= DMA_PREP_LOAD_EOT; > > > > > ... > > > > > flags); > > > > > > > > > > > kfree(vecs); > > > > > > > >