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[92.208.247.184]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-52fbe850864sm73241871cf.26.2026.08.31.08.20.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 31 Aug 2026 08:20:09 -0700 (PDT) Message-ID: Date: Mon, 31 Aug 2026 17:20:04 +0200 Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 05/20] iio: adc: Add AD7768 and AD7768-4 core support To: Andy Shevchenko , Janani Sunil Cc: =?UTF-8?Q?Nuno_S=C3=A1?= , Michael Hennerich , Jonathan Cameron , David Lechner , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan , Philipp Zabel , Linus Walleij , Bartosz Golaszewski , Jonathan Corbet , Shuah Khan , Michael Walle , linux@analog.com, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-doc@vger.kernel.org, =?UTF-8?Q?Uwe_Kleine-K=C3=B6nig?= References: <20260828-ad7768-driver-v5-0-e33ca6f841a2@analog.com> <20260828-ad7768-driver-v5-5-e33ca6f841a2@analog.com> Content-Language: en-US From: Janani Sunil In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 8/31/26 11:04, Andy Shevchenko wrote: > On Fri, Aug 28, 2026 at 05:30:28PM +0200, Janani Sunil wrote: >> Add core support for the AD7768 and AD7768-4 simultaneous sampling ADCs. >> Configure supplies, clock and reset, use a custom regmap bus for the SPI >> protocol, and parse the enabled channels and input buffer settings from >> devicetree. >> >> Connect the converter to an IIO backend for buffered capture with CRC, >> provide a fixed safe wideband sampling configuration and add runtime >> power management. > ... > > + ret = regmap_update_bits(st->regmap, AD7768_REG_CH_MODE(0), > + AD7768_CH_MODE_FILTER_TYPE_MSK | > + AD7768_CH_MODE_DEC_RATE_MSK, > + mode_config); > + if (ret) > + return ret; > + > + ret = regmap_write(st->regmap, AD7768_REG_CH_MODE_SEL, 0); > + if (ret) > + return ret; > + > + dclk_div = 8 * st->datalines / st->chip_info->num_channels; > Does 8 represent BITS_PER_BYTE? Can BITS_TO_BYTES() be used? 8 is not BITS_PER_BYTE. With fast mode (fMOD = MCLK / 4) and ×64 decimation, this gives: MCLK / DCLK = (4 × 64 / 32) × data lines / channels Therefore, the factor is 8. I will add a comment explaining this. Best Regards, Jan