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Thu, 18 Dec 2025 05:43:02 -0800 (PST) Received: from [10.5.0.2] ([45.94.208.108]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b802350db89sm233624166b.63.2025.12.18.05.43.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Dec 2025 05:43:02 -0800 (PST) Message-ID: Subject: Re: [PATCH 1/2] iio: adc: ad9467: include two's complement in default mode From: Nuno =?ISO-8859-1?Q?S=E1?= To: Tomas Melin , Michael Hennerich , Nuno Sa , Lars-Peter Clausen , Jonathan Cameron , David Lechner , Andy Shevchenko Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Date: Thu, 18 Dec 2025 13:43:43 +0000 In-Reply-To: <20251216-b4-ad9467-optional-backend-v1-1-83e61531ef4d@vaisala.com> References: <20251216-b4-ad9467-optional-backend-v1-0-83e61531ef4d@vaisala.com> <20251216-b4-ad9467-optional-backend-v1-1-83e61531ef4d@vaisala.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.58.2 Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Tue, 2025-12-16 at 11:40 +0000, Tomas Melin wrote: > All supported drivers currently implicitly use two's complement mode. > Make this clear by declaring two's complement in the default > output mode. Calibration mode uses offset binary, so change the output > mode only when running the calibration or other test mode. >=20 > Signed-off-by: Tomas Melin > --- Reviewed-by: Nuno S=C3=A1 > =C2=A0drivers/iio/adc/ad9467.c | 33 +++++++++++++++++++++++++-------- > =C2=A01 file changed, 25 insertions(+), 8 deletions(-) >=20 > diff --git a/drivers/iio/adc/ad9467.c b/drivers/iio/adc/ad9467.c > index 59c3fa3bcc9b0b8b36b78c3b54fd7977cae23496..60fc3361b2689a4c38287c613= ef93fe00338e5fa 100644 > --- a/drivers/iio/adc/ad9467.c > +++ b/drivers/iio/adc/ad9467.c > @@ -72,6 +72,7 @@ > =C2=A0#define AN877_ADC_OUTPUT_MODE_OFFSET_BINARY 0x0 > =C2=A0#define AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT 0x1 > =C2=A0#define AN877_ADC_OUTPUT_MODE_GRAY_CODE 0x2 > +#define AN877_ADC_OUTPUT_MODE_MASK GENMASK(1, 0) > =C2=A0 > =C2=A0/* AN877_ADC_REG_OUTPUT_PHASE */ > =C2=A0#define AN877_ADC_OUTPUT_EVEN_ODD_MODE_EN 0x20 > @@ -85,7 +86,7 @@ > =C2=A0 */ > =C2=A0 > =C2=A0#define CHIPID_AD9211 0x06 > -#define AD9211_DEF_OUTPUT_MODE 0x00 > +#define AD9211_DEF_OUTPUT_MODE 0x01 > =C2=A0#define AD9211_REG_VREF_MASK GENMASK(4, 0) > =C2=A0 > =C2=A0/* > @@ -93,7 +94,7 @@ > =C2=A0 */ > =C2=A0 > =C2=A0#define CHIPID_AD9265 0x64 > -#define AD9265_DEF_OUTPUT_MODE 0x40 > +#define AD9265_DEF_OUTPUT_MODE 0x41 > =C2=A0#define AD9265_REG_VREF_MASK 0xC0 > =C2=A0 > =C2=A0/* > @@ -101,7 +102,7 @@ > =C2=A0 */ > =C2=A0 > =C2=A0#define CHIPID_AD9434 0x6A > -#define AD9434_DEF_OUTPUT_MODE 0x00 > +#define AD9434_DEF_OUTPUT_MODE 0x01 > =C2=A0#define AD9434_REG_VREF_MASK 0xC0 > =C2=A0 > =C2=A0/* > @@ -109,7 +110,7 @@ > =C2=A0 */ > =C2=A0 > =C2=A0#define CHIPID_AD9467 0x50 > -#define AD9467_DEF_OUTPUT_MODE 0x08 > +#define AD9467_DEF_OUTPUT_MODE 0x09 > =C2=A0#define AD9467_REG_VREF_MASK 0x0F > =C2=A0 > =C2=A0/* > @@ -117,6 +118,7 @@ > =C2=A0 */ > =C2=A0 > =C2=A0#define CHIPID_AD9643 0x82 > +#define AD9643_DEF_OUTPUT_MODE 0x01 > =C2=A0#define AD9643_REG_VREF_MASK 0x1F > =C2=A0 > =C2=A0/* > @@ -124,6 +126,7 @@ > =C2=A0 */ > =C2=A0 > =C2=A0#define CHIPID_AD9652=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0xC1 > +#define AD9652_DEF_OUTPUT_MODE 0x01 > =C2=A0#define AD9652_REG_VREF_MASK=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 0xC0 > =C2=A0 > =C2=A0/* > @@ -131,6 +134,7 @@ > =C2=A0 */ > =C2=A0 > =C2=A0#define CHIPID_AD9649 0x6F > +#define AD9649_DEF_OUTPUT_MODE 0x01 > =C2=A0#define AD9649_TEST_POINTS 8 > =C2=A0 > =C2=A0#define AD9647_MAX_TEST_POINTS 32 > @@ -461,6 +465,7 @@ static const struct ad9467_chip_info ad9643_chip_tbl = =3D { > =C2=A0 .test_mask =3D BIT(AN877_ADC_TESTMODE_RAMP) | > =C2=A0 GENMASK(AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY, AN877_ADC_TESTMOD= E_OFF), > =C2=A0 .test_mask_len =3D AN877_ADC_TESTMODE_RAMP + 1, > + .default_output_mode =3D AD9643_DEF_OUTPUT_MODE, > =C2=A0 .vref_mask =3D AD9643_REG_VREF_MASK, > =C2=A0 .has_dco =3D true, > =C2=A0 .has_dco_invert =3D true, > @@ -479,6 +484,7 @@ static const struct ad9467_chip_info ad9649_chip_tbl = =3D { > =C2=A0 .test_mask =3D GENMASK(AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY, > =C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0 AN877_ADC_TESTMODE_OFF), > =C2=A0 .test_mask_len =3D AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY + 1, > + .default_output_mode =3D AD9649_DEF_OUTPUT_MODE, > =C2=A0 .has_dco =3D true, > =C2=A0 .has_dco_invert =3D true, > =C2=A0 .dco_en =3D AN877_ADC_DCO_DELAY_ENABLE, > @@ -496,6 +502,7 @@ static const struct ad9467_chip_info ad9652_chip_tbl = =3D { > =C2=A0 .test_mask =3D GENMASK(AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE, > =C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0 AN877_ADC_TESTMODE_OFF), > =C2=A0 .test_mask_len =3D AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE + 1, > + .default_output_mode =3D AD9652_DEF_OUTPUT_MODE, > =C2=A0 .vref_mask =3D AD9652_REG_VREF_MASK, > =C2=A0 .has_dco =3D true, > =C2=A0}; > @@ -671,10 +678,14 @@ static int ad9467_backend_testmode_off(struct ad946= 7_state *st, > =C2=A0 > =C2=A0static int ad9647_calibrate_prepare(struct ad9467_state *st) > =C2=A0{ > + unsigned int cmode; > =C2=A0 unsigned int c; > =C2=A0 int ret; > =C2=A0 > - ret =3D ad9467_outputmode_set(st, st->info->default_output_mode); > + cmode =3D (st->info->default_output_mode & ~AN877_ADC_OUTPUT_MODE_MASK)= | > + FIELD_PREP(AN877_ADC_OUTPUT_MODE_MASK, > + =C2=A0=C2=A0 AN877_ADC_OUTPUT_MODE_OFFSET_BINARY); > + ret =3D ad9467_outputmode_set(st, cmode); > =C2=A0 if (ret) > =C2=A0 return ret; > =C2=A0 > @@ -778,7 +789,7 @@ static int ad9647_calibrate_stop(struct ad9467_state = *st) > =C2=A0 return ret; > =C2=A0 } > =C2=A0 > - mode =3D st->info->default_output_mode | AN877_ADC_OUTPUT_MODE_TWOS_COM= PLEMENT; > + mode =3D st->info->default_output_mode; > =C2=A0 return ad9467_outputmode_set(st, mode); > =C2=A0} > =C2=A0 > @@ -1174,12 +1185,18 @@ static ssize_t ad9467_chan_test_mode_write(struct= file *file, > =C2=A0 if (ret) > =C2=A0 return ret; > =C2=A0 > - out_mode =3D st->info->default_output_mode | AN877_ADC_OUTPUT_MODE_TWO= S_COMPLEMENT; > + out_mode =3D st->info->default_output_mode; > =C2=A0 ret =3D ad9467_outputmode_set(st, out_mode); > =C2=A0 if (ret) > =C2=A0 return ret; > =C2=A0 } else { > - ret =3D ad9467_outputmode_set(st, st->info->default_output_mode); > + unsigned int cmode; > + > + cmode =3D (st->info->default_output_mode & > + ~AN877_ADC_OUTPUT_MODE_MASK) | > + FIELD_PREP(AN877_ADC_OUTPUT_MODE_MASK, > + =C2=A0=C2=A0 AN877_ADC_OUTPUT_MODE_OFFSET_BINARY); > + ret =3D ad9467_outputmode_set(st, cmode); > =C2=A0 if (ret) > =C2=A0 return ret; > =C2=A0