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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b6cfa6cb6e6sm404145466b.49.2025.10.22.04.02.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 22 Oct 2025 04:02:07 -0700 (PDT) Message-ID: Date: Wed, 22 Oct 2025 13:02:02 +0200 Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V7 3/5] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC To: Krzysztof Kozlowski , Jishnu Prakash , Krzysztof Kozlowski Cc: Jonathan Cameron , robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, agross@kernel.org, andersson@kernel.org, lumag@kernel.org, dmitry.baryshkov@oss.qualcomm.com, konradybcio@kernel.org, daniel.lezcano@linaro.org, sboyd@kernel.org, amitk@kernel.org, thara.gopinath@gmail.com, lee@kernel.org, rafael@kernel.org, subbaraman.narayanamurthy@oss.qualcomm.com, david.collins@oss.qualcomm.com, anjelique.melendez@oss.qualcomm.com, kamal.wadhwa@oss.qualcomm.com, rui.zhang@intel.com, lukasz.luba@arm.com, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, cros-qcom-dts-watchers@chromium.org, quic_kotarake@quicinc.com, neil.armstrong@linaro.org, stephan.gerhold@linaro.org, Jonathan Cameron References: <20250826083657.4005727-1-jishnu.prakash@oss.qualcomm.com> <20250826083657.4005727-4-jishnu.prakash@oss.qualcomm.com> <20250829-classic-dynamic-clam-addbd8@kuoka> <5d662148-408f-49e1-a769-2a5d61371cae@oss.qualcomm.com> <4e974e77-adfc-49e5-90c8-cf8996ded513@kernel.org> <8c90cc3f-115e-4362-9293-05d9bee24214@linaro.org> <5d4edecf-51f3-4d4a-861f-fce419e3a314@oss.qualcomm.com> <20250927144757.4d36d5c8@jic23-huawei> <31bd08ce-823a-4a71-baca-a9d1e02fcb6a@oss.qualcomm.com> <08eb477f-ea34-4a31-b181-bfc629aef4c8@kernel.org> <68a9b8e8-bdf4-430f-baef-6a293ccea78d@oss.qualcomm.com> <3a32746a-5b0e-4c0a-8322-00cd3a84394a@oss.qualcomm.com> <4979bd26-0a77-4390-9db2-6d40cd7f963c@kernel.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <4979bd26-0a77-4390-9db2-6d40cd7f963c@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDIwMDE0OCBTYWx0ZWRfX6wLA83nhRHk2 m1JnzcG52WcPfWb+ts/BKTsLJz0d77hOdqtJVNVWy1qJaORjecDplX3LZCL4js0n7GpSZzd8QJO fVbTFLjFHf9y3/x57YiW+ZWl+6nUJUddAXBOFPjmL/7W0MsaAnLVqDi+anpeGAGEKe+R2frp4cS vT6tqUPwDXJTdJyrR26SXIqWwI35YaKBAdIkl+/+VtIwjxtnUo2tLUhu8+jqS2BM3Cx+uP7ToPg YLQZRsoQ9DLPKdP0uFGqCIbazOOOQ/25raH66vEG8GMvVaOgYg+Gte2vG18wE8xa2aOP7a5t5ad qo/iXHxVWomWIoCq1TqdXFGdXTz1csZgEEZoaGU+RM8dHM/t7xL5vQUE6uPxadat2G5iLCfhZzh tKQuzekmPaAJacfS0hTg/cr5KMSpNw== X-Proofpoint-GUID: h0w-NR8rYJJoJdL0Os9m531f5TcKHp7s X-Proofpoint-ORIG-GUID: h0w-NR8rYJJoJdL0Os9m531f5TcKHp7s X-Authority-Analysis: v=2.4 cv=a+E9NESF c=1 sm=1 tr=0 ts=68f8b9b2 cx=c_pps a=P2rfLEam3zuxRRdjJWA2cw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=lSOnRjTSg1CY54VbDlwA:9 a=QEXdDO2ut3YA:10 a=ODZdjJIeia2B_SHc_B0f:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-22_04,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 clxscore=1015 priorityscore=1501 phishscore=0 bulkscore=0 suspectscore=0 malwarescore=0 impostorscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510200148 On 20-Oct-25 17:55, Krzysztof Kozlowski wrote: > On 20/10/2025 14:51, Konrad Dybcio wrote: >> On 10/17/25 3:40 PM, Krzysztof Kozlowski wrote: >>> On 17/10/2025 13:18, Jishnu Prakash wrote: >>>> Hi Krzysztof, >>>> >>>> On 10/9/2025 5:22 AM, Krzysztof Kozlowski wrote: >>>>> On 08/10/2025 23:20, Jishnu Prakash wrote: >>>>>> Hi Krzysztof, >>>>>> >>>>>> On 10/4/2025 12:22 PM, Krzysztof Kozlowski wrote: >>>>>>> On Sat, 4 Oct 2025 at 11:42, Jishnu Prakash >>>>>>> wrote: >>>>>>>> >>>>>>>> Hi Jonathan, >>>>>>>> >>>>>>>> On 9/27/2025 7:17 PM, Jonathan Cameron wrote: >>>>>>>>> On Fri, 19 Sep 2025 20:17:43 +0530 >>>>>>>>> Jishnu Prakash wrote: >> >> [...] >> >>>> Can you please provide your suggestions on changes we can make >>>> in the above points ? >>> >>> You just pasted DT. I asked about SW, software. Please read carefully >>> previous comments. >> >> Is the problem that Jishnu included some indices in dt-bindings without >> also adding them in the driver's adc5_gen3_chans_pmic[] array? >> >> As in, would the resolution to this thread be simply handling all of >> them in the driver correctly? > > The solution is to remove them from the bindings, just like we do with > many other hardware constants. Of course if these are not hardware > constants, but part of ABI, then solution would be different but no one > provided proof or argument that this is any binding. All proofs were > "but I want to use it in my DTS", which proofs nothing. Not a binding. > > While this issue is not that important, we keep discussing it because > author does not try to understand the problem or even keep up the > discussion. Instead repeats the same without really reading my > messages... and then disappears for month or more. In Bulgaria, people shake their heads left to right to say "yes", and up&down to say "no" (or so I've heard).. I feel like we're having a similar situation here.. I'll try to make a case for keeping these defines in some form. Here's hopefully all the related aspects, condensed down: 1. In a multi-PMIC setup, only the main PMIC's ADC is accessible by the OS. It then mediates accesses to secondary PMICs' ADCs through internal mechanisms, which requires the SID of the target to be retrieved and written to a register, along with the physical index of the desired channel to be measured (see patch 3/5 commit msg). 2. The PMIC SIDs are fixed per board and are the values of PMIC top-level nodes' reg property (since forever) 3. The channel indices are fixed in HW, but this patchset proposed to reuse them for logical mappings consumed through io-channels = <> as well (because of 1.), with the drivers taking the lower 8 bits that of reg/io-channels[1] value as the ADC channel id and the higher 8 bits as the SID (this is the define macros with an argument) 4. Fixing 3. in a "simply define all possible options and bind them to consecutive integers" fashion would require a huge table matching 0..n to [0-max_sid][0-max_chan] which is unreasonable The alternative to the SID packing would be to reference the target PMIC somehow, be it by referencing the PMIC itself: io-channels = <&pm8550_adc &pmr735a CHANNEL_XYZ> or by creating a faux node for the actual inaccessible ADC onboard each of the PMICs: io-channels = <&pm8550_adc &pmr735a_adc CHANNEL_XYZ> and have the OS retrieve the SID from the DT node & encode that value instead of hardcoding it in the DT, leaving just the actual channel IDs in dt-bindings. The define macros without an argument do specify physical channel indices, but we do need some sort of an identifier to put into io-channels (which is why this lives in dt-bindings in the first place), and a 1:1 mapping to the physical id sounds like a good option. I don't think anyone objects to any of these resolutions, so long as they are acceptable from your side Konrad