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([2a10:a5c0:800d:dd00:8fdf:935a:2c85:d703]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-549ba864f9bsm1261696e87.153.2025.03.17.01.33.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 17 Mar 2025 01:33:37 -0700 (PDT) Message-ID: Date: Mon, 17 Mar 2025 10:33:36 +0200 Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 06/10] iio: adc: Support ROHM BD79124 ADC To: Andy Shevchenko Cc: Matti Vaittinen , Jonathan Cameron , Lars-Peter Clausen , Nuno Sa , David Lechner , Javier Carrasco , Olivier Moysan , Guillaume Stols , Dumitru Ceclan , Trevor Gamblin , Matteo Martelli , Alisa-Dariana Roman , =?UTF-8?Q?Jo=C3=A3o_Paulo_Gon=C3=A7alves?= , AngeloGioacchino Del Regno , linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org References: <0d7b37fd-be93-42d7-9610-d2184c601981@gmail.com> Content-Language: en-US, en-AU, en-GB, en-BW From: Matti Vaittinen In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 17/03/2025 09:57, Andy Shevchenko wrote: > On Mon, Mar 17, 2025 at 09:07:30AM +0200, Matti Vaittinen wrote: >> On 14/03/2025 16:37, Andy Shevchenko wrote: >>> On Fri, Mar 14, 2025 at 11:22:37AM +0200, Matti Vaittinen wrote: > > ... > >>> Okay, it seems I misinterpreted the values you have in regmap configuration, >>> I was under the impression that regmap is 16-bit data, but it is about address. >>> >>> So, we need to know why the heck HW has sparse registers >> >> We don't know. And we really don't even need to know it. We can just use >> this device knowing there are some. > > Don't you have a channel to ask HW engineers about this? Let's just say that ROHM is, while not huge, still rather large company. I'm located far away from the HQ, I speak different language and I am from very different cultural background. So, while there are some channels, it is not always easy, clever of possible to ask (not to mention getting answers to) "why this way" - questions :) >>> for what is supposed >>> to be sequential. This needs a good comment. >> >> I think it is quite usual that devices contain undocumented registers. Not >> sure having a comment that this device also has some, adds much of value? I >> suppose I can add a comment that we can't use bulk_write because registers >> aren't in subsequent addresses - but having just removed bunch of >> unnecessary comments from the code (as requested), I'm not sure adding this >> one really improves situation... When one sees separate reads/writes for >> data spread to multiple registers, he is likely to assume addresses aren't >> subsequent. > > From HW design perspective it's silly to sparse hi and lo part of > the semantically same entity. So, either the (undocumented) register > is also part of the soup, or the registers have different semantics. Or, the designer has not thought how software would be doing the reads. Or, this design has originated from a design done for a very specific purpose, which, we don't know of. > This what needs to be commented in my opinion. Yours, -- Matti