Re: [PATCH v8 4/8] iio: dac: adi-axi-dac: extend features

["Nuno Sá" <noname.nuno@gmail.com>]

On Fri, 2024-10-25 at 11:49 +0200, Angelo Dureghello wrote:
> From: Angelo Dureghello <adureghello@baylibre.com>
> 
> Extend AXI-DAC backend with new features required to interface
> to the ad3552r DAC. Mainly, a new compatible string is added to
> support the ad3552r-axi DAC IP, very similar to the generic DAC
> IP but with some customizations to work with the ad3552r.
> 
> Then, a series of generic functions has been added to match with
> ad3552r needs. Function names has been kept generic as much as
> possible, to allow re-utilization from other frontend drivers.
> 
> Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
> ---
>  drivers/iio/dac/adi-axi-dac.c | 244 +++++++++++++++++++++++++++++++++++++++---
>  1 file changed, 230 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/iio/dac/adi-axi-dac.c b/drivers/iio/dac/adi-axi-dac.c
> index 04193a98616e..148e40a8ab2a 100644
> --- a/drivers/iio/dac/adi-axi-dac.c
> +++ b/drivers/iio/dac/adi-axi-dac.c
> @@ -46,9 +46,28 @@
>  #define AXI_DAC_CNTRL_1_REG			0x0044
>  #define   AXI_DAC_CNTRL_1_SYNC			BIT(0)
>  #define AXI_DAC_CNTRL_2_REG			0x0048
> +#define   AXI_DAC_CNTRL_2_SDR_DDR_N		BIT(16)
> +#define   AXI_DAC_CNTRL_2_SYMB_8B		BIT(14)
>  #define   ADI_DAC_CNTRL_2_R1_MODE		BIT(5)
> +#define   AXI_DAC_CNTRL_2_UNSIGNED_DATA		BIT(4)
> +#define AXI_DAC_STATUS_1_REG			0x0054
> +#define AXI_DAC_STATUS_2_REG			0x0058
>  #define AXI_DAC_DRP_STATUS_REG			0x0074
>  #define   AXI_DAC_DRP_STATUS_DRP_LOCKED		BIT(17)
> +#define AXI_DAC_CUSTOM_RD_REG			0x0080
> +#define AXI_DAC_CUSTOM_WR_REG			0x0084
> +#define   AXI_DAC_CUSTOM_WR_DATA_8		GENMASK(23, 16)
> +#define   AXI_DAC_CUSTOM_WR_DATA_16		GENMASK(23, 8)
> +#define AXI_DAC_UI_STATUS_REG			0x0088
> +#define   AXI_DAC_UI_STATUS_IF_BUSY		BIT(4)
> +#define AXI_DAC_CUSTOM_CTRL_REG			0x008C
> +#define   AXI_DAC_CUSTOM_CTRL_ADDRESS		GENMASK(31, 24)
> +#define   AXI_DAC_CUSTOM_CTRL_SYNCED_TRANSFER	BIT(2)
> +#define   AXI_DAC_CUSTOM_CTRL_STREAM		BIT(1)
> +#define   AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA	BIT(0)

...

> 
> +
> +static int axi_dac_bus_reg_write(struct iio_backend *back, u32 reg, u32 val,
> +				 size_t data_size)
> +{
> +	struct axi_dac_state *st = iio_backend_get_priv(back);
> +	int ret;
> +	u32 ival;
> +
> +	/*
> +	 * Both AXI_DAC_CNTRL_2_REG and AXI_DAC_CUSTOM_WR_REG need to know
> +	 * the data size. So keeping data size control here only,
> +	 * since data size is mandatory for the current transfer.
> +	 * DDR state handled separately by specific backend calls,
> +	 * generally all raw register writes are SDR.
> +	 */
> +	if (data_size == sizeof(u16))
> +		ival = FIELD_PREP(AXI_DAC_CUSTOM_WR_DATA_16, val);
> +	else
> +		ival = FIELD_PREP(AXI_DAC_CUSTOM_WR_DATA_8, val);
> +
> +	ret = regmap_write(st->regmap, AXI_DAC_CUSTOM_WR_REG, ival);
> +	if (ret)
> +		return ret;
> +
> +	if (data_size == sizeof(u8))
> +		ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_2_REG,
> +				      AXI_DAC_CNTRL_2_SYMB_8B);
> +	else
> +		ret = regmap_clear_bits(st->regmap, AXI_DAC_CNTRL_2_REG,
> +					AXI_DAC_CNTRL_2_SYMB_8B);
> +	if (ret)
> +		return ret;
> +
> +	ret = regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG,
> +				 AXI_DAC_CUSTOM_CTRL_ADDRESS,
> +				 FIELD_PREP(AXI_DAC_CUSTOM_CTRL_ADDRESS, reg));
> +	if (ret)
> +		return ret;
> +
> +	ret = regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG,
> +				 AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA,
> +				 AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA);
> +	if (ret)
> +		return ret;
> +
> +	ret = regmap_read_poll_timeout(st->regmap,
> +				AXI_DAC_UI_STATUS_REG, ival,
> +				FIELD_GET(AXI_DAC_UI_STATUS_IF_BUSY, ival) == 0,
> +				10, 100 * KILO);
> +	if (ret == -ETIMEDOUT)
> +		dev_err(st->dev, "AXI read timeout\n");
> +
> +	/* Cleaning always AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA */
> +	return regmap_clear_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG,
> +				 AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA);
> +}
> +
> +static int axi_dac_bus_reg_read(struct iio_backend *back, u32 reg, u32 *val,
> +				size_t data_size)
> +{
> +	struct axi_dac_state *st = iio_backend_get_priv(back);
> +	int ret;
> +
> +	/*
> +	 * SPI, we write with read flag, then we read just at the AXI
> +	 * io address space to get data read.
> +	 */
> +	ret = axi_dac_bus_reg_write(back, AXI_DAC_RD_ADDR(reg), 0, data_size);
> +	if (ret)
> +		return ret;
> +
> +	return regmap_read(st->regmap, AXI_DAC_CUSTOM_RD_REG, val);
> +}

Just noticed now that both reg_read() and reg_write() should use the lock. That meas
having an unlocked helper of reg_write. Other than that, LGTM.

- Nuno Sá