From mboxrd@z Thu Jan  1 00:00:00 1970
From: David Brownell <david-b@pacbell.net>
Subject: Re: [PATCH] ads7846: allocate separate cache lines for tx and rx data
Date: Thu, 16 Jul 2009 01:35:51 -0700
Message-ID: <200907160135.51307.david-b@pacbell.net>
References: <200907160051.04506.david-b@pacbell.net> <20090715193326.GA13306@mail.gnudd.com> <20090716081527.GA29374@mail.gnudd.com>
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To: Alessandro Rubini <rubini-list@gnudd.com>
Cc: linux-input@vger.kernel.org, linux@arm.linux.org.uk, linux-arm-kernel@lists.arm.linux.org.uk

On Thursday 16 July 2009, Alessandro Rubini wrote:
> > Note that this issue is unrelated to full duplex DMA support.
> 
> Yes, that's right. But full duplex is not involved here, it's
> just 2 or 3 rounds of "one byte tx then two bytes rx".

Then your patch description was *seriously* misleading:

> > > Since the SPI master might use DMA, tx and rx buffers must live on
> > > different cache lines. ...

I'll have another look at that patch to see if it could make
sense after I discard the description.

- dave