* [PATCH v4 1/8] dt-bindings: arm: fsl: Add various solidrun i.mx8m boards
2025-12-01 13:07 [PATCH v4 0/8] arm64: dts: add description for solidrun imx8mp hummingboard-iiot Josua Mayer
@ 2025-12-01 13:07 ` Josua Mayer
2025-12-01 13:07 ` [PATCH v4 2/8] Input: ilitek_ts_i2c: fix warning with gpio controllers that sleep Josua Mayer
` (6 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Josua Mayer @ 2025-12-01 13:07 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Dmitry Torokhov, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam
Cc: Jon Nettleton, Mikhail Anikin, Yazan Shhady, devicetree,
linux-kernel, linux-input, imx, linux-arm-kernel, Josua Mayer,
Krzysztof Kozlowski
Add bindings for various SolidRun boards:
- i.MX8MP HummingBoard IIoT - based on the SolidRun i.MX8M Plus SoM
- SolidSense N8 - single-board design with i.MX8M Nano
- i.MX8M Mini System on Module
- i.MX8M Mini HummingBoard Ripple
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
Documentation/devicetree/bindings/arm/fsl.yaml | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 00cdf490b0620..f70b933ce3746 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -1041,6 +1041,13 @@ properties:
- const: phytec,imx8mm-phycore-som # phyCORE-i.MX8MM SoM
- const: fsl,imx8mm
+ - description: SolidRun i.MX8MM SoM based boards
+ items:
+ - enum:
+ - solidrun,imx8mm-hummingboard-ripple # SolidRun i.MX8MM SoM on HummingBoard Ripple
+ - const: solidrun,imx8mm-sr-som
+ - const: fsl,imx8mm
+
- description: Variscite VAR-SOM-MX8MM based boards
items:
- const: variscite,var-som-mx8mm-symphony
@@ -1069,6 +1076,7 @@ properties:
- fsl,imx8mn-ddr4-evk # i.MX8MN DDR4 EVK Board
- fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board
- gw,imx8mn-gw7902 # i.MX8MM Gateworks Board
+ - solidrun,solidsense-n8-compact # SolidRun SolidSense N8 Compact
- const: fsl,imx8mn
- description: Variscite VAR-SOM-MX8MN based boards
@@ -1205,6 +1213,7 @@ properties:
items:
- enum:
- solidrun,imx8mp-cubox-m # SolidRun i.MX8MP SoM on CuBox-M
+ - solidrun,imx8mp-hummingboard-iiot # SolidRun i.MX8MP SoM on HummingBoard IIoT
- solidrun,imx8mp-hummingboard-mate # SolidRun i.MX8MP SoM on HummingBoard Mate
- solidrun,imx8mp-hummingboard-pro # SolidRun i.MX8MP SoM on HummingBoard Pro
- solidrun,imx8mp-hummingboard-pulse # SolidRun i.MX8MP SoM on HummingBoard Pulse
--
2.51.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v4 2/8] Input: ilitek_ts_i2c: fix warning with gpio controllers that sleep
2025-12-01 13:07 [PATCH v4 0/8] arm64: dts: add description for solidrun imx8mp hummingboard-iiot Josua Mayer
2025-12-01 13:07 ` [PATCH v4 1/8] dt-bindings: arm: fsl: Add various solidrun i.mx8m boards Josua Mayer
@ 2025-12-01 13:07 ` Josua Mayer
2025-12-01 13:07 ` [PATCH v4 3/8] arm64: dts: imx8mp-hummingboard-pulse/cubox-m: fix vmmc gpio polarity Josua Mayer
` (5 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Josua Mayer @ 2025-12-01 13:07 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Dmitry Torokhov, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam
Cc: Jon Nettleton, Mikhail Anikin, Yazan Shhady, devicetree,
linux-kernel, linux-input, imx, linux-arm-kernel, Josua Mayer
The ilitek touchscreen driver uses the non-sleeping gpiod_set_value
function for reset.
Switch to using gpiod_set_value_cansleep() when controlling reset_gpio to
support GPIO providers that may sleep, such as I2C GPIO expanders.
Further switch the mdelay calls on the reset path to fsleep (preferred
in non-atomic contexts).
This fixes noisy complaints in kernel log for gpio providers that do
sleep.
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
drivers/input/touchscreen/ilitek_ts_i2c.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/input/touchscreen/ilitek_ts_i2c.c b/drivers/input/touchscreen/ilitek_ts_i2c.c
index 0dd632724a003..10e5530d6a5d0 100644
--- a/drivers/input/touchscreen/ilitek_ts_i2c.c
+++ b/drivers/input/touchscreen/ilitek_ts_i2c.c
@@ -396,10 +396,10 @@ static const struct ilitek_protocol_map ptl_func_map[] = {
static void ilitek_reset(struct ilitek_ts_data *ts, int delay)
{
if (ts->reset_gpio) {
- gpiod_set_value(ts->reset_gpio, 1);
- mdelay(10);
- gpiod_set_value(ts->reset_gpio, 0);
- mdelay(delay);
+ gpiod_set_value_cansleep(ts->reset_gpio, 1);
+ fsleep(10000);
+ gpiod_set_value_cansleep(ts->reset_gpio, 0);
+ fsleep(delay * 1000);
}
}
--
2.51.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v4 3/8] arm64: dts: imx8mp-hummingboard-pulse/cubox-m: fix vmmc gpio polarity
2025-12-01 13:07 [PATCH v4 0/8] arm64: dts: add description for solidrun imx8mp hummingboard-iiot Josua Mayer
2025-12-01 13:07 ` [PATCH v4 1/8] dt-bindings: arm: fsl: Add various solidrun i.mx8m boards Josua Mayer
2025-12-01 13:07 ` [PATCH v4 2/8] Input: ilitek_ts_i2c: fix warning with gpio controllers that sleep Josua Mayer
@ 2025-12-01 13:07 ` Josua Mayer
2025-12-01 13:07 ` [PATCH v4 4/8] arm64: dts: imx8mp-hummingboard-pulse: fix mini-hdmi dsi port reference Josua Mayer
` (4 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Josua Mayer @ 2025-12-01 13:07 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Dmitry Torokhov, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam
Cc: Jon Nettleton, Mikhail Anikin, Yazan Shhady, devicetree,
linux-kernel, linux-input, imx, linux-arm-kernel, Josua Mayer
Fix the polarity in vmmc regulator node for the gpio from active-high to
active-low. This is a cosmetic change as regulator default to active-low
unless property enable-active-high was also specified - ignoring the
flag on gpio handle.
Fixes: a009c0c66ecb ("arm64: dts: add description for solidrun imx8mp som and cubox-m")
Fixes: 2a222aa2bee9 ("arm64: dts: add description for solidrun imx8mp hummingboard variants")
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts | 2 +-
arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts b/arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts
index 8290f187b79fd..7bc213499f094 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts
@@ -68,7 +68,7 @@ vmmc: regulator-mmc {
regulator-name = "vmmc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio2 19 GPIO_ACTIVE_LOW>;
startup-delay-us = <250>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi
index 825ad6a2ba14e..5b8c8489713c4 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi
@@ -73,7 +73,7 @@ vmmc: regulator-mmc {
regulator-name = "vmmc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio2 19 GPIO_ACTIVE_LOW>;
startup-delay-us = <250>;
};
--
2.51.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v4 4/8] arm64: dts: imx8mp-hummingboard-pulse: fix mini-hdmi dsi port reference
2025-12-01 13:07 [PATCH v4 0/8] arm64: dts: add description for solidrun imx8mp hummingboard-iiot Josua Mayer
` (2 preceding siblings ...)
2025-12-01 13:07 ` [PATCH v4 3/8] arm64: dts: imx8mp-hummingboard-pulse/cubox-m: fix vmmc gpio polarity Josua Mayer
@ 2025-12-01 13:07 ` Josua Mayer
2025-12-01 13:07 ` [PATCH v4 5/8] arm64: dts: imx8mp-sr-som: build dtbs with symbols for overlay support Josua Mayer
` (3 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Josua Mayer @ 2025-12-01 13:07 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Dmitry Torokhov, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam
Cc: Jon Nettleton, Mikhail Anikin, Yazan Shhady, devicetree,
linux-kernel, linux-input, imx, linux-arm-kernel, Josua Mayer
imx8mp.dtsi includes a default port@1 node with an empty placeholder
endpoint intended for linking to a dsi bridge or panel.
HummingBoard Pulse mini-hdmi dtsi added and linked hdmi brodge to yet
another endpoint.
This duplicate endpoint can cause dsi_attach to fail.
Remove the duplicate node and link to the one defined in soc dtsi.
Further remove the unnecessary attach-bridge property.
Fixes: 2a222aa2bee9 ("arm64: dts: add description for solidrun imx8mp hummingboard variants")
Signed-off-by Josua Mayer <josua@solid-run.com>
---
.../dts/freescale/imx8mp-hummingboard-pulse-mini-hdmi.dtsi | 11 ++++-------
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-mini-hdmi.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-mini-hdmi.dtsi
index 46916ddc05335..0e5f4607c7c1b 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-mini-hdmi.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-mini-hdmi.dtsi
@@ -41,7 +41,7 @@ port@0 {
reg = <0>;
adv7535_from_dsim: endpoint {
- remote-endpoint = <&dsim_to_adv7535>;
+ remote-endpoint = <&mipi_dsi_out>;
};
};
@@ -71,11 +71,8 @@ &lcdif1 {
&mipi_dsi {
samsung,esc-clock-frequency = <10000000>;
status = "okay";
+};
- port@1 {
- dsim_to_adv7535: endpoint {
- remote-endpoint = <&adv7535_from_dsim>;
- attach-bridge;
- };
- };
+&mipi_dsi_out {
+ remote-endpoint = <&adv7535_from_dsim>;
};
--
2.51.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v4 5/8] arm64: dts: imx8mp-sr-som: build dtbs with symbols for overlay support
2025-12-01 13:07 [PATCH v4 0/8] arm64: dts: add description for solidrun imx8mp hummingboard-iiot Josua Mayer
` (3 preceding siblings ...)
2025-12-01 13:07 ` [PATCH v4 4/8] arm64: dts: imx8mp-hummingboard-pulse: fix mini-hdmi dsi port reference Josua Mayer
@ 2025-12-01 13:07 ` Josua Mayer
2025-12-01 13:07 ` [PATCH v4 6/8] arm64: dts: add description for solidrun imx8mp hummingboard-iiot Josua Mayer
` (2 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Josua Mayer @ 2025-12-01 13:07 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Dmitry Torokhov, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam
Cc: Jon Nettleton, Mikhail Anikin, Yazan Shhady, devicetree,
linux-kernel, linux-input, imx, linux-arm-kernel, Josua Mayer
Build all dtbs based on SolidRun i.MX8MP SoM with symbols (adding -@ to
dtc flags) to enable support for device-tree addons.
The SoM has a camera connector for basler cameras that can be enabled by
downstream dtbo.
Hence by extension all boards based on this SoM should support addons.
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/freescale/Makefile | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 525ef180481d3..8bda6fb0ff9c1 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -197,6 +197,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-aristainetos3-helios-lvds.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-aristainetos3-proton2s.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-beacon-kit.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-cubox-m.dtb
+DTC_FLAGS_imx8mp-cubox-m := -@
dtb-$(CONFIG_ARCH_MXC) += imx8mp-data-modul-edm-sbc.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-model-a.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-som-a-bmb-08.dtb
@@ -207,9 +208,13 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-picoitx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-edm-g-wb.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-mate.dtb
+DTC_FLAGS_imx8mp-hummingboard-mate := -@
dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-pro.dtb
+DTC_FLAGS_imx8mp-hummingboard-pro := -@
dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-pulse.dtb
+DTC_FLAGS_imx8mp-hummingboard-pulse := -@
dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-ripple.dtb
+DTC_FLAGS_imx8mp-hummingboard-ripple := -@
dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-iota2-lumpy.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-bl-osm-s.dtb
--
2.51.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v4 6/8] arm64: dts: add description for solidrun imx8mp hummingboard-iiot
2025-12-01 13:07 [PATCH v4 0/8] arm64: dts: add description for solidrun imx8mp hummingboard-iiot Josua Mayer
` (4 preceding siblings ...)
2025-12-01 13:07 ` [PATCH v4 5/8] arm64: dts: imx8mp-sr-som: build dtbs with symbols for overlay support Josua Mayer
@ 2025-12-01 13:07 ` Josua Mayer
2025-12-01 13:07 ` [PATCH v4 7/8] arm64: dts: add description for solidrun solidsense-n8 board Josua Mayer
2025-12-01 13:07 ` [PATCH v4 8/8] arm64: dts: add description for solidrun i.mx8mm som and evb Josua Mayer
7 siblings, 0 replies; 11+ messages in thread
From: Josua Mayer @ 2025-12-01 13:07 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Dmitry Torokhov, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam
Cc: Jon Nettleton, Mikhail Anikin, Yazan Shhady, devicetree,
linux-kernel, linux-input, imx, linux-arm-kernel, Josua Mayer
Add description for the SolidRun i.MX8MP HummingBoard IIoT.
The board is a new design around the i.MX8MP System on Module, not
sharing much with previous HummingBoards.
It comes with some common features:
- 3x USB-3.0 Type A connector
- 2x 1Gbps RJ45 Ethernet
- USB Type-C Console Port
- microSD connector
- RTC with backup battery
- RGB Status LED
- 1x M.2 M-Key connector with PCI-E Gen. 3 x1
- 1x M.2 B-Key connector with USB-2.0/3.0 + SIM card holder
- 1x LVDS Display Connector
- 1x DSI Display Connector
- GPIO header
- 2x RS232/RS485 ports (configurable)
- 2x CAN
In addition there is a board-to-board expansion connector to support
custom daughter boards with access to SPI, a range of GPIOs and -
notably - CAN and UART. Both 2x CAN and 2x UART can be muxed either
to this b2b connector, or a termianl block connector on the base board.
The routing choice for UART and CAN is expressed through gpio
mux-controllers in DT and can be changed by applying dtb addons.
Four dtb addons are provided:
- dsi panel Winstar WJ70N3TYJHMNG0
- lvds panel Winstar WF70A8SYJHLNGA
- RS485 on UART port "A" (default rs232)
- RS485 on UART port "B" (default rs232)
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/freescale/Makefile | 6 +
...hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtso | 69 ++
...ummingboard-iiot-panel-lvds-WF70A8SYJHLNGA.dtso | 105 +++
.../imx8mp-hummingboard-iiot-rs485-a.dtso | 18 +
.../imx8mp-hummingboard-iiot-rs485-b.dtso | 18 +
.../dts/freescale/imx8mp-hummingboard-iiot.dts | 713 +++++++++++++++++++++
6 files changed, 929 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 8bda6fb0ff9c1..d414d0efe5e74 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -207,6 +207,12 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-picoitx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-edm-g-wb.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot.dtb
+DTC_FLAGS_imx8mp-hummingboard-iiot := -@
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtbo
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot-panel-lvds-WF70A8SYJHLNGA.dtbo
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot-rs485-a.dtbo
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot-rs485-b.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-mate.dtb
DTC_FLAGS_imx8mp-hummingboard-mate := -@
dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-pro.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtso b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtso
new file mode 100644
index 0000000000000..e66ee2ce69d8d
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtso
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ *
+ * Overlay for enabling HummingBoard IIoT MIPI-DSI connector
+ * with Winstar WJ70N3TYJHMNG0 panel.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+&{/} {
+ dsi_backlight: dsi-backlight {
+ compatible = "gpio-backlight";
+ gpios = <&tca6408_u48 3 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&i2c_dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ touchscreen@41 {
+ compatible = "ilitek,ili2130";
+ reg = <0x41>;
+ reset-gpios = <&tca6408_u48 6 GPIO_ACTIVE_LOW>;
+ interrupts-extended = <&tca6416_u21 13 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&lcdif1 {
+ status = "okay";
+};
+
+&mipi_dsi {
+ samsung,esc-clock-frequency = <10000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ panel@0 {
+ /* This is a Winstar panel, but the ronbo panel uses same controls. */
+ compatible = "ronbo,rb070d30";
+ reg = <0>;
+ vcc-lcd-supply = <®_dsi_panel>;
+ power-gpios = <&tca6408_u48 2 GPIO_ACTIVE_HIGH>;
+ /* reset is active-low but driver inverts it internally */
+ reset-gpios = <&tca6408_u48 1 GPIO_ACTIVE_HIGH>;
+ updn-gpios = <&tca6408_u48 5 GPIO_ACTIVE_HIGH>;
+ shlr-gpios = <&tca6408_u48 4 GPIO_ACTIVE_LOW>;
+ backlight = <&dsi_backlight>;
+
+ port {
+ panel_from_dsim: endpoint {
+ remote-endpoint = <&dsim_to_panel>;
+ };
+ };
+ };
+
+ port@1 {
+ dsim_to_panel: endpoint {
+ remote-endpoint = <&panel_from_dsim>;
+ data-lanes = <1 2 3 4>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-panel-lvds-WF70A8SYJHLNGA.dtso b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-panel-lvds-WF70A8SYJHLNGA.dtso
new file mode 100644
index 0000000000000..f8fb7fd0e4e49
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-panel-lvds-WF70A8SYJHLNGA.dtso
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ *
+ * Overlay for enabling HummingBoard IIoT LVDS connector
+ * with Winstar WF70A8SYJHLNGA panel.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+&{/} {
+ lvds_backlight: lvds-backlight {
+ compatible = "gpio-backlight";
+ gpios = <&tca6408_u37 3 GPIO_ACTIVE_LOW>;
+ };
+
+ panel-lvds {
+ compatible = "winstar,wf70a8syjhlnga", "panel-lvds";
+ backlight = <&lvds_backlight>;
+ power-supply = <®_dsi_panel>;
+ enable-gpios = <&tca6408_u37 2 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&tca6408_u37 1 GPIO_ACTIVE_HIGH>;
+ data-mapping = "vesa-24";
+ width-mm = <154>;
+ height-mm = <86>;
+
+ panel-timing {
+ /*
+ * Note: NXP BSP hard-codes 74MHz clock in ldb driver:
+ * drivers/gpu/drm/imx/imx8mp-ldb.c
+ * SolidRun BSP carries patch.
+ */
+ clock-frequency = <49500000>;
+ hactive = <1024>;
+ vactive = <600>;
+ hfront-porch = <40>;
+ hback-porch = <144>;
+ hsync-len = <104>;
+ hsync-active = <0>;
+ vfront-porch = <3>;
+ vback-porch = <11>;
+ vsync-len = <10>;
+ vsync-active = <1>;
+ de-active = <1>;
+ };
+
+ port {
+ panel_from_lvds: endpoint {
+ remote-endpoint = <&lvds_ch0_out>;
+ };
+ };
+ };
+};
+
+&i2c_lvds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ touchscreen@41 {
+ compatible = "ilitek,ili2130";
+ reg = <0x41>;
+ reset-gpios = <&tca6408_u37 6 GPIO_ACTIVE_LOW>;
+ interrupts-extended = <&tca6416_u21 13 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&lcdif2 {
+ status = "okay";
+};
+
+&lvds_bridge {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ port@1 {
+ lvds_ch0_out: endpoint {
+ remote-endpoint = <&panel_from_lvds>;
+ };
+ };
+ };
+};
+
+&tca6408_u37 {
+ lvds-lr-hog {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "lvds-l/r";
+ };
+
+ lvds-ud-hog {
+ gpio-hog;
+ gpios = <5 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "lvds-u/d";
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-rs485-a.dtso b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-rs485-a.dtso
new file mode 100644
index 0000000000000..7bbf800b78fb1
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-rs485-a.dtso
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ *
+ * Overlay for enabling HummingBoard IIoT on-board RS485 Port A on connector J5004.
+ */
+
+/dts-v1/;
+/plugin/;
+
+&uart3_rs_232_485_mux {
+ /* select rs485 */
+ idle-state = <1>;
+};
+
+&uart3 {
+ linux,rs485-enabled-at-boot-time;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-rs485-b.dtso b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-rs485-b.dtso
new file mode 100644
index 0000000000000..d4bfea886ad12
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-rs485-b.dtso
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ *
+ * Overlay for enabling HummingBoard IIoT on-board RS485 Port B on connector J5004.
+ */
+
+/dts-v1/;
+/plugin/;
+
+&uart4_rs_232_485_mux {
+ /* select rs485 */
+ idle-state = <1>;
+};
+
+&uart4 {
+ linux,rs485-enabled-at-boot-time;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot.dts b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot.dts
new file mode 100644
index 0000000000000..070f03e5abab9
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot.dts
@@ -0,0 +1,713 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 Yazan Shhady <yazan.shhady@solid-run.com>
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+
+#include "imx8mp-sr-som.dtsi"
+
+/ {
+ model = "SolidRun i.MX8MP HummingBoard IIoT";
+ compatible = "solidrun,imx8mp-hummingboard-iiot",
+ "solidrun,imx8mp-sr-som", "fsl,imx8mp";
+
+ aliases {
+ ethernet0 = &eqos; /* J10 */
+ ethernet1 = &fec; /* J11 */
+ rtc0 = &carrier_rtc;
+ rtc1 = &snvs_rtc;
+ gpio5 = &tca6408_u48;
+ gpio6 = &tca6408_u37;
+ gpio7 = &tca6416_u20;
+ gpio8 = &tca6416_u21;
+ i2c6 = &i2c_exp;
+ i2c7 = &i2c_csi;
+ i2c8 = &i2c_dsi;
+ i2c9 = &i2c_lvds;
+ };
+
+ v_1_2: regulator-1-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "1v2";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ reg_dsi_panel: regulator-dsi-panel {
+ compatible = "regulator-fixed";
+ regulator-name = "dsi-panel";
+ regulator-min-microvolt = <11200000>;
+ regulator-max-microvolt = <11200000>;
+ gpios = <&tca6416_u20 15 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ /* power for M.2 B-Key connector (J6) */
+ regulator-m2-b {
+ compatible = "regulator-fixed";
+ regulator-name = "m2-b";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&tca6416_u20 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ /* power for M.2 M-Key connector (J4) */
+ regulator-m2-m {
+ compatible = "regulator-fixed";
+ regulator-name = "m2-m";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&tca6416_u20 6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ vmmc: regulator-mmc {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vmmc_pins>;
+ regulator-name = "vmmc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 19 GPIO_ACTIVE_LOW>;
+ enable-active-high;
+ startup-delay-us = <250>;
+ };
+
+ /* power for USB-A J5003 */
+ vbus1: regulator-vbus-1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus1";
+ gpio = <&tca6416_u20 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ /* power for USB-A J27 behind USB Hub Port 3 */
+ regulator-vbus-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus2";
+ gpio = <&tca6416_u20 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ /* power for USB-A J27 behind USB Hub Port 4 */
+ regulator-vbus-3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus3";
+ gpio = <&tca6416_u20 13 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ rfkill-m2-b-gnss {
+ compatible = "rfkill-gpio";
+ label = "m2-b gnss";
+ radio-type = "gps";
+ /* rfkill-gpio inverts internally */
+ shutdown-gpios = <&tca6416_u20 10 GPIO_ACTIVE_HIGH>;
+ };
+
+ rfkill-m2-b-wwan {
+ compatible = "rfkill-gpio";
+ label = "m2-b radio";
+ radio-type = "wwan";
+ /* rfkill-gpio inverts internally */
+ shutdown-gpios = <&tca6416_u20 9 GPIO_ACTIVE_HIGH>;
+ };
+
+ flexcan1_flexcan2_b2b_mux: mux-controller-0 {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+ /*
+ * Mux switches both flexcan1 and flexcan2 tx/rx between
+ * expansion connector (J22) and on-board transceivers
+ * using one GPIO: 0 = on-board, 1 connector.
+ */
+ mux-gpios = <&tca6416_u20 3 GPIO_ACTIVE_HIGH>;
+ /* default on-board */
+ idle-state = <0>;
+ };
+
+ mux-controller-1 {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+ /*
+ * Mux switches can bus between different SoM board-to-board
+ * connector pins which is used to support different SoMs.
+ * i.MX8M Plus uses J7-12/16 and J9-54/56 for 2x flexcan.
+ */
+ mux-gpios = <&tca6416_u20 4 GPIO_ACTIVE_HIGH>;
+ idle-state = <1>;
+ };
+
+ spi_mux: mux-controller-2 {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+ /*
+ * Mux switches spi bus between on-board tpm
+ * and expansion connector (J22).
+ */
+ mux-gpios = <&tca6416_u21 0 GPIO_ACTIVE_HIGH>;
+ /* default on-board */
+ idle-state = <0>;
+ };
+
+ uart3_uart4_b2b_mux: mux-controller-3 {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+ /*
+ * Mux switches both uart3 and uart4 tx/rx between expansion
+ * connector (J22) and on-board rs232/rs485 transceivers
+ * using one GPIO: 0 = on-board, 1 connector.
+ */
+ mux-gpios = <&tca6416_u20 0 GPIO_ACTIVE_HIGH>;
+ /* default on-board */
+ idle-state = <0>;
+ };
+
+ uart3_rs_232_485_mux: mux-controller-4 {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+ /*
+ * Mux switches uart3 tx/rx between rs232 and rs485
+ * transceivers. using one GPIO: 0 = rs232; 1 = rs485.
+ */
+ mux-gpios = <&tca6416_u20 1 GPIO_ACTIVE_HIGH>;
+ /* default rs232 */
+ idle-state = <0>;
+ };
+
+ uart4_rs_232_485_mux: mux-controller-5 {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+ /*
+ * Mux switches uart4 tx/rx between rs232 and rs485
+ * transceivers. using one GPIO: 0 = rs232; 1 = rs485.
+ */
+ mux-gpios = <&tca6416_u20 2 GPIO_ACTIVE_HIGH>;
+ /* default rs232 */
+ idle-state = <0>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ wakeup-event {
+ label = "m2-m-wakeup";
+ interrupts-extended = <&tca6416_u21 11 IRQ_TYPE_EDGE_FALLING>;
+ linux,code = <KEY_WAKEUP>;
+ wakeup-source;
+ };
+ };
+};
+
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ecspi2_pins>;
+ num-cs = <1>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ ecspi2_muxed: spi@0 {
+ compatible = "spi-mux";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* mux bandwidth is 2GHz, soc max. spi clock is 166MHz */
+ spi-max-frequency = <166000000>;
+ mux-controls = <&spi_mux>;
+
+ tpm@0 {
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+ reg = <0>;
+ spi-max-frequency = <43000000>;
+ reset-gpios = <&tca6416_u21 1 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+ interrupts-extended = <&tca6416_u21 9 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
+};
+
+&flexcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&can1_pins>;
+ status = "okay";
+
+ can-transceiver {
+ max-bitrate = <8000000>;
+ };
+};
+
+&flexcan2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&can2_pins>;
+ status = "okay";
+
+ can-transceiver {
+ max-bitrate = <8000000>;
+ };
+};
+
+&i2c2 {
+ i2c-mux@70 {
+ compatible = "nxp,pca9546";
+ reg = <0x70>;
+ /*
+ * This reset is open drain,
+ * but reset core does not support GPIO_OPEN_DRAIN flag.
+ */
+ reset-gpios = <&tca6416_u21 2 GPIO_ACTIVE_LOW>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* channel 0 routed to expansion connector (J22) */
+ i2c_exp: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ /* channel 1 routed to mipi-csi connector (J23) */
+ i2c_csi: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ /* channel 2 routed to mipi-dsi connector (J25) */
+ i2c_dsi: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tca6408_u48: gpio@21 {
+ compatible = "ti,tca6408";
+ reg = <0x21>;
+ /*
+ * reset shared between U37 and U48, to be
+ * supported once gpio-pca953x switches to
+ * reset framework.
+ *
+ * reset-gpios = <&tca6416_u21 4 (GPIO_ACTIVE_LOW|GPIO_PULL_UP|GPIO_OPEN_DRAIN)>;
+ */
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "CAM_RST#", "DSI_RESET",
+ "DSI_STBYB", "DSI_PWM_BL",
+ "DSI_L/R", "DSI_U/D",
+ "DSI_CTP_/RST", "CAM_TRIG";
+ };
+ };
+
+ /* channel 2 routed to lvds connector (J24) */
+ i2c_lvds: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tca6408_u37: gpio@20 {
+ compatible = "ti,tca6408";
+ reg = <0x20>;
+ /*
+ * reset shared between U37 and U48, to be
+ * supported once gpio-pca953x switches to
+ * reset framework.
+ *
+ * reset-gpios = <&tca6416_u21 4 (GPIO_ACTIVE_LOW|GPIO_PULL_UP|GPIO_OPEN_DRAIN)>;
+ */
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "SELB", "LVDS_RESET",
+ "LVDS_STBYB", "LVDS_PWM_BL",
+ "LVDS_L/R", "LVDS_U/D",
+ "LVDS_CTP_/RST", "";
+ };
+ };
+ };
+};
+
+&i2c3 {
+ /* highest i2c clock supported by all peripherals is 400kHz */
+ clock-frequency = <400000>;
+
+ tca6416_u20: gpio@20 {
+ /*
+ * This is a TI TCAL6416 using same programming model as
+ * NXP PCAL6416, not to be confused with TI TCA6416.
+ */
+ compatible = "nxp,pcal6416";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "TCA_INT/EXT_UART", "TCA_UARTA_232/485",
+ "TCA_UARTB_232/485", "TCA_INT/EXT_CAN",
+ "TCA_NXP/REN", "TCA_M.2B_3V3_EN",
+ "TCA_M.2M_3V3_EN", "TCA_M.2M_RESET#",
+ "TCA_M.2B_RESET#", "TCA_M.2B_W_DIS#",
+ "TCA_M.2B_GPS_EN#", "TCA_USB-HUB_RST#",
+ "TCA_USB_HUB3_PWR_EN", "TCA_USB_HUB4_PWR_EN",
+ "TCA_USB1_PWR_EN", "TCA_VIDEO_PWR_EN";
+
+ m2-b-reset-hog {
+ gpio-hog;
+ gpios = <8 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "m2-b-reset";
+ };
+ };
+
+ tca6416_u21: gpio@21 {
+ /*
+ * This is a TI TCAL6416 using same programming model as
+ * NXP PCAL6416, not to be confused with TI TCA6416.
+ */
+ compatible = "nxp,pcal6416";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&tca6416_u21_int_pins>;
+ interrupts-extended = <&gpio1 15 IRQ_TYPE_EDGE_FALLING>;
+ gpio-line-names = "TCA_SPI_TPM/EXT", "TCA_TPM_RST#",
+ "TCA_I2C_RST", "TCA_RS232_SHTD#",
+ "TCA_LCD_I2C_RST", "TCA_DIG_OUT1",
+ "TCA_bDIG_IN1", "TCA_SENS_INT",
+ "TCA_ALERT#", "TCA_TPM_PIRQ#",
+ "TCA_RTC_INT", "TCA_M.2M_WAKW_ON_LAN",
+ "TCA_M.2M_CLKREQ#", "TCA_LVDS_INT#",
+ "", "TCA_POE_AT";
+
+ rs232_shutdown: rs232-shutdown-hog {
+ gpio-hog;
+ gpios = <3 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "rs232-shutdown";
+ };
+
+ lcd-i2c-reset-hog {
+ /*
+ * reset shared between U37 and U48, to be
+ * supported once gpio-pca953x switches to
+ * reset framework.
+ */
+ gpio-hog;
+ gpios = <4 (GPIO_ACTIVE_LOW|GPIO_PULL_UP|GPIO_OPEN_DRAIN)>;
+ output-low;
+ line-name = "lcd-i2c-reset";
+ };
+
+ m2-m-clkreq-hog {
+ gpio-hog;
+ gpios = <12 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "m2-m-clkreq";
+ };
+ };
+
+ led-controller@30 {
+ compatible = "ti,lp5562";
+ reg = <0x30>;
+ /* use internal clock, could use external generated by rtc */
+ clock-mode = /bits/ 8 <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ multi-led@0 {
+ reg = <0x0>;
+ label = "D7";
+ color = <LED_COLOR_ID_RGB>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0x0>;
+ color = <LED_COLOR_ID_RED>;
+ led-cur = /bits/ 8 <0x32>;
+ max-cur = /bits/ 8 <0x64>;
+ };
+
+ led@1 {
+ reg = <0x1>;
+ color = <LED_COLOR_ID_GREEN>;
+ led-cur = /bits/ 8 <0x19>;
+ max-cur = /bits/ 8 <0x32>;
+ };
+
+ led@2 {
+ reg = <0x2>;
+ color = <LED_COLOR_ID_BLUE>;
+ led-cur = /bits/ 8 <0x19>;
+ max-cur = /bits/ 8 <0x32>;
+ };
+ };
+
+ led@3 {
+ reg = <3>;
+ chan-name = "D8";
+ label = "D8";
+ color = <LED_COLOR_ID_GREEN>;
+ led-cur = /bits/ 8 <0x19>;
+ max-cur = /bits/ 8 <0x64>;
+ };
+ };
+
+ light-sensor@44 {
+ compatible = "isil,isl29023";
+ reg = <0x44>;
+ /* IRQ shared between accelerometer, light-sensor and Tamper input (J5007) */
+ interrupts-extended = <&tca6416_u21 7 IRQ_TYPE_EDGE_FALLING>;
+ };
+
+ accelerometer@53 {
+ compatible = "adi,adxl345";
+ reg = <0x53>;
+ /* IRQ shared between accelerometer, light-sensor and Tamper input (J5007) */
+ interrupt-names = "INT1";
+ interrupts-extended = <&tca6416_u21 7 IRQ_TYPE_EDGE_FALLING>;
+ };
+
+ carrier_eeprom: eeprom@57{
+ compatible = "atmel,24c02";
+ reg = <0x57>;
+ pagesize = <8>;
+ };
+
+ carrier_rtc: rtc@69 {
+ compatible = "abracon,ab1805";
+ reg = <0x69>;
+ abracon,tc-diode = "schottky";
+ abracon,tc-resistor = <3>;
+ interrupts-extended = <&tca6416_u21 10 IRQ_TYPE_EDGE_FALLING>;
+ };
+};
+
+&iomuxc {
+ can1_pins: pinctrl-can1-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
+ MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
+ >;
+ };
+
+ can2_pins: pinctrl-can2-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
+ MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
+ >;
+ };
+
+ ecspi2_pins: pinctrl-ecspi2-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140
+ MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140
+ MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140
+ MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
+ >;
+ };
+
+ tca6416_u21_int_pins: pinctrl-tca6416-u21-int-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x0
+ >;
+ };
+
+ /* UARTA */
+ uart3_pins: pinctrl-uart3-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140
+ MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140
+ MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x140
+ >;
+ };
+
+ /* UARTB */
+ uart4_pins: pinctrl-uart4-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_DATA00__UART4_DCE_RX 0x140
+ MX8MP_IOMUXC_NAND_DATA01__UART4_DCE_TX 0x140
+ MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x140
+ >;
+ };
+
+ usdhc2_pins: pinctrl-usdhc2-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x140
+ MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x140
+ >;
+ };
+
+ usdhc2_100mhz_pins: pinctrl-usdhc2-100mhz-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x140
+ MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x140
+ >;
+ };
+
+ usdhc2_200mhz_pins: pinctrl-usdhc2-200mhz-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x140
+ MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x140
+ >;
+ };
+
+ vmmc_pins: pinctrl-vmmc-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x0
+ >;
+ };
+};
+
+&pcie {
+ reset-gpio = <&tca6416_u20 7 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+/* M.2 M-Key (J4) */
+&pcie_phy {
+ clocks = <&hsio_blk_ctrl>;
+ clock-names = "ref";
+ fsl,clkreq-unsupported;
+ fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
+ status = "okay";
+};
+
+&phy0 {
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* ADIN1300 LED_0 pin */
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
+};
+
+&phy1 {
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* ADIN1300 LED_0 pin */
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>;
+ rts-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+ /* select 80MHz parent clock to support maximum baudrate 4Mbps */
+ assigned-clocks = <&clk IMX8MP_CLK_UART3>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins>;
+ rts-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
+ /* select 80MHz parent clock to support maximum baudrate 4Mbps */
+ assigned-clocks = <&clk IMX8MP_CLK_UART4>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
+ status = "okay";
+};
+
+&usb3_phy0 {
+ fsl,phy-tx-preemp-amp-tune-microamp = <1200>;
+ vbus-supply = <&vbus1>;
+ status = "okay";
+};
+
+&usb3_0 {
+ status = "okay";
+};
+
+&usb3_phy1 {
+ status = "okay";
+};
+
+&usb3_1 {
+ status = "okay";
+};
+
+&usb_dwc3_0 {
+ dr_mode = "host";
+};
+
+&usb_dwc3_1 {
+ dr_mode = "host";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hub_2_0: hub@1 {
+ compatible = "usb4b4,6502", "usb4b4,6506";
+ reg = <1>;
+ peer-hub = <&hub_3_0>;
+ reset-gpios = <&tca6416_u20 11 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&v_1_2>;
+ vdd2-supply = <&v_3_3>;
+ };
+
+ hub_3_0: hub@2 {
+ compatible = "usb4b4,6500", "usb4b4,6504";
+ reg = <2>;
+ peer-hub = <&hub_2_0>;
+ reset-gpios = <&tca6416_u20 11 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&v_1_2>;
+ vdd2-supply = <&v_3_3>;
+ };
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&usdhc2_pins>;
+ pinctrl-1 = <&usdhc2_100mhz_pins>;
+ pinctrl-2 = <&usdhc2_200mhz_pins>;
+ vmmc-supply = <&vmmc>;
+ bus-width = <4>;
+ cap-power-off-card;
+ full-pwr-cycle;
+ status = "okay";
+};
--
2.51.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v4 7/8] arm64: dts: add description for solidrun solidsense-n8 board
2025-12-01 13:07 [PATCH v4 0/8] arm64: dts: add description for solidrun imx8mp hummingboard-iiot Josua Mayer
` (5 preceding siblings ...)
2025-12-01 13:07 ` [PATCH v4 6/8] arm64: dts: add description for solidrun imx8mp hummingboard-iiot Josua Mayer
@ 2025-12-01 13:07 ` Josua Mayer
2025-12-01 13:49 ` Andrew Lunn
2025-12-01 13:07 ` [PATCH v4 8/8] arm64: dts: add description for solidrun i.mx8mm som and evb Josua Mayer
7 siblings, 1 reply; 11+ messages in thread
From: Josua Mayer @ 2025-12-01 13:07 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Dmitry Torokhov, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam
Cc: Jon Nettleton, Mikhail Anikin, Yazan Shhady, devicetree,
linux-kernel, linux-input, imx, linux-arm-kernel, Josua Mayer
Add description for the SolidRun SolidSense N8 Compact.
The board is designed around the i.MX8MN SoC and comes as a complete
product including enclosure and labels.
Features:
- USB-2.0 Type A connector
- 1Gbps RJ45 Ethernet with PoE
- microSD connector
- eMMC
- Cellular Modem + SIM holder
- WiFi + Bluetooth
- RS485
- CAN
- 802.15.1 radio
- supercapacitor backup power supply
This is a headless design without display.
The board includes an internal expansion connector for daughterboards
which may be described by dt addon.
The supercap is not currently described due to lack of suitable bindings.
Vendor BSP uses gpio-keys driver to trigger shutdown on power loss.
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/freescale/Makefile | 2 +
.../dts/freescale/imx8mn-solidsense-n8-compact.dts | 853 +++++++++++++++++++++
2 files changed, 855 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index d414d0efe5e74..c56137097da3b 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -181,6 +181,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr3l-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-rve-gateway.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mn-solidsense-n8-compact.dtb
+DTC_FLAGS_imx8mn-solidsense-n8-compact += -@
dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-solidsense-n8-compact.dts b/arch/arm64/boot/dts/freescale/imx8mn-solidsense-n8-compact.dts
new file mode 100644
index 0000000000000..93396e22ba409
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mn-solidsense-n8-compact.dts
@@ -0,0 +1,853 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Device Tree file for SolidSense N8 Compact
+ *
+ * Copyright 2024 Josua Mayer <josua@solid-run.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+
+#include "imx8mn.dtsi"
+
+/ {
+ model = "SolidRun SolidSense N8 Compact";
+ compatible = "solidrun,solidsense-n8-compact", "fsl,imx8mn";
+
+ aliases {
+ gpio5 = &expander;
+ rtc0 = &rtc;
+ rtc1 = &snvs_rtc;
+ usb0 = &usbotg1;
+ watchdog0 = &wdog1;
+ watchdog1 = &rtc;
+ };
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ /* LED labels based on enclosure, schematic names differ. */
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins>;
+
+ /* D20 */
+ led1 {
+ label = "led1";
+ gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ /* D18 */
+ led2 {
+ label = "led2";
+ gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ /* D19 */
+ led3 {
+ label = "led3";
+ gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ memory@40000000 {
+ reg = <0x0 0x40000000 0 0x80000000>;
+ device_type = "memory";
+ };
+
+ reg_modem_vbat: regulator-modem-vbat {
+ compatible = "regulator-fixed";
+ regulator-name = "modem-vbat";
+ pinctrl-names = "default";
+ pinctrl-0 = <®ulator_modem_vbat_pins>;
+ regulator-min-microvolt = <3800000>;
+ regulator-max-microvolt = <3800000>;
+ gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ /* power to lte modems behind hub ports 2/3 */
+ reg_modem_vbus: regulator-modem-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "modem-vbus";
+ pinctrl-names = "default";
+ pinctrl-0 = <®ulator_modem_vbus_pins>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio5 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ /* power to usb hub, and type-a behind hub port 1 */
+ reg_usb1_vbus: regulator-usb1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb1-vbus";
+ pinctrl-names = "default";
+ pinctrl-0 = <®ulator_usb1_vbus_pins>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_vdd_1v8: regulator-vdd-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ reg_vdd_3v3: regulator-vdd-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "usdhc2-vmmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <®ulator_usdhc2_vmmc_pins>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <®_vdd_3v3>;
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ off-on-delay-us = <250>;
+ };
+
+ rfkill {
+ compatible = "rfkill-gpio";
+ label = "rfkill-wwan";
+ radio-type = "wwan";
+ pinctrl-names = "default";
+ pinctrl-0 = <&modem_pins>;
+ /* rfkill-gpio inverts internally */
+ shutdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ };
+
+ usdhc1_pwrseq: usdhc1-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&A53_0 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&A53_1 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&A53_2 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&A53_3 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&ddrc {
+ operating-points-v2 = <&ddrc_opp_table>;
+
+ ddrc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-266500000 {
+ opp-hz = /bits/ 64 <266500000>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ };
+ };
+};
+
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ecspi2_pins>;
+ /* native chip-select causes reading 0xffffffff */
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ num-cs = <1>;
+ status = "okay";
+
+ can@0 {
+ compatible = "microchip,mcp2518fd";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&can_pins>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ clocks = <&clk IMX8MN_CLK_CLKOUT1>;
+ /* generate 8MHz clock from soc-internal 24mhz reference */
+ assigned-clocks = <&clk IMX8MN_CLK_CLKOUT1_SEL>,
+ <&clk IMX8MN_CLK_CLKOUT1_DIV>;
+ assigned-clock-rates = <0>, <8000000>;
+ assigned-clock-parents = <&clk IMX8MN_CLK_24M>, <0>;
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&fec1_pins>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy4>;
+ local-mac-address = [00 00 00 00 00 00];
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /*
+ * Depending on board revision two different phys are used:
+ * - v1.1: atheros phy at address 4
+ * - v1.2+: analog devices phy at address 0
+ * Configure first version by default.
+ * On v1.2 and later, U-Boot will enable the correct phy
+ * based on runtime detection and patch dtb accordingly.
+ */
+
+ /* ADIN1300 */
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ reset-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10>;
+ reset-deassert-us = <5000>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
+ adi,link-st-polarity = <GPIO_ACTIVE_LOW>;
+ adi,led-polarity = <GPIO_ACTIVE_LOW>;
+ status = "disabled";
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_YELLOW>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ active-low;
+ };
+ };
+ };
+
+ /* AR8035 */
+ phy4: ethernet-phy@4 {
+ reg = <4>;
+ reset-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ status = "okay";
+ };
+ };
+};
+
+&gpio5 {
+ usb-hub-reset-hog {
+ gpio-hog;
+ gpios = <3 GPIO_ACTIVE_LOW>;
+ output-low; /* deasserted */
+ line-name = "usb-hub-reset";
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ status = "okay";
+
+ pmic@4b {
+ compatible = "rohm,bd71847";
+ reg = <0x4b>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_pins>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+ rohm,reset-snvs-powered;
+
+ #clock-cells = <0>;
+ clocks = <&osc_32k>;
+ clock-output-names = "clk-32k-out";
+
+ regulators {
+ BUCK1 {
+ // supplies soc vdd, soc mipi vdd @ 0.9V
+ regulator-name = "buck1";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ rohm,dvs-run-voltage = <850000>;
+ rohm,dvs-suspend-voltage = <750000>;
+ };
+
+ buck2_reg: BUCK2 {
+ regulator-name = "buck2";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ rohm,dvs-run-voltage = <1000000>;
+ rohm,dvs-idle-voltage = <900000>;
+ rohm,dvs-suspend-voltage = <0>;
+ };
+
+ BUCK3 {
+ // BUCK5 in datasheet
+ // output floating
+ regulator-name = "buck3";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ };
+
+ BUCK4 {
+ // BUCK6 in datasheet
+ // supplies ldo3, ldo5, muxsw
+ regulator-name = "buck4";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ BUCK5 {
+ // BUCK7 in datasheet
+ // supplies ldo4, ldo6, muxsw
+ // enables dram vpp @ 2.5V
+ regulator-name = "buck5";
+ regulator-min-microvolt = <1605000>;
+ regulator-max-microvolt = <1995000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ BUCK6 {
+ // BUCK8 in datasheet
+ // supplies dram @ 1.2V
+ regulator-name = "buck6";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO1 {
+ // supplies soc snvs @ 1.8V
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO2 {
+ // supplies soc snvs @ 0.8V
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO3 {
+ // supplies soc vdd @ 1.8V
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO4 {
+ // output floating
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ LDO5 {
+ // output floating
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ LDO6 {
+ // supplies soc vdd mipi @ 1.2V
+ regulator-name = "ldo6";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ /*
+ * routed to various connectors:
+ * - basler camera (CON2)
+ * - touchscreen (J3)
+ * - expansion connector (J14)
+ */
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+ status = "okay";
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins>;
+ status = "okay";
+
+ expander: gpio@20 {
+ compatible = "ti,tca6408";
+ reg = <0x20>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_expander_pins>;
+ reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "SYSGD", "PFO#", "CAPGD", "CAPFLT#",
+ "CHGEN#", "BSTEN#", "", "";
+ };
+
+ light-sensor@44 {
+ compatible = "isil,isl29023";
+ reg = <0x44>;
+ };
+
+ accelerometer@53 {
+ compatible = "adi,adxl345";
+ reg = <0x53>;
+ };
+
+ /* battery-charger@68 */
+
+ rtc: rtc@69 {
+ compatible = "abracon,abx80x";
+ reg = <0x69>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rtc_pins>;
+ abracon,tc-diode = "schottky";
+ abracon,tc-resistor = <3>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ };
+};
+
+&i2c4 {
+ /* routed to expansion connector (J14) */
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_pins>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&tamper_pins>, <&usb_hub_pins>;
+
+ ieee802151_radio_pins: pinctrl-ieee802151-radio-grp {
+ fsl,pins = <
+ /* RESETN */
+ MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x0
+ /* VDD_EN */
+ MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x0
+ /* SWDCLK */
+ MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x0
+ /* SDIO */
+ MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x0
+ >;
+ };
+
+ can_pins: pinctrl-can-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SAI3_TXD_GPIO5_IO1 0x140
+ >;
+ };
+
+ ecspi2_pins: pinctrl-ecspi2-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x96
+ MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x1d6
+ MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x1d6
+ MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x1d6
+ >;
+ };
+
+ fec1_pins: pinctrl-fec1-grp {
+ /*
+ * Some pins are sampled at phy reset to apply configuration:
+ * - AR803x PHY (revision 1.1)
+ * - RXD[1:0]: phy address bits [1:0]
+ * - RXD[3:2],RX_CTL: mac interface select bits 3,1,0
+ * - ADIN1300 PHY (revision 1.2 or later)
+ * - RXD[3:0]: phy address bits [3:0]
+ * - RX_CTL,RXC: mac interface select bits 1,0
+ * SoC enables pull-down at reset, PHYs have internal
+ * pull-down, so pinmux may unset pull-enable.
+ */
+ fsl,pins = <
+ MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x2
+ MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x2
+ MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1e
+ MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1e
+ MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1e
+ MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1e
+ /* RD[3:0] sampled at phy reset for address bits [3:0] */
+ MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90
+ MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90
+ MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90
+ MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90
+ MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x10
+ MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90
+ MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90
+ MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x10
+ /* phy reset */
+ MX8MN_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x0
+ /* phy interrupt */
+ MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140
+ >;
+ };
+
+ gpio_expander_pins: pinctrl-gpio-expander-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x140
+ MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x140
+ >;
+ };
+
+ i2c1_pins: pinctrl-i2c1-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c2
+ MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c2
+ >;
+ };
+
+ i2c2_pins: pinctrl-i2c2-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c2
+ MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c2
+ >;
+ };
+
+ i2c3_pins: pinctrl-i2c3-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2
+ MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2
+ >;
+ };
+
+ i2c4_pins: pinctrl-i2c4-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2
+ MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2
+ >;
+ };
+
+ led_pins: pinctrl-led-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x100
+ MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x100
+ MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x100
+ >;
+ };
+
+ modem_pins: pinctrl-modem-grp {
+ fsl,pins = <
+ /* RESET_N: modem-internal pull-down */
+ MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x0
+ /* PWRKEY: pull-down ensures always-on */
+ MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x100
+ >;
+ };
+
+ pmic_pins: pinctrl-pmic-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x140
+ >;
+ };
+
+ regulator_modem_vbat_pins: pinctrl-regulator-modem-vbat-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x0
+ >;
+ };
+
+ regulator_modem_vbus_pins: pinctrl-regulator-modem-vbus-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x0
+ >;
+ };
+
+ regulator_usb1_vbus_pins: pinctrl-regulator-usb1-vbus-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x0
+ >;
+ };
+
+ regulator_usdhc2_vmmc_pins: pinctrl-regulator-usdhc2-vmmc-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0
+ >;
+ };
+
+ rtc_pins: pinctrl-rtc-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140
+ MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x100
+ >;
+ };
+
+ tamper_pins: pinctrl-tamper-grp {
+ /*
+ * Routed to physical tamper input (J12),
+ * accelerometer and light-sensor interrupts.
+ */
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x140
+ >;
+ };
+
+ uart1_pins: pinctrl-uart1-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
+ MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
+ MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
+ MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
+ /* BT_REG_ON */
+ MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0
+ /* BT_WAKE_DEV */
+ MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0
+ /* BT_WAKE_HOST */
+ MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x100
+ >;
+ };
+
+ uart2_pins: pinctrl-uart2-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ >;
+ };
+
+ uart3_pins: pinctrl-uart3-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x140
+ MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x140
+ MX8MN_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x140
+ MX8MN_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x140
+ >;
+ };
+
+ uart4_pins: pinctrl-uart4-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
+ MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
+ >;
+ };
+
+ usb_hub_pins: pinctrl-usb-hub-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x0
+ >;
+ };
+
+ usdhc1_pins: pinctrl-usdhc1-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
+ MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
+ MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
+ MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
+ MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
+ MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
+ /* wifi refclk */
+ MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x0
+ /* WL_WAKE_HOST */
+ MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x100
+ /* WL_REG_ON */
+ MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0
+ >;
+ };
+
+ usdhc2_pins: pinctrl-usdhc2-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0
+ /* usdhc2 signalling voltage pmic control */
+ MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x140
+ >;
+ };
+
+ usdhc2_100mhz_pins: pinctrl-usdhc2-100mhz-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0
+ /* usdhc2 signalling voltage pmic control */
+ MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x140
+ >;
+ };
+
+ usdhc2_200mhz_pins: pinctrl-usdhc2-100mhz-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
+ MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
+ MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
+ MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
+ MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
+ MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
+ MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0
+ /* usdhc2 signalling voltage pmic control */
+ MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x140
+ >;
+ };
+
+ usdhc3_pins: pinctrl-usdhc3-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
+ MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
+ MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
+ MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
+ MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
+ MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
+ MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
+ MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
+ MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
+ MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
+ MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
+ >;
+ };
+
+ wdog1_pins: pinctrl-wdog1-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x140
+ >;
+ };
+};
+
+/* Bluetooth */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ uart-has-rtscts;
+ /* select 80MHz parent clock to support maximum baudrate 4Mbps */
+ assigned-clocks = <&clk IMX8MN_CLK_UART1>;
+ assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm4330-bt";
+ device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
+ max-speed = <3000000>;
+ };
+};
+
+/* console */
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "okay";
+};
+
+/* RS485 */
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>;
+ uart-has-rtscts;
+ linux,rs485-enabled-at-boot-time;
+ fsl,dte-mode;
+ status = "okay";
+};
+
+/* 802.15.1 radio */
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins &ieee802151_radio_pins>;
+ status = "okay";
+};
+
+&usbotg1 {
+ vbus-supply = <®_usb1_vbus>;
+ dr_mode = "host";
+ disable-over-current;
+ status = "okay";
+};
+
+/* WiFi */
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usdhc1_pins>;
+ vmmc-supply = <®_vdd_3v3>;
+ vqmmc-supply = <®_vdd_1v8>;
+ bus-width = <4>;
+ mmc-pwrseq = <&usdhc1_pwrseq>;
+ status = "okay";
+};
+
+/* microSD */
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&usdhc2_pins>;
+ pinctrl-1 = <&usdhc2_100mhz_pins>;
+ pinctrl-2 = <&usdhc2_200mhz_pins>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ bus-width = <4>;
+ broken-cd;
+ status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+ /*
+ * Use lowest drive strength for all high-speed modes to minimise
+ * electro-magnetic emissions.
+ * In this particular design HS-400 still works okay, no extra
+ * pinctrl for 100mhz and 200mhz are required.
+ */
+ pinctrl-names = "default";
+ pinctrl-0 = <&usdhc3_pins>;
+ vmmc-supply = <®_vdd_3v3>;
+ vqmmc-supply = <®_vdd_1v8>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wdog1_pins>;
+ status = "okay";
+};
--
2.51.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v4 7/8] arm64: dts: add description for solidrun solidsense-n8 board
2025-12-01 13:07 ` [PATCH v4 7/8] arm64: dts: add description for solidrun solidsense-n8 board Josua Mayer
@ 2025-12-01 13:49 ` Andrew Lunn
2025-12-10 14:21 ` Josua Mayer
0 siblings, 1 reply; 11+ messages in thread
From: Andrew Lunn @ 2025-12-01 13:49 UTC (permalink / raw)
To: Josua Mayer
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Dmitry Torokhov, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Jon Nettleton, Mikhail Anikin, Yazan Shhady,
devicetree, linux-kernel, linux-input, imx, linux-arm-kernel
> +&fec1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&fec1_pins>;
> + phy-mode = "rgmii-id";
> + phy-handle = <&phy4>;
> + local-mac-address = [00 00 00 00 00 00];
> + fsl,magic-packet;
Has WoL been tested, or is this copy/paste from the binding
documentation?
> + status = "okay";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /*
> + * Depending on board revision two different phys are used:
> + * - v1.1: atheros phy at address 4
> + * - v1.2+: analog devices phy at address 0
> + * Configure first version by default.
> + * On v1.2 and later, U-Boot will enable the correct phy
> + * based on runtime detection and patch dtb accordingly.
> + */
> +
> + /* ADIN1300 */
> + phy0: ethernet-phy@0 {
> + reg = <0>;
> + reset-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
> + reset-assert-us = <10>;
> + reset-deassert-us = <5000>;
> + interrupt-parent = <&gpio1>;
> + interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
The analog devices PHY has interrupts, so can it implement WoL? Has
this been tested?
> + /* AR8035 */
> + phy4: ethernet-phy@4 {
> + reg = <4>;
> + reset-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
> + reset-assert-us = <10000>;
> + status = "okay";
The Atheros PHY does not interrupts, so i assume it cannot support
WoL? You only have MAC WoL?
Andrew
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v4 7/8] arm64: dts: add description for solidrun solidsense-n8 board
2025-12-01 13:49 ` Andrew Lunn
@ 2025-12-10 14:21 ` Josua Mayer
0 siblings, 0 replies; 11+ messages in thread
From: Josua Mayer @ 2025-12-10 14:21 UTC (permalink / raw)
To: Andrew Lunn
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Dmitry Torokhov, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Jon Nettleton, Mikhail Anikin, Yazan Shhady,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-input@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org
Hi Andrew,
Am 01.12.25 um 14:49 schrieb Andrew Lunn:
>> +&fec1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&fec1_pins>;
>> + phy-mode = "rgmii-id";
>> + phy-handle = <&phy4>;
>> + local-mac-address = [00 00 00 00 00 00];
>> + fsl,magic-packet;
> Has WoL been tested, or is this copy/paste from the binding
> documentation?
This is copy-paste by previous developers which I did not validate.
So I may wish to drop both local-mac-address property
(should be automatic by u-boot),
and drop the magic-packet here.
>
>> + status = "okay";
>> +
>> + mdio {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + /*
>> + * Depending on board revision two different phys are used:
>> + * - v1.1: atheros phy at address 4
>> + * - v1.2+: analog devices phy at address 0
>> + * Configure first version by default.
>> + * On v1.2 and later, U-Boot will enable the correct phy
>> + * based on runtime detection and patch dtb accordingly.
>> + */
>> +
>> + /* ADIN1300 */
>> + phy0: ethernet-phy@0 {
>> + reg = <0>;
>> + reset-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
>> + reset-assert-us = <10>;
>> + reset-deassert-us = <5000>;
>> + interrupt-parent = <&gpio1>;
>> + interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
> The analog devices PHY has interrupts, so can it implement WoL? Has
> this been tested?
Interrupts were tested, WoL was not.
>
>> + /* AR8035 */
>> + phy4: ethernet-phy@4 {
>> + reg = <4>;
>> + reset-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
>> + reset-assert-us = <10000>;
>> + status = "okay";
> The Atheros PHY does not interrupts, so i assume it cannot support
> WoL? You only have MAC WoL?
We have never tested any off states where the phy was still on.
Instead the board is designed to be always-in with supercap to cover
glitches and/or ensure graceful shutdown.
So I suggest dropping any traces of WoL.
regards
Josua Mayer
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v4 8/8] arm64: dts: add description for solidrun i.mx8mm som and evb
2025-12-01 13:07 [PATCH v4 0/8] arm64: dts: add description for solidrun imx8mp hummingboard-iiot Josua Mayer
` (6 preceding siblings ...)
2025-12-01 13:07 ` [PATCH v4 7/8] arm64: dts: add description for solidrun solidsense-n8 board Josua Mayer
@ 2025-12-01 13:07 ` Josua Mayer
7 siblings, 0 replies; 11+ messages in thread
From: Josua Mayer @ 2025-12-01 13:07 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Dmitry Torokhov, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam
Cc: Jon Nettleton, Mikhail Anikin, Yazan Shhady, devicetree,
linux-kernel, linux-input, imx, linux-arm-kernel, Josua Mayer
Add description for the SolidRun i.MX8M Mini SoM on HummingBoard Ripple.
The SoM features:
- 1Gbps Ethernet with PHY
- eMMC
- 1/2GB DDR
- NPU (assembly option)
- WiFi + Bluetooth
The HummingBoard Ripple features:
- 2x USB-2.0 Type-A connector
- 1Gbps RJ45 Ethernet with PoE
- microSD connector
- microHDMI connector
- mpcie connector with USB-2.0 interface + SIM card holder
- microUSB connector for console (using fdtdi chip)
- RTC with backup battery
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/freescale/Makefile | 2 +
.../dts/freescale/imx8mm-hummingboard-ripple.dts | 335 +++++++++++++++++
arch/arm64/boot/dts/freescale/imx8mm-sr-som.dtsi | 395 +++++++++++++++++++++
3 files changed, 732 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index c56137097da3b..3fbc8a1a1bf6e 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -124,6 +124,8 @@ imx8mm-evk-pcie-ep-dtbs += imx8mm-evk.dtb imx-pcie0-ep.dtbo
imx8mm-evkb-pcie-ep-dtbs += imx8mm-evkb.dtb imx-pcie0-ep.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk-pcie-ep.dtb imx8mm-evkb-pcie-ep.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mm-hummingboard-ripple.dtb
+DTC_FLAGS_imx8mm-hummingboard-ripple += -@
dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-iot-gateway.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-hummingboard-ripple.dts b/arch/arm64/boot/dts/freescale/imx8mm-hummingboard-ripple.dts
new file mode 100644
index 0000000000000..110e7ff1ff135
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-hummingboard-ripple.dts
@@ -0,0 +1,335 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+
+#include "imx8mm-sr-som.dtsi"
+
+/ {
+ model = "SolidRun i.MX8MM HummingBoard Ripple";
+ compatible = "solidrun,imx8mm-hummingboard-ripple",
+ "solidrun,imx8mm-sr-som", "fsl,imx8mm";
+
+ aliases {
+ rtc0 = &carrier_rtc;
+ rtc1 = &snvs_rtc;
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+ type = "c";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&adv7535_out>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins>;
+
+ led-0 {
+ label = "D30";
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ };
+
+ led-1 {
+ label = "D31";
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ };
+
+ led-2 {
+ label = "D32";
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ };
+
+ led-3 {
+ label = "D33";
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio5 7 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ };
+
+ led-4 {
+ label = "D34";
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ };
+ };
+
+ rfkill-mpcie-wifi {
+ compatible = "rfkill-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_rfkill_pins>;
+ label = "mpcie WiFi";
+ radio-type = "wlan";
+ /* rfkill-gpio inverts internally */
+ shutdown-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+ };
+
+ vmmc: regulator-mmc {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vmmc_pins>;
+ regulator-name = "vmmc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 19 GPIO_ACTIVE_LOW>;
+ startup-delay-us = <250>;
+ };
+
+ vbus1: regulator-vbus-1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus1";
+ gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vbus1_pins>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vbus2: regulator-vbus-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus2";
+ gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vbus2_pins>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ v_1_2: regulator-1-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "1v2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins>;
+ status = "okay";
+
+ carrier_rtc: rtc@69 {
+ compatible = "abracon,ab1805";
+ reg = <0x69>;
+ abracon,tc-diode = "schottky";
+ abracon,tc-resistor = <3>;
+ };
+
+ carrier_eeprom: eeprom@57{
+ compatible = "st,24c02", "atmel,24c02";
+ reg = <0x57>;
+ pagesize = <16>;
+ };
+
+ hdmi@3d {
+ compatible = "adi,adv7535";
+ reg = <0x3d>, <0x3f>, <0x3c>, <0x38>;
+ reg-names = "main", "edid", "cec", "packet";
+ adi,dsi-lanes = <4>;
+ avdd-supply = <&v_1_8>;
+ dvdd-supply = <&v_1_8>;
+ pvdd-supply = <&v_1_8>;
+ a2vdd-supply = <&v_1_8>;
+ v3p3-supply = <&v_3_3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pins>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
+ pd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ adv7535_from_dsim: endpoint {
+ remote-endpoint = <&mipi_dsi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ adv7535_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+};
+
+&iomuxc {
+ hdmi_pins: pinctrl-hdmi-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x0
+ MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x0
+ >;
+ };
+
+ i2c3_pins: pinctrl-i2c3-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
+ >;
+ };
+
+ led_pins: pinctrl-led-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x0
+ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x0
+ MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x0
+ MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x0
+ MX8MM_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x0
+ >;
+ };
+
+ pcie_rfkill_pins: pinctrl-pcie-rfkill-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x0
+ >;
+ };
+
+ usb_hub_pins: pinctrl-usb-hub-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x0
+ >;
+ };
+
+ usdhc2_pins: pinctrl-usdhc2-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x140
+ MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0
+ >;
+ };
+
+ usdhc2_100mhz_pins: pinctrl-usdhc2-100mhz-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x140
+ MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0
+ >;
+ };
+
+ usdhc2_200mhz_pins: pinctrl-usdhc2-100mhz-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x140
+ MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0
+ >;
+ };
+
+ vbus1_pins: pinctrl-vbus-1-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x20
+ >;
+ };
+
+ vbus2_pins: pinctrl-vbus-2-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x20
+ >;
+ };
+
+ vmmc_pins: pinctrl-vmmc-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
+ >;
+ };
+};
+
+&lcdif {
+ status = "okay";
+};
+
+&mipi_dsi {
+ samsung,esc-clock-frequency = <10000000>;
+ status = "okay";
+};
+
+&mipi_dsi_out {
+ remote-endpoint = <&adv7535_from_dsim>;
+};
+
+&usbotg1 {
+ dr_mode = "host";
+ vbus-supply = <&vbus2>;
+ status = "okay";
+};
+
+&usbotg2 {
+ status = "okay";
+ dr_mode = "host";
+ vbus-supply = <&vbus1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_hub_pins>;
+
+ hub_2_0: hub@1 {
+ compatible = "usb4b4,6502", "usb4b4,6506";
+ reg = <1>;
+ peer-hub = <&hub_3_0>;
+ reset-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&v_1_2>;
+ vdd2-supply = <&v_3_3>;
+ };
+
+ /* this device is not visible because host supports 2.0 only */
+ hub_3_0: hub@2 {
+ compatible = "usb4b4,6500", "usb4b4,6504";
+ reg = <2>;
+ peer-hub = <&hub_2_0>;
+ reset-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&v_1_2>;
+ vdd2-supply = <&v_3_3>;
+ };
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&usdhc2_pins>;
+ pinctrl-1 = <&usdhc2_100mhz_pins>;
+ pinctrl-2 = <&usdhc2_200mhz_pins>;
+ vmmc-supply = <&vmmc>;
+ bus-width = <4>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-sr-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-sr-som.dtsi
new file mode 100644
index 0000000000000..04c16475e64a8
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-sr-som.dtsi
@@ -0,0 +1,395 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ */
+
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+
+#include "imx8mm.dtsi"
+
+/ {
+ model = "SolidRun i.MX8MM SoM";
+ compatible = "solidrun,imx8mm-sr-som", "fsl,imx8mm";
+
+ chosen {
+ bootargs = "earlycon=ec_imx6q,0x30890000,115200";
+ stdout-path = &uart2;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0 0x80000000>;
+ };
+
+ usdhc1_pwrseq: usdhc1-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+ };
+
+ v_1_8: regulator-1-8 {
+ compatible = "regulator-fixed";
+ regulator-name = "1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ v_3_3: regulator-3-3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&fec1_pins>;
+ phy-mode = "rgmii-id";
+ phy = <&phy0>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy0: ethernet-phy@4 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x4>;
+ reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <10>;
+ qca,smarteee-tw-us-1g = <24>;
+ vddio-supply = <&vddio>;
+
+ vddio: vddio-regulator {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ status = "okay";
+
+ som_eeprom: eeprom@50{
+ compatible = "st,24c01", "atmel,24c01";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+
+ pmic@4b {
+ compatible = "rohm,bd71847";
+ reg = <0x4b>;
+ pinctrl-0 = <&pmic_pins>;
+ pinctrl-names = "default";
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+ rohm,reset-snvs-powered;
+
+ #clock-cells = <0>;
+ clocks = <&osc_32k>;
+ clock-output-names = "clk-32k-out";
+
+ regulators {
+ buck1_reg: BUCK1 {
+ regulator-name = "buck1";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ };
+
+ buck2_reg: BUCK2 {
+ regulator-name = "buck2";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ rohm,dvs-run-voltage = <1000000>;
+ rohm,dvs-idle-voltage = <900000>;
+ };
+
+ buck3_reg: BUCK3 {
+ // BUCK5 in datasheet
+ regulator-name = "buck3";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck4_reg: BUCK4 {
+ // BUCK6 in datasheet
+ regulator-name = "buck4";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5_reg: BUCK5 {
+ // BUCK7 in datasheet
+ regulator-name = "buck5";
+ regulator-min-microvolt = <1605000>;
+ regulator-max-microvolt = <1995000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck6_reg: BUCK6 {
+ // BUCK8 in datasheet
+ regulator-name = "buck6";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: LDO1 {
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2_reg: LDO2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3_reg: LDO3 {
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo6_reg: LDO6 {
+ regulator-name = "ldo6";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&iomuxc {
+ fec1_pins: pinctrl-fec1-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
+ MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
+ >;
+ };
+
+ i2c1_pins: pinctrl-i2c1-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
+ >;
+ };
+
+ pcie_pins: pinctrl-pcie-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x0
+ >;
+ };
+
+ pmic_pins: pinctrl-pmic-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x140
+ >;
+ };
+
+ uart1_pins: pinctrl-uart1-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
+ MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
+ MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
+ MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
+ /* BT_REG_ON */
+ MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0
+ /* BT_WAKE_DEV */
+ MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0
+ /* BT_WAKE_HOST */
+ MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x100
+ >;
+ };
+
+ uart2_pins: pinctrl-uart2-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ >;
+ };
+
+ usdhc1_pins: pinctrl-usdhc1-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
+ /* wifi refclk */
+ MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x0
+ /* WL_REG_ON */
+ MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0
+ /* WL_WAKE_HOST */
+ MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x100
+ >;
+ };
+
+ usdhc3_pins: pinctrl-usdhc3-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
+ >;
+ };
+
+ usdhc3_100mhz_pins: pinctrl-usdhc3-100mhz-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
+ >;
+ };
+
+ usdhc3_200mhz_pins: pinctrl-usdhc3-200mhz-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
+ >;
+ };
+
+ wdog1_pins: pinctrl-wdog1-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x140
+ >;
+ };
+};
+
+&pcie_phy {
+ fsl,clkreq-unsupported;
+ fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
+ status = "okay";
+};
+
+/* assembly-option for AI accelerator on SoM, otherwise routed to carrier */
+&pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pins>;
+ reset-gpios = <&gpio1 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ uart-has-rtscts;
+ /* select 80MHz parent clock to support maximum baudrate 4Mbps */
+ assigned-clocks = <&clk IMX8MM_CLK_UART1>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm4330-bt";
+ device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
+ max-speed = <3000000>;
+ };
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usdhc1_pins>;
+ vmmc-supply = <&v_3_3>;
+ vqmmc-supply = <&v_1_8>;
+ bus-width = <4>;
+ mmc-pwrseq = <&usdhc1_pwrseq>;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&usdhc3_pins>;
+ pinctrl-1 = <&usdhc3_100mhz_pins>;
+ pinctrl-2 = <&usdhc3_200mhz_pins>;
+ vmmc-supply = <&v_3_3>;
+ vqmmc-supply = <&v_1_8>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wdog1_pins>;
+ status = "okay";
+};
--
2.51.0
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