From: Breno Rodrigues Alves <breno3011alves@gmail.com>
To: gregkh@linuxfoundation.org
Cc: torvalds@linux-foundation.org, linux-kernel@vger.kernel.org,
arnd@arndb.de, linux-clk@vger.kernel.org,
linux-input@vger.kernel.org, linux-media@vger.kernel.org,
linux-pci@vger.kernel.org, linux-usb@vger.kernel.org,
linux-sound@vger.kernel.org, linux-staging@lists.linux.dev,
linux-fbdev@vger.kernel.org,
linux-security-module@vger.kernel.org,
Breno Rodrigues Alves <breno3011alves@gmail.com>
Subject: [PATCH v2] tree-wide: extirpate seventy-eight orphaned code files
Date: Sat, 5 Sep 2026 10:17:38 -0300 [thread overview]
Message-ID: <20260905131740.7397-1-breno3011alves@gmail.com> (raw)
We have 78 source code files (.c and .h) rotting in the directories
that are completely omitted from local Makefiles. They gate nothing,
compile into nothing, and serve only as ghost weights mimicking active
code when users grep the tree.
This patch cleans up these dead source files completely. All removals
have been fully verified via scripts/checkpatch.pl to ensure no local
include loops are broken and headers_install remains pristine.
Assisted-by: OpenCode AI
Signed-off-by: Breno Rodrigues Alves <breno3011alves@gmail.com>
---
.../amd/amdgpu/dimgrey_cavefish_reg_init.c | 54 -
.../amd/display/dc/dce/dce_scl_filters_old.c | 25 -
.../gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c | 131 -
.../dc/dml2_0/dml21/inc/dml_dmub_cmd.h | 502 -
.../src/dml2_core/dml2_core_dcn6_calcs.c | 11 -
.../dml21/src/dml2_top/dml2_top_legacy.c | 9 -
.../amd/display/dmub/inc/dmub_trace_buffer.h | 68 -
.../drm/amd/display/modules/color/luts_1d.h | 51 -
.../amd/display/modules/inc/mod_color_types.h | 47 -
.../drm/amd/display/modules/inc/mod_stats.h | 75 -
.../amd/include/asic_reg/bif/bif_5_0_enum.h | 1198 -
.../amd/include/asic_reg/bif/bif_5_1_enum.h | 1068 -
.../amd/include/asic_reg/dce/dce_11_2_enum.h | 6813 ----
.../amd/include/asic_reg/dce/dce_8_0_enum.h | 1117 -
.../include/asic_reg/gc/gc_12_1_1_offset.h | 149 -
.../include/asic_reg/gc/gc_12_1_1_sh_mask.h | 377 -
.../amd/include/asic_reg/gc/gc_9_1_sh_mask.h | 31176 ----------------
.../drm/amd/include/asic_reg/gca/gfx_8_1_d.h | 2791 --
.../amd/include/asic_reg/gca/gfx_8_1_enum.h | 6808 ----
.../include/asic_reg/gca/gfx_8_1_sh_mask.h | 21368 -----------
.../amd/include/asic_reg/gmc/gmc_8_1_enum.h | 1198 -
.../amd/include/asic_reg/gmc/gmc_8_2_enum.h | 1068 -
.../include/asic_reg/hdp/hdp_4_4_2_offset.h | 219 -
.../include/asic_reg/hdp/hdp_4_4_2_sh_mask.h | 663 -
.../asic_reg/mmhub/mmhub_9_3_0_offset.h | 1991 -
.../asic_reg/mmhub/mmhub_9_3_0_sh_mask.h | 10265 -----
.../include/asic_reg/mp/mp_11_0_8_sh_mask.h | 355 -
.../include/asic_reg/mp/mp_13_0_5_sh_mask.h | 672 -
.../include/asic_reg/nbif/nbif_6_1_sh_mask.h | 10281 -----
.../amd/include/asic_reg/oss/oss_2_4_enum.h | 1340 -
.../amd/include/asic_reg/oss/oss_3_0_1_enum.h | 1464 -
.../amd/include/asic_reg/oss/oss_3_0_enum.h | 1497 -
.../asic_reg/oss/osssys_4_0_1_offset.h | 337 -
.../asic_reg/oss/osssys_4_0_1_sh_mask.h | 1249 -
.../asic_reg/sdma0/sdma0_4_0_default.h | 286 -
.../asic_reg/sdma0/sdma0_4_1_sh_mask.h | 1658 -
.../asic_reg/sdma1/sdma1_4_0_default.h | 282 -
.../amd/include/asic_reg/smu/smu_7_1_0_d.h | 1344 -
.../amd/include/asic_reg/smu/smu_7_1_0_enum.h | 1191 -
.../include/asic_reg/smu/smu_7_1_0_sh_mask.h | 5648 ---
.../amd/include/asic_reg/smu/smu_7_1_1_enum.h | 1205 -
.../amd/include/asic_reg/smu/smu_7_1_2_enum.h | 1246 -
.../amd/include/asic_reg/smu/smu_7_1_3_enum.h | 1282 -
.../amd/include/asic_reg/smu/smu_8_0_enum.h | 1072 -
.../asic_reg/smuio/smuio_10_0_2_offset.h | 102 -
.../asic_reg/smuio/smuio_10_0_2_sh_mask.h | 184 -
.../include/asic_reg/umc/umc_6_0_default.h | 31 -
.../amd/include/asic_reg/umc/umc_6_0_offset.h | 52 -
.../include/asic_reg/umc/umc_6_1_2_sh_mask.h | 91 -
.../include/asic_reg/uvd/uvd_4_0_sh_mask.h | 793 -
.../amd/include/asic_reg/uvd/uvd_5_0_enum.h | 1211 -
.../amd/include/asic_reg/uvd/uvd_6_0_enum.h | 1081 -
.../include/asic_reg/vcn/vcn_2_6_0_offset.h | 1462 -
.../include/asic_reg/vcn/vcn_2_6_0_sh_mask.h | 4535 ---
.../drm/amd/include/beige_goby_ip_offset.h | 1272 -
drivers/gpu/drm/amd/include/displayobject.h | 249 -
.../gpu/drm/amd/include/navi12_ip_offset.h | 1117 -
.../gpu/drm/amd/include/navi14_ip_offset.h | 1117 -
.../drm/nouveau/include/nvhw/class/cl502d.h | 337 -
.../drm/nouveau/include/nvhw/class/cl902d.h | 357 -
.../drm/nouveau/include/nvkm/engine/msenc.h | 5 -
drivers/gpu/host1x/hw/hw_host1x08_channel.h | 11 -
drivers/net/ethernet/smsc/smc9194.h | 241 -
.../rtlwifi/btcoexist/halbtc8822bwifionly.c | 44 -
.../rtlwifi/btcoexist/halbtc8822bwifionly.h | 14 -
drivers/pcmcia/vg468.h | 106 -
.../raspberrypi/vchiq-mmal/mmal-encodings.h | 124 -
.../raspberrypi/vchiq-mmal/mmal-parameters.h | 752 -
.../Documentation/firmware/authenticate.c | 94 -
drivers/staging/greybus/audio_manager_sysfs.c | 101 -
.../pci/hive_isp_css_include/misc_support.h | 18 -
.../media/ipu7/abi/ipu7_fw_psys_config_abi.h | 24 -
drivers/thermal/thermal-fw.c | 12 -
drivers/thermal/thermal_fw.c | 97 -
drivers/usb/misc/sisusbvga/sisusb_tables.h | 688 -
drivers/usb/phy/phy-mv-usb.h | 160 -
fs/netfs/fscache_internal.h | 14 -
sound/soc/amd/include/acp_2_2_enum.h | 1052 -
78 files changed, 139199 deletions(-)
delete mode 100644 drivers/gpu/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c
delete mode 100644 drivers/gpu/drm/amd/display/dc/dce/dce_scl_filters_old.c
delete mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
delete mode 100644 drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_dmub_cmd.h
delete mode 100644 drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_calcs.c
delete mode 100644 drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_legacy.c
delete mode 100644 drivers/gpu/drm/amd/display/dmub/inc/dmub_trace_buffer.h
delete mode 100644 drivers/gpu/drm/amd/display/modules/color/luts_1d.h
delete mode 100644 drivers/gpu/drm/amd/display/modules/inc/mod_color_types.h
delete mode 100644 drivers/gpu/drm/amd/display/modules/inc/mod_stats.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_enum.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_enum.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_enum.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_enum.h
delete mode 100755 drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_1_offset.h
delete mode 100755 drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_1_sh_mask.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_enum.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_enum.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_enum.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_4_2_offset.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_4_2_sh_mask.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_offset.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_sh_mask.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_8_sh_mask.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_5_sh_mask.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_sh_mask.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_enum.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_enum.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_enum.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_1_offset.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_1_sh_mask.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_default.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_default.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_d.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_enum.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_enum.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_enum.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_enum.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_enum.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_2_offset.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_2_sh_mask.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_default.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_offset.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_2_sh_mask.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_enum.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_enum.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_offset.h
delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h
delete mode 100644 drivers/gpu/drm/amd/include/beige_goby_ip_offset.h
delete mode 100644 drivers/gpu/drm/amd/include/displayobject.h
delete mode 100644 drivers/gpu/drm/amd/include/navi12_ip_offset.h
delete mode 100644 drivers/gpu/drm/amd/include/navi14_ip_offset.h
delete mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/cl502d.h
delete mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/cl902d.h
delete mode 100644 drivers/gpu/drm/nouveau/include/nvkm/engine/msenc.h
delete mode 100644 drivers/gpu/host1x/hw/hw_host1x08_channel.h
delete mode 100644 drivers/net/ethernet/smsc/smc9194.h
delete mode 100644 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8822bwifionly.c
delete mode 100644 drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8822bwifionly.h
delete mode 100644 drivers/pcmcia/vg468.h
delete mode 100644 drivers/platform/raspberrypi/vchiq-mmal/mmal-encodings.h
delete mode 100644 drivers/platform/raspberrypi/vchiq-mmal/mmal-parameters.h
delete mode 100644 drivers/staging/greybus/Documentation/firmware/authenticate.c
delete mode 100644 drivers/staging/greybus/audio_manager_sysfs.c
delete mode 100644 drivers/staging/media/atomisp/pci/hive_isp_css_include/misc_support.h
delete mode 100644 drivers/staging/media/ipu7/abi/ipu7_fw_psys_config_abi.h
delete mode 100644 drivers/thermal/thermal-fw.c
delete mode 100644 drivers/thermal/thermal_fw.c
delete mode 100644 drivers/usb/misc/sisusbvga/sisusb_tables.h
delete mode 100644 drivers/usb/phy/phy-mv-usb.h
delete mode 100644 fs/netfs/fscache_internal.h
delete mode 100644 sound/soc/amd/include/acp_2_2_enum.h
diff --git a/drivers/gpu/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c b/drivers/gpu/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c
deleted file mode 100644
index e9f177e9e..000000000
--- a/drivers/gpu/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright 2020 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#include "amdgpu.h"
-#include "nv.h"
-
-#include "soc15_common.h"
-#include "soc15_hw_ip.h"
-#include "dimgrey_cavefish_ip_offset.h"
-
-int dimgrey_cavefish_reg_base_init(struct amdgpu_device *adev)
-{
- /* HW has more IP blocks, only initialize the block needed by driver */
- uint32_t i;
- for (i = 0 ; i < MAX_INSTANCE ; ++i) {
- adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
- adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
- adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
- adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
- adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
- adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
- adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
- adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN0_BASE.instance[i]));
- adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
- adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCN_BASE.instance[i]));
- adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
- adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
- adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
- adev->reg_offset[SDMA2_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
- adev->reg_offset[SDMA3_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
- adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
- adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
- }
- return 0;
-}
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_scl_filters_old.c b/drivers/gpu/drm/amd/display/dc/dce/dce_scl_filters_old.c
deleted file mode 100644
index bb0e1b80e..000000000
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_scl_filters_old.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright 2012-16 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
deleted file mode 100644
index e9efbb495..000000000
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * Copyright 2012-17 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "reg_helper.h"
-#include "resource.h"
-#include "dwb.h"
-#include "dcn10_dwb.h"
-
-
-#define REG(reg)\
- dwbc10->dwbc_regs->reg
-
-#define CTX \
- dwbc10->base.ctx
-
-#undef FN
-#define FN(reg_name, field_name) \
- dwbc10->dwbc_shift->field_name, dwbc10->dwbc_mask->field_name
-
-#define TO_DCN10_DWBC(dwbc_base) \
- container_of(dwbc_base, struct dcn10_dwbc, base)
-
-static bool dwb1_get_caps(struct dwbc *dwbc, struct dwb_caps *caps)
-{
- (void)dwbc;
- if (caps) {
- caps->adapter_id = 0; /* we only support 1 adapter currently */
- caps->hw_version = DCN_VERSION_1_0;
- caps->num_pipes = 2;
- memset(&caps->reserved, 0, sizeof(caps->reserved));
- memset(&caps->reserved2, 0, sizeof(caps->reserved2));
- caps->sw_version = dwb_ver_1_0;
- caps->caps.support_dwb = true;
- caps->caps.support_ogam = false;
- caps->caps.support_wbscl = true;
- caps->caps.support_ocsc = false;
- return true;
- } else {
- return false;
- }
-}
-
-static bool dwb1_enable(struct dwbc *dwbc, struct dc_dwb_params *params)
-{
- (void)params;
- struct dcn10_dwbc *dwbc10 = TO_DCN10_DWBC(dwbc);
-
- /* disable first. */
- dwbc->funcs->disable(dwbc);
-
- /* disable power gating */
- REG_UPDATE_5(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, 1,
- DISPCLK_G_WB_GATE_DIS, 1, DISPCLK_G_WBSCL_GATE_DIS, 1,
- WB_LB_LS_DIS, 1, WB_LUT_LS_DIS, 1);
-
- REG_UPDATE(WB_ENABLE, WB_ENABLE, 1);
-
- return true;
-}
-
-static bool dwb1_disable(struct dwbc *dwbc)
-{
- struct dcn10_dwbc *dwbc10 = TO_DCN10_DWBC(dwbc);
-
- /* disable CNV */
- REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_EN, 0);
-
- /* disable WB */
- REG_UPDATE(WB_ENABLE, WB_ENABLE, 0);
-
- /* soft reset */
- REG_UPDATE(WB_SOFT_RESET, WB_SOFT_RESET, 1);
- REG_UPDATE(WB_SOFT_RESET, WB_SOFT_RESET, 0);
-
- /* enable power gating */
- REG_UPDATE_5(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, 0,
- DISPCLK_G_WB_GATE_DIS, 0, DISPCLK_G_WBSCL_GATE_DIS, 0,
- WB_LB_LS_DIS, 0, WB_LUT_LS_DIS, 0);
-
- return true;
-}
-
-const struct dwbc_funcs dcn10_dwbc_funcs = {
- .get_caps = dwb1_get_caps,
- .enable = dwb1_enable,
- .disable = dwb1_disable,
- .update = NULL,
- .set_stereo = NULL,
- .set_new_content = NULL,
- .set_warmup = NULL,
- .dwb_set_scaler = NULL,
-};
-
-void dcn10_dwbc_construct(struct dcn10_dwbc *dwbc10,
- struct dc_context *ctx,
- const struct dcn10_dwbc_registers *dwbc_regs,
- const struct dcn10_dwbc_shift *dwbc_shift,
- const struct dcn10_dwbc_mask *dwbc_mask,
- int inst)
-{
- dwbc10->base.ctx = ctx;
-
- dwbc10->base.inst = inst;
- dwbc10->base.funcs = &dcn10_dwbc_funcs;
-
- dwbc10->dwbc_regs = dwbc_regs;
- dwbc10->dwbc_shift = dwbc_shift;
- dwbc10->dwbc_mask = dwbc_mask;
-}
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_dmub_cmd.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_dmub_cmd.h
deleted file mode 100644
index f73d5aa48..000000000
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_dmub_cmd.h
+++ /dev/null
@@ -1,502 +0,0 @@
-// SPDX-License-Identifier: MIT
-//
-// Copyright 2024 Advanced Micro Devices, Inc.
-
-#ifndef DML_DMUB_CMD_H
-#define DML_DMUB_CMD_H
-
- /* always include for now */
-#include <asm/byteorder.h>
-#include <linux/types.h>
-#include <linux/string.h>
-
-#define DMUB_MAX(X, Y) ((X) > (Y) ? (X) : (Y))
-
-#define DMUB_MIN(X, Y) ((X) < (Y) ? (X) : (Y))
-
-/* Define to ensure that the "common" members always appear in the same
- * order in different structs for back compat purposes
- */
-#define COMMON_STREAM_STATIC_SUB_STATE \
- struct dmub_fams2_cmd_legacy_stream_static_state legacy; \
- struct dmub_fams2_cmd_subvp_stream_static_state subvp; \
- struct dmub_fams2_cmd_drr_stream_static_state drr;
-
-/* Maximum number of streams on any ASIC. */
-#define DMUB_MAX_STREAMS 6
-
-/* Maximum number of planes on any ASIC. */
-#define DMUB_MAX_PLANES 6
-
-/* Maximum number of phantom planes on any ASIC */
-#define DMUB_MAX_PHANTOM_PLANES (DMUB_MAX_PLANES) / 2
-
-/* Flattened structure containing SOC BB parameters stored in the VBIOS
- * It is not practical to store the entire bounding box in VBIOS since the bounding box struct can gain new parameters.
- * This also prevents alighment issues when new parameters are added to the SoC BB.
- * The following parameters should be added since these values can't be obtained elsewhere:
- * -dml2_soc_power_management_parameters
- * -dml2_soc_vmin_clock_limits
- */
-struct dmub_soc_bb_params {
- uint32_t dram_clk_change_blackout_ns;
- uint32_t dram_clk_change_read_only_ns;
- uint32_t dram_clk_change_write_only_ns;
- uint32_t fclk_change_blackout_ns;
- uint32_t g7_ppt_blackout_ns;
- uint32_t stutter_enter_plus_exit_latency_ns;
- uint32_t stutter_exit_latency_ns;
- uint32_t z8_stutter_enter_plus_exit_latency_ns;
- uint32_t z8_stutter_exit_latency_ns;
- uint32_t z8_min_idle_time_ns;
- uint32_t type_b_dram_clk_change_blackout_ns;
- uint32_t type_b_ppt_blackout_ns;
- uint32_t vmin_limit_dispclk_khz;
- uint32_t vmin_limit_dcfclk_khz;
- uint32_t g7_temperature_read_blackout_ns;
-};
-
-struct dmub_rect16 {
- /**
- * Dirty rect x offset.
- */
- uint16_t x; // src_x
-
- /**
- * Dirty rect y offset.
- */
- uint16_t y; // src_y
-
- /**
- * Dirty rect width.
- */
- uint16_t width; // dest_width, rect_x
-
- /**
- * Dirty rect height.
- */
- uint16_t height; // dest_height, rect_y
-};
-
-union fw_assisted_mclk_switch_version {
- struct {
- uint8_t minor : 5;
- uint8_t major : 3;
- };
- uint8_t ver;
-};
-
-/* generic structures and enums */
-struct dmub_optc_position {
- uint32_t vpos;
- uint32_t hpos;
- uint32_t frame;
-};
-
-/* HW and FW global configuration data for FAMS2 */
-/* FAMS2 types and structs */
-enum fams2_stream_type {
- FAMS2_STREAM_TYPE_NONE = 0,
- FAMS2_STREAM_TYPE_VBLANK = 1,
- FAMS2_STREAM_TYPE_VACTIVE = 2,
- FAMS2_STREAM_TYPE_DRR = 3,
- FAMS2_STREAM_TYPE_SUBVP = 4,
- FAMS2_STREAM_TYPE_ALTERNATE = 5,
-};
-
-struct plane_pipe_rect {
- struct dmub_rect16 luma;
- struct dmub_rect16 chroma;
-};
-
-/**
- * Structure to hold the LSDMA source / dest copy parameters.
- * Each field is an array of [2][4]:
- * [2] - Instance 0 is the copy for current frame, instance 1 is the copy for next frame (instance 1 potentially unused if no next)
- * [4] - One instance per pipe
- */
-struct lsdma_outputs {
- uint16_t src_x[2][4]; // src x position for the copy. Array of [2][4] for curr vs. next and each pipe
- uint16_t src_y[2][4]; // src y position for the copy
- uint16_t dst_x[2][4]; // dst x position for the copy (can change for curr vs. next)
- uint16_t dst_y[2][4]; // dst y position for the copy (can change for curr vs. next)
- uint16_t width[2][4]; // src and dst width for the copy (src and dst must match)
- uint16_t height[2][4]; // src and dst height for the copy (src and dst must match)
- uint16_t dst_pitch[4]; // dst pitch for the copy (same for curr and next)
-};
-
-struct dmub_fams2_alternate_stream_dynamic_state {
- uint64_t earliest_init_tick; // track earliest possible init tick for calculating is_tick_in_allow
- uint32_t otg_frame_pending_clear[3]; // In this context pending means prefetch has never been completed for this frame yet
- uint8_t flip_pending_clear_order[3];
- uint8_t num_pending_flips;
- uint32_t prefetch_start_line_x1000[3]; // can compute from existing params, but store because we use this multiple times
- uint16_t prefetch_end_line[3]; // can compute from existing params, but store because we use this multiple times
- uint16_t recout_y[3];
- uint8_t flip_pending[3];
- uint8_t copy_from_earliest[3];
- uint16_t lsdma_bandwidth_mbps;
- uint16_t vstartup_line;
- uint16_t vready_line;
- uint8_t cursor_size[3]; // Cursor array per plane for now - if we assume a single cursor, then we don't need an array
- uint8_t pad; // to maintain alignment for below fields - re-arrange structure once all fields are finalized
- /* outputs: */
- uint16_t subvp_start_line_a[3];
- uint16_t subvp_height_a[3];
- uint16_t subvp_next_start_line_a[3];
- uint16_t subvp_next_height_a[3];
- uint16_t subvp_start_line_b[3];
- uint16_t subvp_height_b[3];
- uint16_t subvp_next_start_line_b[3];
- uint16_t subvp_next_height_b[3];
- uint16_t subvp_c_start_line_a[3];
- uint16_t subvp_c_height_a[3];
- uint16_t subvp_c_next_start_line_a[3];
- uint16_t subvp_c_next_height_a[3];
- uint16_t subvp_c_start_line_b[3];
- uint16_t subvp_c_height_b[3];
- uint16_t subvp_c_next_start_line_b[3];
- uint16_t subvp_c_next_height_b[3];
- uint8_t subvp_position[3];
- uint8_t copy_from_primary[3];
- uint8_t pad1[2]; // to maintain alignment for below fields - re-arrange structure once all fields are finalized
- uint32_t program_go_line;
- uint32_t program_go_frame_count;
- uint16_t svp0_start_dst_line;
- uint16_t svp0_end_dst_line;
- uint16_t svp1_start_dst_line;
- uint16_t svp1_end_dst_line;
- struct lsdma_outputs lsdma[2]; // [2] - instance per SVP0 and SVP1
- struct lsdma_outputs lsdma_c[2]; // [2] - instance per SVP0 and SVP1
-};
-
-/* dynamic stream state */
-struct dmub_fams2_legacy_stream_dynamic_state {
- uint8_t force_allow_at_vblank;
- uint8_t pad[3];
-};
-
-struct dmub_fams2_subvp_stream_dynamic_state {
- uint16_t viewport_start_hubp_vline;
- uint16_t viewport_height_hubp_vlines;
- uint16_t viewport_start_c_hubp_vline;
- uint16_t viewport_height_c_hubp_vlines;
- uint16_t phantom_viewport_height_hubp_vlines;
- uint16_t phantom_viewport_height_c_hubp_vlines;
- uint16_t microschedule_start_otg_vline;
- uint16_t mall_start_otg_vline;
- uint16_t mall_start_hubp_vline;
- uint16_t mall_start_c_hubp_vline;
- uint8_t force_allow_at_vblank_only;
- uint8_t swath_height;
- uint8_t swath_height_c;
- uint8_t pad;
-};
-
-struct dmub_fams2_drr_stream_dynamic_state {
- uint16_t stretched_vtotal;
- uint8_t use_cur_vtotal;
- uint8_t pad;
-};
-
-struct dmub_fams2_cmd_alternate_stream_static_state {
- uint32_t total_bytes_to_copy;
- uint16_t svp0_dst_lines; // per stream
- uint16_t svp1_dst_lines; // per stream
- uint16_t min_lead_dst_lines; // per stream, should be max(nominal_req_limit, vstartup_to_vactive). Does not have to be maxed over all planes
- uint16_t svp_req_limit; // per stream, should be the same value in time between all streams max(2 swaths, dst_y_pre) over all planes
- uint16_t fw_delays;
- uint16_t vstartup_start;
- uint16_t rec_height[3];
- uint16_t viewport_start[3];
- uint16_t viewport_size[3]; // for now size will be the number of lines perpendicular to scan direction (height for 0 / 180, width for 90 and 270)
- uint16_t viewport_start_c[3];
- uint16_t viewport_size_c[3];
- uint16_t surface_pitch[3];
- uint16_t surface_pitch_c[3];
- uint16_t surface_height[3];
- uint16_t surface_height_c[3];
- uint8_t element_size[3];
- uint8_t element_size_c[3];
- uint8_t swizzle_mode[3]; // TODO: Add mapping, should be value used in LSDMA command
- uint8_t vready_offset_lines; // vready offset from vstartup in lines (rounded up, as the actual offset may be a fraction of a line)
- uint16_t dst_y_prefetch_x1000[3];
- uint16_t total_swaths[3];
- uint16_t total_swaths_c[3];
- uint8_t prefetch_swaths[3];
- uint8_t prefetch_swaths_c[3];
- uint8_t swath_height[3];
- uint8_t swath_height_c[3];
- uint16_t block_256b_width[3];
- uint16_t block_256b_height[3];
- uint16_t block_256b_width_c[3];
- uint16_t block_256b_height_c[3];
- uint16_t macro_tile_width[3];
- uint16_t macro_tile_width_c[3];
- union {
- struct {
- uint8_t is_multi_planar : 1;
- uint8_t is_yuv420 : 1;
- uint8_t prefetch_relative_vblank : 1;
- uint8_t vertical_access : 1; // vertical_access = 1 means 90 or 270 rotation
- uint8_t access_direction : 1; // access_direction = 1 means bigger to smaller coordinations (e.g., scan from 2160 to 0 as opposed to regular 0 to 2160)
- uint8_t dcc : 1;
- uint8_t tmz : 1; // TODO: Need to assign outside of DML (DML not aware of TMZ)
- } bits;
- uint8_t all;
- } config[3];
- uint8_t max_cursor_size;
- uint16_t pre_hdl_delta_x1000[3];
- uint16_t pre_hdl_delta_c_x1000[3];
- uint16_t rec_hdl_delta_x1000[3];
- uint16_t rec_hdl_delta_c_x1000[3];
- uint16_t dst_y_per_vm_vblank_x1000[3];
- uint16_t dst_y_per_row_vblank_x1000[3];
- uint16_t dst_y_after_scaler[3];
- uint16_t vinit_prefill[3];
- uint16_t vinit_prefill_c[3];
- uint16_t vratio_x1000[3];
- uint16_t vratio_c_x1000[3];
- struct plane_pipe_rect pipe_viewports[4];
- /* TODO - remove these deprecated vars */
- uint32_t pipe_copy_offset[2][4]; // [2] - SVP0/1, [4] - 4 pipes
- uint32_t pipe_copy_offset_c[2][4];
- /* bits 47:16 of the surface address */
- uint32_t pipe_copy_addr_47_16[2][4]; // [2] - SVP0/1, [4] - 4 pipes
- uint32_t pipe_copy_addr_47_16_c[2][4];
- uint32_t pipe_copy_max_size[2][4];
- uint32_t pipe_copy_max_size_c[2][4];
-};
-
-struct dmub_fams2_stream_dynamic_state {
- uint64_t ref_tick;
- uint32_t cur_vtotal;
- uint16_t adjusted_allow_end_otg_vline;
- uint8_t pad[2];
- struct dmub_optc_position ref_otg_pos;
- struct dmub_optc_position target_otg_pos;
- union {
- struct dmub_fams2_legacy_stream_dynamic_state legacy;
- struct dmub_fams2_subvp_stream_dynamic_state subvp;
- struct dmub_fams2_drr_stream_dynamic_state drr;
- struct dmub_fams2_alternate_stream_dynamic_state alternate;
- } sub_state;
-};
-
-/* static stream state */
-struct dmub_fams2_legacy_stream_static_state {
- uint8_t vactive_det_fill_delay_otg_vlines;
- uint8_t programming_delay_otg_vlines;
-}; //v0
-
-struct dmub_fams2_subvp_stream_static_state {
- uint16_t vratio_numerator;
- uint16_t vratio_denominator;
- uint16_t phantom_vtotal;
- uint16_t phantom_vactive;
- union {
- struct {
- uint8_t is_multi_planar : 1;
- uint8_t is_yuv420 : 1;
- } bits;
- uint8_t all;
- } config;
- uint8_t programming_delay_otg_vlines;
- uint8_t prefetch_to_mall_otg_vlines;
- uint8_t phantom_otg_inst;
- uint8_t phantom_pipe_mask;
- uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough)
-}; //v0
-
-struct dmub_fams2_drr_stream_static_state {
- uint16_t nom_stretched_vtotal;
- uint8_t programming_delay_otg_vlines;
- uint8_t only_stretch_if_required;
- uint8_t pad[2];
-}; //v0
-
-struct dmub_fams2_cmd_legacy_stream_static_state {
- uint16_t vactive_det_fill_delay_otg_vlines;
- uint16_t programming_delay_otg_vlines;
- uint32_t disallow_time_us;
-}; //v1
-
-struct dmub_fams2_cmd_subvp_stream_static_state {
- uint16_t vratio_numerator;
- uint16_t vratio_denominator;
- uint16_t phantom_vtotal;
- uint16_t phantom_vactive;
- uint16_t programming_delay_otg_vlines;
- uint16_t prefetch_to_mall_otg_vlines;
- union {
- struct {
- uint8_t is_multi_planar : 1;
- uint8_t is_yuv420 : 1;
- } bits;
- uint8_t all;
- } config;
- uint8_t phantom_otg_inst;
- uint8_t phantom_pipe_mask;
- uint8_t pad0;
- uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough)
- uint8_t pad1[4 - (DMUB_MAX_PHANTOM_PLANES % 4)];
-}; //v1
-
-struct dmub_fams2_cmd_drr_stream_static_state {
- uint16_t nom_stretched_vtotal;
- uint16_t programming_delay_otg_vlines;
- uint8_t only_stretch_if_required;
- uint8_t pad[3];
-}; //v1
-
-union dmub_fams2_stream_static_sub_state {
- struct dmub_fams2_legacy_stream_static_state legacy;
- struct dmub_fams2_subvp_stream_static_state subvp;
- struct dmub_fams2_drr_stream_static_state drr;
-}; //v0
-
-union dmub_fams2_cmd_stream_static_sub_state {
- COMMON_STREAM_STATIC_SUB_STATE
-}; //v1
-
-union dmub_fams2_stream_static_sub_state_v2 {
- COMMON_STREAM_STATIC_SUB_STATE
- struct dmub_fams2_cmd_alternate_stream_static_state alternate;
-}; //v2
-
-struct dmub_fams2_stream_static_state {
- enum fams2_stream_type type;
- uint32_t otg_vline_time_ns;
- uint32_t otg_vline_time_ticks;
- uint16_t htotal;
- uint16_t vtotal; // nominal vtotal
- uint16_t vblank_start;
- uint16_t vblank_end;
- uint16_t max_vtotal;
- uint16_t allow_start_otg_vline;
- uint16_t allow_end_otg_vline;
- uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed
- uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start
- uint8_t contention_delay_otg_vlines; // time to budget for contention on execution
- uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing
- uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline
- union {
- struct {
- uint8_t is_drr : 1; // stream is DRR enabled
- uint8_t clamp_vtotal_min : 1; // clamp vtotal to min instead of nominal
- uint8_t min_ttu_vblank_usable : 1; // if min ttu vblank is above wm, no force pstate is needed in blank
- } bits;
- uint8_t all;
- } config;
- uint8_t otg_inst;
- uint8_t pipe_mask; // pipe mask for the whole config
- uint8_t num_planes;
- uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough)
- uint8_t pad[DMUB_MAX_PLANES % 4];
- union dmub_fams2_stream_static_sub_state sub_state;
-}; //v0
-
-struct dmub_fams2_cmd_stream_static_base_state {
- enum fams2_stream_type type;
- uint32_t otg_vline_time_ns;
- uint32_t otg_vline_time_ticks;
- uint16_t htotal;
- uint16_t vtotal; // nominal vtotal
- uint16_t vblank_start;
- uint16_t vblank_end;
- uint16_t max_vtotal;
- uint16_t allow_start_otg_vline;
- uint16_t allow_end_otg_vline;
- uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed
- uint16_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start
- uint16_t contention_delay_otg_vlines; // time to budget for contention on execution
- uint16_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing
- uint16_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline
- union {
- struct {
- uint8_t is_drr : 1; // stream is DRR enabled
- uint8_t clamp_vtotal_min : 1; // clamp vtotal to min instead of nominal
- uint8_t min_ttu_vblank_usable : 1; // if min ttu vblank is above wm, no force pstate is needed in blank
- } bits;
- uint8_t all;
- } config;
- uint8_t otg_inst;
- uint8_t pipe_mask; // pipe mask for the whole config
- uint8_t num_planes;
- uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough)
- uint8_t pad[DMUB_MAX_PLANES % 4];
-}; //v1
-
-struct dmub_fams2_stream_static_state_v1 {
- struct dmub_fams2_cmd_stream_static_base_state base;
- union dmub_fams2_stream_static_sub_state_v2 sub_state;
-}; //v1
-
-/**
- * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive
- * p-state request to allow latency
- */
-enum dmub_fams2_allow_delay_check_mode {
- /* No check for request to allow delay */
- FAMS2_ALLOW_DELAY_CHECK_NONE = 0,
- /* Check for request to allow delay */
- FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1,
- /* Check for prepare to allow delay */
- FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2,
-};
-
-union dmub_fams2_global_feature_config {
- struct {
- uint32_t enable : 1;
- uint32_t enable_ppt_check : 1;
- uint32_t enable_stall_recovery : 1;
- uint32_t enable_debug : 1;
- uint32_t enable_offload_flip : 1;
- uint32_t enable_visual_confirm : 1;
- uint32_t allow_delay_check_mode : 2;
- uint32_t legacy_method_no_fams2 : 1;
- uint32_t reserved : 23;
- } bits;
- uint32_t all;
-};
-
-struct dmub_cmd_fams2_global_config {
- uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin
- uint32_t lock_wait_time_us; // time to forecast acquisition of lock
- uint32_t num_streams;
- union dmub_fams2_global_feature_config features;
- uint32_t recovery_timeout_us;
- uint32_t hwfq_flip_programming_delay_us;
- uint32_t max_allow_to_target_delta_us; // how early DCN could assert P-State allow compared to the P-State target
-};
-
-union dmub_cmd_fams2_config {
- struct dmub_cmd_fams2_global_config global;
- struct dmub_fams2_stream_static_state stream; //v0
- union {
- struct dmub_fams2_cmd_stream_static_base_state base;
- union dmub_fams2_cmd_stream_static_sub_state sub_state;
- } stream_v1; //v1
-};
-
-struct dmub_fams2_config_v2 {
- struct dmub_cmd_fams2_global_config global;
- struct dmub_fams2_stream_static_state_v1 stream_v1[DMUB_MAX_STREAMS]; //v1
-};
-
-/**
- * OS/FW agnostic memcpy
- */
-#ifndef dmub_memcpy
-#define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes))
-#endif
-
- /**
- * OS/FW agnostic memset
- */
-#ifndef dmub_memset
-#define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes))
-#endif
-
- //#endif
-#endif /* _DML_DMUB_CMD_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_calcs.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_calcs.c
deleted file mode 100644
index c86e9c5fe..000000000
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_calcs.c
+++ /dev/null
@@ -1,11 +0,0 @@
-// SPDX-License-Identifier: MIT
-//
-// Copyright 2026 Advanced Micro Devices, Inc.
-
-#include "dml2_core_dcn6_calcs.h"
-
-/*
- * Placeholder for future DCN6 calcs table implementation.
- * Remove this typedef once real declarations are added here.
- */
-typedef int dml2_core_dcn6_calcs_placeholder;
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_legacy.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_legacy.c
deleted file mode 100644
index 0e3177fe9..000000000
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_legacy.c
+++ /dev/null
@@ -1,9 +0,0 @@
-// SPDX-License-Identifier: MIT
-//
-// Copyright 2024 Advanced Micro Devices, Inc.
-
-#include "dml2_top_legacy.h"
-#include "dml2_core_factory.h"
-#include "dml2_pmo_factory.h"
-#include "display_mode_core_structs.h"
-
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_trace_buffer.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_trace_buffer.h
deleted file mode 100644
index 8a122ceab..000000000
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_trace_buffer.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * Copyright 2019 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-#ifndef _DMUB_TRACE_BUFFER_H_
-#define _DMUB_TRACE_BUFFER_H_
-
-#include "dmub_cmd.h"
-
-#define LOAD_DMCU_FW 1
-#define LOAD_PHY_FW 2
-
-
-enum dmucb_trace_code {
- DMCUB__UNKNOWN,
- DMCUB__MAIN_BEGIN,
- DMCUB__PHY_INIT_BEGIN,
- DMCUB__PHY_FW_SRAM_LOAD_BEGIN,
- DMCUB__PHY_FW_SRAM_LOAD_END,
- DMCUB__PHY_INIT_POLL_DONE,
- DMCUB__PHY_INIT_END,
- DMCUB__DMCU_ERAM_LOAD_BEGIN,
- DMCUB__DMCU_ERAM_LOAD_END,
- DMCUB__DMCU_ISR_LOAD_BEGIN,
- DMCUB__DMCU_ISR_LOAD_END,
- DMCUB__MAIN_IDLE,
- DMCUB__PERF_TRACE,
- DMCUB__PG_DONE,
-};
-
-struct dmcub_trace_buf_entry {
- enum dmucb_trace_code trace_code;
- uint32_t tick_count;
- uint32_t param0;
- uint32_t param1;
-};
-
-#define TRACE_BUF_SIZE (1024) //1 kB
-#define PERF_TRACE_MAX_ENTRY ((TRACE_BUF_SIZE - 8)/sizeof(struct dmcub_trace_buf_entry))
-
-
-struct dmcub_trace_buf {
- uint32_t entry_count;
- uint32_t clk_freq;
- struct dmcub_trace_buf_entry entries[PERF_TRACE_MAX_ENTRY];
-};
-
-#endif /* _DMUB_TRACE_BUFFER_H_ */
diff --git a/drivers/gpu/drm/amd/display/modules/color/luts_1d.h b/drivers/gpu/drm/amd/display/modules/color/luts_1d.h
deleted file mode 100644
index 66b1fad57..000000000
--- a/drivers/gpu/drm/amd/display/modules/color/luts_1d.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright 2016 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-#ifndef LUTS_1D_H
-#define LUTS_1D_H
-
-#include "hw_shared.h"
-
-struct point_config {
- uint32_t custom_float_x;
- uint32_t custom_float_y;
- uint32_t custom_float_slope;
-};
-
-struct lut_point {
- uint32_t red;
- uint32_t green;
- uint32_t blue;
- uint32_t delta_red;
- uint32_t delta_green;
- uint32_t delta_blue;
-};
-
-struct pwl_1dlut_parameter {
- struct gamma_curve arr_curve_points[34];
- struct point_config arr_points[2];
- struct lut_point rgb_resulted[256];
- uint32_t hw_points_num;
-};
-#endif // LUTS_1D_H
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_color_types.h b/drivers/gpu/drm/amd/display/modules/inc/mod_color_types.h
deleted file mode 100644
index bf7313df5..000000000
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_color_types.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright 2019 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef MOD_COLOR_TYPES_H_
-#define MOD_COLOR_TYPES_H_
-
-enum predefined_gamut_type {
- gamut_type_bt709,
- gamut_type_bt601,
- gamut_type_adobe_rgb,
- gamut_type_srgb,
- gamut_type_bt2020,
- gamut_type_dcip3,
- gamut_type_unknown,
-};
-
-enum predefined_white_point_type {
- white_point_type_5000k_horizon,
- white_point_type_6500k_noon,
- white_point_type_7500k_north_sky,
- white_point_type_9300k,
- white_point_type_unknown,
-};
-
-#endif /* MOD_COLOR_TYPES_H_ */
\ No newline at end of file
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_stats.h b/drivers/gpu/drm/amd/display/modules/inc/mod_stats.h
deleted file mode 100644
index 8ce6c22e5..000000000
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_stats.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Copyright 2016 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef MODULES_INC_MOD_STATS_H_
-#define MODULES_INC_MOD_STATS_H_
-
-#include "dm_services.h"
-
-struct mod_stats {
- int dummy;
-};
-
-struct mod_stats_caps {
- bool dummy;
-};
-
-struct mod_stats_init_params {
- unsigned int stats_enable;
- unsigned int stats_entries;
-};
-
-struct mod_stats *mod_stats_create(struct dc *dc,
- struct mod_stats_init_params *init_params);
-
-void mod_stats_destroy(struct mod_stats *mod_stats);
-
-bool mod_stats_init(struct mod_stats *mod_stats);
-
-void mod_stats_dump(struct mod_stats *mod_stats);
-
-void mod_stats_reset_data(struct mod_stats *mod_stats);
-
-void mod_stats_update_event(struct mod_stats *mod_stats,
- const char *event_string,
- unsigned int length);
-
-void mod_stats_update_flip(struct mod_stats *mod_stats,
- unsigned long long timestamp_in_ns);
-
-void mod_stats_update_vupdate(struct mod_stats *mod_stats,
- unsigned long long timestamp_in_ns);
-
-void mod_stats_update_freesync(struct mod_stats *mod_stats,
- unsigned int v_total_min,
- unsigned int v_total_max,
- unsigned int event_triggers,
- unsigned int window_min,
- unsigned int window_max,
- unsigned int lfc_mid_point_in_us,
- unsigned int inserted_frames,
- unsigned int inserted_frame_duration_in_us);
-
-#endif /* MODULES_INC_MOD_STATS_H_ */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_enum.h
deleted file mode 100644
index 46b75f4bb..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_enum.h
+++ /dev/null
@@ -1,1198 +0,0 @@
-/*
- * BIF_5_0 Register documentation
- *
- * Copyright (C) 2014 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef BIF_5_0_ENUM_H
-#define BIF_5_0_ENUM_H
-
-typedef enum SurfaceEndian {
- ENDIAN_NONE = 0x0,
- ENDIAN_8IN16 = 0x1,
- ENDIAN_8IN32 = 0x2,
- ENDIAN_8IN64 = 0x3,
-} SurfaceEndian;
-typedef enum ArrayMode {
- ARRAY_LINEAR_GENERAL = 0x0,
- ARRAY_LINEAR_ALIGNED = 0x1,
- ARRAY_1D_TILED_THIN1 = 0x2,
- ARRAY_1D_TILED_THICK = 0x3,
- ARRAY_2D_TILED_THIN1 = 0x4,
- ARRAY_PRT_TILED_THIN1 = 0x5,
- ARRAY_PRT_2D_TILED_THIN1 = 0x6,
- ARRAY_2D_TILED_THICK = 0x7,
- ARRAY_2D_TILED_XTHICK = 0x8,
- ARRAY_PRT_TILED_THICK = 0x9,
- ARRAY_PRT_2D_TILED_THICK = 0xa,
- ARRAY_PRT_3D_TILED_THIN1 = 0xb,
- ARRAY_3D_TILED_THIN1 = 0xc,
- ARRAY_3D_TILED_THICK = 0xd,
- ARRAY_3D_TILED_XTHICK = 0xe,
- ARRAY_PRT_3D_TILED_THICK = 0xf,
-} ArrayMode;
-typedef enum PipeTiling {
- CONFIG_1_PIPE = 0x0,
- CONFIG_2_PIPE = 0x1,
- CONFIG_4_PIPE = 0x2,
- CONFIG_8_PIPE = 0x3,
-} PipeTiling;
-typedef enum BankTiling {
- CONFIG_4_BANK = 0x0,
- CONFIG_8_BANK = 0x1,
-} BankTiling;
-typedef enum GroupInterleave {
- CONFIG_256B_GROUP = 0x0,
- CONFIG_512B_GROUP = 0x1,
-} GroupInterleave;
-typedef enum RowTiling {
- CONFIG_1KB_ROW = 0x0,
- CONFIG_2KB_ROW = 0x1,
- CONFIG_4KB_ROW = 0x2,
- CONFIG_8KB_ROW = 0x3,
- CONFIG_1KB_ROW_OPT = 0x4,
- CONFIG_2KB_ROW_OPT = 0x5,
- CONFIG_4KB_ROW_OPT = 0x6,
- CONFIG_8KB_ROW_OPT = 0x7,
-} RowTiling;
-typedef enum BankSwapBytes {
- CONFIG_128B_SWAPS = 0x0,
- CONFIG_256B_SWAPS = 0x1,
- CONFIG_512B_SWAPS = 0x2,
- CONFIG_1KB_SWAPS = 0x3,
-} BankSwapBytes;
-typedef enum SampleSplitBytes {
- CONFIG_1KB_SPLIT = 0x0,
- CONFIG_2KB_SPLIT = 0x1,
- CONFIG_4KB_SPLIT = 0x2,
- CONFIG_8KB_SPLIT = 0x3,
-} SampleSplitBytes;
-typedef enum NumPipes {
- ADDR_CONFIG_1_PIPE = 0x0,
- ADDR_CONFIG_2_PIPE = 0x1,
- ADDR_CONFIG_4_PIPE = 0x2,
- ADDR_CONFIG_8_PIPE = 0x3,
-} NumPipes;
-typedef enum PipeInterleaveSize {
- ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
- ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
-} PipeInterleaveSize;
-typedef enum BankInterleaveSize {
- ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
- ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
- ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
- ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
-} BankInterleaveSize;
-typedef enum NumShaderEngines {
- ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
- ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
-} NumShaderEngines;
-typedef enum ShaderEngineTileSize {
- ADDR_CONFIG_SE_TILE_16 = 0x0,
- ADDR_CONFIG_SE_TILE_32 = 0x1,
-} ShaderEngineTileSize;
-typedef enum NumGPUs {
- ADDR_CONFIG_1_GPU = 0x0,
- ADDR_CONFIG_2_GPU = 0x1,
- ADDR_CONFIG_4_GPU = 0x2,
-} NumGPUs;
-typedef enum MultiGPUTileSize {
- ADDR_CONFIG_GPU_TILE_16 = 0x0,
- ADDR_CONFIG_GPU_TILE_32 = 0x1,
- ADDR_CONFIG_GPU_TILE_64 = 0x2,
- ADDR_CONFIG_GPU_TILE_128 = 0x3,
-} MultiGPUTileSize;
-typedef enum RowSize {
- ADDR_CONFIG_1KB_ROW = 0x0,
- ADDR_CONFIG_2KB_ROW = 0x1,
- ADDR_CONFIG_4KB_ROW = 0x2,
-} RowSize;
-typedef enum NumLowerPipes {
- ADDR_CONFIG_1_LOWER_PIPES = 0x0,
- ADDR_CONFIG_2_LOWER_PIPES = 0x1,
-} NumLowerPipes;
-typedef enum DebugBlockId {
- DBG_CLIENT_BLKID_RESERVED = 0x0,
- DBG_CLIENT_BLKID_dbg = 0x1,
- DBG_CLIENT_BLKID_scf2 = 0x2,
- DBG_CLIENT_BLKID_mcd5 = 0x3,
- DBG_CLIENT_BLKID_vmc = 0x4,
- DBG_CLIENT_BLKID_sx30 = 0x5,
- DBG_CLIENT_BLKID_mcd2 = 0x6,
- DBG_CLIENT_BLKID_bci1 = 0x7,
- DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0x8,
- DBG_CLIENT_BLKID_mcc0 = 0x9,
- DBG_CLIENT_BLKID_uvdf_0 = 0xa,
- DBG_CLIENT_BLKID_uvdf_1 = 0xb,
- DBG_CLIENT_BLKID_uvdf_2 = 0xc,
- DBG_CLIENT_BLKID_uvdi_0 = 0xd,
- DBG_CLIENT_BLKID_bci0 = 0xe,
- DBG_CLIENT_BLKID_vcec0_0 = 0xf,
- DBG_CLIENT_BLKID_cb100 = 0x10,
- DBG_CLIENT_BLKID_cb001 = 0x11,
- DBG_CLIENT_BLKID_mcd4 = 0x12,
- DBG_CLIENT_BLKID_tmonw00 = 0x13,
- DBG_CLIENT_BLKID_cb101 = 0x14,
- DBG_CLIENT_BLKID_sx10 = 0x15,
- DBG_CLIENT_BLKID_cb301 = 0x16,
- DBG_CLIENT_BLKID_tmonw01 = 0x17,
- DBG_CLIENT_BLKID_vcea0_0 = 0x18,
- DBG_CLIENT_BLKID_vcea0_1 = 0x19,
- DBG_CLIENT_BLKID_vcea0_2 = 0x1a,
- DBG_CLIENT_BLKID_vcea0_3 = 0x1b,
- DBG_CLIENT_BLKID_scf1 = 0x1c,
- DBG_CLIENT_BLKID_sx20 = 0x1d,
- DBG_CLIENT_BLKID_spim1 = 0x1e,
- DBG_CLIENT_BLKID_pa10 = 0x1f,
- DBG_CLIENT_BLKID_pa00 = 0x20,
- DBG_CLIENT_BLKID_gmcon = 0x21,
- DBG_CLIENT_BLKID_mcb = 0x22,
- DBG_CLIENT_BLKID_vgt0 = 0x23,
- DBG_CLIENT_BLKID_pc0 = 0x24,
- DBG_CLIENT_BLKID_bci2 = 0x25,
- DBG_CLIENT_BLKID_uvdb_0 = 0x26,
- DBG_CLIENT_BLKID_spim3 = 0x27,
- DBG_CLIENT_BLKID_cpc_0 = 0x28,
- DBG_CLIENT_BLKID_cpc_1 = 0x29,
- DBG_CLIENT_BLKID_uvdm_0 = 0x2a,
- DBG_CLIENT_BLKID_uvdm_1 = 0x2b,
- DBG_CLIENT_BLKID_uvdm_2 = 0x2c,
- DBG_CLIENT_BLKID_uvdm_3 = 0x2d,
- DBG_CLIENT_BLKID_cb000 = 0x2e,
- DBG_CLIENT_BLKID_spim0 = 0x2f,
- DBG_CLIENT_BLKID_mcc2 = 0x30,
- DBG_CLIENT_BLKID_ds0 = 0x31,
- DBG_CLIENT_BLKID_srbm = 0x32,
- DBG_CLIENT_BLKID_ih = 0x33,
- DBG_CLIENT_BLKID_sem = 0x34,
- DBG_CLIENT_BLKID_sdma_0 = 0x35,
- DBG_CLIENT_BLKID_sdma_1 = 0x36,
- DBG_CLIENT_BLKID_hdp = 0x37,
- DBG_CLIENT_BLKID_acp_0 = 0x38,
- DBG_CLIENT_BLKID_acp_1 = 0x39,
- DBG_CLIENT_BLKID_cb200 = 0x3a,
- DBG_CLIENT_BLKID_scf3 = 0x3b,
- DBG_CLIENT_BLKID_vceb1_0 = 0x3c,
- DBG_CLIENT_BLKID_vcea1_0 = 0x3d,
- DBG_CLIENT_BLKID_vcea1_1 = 0x3e,
- DBG_CLIENT_BLKID_vcea1_2 = 0x3f,
- DBG_CLIENT_BLKID_vcea1_3 = 0x40,
- DBG_CLIENT_BLKID_bci3 = 0x41,
- DBG_CLIENT_BLKID_mcd0 = 0x42,
- DBG_CLIENT_BLKID_pa11 = 0x43,
- DBG_CLIENT_BLKID_pa01 = 0x44,
- DBG_CLIENT_BLKID_cb201 = 0x45,
- DBG_CLIENT_BLKID_spim2 = 0x46,
- DBG_CLIENT_BLKID_vgt2 = 0x47,
- DBG_CLIENT_BLKID_pc2 = 0x48,
- DBG_CLIENT_BLKID_smu_0 = 0x49,
- DBG_CLIENT_BLKID_smu_1 = 0x4a,
- DBG_CLIENT_BLKID_smu_2 = 0x4b,
- DBG_CLIENT_BLKID_cb1 = 0x4c,
- DBG_CLIENT_BLKID_ia0 = 0x4d,
- DBG_CLIENT_BLKID_wd = 0x4e,
- DBG_CLIENT_BLKID_ia1 = 0x4f,
- DBG_CLIENT_BLKID_vcec1_0 = 0x50,
- DBG_CLIENT_BLKID_scf0 = 0x51,
- DBG_CLIENT_BLKID_vgt1 = 0x52,
- DBG_CLIENT_BLKID_pc1 = 0x53,
- DBG_CLIENT_BLKID_cb0 = 0x54,
- DBG_CLIENT_BLKID_gdc_one_0 = 0x55,
- DBG_CLIENT_BLKID_gdc_one_1 = 0x56,
- DBG_CLIENT_BLKID_gdc_one_2 = 0x57,
- DBG_CLIENT_BLKID_gdc_one_3 = 0x58,
- DBG_CLIENT_BLKID_gdc_one_4 = 0x59,
- DBG_CLIENT_BLKID_gdc_one_5 = 0x5a,
- DBG_CLIENT_BLKID_gdc_one_6 = 0x5b,
- DBG_CLIENT_BLKID_gdc_one_7 = 0x5c,
- DBG_CLIENT_BLKID_gdc_one_8 = 0x5d,
- DBG_CLIENT_BLKID_gdc_one_9 = 0x5e,
- DBG_CLIENT_BLKID_gdc_one_10 = 0x5f,
- DBG_CLIENT_BLKID_gdc_one_11 = 0x60,
- DBG_CLIENT_BLKID_gdc_one_12 = 0x61,
- DBG_CLIENT_BLKID_gdc_one_13 = 0x62,
- DBG_CLIENT_BLKID_gdc_one_14 = 0x63,
- DBG_CLIENT_BLKID_gdc_one_15 = 0x64,
- DBG_CLIENT_BLKID_gdc_one_16 = 0x65,
- DBG_CLIENT_BLKID_gdc_one_17 = 0x66,
- DBG_CLIENT_BLKID_gdc_one_18 = 0x67,
- DBG_CLIENT_BLKID_gdc_one_19 = 0x68,
- DBG_CLIENT_BLKID_gdc_one_20 = 0x69,
- DBG_CLIENT_BLKID_gdc_one_21 = 0x6a,
- DBG_CLIENT_BLKID_gdc_one_22 = 0x6b,
- DBG_CLIENT_BLKID_gdc_one_23 = 0x6c,
- DBG_CLIENT_BLKID_gdc_one_24 = 0x6d,
- DBG_CLIENT_BLKID_gdc_one_25 = 0x6e,
- DBG_CLIENT_BLKID_gdc_one_26 = 0x6f,
- DBG_CLIENT_BLKID_gdc_one_27 = 0x70,
- DBG_CLIENT_BLKID_gdc_one_28 = 0x71,
- DBG_CLIENT_BLKID_gdc_one_29 = 0x72,
- DBG_CLIENT_BLKID_gdc_one_30 = 0x73,
- DBG_CLIENT_BLKID_gdc_one_31 = 0x74,
- DBG_CLIENT_BLKID_gdc_one_32 = 0x75,
- DBG_CLIENT_BLKID_gdc_one_33 = 0x76,
- DBG_CLIENT_BLKID_gdc_one_34 = 0x77,
- DBG_CLIENT_BLKID_gdc_one_35 = 0x78,
- DBG_CLIENT_BLKID_vceb0_0 = 0x79,
- DBG_CLIENT_BLKID_vgt3 = 0x7a,
- DBG_CLIENT_BLKID_pc3 = 0x7b,
- DBG_CLIENT_BLKID_mcd3 = 0x7c,
- DBG_CLIENT_BLKID_uvdu_0 = 0x7d,
- DBG_CLIENT_BLKID_uvdu_1 = 0x7e,
- DBG_CLIENT_BLKID_uvdu_2 = 0x7f,
- DBG_CLIENT_BLKID_uvdu_3 = 0x80,
- DBG_CLIENT_BLKID_uvdu_4 = 0x81,
- DBG_CLIENT_BLKID_uvdu_5 = 0x82,
- DBG_CLIENT_BLKID_uvdu_6 = 0x83,
- DBG_CLIENT_BLKID_cb300 = 0x84,
- DBG_CLIENT_BLKID_mcd1 = 0x85,
- DBG_CLIENT_BLKID_sx00 = 0x86,
- DBG_CLIENT_BLKID_uvdc_0 = 0x87,
- DBG_CLIENT_BLKID_uvdc_1 = 0x88,
- DBG_CLIENT_BLKID_mcc3 = 0x89,
- DBG_CLIENT_BLKID_cpg_0 = 0x8a,
- DBG_CLIENT_BLKID_cpg_1 = 0x8b,
- DBG_CLIENT_BLKID_gck = 0x8c,
- DBG_CLIENT_BLKID_mcc1 = 0x8d,
- DBG_CLIENT_BLKID_cpf_0 = 0x8e,
- DBG_CLIENT_BLKID_cpf_1 = 0x8f,
- DBG_CLIENT_BLKID_rlc = 0x90,
- DBG_CLIENT_BLKID_grbm = 0x91,
- DBG_CLIENT_BLKID_sammsp = 0x92,
- DBG_CLIENT_BLKID_dci_pg = 0x93,
- DBG_CLIENT_BLKID_dci_0 = 0x94,
- DBG_CLIENT_BLKID_dccg0_0 = 0x95,
- DBG_CLIENT_BLKID_dccg0_1 = 0x96,
- DBG_CLIENT_BLKID_dcfe01_0 = 0x97,
- DBG_CLIENT_BLKID_dcfe02_0 = 0x98,
- DBG_CLIENT_BLKID_dcfe03_0 = 0x99,
- DBG_CLIENT_BLKID_dcfe04_0 = 0x9a,
- DBG_CLIENT_BLKID_dcfe05_0 = 0x9b,
- DBG_CLIENT_BLKID_dcfe06_0 = 0x9c,
- DBG_CLIENT_BLKID_RESERVED_LAST = 0x9d,
-} DebugBlockId;
-typedef enum DebugBlockId_OLD {
- DBG_BLOCK_ID_RESERVED = 0x0,
- DBG_BLOCK_ID_DBG = 0x1,
- DBG_BLOCK_ID_VMC = 0x2,
- DBG_BLOCK_ID_PDMA = 0x3,
- DBG_BLOCK_ID_CG = 0x4,
- DBG_BLOCK_ID_SRBM = 0x5,
- DBG_BLOCK_ID_GRBM = 0x6,
- DBG_BLOCK_ID_RLC = 0x7,
- DBG_BLOCK_ID_CSC = 0x8,
- DBG_BLOCK_ID_SEM = 0x9,
- DBG_BLOCK_ID_IH = 0xa,
- DBG_BLOCK_ID_SC = 0xb,
- DBG_BLOCK_ID_SQ = 0xc,
- DBG_BLOCK_ID_AVP = 0xd,
- DBG_BLOCK_ID_GMCON = 0xe,
- DBG_BLOCK_ID_SMU = 0xf,
- DBG_BLOCK_ID_DMA0 = 0x10,
- DBG_BLOCK_ID_DMA1 = 0x11,
- DBG_BLOCK_ID_SPIM = 0x12,
- DBG_BLOCK_ID_GDS = 0x13,
- DBG_BLOCK_ID_SPIS = 0x14,
- DBG_BLOCK_ID_UNUSED0 = 0x15,
- DBG_BLOCK_ID_PA0 = 0x16,
- DBG_BLOCK_ID_PA1 = 0x17,
- DBG_BLOCK_ID_CP0 = 0x18,
- DBG_BLOCK_ID_CP1 = 0x19,
- DBG_BLOCK_ID_CP2 = 0x1a,
- DBG_BLOCK_ID_UNUSED1 = 0x1b,
- DBG_BLOCK_ID_UVDU = 0x1c,
- DBG_BLOCK_ID_UVDM = 0x1d,
- DBG_BLOCK_ID_VCE = 0x1e,
- DBG_BLOCK_ID_UNUSED2 = 0x1f,
- DBG_BLOCK_ID_VGT0 = 0x20,
- DBG_BLOCK_ID_VGT1 = 0x21,
- DBG_BLOCK_ID_IA = 0x22,
- DBG_BLOCK_ID_UNUSED3 = 0x23,
- DBG_BLOCK_ID_SCT0 = 0x24,
- DBG_BLOCK_ID_SCT1 = 0x25,
- DBG_BLOCK_ID_SPM0 = 0x26,
- DBG_BLOCK_ID_SPM1 = 0x27,
- DBG_BLOCK_ID_TCAA = 0x28,
- DBG_BLOCK_ID_TCAB = 0x29,
- DBG_BLOCK_ID_TCCA = 0x2a,
- DBG_BLOCK_ID_TCCB = 0x2b,
- DBG_BLOCK_ID_MCC0 = 0x2c,
- DBG_BLOCK_ID_MCC1 = 0x2d,
- DBG_BLOCK_ID_MCC2 = 0x2e,
- DBG_BLOCK_ID_MCC3 = 0x2f,
- DBG_BLOCK_ID_SX0 = 0x30,
- DBG_BLOCK_ID_SX1 = 0x31,
- DBG_BLOCK_ID_SX2 = 0x32,
- DBG_BLOCK_ID_SX3 = 0x33,
- DBG_BLOCK_ID_UNUSED4 = 0x34,
- DBG_BLOCK_ID_UNUSED5 = 0x35,
- DBG_BLOCK_ID_UNUSED6 = 0x36,
- DBG_BLOCK_ID_UNUSED7 = 0x37,
- DBG_BLOCK_ID_PC0 = 0x38,
- DBG_BLOCK_ID_PC1 = 0x39,
- DBG_BLOCK_ID_UNUSED8 = 0x3a,
- DBG_BLOCK_ID_UNUSED9 = 0x3b,
- DBG_BLOCK_ID_UNUSED10 = 0x3c,
- DBG_BLOCK_ID_UNUSED11 = 0x3d,
- DBG_BLOCK_ID_MCB = 0x3e,
- DBG_BLOCK_ID_UNUSED12 = 0x3f,
- DBG_BLOCK_ID_SCB0 = 0x40,
- DBG_BLOCK_ID_SCB1 = 0x41,
- DBG_BLOCK_ID_UNUSED13 = 0x42,
- DBG_BLOCK_ID_UNUSED14 = 0x43,
- DBG_BLOCK_ID_SCF0 = 0x44,
- DBG_BLOCK_ID_SCF1 = 0x45,
- DBG_BLOCK_ID_UNUSED15 = 0x46,
- DBG_BLOCK_ID_UNUSED16 = 0x47,
- DBG_BLOCK_ID_BCI0 = 0x48,
- DBG_BLOCK_ID_BCI1 = 0x49,
- DBG_BLOCK_ID_BCI2 = 0x4a,
- DBG_BLOCK_ID_BCI3 = 0x4b,
- DBG_BLOCK_ID_UNUSED17 = 0x4c,
- DBG_BLOCK_ID_UNUSED18 = 0x4d,
- DBG_BLOCK_ID_UNUSED19 = 0x4e,
- DBG_BLOCK_ID_UNUSED20 = 0x4f,
- DBG_BLOCK_ID_CB00 = 0x50,
- DBG_BLOCK_ID_CB01 = 0x51,
- DBG_BLOCK_ID_CB02 = 0x52,
- DBG_BLOCK_ID_CB03 = 0x53,
- DBG_BLOCK_ID_CB04 = 0x54,
- DBG_BLOCK_ID_UNUSED21 = 0x55,
- DBG_BLOCK_ID_UNUSED22 = 0x56,
- DBG_BLOCK_ID_UNUSED23 = 0x57,
- DBG_BLOCK_ID_CB10 = 0x58,
- DBG_BLOCK_ID_CB11 = 0x59,
- DBG_BLOCK_ID_CB12 = 0x5a,
- DBG_BLOCK_ID_CB13 = 0x5b,
- DBG_BLOCK_ID_CB14 = 0x5c,
- DBG_BLOCK_ID_UNUSED24 = 0x5d,
- DBG_BLOCK_ID_UNUSED25 = 0x5e,
- DBG_BLOCK_ID_UNUSED26 = 0x5f,
- DBG_BLOCK_ID_TCP0 = 0x60,
- DBG_BLOCK_ID_TCP1 = 0x61,
- DBG_BLOCK_ID_TCP2 = 0x62,
- DBG_BLOCK_ID_TCP3 = 0x63,
- DBG_BLOCK_ID_TCP4 = 0x64,
- DBG_BLOCK_ID_TCP5 = 0x65,
- DBG_BLOCK_ID_TCP6 = 0x66,
- DBG_BLOCK_ID_TCP7 = 0x67,
- DBG_BLOCK_ID_TCP8 = 0x68,
- DBG_BLOCK_ID_TCP9 = 0x69,
- DBG_BLOCK_ID_TCP10 = 0x6a,
- DBG_BLOCK_ID_TCP11 = 0x6b,
- DBG_BLOCK_ID_TCP12 = 0x6c,
- DBG_BLOCK_ID_TCP13 = 0x6d,
- DBG_BLOCK_ID_TCP14 = 0x6e,
- DBG_BLOCK_ID_TCP15 = 0x6f,
- DBG_BLOCK_ID_TCP16 = 0x70,
- DBG_BLOCK_ID_TCP17 = 0x71,
- DBG_BLOCK_ID_TCP18 = 0x72,
- DBG_BLOCK_ID_TCP19 = 0x73,
- DBG_BLOCK_ID_TCP20 = 0x74,
- DBG_BLOCK_ID_TCP21 = 0x75,
- DBG_BLOCK_ID_TCP22 = 0x76,
- DBG_BLOCK_ID_TCP23 = 0x77,
- DBG_BLOCK_ID_TCP_RESERVED0 = 0x78,
- DBG_BLOCK_ID_TCP_RESERVED1 = 0x79,
- DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a,
- DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b,
- DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c,
- DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d,
- DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e,
- DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f,
- DBG_BLOCK_ID_DB00 = 0x80,
- DBG_BLOCK_ID_DB01 = 0x81,
- DBG_BLOCK_ID_DB02 = 0x82,
- DBG_BLOCK_ID_DB03 = 0x83,
- DBG_BLOCK_ID_DB04 = 0x84,
- DBG_BLOCK_ID_UNUSED27 = 0x85,
- DBG_BLOCK_ID_UNUSED28 = 0x86,
- DBG_BLOCK_ID_UNUSED29 = 0x87,
- DBG_BLOCK_ID_DB10 = 0x88,
- DBG_BLOCK_ID_DB11 = 0x89,
- DBG_BLOCK_ID_DB12 = 0x8a,
- DBG_BLOCK_ID_DB13 = 0x8b,
- DBG_BLOCK_ID_DB14 = 0x8c,
- DBG_BLOCK_ID_UNUSED30 = 0x8d,
- DBG_BLOCK_ID_UNUSED31 = 0x8e,
- DBG_BLOCK_ID_UNUSED32 = 0x8f,
- DBG_BLOCK_ID_TCC0 = 0x90,
- DBG_BLOCK_ID_TCC1 = 0x91,
- DBG_BLOCK_ID_TCC2 = 0x92,
- DBG_BLOCK_ID_TCC3 = 0x93,
- DBG_BLOCK_ID_TCC4 = 0x94,
- DBG_BLOCK_ID_TCC5 = 0x95,
- DBG_BLOCK_ID_TCC6 = 0x96,
- DBG_BLOCK_ID_TCC7 = 0x97,
- DBG_BLOCK_ID_SPS00 = 0x98,
- DBG_BLOCK_ID_SPS01 = 0x99,
- DBG_BLOCK_ID_SPS02 = 0x9a,
- DBG_BLOCK_ID_SPS10 = 0x9b,
- DBG_BLOCK_ID_SPS11 = 0x9c,
- DBG_BLOCK_ID_SPS12 = 0x9d,
- DBG_BLOCK_ID_UNUSED33 = 0x9e,
- DBG_BLOCK_ID_UNUSED34 = 0x9f,
- DBG_BLOCK_ID_TA00 = 0xa0,
- DBG_BLOCK_ID_TA01 = 0xa1,
- DBG_BLOCK_ID_TA02 = 0xa2,
- DBG_BLOCK_ID_TA03 = 0xa3,
- DBG_BLOCK_ID_TA04 = 0xa4,
- DBG_BLOCK_ID_TA05 = 0xa5,
- DBG_BLOCK_ID_TA06 = 0xa6,
- DBG_BLOCK_ID_TA07 = 0xa7,
- DBG_BLOCK_ID_TA08 = 0xa8,
- DBG_BLOCK_ID_TA09 = 0xa9,
- DBG_BLOCK_ID_TA0A = 0xaa,
- DBG_BLOCK_ID_TA0B = 0xab,
- DBG_BLOCK_ID_UNUSED35 = 0xac,
- DBG_BLOCK_ID_UNUSED36 = 0xad,
- DBG_BLOCK_ID_UNUSED37 = 0xae,
- DBG_BLOCK_ID_UNUSED38 = 0xaf,
- DBG_BLOCK_ID_TA10 = 0xb0,
- DBG_BLOCK_ID_TA11 = 0xb1,
- DBG_BLOCK_ID_TA12 = 0xb2,
- DBG_BLOCK_ID_TA13 = 0xb3,
- DBG_BLOCK_ID_TA14 = 0xb4,
- DBG_BLOCK_ID_TA15 = 0xb5,
- DBG_BLOCK_ID_TA16 = 0xb6,
- DBG_BLOCK_ID_TA17 = 0xb7,
- DBG_BLOCK_ID_TA18 = 0xb8,
- DBG_BLOCK_ID_TA19 = 0xb9,
- DBG_BLOCK_ID_TA1A = 0xba,
- DBG_BLOCK_ID_TA1B = 0xbb,
- DBG_BLOCK_ID_UNUSED39 = 0xbc,
- DBG_BLOCK_ID_UNUSED40 = 0xbd,
- DBG_BLOCK_ID_UNUSED41 = 0xbe,
- DBG_BLOCK_ID_UNUSED42 = 0xbf,
- DBG_BLOCK_ID_TD00 = 0xc0,
- DBG_BLOCK_ID_TD01 = 0xc1,
- DBG_BLOCK_ID_TD02 = 0xc2,
- DBG_BLOCK_ID_TD03 = 0xc3,
- DBG_BLOCK_ID_TD04 = 0xc4,
- DBG_BLOCK_ID_TD05 = 0xc5,
- DBG_BLOCK_ID_TD06 = 0xc6,
- DBG_BLOCK_ID_TD07 = 0xc7,
- DBG_BLOCK_ID_TD08 = 0xc8,
- DBG_BLOCK_ID_TD09 = 0xc9,
- DBG_BLOCK_ID_TD0A = 0xca,
- DBG_BLOCK_ID_TD0B = 0xcb,
- DBG_BLOCK_ID_UNUSED43 = 0xcc,
- DBG_BLOCK_ID_UNUSED44 = 0xcd,
- DBG_BLOCK_ID_UNUSED45 = 0xce,
- DBG_BLOCK_ID_UNUSED46 = 0xcf,
- DBG_BLOCK_ID_TD10 = 0xd0,
- DBG_BLOCK_ID_TD11 = 0xd1,
- DBG_BLOCK_ID_TD12 = 0xd2,
- DBG_BLOCK_ID_TD13 = 0xd3,
- DBG_BLOCK_ID_TD14 = 0xd4,
- DBG_BLOCK_ID_TD15 = 0xd5,
- DBG_BLOCK_ID_TD16 = 0xd6,
- DBG_BLOCK_ID_TD17 = 0xd7,
- DBG_BLOCK_ID_TD18 = 0xd8,
- DBG_BLOCK_ID_TD19 = 0xd9,
- DBG_BLOCK_ID_TD1A = 0xda,
- DBG_BLOCK_ID_TD1B = 0xdb,
- DBG_BLOCK_ID_UNUSED47 = 0xdc,
- DBG_BLOCK_ID_UNUSED48 = 0xdd,
- DBG_BLOCK_ID_UNUSED49 = 0xde,
- DBG_BLOCK_ID_UNUSED50 = 0xdf,
- DBG_BLOCK_ID_MCD0 = 0xe0,
- DBG_BLOCK_ID_MCD1 = 0xe1,
- DBG_BLOCK_ID_MCD2 = 0xe2,
- DBG_BLOCK_ID_MCD3 = 0xe3,
- DBG_BLOCK_ID_MCD4 = 0xe4,
- DBG_BLOCK_ID_MCD5 = 0xe5,
- DBG_BLOCK_ID_UNUSED51 = 0xe6,
- DBG_BLOCK_ID_UNUSED52 = 0xe7,
-} DebugBlockId_OLD;
-typedef enum DebugBlockId_BY2 {
- DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
- DBG_BLOCK_ID_VMC_BY2 = 0x1,
- DBG_BLOCK_ID_CG_BY2 = 0x2,
- DBG_BLOCK_ID_GRBM_BY2 = 0x3,
- DBG_BLOCK_ID_CSC_BY2 = 0x4,
- DBG_BLOCK_ID_IH_BY2 = 0x5,
- DBG_BLOCK_ID_SQ_BY2 = 0x6,
- DBG_BLOCK_ID_GMCON_BY2 = 0x7,
- DBG_BLOCK_ID_DMA0_BY2 = 0x8,
- DBG_BLOCK_ID_SPIM_BY2 = 0x9,
- DBG_BLOCK_ID_SPIS_BY2 = 0xa,
- DBG_BLOCK_ID_PA0_BY2 = 0xb,
- DBG_BLOCK_ID_CP0_BY2 = 0xc,
- DBG_BLOCK_ID_CP2_BY2 = 0xd,
- DBG_BLOCK_ID_UVDU_BY2 = 0xe,
- DBG_BLOCK_ID_VCE_BY2 = 0xf,
- DBG_BLOCK_ID_VGT0_BY2 = 0x10,
- DBG_BLOCK_ID_IA_BY2 = 0x11,
- DBG_BLOCK_ID_SCT0_BY2 = 0x12,
- DBG_BLOCK_ID_SPM0_BY2 = 0x13,
- DBG_BLOCK_ID_TCAA_BY2 = 0x14,
- DBG_BLOCK_ID_TCCA_BY2 = 0x15,
- DBG_BLOCK_ID_MCC0_BY2 = 0x16,
- DBG_BLOCK_ID_MCC2_BY2 = 0x17,
- DBG_BLOCK_ID_SX0_BY2 = 0x18,
- DBG_BLOCK_ID_SX2_BY2 = 0x19,
- DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a,
- DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b,
- DBG_BLOCK_ID_PC0_BY2 = 0x1c,
- DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d,
- DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e,
- DBG_BLOCK_ID_MCB_BY2 = 0x1f,
- DBG_BLOCK_ID_SCB0_BY2 = 0x20,
- DBG_BLOCK_ID_UNUSED13_BY2 = 0x21,
- DBG_BLOCK_ID_SCF0_BY2 = 0x22,
- DBG_BLOCK_ID_UNUSED15_BY2 = 0x23,
- DBG_BLOCK_ID_BCI0_BY2 = 0x24,
- DBG_BLOCK_ID_BCI2_BY2 = 0x25,
- DBG_BLOCK_ID_UNUSED17_BY2 = 0x26,
- DBG_BLOCK_ID_UNUSED19_BY2 = 0x27,
- DBG_BLOCK_ID_CB00_BY2 = 0x28,
- DBG_BLOCK_ID_CB02_BY2 = 0x29,
- DBG_BLOCK_ID_CB04_BY2 = 0x2a,
- DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b,
- DBG_BLOCK_ID_CB10_BY2 = 0x2c,
- DBG_BLOCK_ID_CB12_BY2 = 0x2d,
- DBG_BLOCK_ID_CB14_BY2 = 0x2e,
- DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f,
- DBG_BLOCK_ID_TCP0_BY2 = 0x30,
- DBG_BLOCK_ID_TCP2_BY2 = 0x31,
- DBG_BLOCK_ID_TCP4_BY2 = 0x32,
- DBG_BLOCK_ID_TCP6_BY2 = 0x33,
- DBG_BLOCK_ID_TCP8_BY2 = 0x34,
- DBG_BLOCK_ID_TCP10_BY2 = 0x35,
- DBG_BLOCK_ID_TCP12_BY2 = 0x36,
- DBG_BLOCK_ID_TCP14_BY2 = 0x37,
- DBG_BLOCK_ID_TCP16_BY2 = 0x38,
- DBG_BLOCK_ID_TCP18_BY2 = 0x39,
- DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
- DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
- DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
- DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
- DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
- DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
- DBG_BLOCK_ID_DB00_BY2 = 0x40,
- DBG_BLOCK_ID_DB02_BY2 = 0x41,
- DBG_BLOCK_ID_DB04_BY2 = 0x42,
- DBG_BLOCK_ID_UNUSED28_BY2 = 0x43,
- DBG_BLOCK_ID_DB10_BY2 = 0x44,
- DBG_BLOCK_ID_DB12_BY2 = 0x45,
- DBG_BLOCK_ID_DB14_BY2 = 0x46,
- DBG_BLOCK_ID_UNUSED31_BY2 = 0x47,
- DBG_BLOCK_ID_TCC0_BY2 = 0x48,
- DBG_BLOCK_ID_TCC2_BY2 = 0x49,
- DBG_BLOCK_ID_TCC4_BY2 = 0x4a,
- DBG_BLOCK_ID_TCC6_BY2 = 0x4b,
- DBG_BLOCK_ID_SPS00_BY2 = 0x4c,
- DBG_BLOCK_ID_SPS02_BY2 = 0x4d,
- DBG_BLOCK_ID_SPS11_BY2 = 0x4e,
- DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f,
- DBG_BLOCK_ID_TA00_BY2 = 0x50,
- DBG_BLOCK_ID_TA02_BY2 = 0x51,
- DBG_BLOCK_ID_TA04_BY2 = 0x52,
- DBG_BLOCK_ID_TA06_BY2 = 0x53,
- DBG_BLOCK_ID_TA08_BY2 = 0x54,
- DBG_BLOCK_ID_TA0A_BY2 = 0x55,
- DBG_BLOCK_ID_UNUSED35_BY2 = 0x56,
- DBG_BLOCK_ID_UNUSED37_BY2 = 0x57,
- DBG_BLOCK_ID_TA10_BY2 = 0x58,
- DBG_BLOCK_ID_TA12_BY2 = 0x59,
- DBG_BLOCK_ID_TA14_BY2 = 0x5a,
- DBG_BLOCK_ID_TA16_BY2 = 0x5b,
- DBG_BLOCK_ID_TA18_BY2 = 0x5c,
- DBG_BLOCK_ID_TA1A_BY2 = 0x5d,
- DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e,
- DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f,
- DBG_BLOCK_ID_TD00_BY2 = 0x60,
- DBG_BLOCK_ID_TD02_BY2 = 0x61,
- DBG_BLOCK_ID_TD04_BY2 = 0x62,
- DBG_BLOCK_ID_TD06_BY2 = 0x63,
- DBG_BLOCK_ID_TD08_BY2 = 0x64,
- DBG_BLOCK_ID_TD0A_BY2 = 0x65,
- DBG_BLOCK_ID_UNUSED43_BY2 = 0x66,
- DBG_BLOCK_ID_UNUSED45_BY2 = 0x67,
- DBG_BLOCK_ID_TD10_BY2 = 0x68,
- DBG_BLOCK_ID_TD12_BY2 = 0x69,
- DBG_BLOCK_ID_TD14_BY2 = 0x6a,
- DBG_BLOCK_ID_TD16_BY2 = 0x6b,
- DBG_BLOCK_ID_TD18_BY2 = 0x6c,
- DBG_BLOCK_ID_TD1A_BY2 = 0x6d,
- DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e,
- DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f,
- DBG_BLOCK_ID_MCD0_BY2 = 0x70,
- DBG_BLOCK_ID_MCD2_BY2 = 0x71,
- DBG_BLOCK_ID_MCD4_BY2 = 0x72,
- DBG_BLOCK_ID_UNUSED51_BY2 = 0x73,
-} DebugBlockId_BY2;
-typedef enum DebugBlockId_BY4 {
- DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
- DBG_BLOCK_ID_CG_BY4 = 0x1,
- DBG_BLOCK_ID_CSC_BY4 = 0x2,
- DBG_BLOCK_ID_SQ_BY4 = 0x3,
- DBG_BLOCK_ID_DMA0_BY4 = 0x4,
- DBG_BLOCK_ID_SPIS_BY4 = 0x5,
- DBG_BLOCK_ID_CP0_BY4 = 0x6,
- DBG_BLOCK_ID_UVDU_BY4 = 0x7,
- DBG_BLOCK_ID_VGT0_BY4 = 0x8,
- DBG_BLOCK_ID_SCT0_BY4 = 0x9,
- DBG_BLOCK_ID_TCAA_BY4 = 0xa,
- DBG_BLOCK_ID_MCC0_BY4 = 0xb,
- DBG_BLOCK_ID_SX0_BY4 = 0xc,
- DBG_BLOCK_ID_UNUSED4_BY4 = 0xd,
- DBG_BLOCK_ID_PC0_BY4 = 0xe,
- DBG_BLOCK_ID_UNUSED10_BY4 = 0xf,
- DBG_BLOCK_ID_SCB0_BY4 = 0x10,
- DBG_BLOCK_ID_SCF0_BY4 = 0x11,
- DBG_BLOCK_ID_BCI0_BY4 = 0x12,
- DBG_BLOCK_ID_UNUSED17_BY4 = 0x13,
- DBG_BLOCK_ID_CB00_BY4 = 0x14,
- DBG_BLOCK_ID_CB04_BY4 = 0x15,
- DBG_BLOCK_ID_CB10_BY4 = 0x16,
- DBG_BLOCK_ID_CB14_BY4 = 0x17,
- DBG_BLOCK_ID_TCP0_BY4 = 0x18,
- DBG_BLOCK_ID_TCP4_BY4 = 0x19,
- DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
- DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
- DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
- DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
- DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
- DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
- DBG_BLOCK_ID_DB_BY4 = 0x20,
- DBG_BLOCK_ID_DB04_BY4 = 0x21,
- DBG_BLOCK_ID_DB10_BY4 = 0x22,
- DBG_BLOCK_ID_DB14_BY4 = 0x23,
- DBG_BLOCK_ID_TCC0_BY4 = 0x24,
- DBG_BLOCK_ID_TCC4_BY4 = 0x25,
- DBG_BLOCK_ID_SPS00_BY4 = 0x26,
- DBG_BLOCK_ID_SPS11_BY4 = 0x27,
- DBG_BLOCK_ID_TA00_BY4 = 0x28,
- DBG_BLOCK_ID_TA04_BY4 = 0x29,
- DBG_BLOCK_ID_TA08_BY4 = 0x2a,
- DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b,
- DBG_BLOCK_ID_TA10_BY4 = 0x2c,
- DBG_BLOCK_ID_TA14_BY4 = 0x2d,
- DBG_BLOCK_ID_TA18_BY4 = 0x2e,
- DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f,
- DBG_BLOCK_ID_TD00_BY4 = 0x30,
- DBG_BLOCK_ID_TD04_BY4 = 0x31,
- DBG_BLOCK_ID_TD08_BY4 = 0x32,
- DBG_BLOCK_ID_UNUSED43_BY4 = 0x33,
- DBG_BLOCK_ID_TD10_BY4 = 0x34,
- DBG_BLOCK_ID_TD14_BY4 = 0x35,
- DBG_BLOCK_ID_TD18_BY4 = 0x36,
- DBG_BLOCK_ID_UNUSED47_BY4 = 0x37,
- DBG_BLOCK_ID_MCD0_BY4 = 0x38,
- DBG_BLOCK_ID_MCD4_BY4 = 0x39,
-} DebugBlockId_BY4;
-typedef enum DebugBlockId_BY8 {
- DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
- DBG_BLOCK_ID_CSC_BY8 = 0x1,
- DBG_BLOCK_ID_DMA0_BY8 = 0x2,
- DBG_BLOCK_ID_CP0_BY8 = 0x3,
- DBG_BLOCK_ID_VGT0_BY8 = 0x4,
- DBG_BLOCK_ID_TCAA_BY8 = 0x5,
- DBG_BLOCK_ID_SX0_BY8 = 0x6,
- DBG_BLOCK_ID_PC0_BY8 = 0x7,
- DBG_BLOCK_ID_SCB0_BY8 = 0x8,
- DBG_BLOCK_ID_BCI0_BY8 = 0x9,
- DBG_BLOCK_ID_CB00_BY8 = 0xa,
- DBG_BLOCK_ID_CB10_BY8 = 0xb,
- DBG_BLOCK_ID_TCP0_BY8 = 0xc,
- DBG_BLOCK_ID_TCP8_BY8 = 0xd,
- DBG_BLOCK_ID_TCP16_BY8 = 0xe,
- DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
- DBG_BLOCK_ID_DB00_BY8 = 0x10,
- DBG_BLOCK_ID_DB10_BY8 = 0x11,
- DBG_BLOCK_ID_TCC0_BY8 = 0x12,
- DBG_BLOCK_ID_SPS00_BY8 = 0x13,
- DBG_BLOCK_ID_TA00_BY8 = 0x14,
- DBG_BLOCK_ID_TA08_BY8 = 0x15,
- DBG_BLOCK_ID_TA10_BY8 = 0x16,
- DBG_BLOCK_ID_TA18_BY8 = 0x17,
- DBG_BLOCK_ID_TD00_BY8 = 0x18,
- DBG_BLOCK_ID_TD08_BY8 = 0x19,
- DBG_BLOCK_ID_TD10_BY8 = 0x1a,
- DBG_BLOCK_ID_TD18_BY8 = 0x1b,
- DBG_BLOCK_ID_MCD0_BY8 = 0x1c,
-} DebugBlockId_BY8;
-typedef enum DebugBlockId_BY16 {
- DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
- DBG_BLOCK_ID_DMA0_BY16 = 0x1,
- DBG_BLOCK_ID_VGT0_BY16 = 0x2,
- DBG_BLOCK_ID_SX0_BY16 = 0x3,
- DBG_BLOCK_ID_SCB0_BY16 = 0x4,
- DBG_BLOCK_ID_CB00_BY16 = 0x5,
- DBG_BLOCK_ID_TCP0_BY16 = 0x6,
- DBG_BLOCK_ID_TCP16_BY16 = 0x7,
- DBG_BLOCK_ID_DB00_BY16 = 0x8,
- DBG_BLOCK_ID_TCC0_BY16 = 0x9,
- DBG_BLOCK_ID_TA00_BY16 = 0xa,
- DBG_BLOCK_ID_TA10_BY16 = 0xb,
- DBG_BLOCK_ID_TD00_BY16 = 0xc,
- DBG_BLOCK_ID_TD10_BY16 = 0xd,
- DBG_BLOCK_ID_MCD0_BY16 = 0xe,
-} DebugBlockId_BY16;
-typedef enum ColorTransform {
- DCC_CT_AUTO = 0x0,
- DCC_CT_NONE = 0x1,
- ABGR_TO_A_BG_G_RB = 0x2,
- BGRA_TO_BG_G_RB_A = 0x3,
-} ColorTransform;
-typedef enum CompareRef {
- REF_NEVER = 0x0,
- REF_LESS = 0x1,
- REF_EQUAL = 0x2,
- REF_LEQUAL = 0x3,
- REF_GREATER = 0x4,
- REF_NOTEQUAL = 0x5,
- REF_GEQUAL = 0x6,
- REF_ALWAYS = 0x7,
-} CompareRef;
-typedef enum ReadSize {
- READ_256_BITS = 0x0,
- READ_512_BITS = 0x1,
-} ReadSize;
-typedef enum DepthFormat {
- DEPTH_INVALID = 0x0,
- DEPTH_16 = 0x1,
- DEPTH_X8_24 = 0x2,
- DEPTH_8_24 = 0x3,
- DEPTH_X8_24_FLOAT = 0x4,
- DEPTH_8_24_FLOAT = 0x5,
- DEPTH_32_FLOAT = 0x6,
- DEPTH_X24_8_32_FLOAT = 0x7,
-} DepthFormat;
-typedef enum ZFormat {
- Z_INVALID = 0x0,
- Z_16 = 0x1,
- Z_24 = 0x2,
- Z_32_FLOAT = 0x3,
-} ZFormat;
-typedef enum StencilFormat {
- STENCIL_INVALID = 0x0,
- STENCIL_8 = 0x1,
-} StencilFormat;
-typedef enum CmaskMode {
- CMASK_CLEAR_NONE = 0x0,
- CMASK_CLEAR_ONE = 0x1,
- CMASK_CLEAR_ALL = 0x2,
- CMASK_ANY_EXPANDED = 0x3,
- CMASK_ALPHA0_FRAG1 = 0x4,
- CMASK_ALPHA0_FRAG2 = 0x5,
- CMASK_ALPHA0_FRAG4 = 0x6,
- CMASK_ALPHA0_FRAGS = 0x7,
- CMASK_ALPHA1_FRAG1 = 0x8,
- CMASK_ALPHA1_FRAG2 = 0x9,
- CMASK_ALPHA1_FRAG4 = 0xa,
- CMASK_ALPHA1_FRAGS = 0xb,
- CMASK_ALPHAX_FRAG1 = 0xc,
- CMASK_ALPHAX_FRAG2 = 0xd,
- CMASK_ALPHAX_FRAG4 = 0xe,
- CMASK_ALPHAX_FRAGS = 0xf,
-} CmaskMode;
-typedef enum QuadExportFormat {
- EXPORT_UNUSED = 0x0,
- EXPORT_32_R = 0x1,
- EXPORT_32_GR = 0x2,
- EXPORT_32_AR = 0x3,
- EXPORT_FP16_ABGR = 0x4,
- EXPORT_UNSIGNED16_ABGR = 0x5,
- EXPORT_SIGNED16_ABGR = 0x6,
- EXPORT_32_ABGR = 0x7,
-} QuadExportFormat;
-typedef enum QuadExportFormatOld {
- EXPORT_4P_32BPC_ABGR = 0x0,
- EXPORT_4P_16BPC_ABGR = 0x1,
- EXPORT_4P_32BPC_GR = 0x2,
- EXPORT_4P_32BPC_AR = 0x3,
- EXPORT_2P_32BPC_ABGR = 0x4,
- EXPORT_8P_32BPC_R = 0x5,
-} QuadExportFormatOld;
-typedef enum ColorFormat {
- COLOR_INVALID = 0x0,
- COLOR_8 = 0x1,
- COLOR_16 = 0x2,
- COLOR_8_8 = 0x3,
- COLOR_32 = 0x4,
- COLOR_16_16 = 0x5,
- COLOR_10_11_11 = 0x6,
- COLOR_11_11_10 = 0x7,
- COLOR_10_10_10_2 = 0x8,
- COLOR_2_10_10_10 = 0x9,
- COLOR_8_8_8_8 = 0xa,
- COLOR_32_32 = 0xb,
- COLOR_16_16_16_16 = 0xc,
- COLOR_RESERVED_13 = 0xd,
- COLOR_32_32_32_32 = 0xe,
- COLOR_RESERVED_15 = 0xf,
- COLOR_5_6_5 = 0x10,
- COLOR_1_5_5_5 = 0x11,
- COLOR_5_5_5_1 = 0x12,
- COLOR_4_4_4_4 = 0x13,
- COLOR_8_24 = 0x14,
- COLOR_24_8 = 0x15,
- COLOR_X24_8_32_FLOAT = 0x16,
- COLOR_RESERVED_23 = 0x17,
-} ColorFormat;
-typedef enum SurfaceFormat {
- FMT_INVALID = 0x0,
- FMT_8 = 0x1,
- FMT_16 = 0x2,
- FMT_8_8 = 0x3,
- FMT_32 = 0x4,
- FMT_16_16 = 0x5,
- FMT_10_11_11 = 0x6,
- FMT_11_11_10 = 0x7,
- FMT_10_10_10_2 = 0x8,
- FMT_2_10_10_10 = 0x9,
- FMT_8_8_8_8 = 0xa,
- FMT_32_32 = 0xb,
- FMT_16_16_16_16 = 0xc,
- FMT_32_32_32 = 0xd,
- FMT_32_32_32_32 = 0xe,
- FMT_RESERVED_4 = 0xf,
- FMT_5_6_5 = 0x10,
- FMT_1_5_5_5 = 0x11,
- FMT_5_5_5_1 = 0x12,
- FMT_4_4_4_4 = 0x13,
- FMT_8_24 = 0x14,
- FMT_24_8 = 0x15,
- FMT_X24_8_32_FLOAT = 0x16,
- FMT_RESERVED_33 = 0x17,
- FMT_11_11_10_FLOAT = 0x18,
- FMT_16_FLOAT = 0x19,
- FMT_32_FLOAT = 0x1a,
- FMT_16_16_FLOAT = 0x1b,
- FMT_8_24_FLOAT = 0x1c,
- FMT_24_8_FLOAT = 0x1d,
- FMT_32_32_FLOAT = 0x1e,
- FMT_10_11_11_FLOAT = 0x1f,
- FMT_16_16_16_16_FLOAT = 0x20,
- FMT_3_3_2 = 0x21,
- FMT_6_5_5 = 0x22,
- FMT_32_32_32_32_FLOAT = 0x23,
- FMT_RESERVED_36 = 0x24,
- FMT_1 = 0x25,
- FMT_1_REVERSED = 0x26,
- FMT_GB_GR = 0x27,
- FMT_BG_RG = 0x28,
- FMT_32_AS_8 = 0x29,
- FMT_32_AS_8_8 = 0x2a,
- FMT_5_9_9_9_SHAREDEXP = 0x2b,
- FMT_8_8_8 = 0x2c,
- FMT_16_16_16 = 0x2d,
- FMT_16_16_16_FLOAT = 0x2e,
- FMT_4_4 = 0x2f,
- FMT_32_32_32_FLOAT = 0x30,
- FMT_BC1 = 0x31,
- FMT_BC2 = 0x32,
- FMT_BC3 = 0x33,
- FMT_BC4 = 0x34,
- FMT_BC5 = 0x35,
- FMT_BC6 = 0x36,
- FMT_BC7 = 0x37,
- FMT_32_AS_32_32_32_32 = 0x38,
- FMT_APC3 = 0x39,
- FMT_APC4 = 0x3a,
- FMT_APC5 = 0x3b,
- FMT_APC6 = 0x3c,
- FMT_APC7 = 0x3d,
- FMT_CTX1 = 0x3e,
- FMT_RESERVED_63 = 0x3f,
-} SurfaceFormat;
-typedef enum BUF_DATA_FORMAT {
- BUF_DATA_FORMAT_INVALID = 0x0,
- BUF_DATA_FORMAT_8 = 0x1,
- BUF_DATA_FORMAT_16 = 0x2,
- BUF_DATA_FORMAT_8_8 = 0x3,
- BUF_DATA_FORMAT_32 = 0x4,
- BUF_DATA_FORMAT_16_16 = 0x5,
- BUF_DATA_FORMAT_10_11_11 = 0x6,
- BUF_DATA_FORMAT_11_11_10 = 0x7,
- BUF_DATA_FORMAT_10_10_10_2 = 0x8,
- BUF_DATA_FORMAT_2_10_10_10 = 0x9,
- BUF_DATA_FORMAT_8_8_8_8 = 0xa,
- BUF_DATA_FORMAT_32_32 = 0xb,
- BUF_DATA_FORMAT_16_16_16_16 = 0xc,
- BUF_DATA_FORMAT_32_32_32 = 0xd,
- BUF_DATA_FORMAT_32_32_32_32 = 0xe,
- BUF_DATA_FORMAT_RESERVED_15 = 0xf,
-} BUF_DATA_FORMAT;
-typedef enum IMG_DATA_FORMAT {
- IMG_DATA_FORMAT_INVALID = 0x0,
- IMG_DATA_FORMAT_8 = 0x1,
- IMG_DATA_FORMAT_16 = 0x2,
- IMG_DATA_FORMAT_8_8 = 0x3,
- IMG_DATA_FORMAT_32 = 0x4,
- IMG_DATA_FORMAT_16_16 = 0x5,
- IMG_DATA_FORMAT_10_11_11 = 0x6,
- IMG_DATA_FORMAT_11_11_10 = 0x7,
- IMG_DATA_FORMAT_10_10_10_2 = 0x8,
- IMG_DATA_FORMAT_2_10_10_10 = 0x9,
- IMG_DATA_FORMAT_8_8_8_8 = 0xa,
- IMG_DATA_FORMAT_32_32 = 0xb,
- IMG_DATA_FORMAT_16_16_16_16 = 0xc,
- IMG_DATA_FORMAT_32_32_32 = 0xd,
- IMG_DATA_FORMAT_32_32_32_32 = 0xe,
- IMG_DATA_FORMAT_RESERVED_15 = 0xf,
- IMG_DATA_FORMAT_5_6_5 = 0x10,
- IMG_DATA_FORMAT_1_5_5_5 = 0x11,
- IMG_DATA_FORMAT_5_5_5_1 = 0x12,
- IMG_DATA_FORMAT_4_4_4_4 = 0x13,
- IMG_DATA_FORMAT_8_24 = 0x14,
- IMG_DATA_FORMAT_24_8 = 0x15,
- IMG_DATA_FORMAT_X24_8_32 = 0x16,
- IMG_DATA_FORMAT_RESERVED_23 = 0x17,
- IMG_DATA_FORMAT_RESERVED_24 = 0x18,
- IMG_DATA_FORMAT_RESERVED_25 = 0x19,
- IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
- IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
- IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
- IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
- IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
- IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
- IMG_DATA_FORMAT_GB_GR = 0x20,
- IMG_DATA_FORMAT_BG_RG = 0x21,
- IMG_DATA_FORMAT_5_9_9_9 = 0x22,
- IMG_DATA_FORMAT_BC1 = 0x23,
- IMG_DATA_FORMAT_BC2 = 0x24,
- IMG_DATA_FORMAT_BC3 = 0x25,
- IMG_DATA_FORMAT_BC4 = 0x26,
- IMG_DATA_FORMAT_BC5 = 0x27,
- IMG_DATA_FORMAT_BC6 = 0x28,
- IMG_DATA_FORMAT_BC7 = 0x29,
- IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
- IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
- IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
- IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
- IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
- IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
- IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
- IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
- IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
- IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
- IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
- IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
- IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
- IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
- IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
- IMG_DATA_FORMAT_4_4 = 0x39,
- IMG_DATA_FORMAT_6_5_5 = 0x3a,
- IMG_DATA_FORMAT_1 = 0x3b,
- IMG_DATA_FORMAT_1_REVERSED = 0x3c,
- IMG_DATA_FORMAT_32_AS_8 = 0x3d,
- IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
- IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
-} IMG_DATA_FORMAT;
-typedef enum BUF_NUM_FORMAT {
- BUF_NUM_FORMAT_UNORM = 0x0,
- BUF_NUM_FORMAT_SNORM = 0x1,
- BUF_NUM_FORMAT_USCALED = 0x2,
- BUF_NUM_FORMAT_SSCALED = 0x3,
- BUF_NUM_FORMAT_UINT = 0x4,
- BUF_NUM_FORMAT_SINT = 0x5,
- BUF_NUM_FORMAT_RESERVED_6 = 0x6,
- BUF_NUM_FORMAT_FLOAT = 0x7,
-} BUF_NUM_FORMAT;
-typedef enum IMG_NUM_FORMAT {
- IMG_NUM_FORMAT_UNORM = 0x0,
- IMG_NUM_FORMAT_SNORM = 0x1,
- IMG_NUM_FORMAT_USCALED = 0x2,
- IMG_NUM_FORMAT_SSCALED = 0x3,
- IMG_NUM_FORMAT_UINT = 0x4,
- IMG_NUM_FORMAT_SINT = 0x5,
- IMG_NUM_FORMAT_RESERVED_6 = 0x6,
- IMG_NUM_FORMAT_FLOAT = 0x7,
- IMG_NUM_FORMAT_RESERVED_8 = 0x8,
- IMG_NUM_FORMAT_SRGB = 0x9,
- IMG_NUM_FORMAT_RESERVED_10 = 0xa,
- IMG_NUM_FORMAT_RESERVED_11 = 0xb,
- IMG_NUM_FORMAT_RESERVED_12 = 0xc,
- IMG_NUM_FORMAT_RESERVED_13 = 0xd,
- IMG_NUM_FORMAT_RESERVED_14 = 0xe,
- IMG_NUM_FORMAT_RESERVED_15 = 0xf,
-} IMG_NUM_FORMAT;
-typedef enum TileType {
- ARRAY_COLOR_TILE = 0x0,
- ARRAY_DEPTH_TILE = 0x1,
-} TileType;
-typedef enum NonDispTilingOrder {
- ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
- ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
-} NonDispTilingOrder;
-typedef enum MicroTileMode {
- ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
- ADDR_SURF_THIN_MICRO_TILING = 0x1,
- ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
- ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
- ADDR_SURF_THICK_MICRO_TILING = 0x4,
-} MicroTileMode;
-typedef enum TileSplit {
- ADDR_SURF_TILE_SPLIT_64B = 0x0,
- ADDR_SURF_TILE_SPLIT_128B = 0x1,
- ADDR_SURF_TILE_SPLIT_256B = 0x2,
- ADDR_SURF_TILE_SPLIT_512B = 0x3,
- ADDR_SURF_TILE_SPLIT_1KB = 0x4,
- ADDR_SURF_TILE_SPLIT_2KB = 0x5,
- ADDR_SURF_TILE_SPLIT_4KB = 0x6,
-} TileSplit;
-typedef enum SampleSplit {
- ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
- ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
- ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
- ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
-} SampleSplit;
-typedef enum PipeConfig {
- ADDR_SURF_P2 = 0x0,
- ADDR_SURF_P2_RESERVED0 = 0x1,
- ADDR_SURF_P2_RESERVED1 = 0x2,
- ADDR_SURF_P2_RESERVED2 = 0x3,
- ADDR_SURF_P4_8x16 = 0x4,
- ADDR_SURF_P4_16x16 = 0x5,
- ADDR_SURF_P4_16x32 = 0x6,
- ADDR_SURF_P4_32x32 = 0x7,
- ADDR_SURF_P8_16x16_8x16 = 0x8,
- ADDR_SURF_P8_16x32_8x16 = 0x9,
- ADDR_SURF_P8_32x32_8x16 = 0xa,
- ADDR_SURF_P8_16x32_16x16 = 0xb,
- ADDR_SURF_P8_32x32_16x16 = 0xc,
- ADDR_SURF_P8_32x32_16x32 = 0xd,
- ADDR_SURF_P8_32x64_32x32 = 0xe,
- ADDR_SURF_P8_RESERVED0 = 0xf,
- ADDR_SURF_P16_32x32_8x16 = 0x10,
- ADDR_SURF_P16_32x32_16x16 = 0x11,
-} PipeConfig;
-typedef enum NumBanks {
- ADDR_SURF_2_BANK = 0x0,
- ADDR_SURF_4_BANK = 0x1,
- ADDR_SURF_8_BANK = 0x2,
- ADDR_SURF_16_BANK = 0x3,
-} NumBanks;
-typedef enum BankWidth {
- ADDR_SURF_BANK_WIDTH_1 = 0x0,
- ADDR_SURF_BANK_WIDTH_2 = 0x1,
- ADDR_SURF_BANK_WIDTH_4 = 0x2,
- ADDR_SURF_BANK_WIDTH_8 = 0x3,
-} BankWidth;
-typedef enum BankHeight {
- ADDR_SURF_BANK_HEIGHT_1 = 0x0,
- ADDR_SURF_BANK_HEIGHT_2 = 0x1,
- ADDR_SURF_BANK_HEIGHT_4 = 0x2,
- ADDR_SURF_BANK_HEIGHT_8 = 0x3,
-} BankHeight;
-typedef enum BankWidthHeight {
- ADDR_SURF_BANK_WH_1 = 0x0,
- ADDR_SURF_BANK_WH_2 = 0x1,
- ADDR_SURF_BANK_WH_4 = 0x2,
- ADDR_SURF_BANK_WH_8 = 0x3,
-} BankWidthHeight;
-typedef enum MacroTileAspect {
- ADDR_SURF_MACRO_ASPECT_1 = 0x0,
- ADDR_SURF_MACRO_ASPECT_2 = 0x1,
- ADDR_SURF_MACRO_ASPECT_4 = 0x2,
- ADDR_SURF_MACRO_ASPECT_8 = 0x3,
-} MacroTileAspect;
-typedef enum GATCL1RequestType {
- GATCL1_TYPE_NORMAL = 0x0,
- GATCL1_TYPE_SHOOTDOWN = 0x1,
- GATCL1_TYPE_BYPASS = 0x2,
-} GATCL1RequestType;
-typedef enum TCC_CACHE_POLICIES {
- TCC_CACHE_POLICY_LRU = 0x0,
- TCC_CACHE_POLICY_STREAM = 0x1,
-} TCC_CACHE_POLICIES;
-typedef enum MTYPE {
- MTYPE_NC_NV = 0x0,
- MTYPE_NC = 0x1,
- MTYPE_CC = 0x2,
- MTYPE_UC = 0x3,
-} MTYPE;
-typedef enum PERFMON_COUNTER_MODE {
- PERFMON_COUNTER_MODE_ACCUM = 0x0,
- PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
- PERFMON_COUNTER_MODE_MAX = 0x2,
- PERFMON_COUNTER_MODE_DIRTY = 0x3,
- PERFMON_COUNTER_MODE_SAMPLE = 0x4,
- PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
- PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
- PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
- PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
- PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
- PERFMON_COUNTER_MODE_RESERVED = 0xf,
-} PERFMON_COUNTER_MODE;
-typedef enum PERFMON_SPM_MODE {
- PERFMON_SPM_MODE_OFF = 0x0,
- PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
- PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
- PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
- PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
- PERFMON_SPM_MODE_RESERVED_5 = 0x5,
- PERFMON_SPM_MODE_RESERVED_6 = 0x6,
- PERFMON_SPM_MODE_RESERVED_7 = 0x7,
- PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
- PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
- PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
-} PERFMON_SPM_MODE;
-typedef enum SurfaceTiling {
- ARRAY_LINEAR = 0x0,
- ARRAY_TILED = 0x1,
-} SurfaceTiling;
-typedef enum SurfaceArray {
- ARRAY_1D = 0x0,
- ARRAY_2D = 0x1,
- ARRAY_3D = 0x2,
- ARRAY_3D_SLICE = 0x3,
-} SurfaceArray;
-typedef enum ColorArray {
- ARRAY_2D_ALT_COLOR = 0x0,
- ARRAY_2D_COLOR = 0x1,
- ARRAY_3D_SLICE_COLOR = 0x3,
-} ColorArray;
-typedef enum DepthArray {
- ARRAY_2D_ALT_DEPTH = 0x0,
- ARRAY_2D_DEPTH = 0x1,
-} DepthArray;
-typedef enum ENUM_NUM_SIMD_PER_CU {
- NUM_SIMD_PER_CU = 0x4,
-} ENUM_NUM_SIMD_PER_CU;
-typedef enum MEM_PWR_FORCE_CTRL {
- NO_FORCE_REQUEST = 0x0,
- FORCE_LIGHT_SLEEP_REQUEST = 0x1,
- FORCE_DEEP_SLEEP_REQUEST = 0x2,
- FORCE_SHUT_DOWN_REQUEST = 0x3,
-} MEM_PWR_FORCE_CTRL;
-typedef enum MEM_PWR_FORCE_CTRL2 {
- NO_FORCE_REQ = 0x0,
- FORCE_LIGHT_SLEEP_REQ = 0x1,
-} MEM_PWR_FORCE_CTRL2;
-typedef enum MEM_PWR_DIS_CTRL {
- ENABLE_MEM_PWR_CTRL = 0x0,
- DISABLE_MEM_PWR_CTRL = 0x1,
-} MEM_PWR_DIS_CTRL;
-typedef enum MEM_PWR_SEL_CTRL {
- DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
- DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
- DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
-} MEM_PWR_SEL_CTRL;
-typedef enum MEM_PWR_SEL_CTRL2 {
- DYNAMIC_DEEP_SLEEP_EN = 0x0,
- DYNAMIC_LIGHT_SLEEP_EN = 0x1,
-} MEM_PWR_SEL_CTRL2;
-
-#endif /* BIF_5_0_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_enum.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_enum.h
deleted file mode 100644
index d8d5ae0b3..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_enum.h
+++ /dev/null
@@ -1,1068 +0,0 @@
-/*
- * BIF_5_1 Register documentation
- *
- * Copyright (C) 2014 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef BIF_5_1_ENUM_H
-#define BIF_5_1_ENUM_H
-
-typedef enum DebugBlockId {
- DBG_BLOCK_ID_RESERVED = 0x0,
- DBG_BLOCK_ID_DBG = 0x1,
- DBG_BLOCK_ID_VMC = 0x2,
- DBG_BLOCK_ID_PDMA = 0x3,
- DBG_BLOCK_ID_CG = 0x4,
- DBG_BLOCK_ID_SRBM = 0x5,
- DBG_BLOCK_ID_GRBM = 0x6,
- DBG_BLOCK_ID_RLC = 0x7,
- DBG_BLOCK_ID_CSC = 0x8,
- DBG_BLOCK_ID_SEM = 0x9,
- DBG_BLOCK_ID_IH = 0xa,
- DBG_BLOCK_ID_SC = 0xb,
- DBG_BLOCK_ID_SQ = 0xc,
- DBG_BLOCK_ID_UVDU = 0xd,
- DBG_BLOCK_ID_SQA = 0xe,
- DBG_BLOCK_ID_SDMA0 = 0xf,
- DBG_BLOCK_ID_SDMA1 = 0x10,
- DBG_BLOCK_ID_SPIM = 0x11,
- DBG_BLOCK_ID_GDS = 0x12,
- DBG_BLOCK_ID_VC0 = 0x13,
- DBG_BLOCK_ID_VC1 = 0x14,
- DBG_BLOCK_ID_PA0 = 0x15,
- DBG_BLOCK_ID_PA1 = 0x16,
- DBG_BLOCK_ID_CP0 = 0x17,
- DBG_BLOCK_ID_CP1 = 0x18,
- DBG_BLOCK_ID_CP2 = 0x19,
- DBG_BLOCK_ID_XBR = 0x1a,
- DBG_BLOCK_ID_UVDM = 0x1b,
- DBG_BLOCK_ID_VGT0 = 0x1c,
- DBG_BLOCK_ID_VGT1 = 0x1d,
- DBG_BLOCK_ID_IA = 0x1e,
- DBG_BLOCK_ID_SXM0 = 0x1f,
- DBG_BLOCK_ID_SXM1 = 0x20,
- DBG_BLOCK_ID_SCT0 = 0x21,
- DBG_BLOCK_ID_SCT1 = 0x22,
- DBG_BLOCK_ID_SPM0 = 0x23,
- DBG_BLOCK_ID_SPM1 = 0x24,
- DBG_BLOCK_ID_UNUSED0 = 0x25,
- DBG_BLOCK_ID_UNUSED1 = 0x26,
- DBG_BLOCK_ID_TCAA = 0x27,
- DBG_BLOCK_ID_TCAB = 0x28,
- DBG_BLOCK_ID_TCCA = 0x29,
- DBG_BLOCK_ID_TCCB = 0x2a,
- DBG_BLOCK_ID_MCC0 = 0x2b,
- DBG_BLOCK_ID_MCC1 = 0x2c,
- DBG_BLOCK_ID_MCC2 = 0x2d,
- DBG_BLOCK_ID_MCC3 = 0x2e,
- DBG_BLOCK_ID_SXS0 = 0x2f,
- DBG_BLOCK_ID_SXS1 = 0x30,
- DBG_BLOCK_ID_SXS2 = 0x31,
- DBG_BLOCK_ID_SXS3 = 0x32,
- DBG_BLOCK_ID_SXS4 = 0x33,
- DBG_BLOCK_ID_SXS5 = 0x34,
- DBG_BLOCK_ID_SXS6 = 0x35,
- DBG_BLOCK_ID_SXS7 = 0x36,
- DBG_BLOCK_ID_SXS8 = 0x37,
- DBG_BLOCK_ID_SXS9 = 0x38,
- DBG_BLOCK_ID_BCI0 = 0x39,
- DBG_BLOCK_ID_BCI1 = 0x3a,
- DBG_BLOCK_ID_BCI2 = 0x3b,
- DBG_BLOCK_ID_BCI3 = 0x3c,
- DBG_BLOCK_ID_MCB = 0x3d,
- DBG_BLOCK_ID_UNUSED6 = 0x3e,
- DBG_BLOCK_ID_SQA00 = 0x3f,
- DBG_BLOCK_ID_SQA01 = 0x40,
- DBG_BLOCK_ID_SQA02 = 0x41,
- DBG_BLOCK_ID_SQA10 = 0x42,
- DBG_BLOCK_ID_SQA11 = 0x43,
- DBG_BLOCK_ID_SQA12 = 0x44,
- DBG_BLOCK_ID_UNUSED7 = 0x45,
- DBG_BLOCK_ID_UNUSED8 = 0x46,
- DBG_BLOCK_ID_SQB00 = 0x47,
- DBG_BLOCK_ID_SQB01 = 0x48,
- DBG_BLOCK_ID_SQB10 = 0x49,
- DBG_BLOCK_ID_SQB11 = 0x4a,
- DBG_BLOCK_ID_SQ00 = 0x4b,
- DBG_BLOCK_ID_SQ01 = 0x4c,
- DBG_BLOCK_ID_SQ10 = 0x4d,
- DBG_BLOCK_ID_SQ11 = 0x4e,
- DBG_BLOCK_ID_CB00 = 0x4f,
- DBG_BLOCK_ID_CB01 = 0x50,
- DBG_BLOCK_ID_CB02 = 0x51,
- DBG_BLOCK_ID_CB03 = 0x52,
- DBG_BLOCK_ID_CB04 = 0x53,
- DBG_BLOCK_ID_UNUSED9 = 0x54,
- DBG_BLOCK_ID_UNUSED10 = 0x55,
- DBG_BLOCK_ID_UNUSED11 = 0x56,
- DBG_BLOCK_ID_CB10 = 0x57,
- DBG_BLOCK_ID_CB11 = 0x58,
- DBG_BLOCK_ID_CB12 = 0x59,
- DBG_BLOCK_ID_CB13 = 0x5a,
- DBG_BLOCK_ID_CB14 = 0x5b,
- DBG_BLOCK_ID_UNUSED12 = 0x5c,
- DBG_BLOCK_ID_UNUSED13 = 0x5d,
- DBG_BLOCK_ID_UNUSED14 = 0x5e,
- DBG_BLOCK_ID_TCP0 = 0x5f,
- DBG_BLOCK_ID_TCP1 = 0x60,
- DBG_BLOCK_ID_TCP2 = 0x61,
- DBG_BLOCK_ID_TCP3 = 0x62,
- DBG_BLOCK_ID_TCP4 = 0x63,
- DBG_BLOCK_ID_TCP5 = 0x64,
- DBG_BLOCK_ID_TCP6 = 0x65,
- DBG_BLOCK_ID_TCP7 = 0x66,
- DBG_BLOCK_ID_TCP8 = 0x67,
- DBG_BLOCK_ID_TCP9 = 0x68,
- DBG_BLOCK_ID_TCP10 = 0x69,
- DBG_BLOCK_ID_TCP11 = 0x6a,
- DBG_BLOCK_ID_TCP12 = 0x6b,
- DBG_BLOCK_ID_TCP13 = 0x6c,
- DBG_BLOCK_ID_TCP14 = 0x6d,
- DBG_BLOCK_ID_TCP15 = 0x6e,
- DBG_BLOCK_ID_TCP16 = 0x6f,
- DBG_BLOCK_ID_TCP17 = 0x70,
- DBG_BLOCK_ID_TCP18 = 0x71,
- DBG_BLOCK_ID_TCP19 = 0x72,
- DBG_BLOCK_ID_TCP20 = 0x73,
- DBG_BLOCK_ID_TCP21 = 0x74,
- DBG_BLOCK_ID_TCP22 = 0x75,
- DBG_BLOCK_ID_TCP23 = 0x76,
- DBG_BLOCK_ID_TCP_RESERVED0 = 0x77,
- DBG_BLOCK_ID_TCP_RESERVED1 = 0x78,
- DBG_BLOCK_ID_TCP_RESERVED2 = 0x79,
- DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a,
- DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b,
- DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c,
- DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d,
- DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e,
- DBG_BLOCK_ID_DB00 = 0x7f,
- DBG_BLOCK_ID_DB01 = 0x80,
- DBG_BLOCK_ID_DB02 = 0x81,
- DBG_BLOCK_ID_DB03 = 0x82,
- DBG_BLOCK_ID_DB04 = 0x83,
- DBG_BLOCK_ID_UNUSED15 = 0x84,
- DBG_BLOCK_ID_UNUSED16 = 0x85,
- DBG_BLOCK_ID_UNUSED17 = 0x86,
- DBG_BLOCK_ID_DB10 = 0x87,
- DBG_BLOCK_ID_DB11 = 0x88,
- DBG_BLOCK_ID_DB12 = 0x89,
- DBG_BLOCK_ID_DB13 = 0x8a,
- DBG_BLOCK_ID_DB14 = 0x8b,
- DBG_BLOCK_ID_UNUSED18 = 0x8c,
- DBG_BLOCK_ID_UNUSED19 = 0x8d,
- DBG_BLOCK_ID_UNUSED20 = 0x8e,
- DBG_BLOCK_ID_TCC0 = 0x8f,
- DBG_BLOCK_ID_TCC1 = 0x90,
- DBG_BLOCK_ID_TCC2 = 0x91,
- DBG_BLOCK_ID_TCC3 = 0x92,
- DBG_BLOCK_ID_TCC4 = 0x93,
- DBG_BLOCK_ID_TCC5 = 0x94,
- DBG_BLOCK_ID_TCC6 = 0x95,
- DBG_BLOCK_ID_TCC7 = 0x96,
- DBG_BLOCK_ID_SPS00 = 0x97,
- DBG_BLOCK_ID_SPS01 = 0x98,
- DBG_BLOCK_ID_SPS02 = 0x99,
- DBG_BLOCK_ID_SPS10 = 0x9a,
- DBG_BLOCK_ID_SPS11 = 0x9b,
- DBG_BLOCK_ID_SPS12 = 0x9c,
- DBG_BLOCK_ID_UNUSED21 = 0x9d,
- DBG_BLOCK_ID_UNUSED22 = 0x9e,
- DBG_BLOCK_ID_TA00 = 0x9f,
- DBG_BLOCK_ID_TA01 = 0xa0,
- DBG_BLOCK_ID_TA02 = 0xa1,
- DBG_BLOCK_ID_TA03 = 0xa2,
- DBG_BLOCK_ID_TA04 = 0xa3,
- DBG_BLOCK_ID_TA05 = 0xa4,
- DBG_BLOCK_ID_TA06 = 0xa5,
- DBG_BLOCK_ID_TA07 = 0xa6,
- DBG_BLOCK_ID_TA08 = 0xa7,
- DBG_BLOCK_ID_TA09 = 0xa8,
- DBG_BLOCK_ID_TA0A = 0xa9,
- DBG_BLOCK_ID_TA0B = 0xaa,
- DBG_BLOCK_ID_UNUSED23 = 0xab,
- DBG_BLOCK_ID_UNUSED24 = 0xac,
- DBG_BLOCK_ID_UNUSED25 = 0xad,
- DBG_BLOCK_ID_UNUSED26 = 0xae,
- DBG_BLOCK_ID_TA10 = 0xaf,
- DBG_BLOCK_ID_TA11 = 0xb0,
- DBG_BLOCK_ID_TA12 = 0xb1,
- DBG_BLOCK_ID_TA13 = 0xb2,
- DBG_BLOCK_ID_TA14 = 0xb3,
- DBG_BLOCK_ID_TA15 = 0xb4,
- DBG_BLOCK_ID_TA16 = 0xb5,
- DBG_BLOCK_ID_TA17 = 0xb6,
- DBG_BLOCK_ID_TA18 = 0xb7,
- DBG_BLOCK_ID_TA19 = 0xb8,
- DBG_BLOCK_ID_TA1A = 0xb9,
- DBG_BLOCK_ID_TA1B = 0xba,
- DBG_BLOCK_ID_UNUSED27 = 0xbb,
- DBG_BLOCK_ID_UNUSED28 = 0xbc,
- DBG_BLOCK_ID_UNUSED29 = 0xbd,
- DBG_BLOCK_ID_UNUSED30 = 0xbe,
- DBG_BLOCK_ID_TD00 = 0xbf,
- DBG_BLOCK_ID_TD01 = 0xc0,
- DBG_BLOCK_ID_TD02 = 0xc1,
- DBG_BLOCK_ID_TD03 = 0xc2,
- DBG_BLOCK_ID_TD04 = 0xc3,
- DBG_BLOCK_ID_TD05 = 0xc4,
- DBG_BLOCK_ID_TD06 = 0xc5,
- DBG_BLOCK_ID_TD07 = 0xc6,
- DBG_BLOCK_ID_TD08 = 0xc7,
- DBG_BLOCK_ID_TD09 = 0xc8,
- DBG_BLOCK_ID_TD0A = 0xc9,
- DBG_BLOCK_ID_TD0B = 0xca,
- DBG_BLOCK_ID_UNUSED31 = 0xcb,
- DBG_BLOCK_ID_UNUSED32 = 0xcc,
- DBG_BLOCK_ID_UNUSED33 = 0xcd,
- DBG_BLOCK_ID_UNUSED34 = 0xce,
- DBG_BLOCK_ID_TD10 = 0xcf,
- DBG_BLOCK_ID_TD11 = 0xd0,
- DBG_BLOCK_ID_TD12 = 0xd1,
- DBG_BLOCK_ID_TD13 = 0xd2,
- DBG_BLOCK_ID_TD14 = 0xd3,
- DBG_BLOCK_ID_TD15 = 0xd4,
- DBG_BLOCK_ID_TD16 = 0xd5,
- DBG_BLOCK_ID_TD17 = 0xd6,
- DBG_BLOCK_ID_TD18 = 0xd7,
- DBG_BLOCK_ID_TD19 = 0xd8,
- DBG_BLOCK_ID_TD1A = 0xd9,
- DBG_BLOCK_ID_TD1B = 0xda,
- DBG_BLOCK_ID_UNUSED35 = 0xdb,
- DBG_BLOCK_ID_UNUSED36 = 0xdc,
- DBG_BLOCK_ID_UNUSED37 = 0xdd,
- DBG_BLOCK_ID_UNUSED38 = 0xde,
- DBG_BLOCK_ID_LDS00 = 0xdf,
- DBG_BLOCK_ID_LDS01 = 0xe0,
- DBG_BLOCK_ID_LDS02 = 0xe1,
- DBG_BLOCK_ID_LDS03 = 0xe2,
- DBG_BLOCK_ID_LDS04 = 0xe3,
- DBG_BLOCK_ID_LDS05 = 0xe4,
- DBG_BLOCK_ID_LDS06 = 0xe5,
- DBG_BLOCK_ID_LDS07 = 0xe6,
- DBG_BLOCK_ID_LDS08 = 0xe7,
- DBG_BLOCK_ID_LDS09 = 0xe8,
- DBG_BLOCK_ID_LDS0A = 0xe9,
- DBG_BLOCK_ID_LDS0B = 0xea,
- DBG_BLOCK_ID_UNUSED39 = 0xeb,
- DBG_BLOCK_ID_UNUSED40 = 0xec,
- DBG_BLOCK_ID_UNUSED41 = 0xed,
- DBG_BLOCK_ID_UNUSED42 = 0xee,
- DBG_BLOCK_ID_LDS10 = 0xef,
- DBG_BLOCK_ID_LDS11 = 0xf0,
- DBG_BLOCK_ID_LDS12 = 0xf1,
- DBG_BLOCK_ID_LDS13 = 0xf2,
- DBG_BLOCK_ID_LDS14 = 0xf3,
- DBG_BLOCK_ID_LDS15 = 0xf4,
- DBG_BLOCK_ID_LDS16 = 0xf5,
- DBG_BLOCK_ID_LDS17 = 0xf6,
- DBG_BLOCK_ID_LDS18 = 0xf7,
- DBG_BLOCK_ID_LDS19 = 0xf8,
- DBG_BLOCK_ID_LDS1A = 0xf9,
- DBG_BLOCK_ID_LDS1B = 0xfa,
- DBG_BLOCK_ID_UNUSED43 = 0xfb,
- DBG_BLOCK_ID_UNUSED44 = 0xfc,
- DBG_BLOCK_ID_UNUSED45 = 0xfd,
- DBG_BLOCK_ID_UNUSED46 = 0xfe,
-} DebugBlockId;
-typedef enum DebugBlockId_BY2 {
- DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
- DBG_BLOCK_ID_VMC_BY2 = 0x1,
- DBG_BLOCK_ID_UNUSED0_BY2 = 0x2,
- DBG_BLOCK_ID_GRBM_BY2 = 0x3,
- DBG_BLOCK_ID_CSC_BY2 = 0x4,
- DBG_BLOCK_ID_IH_BY2 = 0x5,
- DBG_BLOCK_ID_SQ_BY2 = 0x6,
- DBG_BLOCK_ID_UVD_BY2 = 0x7,
- DBG_BLOCK_ID_SDMA0_BY2 = 0x8,
- DBG_BLOCK_ID_SPIM_BY2 = 0x9,
- DBG_BLOCK_ID_VC0_BY2 = 0xa,
- DBG_BLOCK_ID_PA_BY2 = 0xb,
- DBG_BLOCK_ID_CP0_BY2 = 0xc,
- DBG_BLOCK_ID_CP2_BY2 = 0xd,
- DBG_BLOCK_ID_PC0_BY2 = 0xe,
- DBG_BLOCK_ID_BCI0_BY2 = 0xf,
- DBG_BLOCK_ID_SXM0_BY2 = 0x10,
- DBG_BLOCK_ID_SCT0_BY2 = 0x11,
- DBG_BLOCK_ID_SPM0_BY2 = 0x12,
- DBG_BLOCK_ID_BCI2_BY2 = 0x13,
- DBG_BLOCK_ID_TCA_BY2 = 0x14,
- DBG_BLOCK_ID_TCCA_BY2 = 0x15,
- DBG_BLOCK_ID_MCC_BY2 = 0x16,
- DBG_BLOCK_ID_MCC2_BY2 = 0x17,
- DBG_BLOCK_ID_MCD_BY2 = 0x18,
- DBG_BLOCK_ID_MCD2_BY2 = 0x19,
- DBG_BLOCK_ID_MCD4_BY2 = 0x1a,
- DBG_BLOCK_ID_MCB_BY2 = 0x1b,
- DBG_BLOCK_ID_SQA_BY2 = 0x1c,
- DBG_BLOCK_ID_SQA02_BY2 = 0x1d,
- DBG_BLOCK_ID_SQA11_BY2 = 0x1e,
- DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f,
- DBG_BLOCK_ID_SQB_BY2 = 0x20,
- DBG_BLOCK_ID_SQB10_BY2 = 0x21,
- DBG_BLOCK_ID_UNUSED10_BY2 = 0x22,
- DBG_BLOCK_ID_UNUSED12_BY2 = 0x23,
- DBG_BLOCK_ID_CB_BY2 = 0x24,
- DBG_BLOCK_ID_CB02_BY2 = 0x25,
- DBG_BLOCK_ID_CB10_BY2 = 0x26,
- DBG_BLOCK_ID_CB12_BY2 = 0x27,
- DBG_BLOCK_ID_SXS_BY2 = 0x28,
- DBG_BLOCK_ID_SXS2_BY2 = 0x29,
- DBG_BLOCK_ID_SXS4_BY2 = 0x2a,
- DBG_BLOCK_ID_SXS6_BY2 = 0x2b,
- DBG_BLOCK_ID_DB_BY2 = 0x2c,
- DBG_BLOCK_ID_DB02_BY2 = 0x2d,
- DBG_BLOCK_ID_DB10_BY2 = 0x2e,
- DBG_BLOCK_ID_DB12_BY2 = 0x2f,
- DBG_BLOCK_ID_TCP_BY2 = 0x30,
- DBG_BLOCK_ID_TCP2_BY2 = 0x31,
- DBG_BLOCK_ID_TCP4_BY2 = 0x32,
- DBG_BLOCK_ID_TCP6_BY2 = 0x33,
- DBG_BLOCK_ID_TCP8_BY2 = 0x34,
- DBG_BLOCK_ID_TCP10_BY2 = 0x35,
- DBG_BLOCK_ID_TCP12_BY2 = 0x36,
- DBG_BLOCK_ID_TCP14_BY2 = 0x37,
- DBG_BLOCK_ID_TCP16_BY2 = 0x38,
- DBG_BLOCK_ID_TCP18_BY2 = 0x39,
- DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
- DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
- DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
- DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
- DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
- DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
- DBG_BLOCK_ID_TCC_BY2 = 0x40,
- DBG_BLOCK_ID_TCC2_BY2 = 0x41,
- DBG_BLOCK_ID_TCC4_BY2 = 0x42,
- DBG_BLOCK_ID_TCC6_BY2 = 0x43,
- DBG_BLOCK_ID_SPS_BY2 = 0x44,
- DBG_BLOCK_ID_SPS02_BY2 = 0x45,
- DBG_BLOCK_ID_SPS11_BY2 = 0x46,
- DBG_BLOCK_ID_UNUSED14_BY2 = 0x47,
- DBG_BLOCK_ID_TA_BY2 = 0x48,
- DBG_BLOCK_ID_TA02_BY2 = 0x49,
- DBG_BLOCK_ID_TA04_BY2 = 0x4a,
- DBG_BLOCK_ID_TA06_BY2 = 0x4b,
- DBG_BLOCK_ID_TA08_BY2 = 0x4c,
- DBG_BLOCK_ID_TA0A_BY2 = 0x4d,
- DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e,
- DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f,
- DBG_BLOCK_ID_TA10_BY2 = 0x50,
- DBG_BLOCK_ID_TA12_BY2 = 0x51,
- DBG_BLOCK_ID_TA14_BY2 = 0x52,
- DBG_BLOCK_ID_TA16_BY2 = 0x53,
- DBG_BLOCK_ID_TA18_BY2 = 0x54,
- DBG_BLOCK_ID_TA1A_BY2 = 0x55,
- DBG_BLOCK_ID_UNUSED24_BY2 = 0x56,
- DBG_BLOCK_ID_UNUSED26_BY2 = 0x57,
- DBG_BLOCK_ID_TD_BY2 = 0x58,
- DBG_BLOCK_ID_TD02_BY2 = 0x59,
- DBG_BLOCK_ID_TD04_BY2 = 0x5a,
- DBG_BLOCK_ID_TD06_BY2 = 0x5b,
- DBG_BLOCK_ID_TD08_BY2 = 0x5c,
- DBG_BLOCK_ID_TD0A_BY2 = 0x5d,
- DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e,
- DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f,
- DBG_BLOCK_ID_TD10_BY2 = 0x60,
- DBG_BLOCK_ID_TD12_BY2 = 0x61,
- DBG_BLOCK_ID_TD14_BY2 = 0x62,
- DBG_BLOCK_ID_TD16_BY2 = 0x63,
- DBG_BLOCK_ID_TD18_BY2 = 0x64,
- DBG_BLOCK_ID_TD1A_BY2 = 0x65,
- DBG_BLOCK_ID_UNUSED32_BY2 = 0x66,
- DBG_BLOCK_ID_UNUSED34_BY2 = 0x67,
- DBG_BLOCK_ID_LDS_BY2 = 0x68,
- DBG_BLOCK_ID_LDS02_BY2 = 0x69,
- DBG_BLOCK_ID_LDS04_BY2 = 0x6a,
- DBG_BLOCK_ID_LDS06_BY2 = 0x6b,
- DBG_BLOCK_ID_LDS08_BY2 = 0x6c,
- DBG_BLOCK_ID_LDS0A_BY2 = 0x6d,
- DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e,
- DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f,
- DBG_BLOCK_ID_LDS10_BY2 = 0x70,
- DBG_BLOCK_ID_LDS12_BY2 = 0x71,
- DBG_BLOCK_ID_LDS14_BY2 = 0x72,
- DBG_BLOCK_ID_LDS16_BY2 = 0x73,
- DBG_BLOCK_ID_LDS18_BY2 = 0x74,
- DBG_BLOCK_ID_LDS1A_BY2 = 0x75,
- DBG_BLOCK_ID_UNUSED40_BY2 = 0x76,
- DBG_BLOCK_ID_UNUSED42_BY2 = 0x77,
-} DebugBlockId_BY2;
-typedef enum DebugBlockId_BY4 {
- DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
- DBG_BLOCK_ID_UNUSED0_BY4 = 0x1,
- DBG_BLOCK_ID_CSC_BY4 = 0x2,
- DBG_BLOCK_ID_SQ_BY4 = 0x3,
- DBG_BLOCK_ID_SDMA0_BY4 = 0x4,
- DBG_BLOCK_ID_VC0_BY4 = 0x5,
- DBG_BLOCK_ID_CP0_BY4 = 0x6,
- DBG_BLOCK_ID_UNUSED1_BY4 = 0x7,
- DBG_BLOCK_ID_SXM0_BY4 = 0x8,
- DBG_BLOCK_ID_SPM0_BY4 = 0x9,
- DBG_BLOCK_ID_TCAA_BY4 = 0xa,
- DBG_BLOCK_ID_MCC_BY4 = 0xb,
- DBG_BLOCK_ID_MCD_BY4 = 0xc,
- DBG_BLOCK_ID_MCD4_BY4 = 0xd,
- DBG_BLOCK_ID_SQA_BY4 = 0xe,
- DBG_BLOCK_ID_SQA11_BY4 = 0xf,
- DBG_BLOCK_ID_SQB_BY4 = 0x10,
- DBG_BLOCK_ID_UNUSED10_BY4 = 0x11,
- DBG_BLOCK_ID_CB_BY4 = 0x12,
- DBG_BLOCK_ID_CB10_BY4 = 0x13,
- DBG_BLOCK_ID_SXS_BY4 = 0x14,
- DBG_BLOCK_ID_SXS4_BY4 = 0x15,
- DBG_BLOCK_ID_DB_BY4 = 0x16,
- DBG_BLOCK_ID_DB10_BY4 = 0x17,
- DBG_BLOCK_ID_TCP_BY4 = 0x18,
- DBG_BLOCK_ID_TCP4_BY4 = 0x19,
- DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
- DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
- DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
- DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
- DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
- DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
- DBG_BLOCK_ID_TCC_BY4 = 0x20,
- DBG_BLOCK_ID_TCC4_BY4 = 0x21,
- DBG_BLOCK_ID_SPS_BY4 = 0x22,
- DBG_BLOCK_ID_SPS11_BY4 = 0x23,
- DBG_BLOCK_ID_TA_BY4 = 0x24,
- DBG_BLOCK_ID_TA04_BY4 = 0x25,
- DBG_BLOCK_ID_TA08_BY4 = 0x26,
- DBG_BLOCK_ID_UNUSED20_BY4 = 0x27,
- DBG_BLOCK_ID_TA10_BY4 = 0x28,
- DBG_BLOCK_ID_TA14_BY4 = 0x29,
- DBG_BLOCK_ID_TA18_BY4 = 0x2a,
- DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b,
- DBG_BLOCK_ID_TD_BY4 = 0x2c,
- DBG_BLOCK_ID_TD04_BY4 = 0x2d,
- DBG_BLOCK_ID_TD08_BY4 = 0x2e,
- DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f,
- DBG_BLOCK_ID_TD10_BY4 = 0x30,
- DBG_BLOCK_ID_TD14_BY4 = 0x31,
- DBG_BLOCK_ID_TD18_BY4 = 0x32,
- DBG_BLOCK_ID_UNUSED32_BY4 = 0x33,
- DBG_BLOCK_ID_LDS_BY4 = 0x34,
- DBG_BLOCK_ID_LDS04_BY4 = 0x35,
- DBG_BLOCK_ID_LDS08_BY4 = 0x36,
- DBG_BLOCK_ID_UNUSED36_BY4 = 0x37,
- DBG_BLOCK_ID_LDS10_BY4 = 0x38,
- DBG_BLOCK_ID_LDS14_BY4 = 0x39,
- DBG_BLOCK_ID_LDS18_BY4 = 0x3a,
- DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b,
-} DebugBlockId_BY4;
-typedef enum DebugBlockId_BY8 {
- DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
- DBG_BLOCK_ID_CSC_BY8 = 0x1,
- DBG_BLOCK_ID_SDMA0_BY8 = 0x2,
- DBG_BLOCK_ID_CP0_BY8 = 0x3,
- DBG_BLOCK_ID_SXM0_BY8 = 0x4,
- DBG_BLOCK_ID_TCA_BY8 = 0x5,
- DBG_BLOCK_ID_MCD_BY8 = 0x6,
- DBG_BLOCK_ID_SQA_BY8 = 0x7,
- DBG_BLOCK_ID_SQB_BY8 = 0x8,
- DBG_BLOCK_ID_CB_BY8 = 0x9,
- DBG_BLOCK_ID_SXS_BY8 = 0xa,
- DBG_BLOCK_ID_DB_BY8 = 0xb,
- DBG_BLOCK_ID_TCP_BY8 = 0xc,
- DBG_BLOCK_ID_TCP8_BY8 = 0xd,
- DBG_BLOCK_ID_TCP16_BY8 = 0xe,
- DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
- DBG_BLOCK_ID_TCC_BY8 = 0x10,
- DBG_BLOCK_ID_SPS_BY8 = 0x11,
- DBG_BLOCK_ID_TA_BY8 = 0x12,
- DBG_BLOCK_ID_TA08_BY8 = 0x13,
- DBG_BLOCK_ID_TA10_BY8 = 0x14,
- DBG_BLOCK_ID_TA18_BY8 = 0x15,
- DBG_BLOCK_ID_TD_BY8 = 0x16,
- DBG_BLOCK_ID_TD08_BY8 = 0x17,
- DBG_BLOCK_ID_TD10_BY8 = 0x18,
- DBG_BLOCK_ID_TD18_BY8 = 0x19,
- DBG_BLOCK_ID_LDS_BY8 = 0x1a,
- DBG_BLOCK_ID_LDS08_BY8 = 0x1b,
- DBG_BLOCK_ID_LDS10_BY8 = 0x1c,
- DBG_BLOCK_ID_LDS18_BY8 = 0x1d,
-} DebugBlockId_BY8;
-typedef enum DebugBlockId_BY16 {
- DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
- DBG_BLOCK_ID_SDMA0_BY16 = 0x1,
- DBG_BLOCK_ID_SXM_BY16 = 0x2,
- DBG_BLOCK_ID_MCD_BY16 = 0x3,
- DBG_BLOCK_ID_SQB_BY16 = 0x4,
- DBG_BLOCK_ID_SXS_BY16 = 0x5,
- DBG_BLOCK_ID_TCP_BY16 = 0x6,
- DBG_BLOCK_ID_TCP16_BY16 = 0x7,
- DBG_BLOCK_ID_TCC_BY16 = 0x8,
- DBG_BLOCK_ID_TA_BY16 = 0x9,
- DBG_BLOCK_ID_TA10_BY16 = 0xa,
- DBG_BLOCK_ID_TD_BY16 = 0xb,
- DBG_BLOCK_ID_TD10_BY16 = 0xc,
- DBG_BLOCK_ID_LDS_BY16 = 0xd,
- DBG_BLOCK_ID_LDS10_BY16 = 0xe,
-} DebugBlockId_BY16;
-typedef enum SurfaceEndian {
- ENDIAN_NONE = 0x0,
- ENDIAN_8IN16 = 0x1,
- ENDIAN_8IN32 = 0x2,
- ENDIAN_8IN64 = 0x3,
-} SurfaceEndian;
-typedef enum ArrayMode {
- ARRAY_LINEAR_GENERAL = 0x0,
- ARRAY_LINEAR_ALIGNED = 0x1,
- ARRAY_1D_TILED_THIN1 = 0x2,
- ARRAY_1D_TILED_THICK = 0x3,
- ARRAY_2D_TILED_THIN1 = 0x4,
- ARRAY_PRT_TILED_THIN1 = 0x5,
- ARRAY_PRT_2D_TILED_THIN1 = 0x6,
- ARRAY_2D_TILED_THICK = 0x7,
- ARRAY_2D_TILED_XTHICK = 0x8,
- ARRAY_PRT_TILED_THICK = 0x9,
- ARRAY_PRT_2D_TILED_THICK = 0xa,
- ARRAY_PRT_3D_TILED_THIN1 = 0xb,
- ARRAY_3D_TILED_THIN1 = 0xc,
- ARRAY_3D_TILED_THICK = 0xd,
- ARRAY_3D_TILED_XTHICK = 0xe,
- ARRAY_PRT_3D_TILED_THICK = 0xf,
-} ArrayMode;
-typedef enum PipeTiling {
- CONFIG_1_PIPE = 0x0,
- CONFIG_2_PIPE = 0x1,
- CONFIG_4_PIPE = 0x2,
- CONFIG_8_PIPE = 0x3,
-} PipeTiling;
-typedef enum BankTiling {
- CONFIG_4_BANK = 0x0,
- CONFIG_8_BANK = 0x1,
-} BankTiling;
-typedef enum GroupInterleave {
- CONFIG_256B_GROUP = 0x0,
- CONFIG_512B_GROUP = 0x1,
-} GroupInterleave;
-typedef enum RowTiling {
- CONFIG_1KB_ROW = 0x0,
- CONFIG_2KB_ROW = 0x1,
- CONFIG_4KB_ROW = 0x2,
- CONFIG_8KB_ROW = 0x3,
- CONFIG_1KB_ROW_OPT = 0x4,
- CONFIG_2KB_ROW_OPT = 0x5,
- CONFIG_4KB_ROW_OPT = 0x6,
- CONFIG_8KB_ROW_OPT = 0x7,
-} RowTiling;
-typedef enum BankSwapBytes {
- CONFIG_128B_SWAPS = 0x0,
- CONFIG_256B_SWAPS = 0x1,
- CONFIG_512B_SWAPS = 0x2,
- CONFIG_1KB_SWAPS = 0x3,
-} BankSwapBytes;
-typedef enum SampleSplitBytes {
- CONFIG_1KB_SPLIT = 0x0,
- CONFIG_2KB_SPLIT = 0x1,
- CONFIG_4KB_SPLIT = 0x2,
- CONFIG_8KB_SPLIT = 0x3,
-} SampleSplitBytes;
-typedef enum NumPipes {
- ADDR_CONFIG_1_PIPE = 0x0,
- ADDR_CONFIG_2_PIPE = 0x1,
- ADDR_CONFIG_4_PIPE = 0x2,
- ADDR_CONFIG_8_PIPE = 0x3,
-} NumPipes;
-typedef enum PipeInterleaveSize {
- ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
- ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
-} PipeInterleaveSize;
-typedef enum BankInterleaveSize {
- ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
- ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
- ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
- ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
-} BankInterleaveSize;
-typedef enum NumShaderEngines {
- ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
- ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
-} NumShaderEngines;
-typedef enum ShaderEngineTileSize {
- ADDR_CONFIG_SE_TILE_16 = 0x0,
- ADDR_CONFIG_SE_TILE_32 = 0x1,
-} ShaderEngineTileSize;
-typedef enum NumGPUs {
- ADDR_CONFIG_1_GPU = 0x0,
- ADDR_CONFIG_2_GPU = 0x1,
- ADDR_CONFIG_4_GPU = 0x2,
-} NumGPUs;
-typedef enum MultiGPUTileSize {
- ADDR_CONFIG_GPU_TILE_16 = 0x0,
- ADDR_CONFIG_GPU_TILE_32 = 0x1,
- ADDR_CONFIG_GPU_TILE_64 = 0x2,
- ADDR_CONFIG_GPU_TILE_128 = 0x3,
-} MultiGPUTileSize;
-typedef enum RowSize {
- ADDR_CONFIG_1KB_ROW = 0x0,
- ADDR_CONFIG_2KB_ROW = 0x1,
- ADDR_CONFIG_4KB_ROW = 0x2,
-} RowSize;
-typedef enum NumLowerPipes {
- ADDR_CONFIG_1_LOWER_PIPES = 0x0,
- ADDR_CONFIG_2_LOWER_PIPES = 0x1,
-} NumLowerPipes;
-typedef enum ColorTransform {
- DCC_CT_AUTO = 0x0,
- DCC_CT_NONE = 0x1,
- ABGR_TO_A_BG_G_RB = 0x2,
- BGRA_TO_BG_G_RB_A = 0x3,
-} ColorTransform;
-typedef enum CompareRef {
- REF_NEVER = 0x0,
- REF_LESS = 0x1,
- REF_EQUAL = 0x2,
- REF_LEQUAL = 0x3,
- REF_GREATER = 0x4,
- REF_NOTEQUAL = 0x5,
- REF_GEQUAL = 0x6,
- REF_ALWAYS = 0x7,
-} CompareRef;
-typedef enum ReadSize {
- READ_256_BITS = 0x0,
- READ_512_BITS = 0x1,
-} ReadSize;
-typedef enum DepthFormat {
- DEPTH_INVALID = 0x0,
- DEPTH_16 = 0x1,
- DEPTH_X8_24 = 0x2,
- DEPTH_8_24 = 0x3,
- DEPTH_X8_24_FLOAT = 0x4,
- DEPTH_8_24_FLOAT = 0x5,
- DEPTH_32_FLOAT = 0x6,
- DEPTH_X24_8_32_FLOAT = 0x7,
-} DepthFormat;
-typedef enum ZFormat {
- Z_INVALID = 0x0,
- Z_16 = 0x1,
- Z_24 = 0x2,
- Z_32_FLOAT = 0x3,
-} ZFormat;
-typedef enum StencilFormat {
- STENCIL_INVALID = 0x0,
- STENCIL_8 = 0x1,
-} StencilFormat;
-typedef enum CmaskMode {
- CMASK_CLEAR_NONE = 0x0,
- CMASK_CLEAR_ONE = 0x1,
- CMASK_CLEAR_ALL = 0x2,
- CMASK_ANY_EXPANDED = 0x3,
- CMASK_ALPHA0_FRAG1 = 0x4,
- CMASK_ALPHA0_FRAG2 = 0x5,
- CMASK_ALPHA0_FRAG4 = 0x6,
- CMASK_ALPHA0_FRAGS = 0x7,
- CMASK_ALPHA1_FRAG1 = 0x8,
- CMASK_ALPHA1_FRAG2 = 0x9,
- CMASK_ALPHA1_FRAG4 = 0xa,
- CMASK_ALPHA1_FRAGS = 0xb,
- CMASK_ALPHAX_FRAG1 = 0xc,
- CMASK_ALPHAX_FRAG2 = 0xd,
- CMASK_ALPHAX_FRAG4 = 0xe,
- CMASK_ALPHAX_FRAGS = 0xf,
-} CmaskMode;
-typedef enum QuadExportFormat {
- EXPORT_UNUSED = 0x0,
- EXPORT_32_R = 0x1,
- EXPORT_32_GR = 0x2,
- EXPORT_32_AR = 0x3,
- EXPORT_FP16_ABGR = 0x4,
- EXPORT_UNSIGNED16_ABGR = 0x5,
- EXPORT_SIGNED16_ABGR = 0x6,
- EXPORT_32_ABGR = 0x7,
-} QuadExportFormat;
-typedef enum QuadExportFormatOld {
- EXPORT_4P_32BPC_ABGR = 0x0,
- EXPORT_4P_16BPC_ABGR = 0x1,
- EXPORT_4P_32BPC_GR = 0x2,
- EXPORT_4P_32BPC_AR = 0x3,
- EXPORT_2P_32BPC_ABGR = 0x4,
- EXPORT_8P_32BPC_R = 0x5,
-} QuadExportFormatOld;
-typedef enum ColorFormat {
- COLOR_INVALID = 0x0,
- COLOR_8 = 0x1,
- COLOR_16 = 0x2,
- COLOR_8_8 = 0x3,
- COLOR_32 = 0x4,
- COLOR_16_16 = 0x5,
- COLOR_10_11_11 = 0x6,
- COLOR_11_11_10 = 0x7,
- COLOR_10_10_10_2 = 0x8,
- COLOR_2_10_10_10 = 0x9,
- COLOR_8_8_8_8 = 0xa,
- COLOR_32_32 = 0xb,
- COLOR_16_16_16_16 = 0xc,
- COLOR_RESERVED_13 = 0xd,
- COLOR_32_32_32_32 = 0xe,
- COLOR_RESERVED_15 = 0xf,
- COLOR_5_6_5 = 0x10,
- COLOR_1_5_5_5 = 0x11,
- COLOR_5_5_5_1 = 0x12,
- COLOR_4_4_4_4 = 0x13,
- COLOR_8_24 = 0x14,
- COLOR_24_8 = 0x15,
- COLOR_X24_8_32_FLOAT = 0x16,
- COLOR_RESERVED_23 = 0x17,
-} ColorFormat;
-typedef enum SurfaceFormat {
- FMT_INVALID = 0x0,
- FMT_8 = 0x1,
- FMT_16 = 0x2,
- FMT_8_8 = 0x3,
- FMT_32 = 0x4,
- FMT_16_16 = 0x5,
- FMT_10_11_11 = 0x6,
- FMT_11_11_10 = 0x7,
- FMT_10_10_10_2 = 0x8,
- FMT_2_10_10_10 = 0x9,
- FMT_8_8_8_8 = 0xa,
- FMT_32_32 = 0xb,
- FMT_16_16_16_16 = 0xc,
- FMT_32_32_32 = 0xd,
- FMT_32_32_32_32 = 0xe,
- FMT_RESERVED_4 = 0xf,
- FMT_5_6_5 = 0x10,
- FMT_1_5_5_5 = 0x11,
- FMT_5_5_5_1 = 0x12,
- FMT_4_4_4_4 = 0x13,
- FMT_8_24 = 0x14,
- FMT_24_8 = 0x15,
- FMT_X24_8_32_FLOAT = 0x16,
- FMT_RESERVED_33 = 0x17,
- FMT_11_11_10_FLOAT = 0x18,
- FMT_16_FLOAT = 0x19,
- FMT_32_FLOAT = 0x1a,
- FMT_16_16_FLOAT = 0x1b,
- FMT_8_24_FLOAT = 0x1c,
- FMT_24_8_FLOAT = 0x1d,
- FMT_32_32_FLOAT = 0x1e,
- FMT_10_11_11_FLOAT = 0x1f,
- FMT_16_16_16_16_FLOAT = 0x20,
- FMT_3_3_2 = 0x21,
- FMT_6_5_5 = 0x22,
- FMT_32_32_32_32_FLOAT = 0x23,
- FMT_RESERVED_36 = 0x24,
- FMT_1 = 0x25,
- FMT_1_REVERSED = 0x26,
- FMT_GB_GR = 0x27,
- FMT_BG_RG = 0x28,
- FMT_32_AS_8 = 0x29,
- FMT_32_AS_8_8 = 0x2a,
- FMT_5_9_9_9_SHAREDEXP = 0x2b,
- FMT_8_8_8 = 0x2c,
- FMT_16_16_16 = 0x2d,
- FMT_16_16_16_FLOAT = 0x2e,
- FMT_4_4 = 0x2f,
- FMT_32_32_32_FLOAT = 0x30,
- FMT_BC1 = 0x31,
- FMT_BC2 = 0x32,
- FMT_BC3 = 0x33,
- FMT_BC4 = 0x34,
- FMT_BC5 = 0x35,
- FMT_BC6 = 0x36,
- FMT_BC7 = 0x37,
- FMT_32_AS_32_32_32_32 = 0x38,
- FMT_APC3 = 0x39,
- FMT_APC4 = 0x3a,
- FMT_APC5 = 0x3b,
- FMT_APC6 = 0x3c,
- FMT_APC7 = 0x3d,
- FMT_CTX1 = 0x3e,
- FMT_RESERVED_63 = 0x3f,
-} SurfaceFormat;
-typedef enum BUF_DATA_FORMAT {
- BUF_DATA_FORMAT_INVALID = 0x0,
- BUF_DATA_FORMAT_8 = 0x1,
- BUF_DATA_FORMAT_16 = 0x2,
- BUF_DATA_FORMAT_8_8 = 0x3,
- BUF_DATA_FORMAT_32 = 0x4,
- BUF_DATA_FORMAT_16_16 = 0x5,
- BUF_DATA_FORMAT_10_11_11 = 0x6,
- BUF_DATA_FORMAT_11_11_10 = 0x7,
- BUF_DATA_FORMAT_10_10_10_2 = 0x8,
- BUF_DATA_FORMAT_2_10_10_10 = 0x9,
- BUF_DATA_FORMAT_8_8_8_8 = 0xa,
- BUF_DATA_FORMAT_32_32 = 0xb,
- BUF_DATA_FORMAT_16_16_16_16 = 0xc,
- BUF_DATA_FORMAT_32_32_32 = 0xd,
- BUF_DATA_FORMAT_32_32_32_32 = 0xe,
- BUF_DATA_FORMAT_RESERVED_15 = 0xf,
-} BUF_DATA_FORMAT;
-typedef enum IMG_DATA_FORMAT {
- IMG_DATA_FORMAT_INVALID = 0x0,
- IMG_DATA_FORMAT_8 = 0x1,
- IMG_DATA_FORMAT_16 = 0x2,
- IMG_DATA_FORMAT_8_8 = 0x3,
- IMG_DATA_FORMAT_32 = 0x4,
- IMG_DATA_FORMAT_16_16 = 0x5,
- IMG_DATA_FORMAT_10_11_11 = 0x6,
- IMG_DATA_FORMAT_11_11_10 = 0x7,
- IMG_DATA_FORMAT_10_10_10_2 = 0x8,
- IMG_DATA_FORMAT_2_10_10_10 = 0x9,
- IMG_DATA_FORMAT_8_8_8_8 = 0xa,
- IMG_DATA_FORMAT_32_32 = 0xb,
- IMG_DATA_FORMAT_16_16_16_16 = 0xc,
- IMG_DATA_FORMAT_32_32_32 = 0xd,
- IMG_DATA_FORMAT_32_32_32_32 = 0xe,
- IMG_DATA_FORMAT_RESERVED_15 = 0xf,
- IMG_DATA_FORMAT_5_6_5 = 0x10,
- IMG_DATA_FORMAT_1_5_5_5 = 0x11,
- IMG_DATA_FORMAT_5_5_5_1 = 0x12,
- IMG_DATA_FORMAT_4_4_4_4 = 0x13,
- IMG_DATA_FORMAT_8_24 = 0x14,
- IMG_DATA_FORMAT_24_8 = 0x15,
- IMG_DATA_FORMAT_X24_8_32 = 0x16,
- IMG_DATA_FORMAT_RESERVED_23 = 0x17,
- IMG_DATA_FORMAT_RESERVED_24 = 0x18,
- IMG_DATA_FORMAT_RESERVED_25 = 0x19,
- IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
- IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
- IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
- IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
- IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
- IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
- IMG_DATA_FORMAT_GB_GR = 0x20,
- IMG_DATA_FORMAT_BG_RG = 0x21,
- IMG_DATA_FORMAT_5_9_9_9 = 0x22,
- IMG_DATA_FORMAT_BC1 = 0x23,
- IMG_DATA_FORMAT_BC2 = 0x24,
- IMG_DATA_FORMAT_BC3 = 0x25,
- IMG_DATA_FORMAT_BC4 = 0x26,
- IMG_DATA_FORMAT_BC5 = 0x27,
- IMG_DATA_FORMAT_BC6 = 0x28,
- IMG_DATA_FORMAT_BC7 = 0x29,
- IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
- IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
- IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
- IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
- IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
- IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
- IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
- IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
- IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
- IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
- IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
- IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
- IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
- IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
- IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
- IMG_DATA_FORMAT_4_4 = 0x39,
- IMG_DATA_FORMAT_6_5_5 = 0x3a,
- IMG_DATA_FORMAT_1 = 0x3b,
- IMG_DATA_FORMAT_1_REVERSED = 0x3c,
- IMG_DATA_FORMAT_32_AS_8 = 0x3d,
- IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
- IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
-} IMG_DATA_FORMAT;
-typedef enum BUF_NUM_FORMAT {
- BUF_NUM_FORMAT_UNORM = 0x0,
- BUF_NUM_FORMAT_SNORM = 0x1,
- BUF_NUM_FORMAT_USCALED = 0x2,
- BUF_NUM_FORMAT_SSCALED = 0x3,
- BUF_NUM_FORMAT_UINT = 0x4,
- BUF_NUM_FORMAT_SINT = 0x5,
- BUF_NUM_FORMAT_RESERVED_6 = 0x6,
- BUF_NUM_FORMAT_FLOAT = 0x7,
-} BUF_NUM_FORMAT;
-typedef enum IMG_NUM_FORMAT {
- IMG_NUM_FORMAT_UNORM = 0x0,
- IMG_NUM_FORMAT_SNORM = 0x1,
- IMG_NUM_FORMAT_USCALED = 0x2,
- IMG_NUM_FORMAT_SSCALED = 0x3,
- IMG_NUM_FORMAT_UINT = 0x4,
- IMG_NUM_FORMAT_SINT = 0x5,
- IMG_NUM_FORMAT_RESERVED_6 = 0x6,
- IMG_NUM_FORMAT_FLOAT = 0x7,
- IMG_NUM_FORMAT_RESERVED_8 = 0x8,
- IMG_NUM_FORMAT_SRGB = 0x9,
- IMG_NUM_FORMAT_RESERVED_10 = 0xa,
- IMG_NUM_FORMAT_RESERVED_11 = 0xb,
- IMG_NUM_FORMAT_RESERVED_12 = 0xc,
- IMG_NUM_FORMAT_RESERVED_13 = 0xd,
- IMG_NUM_FORMAT_RESERVED_14 = 0xe,
- IMG_NUM_FORMAT_RESERVED_15 = 0xf,
-} IMG_NUM_FORMAT;
-typedef enum TileType {
- ARRAY_COLOR_TILE = 0x0,
- ARRAY_DEPTH_TILE = 0x1,
-} TileType;
-typedef enum NonDispTilingOrder {
- ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
- ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
-} NonDispTilingOrder;
-typedef enum MicroTileMode {
- ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
- ADDR_SURF_THIN_MICRO_TILING = 0x1,
- ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
- ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
- ADDR_SURF_THICK_MICRO_TILING = 0x4,
-} MicroTileMode;
-typedef enum TileSplit {
- ADDR_SURF_TILE_SPLIT_64B = 0x0,
- ADDR_SURF_TILE_SPLIT_128B = 0x1,
- ADDR_SURF_TILE_SPLIT_256B = 0x2,
- ADDR_SURF_TILE_SPLIT_512B = 0x3,
- ADDR_SURF_TILE_SPLIT_1KB = 0x4,
- ADDR_SURF_TILE_SPLIT_2KB = 0x5,
- ADDR_SURF_TILE_SPLIT_4KB = 0x6,
-} TileSplit;
-typedef enum SampleSplit {
- ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
- ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
- ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
- ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
-} SampleSplit;
-typedef enum PipeConfig {
- ADDR_SURF_P2 = 0x0,
- ADDR_SURF_P2_RESERVED0 = 0x1,
- ADDR_SURF_P2_RESERVED1 = 0x2,
- ADDR_SURF_P2_RESERVED2 = 0x3,
- ADDR_SURF_P4_8x16 = 0x4,
- ADDR_SURF_P4_16x16 = 0x5,
- ADDR_SURF_P4_16x32 = 0x6,
- ADDR_SURF_P4_32x32 = 0x7,
- ADDR_SURF_P8_16x16_8x16 = 0x8,
- ADDR_SURF_P8_16x32_8x16 = 0x9,
- ADDR_SURF_P8_32x32_8x16 = 0xa,
- ADDR_SURF_P8_16x32_16x16 = 0xb,
- ADDR_SURF_P8_32x32_16x16 = 0xc,
- ADDR_SURF_P8_32x32_16x32 = 0xd,
- ADDR_SURF_P8_32x64_32x32 = 0xe,
- ADDR_SURF_P8_RESERVED0 = 0xf,
- ADDR_SURF_P16_32x32_8x16 = 0x10,
- ADDR_SURF_P16_32x32_16x16 = 0x11,
-} PipeConfig;
-typedef enum NumBanks {
- ADDR_SURF_2_BANK = 0x0,
- ADDR_SURF_4_BANK = 0x1,
- ADDR_SURF_8_BANK = 0x2,
- ADDR_SURF_16_BANK = 0x3,
-} NumBanks;
-typedef enum BankWidth {
- ADDR_SURF_BANK_WIDTH_1 = 0x0,
- ADDR_SURF_BANK_WIDTH_2 = 0x1,
- ADDR_SURF_BANK_WIDTH_4 = 0x2,
- ADDR_SURF_BANK_WIDTH_8 = 0x3,
-} BankWidth;
-typedef enum BankHeight {
- ADDR_SURF_BANK_HEIGHT_1 = 0x0,
- ADDR_SURF_BANK_HEIGHT_2 = 0x1,
- ADDR_SURF_BANK_HEIGHT_4 = 0x2,
- ADDR_SURF_BANK_HEIGHT_8 = 0x3,
-} BankHeight;
-typedef enum BankWidthHeight {
- ADDR_SURF_BANK_WH_1 = 0x0,
- ADDR_SURF_BANK_WH_2 = 0x1,
- ADDR_SURF_BANK_WH_4 = 0x2,
- ADDR_SURF_BANK_WH_8 = 0x3,
-} BankWidthHeight;
-typedef enum MacroTileAspect {
- ADDR_SURF_MACRO_ASPECT_1 = 0x0,
- ADDR_SURF_MACRO_ASPECT_2 = 0x1,
- ADDR_SURF_MACRO_ASPECT_4 = 0x2,
- ADDR_SURF_MACRO_ASPECT_8 = 0x3,
-} MacroTileAspect;
-typedef enum GATCL1RequestType {
- GATCL1_TYPE_NORMAL = 0x0,
- GATCL1_TYPE_SHOOTDOWN = 0x1,
- GATCL1_TYPE_BYPASS = 0x2,
-} GATCL1RequestType;
-typedef enum TCC_CACHE_POLICIES {
- TCC_CACHE_POLICY_LRU = 0x0,
- TCC_CACHE_POLICY_STREAM = 0x1,
-} TCC_CACHE_POLICIES;
-typedef enum MTYPE {
- MTYPE_NC_NV = 0x0,
- MTYPE_NC = 0x1,
- MTYPE_CC = 0x2,
- MTYPE_UC = 0x3,
-} MTYPE;
-typedef enum PERFMON_COUNTER_MODE {
- PERFMON_COUNTER_MODE_ACCUM = 0x0,
- PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
- PERFMON_COUNTER_MODE_MAX = 0x2,
- PERFMON_COUNTER_MODE_DIRTY = 0x3,
- PERFMON_COUNTER_MODE_SAMPLE = 0x4,
- PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
- PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
- PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
- PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
- PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
- PERFMON_COUNTER_MODE_RESERVED = 0xf,
-} PERFMON_COUNTER_MODE;
-typedef enum PERFMON_SPM_MODE {
- PERFMON_SPM_MODE_OFF = 0x0,
- PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
- PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
- PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
- PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
- PERFMON_SPM_MODE_RESERVED_5 = 0x5,
- PERFMON_SPM_MODE_RESERVED_6 = 0x6,
- PERFMON_SPM_MODE_RESERVED_7 = 0x7,
- PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
- PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
- PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
-} PERFMON_SPM_MODE;
-typedef enum SurfaceTiling {
- ARRAY_LINEAR = 0x0,
- ARRAY_TILED = 0x1,
-} SurfaceTiling;
-typedef enum SurfaceArray {
- ARRAY_1D = 0x0,
- ARRAY_2D = 0x1,
- ARRAY_3D = 0x2,
- ARRAY_3D_SLICE = 0x3,
-} SurfaceArray;
-typedef enum ColorArray {
- ARRAY_2D_ALT_COLOR = 0x0,
- ARRAY_2D_COLOR = 0x1,
- ARRAY_3D_SLICE_COLOR = 0x3,
-} ColorArray;
-typedef enum DepthArray {
- ARRAY_2D_ALT_DEPTH = 0x0,
- ARRAY_2D_DEPTH = 0x1,
-} DepthArray;
-typedef enum ENUM_NUM_SIMD_PER_CU {
- NUM_SIMD_PER_CU = 0x4,
-} ENUM_NUM_SIMD_PER_CU;
-typedef enum MEM_PWR_FORCE_CTRL {
- NO_FORCE_REQUEST = 0x0,
- FORCE_LIGHT_SLEEP_REQUEST = 0x1,
- FORCE_DEEP_SLEEP_REQUEST = 0x2,
- FORCE_SHUT_DOWN_REQUEST = 0x3,
-} MEM_PWR_FORCE_CTRL;
-typedef enum MEM_PWR_FORCE_CTRL2 {
- NO_FORCE_REQ = 0x0,
- FORCE_LIGHT_SLEEP_REQ = 0x1,
-} MEM_PWR_FORCE_CTRL2;
-typedef enum MEM_PWR_DIS_CTRL {
- ENABLE_MEM_PWR_CTRL = 0x0,
- DISABLE_MEM_PWR_CTRL = 0x1,
-} MEM_PWR_DIS_CTRL;
-typedef enum MEM_PWR_SEL_CTRL {
- DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
- DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
- DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
-} MEM_PWR_SEL_CTRL;
-typedef enum MEM_PWR_SEL_CTRL2 {
- DYNAMIC_DEEP_SLEEP_EN = 0x0,
- DYNAMIC_LIGHT_SLEEP_EN = 0x1,
-} MEM_PWR_SEL_CTRL2;
-
-#endif /* BIF_5_1_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_enum.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_enum.h
deleted file mode 100644
index b2ea4202d..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_enum.h
+++ /dev/null
@@ -1,6813 +0,0 @@
-/*
- * DCE_11_2 Register documentation
- *
- * Copyright (C) 2016 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef DCE_11_2_ENUM_H
-#define DCE_11_2_ENUM_H
-
-typedef enum CRTC_CONTROL_CRTC_START_POINT_CNTL {
- CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL = 0x0,
- CRTC_CONTROL_CRTC_START_POINT_CNTL_DP = 0x1,
-} CRTC_CONTROL_CRTC_START_POINT_CNTL;
-typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL {
- CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL = 0x0,
- CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP = 0x1,
-} CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL;
-typedef enum CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL {
- CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE = 0x0,
- CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT= 0x1,
- CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED = 0x2,
- CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST= 0x3,
-} CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL;
-typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY {
- CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE = 0x0,
- CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE = 0x1,
-} CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY;
-typedef enum CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE {
- CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_FALSE= 0x0,
- CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE = 0x1,
-} CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE;
-typedef enum CRTC_CONTROL_CRTC_SOF_PULL_EN {
- CRTC_CONTROL_CRTC_SOF_PULL_EN_FALSE = 0x0,
- CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE = 0x1,
-} CRTC_CONTROL_CRTC_SOF_PULL_EN;
-typedef enum CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL {
- CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_FALSE = 0x0,
- CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE = 0x1,
-} CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL;
-typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL {
- CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_FALSE = 0x0,
- CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE = 0x1,
-} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL;
-typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL {
- CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_FALSE = 0x0,
- CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE = 0x1,
-} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL;
-typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN {
- CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_FALSE= 0x0,
- CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE= 0x1,
-} CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN;
-typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC {
- CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE= 0x0,
- CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE= 0x1,
-} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC;
-typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT {
- CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_DISABLE= 0x0,
- CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_ENABLE= 0x1,
-} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT;
-typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK {
- CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_FRAME_START= 0x0,
- CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CRTC_TRIG_A= 0x1,
- CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CRTC_TRIG_B= 0x2,
- CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CURSOR_CHANGE= 0x3,
- CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_OTHER_CLIENT= 0x4,
- CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION0= 0x5,
- CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION1= 0x6,
- CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION2= 0x7,
- CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION3= 0x8,
- CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_GRAPHIC_UPDATE_PENDING= 0x9,
- CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_RESERVED2= 0xa,
- CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_INVALID= 0xb,
- CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_DOUBLE_BUFFER= 0xc,
- CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_D1CRTC_VERT_COUNT_NOM= 0xd,
- CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_D1CRTC_VERT_COUNT= 0xe,
- CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_RESERVED= 0xf,
-} CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK;
-typedef enum CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK {
- CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE= 0x0,
- CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE= 0x1,
-} CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK;
-typedef enum CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR {
- CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_FALSE= 0x0,
- CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_TRUE= 0x1,
-} CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR;
-typedef enum CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL {
- CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_FALSE = 0x0,
- CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_TRUE = 0x1,
-} CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL;
-typedef enum CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN {
- CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_FALSE = 0x0,
- CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_TRUE = 0x1,
-} CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN;
-typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT {
- CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA_OTHER= 0x1,
- CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA_OTHER= 0x2,
- CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICF= 0x5,
- CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICE= 0x6,
- CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA = 0x7,
- CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA = 0x8,
- CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCB = 0x9,
- CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCB = 0xa,
- CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD1 = 0xb,
- CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD2 = 0xc,
- CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICD= 0xd,
- CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICC= 0xe,
- CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL0 = 0x10,
- CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL1 = 0x11,
- CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL2 = 0x12,
- CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IBLON = 0x13,
- CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICA= 0x14,
- CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICB= 0x15,
- CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL_ALLOW= 0x16,
- CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_MANUAL_FLOW= 0x17,
-} CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT;
-typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT {
- CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_INTERLACE= 0x1,
- CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICA= 0x2,
- CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICB= 0x3,
- CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCA= 0x4,
- CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCB= 0x5,
- CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_VIDEO = 0x6,
- CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICC= 0x7,
-} CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT;
-typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN {
- CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_FALSE= 0x0,
- CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_TRUE = 0x1,
-} CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN;
-typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR {
- CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_FALSE = 0x0,
- CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_TRUE = 0x1,
-} CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR;
-typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT {
- CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA_OTHER= 0x1,
- CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA_OTHER= 0x2,
- CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICF= 0x5,
- CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICE= 0x6,
- CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA = 0x7,
- CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA = 0x8,
- CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCB = 0x9,
- CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCB = 0xa,
- CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD1 = 0xb,
- CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD2 = 0xc,
- CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICD= 0xd,
- CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICC= 0xe,
- CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL0 = 0x10,
- CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL1 = 0x11,
- CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL2 = 0x12,
- CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IBLON = 0x13,
- CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICA= 0x14,
- CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICB= 0x15,
- CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL_ALLOW= 0x16,
- CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_MANUAL_FLOW= 0x17,
-} CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT;
-typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT {
- CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_INTERLACE= 0x1,
- CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICA= 0x2,
- CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB= 0x3,
- CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCA= 0x4,
- CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCB= 0x5,
- CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_VIDEO = 0x6,
- CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICC= 0x7,
-} CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT;
-typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN {
- CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_FALSE= 0x0,
- CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_TRUE = 0x1,
-} CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN;
-typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR {
- CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_FALSE = 0x0,
- CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_TRUE = 0x1,
-} CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR;
-typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE {
- CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_DISABLE= 0x0,
- CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT= 0x1,
- CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT= 0x2,
- CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_RESERVED= 0x3,
-} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE;
-typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK {
- CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_FALSE= 0x0,
- CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_TRUE= 0x1,
-} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK;
-typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL {
- CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_FALSE= 0x0,
- CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_TRUE= 0x1,
-} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL;
-typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR {
- CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_FALSE= 0x0,
- CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_TRUE= 0x1,
-} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR;
-typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT {
- CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC0= 0x0,
- CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICF= 0x1,
- CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICE= 0x2,
- CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD1= 0x3,
- CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD2= 0x4,
- CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA= 0x5,
- CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK= 0x6,
- CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA= 0x7,
- CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK= 0x8,
- CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DVOCLK= 0x9,
- CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_MANUAL= 0xa,
- CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC1= 0xb,
- CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICB= 0xc,
- CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICA= 0xd,
- CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICD= 0xe,
- CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICC= 0xf,
-} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT;
-typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY {
- CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_FALSE= 0x0,
- CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_TRUE= 0x1,
-} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY;
-typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY {
- CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_FALSE= 0x0,
- CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_TRUE= 0x1,
-} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY;
-typedef enum CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE {
- CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_NO= 0x0,
- CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RIGHT= 0x1,
- CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_LEFT= 0x2,
- CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RESERVED= 0x3,
-} CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE;
-typedef enum CRTC_CONTROL_CRTC_MASTER_EN {
- CRTC_CONTROL_CRTC_MASTER_EN_FALSE = 0x0,
- CRTC_CONTROL_CRTC_MASTER_EN_TRUE = 0x1,
-} CRTC_CONTROL_CRTC_MASTER_EN;
-typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN {
- CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_FALSE = 0x0,
- CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_TRUE = 0x1,
-} CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN;
-typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE {
- CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_FALSE = 0x0,
- CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_TRUE = 0x1,
-} CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE;
-typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE {
- CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_FALSE= 0x0,
- CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_TRUE= 0x1,
-} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE;
-typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD {
- CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT= 0x0,
- CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD= 0x1,
- CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN= 0x2,
- CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT2= 0x3,
-} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD;
-typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY {
- CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_FALSE= 0x0,
- CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_TRUE= 0x1,
-} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY;
-typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT {
- CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_FALSE= 0x0,
- CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_TRUE= 0x1,
-} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT;
-typedef enum CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN {
- CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_FALSE = 0x0,
- CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_TRUE = 0x1,
-} CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN;
-typedef enum CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE {
- CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE= 0x0,
- CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE= 0x1,
-} CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE;
-typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR {
- CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE= 0x0,
- CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE= 0x1,
-} CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR;
-typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE {
- CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_DISABLE= 0x0,
- CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERA= 0x1,
- CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERB= 0x2,
- CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED= 0x3,
-} CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE;
-typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY {
- CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_FALSE= 0x0,
- CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_TRUE= 0x1,
-} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY;
-typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY {
- CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_FALSE= 0x0,
- CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_TRUE= 0x1,
-} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY;
-typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY {
- CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_FALSE= 0x0,
- CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_TRUE= 0x1,
-} CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY;
-typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EN {
- CRTC_STEREO_CONTROL_CRTC_STEREO_EN_FALSE = 0x0,
- CRTC_STEREO_CONTROL_CRTC_STEREO_EN_TRUE = 0x1,
-} CRTC_STEREO_CONTROL_CRTC_STEREO_EN;
-typedef enum CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR {
- CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_FALSE = 0x0,
- CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_TRUE = 0x1,
-} CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR;
-typedef enum CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL {
- CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_DISABLE= 0x0,
- CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA= 0x1,
- CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB= 0x2,
- CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_RESERVED= 0x3,
-} CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL;
-typedef enum CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY {
- CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_FALSE= 0x0,
- CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_TRUE= 0x1,
-} CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY;
-typedef enum CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY {
- CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_FALSE= 0x0,
- CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_TRUE= 0x1,
-} CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY;
-typedef enum CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN {
- CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_FALSE= 0x0,
- CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_TRUE= 0x1,
-} CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN;
-typedef enum CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN {
- CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_FALSE = 0x0,
- CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_TRUE = 0x1,
-} CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN;
-typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK {
- CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_FALSE= 0x0,
- CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_TRUE= 0x1,
-} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK;
-typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE {
- CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_FALSE= 0x0,
- CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_TRUE= 0x1,
-} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE;
-typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK {
- CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_FALSE= 0x0,
- CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_TRUE= 0x1,
-} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK;
-typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE {
- CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_FALSE= 0x0,
- CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_TRUE= 0x1,
-} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE;
-typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK {
- CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_FALSE= 0x0,
- CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_TRUE= 0x1,
-} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK;
-typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE {
- CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_FALSE= 0x0,
- CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_TRUE= 0x1,
-} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE;
-typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK {
- CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE= 0x0,
- CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE= 0x1,
-} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK;
-typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE {
- CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE= 0x0,
- CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE= 0x1,
-} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE;
-typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK {
- CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_FALSE = 0x0,
- CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_TRUE = 0x1,
-} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK;
-typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE {
- CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_FALSE = 0x0,
- CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_TRUE = 0x1,
-} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE;
-typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK {
- CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_FALSE = 0x0,
- CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_TRUE = 0x1,
-} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK;
-typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE {
- CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_FALSE = 0x0,
- CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_TRUE = 0x1,
-} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE;
-typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK {
- CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_FALSE= 0x0,
- CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_TRUE= 0x1,
-} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK;
-typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE {
- CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_FALSE= 0x0,
- CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_TRUE= 0x1,
-} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE;
-typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK {
- CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_FALSE= 0x0,
- CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_TRUE= 0x1,
-} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK;
-typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE {
- CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_FALSE= 0x0,
- CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_TRUE= 0x1,
-} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE;
-typedef enum CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK {
- CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_FALSE = 0x0,
- CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_TRUE = 0x1,
-} CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK;
-typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY {
- CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_FALSE= 0x0,
- CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_TRUE= 0x1,
-} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY;
-typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN {
- CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE= 0x0,
- CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE= 0x1,
-} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN;
-typedef enum CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE {
- CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_FALSE= 0x0,
- CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_TRUE= 0x1,
-} CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE;
-typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN {
- CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_FALSE= 0x0,
- CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_TRUE= 0x1,
-} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN;
-typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE {
- CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_RGB= 0x0,
- CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR601= 0x1,
- CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR709= 0x2,
- CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_VBARS= 0x3,
- CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_HBARS= 0x4,
- CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_SRRGB= 0x5,
- CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_DRRGB= 0x6,
- CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_XRBIAS= 0x7,
-} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE;
-typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE {
- CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_FALSE= 0x0,
- CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_TRUE= 0x1,
-} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE;
-typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT {
- CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_6BPC= 0x0,
- CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_8BPC= 0x1,
- CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_10BPC= 0x2,
- CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_RESERVED= 0x3,
-} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT;
-typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK {
- MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0x0,
- MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 0x1,
-} MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK;
-typedef enum MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK {
- MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_FALSE= 0x0,
- MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_TRUE= 0x1,
-} MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK;
-typedef enum MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK {
- MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE = 0x0,
- MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE = 0x1,
-} MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK;
-typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_MODE {
- MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BETWEEN = 0x0,
- MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_HSYNCA = 0x1,
- MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_VSYNCA = 0x2,
- MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BEFORE = 0x3,
-} MASTER_UPDATE_MODE_MASTER_UPDATE_MODE;
-typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE {
- MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH= 0x0,
- MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_EVEN= 0x1,
- MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_ODD= 0x2,
- MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED= 0x3,
-} MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE;
-typedef enum CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE {
- CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DISABLE= 0x0,
- CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DEBUG= 0x1,
- CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_NORMAL= 0x2,
-} CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE;
-typedef enum CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR {
- CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_FALSE = 0x0,
- CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_TRUE = 0x1,
-} CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR;
-typedef enum CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR {
- CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE= 0x0,
- CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE= 0x1,
-} CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR;
-typedef enum CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR {
- CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_FALSE= 0x0,
- CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_TRUE= 0x1,
-} CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR;
-typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY {
- CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE= 0x0,
- CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE= 0x1,
-} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY;
-typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE {
- CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE= 0x0,
- CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE= 0x1,
-} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE;
-typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR {
- CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_FALSE= 0x0,
- CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_TRUE= 0x1,
-} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR;
-typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE {
- CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_FALSE= 0x0,
- CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_TRUE= 0x1,
-} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE;
-typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR {
- CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE= 0x0,
- CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_TRUE= 0x1,
-} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR;
-typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE {
- CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE= 0x0,
- CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE= 0x1,
-} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE;
-typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE {
- CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_FALSE= 0x0,
- CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_TRUE= 0x1,
-} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE;
-typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR {
- CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE= 0x0,
- CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_TRUE= 0x1,
-} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR;
-typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE {
- CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE= 0x0,
- CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE= 0x1,
-} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE;
-typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE {
- CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_FALSE= 0x0,
- CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_TRUE= 0x1,
-} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE;
-typedef enum CRTC_CRC_CNTL_CRTC_CRC_EN {
- CRTC_CRC_CNTL_CRTC_CRC_EN_FALSE = 0x0,
- CRTC_CRC_CNTL_CRTC_CRC_EN_TRUE = 0x1,
-} CRTC_CRC_CNTL_CRTC_CRC_EN;
-typedef enum CRTC_CRC_CNTL_CRTC_CRC_CONT_EN {
- CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_FALSE = 0x0,
- CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_TRUE = 0x1,
-} CRTC_CRC_CNTL_CRTC_CRC_CONT_EN;
-typedef enum CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE {
- CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_LEFT = 0x0,
- CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_RIGHT = 0x1,
- CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_EYES = 0x2,
- CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_FIELDS = 0x3,
-} CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE;
-typedef enum CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE {
- CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_TOP = 0x0,
- CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTTOM = 0x1,
- CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_BOTTOM= 0x2,
- CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_FIELD = 0x3,
-} CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE;
-typedef enum CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS {
- CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE= 0x0,
- CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE= 0x1,
-} CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS;
-typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT {
- CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UAB = 0x0,
- CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UA_B = 0x1,
- CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_AB = 0x2,
- CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_A_B = 0x3,
- CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IAB = 0x4,
- CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IA_B = 0x5,
- CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_AB = 0x6,
- CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_A_B = 0x7,
-} CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT;
-typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT {
- CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UAB = 0x0,
- CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UA_B = 0x1,
- CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_AB = 0x2,
- CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_A_B = 0x3,
- CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IAB = 0x4,
- CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IA_B = 0x5,
- CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_AB = 0x6,
- CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_A_B = 0x7,
-} CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT;
-typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE {
- CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_DISABLE= 0x0,
- CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_ONESHOT= 0x1,
- CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_CONTINUOUS= 0x2,
- CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_RESERVED= 0x3,
-} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE;
-typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE {
- CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE= 0x0,
- CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE= 0x1,
-} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE;
-typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE {
- CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE= 0x0,
- CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE= 0x1,
-} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE;
-typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW {
- CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel= 0x0,
- CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel= 0x1,
- CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel= 0x2,
- CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel= 0x3,
-} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW;
-typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE {
- CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE= 0x0,
- CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE= 0x1,
-} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE;
-typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE {
- CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE= 0x0,
- CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE= 0x1,
-} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE;
-typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY {
- CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE= 0x0,
- CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE= 0x1,
-} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY;
-typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY {
- CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE= 0x0,
- CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE= 0x1,
-} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY;
-typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE {
- CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE= 0x0,
- CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE= 0x1,
-} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE;
-typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE {
- CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE= 0x0,
- CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE= 0x1,
-} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE;
-typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR {
- CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE= 0x0,
- CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE= 0x1,
-} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR;
-typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE {
- CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE= 0x0,
- CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE= 0x1,
-} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE;
-typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT {
- CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME= 0x0,
- CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME= 0x1,
- CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME= 0x2,
- CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME= 0x3,
- CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME= 0x4,
- CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME= 0x5,
- CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME= 0x6,
- CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME= 0x7,
-} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT;
-typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE {
- CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_FALSE= 0x0,
- CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_TRUE= 0x1,
-} CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE;
-typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR {
- CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_FALSE= 0x0,
- CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_TRUE= 0x1,
-} CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR;
-typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE {
- CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_FALSE= 0x0,
- CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_TRUE= 0x1,
-} CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE;
-typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE {
- CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE= 0x0,
- CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE= 0x1,
-} CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE;
-typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR {
- CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE= 0x0,
- CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE= 0x1,
-} CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR;
-typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE {
- CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE= 0x0,
- CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE= 0x1,
-} CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE;
-typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE {
- CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_FALSE= 0x0,
- CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_TRUE= 0x1,
-} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE;
-typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR {
- CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_FALSE= 0x0,
- CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_TRUE= 0x1,
-} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR;
-typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE {
- CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_FALSE= 0x0,
- CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_TRUE= 0x1,
-} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE;
-typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE {
- CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_FALSE= 0x0,
- CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_TRUE= 0x1,
-} CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE;
-typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE {
- CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_OFF= 0x0,
- CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_ON= 0x1,
-} CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE;
-typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN {
- CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_FALSE= 0x0,
- CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_TRUE= 0x1,
-} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN;
-typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB {
- CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_FALSE= 0x0,
- CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_TRUE= 0x1,
-} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB;
-typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE {
- CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH= 0x0,
- CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE= 0x1,
- CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE= 0x2,
- CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_RESERVED= 0x3,
-} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE;
-typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR {
- CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_FALSE= 0x0,
- CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_TRUE= 0x1,
-} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR;
-typedef enum CRTC_V_SYNC_A_POL {
- CRTC_V_SYNC_A_POL_HIGH = 0x0,
- CRTC_V_SYNC_A_POL_LOW = 0x1,
-} CRTC_V_SYNC_A_POL;
-typedef enum CRTC_H_SYNC_A_POL {
- CRTC_H_SYNC_A_POL_HIGH = 0x0,
- CRTC_H_SYNC_A_POL_LOW = 0x1,
-} CRTC_H_SYNC_A_POL;
-typedef enum CRTC_HORZ_REPETITION_COUNT {
- CRTC_HORZ_REPETITION_COUNT_0 = 0x0,
- CRTC_HORZ_REPETITION_COUNT_1 = 0x1,
- CRTC_HORZ_REPETITION_COUNT_2 = 0x2,
- CRTC_HORZ_REPETITION_COUNT_3 = 0x3,
- CRTC_HORZ_REPETITION_COUNT_4 = 0x4,
- CRTC_HORZ_REPETITION_COUNT_5 = 0x5,
- CRTC_HORZ_REPETITION_COUNT_6 = 0x6,
- CRTC_HORZ_REPETITION_COUNT_7 = 0x7,
- CRTC_HORZ_REPETITION_COUNT_8 = 0x8,
- CRTC_HORZ_REPETITION_COUNT_9 = 0x9,
- CRTC_HORZ_REPETITION_COUNT_10 = 0xa,
- CRTC_HORZ_REPETITION_COUNT_11 = 0xb,
- CRTC_HORZ_REPETITION_COUNT_12 = 0xc,
- CRTC_HORZ_REPETITION_COUNT_13 = 0xd,
- CRTC_HORZ_REPETITION_COUNT_14 = 0xe,
- CRTC_HORZ_REPETITION_COUNT_15 = 0xf,
-} CRTC_HORZ_REPETITION_COUNT;
-typedef enum PERFCOUNTER_CVALUE_SEL {
- PERFCOUNTER_CVALUE_SEL_47_0 = 0x0,
- PERFCOUNTER_CVALUE_SEL_15_0 = 0x1,
- PERFCOUNTER_CVALUE_SEL_31_16 = 0x2,
- PERFCOUNTER_CVALUE_SEL_47_32 = 0x3,
- PERFCOUNTER_CVALUE_SEL_11_0 = 0x4,
- PERFCOUNTER_CVALUE_SEL_23_12 = 0x5,
- PERFCOUNTER_CVALUE_SEL_35_24 = 0x6,
- PERFCOUNTER_CVALUE_SEL_47_36 = 0x7,
-} PERFCOUNTER_CVALUE_SEL;
-typedef enum PERFCOUNTER_INC_MODE {
- PERFCOUNTER_INC_MODE_MULTI_BIT = 0x0,
- PERFCOUNTER_INC_MODE_BOTH_EDGE = 0x1,
- PERFCOUNTER_INC_MODE_LSB = 0x2,
- PERFCOUNTER_INC_MODE_POS_EDGE = 0x3,
-} PERFCOUNTER_INC_MODE;
-typedef enum PERFCOUNTER_HW_CNTL_SEL {
- PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0x0,
- PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 0x1,
-} PERFCOUNTER_HW_CNTL_SEL;
-typedef enum PERFCOUNTER_RUNEN_MODE {
- PERFCOUNTER_RUNEN_MODE_LEVEL = 0x0,
- PERFCOUNTER_RUNEN_MODE_EDGE = 0x1,
-} PERFCOUNTER_RUNEN_MODE;
-typedef enum PERFCOUNTER_CNTOFF_START_DIS {
- PERFCOUNTER_CNTOFF_START_ENABLE = 0x0,
- PERFCOUNTER_CNTOFF_START_DISABLE = 0x1,
-} PERFCOUNTER_CNTOFF_START_DIS;
-typedef enum PERFCOUNTER_RESTART_EN {
- PERFCOUNTER_RESTART_DISABLE = 0x0,
- PERFCOUNTER_RESTART_ENABLE = 0x1,
-} PERFCOUNTER_RESTART_EN;
-typedef enum PERFCOUNTER_INT_EN {
- PERFCOUNTER_INT_DISABLE = 0x0,
- PERFCOUNTER_INT_ENABLE = 0x1,
-} PERFCOUNTER_INT_EN;
-typedef enum PERFCOUNTER_OFF_MASK {
- PERFCOUNTER_OFF_MASK_DISABLE = 0x0,
- PERFCOUNTER_OFF_MASK_ENABLE = 0x1,
-} PERFCOUNTER_OFF_MASK;
-typedef enum PERFCOUNTER_ACTIVE {
- PERFCOUNTER_IS_IDLE = 0x0,
- PERFCOUNTER_IS_ACTIVE = 0x1,
-} PERFCOUNTER_ACTIVE;
-typedef enum PERFCOUNTER_INT_TYPE {
- PERFCOUNTER_INT_TYPE_LEVEL = 0x0,
- PERFCOUNTER_INT_TYPE_PULSE = 0x1,
-} PERFCOUNTER_INT_TYPE;
-typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE {
- PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0x0,
- PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 0x1,
-} PERFCOUNTER_COUNTED_VALUE_TYPE;
-typedef enum PERFCOUNTER_CNTL_SEL {
- PERFCOUNTER_CNTL_SEL_0 = 0x0,
- PERFCOUNTER_CNTL_SEL_1 = 0x1,
- PERFCOUNTER_CNTL_SEL_2 = 0x2,
- PERFCOUNTER_CNTL_SEL_3 = 0x3,
- PERFCOUNTER_CNTL_SEL_4 = 0x4,
- PERFCOUNTER_CNTL_SEL_5 = 0x5,
- PERFCOUNTER_CNTL_SEL_6 = 0x6,
- PERFCOUNTER_CNTL_SEL_7 = 0x7,
-} PERFCOUNTER_CNTL_SEL;
-typedef enum PERFCOUNTER_CNT0_STATE {
- PERFCOUNTER_CNT0_STATE_RESET = 0x0,
- PERFCOUNTER_CNT0_STATE_START = 0x1,
- PERFCOUNTER_CNT0_STATE_FREEZE = 0x2,
- PERFCOUNTER_CNT0_STATE_HW = 0x3,
-} PERFCOUNTER_CNT0_STATE;
-typedef enum PERFCOUNTER_STATE_SEL0 {
- PERFCOUNTER_STATE_SEL0_GLOBAL = 0x0,
- PERFCOUNTER_STATE_SEL0_LOCAL = 0x1,
-} PERFCOUNTER_STATE_SEL0;
-typedef enum PERFCOUNTER_CNT1_STATE {
- PERFCOUNTER_CNT1_STATE_RESET = 0x0,
- PERFCOUNTER_CNT1_STATE_START = 0x1,
- PERFCOUNTER_CNT1_STATE_FREEZE = 0x2,
- PERFCOUNTER_CNT1_STATE_HW = 0x3,
-} PERFCOUNTER_CNT1_STATE;
-typedef enum PERFCOUNTER_STATE_SEL1 {
- PERFCOUNTER_STATE_SEL1_GLOBAL = 0x0,
- PERFCOUNTER_STATE_SEL1_LOCAL = 0x1,
-} PERFCOUNTER_STATE_SEL1;
-typedef enum PERFCOUNTER_CNT2_STATE {
- PERFCOUNTER_CNT2_STATE_RESET = 0x0,
- PERFCOUNTER_CNT2_STATE_START = 0x1,
- PERFCOUNTER_CNT2_STATE_FREEZE = 0x2,
- PERFCOUNTER_CNT2_STATE_HW = 0x3,
-} PERFCOUNTER_CNT2_STATE;
-typedef enum PERFCOUNTER_STATE_SEL2 {
- PERFCOUNTER_STATE_SEL2_GLOBAL = 0x0,
- PERFCOUNTER_STATE_SEL2_LOCAL = 0x1,
-} PERFCOUNTER_STATE_SEL2;
-typedef enum PERFCOUNTER_CNT3_STATE {
- PERFCOUNTER_CNT3_STATE_RESET = 0x0,
- PERFCOUNTER_CNT3_STATE_START = 0x1,
- PERFCOUNTER_CNT3_STATE_FREEZE = 0x2,
- PERFCOUNTER_CNT3_STATE_HW = 0x3,
-} PERFCOUNTER_CNT3_STATE;
-typedef enum PERFCOUNTER_STATE_SEL3 {
- PERFCOUNTER_STATE_SEL3_GLOBAL = 0x0,
- PERFCOUNTER_STATE_SEL3_LOCAL = 0x1,
-} PERFCOUNTER_STATE_SEL3;
-typedef enum PERFCOUNTER_CNT4_STATE {
- PERFCOUNTER_CNT4_STATE_RESET = 0x0,
- PERFCOUNTER_CNT4_STATE_START = 0x1,
- PERFCOUNTER_CNT4_STATE_FREEZE = 0x2,
- PERFCOUNTER_CNT4_STATE_HW = 0x3,
-} PERFCOUNTER_CNT4_STATE;
-typedef enum PERFCOUNTER_STATE_SEL4 {
- PERFCOUNTER_STATE_SEL4_GLOBAL = 0x0,
- PERFCOUNTER_STATE_SEL4_LOCAL = 0x1,
-} PERFCOUNTER_STATE_SEL4;
-typedef enum PERFCOUNTER_CNT5_STATE {
- PERFCOUNTER_CNT5_STATE_RESET = 0x0,
- PERFCOUNTER_CNT5_STATE_START = 0x1,
- PERFCOUNTER_CNT5_STATE_FREEZE = 0x2,
- PERFCOUNTER_CNT5_STATE_HW = 0x3,
-} PERFCOUNTER_CNT5_STATE;
-typedef enum PERFCOUNTER_STATE_SEL5 {
- PERFCOUNTER_STATE_SEL5_GLOBAL = 0x0,
- PERFCOUNTER_STATE_SEL5_LOCAL = 0x1,
-} PERFCOUNTER_STATE_SEL5;
-typedef enum PERFCOUNTER_CNT6_STATE {
- PERFCOUNTER_CNT6_STATE_RESET = 0x0,
- PERFCOUNTER_CNT6_STATE_START = 0x1,
- PERFCOUNTER_CNT6_STATE_FREEZE = 0x2,
- PERFCOUNTER_CNT6_STATE_HW = 0x3,
-} PERFCOUNTER_CNT6_STATE;
-typedef enum PERFCOUNTER_STATE_SEL6 {
- PERFCOUNTER_STATE_SEL6_GLOBAL = 0x0,
- PERFCOUNTER_STATE_SEL6_LOCAL = 0x1,
-} PERFCOUNTER_STATE_SEL6;
-typedef enum PERFCOUNTER_CNT7_STATE {
- PERFCOUNTER_CNT7_STATE_RESET = 0x0,
- PERFCOUNTER_CNT7_STATE_START = 0x1,
- PERFCOUNTER_CNT7_STATE_FREEZE = 0x2,
- PERFCOUNTER_CNT7_STATE_HW = 0x3,
-} PERFCOUNTER_CNT7_STATE;
-typedef enum PERFCOUNTER_STATE_SEL7 {
- PERFCOUNTER_STATE_SEL7_GLOBAL = 0x0,
- PERFCOUNTER_STATE_SEL7_LOCAL = 0x1,
-} PERFCOUNTER_STATE_SEL7;
-typedef enum PERFMON_STATE {
- PERFMON_STATE_RESET = 0x0,
- PERFMON_STATE_START = 0x1,
- PERFMON_STATE_FREEZE = 0x2,
- PERFMON_STATE_HW = 0x3,
-} PERFMON_STATE;
-typedef enum PERFMON_CNTOFF_AND_OR {
- PERFMON_CNTOFF_OR = 0x0,
- PERFMON_CNTOFF_AND = 0x1,
-} PERFMON_CNTOFF_AND_OR;
-typedef enum PERFMON_CNTOFF_INT_EN {
- PERFMON_CNTOFF_INT_DISABLE = 0x0,
- PERFMON_CNTOFF_INT_ENABLE = 0x1,
-} PERFMON_CNTOFF_INT_EN;
-typedef enum PERFMON_CNTOFF_INT_TYPE {
- PERFMON_CNTOFF_INT_TYPE_LEVEL = 0x0,
- PERFMON_CNTOFF_INT_TYPE_PULSE = 0x1,
-} PERFMON_CNTOFF_INT_TYPE;
-typedef enum ENABLE {
- DISABLE_THE_FEATURE = 0x0,
- ENABLE_THE_FEATURE = 0x1,
-} ENABLE;
-typedef enum ENABLE_CLOCK {
- DISABLE_THE_CLOCK = 0x0,
- ENABLE_THE_CLOCK = 0x1,
-} ENABLE_CLOCK;
-typedef enum FORCE_VBI {
- FORCE_VBI_LOW = 0x0,
- FORCE_VBI_HIGH = 0x1,
-} FORCE_VBI;
-typedef enum OVERRIDE_CGTT_SCLK {
- OVERRIDE_CGTT_SCLK_NOOP = 0x0,
- SET_OVERRIDE_CGTT_SCLK = 0x1,
-} OVERRIDE_CGTT_SCLK;
-typedef enum CLEAR_SMU_INTR {
- SMU_INTR_STATUS_NOOP = 0x0,
- SMU_INTR_STATUS_CLEAR = 0x1,
-} CLEAR_SMU_INTR;
-typedef enum STATIC_SCREEN_SMU_INTR {
- STATIC_SCREEN_SMU_INTR_NOOP = 0x0,
- SET_STATIC_SCREEN_SMU_INTR = 0x1,
-} STATIC_SCREEN_SMU_INTR;
-typedef enum JITTER_REMOVE_DISABLE {
- ENABLE_JITTER_REMOVAL = 0x0,
- DISABLE_JITTER_REMOVAL = 0x1,
-} JITTER_REMOVE_DISABLE;
-typedef enum DISABLE_CLOCK_GATING {
- CLOCK_GATING_ENABLED = 0x0,
- CLOCK_GATING_DISABLED = 0x1,
-} DISABLE_CLOCK_GATING;
-typedef enum DISABLE_CLOCK_GATING_IN_DCO {
- CLOCK_GATING_ENABLED_IN_DCO = 0x0,
- CLOCK_GATING_DISABLED_IN_DCO = 0x1,
-} DISABLE_CLOCK_GATING_IN_DCO;
-typedef enum DCCG_DEEP_COLOR_CNTL {
- DCCG_DEEP_COLOR_DTO_DISABLE = 0x0,
- DCCG_DEEP_COLOR_DTO_5_4_RATIO = 0x1,
- DCCG_DEEP_COLOR_DTO_3_2_RATIO = 0x2,
- DCCG_DEEP_COLOR_DTO_2_1_RATIO = 0x3,
-} DCCG_DEEP_COLOR_CNTL;
-typedef enum REFCLK_CLOCK_EN {
- REFCLK_CLOCK_EN_PCIE_REFCLK = 0x0,
- REFCLK_CLOCK_EN_ALLOW_SRC = 0x1,
-} REFCLK_CLOCK_EN;
-typedef enum REFCLK_SRC_SEL {
- REFCLK_SRC_SEL_XTALIN = 0x0,
- REFCLK_SRC_SEL_DISPPLL = 0x1,
-} REFCLK_SRC_SEL;
-typedef enum DPREFCLK_SRC_SEL {
- DPREFCLK_SRC_SEL_CK = 0x0,
- DPREFCLK_SRC_SEL_P0PLL = 0x1,
- DPREFCLK_SRC_SEL_P1PLL = 0x2,
- DPREFCLK_SRC_SEL_P2PLL = 0x3,
- DPREFCLK_SRC_SEL_P3PLL = 0x4,
-} DPREFCLK_SRC_SEL;
-typedef enum XTAL_REF_SEL {
- XTAL_REF_SEL_1X = 0x0,
- XTAL_REF_SEL_2X = 0x1,
-} XTAL_REF_SEL;
-typedef enum XTAL_REF_CLOCK_SOURCE_SEL {
- XTAL_REF_CLOCK_SOURCE_SEL_XTALIN = 0x0,
- XTAL_REF_CLOCK_SOURCE_SEL_PPLL = 0x1,
-} XTAL_REF_CLOCK_SOURCE_SEL;
-typedef enum MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL {
- MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN = 0x0,
- MICROSECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK = 0x1,
-} MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL;
-typedef enum ALLOW_SR_ON_TRANS_REQ {
- ALLOW_SR_ON_TRANS_REQ_ENABLE = 0x0,
- ALLOW_SR_ON_TRANS_REQ_DISABLE = 0x1,
-} ALLOW_SR_ON_TRANS_REQ;
-typedef enum MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL {
- MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN = 0x0,
- MILLISECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK = 0x1,
-} MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL;
-typedef enum PIPE_PIXEL_RATE_SOURCE {
- PIPE_PIXEL_RATE_SOURCE_P0PLL = 0x0,
- PIPE_PIXEL_RATE_SOURCE_P1PLL = 0x1,
- PIPE_PIXEL_RATE_SOURCE_P2PLL = 0x2,
-} PIPE_PIXEL_RATE_SOURCE;
-typedef enum PIPE_PHYPLL_PIXEL_RATE_SOURCE {
- PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA = 0x0,
- PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB = 0x1,
- PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC = 0x2,
- PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD = 0x3,
- PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE = 0x4,
- PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF = 0x5,
- PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYG = 0x6,
-} PIPE_PHYPLL_PIXEL_RATE_SOURCE;
-typedef enum PIPE_PIXEL_RATE_PLL_SOURCE {
- PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL = 0x0,
- PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL = 0x1,
-} PIPE_PIXEL_RATE_PLL_SOURCE;
-typedef enum DP_DTO_DS_DISABLE {
- DP_DTO_DESPREAD_DISABLE = 0x0,
- DP_DTO_DESPREAD_ENABLE = 0x1,
-} DP_DTO_DS_DISABLE;
-typedef enum CRTC_ADD_PIXEL {
- CRTC_ADD_PIXEL_NOOP = 0x0,
- CRTC_ADD_PIXEL_FORCE = 0x1,
-} CRTC_ADD_PIXEL;
-typedef enum CRTC_DROP_PIXEL {
- CRTC_DROP_PIXEL_NOOP = 0x0,
- CRTC_DROP_PIXEL_FORCE = 0x1,
-} CRTC_DROP_PIXEL;
-typedef enum SYMCLK_FE_FORCE_EN {
- SYMCLK_FE_FORCE_EN_DISABLE = 0x0,
- SYMCLK_FE_FORCE_EN_ENABLE = 0x1,
-} SYMCLK_FE_FORCE_EN;
-typedef enum SYMCLK_FE_FORCE_SRC {
- SYMCLK_FE_FORCE_SRC_UNIPHYA = 0x0,
- SYMCLK_FE_FORCE_SRC_UNIPHYB = 0x1,
- SYMCLK_FE_FORCE_SRC_UNIPHYC = 0x2,
- SYMCLK_FE_FORCE_SRC_UNIPHYD = 0x3,
- SYMCLK_FE_FORCE_SRC_UNIPHYE = 0x4,
- SYMCLK_FE_FORCE_SRC_UNIPHYF = 0x5,
- SYMCLK_FE_FORCE_SRC_UNIPHYG = 0x6,
-} SYMCLK_FE_FORCE_SRC;
-typedef enum DPDBG_CLK_FORCE_EN {
- DPDBG_CLK_FORCE_EN_DISABLE = 0x0,
- DPDBG_CLK_FORCE_EN_ENABLE = 0x1,
-} DPDBG_CLK_FORCE_EN;
-typedef enum DVOACLK_COARSE_SKEW_CNTL {
- DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT = 0x0,
- DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP = 0x1,
- DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS = 0x2,
- DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS = 0x3,
- DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS = 0x4,
- DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS = 0x5,
- DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS = 0x6,
- DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS = 0x7,
- DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS = 0x8,
- DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS = 0x9,
- DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS = 0xa,
- DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS = 0xb,
- DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS = 0xc,
- DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS = 0xd,
- DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS = 0xe,
- DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS = 0xf,
- DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP = 0x10,
- DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS = 0x11,
- DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS = 0x12,
- DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS = 0x13,
- DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS = 0x14,
- DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS = 0x15,
- DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS = 0x16,
- DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS = 0x17,
- DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS = 0x18,
- DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS = 0x19,
- DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS = 0x1a,
- DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS = 0x1b,
- DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS = 0x1c,
- DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS = 0x1d,
- DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS = 0x1e,
-} DVOACLK_COARSE_SKEW_CNTL;
-typedef enum DVOACLK_FINE_SKEW_CNTL {
- DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT = 0x0,
- DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP = 0x1,
- DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS = 0x2,
- DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS = 0x3,
- DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP = 0x4,
- DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS = 0x5,
- DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS = 0x6,
- DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS = 0x7,
-} DVOACLK_FINE_SKEW_CNTL;
-typedef enum DVOACLKD_IN_PHASE {
- DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x0,
- DVOACLKD_IN_PHASE_WITH_PCLK_DVO = 0x1,
-} DVOACLKD_IN_PHASE;
-typedef enum DVOACLKC_IN_PHASE {
- DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x0,
- DVOACLKC_IN_PHASE_WITH_PCLK_DVO = 0x1,
-} DVOACLKC_IN_PHASE;
-typedef enum DVOACLKC_MVP_IN_PHASE {
- DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x0,
- DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO = 0x1,
-} DVOACLKC_MVP_IN_PHASE;
-typedef enum DVOACLKC_MVP_SKEW_PHASE_OVERRIDE {
- DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE = 0x0,
- DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE = 0x1,
-} DVOACLKC_MVP_SKEW_PHASE_OVERRIDE;
-typedef enum MVP_CLK_SRC_SEL {
- MVP_CLK_SRC_SEL_RSRV = 0x0,
- MVP_CLK_SRC_SEL_IO_1 = 0x1,
- MVP_CLK_SRC_SEL_IO_2 = 0x2,
- MVP_CLK_SRC_SEL_REFCLK = 0x3,
-} MVP_CLK_SRC_SEL;
-typedef enum DCCG_AUDIO_DTO0_SOURCE_SEL {
- DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC0 = 0x0,
- DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC1 = 0x1,
- DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC2 = 0x2,
- DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC3 = 0x3,
- DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC4 = 0x4,
- DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC5 = 0x5,
- DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED = 0x6,
-} DCCG_AUDIO_DTO0_SOURCE_SEL;
-typedef enum DCCG_AUDIO_DTO_SEL {
- DCCG_AUDIO_DTO_SEL_AUDIO_DTO0 = 0x0,
- DCCG_AUDIO_DTO_SEL_AUDIO_DTO1 = 0x1,
- DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO = 0x2,
-} DCCG_AUDIO_DTO_SEL;
-typedef enum DCCG_AUDIO_DTO2_SOURCE_SEL {
- DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0 = 0x0,
- DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1 = 0x1,
-} DCCG_AUDIO_DTO2_SOURCE_SEL;
-typedef enum DCCG_AUDIO_DTO_USE_512FBR_DTO {
- DCCG_AUDIO_DTO_USE_128FBR_FOR_DP = 0x0,
- DCCG_AUDIO_DTO_USE_512FBR_FOR_DP = 0x1,
-} DCCG_AUDIO_DTO_USE_512FBR_DTO;
-typedef enum DCCG_DBG_EN {
- DCCG_DBG_EN_DISABLE = 0x0,
- DCCG_DBG_EN_ENABLE = 0x1,
-} DCCG_DBG_EN;
-typedef enum DCCG_DBG_BLOCK_SEL {
- DCCG_DBG_BLOCK_SEL_DCCG = 0x0,
- DCCG_DBG_BLOCK_SEL_PMON = 0x1,
- DCCG_DBG_BLOCK_SEL_PMON2 = 0x2,
-} DCCG_DBG_BLOCK_SEL;
-typedef enum DCCG_DBG_CLOCK_SEL {
- DCCG_DBG_CLOCK_SEL_DISPCLK = 0x0,
- DCCG_DBG_CLOCK_SEL_SCLK = 0x1,
- DCCG_DBG_CLOCK_SEL_MVPCLK = 0x2,
- DCCG_DBG_CLOCK_SEL_DVOCLK = 0x3,
- DCCG_DBG_CLOCK_SEL_DACCLK = 0x4,
- DCCG_DBG_CLOCK_SEL_REFCLK = 0x5,
- DCCG_DBG_CLOCK_SEL_SYMCLKA = 0x6,
- DCCG_DBG_CLOCK_SEL_SYMCLKB = 0x7,
- DCCG_DBG_CLOCK_SEL_SYMCLKC = 0x8,
- DCCG_DBG_CLOCK_SEL_SYMCLKD = 0x9,
- DCCG_DBG_CLOCK_SEL_SYMCLKE = 0xa,
- DCCG_DBG_CLOCK_SEL_SYMCLKG = 0xb,
- DCCG_DBG_CLOCK_SEL_SYMCLKF = 0xc,
- DCCG_DBG_CLOCK_SEL_RSRV = 0xd,
- DCCG_DBG_CLOCK_SEL_AOMCLK0 = 0xe,
- DCCG_DBG_CLOCK_SEL_AOMCLK1 = 0xf,
- DCCG_DBG_CLOCK_SEL_AOMCLK2 = 0x10,
- DCCG_DBG_CLOCK_SEL_DPREFCLK = 0x11,
- DCCG_DBG_CLOCK_SEL_UNB_DB_CLK = 0x12,
- DCCG_DBG_CLOCK_SEL_DSICLK = 0x13,
- DCCG_DBG_CLOCK_SEL_BYTECLK = 0x14,
- DCCG_DBG_CLOCK_SEL_ESCCLK = 0x15,
- DCCG_DBG_CLOCK_SEL_SYMCLKLPA = 0x16,
- DCCG_DBG_CLOCK_SEL_SYMCLKLPB = 0x17,
-} DCCG_DBG_CLOCK_SEL;
-typedef enum DCCG_DBG_OUT_BLOCK_SEL {
- DCCG_DBG_OUT_BLOCK_SEL_DCCG = 0x0,
- DCCG_DBG_OUT_BLOCK_SEL_DCO = 0x1,
- DCCG_DBG_OUT_BLOCK_SEL_DCIO = 0x2,
- DCCG_DBG_OUT_BLOCK_SEL_DSI = 0x3,
-} DCCG_DBG_OUT_BLOCK_SEL;
-typedef enum DISPCLK_FREQ_RAMP_DONE {
- DISPCLK_FREQ_RAMP_IN_PROGRESS = 0x0,
- DISPCLK_FREQ_RAMP_COMPLETED = 0x1,
-} DISPCLK_FREQ_RAMP_DONE;
-typedef enum DCCG_FIFO_ERRDET_RESET {
- DCCG_FIFO_ERRDET_RESET_NOOP = 0x0,
- DCCG_FIFO_ERRDET_RESET_FORCE = 0x1,
-} DCCG_FIFO_ERRDET_RESET;
-typedef enum DCCG_FIFO_ERRDET_STATE {
- DCCG_FIFO_ERRDET_STATE_DETECTION = 0x0,
- DCCG_FIFO_ERRDET_STATE_CALIBRATION = 0x1,
-} DCCG_FIFO_ERRDET_STATE;
-typedef enum DCCG_FIFO_ERRDET_OVR_EN {
- DCCG_FIFO_ERRDET_OVR_DISABLE = 0x0,
- DCCG_FIFO_ERRDET_OVR_ENABLE = 0x1,
-} DCCG_FIFO_ERRDET_OVR_EN;
-typedef enum DISPCLK_CHG_FWD_CORR_DISABLE {
- DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING = 0x0,
- DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING = 0x1,
-} DISPCLK_CHG_FWD_CORR_DISABLE;
-typedef enum DC_MEM_GLOBAL_PWR_REQ_DIS {
- DC_MEM_GLOBAL_PWR_REQ_ENABLE = 0x0,
- DC_MEM_GLOBAL_PWR_REQ_DISABLE = 0x1,
-} DC_MEM_GLOBAL_PWR_REQ_DIS;
-typedef enum DCCG_PERF_RUN {
- DCCG_PERF_RUN_NOOP = 0x0,
- DCCG_PERF_RUN_START = 0x1,
-} DCCG_PERF_RUN;
-typedef enum DCCG_PERF_MODE_VSYNC {
- DCCG_PERF_MODE_VSYNC_NOOP = 0x0,
- DCCG_PERF_MODE_VSYNC_START = 0x1,
-} DCCG_PERF_MODE_VSYNC;
-typedef enum DCCG_PERF_MODE_HSYNC {
- DCCG_PERF_MODE_HSYNC_NOOP = 0x0,
- DCCG_PERF_MODE_HSYNC_START = 0x1,
-} DCCG_PERF_MODE_HSYNC;
-typedef enum DCCG_PERF_CRTC_SELECT {
- DCCG_PERF_SEL_CRTC0 = 0x0,
- DCCG_PERF_SEL_CRTC1 = 0x1,
- DCCG_PERF_SEL_CRTC2 = 0x2,
- DCCG_PERF_SEL_CRTC3 = 0x3,
- DCCG_PERF_SEL_CRTC4 = 0x4,
- DCCG_PERF_SEL_CRTC5 = 0x5,
-} DCCG_PERF_CRTC_SELECT;
-typedef enum CLOCK_BRANCH_SOFT_RESET {
- CLOCK_BRANCH_SOFT_RESET_NOOP = 0x0,
- CLOCK_BRANCH_SOFT_RESET_FORCE = 0x1,
-} CLOCK_BRANCH_SOFT_RESET;
-typedef enum PLL_CFG_IF_SOFT_RESET {
- PLL_CFG_IF_SOFT_RESET_NOOP = 0x0,
- PLL_CFG_IF_SOFT_RESET_FORCE = 0x1,
-} PLL_CFG_IF_SOFT_RESET;
-typedef enum DVO_ENABLE_RST {
- DVO_ENABLE_RST_DISABLE = 0x0,
- DVO_ENABLE_RST_ENABLE = 0x1,
-} DVO_ENABLE_RST;
-typedef enum LptNumBanks {
- LPT_NUM_BANKS_2BANK = 0x0,
- LPT_NUM_BANKS_4BANK = 0x1,
- LPT_NUM_BANKS_8BANK = 0x2,
- LPT_NUM_BANKS_16BANK = 0x3,
- LPT_NUM_BANKS_32BANK = 0x4,
-} LptNumBanks;
-typedef enum DCIO_DC_GENERICA_SEL {
- DCIO_GENERICA_SEL_DACA_STEREOSYNC = 0x0,
- DCIO_GENERICA_SEL_STEREOSYNC = 0x1,
- DCIO_GENERICA_SEL_DACA_PIXCLK = 0x2,
- DCIO_GENERICA_SEL_DACB_PIXCLK = 0x3,
- DCIO_GENERICA_SEL_DVOA_CTL3 = 0x4,
- DCIO_GENERICA_SEL_P1_PLLCLK = 0x5,
- DCIO_GENERICA_SEL_P2_PLLCLK = 0x6,
- DCIO_GENERICA_SEL_DVOA_STEREOSYNC = 0x7,
- DCIO_GENERICA_SEL_DACA_FIELD_NUMBER = 0x8,
- DCIO_GENERICA_SEL_DACB_FIELD_NUMBER = 0x9,
- DCIO_GENERICA_SEL_GENERICA_DCCG = 0xa,
- DCIO_GENERICA_SEL_SYNCEN = 0xb,
- DCIO_GENERICA_SEL_GENERICA_SCG = 0xc,
- DCIO_GENERICA_SEL_RESERVED_VALUE13 = 0xd,
- DCIO_GENERICA_SEL_RESERVED_VALUE14 = 0xe,
- DCIO_GENERICA_SEL_RESERVED_VALUE15 = 0xf,
- DCIO_GENERICA_SEL_GENERICA_DPRX = 0x10,
- DCIO_GENERICA_SEL_GENERICB_DPRX = 0x11,
-} DCIO_DC_GENERICA_SEL;
-typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL {
- DCIO_UNIPHYA_TEST_REFDIV_CLK = 0x0,
- DCIO_UNIPHYB_TEST_REFDIV_CLK = 0x1,
- DCIO_UNIPHYC_TEST_REFDIV_CLK = 0x2,
- DCIO_UNIPHYD_TEST_REFDIV_CLK = 0x3,
- DCIO_UNIPHYE_TEST_REFDIV_CLK = 0x4,
- DCIO_UNIPHYF_TEST_REFDIV_CLK = 0x5,
- DCIO_UNIPHYG_TEST_REFDIV_CLK = 0x6,
- DCIO_UNIPHYLPA_TEST_REFDIV_CLK = 0x7,
- DCIO_UNIPHYLPB_TEST_REFDIV_CLK = 0x8,
-} DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL;
-typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL {
- DCIO_UNIPHYA_FBDIV_CLK = 0x0,
- DCIO_UNIPHYB_FBDIV_CLK = 0x1,
- DCIO_UNIPHYC_FBDIV_CLK = 0x2,
- DCIO_UNIPHYD_FBDIV_CLK = 0x3,
- DCIO_UNIPHYE_FBDIV_CLK = 0x4,
- DCIO_UNIPHYF_FBDIV_CLK = 0x5,
- DCIO_UNIPHYG_FBDIV_CLK = 0x6,
- DCIO_UNIPHYLPA_FBDIV_CLK = 0x7,
- DCIO_UNIPHYLPB_FBDIV_CLK = 0x8,
-} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL;
-typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL {
- DCIO_UNIPHYA_FBDIV_SSC_CLK = 0x0,
- DCIO_UNIPHYB_FBDIV_SSC_CLK = 0x1,
- DCIO_UNIPHYC_FBDIV_SSC_CLK = 0x2,
- DCIO_UNIPHYD_FBDIV_SSC_CLK = 0x3,
- DCIO_UNIPHYE_FBDIV_SSC_CLK = 0x4,
- DCIO_UNIPHYF_FBDIV_SSC_CLK = 0x5,
- DCIO_UNIPHYG_FBDIV_SSC_CLK = 0x6,
- DCIO_UNIPHYLPA_FBDIV_SSC_CLK = 0x7,
- DCIO_UNIPHYLPB_FBDIV_SSC_CLK = 0x8,
-} DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL;
-typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL {
- DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0x0,
- DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 0x1,
- DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 0x2,
- DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 0x3,
- DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 0x4,
- DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 0x5,
- DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2 = 0x6,
- DCIO_UNIPHYLPA_TEST_FBDIV_CLK_DIV2 = 0x7,
- DCIO_UNIPHYLPB_TEST_FBDIV_CLK_DIV2 = 0x8,
-} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL;
-typedef enum DCIO_DC_GENERICB_SEL {
- DCIO_GENERICB_SEL_DACA_STEREOSYNC = 0x0,
- DCIO_GENERICB_SEL_STEREOSYNC = 0x1,
- DCIO_GENERICB_SEL_DACA_PIXCLK = 0x2,
- DCIO_GENERICB_SEL_DACB_PIXCLK = 0x3,
- DCIO_GENERICB_SEL_DVOA_CTL3 = 0x4,
- DCIO_GENERICB_SEL_P1_PLLCLK = 0x5,
- DCIO_GENERICB_SEL_P2_PLLCLK = 0x6,
- DCIO_GENERICB_SEL_DVOA_STEREOSYNC = 0x7,
- DCIO_GENERICB_SEL_DACA_FIELD_NUMBER = 0x8,
- DCIO_GENERICB_SEL_DACB_FIELD_NUMBER = 0x9,
- DCIO_GENERICB_SEL_GENERICB_DCCG = 0xa,
- DCIO_GENERICB_SEL_SYNCEN = 0xb,
- DCIO_GENERICB_SEL_GENERICA_SCG = 0xc,
- DCIO_GENERICB_SEL_RESERVED_VALUE13 = 0xd,
- DCIO_GENERICB_SEL_RESERVED_VALUE14 = 0xe,
- DCIO_GENERICB_SEL_RESERVED_VALUE15 = 0xf,
-} DCIO_DC_GENERICB_SEL;
-typedef enum DCIO_DC_PAD_EXTERN_SIG_SEL {
- DCIO_DC_PAD_EXTERN_SIG_SEL_MVP = 0x0,
- DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA = 0x1,
- DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK = 0x2,
- DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC = 0x3,
- DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA = 0x4,
- DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB = 0x5,
- DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC = 0x6,
- DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1 = 0x7,
- DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2 = 0x8,
- DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK = 0x9,
- DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA = 0xa,
- DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK = 0xb,
- DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA = 0xc,
- DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1 = 0xd,
- DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0 = 0xe,
- DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL = 0xf,
-} DCIO_DC_PAD_EXTERN_SIG_SEL;
-typedef enum DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS {
- DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA = 0x0,
- DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE = 0x1,
- DCIO_MVP_PIXEL_SRC_STATUS_CRTC = 0x2,
- DCIO_MVP_PIXEL_SRC_STATUS_LB = 0x3,
-} DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS;
-typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL {
- DCIO_HSYNCA_OUTPUT_SEL_DISABLE = 0x0,
- DCIO_HSYNCA_OUTPUT_SEL_PPLL1 = 0x1,
- DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 0x2,
- DCIO_HSYNCA_OUTPUT_SEL_RESERVED = 0x3,
-} DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL;
-typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL {
- DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0x0,
- DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 0x1,
- DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 0x2,
- DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 0x3,
-} DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL;
-typedef enum DCIO_DC_GPIO_VIP_DEBUG {
- DCIO_DC_GPIO_VIP_DEBUG_NORMAL = 0x0,
- DCIO_DC_GPIO_VIP_DEBUG_CG_BIG = 0x1,
-} DCIO_DC_GPIO_VIP_DEBUG;
-typedef enum DCIO_DC_GPIO_MACRO_DEBUG {
- DCIO_DC_GPIO_MACRO_DEBUG_NORMAL = 0x0,
- DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF = 0x1,
- DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2 = 0x2,
- DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3 = 0x3,
-} DCIO_DC_GPIO_MACRO_DEBUG;
-typedef enum DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL {
- DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL = 0x0,
- DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP = 0x1,
-} DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL;
-typedef enum DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN {
- DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS = 0x0,
- DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE = 0x1,
-} DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN;
-typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE {
- DCIO_DPRX_LOOPBACK_ENABLE_NORMAL = 0x0,
- DCIO_DPRX_LOOPBACK_ENABLE_LOOP = 0x1,
-} DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE;
-typedef enum DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION {
- DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0x0,
- DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 0x1,
- DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS= 0x2,
- DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS= 0x3,
- DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS= 0x4,
- DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS= 0x5,
- DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS= 0x6,
- DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS= 0x7,
-} DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION;
-typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT {
- DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0x0,
- DCIO_UNIPHY_CHANNEL_INVERTED = 0x1,
-} DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT;
-typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK {
- DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0x0,
- DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 0x1,
- DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 0x2,
- DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED= 0x3,
-} DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK;
-typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE {
- DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0x0,
- DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 0x1,
- DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 0x2,
- DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 0x3,
-} DCIO_UNIPHY_CHANNEL_XBAR_SOURCE;
-typedef enum DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN {
- DCIO_VIP_MUX_EN_DVO = 0x0,
- DCIO_VIP_MUX_EN_VIP = 0x1,
-} DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN;
-typedef enum DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN {
- DCIO_VIP_ALTER_MAPPING_EN_DEFAULT = 0x0,
- DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE = 0x1,
-} DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN;
-typedef enum DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN {
- DCIO_DVO_ALTER_MAPPING_EN_DEFAULT = 0x0,
- DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE = 0x1,
-} DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN;
-typedef enum DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN {
- DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE= 0x0,
- DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE= 0x1,
-} DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN;
-typedef enum DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE {
- DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF = 0x0,
- DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON = 0x1,
-} DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE;
-typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL {
- DCIO_LVTMA_SYNCEN_POL_NON_INVERT = 0x0,
- DCIO_LVTMA_SYNCEN_POL_INVERT = 0x1,
-} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL;
-typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON {
- DCIO_LVTMA_DIGON_OFF = 0x0,
- DCIO_LVTMA_DIGON_ON = 0x1,
-} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON;
-typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL {
- DCIO_LVTMA_DIGON_POL_NON_INVERT = 0x0,
- DCIO_LVTMA_DIGON_POL_INVERT = 0x1,
-} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL;
-typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON {
- DCIO_LVTMA_BLON_OFF = 0x0,
- DCIO_LVTMA_BLON_ON = 0x1,
-} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON;
-typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL {
- DCIO_LVTMA_BLON_POL_NON_INVERT = 0x0,
- DCIO_LVTMA_BLON_POL_INVERT = 0x1,
-} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL;
-typedef enum DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN {
- DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON = 0x0,
- DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE = 0x1,
-} DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN;
-typedef enum DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN {
- DCIO_BL_PWM_FRACTIONAL_DISABLE = 0x0,
- DCIO_BL_PWM_FRACTIONAL_ENABLE = 0x1,
-} DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN;
-typedef enum DCIO_BL_PWM_CNTL_BL_PWM_EN {
- DCIO_BL_PWM_DISABLE = 0x0,
- DCIO_BL_PWM_ENABLE = 0x1,
-} DCIO_BL_PWM_CNTL_BL_PWM_EN;
-typedef enum DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT {
- DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0x0,
- DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 0x1,
- DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 0x2,
- DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 0x3,
-} DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT;
-typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE {
- DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0x0,
- DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 0x1,
-} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE;
-typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN {
- DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL = 0x0,
- DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM = 0x1,
-} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN;
-typedef enum DCIO_BL_PWM_GRP1_REG_LOCK {
- DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE = 0x0,
- DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE = 0x1,
-} DCIO_BL_PWM_GRP1_REG_LOCK;
-typedef enum DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START {
- DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0x0,
- DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 0x1,
-} DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START;
-typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL {
- DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1= 0x0,
- DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2= 0x1,
- DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3= 0x2,
- DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4= 0x3,
- DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5= 0x4,
- DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6= 0x5,
-} DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL;
-typedef enum DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN {
- DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0x0,
- DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM= 0x1,
-} DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN;
-typedef enum DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN {
- DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0x0,
- DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 0x1,
-} DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN;
-typedef enum DCIO_GSL_SEL {
- DCIO_GSL_SEL_GROUP_0 = 0x0,
- DCIO_GSL_SEL_GROUP_1 = 0x1,
- DCIO_GSL_SEL_GROUP_2 = 0x2,
-} DCIO_GSL_SEL;
-typedef enum DCIO_GENLK_CLK_GSL_MASK {
- DCIO_GENLK_CLK_GSL_MASK_NO = 0x0,
- DCIO_GENLK_CLK_GSL_MASK_TIMING = 0x1,
- DCIO_GENLK_CLK_GSL_MASK_STEREO = 0x2,
-} DCIO_GENLK_CLK_GSL_MASK;
-typedef enum DCIO_GENLK_VSYNC_GSL_MASK {
- DCIO_GENLK_VSYNC_GSL_MASK_NO = 0x0,
- DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 0x1,
- DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 0x2,
-} DCIO_GENLK_VSYNC_GSL_MASK;
-typedef enum DCIO_SWAPLOCK_A_GSL_MASK {
- DCIO_SWAPLOCK_A_GSL_MASK_NO = 0x0,
- DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 0x1,
- DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 0x2,
-} DCIO_SWAPLOCK_A_GSL_MASK;
-typedef enum DCIO_SWAPLOCK_B_GSL_MASK {
- DCIO_SWAPLOCK_B_GSL_MASK_NO = 0x0,
- DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 0x1,
- DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 0x2,
-} DCIO_SWAPLOCK_B_GSL_MASK;
-typedef enum DCIO_GSL_VSYNC_SEL {
- DCIO_GSL_VSYNC_SEL_PIPE0 = 0x0,
- DCIO_GSL_VSYNC_SEL_PIPE1 = 0x1,
- DCIO_GSL_VSYNC_SEL_PIPE2 = 0x2,
- DCIO_GSL_VSYNC_SEL_PIPE3 = 0x3,
- DCIO_GSL_VSYNC_SEL_PIPE4 = 0x4,
- DCIO_GSL_VSYNC_SEL_PIPE5 = 0x5,
-} DCIO_GSL_VSYNC_SEL;
-typedef enum DCIO_GSL0_TIMING_SYNC_SEL {
- DCIO_GSL0_TIMING_SYNC_SEL_PIPE = 0x0,
- DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1,
- DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK = 0x2,
- DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A = 0x3,
- DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B = 0x4,
-} DCIO_GSL0_TIMING_SYNC_SEL;
-typedef enum DCIO_GSL0_GLOBAL_UNLOCK_SEL {
- DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION = 0x0,
- DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x1,
- DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2,
- DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x3,
- DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x4,
-} DCIO_GSL0_GLOBAL_UNLOCK_SEL;
-typedef enum DCIO_GSL1_TIMING_SYNC_SEL {
- DCIO_GSL1_TIMING_SYNC_SEL_PIPE = 0x0,
- DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1,
- DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK = 0x2,
- DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A = 0x3,
- DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B = 0x4,
-} DCIO_GSL1_TIMING_SYNC_SEL;
-typedef enum DCIO_GSL1_GLOBAL_UNLOCK_SEL {
- DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION = 0x0,
- DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x1,
- DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2,
- DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x3,
- DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x4,
-} DCIO_GSL1_GLOBAL_UNLOCK_SEL;
-typedef enum DCIO_GSL2_TIMING_SYNC_SEL {
- DCIO_GSL2_TIMING_SYNC_SEL_PIPE = 0x0,
- DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1,
- DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK = 0x2,
- DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A = 0x3,
- DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B = 0x4,
-} DCIO_GSL2_TIMING_SYNC_SEL;
-typedef enum DCIO_GSL2_GLOBAL_UNLOCK_SEL {
- DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION = 0x0,
- DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x1,
- DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2,
- DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x3,
- DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x4,
-} DCIO_GSL2_GLOBAL_UNLOCK_SEL;
-typedef enum DCIO_DC_GPU_TIMER_START_POSITION {
- DCIO_GPU_TIMER_START_0_END_27 = 0x0,
- DCIO_GPU_TIMER_START_1_END_28 = 0x1,
- DCIO_GPU_TIMER_START_2_END_29 = 0x2,
- DCIO_GPU_TIMER_START_3_END_30 = 0x3,
- DCIO_GPU_TIMER_START_4_END_31 = 0x4,
- DCIO_GPU_TIMER_START_6_END_33 = 0x5,
- DCIO_GPU_TIMER_START_8_END_35 = 0x6,
- DCIO_GPU_TIMER_START_10_END_37 = 0x7,
-} DCIO_DC_GPU_TIMER_START_POSITION;
-typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL {
- DCIO_TEST_CLK_SEL_DISPCLK = 0x0,
- DCIO_TEST_CLK_SEL_GATED_DISPCLK = 0x1,
- DCIO_TEST_CLK_SEL_SCLK = 0x2,
-} DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL;
-typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS {
- DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0x0,
- DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 0x1,
-} DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS;
-typedef enum DCIO_DCO_DCFE_EXT_VSYNC_MUX {
- DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0x0,
- DCIO_EXT_VSYNC_MUX_CRTC0 = 0x1,
- DCIO_EXT_VSYNC_MUX_CRTC1 = 0x2,
- DCIO_EXT_VSYNC_MUX_CRTC2 = 0x3,
- DCIO_EXT_VSYNC_MUX_CRTC3 = 0x4,
- DCIO_EXT_VSYNC_MUX_CRTC4 = 0x5,
- DCIO_EXT_VSYNC_MUX_CRTC5 = 0x6,
- DCIO_EXT_VSYNC_MUX_GENERICB = 0x7,
-} DCIO_DCO_DCFE_EXT_VSYNC_MUX;
-typedef enum DCIO_DCO_EXT_VSYNC_MASK {
- DCIO_EXT_VSYNC_MASK_NONE = 0x0,
- DCIO_EXT_VSYNC_MASK_PIPE0 = 0x1,
- DCIO_EXT_VSYNC_MASK_PIPE1 = 0x2,
- DCIO_EXT_VSYNC_MASK_PIPE2 = 0x3,
- DCIO_EXT_VSYNC_MASK_PIPE3 = 0x4,
- DCIO_EXT_VSYNC_MASK_PIPE4 = 0x5,
- DCIO_EXT_VSYNC_MASK_PIPE5 = 0x6,
- DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 0x7,
-} DCIO_DCO_EXT_VSYNC_MASK;
-typedef enum DCIO_DBG_OUT_PIN_SEL {
- DCIO_DBG_OUT_PIN_SEL_LOW_12BIT = 0x0,
- DCIO_DBG_OUT_PIN_SEL_HIGH_12BIT = 0x1,
-} DCIO_DBG_OUT_PIN_SEL;
-typedef enum DCIO_DBG_OUT_12BIT_SEL {
- DCIO_DBG_OUT_12BIT_SEL_LOW_12BIT = 0x0,
- DCIO_DBG_OUT_12BIT_SEL_MID_12BIT = 0x1,
- DCIO_DBG_OUT_12BIT_SEL_HIGH_12BIT = 0x2,
- DCIO_DBG_OUT_12BIT_SEL_OVERRIDE = 0x3,
-} DCIO_DBG_OUT_12BIT_SEL;
-typedef enum DCIO_DSYNC_SOFT_RESET {
- DCIO_DSYNC_SOFT_RESET_DEASSERT = 0x0,
- DCIO_DSYNC_SOFT_RESET_ASSERT = 0x1,
-} DCIO_DSYNC_SOFT_RESET;
-typedef enum DCIO_DACA_SOFT_RESET {
- DCIO_DACA_SOFT_RESET_DEASSERT = 0x0,
- DCIO_DACA_SOFT_RESET_ASSERT = 0x1,
-} DCIO_DACA_SOFT_RESET;
-typedef enum DCIO_DCRXPHY_SOFT_RESET {
- DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0x0,
- DCIO_DCRXPHY_SOFT_RESET_ASSERT = 0x1,
-} DCIO_DCRXPHY_SOFT_RESET;
-typedef enum DCIO_DPHY_LANE_SEL {
- DCIO_DPHY_LANE_SEL_LANE0 = 0x0,
- DCIO_DPHY_LANE_SEL_LANE1 = 0x1,
- DCIO_DPHY_LANE_SEL_LANE2 = 0x2,
- DCIO_DPHY_LANE_SEL_LANE3 = 0x3,
-} DCIO_DPHY_LANE_SEL;
-typedef enum DCIO_DPCS_INTERRUPT_TYPE {
- DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED = 0x0,
- DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED = 0x1,
-} DCIO_DPCS_INTERRUPT_TYPE;
-typedef enum DCIO_DPCS_INTERRUPT_MASK {
- DCIO_DPCS_INTERRUPT_DISABLE = 0x0,
- DCIO_DPCS_INTERRUPT_ENABLE = 0x1,
-} DCIO_DPCS_INTERRUPT_MASK;
-typedef enum DCIO_DC_GPU_TIMER_READ_SELECT {
- DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0x0,
- DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 0x1,
- DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE = 0x2,
- DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE = 0x3,
- DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE = 0x4,
- DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE = 0x5,
- DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE = 0x6,
- DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE = 0x7,
- DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE = 0x8,
- DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE = 0x9,
- DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE = 0xa,
- DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE = 0xb,
- DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 0xc,
- DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 0xd,
- DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP = 0xe,
- DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP = 0xf,
- DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP = 0x10,
- DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP = 0x11,
- DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_P_FLIP = 0x12,
- DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_P_FLIP = 0x13,
- DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_P_FLIP = 0x14,
- DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_P_FLIP = 0x15,
- DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_P_FLIP = 0x16,
- DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_P_FLIP = 0x17,
- DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 0x18,
- DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 0x19,
- DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM = 0x1a,
- DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM = 0x1b,
- DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM = 0x1c,
- DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM = 0x1d,
- DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM = 0x1e,
- DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM = 0x1f,
- DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM = 0x20,
- DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM = 0x21,
- DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM = 0x22,
- DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM = 0x23,
-} DCIO_DC_GPU_TIMER_READ_SELECT;
-typedef enum DCIO_IMPCAL_STEP_DELAY {
- DCIO_IMPCAL_STEP_DELAY_1us = 0x0,
- DCIO_IMPCAL_STEP_DELAY_2us = 0x1,
- DCIO_IMPCAL_STEP_DELAY_3us = 0x2,
- DCIO_IMPCAL_STEP_DELAY_4us = 0x3,
- DCIO_IMPCAL_STEP_DELAY_5us = 0x4,
- DCIO_IMPCAL_STEP_DELAY_6us = 0x5,
- DCIO_IMPCAL_STEP_DELAY_7us = 0x6,
- DCIO_IMPCAL_STEP_DELAY_8us = 0x7,
- DCIO_IMPCAL_STEP_DELAY_9us = 0x8,
- DCIO_IMPCAL_STEP_DELAY_10us = 0x9,
- DCIO_IMPCAL_STEP_DELAY_11us = 0xa,
- DCIO_IMPCAL_STEP_DELAY_12us = 0xb,
- DCIO_IMPCAL_STEP_DELAY_13us = 0xc,
- DCIO_IMPCAL_STEP_DELAY_14us = 0xd,
- DCIO_IMPCAL_STEP_DELAY_15us = 0xe,
- DCIO_IMPCAL_STEP_DELAY_16us = 0xf,
-} DCIO_IMPCAL_STEP_DELAY;
-typedef enum DCIO_UNIPHY_IMPCAL_SEL {
- DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0x0,
- DCIO_UNIPHY_IMPCAL_SEL_BINARY = 0x1,
-} DCIO_UNIPHY_IMPCAL_SEL;
-typedef enum DCIO_DBG_CLOCK_SEL {
- DCIO_DBG_CLOCK_SEL_DISPCLK = 0x0,
- DCIO_DBG_CLOCK_SEL_SYMCLKA = 0x1,
- DCIO_DBG_CLOCK_SEL_SYMCLKB = 0x2,
- DCIO_DBG_CLOCK_SEL_SYMCLKC = 0x3,
- DCIO_DBG_CLOCK_SEL_SYMCLKD = 0x4,
- DCIO_DBG_CLOCK_SEL_SYMCLKE = 0x5,
- DCIO_DBG_CLOCK_SEL_SYMCLKF = 0x6,
- DCIO_DBG_CLOCK_SEL_REFCLK = 0xb,
-} DCIO_DBG_CLOCK_SEL;
-typedef enum DCIOCHIP_HPD_SEL {
- DCIOCHIP_HPD_SEL_ASYNC = 0x0,
- DCIOCHIP_HPD_SEL_CLOCKED = 0x1,
-} DCIOCHIP_HPD_SEL;
-typedef enum DCIOCHIP_PAD_MODE {
- DCIOCHIP_PAD_MODE_DDC = 0x0,
- DCIOCHIP_PAD_MODE_DP = 0x1,
-} DCIOCHIP_PAD_MODE;
-typedef enum DCIOCHIP_AUXSLAVE_PAD_MODE {
- DCIOCHIP_AUXSLAVE_PAD_MODE_I2C = 0x0,
- DCIOCHIP_AUXSLAVE_PAD_MODE_AUX = 0x1,
-} DCIOCHIP_AUXSLAVE_PAD_MODE;
-typedef enum DCIOCHIP_INVERT {
- DCIOCHIP_POL_NON_INVERT = 0x0,
- DCIOCHIP_POL_INVERT = 0x1,
-} DCIOCHIP_INVERT;
-typedef enum DCIOCHIP_PD_EN {
- DCIOCHIP_PD_EN_NOTALLOW = 0x0,
- DCIOCHIP_PD_EN_ALLOW = 0x1,
-} DCIOCHIP_PD_EN;
-typedef enum DCIOCHIP_GPIO_MASK_EN {
- DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0x0,
- DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 0x1,
-} DCIOCHIP_GPIO_MASK_EN;
-typedef enum DCIOCHIP_MASK {
- DCIOCHIP_MASK_DISABLE = 0x0,
- DCIOCHIP_MASK_ENABLE = 0x1,
-} DCIOCHIP_MASK;
-typedef enum DCIOCHIP_GPIO_I2C_MASK {
- DCIOCHIP_GPIO_I2C_MASK_DISABLE = 0x0,
- DCIOCHIP_GPIO_I2C_MASK_ENABLE = 0x1,
-} DCIOCHIP_GPIO_I2C_MASK;
-typedef enum DCIOCHIP_GPIO_I2C_DRIVE {
- DCIOCHIP_GPIO_I2C_DRIVE_LOW = 0x0,
- DCIOCHIP_GPIO_I2C_DRIVE_HIGH = 0x1,
-} DCIOCHIP_GPIO_I2C_DRIVE;
-typedef enum DCIOCHIP_GPIO_I2C_EN {
- DCIOCHIP_GPIO_I2C_DISABLE = 0x0,
- DCIOCHIP_GPIO_I2C_ENABLE = 0x1,
-} DCIOCHIP_GPIO_I2C_EN;
-typedef enum DCIOCHIP_MASK_4BIT {
- DCIOCHIP_MASK_4BIT_DISABLE = 0x0,
- DCIOCHIP_MASK_4BIT_ENABLE = 0xf,
-} DCIOCHIP_MASK_4BIT;
-typedef enum DCIOCHIP_ENABLE_4BIT {
- DCIOCHIP_4BIT_DISABLE = 0x0,
- DCIOCHIP_4BIT_ENABLE = 0xf,
-} DCIOCHIP_ENABLE_4BIT;
-typedef enum DCIOCHIP_MASK_5BIT {
- DCIOCHIP_MASIK_5BIT_DISABLE = 0x0,
- DCIOCHIP_MASIK_5BIT_ENABLE = 0x1f,
-} DCIOCHIP_MASK_5BIT;
-typedef enum DCIOCHIP_ENABLE_5BIT {
- DCIOCHIP_5BIT_DISABLE = 0x0,
- DCIOCHIP_5BIT_ENABLE = 0x1f,
-} DCIOCHIP_ENABLE_5BIT;
-typedef enum DCIOCHIP_MASK_2BIT {
- DCIOCHIP_MASK_2BIT_DISABLE = 0x0,
- DCIOCHIP_MASK_2BIT_ENABLE = 0x3,
-} DCIOCHIP_MASK_2BIT;
-typedef enum DCIOCHIP_ENABLE_2BIT {
- DCIOCHIP_2BIT_DISABLE = 0x0,
- DCIOCHIP_2BIT_ENABLE = 0x3,
-} DCIOCHIP_ENABLE_2BIT;
-typedef enum DCIOCHIP_REF_27_SRC_SEL {
- DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0x0,
- DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 0x1,
- DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 0x2,
- DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 0x3,
-} DCIOCHIP_REF_27_SRC_SEL;
-typedef enum DCIOCHIP_DVO_VREFPON {
- DCIOCHIP_DVO_VREFPON_DISABLE = 0x0,
- DCIOCHIP_DVO_VREFPON_ENABLE = 0x1,
-} DCIOCHIP_DVO_VREFPON;
-typedef enum DCIOCHIP_DVO_VREFSEL {
- DCIOCHIP_DVO_VREFSEL_ONCHIP = 0x0,
- DCIOCHIP_DVO_VREFSEL_EXTERNAL = 0x1,
-} DCIOCHIP_DVO_VREFSEL;
-typedef enum DCIOCHIP_SPDIF1_IMODE {
- DCIOCHIP_SPDIF1_IMODE_OE_A = 0x0,
- DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO = 0x1,
-} DCIOCHIP_SPDIF1_IMODE;
-typedef enum DCIOCHIP_AUX_FALLSLEWSEL {
- DCIOCHIP_AUX_FALLSLEWSEL_LOW = 0x0,
- DCIOCHIP_AUX_FALLSLEWSEL_HIGH0 = 0x1,
- DCIOCHIP_AUX_FALLSLEWSEL_HIGH1 = 0x2,
- DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH = 0x3,
-} DCIOCHIP_AUX_FALLSLEWSEL;
-typedef enum DCIOCHIP_AUX_SPIKESEL {
- DCIOCHIP_AUX_SPIKESEL_50NS = 0x0,
- DCIOCHIP_AUX_SPIKESEL_10NS = 0x1,
-} DCIOCHIP_AUX_SPIKESEL;
-typedef enum DCIOCHIP_AUX_CSEL0P9 {
- DCIOCHIP_AUX_CSEL_DEC1P0 = 0x0,
- DCIOCHIP_AUX_CSEL_DEC0P9 = 0x1,
-} DCIOCHIP_AUX_CSEL0P9;
-typedef enum DCIOCHIP_AUX_CSEL1P1 {
- DCIOCHIP_AUX_CSEL_INC1P0 = 0x0,
- DCIOCHIP_AUX_CSEL_INC1P1 = 0x1,
-} DCIOCHIP_AUX_CSEL1P1;
-typedef enum DCIOCHIP_AUX_RSEL0P9 {
- DCIOCHIP_AUX_RSEL_DEC1P0 = 0x0,
- DCIOCHIP_AUX_RSEL_DEC0P9 = 0x1,
-} DCIOCHIP_AUX_RSEL0P9;
-typedef enum DCIOCHIP_AUX_RSEL1P1 {
- DCIOCHIP_AUX_RSEL_INC1P0 = 0x0,
- DCIOCHIP_AUX_RSEL_INC1P1 = 0x1,
-} DCIOCHIP_AUX_RSEL1P1;
-typedef enum DCP_GRPH_ENABLE {
- DCP_GRPH_ENABLE_FALSE = 0x0,
- DCP_GRPH_ENABLE_TRUE = 0x1,
-} DCP_GRPH_ENABLE;
-typedef enum DCP_GRPH_KEYER_ALPHA_SEL {
- DCP_GRPH_KEYER_ALPHA_SEL_FALSE = 0x0,
- DCP_GRPH_KEYER_ALPHA_SEL_TRUE = 0x1,
-} DCP_GRPH_KEYER_ALPHA_SEL;
-typedef enum DCP_GRPH_DEPTH {
- DCP_GRPH_DEPTH_8BPP = 0x0,
- DCP_GRPH_DEPTH_16BPP = 0x1,
- DCP_GRPH_DEPTH_32BPP = 0x2,
- DCP_GRPH_DEPTH_64BPP = 0x3,
-} DCP_GRPH_DEPTH;
-typedef enum DCP_GRPH_NUM_BANKS {
- DCP_GRPH_NUM_BANKS_2BANK = 0x0,
- DCP_GRPH_NUM_BANKS_4BANK = 0x1,
- DCP_GRPH_NUM_BANKS_8BANK = 0x2,
- DCP_GRPH_NUM_BANKS_16BANK = 0x3,
-} DCP_GRPH_NUM_BANKS;
-typedef enum DCP_GRPH_BANK_WIDTH {
- DCP_GRPH_BANK_WIDTH_1 = 0x0,
- DCP_GRPH_BANK_WIDTH_2 = 0x1,
- DCP_GRPH_BANK_WIDTH_4 = 0x2,
- DCP_GRPH_BANK_WIDTH_8 = 0x3,
-} DCP_GRPH_BANK_WIDTH;
-typedef enum DCP_GRPH_FORMAT {
- DCP_GRPH_FORMAT_8BPP = 0x0,
- DCP_GRPH_FORMAT_16BPP = 0x1,
- DCP_GRPH_FORMAT_32BPP = 0x2,
- DCP_GRPH_FORMAT_64BPP = 0x3,
-} DCP_GRPH_FORMAT;
-typedef enum DCP_GRPH_BANK_HEIGHT {
- DCP_GRPH_BANK_HEIGHT_1 = 0x0,
- DCP_GRPH_BANK_HEIGHT_2 = 0x1,
- DCP_GRPH_BANK_HEIGHT_4 = 0x2,
- DCP_GRPH_BANK_HEIGHT_8 = 0x3,
-} DCP_GRPH_BANK_HEIGHT;
-typedef enum DCP_GRPH_TILE_SPLIT {
- DCP_GRPH_TILE_SPLIT_64B = 0x0,
- DCP_GRPH_TILE_SPLIT_128B = 0x1,
- DCP_GRPH_TILE_SPLIT_256B = 0x2,
- DCP_GRPH_TILE_SPLIT_512B = 0x3,
- DCP_GRPH_TILE_SPLIT_1B = 0x4,
- DCP_GRPH_TILE_SPLIT_2B = 0x5,
- DCP_GRPH_TILE_SPLIT_4B = 0x6,
-} DCP_GRPH_TILE_SPLIT;
-typedef enum DCP_GRPH_ADDRESS_TRANSLATION_ENABLE {
- DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_FALSE = 0x0,
- DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_TRUE = 0x1,
-} DCP_GRPH_ADDRESS_TRANSLATION_ENABLE;
-typedef enum DCP_GRPH_PRIVILEGED_ACCESS_ENABLE {
- DCP_GRPH_PRIVILEGED_ACCESS_ENABLE_FALSE = 0x0,
- DCP_GRPH_PRIVILEGED_ACCESS_ENABLE_TRUE = 0x1,
-} DCP_GRPH_PRIVILEGED_ACCESS_ENABLE;
-typedef enum DCP_GRPH_MACRO_TILE_ASPECT {
- DCP_GRPH_MACRO_TILE_ASPECT_1 = 0x0,
- DCP_GRPH_MACRO_TILE_ASPECT_2 = 0x1,
- DCP_GRPH_MACRO_TILE_ASPECT_4 = 0x2,
- DCP_GRPH_MACRO_TILE_ASPECT_8 = 0x3,
-} DCP_GRPH_MACRO_TILE_ASPECT;
-typedef enum DCP_GRPH_ARRAY_MODE {
- DCP_GRPH_ARRAY_MODE_0 = 0x0,
- DCP_GRPH_ARRAY_MODE_1 = 0x1,
- DCP_GRPH_ARRAY_MODE_2 = 0x2,
- DCP_GRPH_ARRAY_MODE_3 = 0x3,
- DCP_GRPH_ARRAY_MODE_4 = 0x4,
- DCP_GRPH_ARRAY_MODE_7 = 0x7,
- DCP_GRPH_ARRAY_MODE_12 = 0xc,
- DCP_GRPH_ARRAY_MODE_13 = 0xd,
-} DCP_GRPH_ARRAY_MODE;
-typedef enum DCP_GRPH_MICRO_TILE_MODE {
- DCP_GRPH_MICRO_TILE_MODE_0 = 0x0,
- DCP_GRPH_MICRO_TILE_MODE_1 = 0x1,
- DCP_GRPH_MICRO_TILE_MODE_2 = 0x2,
- DCP_GRPH_MICRO_TILE_MODE_3 = 0x3,
-} DCP_GRPH_MICRO_TILE_MODE;
-typedef enum DCP_GRPH_COLOR_EXPANSION_MODE {
- DCP_GRPH_COLOR_EXPANSION_MODE_DEXP = 0x0,
- DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP = 0x1,
-} DCP_GRPH_COLOR_EXPANSION_MODE;
-typedef enum DCP_GRPH_LUT_10BIT_BYPASS_EN {
- DCP_GRPH_LUT_10BIT_BYPASS_EN_FALSE = 0x0,
- DCP_GRPH_LUT_10BIT_BYPASS_EN_TRUE = 0x1,
-} DCP_GRPH_LUT_10BIT_BYPASS_EN;
-typedef enum DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN {
- DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_FALSE = 0x0,
- DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_TRUE = 0x1,
-} DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN;
-typedef enum DCP_GRPH_ENDIAN_SWAP {
- DCP_GRPH_ENDIAN_SWAP_NONE = 0x0,
- DCP_GRPH_ENDIAN_SWAP_8IN16 = 0x1,
- DCP_GRPH_ENDIAN_SWAP_8IN32 = 0x2,
- DCP_GRPH_ENDIAN_SWAP_8IN64 = 0x3,
-} DCP_GRPH_ENDIAN_SWAP;
-typedef enum DCP_GRPH_RED_CROSSBAR {
- DCP_GRPH_RED_CROSSBAR_FROM_R = 0x0,
- DCP_GRPH_RED_CROSSBAR_FROM_G = 0x1,
- DCP_GRPH_RED_CROSSBAR_FROM_B = 0x2,
- DCP_GRPH_RED_CROSSBAR_FROM_A = 0x3,
-} DCP_GRPH_RED_CROSSBAR;
-typedef enum DCP_GRPH_GREEN_CROSSBAR {
- DCP_GRPH_GREEN_CROSSBAR_FROM_G = 0x0,
- DCP_GRPH_GREEN_CROSSBAR_FROM_B = 0x1,
- DCP_GRPH_GREEN_CROSSBAR_FROM_A = 0x2,
- DCP_GRPH_GREEN_CROSSBAR_FROM_R = 0x3,
-} DCP_GRPH_GREEN_CROSSBAR;
-typedef enum DCP_GRPH_BLUE_CROSSBAR {
- DCP_GRPH_BLUE_CROSSBAR_FROM_B = 0x0,
- DCP_GRPH_BLUE_CROSSBAR_FROM_A = 0x1,
- DCP_GRPH_BLUE_CROSSBAR_FROM_R = 0x2,
- DCP_GRPH_BLUE_CROSSBAR_FROM_G = 0x3,
-} DCP_GRPH_BLUE_CROSSBAR;
-typedef enum DCP_GRPH_ALPHA_CROSSBAR {
- DCP_GRPH_ALPHA_CROSSBAR_FROM_A = 0x0,
- DCP_GRPH_ALPHA_CROSSBAR_FROM_R = 0x1,
- DCP_GRPH_ALPHA_CROSSBAR_FROM_G = 0x2,
- DCP_GRPH_ALPHA_CROSSBAR_FROM_B = 0x3,
-} DCP_GRPH_ALPHA_CROSSBAR;
-typedef enum DCP_GRPH_PRIMARY_DFQ_ENABLE {
- DCP_GRPH_PRIMARY_DFQ_ENABLE_FALSE = 0x0,
- DCP_GRPH_PRIMARY_DFQ_ENABLE_TRUE = 0x1,
-} DCP_GRPH_PRIMARY_DFQ_ENABLE;
-typedef enum DCP_GRPH_SECONDARY_DFQ_ENABLE {
- DCP_GRPH_SECONDARY_DFQ_ENABLE_FALSE = 0x0,
- DCP_GRPH_SECONDARY_DFQ_ENABLE_TRUE = 0x1,
-} DCP_GRPH_SECONDARY_DFQ_ENABLE;
-typedef enum DCP_GRPH_INPUT_GAMMA_MODE {
- DCP_GRPH_INPUT_GAMMA_MODE_LUT = 0x0,
- DCP_GRPH_INPUT_GAMMA_MODE_BYPASS = 0x1,
-} DCP_GRPH_INPUT_GAMMA_MODE;
-typedef enum DCP_GRPH_MODE_UPDATE_PENDING {
- DCP_GRPH_MODE_UPDATE_PENDING_FALSE = 0x0,
- DCP_GRPH_MODE_UPDATE_PENDING_TRUE = 0x1,
-} DCP_GRPH_MODE_UPDATE_PENDING;
-typedef enum DCP_GRPH_MODE_UPDATE_TAKEN {
- DCP_GRPH_MODE_UPDATE_TAKEN_FALSE = 0x0,
- DCP_GRPH_MODE_UPDATE_TAKEN_TRUE = 0x1,
-} DCP_GRPH_MODE_UPDATE_TAKEN;
-typedef enum DCP_GRPH_SURFACE_UPDATE_PENDING {
- DCP_GRPH_SURFACE_UPDATE_PENDING_FALSE = 0x0,
- DCP_GRPH_SURFACE_UPDATE_PENDING_TRUE = 0x1,
-} DCP_GRPH_SURFACE_UPDATE_PENDING;
-typedef enum DCP_GRPH_SURFACE_UPDATE_TAKEN {
- DCP_GRPH_SURFACE_UPDATE_TAKEN_FALSE = 0x0,
- DCP_GRPH_SURFACE_UPDATE_TAKEN_TRUE = 0x1,
-} DCP_GRPH_SURFACE_UPDATE_TAKEN;
-typedef enum DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE {
- DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_FALSE = 0x0,
- DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_TRUE = 0x1,
-} DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE;
-typedef enum DCP_GRPH_UPDATE_LOCK {
- DCP_GRPH_UPDATE_LOCK_FALSE = 0x0,
- DCP_GRPH_UPDATE_LOCK_TRUE = 0x1,
-} DCP_GRPH_UPDATE_LOCK;
-typedef enum DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK {
- DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_FALSE = 0x0,
- DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_TRUE = 0x1,
-} DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK;
-typedef enum DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE {
- DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_FALSE = 0x0,
- DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_TRUE = 0x1,
-} DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE;
-typedef enum DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE {
- DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_FALSE = 0x0,
- DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_TRUE = 0x1,
-} DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE;
-typedef enum DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN {
- DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_FALSE = 0x0,
- DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_TRUE = 0x1,
-} DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
-typedef enum DCP_GRPH_XDMA_SUPER_AA_EN {
- DCP_GRPH_XDMA_SUPER_AA_EN_FALSE = 0x0,
- DCP_GRPH_XDMA_SUPER_AA_EN_TRUE = 0x1,
-} DCP_GRPH_XDMA_SUPER_AA_EN;
-typedef enum DCP_GRPH_DFQ_RESET {
- DCP_GRPH_DFQ_RESET_FALSE = 0x0,
- DCP_GRPH_DFQ_RESET_TRUE = 0x1,
-} DCP_GRPH_DFQ_RESET;
-typedef enum DCP_GRPH_DFQ_SIZE {
- DCP_GRPH_DFQ_SIZE_DEEP1 = 0x0,
- DCP_GRPH_DFQ_SIZE_DEEP2 = 0x1,
- DCP_GRPH_DFQ_SIZE_DEEP3 = 0x2,
- DCP_GRPH_DFQ_SIZE_DEEP4 = 0x3,
- DCP_GRPH_DFQ_SIZE_DEEP5 = 0x4,
- DCP_GRPH_DFQ_SIZE_DEEP6 = 0x5,
- DCP_GRPH_DFQ_SIZE_DEEP7 = 0x6,
- DCP_GRPH_DFQ_SIZE_DEEP8 = 0x7,
-} DCP_GRPH_DFQ_SIZE;
-typedef enum DCP_GRPH_DFQ_MIN_FREE_ENTRIES {
- DCP_GRPH_DFQ_MIN_FREE_ENTRIES_1 = 0x0,
- DCP_GRPH_DFQ_MIN_FREE_ENTRIES_2 = 0x1,
- DCP_GRPH_DFQ_MIN_FREE_ENTRIES_3 = 0x2,
- DCP_GRPH_DFQ_MIN_FREE_ENTRIES_4 = 0x3,
- DCP_GRPH_DFQ_MIN_FREE_ENTRIES_5 = 0x4,
- DCP_GRPH_DFQ_MIN_FREE_ENTRIES_6 = 0x5,
- DCP_GRPH_DFQ_MIN_FREE_ENTRIES_7 = 0x6,
- DCP_GRPH_DFQ_MIN_FREE_ENTRIES_8 = 0x7,
-} DCP_GRPH_DFQ_MIN_FREE_ENTRIES;
-typedef enum DCP_GRPH_DFQ_RESET_ACK {
- DCP_GRPH_DFQ_RESET_ACK_FALSE = 0x0,
- DCP_GRPH_DFQ_RESET_ACK_TRUE = 0x1,
-} DCP_GRPH_DFQ_RESET_ACK;
-typedef enum DCP_GRPH_PFLIP_INT_CLEAR {
- DCP_GRPH_PFLIP_INT_CLEAR_FALSE = 0x0,
- DCP_GRPH_PFLIP_INT_CLEAR_TRUE = 0x1,
-} DCP_GRPH_PFLIP_INT_CLEAR;
-typedef enum DCP_GRPH_PFLIP_INT_MASK {
- DCP_GRPH_PFLIP_INT_MASK_FALSE = 0x0,
- DCP_GRPH_PFLIP_INT_MASK_TRUE = 0x1,
-} DCP_GRPH_PFLIP_INT_MASK;
-typedef enum DCP_GRPH_PFLIP_INT_TYPE {
- DCP_GRPH_PFLIP_INT_TYPE_LEGACY_LEVEL = 0x0,
- DCP_GRPH_PFLIP_INT_TYPE_PULSE = 0x1,
-} DCP_GRPH_PFLIP_INT_TYPE;
-typedef enum DCP_GRPH_PRESCALE_SELECT {
- DCP_GRPH_PRESCALE_SELECT_FIXED = 0x0,
- DCP_GRPH_PRESCALE_SELECT_FLOATING = 0x1,
-} DCP_GRPH_PRESCALE_SELECT;
-typedef enum DCP_GRPH_PRESCALE_R_SIGN {
- DCP_GRPH_PRESCALE_R_SIGN_UNSIGNED = 0x0,
- DCP_GRPH_PRESCALE_R_SIGN_SIGNED = 0x1,
-} DCP_GRPH_PRESCALE_R_SIGN;
-typedef enum DCP_GRPH_PRESCALE_G_SIGN {
- DCP_GRPH_PRESCALE_G_SIGN_UNSIGNED = 0x0,
- DCP_GRPH_PRESCALE_G_SIGN_SIGNED = 0x1,
-} DCP_GRPH_PRESCALE_G_SIGN;
-typedef enum DCP_GRPH_PRESCALE_B_SIGN {
- DCP_GRPH_PRESCALE_B_SIGN_UNSIGNED = 0x0,
- DCP_GRPH_PRESCALE_B_SIGN_SIGNED = 0x1,
-} DCP_GRPH_PRESCALE_B_SIGN;
-typedef enum DCP_GRPH_PRESCALE_BYPASS {
- DCP_GRPH_PRESCALE_BYPASS_FALSE = 0x0,
- DCP_GRPH_PRESCALE_BYPASS_TRUE = 0x1,
-} DCP_GRPH_PRESCALE_BYPASS;
-typedef enum DCP_INPUT_CSC_GRPH_MODE {
- DCP_INPUT_CSC_GRPH_MODE_BYPASS = 0x0,
- DCP_INPUT_CSC_GRPH_MODE_INPUT_CSC_COEF = 0x1,
- DCP_INPUT_CSC_GRPH_MODE_SHARED_COEF = 0x2,
- DCP_INPUT_CSC_GRPH_MODE_RESERVED = 0x3,
-} DCP_INPUT_CSC_GRPH_MODE;
-typedef enum DCP_OUTPUT_CSC_GRPH_MODE {
- DCP_OUTPUT_CSC_GRPH_MODE_BYPASS = 0x0,
- DCP_OUTPUT_CSC_GRPH_MODE_RGB = 0x1,
- DCP_OUTPUT_CSC_GRPH_MODE_YCBCR601 = 0x2,
- DCP_OUTPUT_CSC_GRPH_MODE_YCBCR709 = 0x3,
- DCP_OUTPUT_CSC_GRPH_MODE_OUTPUT_CSC_COEF = 0x4,
- DCP_OUTPUT_CSC_GRPH_MODE_SHARED_COEF = 0x5,
- DCP_OUTPUT_CSC_GRPH_MODE_RESERVED0 = 0x6,
- DCP_OUTPUT_CSC_GRPH_MODE_RESERVED1 = 0x7,
-} DCP_OUTPUT_CSC_GRPH_MODE;
-typedef enum DCP_DENORM_MODE {
- DCP_DENORM_MODE_UNITY = 0x0,
- DCP_DENORM_MODE_6BIT = 0x1,
- DCP_DENORM_MODE_8BIT = 0x2,
- DCP_DENORM_MODE_10BIT = 0x3,
- DCP_DENORM_MODE_11BIT = 0x4,
- DCP_DENORM_MODE_12BIT = 0x5,
- DCP_DENORM_MODE_RESERVED0 = 0x6,
- DCP_DENORM_MODE_RESERVED1 = 0x7,
-} DCP_DENORM_MODE;
-typedef enum DCP_DENORM_14BIT_OUT {
- DCP_DENORM_14BIT_OUT_FALSE = 0x0,
- DCP_DENORM_14BIT_OUT_TRUE = 0x1,
-} DCP_DENORM_14BIT_OUT;
-typedef enum DCP_OUT_ROUND_TRUNC_MODE {
- DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_12 = 0x0,
- DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_11 = 0x1,
- DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_10 = 0x2,
- DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_9 = 0x3,
- DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_8 = 0x4,
- DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_RESERVED = 0x5,
- DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_14 = 0x6,
- DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_13 = 0x7,
- DCP_OUT_ROUND_TRUNC_MODE_ROUND_12 = 0x8,
- DCP_OUT_ROUND_TRUNC_MODE_ROUND_11 = 0x9,
- DCP_OUT_ROUND_TRUNC_MODE_ROUND_10 = 0xa,
- DCP_OUT_ROUND_TRUNC_MODE_ROUND_9 = 0xb,
- DCP_OUT_ROUND_TRUNC_MODE_ROUND_8 = 0xc,
- DCP_OUT_ROUND_TRUNC_MODE_ROUND_RESERVED = 0xd,
- DCP_OUT_ROUND_TRUNC_MODE_ROUND_14 = 0xe,
- DCP_OUT_ROUND_TRUNC_MODE_ROUND_13 = 0xf,
-} DCP_OUT_ROUND_TRUNC_MODE;
-typedef enum DCP_KEY_MODE {
- DCP_KEY_MODE_ALPHA0 = 0x0,
- DCP_KEY_MODE_ALPHA1 = 0x1,
- DCP_KEY_MODE_IN_RANGE_ALPHA1 = 0x2,
- DCP_KEY_MODE_IN_RANGE_ALPHA0 = 0x3,
-} DCP_KEY_MODE;
-typedef enum DCP_GRPH_DEGAMMA_MODE {
- DCP_GRPH_DEGAMMA_MODE_BYPASS = 0x0,
- DCP_GRPH_DEGAMMA_MODE_ROMA = 0x1,
- DCP_GRPH_DEGAMMA_MODE_ROMB = 0x2,
- DCP_GRPH_DEGAMMA_MODE_RESERVED = 0x3,
-} DCP_GRPH_DEGAMMA_MODE;
-typedef enum DCP_CURSOR2_DEGAMMA_MODE {
- DCP_CURSOR2_DEGAMMA_MODE_BYPASS = 0x0,
- DCP_CURSOR2_DEGAMMA_MODE_ROMA = 0x1,
- DCP_CURSOR2_DEGAMMA_MODE_ROMB = 0x2,
- DCP_CURSOR2_DEGAMMA_MODE_RESERVED = 0x3,
-} DCP_CURSOR2_DEGAMMA_MODE;
-typedef enum DCP_CURSOR_DEGAMMA_MODE {
- DCP_CURSOR_DEGAMMA_MODE_BYPASS = 0x0,
- DCP_CURSOR_DEGAMMA_MODE_ROMA = 0x1,
- DCP_CURSOR_DEGAMMA_MODE_ROMB = 0x2,
- DCP_CURSOR_DEGAMMA_MODE_RESERVED = 0x3,
-} DCP_CURSOR_DEGAMMA_MODE;
-typedef enum DCP_GRPH_GAMUT_REMAP_MODE {
- DCP_GRPH_GAMUT_REMAP_MODE_BYPASS = 0x0,
- DCP_GRPH_GAMUT_REMAP_MODE_ROMA = 0x1,
- DCP_GRPH_GAMUT_REMAP_MODE_ROMB = 0x2,
- DCP_GRPH_GAMUT_REMAP_MODE_RESERVED = 0x3,
-} DCP_GRPH_GAMUT_REMAP_MODE;
-typedef enum DCP_SPATIAL_DITHER_EN {
- DCP_SPATIAL_DITHER_EN_FALSE = 0x0,
- DCP_SPATIAL_DITHER_EN_TRUE = 0x1,
-} DCP_SPATIAL_DITHER_EN;
-typedef enum DCP_SPATIAL_DITHER_MODE {
- DCP_SPATIAL_DITHER_MODE_BYPASS = 0x0,
- DCP_SPATIAL_DITHER_MODE_ROMA = 0x1,
- DCP_SPATIAL_DITHER_MODE_ROMB = 0x2,
- DCP_SPATIAL_DITHER_MODE_RESERVED = 0x3,
-} DCP_SPATIAL_DITHER_MODE;
-typedef enum DCP_SPATIAL_DITHER_DEPTH {
- DCP_SPATIAL_DITHER_DEPTH_30BPP = 0x0,
- DCP_SPATIAL_DITHER_DEPTH_24BPP = 0x1,
- DCP_SPATIAL_DITHER_DEPTH_36BPP = 0x2,
- DCP_SPATIAL_DITHER_DEPTH_UNDEFINED = 0x3,
-} DCP_SPATIAL_DITHER_DEPTH;
-typedef enum DCP_FRAME_RANDOM_ENABLE {
- DCP_FRAME_RANDOM_ENABLE_FALSE = 0x0,
- DCP_FRAME_RANDOM_ENABLE_TRUE = 0x1,
-} DCP_FRAME_RANDOM_ENABLE;
-typedef enum DCP_RGB_RANDOM_ENABLE {
- DCP_RGB_RANDOM_ENABLE_FALSE = 0x0,
- DCP_RGB_RANDOM_ENABLE_TRUE = 0x1,
-} DCP_RGB_RANDOM_ENABLE;
-typedef enum DCP_HIGHPASS_RANDOM_ENABLE {
- DCP_HIGHPASS_RANDOM_ENABLE_FALSE = 0x0,
- DCP_HIGHPASS_RANDOM_ENABLE_TRUE = 0x1,
-} DCP_HIGHPASS_RANDOM_ENABLE;
-typedef enum DCP_CURSOR_EN {
- DCP_CURSOR_EN_FALSE = 0x0,
- DCP_CURSOR_EN_TRUE = 0x1,
-} DCP_CURSOR_EN;
-typedef enum DCP_CUR_INV_TRANS_CLAMP {
- DCP_CUR_INV_TRANS_CLAMP_FALSE = 0x0,
- DCP_CUR_INV_TRANS_CLAMP_TRUE = 0x1,
-} DCP_CUR_INV_TRANS_CLAMP;
-typedef enum DCP_CURSOR_MODE {
- DCP_CURSOR_MODE_MONO_2BPP = 0x0,
- DCP_CURSOR_MODE_24BPP_1BIT = 0x1,
- DCP_CURSOR_MODE_24BPP_8BIT_PREMULTI = 0x2,
- DCP_CURSOR_MODE_24BPP_8BIT_UNPREMULTI = 0x3,
-} DCP_CURSOR_MODE;
-typedef enum DCP_CURSOR_2X_MAGNIFY {
- DCP_CURSOR_2X_MAGNIFY_FALSE = 0x0,
- DCP_CURSOR_2X_MAGNIFY_TRUE = 0x1,
-} DCP_CURSOR_2X_MAGNIFY;
-typedef enum DCP_CURSOR_FORCE_MC_ON {
- DCP_CURSOR_FORCE_MC_ON_FALSE = 0x0,
- DCP_CURSOR_FORCE_MC_ON_TRUE = 0x1,
-} DCP_CURSOR_FORCE_MC_ON;
-typedef enum DCP_CURSOR_URGENT_CONTROL {
- DCP_CURSOR_URGENT_CONTROL_MODE_0 = 0x0,
- DCP_CURSOR_URGENT_CONTROL_MODE_1 = 0x1,
- DCP_CURSOR_URGENT_CONTROL_MODE_2 = 0x2,
- DCP_CURSOR_URGENT_CONTROL_MODE_3 = 0x3,
- DCP_CURSOR_URGENT_CONTROL_MODE_4 = 0x4,
-} DCP_CURSOR_URGENT_CONTROL;
-typedef enum DCP_CURSOR_UPDATE_PENDING {
- DCP_CURSOR_UPDATE_PENDING_FALSE = 0x0,
- DCP_CURSOR_UPDATE_PENDING_TRUE = 0x1,
-} DCP_CURSOR_UPDATE_PENDING;
-typedef enum DCP_CURSOR_UPDATE_TAKEN {
- DCP_CURSOR_UPDATE_TAKEN_FALSE = 0x0,
- DCP_CURSOR_UPDATE_TAKEN_TRUE = 0x1,
-} DCP_CURSOR_UPDATE_TAKEN;
-typedef enum DCP_CURSOR_UPDATE_LOCK {
- DCP_CURSOR_UPDATE_LOCK_FALSE = 0x0,
- DCP_CURSOR_UPDATE_LOCK_TRUE = 0x1,
-} DCP_CURSOR_UPDATE_LOCK;
-typedef enum DCP_CURSOR_DISABLE_MULTIPLE_UPDATE {
- DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_FALSE = 0x0,
- DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_TRUE = 0x1,
-} DCP_CURSOR_DISABLE_MULTIPLE_UPDATE;
-typedef enum DCP_CURSOR_UPDATE_STEREO_MODE {
- DCP_CURSOR_UPDATE_STEREO_MODE_BOTH = 0x0,
- DCP_CURSOR_UPDATE_STEREO_MODE_SECONDARY_ONLY = 0x1,
- DCP_CURSOR_UPDATE_STEREO_MODE_UNDEFINED = 0x2,
- DCP_CURSOR_UPDATE_STEREO_MODE_PRIMARY_ONLY = 0x3,
-} DCP_CURSOR_UPDATE_STEREO_MODE;
-typedef enum DCP_CURSOR2_EN {
- DCP_CURSOR2_EN_FALSE = 0x0,
- DCP_CURSOR2_EN_TRUE = 0x1,
-} DCP_CURSOR2_EN;
-typedef enum DCP_CUR2_INV_TRANS_CLAMP {
- DCP_CUR2_INV_TRANS_CLAMP_FALSE = 0x0,
- DCP_CUR2_INV_TRANS_CLAMP_TRUE = 0x1,
-} DCP_CUR2_INV_TRANS_CLAMP;
-typedef enum DCP_CURSOR2_MODE {
- DCP_CURSOR2_MODE_MONO_2BPP = 0x0,
- DCP_CURSOR2_MODE_24BPP_1BIT = 0x1,
- DCP_CURSOR2_MODE_24BPP_8BIT_PREMULTI = 0x2,
- DCP_CURSOR2_MODE_24BPP_8BIT_UNPREMULTI = 0x3,
-} DCP_CURSOR2_MODE;
-typedef enum DCP_CURSOR2_2X_MAGNIFY {
- DCP_CURSOR2_2X_MAGNIFY_FALSE = 0x0,
- DCP_CURSOR2_2X_MAGNIFY_TRUE = 0x1,
-} DCP_CURSOR2_2X_MAGNIFY;
-typedef enum DCP_CURSOR2_FORCE_MC_ON {
- DCP_CURSOR2_FORCE_MC_ON_FALSE = 0x0,
- DCP_CURSOR2_FORCE_MC_ON_TRUE = 0x1,
-} DCP_CURSOR2_FORCE_MC_ON;
-typedef enum DCP_CURSOR2_URGENT_CONTROL {
- DCP_CURSOR2_URGENT_CONTROL_MODE_0 = 0x0,
- DCP_CURSOR2_URGENT_CONTROL_MODE_1 = 0x1,
- DCP_CURSOR2_URGENT_CONTROL_MODE_2 = 0x2,
- DCP_CURSOR2_URGENT_CONTROL_MODE_3 = 0x3,
- DCP_CURSOR2_URGENT_CONTROL_MODE_4 = 0x4,
-} DCP_CURSOR2_URGENT_CONTROL;
-typedef enum DCP_CURSOR2_UPDATE_PENDING {
- DCP_CURSOR2_UPDATE_PENDING_FALSE = 0x0,
- DCP_CURSOR2_UPDATE_PENDING_TRUE = 0x1,
-} DCP_CURSOR2_UPDATE_PENDING;
-typedef enum DCP_CURSOR2_UPDATE_TAKEN {
- DCP_CURSOR2_UPDATE_TAKEN_FALSE = 0x0,
- DCP_CURSOR2_UPDATE_TAKEN_TRUE = 0x1,
-} DCP_CURSOR2_UPDATE_TAKEN;
-typedef enum DCP_CURSOR2_UPDATE_LOCK {
- DCP_CURSOR2_UPDATE_LOCK_FALSE = 0x0,
- DCP_CURSOR2_UPDATE_LOCK_TRUE = 0x1,
-} DCP_CURSOR2_UPDATE_LOCK;
-typedef enum DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE {
- DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE_FALSE = 0x0,
- DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE_TRUE = 0x1,
-} DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE;
-typedef enum DCP_CURSOR2_UPDATE_STEREO_MODE {
- DCP_CURSOR2_UPDATE_STEREO_MODE_BOTH = 0x0,
- DCP_CURSOR2_UPDATE_STEREO_MODE_SECONDARY_ONLY = 0x1,
- DCP_CURSOR2_UPDATE_STEREO_MODE_UNDEFINED = 0x2,
- DCP_CURSOR2_UPDATE_STEREO_MODE_PRIMARY_ONLY = 0x3,
-} DCP_CURSOR2_UPDATE_STEREO_MODE;
-typedef enum DCP_CUR_REQUEST_FILTER_DIS {
- DCP_CUR_REQUEST_FILTER_DIS_FALSE = 0x0,
- DCP_CUR_REQUEST_FILTER_DIS_TRUE = 0x1,
-} DCP_CUR_REQUEST_FILTER_DIS;
-typedef enum DCP_CURSOR_STEREO_EN {
- DCP_CURSOR_STEREO_EN_FALSE = 0x0,
- DCP_CURSOR_STEREO_EN_TRUE = 0x1,
-} DCP_CURSOR_STEREO_EN;
-typedef enum DCP_CURSOR_STEREO_OFFSET_YNX {
- DCP_CURSOR_STEREO_OFFSET_YNX_X_POSITION = 0x0,
- DCP_CURSOR_STEREO_OFFSET_YNX_Y_POSITION = 0x1,
-} DCP_CURSOR_STEREO_OFFSET_YNX;
-typedef enum DCP_CURSOR2_STEREO_EN {
- DCP_CURSOR2_STEREO_EN_FALSE = 0x0,
- DCP_CURSOR2_STEREO_EN_TRUE = 0x1,
-} DCP_CURSOR2_STEREO_EN;
-typedef enum DCP_CURSOR2_STEREO_OFFSET_YNX {
- DCP_CURSOR2_STEREO_OFFSET_YNX_X_POSITION = 0x0,
- DCP_CURSOR2_STEREO_OFFSET_YNX_Y_POSITION = 0x1,
-} DCP_CURSOR2_STEREO_OFFSET_YNX;
-typedef enum DCP_DC_LUT_RW_MODE {
- DCP_DC_LUT_RW_MODE_256_ENTRY = 0x0,
- DCP_DC_LUT_RW_MODE_PWL = 0x1,
-} DCP_DC_LUT_RW_MODE;
-typedef enum DCP_DC_LUT_VGA_ACCESS_ENABLE {
- DCP_DC_LUT_VGA_ACCESS_ENABLE_FALSE = 0x0,
- DCP_DC_LUT_VGA_ACCESS_ENABLE_TRUE = 0x1,
-} DCP_DC_LUT_VGA_ACCESS_ENABLE;
-typedef enum DCP_DC_LUT_AUTOFILL {
- DCP_DC_LUT_AUTOFILL_FALSE = 0x0,
- DCP_DC_LUT_AUTOFILL_TRUE = 0x1,
-} DCP_DC_LUT_AUTOFILL;
-typedef enum DCP_DC_LUT_AUTOFILL_DONE {
- DCP_DC_LUT_AUTOFILL_DONE_FALSE = 0x0,
- DCP_DC_LUT_AUTOFILL_DONE_TRUE = 0x1,
-} DCP_DC_LUT_AUTOFILL_DONE;
-typedef enum DCP_DC_LUT_INC_B {
- DCP_DC_LUT_INC_B_NA = 0x0,
- DCP_DC_LUT_INC_B_2 = 0x1,
- DCP_DC_LUT_INC_B_4 = 0x2,
- DCP_DC_LUT_INC_B_8 = 0x3,
- DCP_DC_LUT_INC_B_16 = 0x4,
- DCP_DC_LUT_INC_B_32 = 0x5,
- DCP_DC_LUT_INC_B_64 = 0x6,
- DCP_DC_LUT_INC_B_128 = 0x7,
- DCP_DC_LUT_INC_B_256 = 0x8,
- DCP_DC_LUT_INC_B_512 = 0x9,
-} DCP_DC_LUT_INC_B;
-typedef enum DCP_DC_LUT_DATA_B_SIGNED_EN {
- DCP_DC_LUT_DATA_B_SIGNED_EN_FALSE = 0x0,
- DCP_DC_LUT_DATA_B_SIGNED_EN_TRUE = 0x1,
-} DCP_DC_LUT_DATA_B_SIGNED_EN;
-typedef enum DCP_DC_LUT_DATA_B_FLOAT_POINT_EN {
- DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_FALSE = 0x0,
- DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_TRUE = 0x1,
-} DCP_DC_LUT_DATA_B_FLOAT_POINT_EN;
-typedef enum DCP_DC_LUT_DATA_B_FORMAT {
- DCP_DC_LUT_DATA_B_FORMAT_U0P10 = 0x0,
- DCP_DC_LUT_DATA_B_FORMAT_S1P10 = 0x1,
- DCP_DC_LUT_DATA_B_FORMAT_U1P11 = 0x2,
- DCP_DC_LUT_DATA_B_FORMAT_U0P12 = 0x3,
-} DCP_DC_LUT_DATA_B_FORMAT;
-typedef enum DCP_DC_LUT_INC_G {
- DCP_DC_LUT_INC_G_NA = 0x0,
- DCP_DC_LUT_INC_G_2 = 0x1,
- DCP_DC_LUT_INC_G_4 = 0x2,
- DCP_DC_LUT_INC_G_8 = 0x3,
- DCP_DC_LUT_INC_G_16 = 0x4,
- DCP_DC_LUT_INC_G_32 = 0x5,
- DCP_DC_LUT_INC_G_64 = 0x6,
- DCP_DC_LUT_INC_G_128 = 0x7,
- DCP_DC_LUT_INC_G_256 = 0x8,
- DCP_DC_LUT_INC_G_512 = 0x9,
-} DCP_DC_LUT_INC_G;
-typedef enum DCP_DC_LUT_DATA_G_SIGNED_EN {
- DCP_DC_LUT_DATA_G_SIGNED_EN_FALSE = 0x0,
- DCP_DC_LUT_DATA_G_SIGNED_EN_TRUE = 0x1,
-} DCP_DC_LUT_DATA_G_SIGNED_EN;
-typedef enum DCP_DC_LUT_DATA_G_FLOAT_POINT_EN {
- DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_FALSE = 0x0,
- DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_TRUE = 0x1,
-} DCP_DC_LUT_DATA_G_FLOAT_POINT_EN;
-typedef enum DCP_DC_LUT_DATA_G_FORMAT {
- DCP_DC_LUT_DATA_G_FORMAT_U0P10 = 0x0,
- DCP_DC_LUT_DATA_G_FORMAT_S1P10 = 0x1,
- DCP_DC_LUT_DATA_G_FORMAT_U1P11 = 0x2,
- DCP_DC_LUT_DATA_G_FORMAT_U0P12 = 0x3,
-} DCP_DC_LUT_DATA_G_FORMAT;
-typedef enum DCP_DC_LUT_INC_R {
- DCP_DC_LUT_INC_R_NA = 0x0,
- DCP_DC_LUT_INC_R_2 = 0x1,
- DCP_DC_LUT_INC_R_4 = 0x2,
- DCP_DC_LUT_INC_R_8 = 0x3,
- DCP_DC_LUT_INC_R_16 = 0x4,
- DCP_DC_LUT_INC_R_32 = 0x5,
- DCP_DC_LUT_INC_R_64 = 0x6,
- DCP_DC_LUT_INC_R_128 = 0x7,
- DCP_DC_LUT_INC_R_256 = 0x8,
- DCP_DC_LUT_INC_R_512 = 0x9,
-} DCP_DC_LUT_INC_R;
-typedef enum DCP_DC_LUT_DATA_R_SIGNED_EN {
- DCP_DC_LUT_DATA_R_SIGNED_EN_FALSE = 0x0,
- DCP_DC_LUT_DATA_R_SIGNED_EN_TRUE = 0x1,
-} DCP_DC_LUT_DATA_R_SIGNED_EN;
-typedef enum DCP_DC_LUT_DATA_R_FLOAT_POINT_EN {
- DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_FALSE = 0x0,
- DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_TRUE = 0x1,
-} DCP_DC_LUT_DATA_R_FLOAT_POINT_EN;
-typedef enum DCP_DC_LUT_DATA_R_FORMAT {
- DCP_DC_LUT_DATA_R_FORMAT_U0P10 = 0x0,
- DCP_DC_LUT_DATA_R_FORMAT_S1P10 = 0x1,
- DCP_DC_LUT_DATA_R_FORMAT_U1P11 = 0x2,
- DCP_DC_LUT_DATA_R_FORMAT_U0P12 = 0x3,
-} DCP_DC_LUT_DATA_R_FORMAT;
-typedef enum DCP_CRC_ENABLE {
- DCP_CRC_ENABLE_FALSE = 0x0,
- DCP_CRC_ENABLE_TRUE = 0x1,
-} DCP_CRC_ENABLE;
-typedef enum DCP_CRC_SOURCE_SEL {
- DCP_CRC_SOURCE_SEL_OUTPUT_PIX = 0x0,
- DCP_CRC_SOURCE_SEL_INPUT_L32 = 0x1,
- DCP_CRC_SOURCE_SEL_INPUT_H32 = 0x2,
- DCP_CRC_SOURCE_SEL_OUTPUT_CNTL = 0x4,
-} DCP_CRC_SOURCE_SEL;
-typedef enum DCP_CRC_LINE_SEL {
- DCP_CRC_LINE_SEL_RESERVED = 0x0,
- DCP_CRC_LINE_SEL_EVEN = 0x1,
- DCP_CRC_LINE_SEL_ODD = 0x2,
- DCP_CRC_LINE_SEL_BOTH = 0x3,
-} DCP_CRC_LINE_SEL;
-typedef enum DCP_GRPH_FLIP_RATE {
- DCP_GRPH_FLIP_RATE_1FRAME = 0x0,
- DCP_GRPH_FLIP_RATE_2FRAME = 0x1,
- DCP_GRPH_FLIP_RATE_3FRAME = 0x2,
- DCP_GRPH_FLIP_RATE_4FRAME = 0x3,
- DCP_GRPH_FLIP_RATE_5FRAME = 0x4,
- DCP_GRPH_FLIP_RATE_6FRAME = 0x5,
- DCP_GRPH_FLIP_RATE_7FRAME = 0x6,
- DCP_GRPH_FLIP_RATE_8FRAME = 0x7,
-} DCP_GRPH_FLIP_RATE;
-typedef enum DCP_GRPH_FLIP_RATE_ENABLE {
- DCP_GRPH_FLIP_RATE_ENABLE_FALSE = 0x0,
- DCP_GRPH_FLIP_RATE_ENABLE_TRUE = 0x1,
-} DCP_GRPH_FLIP_RATE_ENABLE;
-typedef enum DCP_GSL0_EN {
- DCP_GSL0_EN_FALSE = 0x0,
- DCP_GSL0_EN_TRUE = 0x1,
-} DCP_GSL0_EN;
-typedef enum DCP_GSL1_EN {
- DCP_GSL1_EN_FALSE = 0x0,
- DCP_GSL1_EN_TRUE = 0x1,
-} DCP_GSL1_EN;
-typedef enum DCP_GSL2_EN {
- DCP_GSL2_EN_FALSE = 0x0,
- DCP_GSL2_EN_TRUE = 0x1,
-} DCP_GSL2_EN;
-typedef enum DCP_GSL_MASTER_EN {
- DCP_GSL_MASTER_EN_FALSE = 0x0,
- DCP_GSL_MASTER_EN_TRUE = 0x1,
-} DCP_GSL_MASTER_EN;
-typedef enum DCP_GSL_XDMA_GROUP {
- DCP_GSL_XDMA_GROUP_VSYNC = 0x0,
- DCP_GSL_XDMA_GROUP_HSYNC0 = 0x1,
- DCP_GSL_XDMA_GROUP_HSYNC1 = 0x2,
- DCP_GSL_XDMA_GROUP_HSYNC2 = 0x3,
-} DCP_GSL_XDMA_GROUP;
-typedef enum DCP_GSL_XDMA_GROUP_UNDERFLOW_EN {
- DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_FALSE = 0x0,
- DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_TRUE = 0x1,
-} DCP_GSL_XDMA_GROUP_UNDERFLOW_EN;
-typedef enum DCP_GSL_SYNC_SOURCE {
- DCP_GSL_SYNC_SOURCE_FLIP = 0x0,
- DCP_GSL_SYNC_SOURCE_PHASE0 = 0x1,
- DCP_GSL_SYNC_SOURCE_RESET = 0x2,
- DCP_GSL_SYNC_SOURCE_PHASE1 = 0x3,
-} DCP_GSL_SYNC_SOURCE;
-typedef enum DCP_GSL_DELAY_SURFACE_UPDATE_PENDING {
- DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_FALSE = 0x0,
- DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_TRUE = 0x1,
-} DCP_GSL_DELAY_SURFACE_UPDATE_PENDING;
-typedef enum DCP_TEST_DEBUG_WRITE_EN {
- DCP_TEST_DEBUG_WRITE_EN_FALSE = 0x0,
- DCP_TEST_DEBUG_WRITE_EN_TRUE = 0x1,
-} DCP_TEST_DEBUG_WRITE_EN;
-typedef enum DCP_GRPH_STEREOSYNC_FLIP_EN {
- DCP_GRPH_STEREOSYNC_FLIP_EN_FALSE = 0x0,
- DCP_GRPH_STEREOSYNC_FLIP_EN_TRUE = 0x1,
-} DCP_GRPH_STEREOSYNC_FLIP_EN;
-typedef enum DCP_GRPH_STEREOSYNC_FLIP_MODE {
- DCP_GRPH_STEREOSYNC_FLIP_MODE_FLIP = 0x0,
- DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE0 = 0x1,
- DCP_GRPH_STEREOSYNC_FLIP_MODE_RESET = 0x2,
- DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE1 = 0x3,
-} DCP_GRPH_STEREOSYNC_FLIP_MODE;
-typedef enum DCP_GRPH_STEREOSYNC_SELECT_DISABLE {
- DCP_GRPH_STEREOSYNC_SELECT_DISABLE_FALSE = 0x0,
- DCP_GRPH_STEREOSYNC_SELECT_DISABLE_TRUE = 0x1,
-} DCP_GRPH_STEREOSYNC_SELECT_DISABLE;
-typedef enum DCP_GRPH_ROTATION_ANGLE {
- DCP_GRPH_ROTATION_ANGLE_0 = 0x0,
- DCP_GRPH_ROTATION_ANGLE_90 = 0x1,
- DCP_GRPH_ROTATION_ANGLE_180 = 0x2,
- DCP_GRPH_ROTATION_ANGLE_270 = 0x3,
-} DCP_GRPH_ROTATION_ANGLE;
-typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN {
- DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_FALSE = 0x0,
- DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_TRUE = 0x1,
-} DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN;
-typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE {
- DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_NUM = 0x0,
- DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_ENABLE= 0x1,
-} DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE;
-typedef enum DCP_GRPH_REGAMMA_MODE {
- DCP_GRPH_REGAMMA_MODE_BYPASS = 0x0,
- DCP_GRPH_REGAMMA_MODE_SRGB = 0x1,
- DCP_GRPH_REGAMMA_MODE_XVYCC = 0x2,
- DCP_GRPH_REGAMMA_MODE_PROGA = 0x3,
- DCP_GRPH_REGAMMA_MODE_PROGB = 0x4,
-} DCP_GRPH_REGAMMA_MODE;
-typedef enum DCP_ALPHA_ROUND_TRUNC_MODE {
- DCP_ALPHA_ROUND_TRUNC_MODE_ROUND = 0x0,
- DCP_ALPHA_ROUND_TRUNC_MODE_TRUNC = 0x1,
-} DCP_ALPHA_ROUND_TRUNC_MODE;
-typedef enum DCP_CURSOR_ALPHA_BLND_ENA {
- DCP_CURSOR_ALPHA_BLND_ENA_FALSE = 0x0,
- DCP_CURSOR_ALPHA_BLND_ENA_TRUE = 0x1,
-} DCP_CURSOR_ALPHA_BLND_ENA;
-typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK {
- DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_FALSE = 0x0,
- DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_TRUE = 0x1,
-} DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK;
-typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK {
- DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_FALSE = 0x0,
- DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_TRUE = 0x1,
-} DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK;
-typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK {
- DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_FALSE = 0x0,
- DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_TRUE = 0x1,
-} DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK;
-typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK {
- DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_FALSE = 0x0,
- DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_TRUE = 0x1,
-} DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK;
-typedef enum DCP_GRPH_SURFACE_COUNTER_EN {
- DCP_GRPH_SURFACE_COUNTER_EN_DISABLE = 0x0,
- DCP_GRPH_SURFACE_COUNTER_EN_ENABLE = 0x1,
-} DCP_GRPH_SURFACE_COUNTER_EN;
-typedef enum DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT {
- DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_0 = 0x0,
- DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_1 = 0x1,
- DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_2 = 0x2,
- DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_3 = 0x3,
- DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_4 = 0x4,
- DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_5 = 0x5,
- DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_6 = 0x6,
- DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_7 = 0x7,
- DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_8 = 0x8,
- DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_9 = 0x9,
- DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_10 = 0xa,
- DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_11 = 0xb,
-} DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT;
-typedef enum DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED {
- DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_NO = 0x0,
- DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_YES = 0x1,
-} DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED;
-typedef enum HDMI_KEEPOUT_MODE {
- HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0x0,
- HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 0x1,
-} HDMI_KEEPOUT_MODE;
-typedef enum HDMI_CLOCK_CHANNEL_RATE {
- HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0x0,
- HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 0x1,
-} HDMI_CLOCK_CHANNEL_RATE;
-typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED {
- HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0x0,
- HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 0x1,
-} HDMI_NO_EXTRA_NULL_PACKET_FILLED;
-typedef enum HDMI_PACKET_GEN_VERSION {
- HDMI_PACKET_GEN_VERSION_OLD = 0x0,
- HDMI_PACKET_GEN_VERSION_NEW = 0x1,
-} HDMI_PACKET_GEN_VERSION;
-typedef enum HDMI_ERROR_ACK {
- HDMI_ERROR_ACK_INT = 0x0,
- HDMI_ERROR_NOT_ACK = 0x1,
-} HDMI_ERROR_ACK;
-typedef enum HDMI_ERROR_MASK {
- HDMI_ERROR_MASK_INT = 0x0,
- HDMI_ERROR_NOT_MASK = 0x1,
-} HDMI_ERROR_MASK;
-typedef enum HDMI_DEEP_COLOR_DEPTH {
- HDMI_DEEP_COLOR_DEPTH_24BPP = 0x0,
- HDMI_DEEP_COLOR_DEPTH_30BPP = 0x1,
- HDMI_DEEP_COLOR_DEPTH_36BPP = 0x2,
- HDMI_DEEP_COLOR_DEPTH_RESERVED = 0x3,
-} HDMI_DEEP_COLOR_DEPTH;
-typedef enum HDMI_AUDIO_DELAY_EN {
- HDMI_AUDIO_DELAY_DISABLE = 0x0,
- HDMI_AUDIO_DELAY_58CLK = 0x1,
- HDMI_AUDIO_DELAY_56CLK = 0x2,
- HDMI_AUDIO_DELAY_RESERVED = 0x3,
-} HDMI_AUDIO_DELAY_EN;
-typedef enum HDMI_AUDIO_SEND_MAX_PACKETS {
- HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0x0,
- HDMI_SEND_MAX_AUDIO_PACKETS = 0x1,
-} HDMI_AUDIO_SEND_MAX_PACKETS;
-typedef enum HDMI_ACR_SEND {
- HDMI_ACR_NOT_SEND = 0x0,
- HDMI_ACR_PKT_SEND = 0x1,
-} HDMI_ACR_SEND;
-typedef enum HDMI_ACR_CONT {
- HDMI_ACR_CONT_DISABLE = 0x0,
- HDMI_ACR_CONT_ENABLE = 0x1,
-} HDMI_ACR_CONT;
-typedef enum HDMI_ACR_SELECT {
- HDMI_ACR_SELECT_HW = 0x0,
- HDMI_ACR_SELECT_32K = 0x1,
- HDMI_ACR_SELECT_44K = 0x2,
- HDMI_ACR_SELECT_48K = 0x3,
-} HDMI_ACR_SELECT;
-typedef enum HDMI_ACR_SOURCE {
- HDMI_ACR_SOURCE_HW = 0x0,
- HDMI_ACR_SOURCE_SW = 0x1,
-} HDMI_ACR_SOURCE;
-typedef enum HDMI_ACR_N_MULTIPLE {
- HDMI_ACR_0_MULTIPLE_RESERVED = 0x0,
- HDMI_ACR_1_MULTIPLE = 0x1,
- HDMI_ACR_2_MULTIPLE = 0x2,
- HDMI_ACR_3_MULTIPLE_RESERVED = 0x3,
- HDMI_ACR_4_MULTIPLE = 0x4,
- HDMI_ACR_5_MULTIPLE_RESERVED = 0x5,
- HDMI_ACR_6_MULTIPLE_RESERVED = 0x6,
- HDMI_ACR_7_MULTIPLE_RESERVED = 0x7,
-} HDMI_ACR_N_MULTIPLE;
-typedef enum HDMI_ACR_AUDIO_PRIORITY {
- HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0x0,
- HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 0x1,
-} HDMI_ACR_AUDIO_PRIORITY;
-typedef enum HDMI_NULL_SEND {
- HDMI_NULL_NOT_SEND = 0x0,
- HDMI_NULL_PKT_SEND = 0x1,
-} HDMI_NULL_SEND;
-typedef enum HDMI_GC_SEND {
- HDMI_GC_NOT_SEND = 0x0,
- HDMI_GC_PKT_SEND = 0x1,
-} HDMI_GC_SEND;
-typedef enum HDMI_GC_CONT {
- HDMI_GC_CONT_DISABLE = 0x0,
- HDMI_GC_CONT_ENABLE = 0x1,
-} HDMI_GC_CONT;
-typedef enum HDMI_ISRC_SEND {
- HDMI_ISRC_NOT_SEND = 0x0,
- HDMI_ISRC_PKT_SEND = 0x1,
-} HDMI_ISRC_SEND;
-typedef enum HDMI_ISRC_CONT {
- HDMI_ISRC_CONT_DISABLE = 0x0,
- HDMI_ISRC_CONT_ENABLE = 0x1,
-} HDMI_ISRC_CONT;
-typedef enum HDMI_AVI_INFO_SEND {
- HDMI_AVI_INFO_NOT_SEND = 0x0,
- HDMI_AVI_INFO_PKT_SEND = 0x1,
-} HDMI_AVI_INFO_SEND;
-typedef enum HDMI_AVI_INFO_CONT {
- HDMI_AVI_INFO_CONT_DISABLE = 0x0,
- HDMI_AVI_INFO_CONT_ENABLE = 0x1,
-} HDMI_AVI_INFO_CONT;
-typedef enum HDMI_AUDIO_INFO_SEND {
- HDMI_AUDIO_INFO_NOT_SEND = 0x0,
- HDMI_AUDIO_INFO_PKT_SEND = 0x1,
-} HDMI_AUDIO_INFO_SEND;
-typedef enum HDMI_AUDIO_INFO_CONT {
- HDMI_AUDIO_INFO_CONT_DISABLE = 0x0,
- HDMI_AUDIO_INFO_CONT_ENABLE = 0x1,
-} HDMI_AUDIO_INFO_CONT;
-typedef enum HDMI_MPEG_INFO_SEND {
- HDMI_MPEG_INFO_NOT_SEND = 0x0,
- HDMI_MPEG_INFO_PKT_SEND = 0x1,
-} HDMI_MPEG_INFO_SEND;
-typedef enum HDMI_MPEG_INFO_CONT {
- HDMI_MPEG_INFO_CONT_DISABLE = 0x0,
- HDMI_MPEG_INFO_CONT_ENABLE = 0x1,
-} HDMI_MPEG_INFO_CONT;
-typedef enum HDMI_GENERIC0_SEND {
- HDMI_GENERIC0_NOT_SEND = 0x0,
- HDMI_GENERIC0_PKT_SEND = 0x1,
-} HDMI_GENERIC0_SEND;
-typedef enum HDMI_GENERIC0_CONT {
- HDMI_GENERIC0_CONT_DISABLE = 0x0,
- HDMI_GENERIC0_CONT_ENABLE = 0x1,
-} HDMI_GENERIC0_CONT;
-typedef enum HDMI_GENERIC1_SEND {
- HDMI_GENERIC1_NOT_SEND = 0x0,
- HDMI_GENERIC1_PKT_SEND = 0x1,
-} HDMI_GENERIC1_SEND;
-typedef enum HDMI_GENERIC1_CONT {
- HDMI_GENERIC1_CONT_DISABLE = 0x0,
- HDMI_GENERIC1_CONT_ENABLE = 0x1,
-} HDMI_GENERIC1_CONT;
-typedef enum HDMI_GC_AVMUTE_CONT {
- HDMI_GC_AVMUTE_CONT_DISABLE = 0x0,
- HDMI_GC_AVMUTE_CONT_ENABLE = 0x1,
-} HDMI_GC_AVMUTE_CONT;
-typedef enum HDMI_PACKING_PHASE_OVERRIDE {
- HDMI_PACKING_PHASE_SET_BY_HW = 0x0,
- HDMI_PACKING_PHASE_SET_BY_SW = 0x1,
-} HDMI_PACKING_PHASE_OVERRIDE;
-typedef enum HDMI_GENERIC2_SEND {
- HDMI_GENERIC2_NOT_SEND = 0x0,
- HDMI_GENERIC2_PKT_SEND = 0x1,
-} HDMI_GENERIC2_SEND;
-typedef enum HDMI_GENERIC2_CONT {
- HDMI_GENERIC2_CONT_DISABLE = 0x0,
- HDMI_GENERIC2_CONT_ENABLE = 0x1,
-} HDMI_GENERIC2_CONT;
-typedef enum HDMI_GENERIC3_SEND {
- HDMI_GENERIC3_NOT_SEND = 0x0,
- HDMI_GENERIC3_PKT_SEND = 0x1,
-} HDMI_GENERIC3_SEND;
-typedef enum HDMI_GENERIC3_CONT {
- HDMI_GENERIC3_CONT_DISABLE = 0x0,
- HDMI_GENERIC3_CONT_ENABLE = 0x1,
-} HDMI_GENERIC3_CONT;
-typedef enum TMDS_PIXEL_ENCODING {
- TMDS_PIXEL_ENCODING_444_OR_420 = 0x0,
- TMDS_PIXEL_ENCODING_422 = 0x1,
-} TMDS_PIXEL_ENCODING;
-typedef enum TMDS_COLOR_FORMAT {
- TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP= 0x0,
- TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 0x1,
- TMDS_COLOR_FORMAT_DUAL30BPP = 0x2,
- TMDS_COLOR_FORMAT_RESERVED = 0x3,
-} TMDS_COLOR_FORMAT;
-typedef enum TMDS_STEREOSYNC_CTL_SEL_REG {
- TMDS_STEREOSYNC_CTL0 = 0x0,
- TMDS_STEREOSYNC_CTL1 = 0x1,
- TMDS_STEREOSYNC_CTL2 = 0x2,
- TMDS_STEREOSYNC_CTL3 = 0x3,
-} TMDS_STEREOSYNC_CTL_SEL_REG;
-typedef enum TMDS_CTL0_DATA_SEL {
- TMDS_CTL0_DATA_SEL0_RESERVED = 0x0,
- TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 0x1,
- TMDS_CTL0_DATA_SEL2_VSYNC = 0x2,
- TMDS_CTL0_DATA_SEL3_RESERVED = 0x3,
- TMDS_CTL0_DATA_SEL4_HSYNC = 0x4,
- TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 0x5,
- TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 0x6,
- TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 0x7,
-} TMDS_CTL0_DATA_SEL;
-typedef enum TMDS_CTL0_DATA_INVERT {
- TMDS_CTL0_DATA_NORMAL = 0x0,
- TMDS_CTL0_DATA_INVERT_EN = 0x1,
-} TMDS_CTL0_DATA_INVERT;
-typedef enum TMDS_CTL0_DATA_MODULATION {
- TMDS_CTL0_DATA_MODULATION_DISABLE = 0x0,
- TMDS_CTL0_DATA_MODULATION_BIT0 = 0x1,
- TMDS_CTL0_DATA_MODULATION_BIT1 = 0x2,
- TMDS_CTL0_DATA_MODULATION_BIT2 = 0x3,
-} TMDS_CTL0_DATA_MODULATION;
-typedef enum TMDS_CTL0_PATTERN_OUT_EN {
- TMDS_CTL0_PATTERN_OUT_DISABLE = 0x0,
- TMDS_CTL0_PATTERN_OUT_ENABLE = 0x1,
-} TMDS_CTL0_PATTERN_OUT_EN;
-typedef enum TMDS_CTL1_DATA_SEL {
- TMDS_CTL1_DATA_SEL0_RESERVED = 0x0,
- TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 0x1,
- TMDS_CTL1_DATA_SEL2_VSYNC = 0x2,
- TMDS_CTL1_DATA_SEL3_RESERVED = 0x3,
- TMDS_CTL1_DATA_SEL4_HSYNC = 0x4,
- TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 0x5,
- TMDS_CTL1_DATA_SEL8_BLANK_TIME = 0x6,
- TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 0x7,
-} TMDS_CTL1_DATA_SEL;
-typedef enum TMDS_CTL1_DATA_INVERT {
- TMDS_CTL1_DATA_NORMAL = 0x0,
- TMDS_CTL1_DATA_INVERT_EN = 0x1,
-} TMDS_CTL1_DATA_INVERT;
-typedef enum TMDS_CTL1_DATA_MODULATION {
- TMDS_CTL1_DATA_MODULATION_DISABLE = 0x0,
- TMDS_CTL1_DATA_MODULATION_BIT0 = 0x1,
- TMDS_CTL1_DATA_MODULATION_BIT1 = 0x2,
- TMDS_CTL1_DATA_MODULATION_BIT2 = 0x3,
-} TMDS_CTL1_DATA_MODULATION;
-typedef enum TMDS_CTL1_PATTERN_OUT_EN {
- TMDS_CTL1_PATTERN_OUT_DISABLE = 0x0,
- TMDS_CTL1_PATTERN_OUT_ENABLE = 0x1,
-} TMDS_CTL1_PATTERN_OUT_EN;
-typedef enum TMDS_CTL2_DATA_SEL {
- TMDS_CTL2_DATA_SEL0_RESERVED = 0x0,
- TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 0x1,
- TMDS_CTL2_DATA_SEL2_VSYNC = 0x2,
- TMDS_CTL2_DATA_SEL3_RESERVED = 0x3,
- TMDS_CTL2_DATA_SEL4_HSYNC = 0x4,
- TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 0x5,
- TMDS_CTL2_DATA_SEL8_BLANK_TIME = 0x6,
- TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 0x7,
-} TMDS_CTL2_DATA_SEL;
-typedef enum TMDS_CTL2_DATA_INVERT {
- TMDS_CTL2_DATA_NORMAL = 0x0,
- TMDS_CTL2_DATA_INVERT_EN = 0x1,
-} TMDS_CTL2_DATA_INVERT;
-typedef enum TMDS_CTL2_DATA_MODULATION {
- TMDS_CTL2_DATA_MODULATION_DISABLE = 0x0,
- TMDS_CTL2_DATA_MODULATION_BIT0 = 0x1,
- TMDS_CTL2_DATA_MODULATION_BIT1 = 0x2,
- TMDS_CTL2_DATA_MODULATION_BIT2 = 0x3,
-} TMDS_CTL2_DATA_MODULATION;
-typedef enum TMDS_CTL2_PATTERN_OUT_EN {
- TMDS_CTL2_PATTERN_OUT_DISABLE = 0x0,
- TMDS_CTL2_PATTERN_OUT_ENABLE = 0x1,
-} TMDS_CTL2_PATTERN_OUT_EN;
-typedef enum TMDS_CTL3_DATA_INVERT {
- TMDS_CTL3_DATA_NORMAL = 0x0,
- TMDS_CTL3_DATA_INVERT_EN = 0x1,
-} TMDS_CTL3_DATA_INVERT;
-typedef enum TMDS_CTL3_DATA_MODULATION {
- TMDS_CTL3_DATA_MODULATION_DISABLE = 0x0,
- TMDS_CTL3_DATA_MODULATION_BIT0 = 0x1,
- TMDS_CTL3_DATA_MODULATION_BIT1 = 0x2,
- TMDS_CTL3_DATA_MODULATION_BIT2 = 0x3,
-} TMDS_CTL3_DATA_MODULATION;
-typedef enum TMDS_CTL3_PATTERN_OUT_EN {
- TMDS_CTL3_PATTERN_OUT_DISABLE = 0x0,
- TMDS_CTL3_PATTERN_OUT_ENABLE = 0x1,
-} TMDS_CTL3_PATTERN_OUT_EN;
-typedef enum TMDS_CTL3_DATA_SEL {
- TMDS_CTL3_DATA_SEL0_RESERVED = 0x0,
- TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 0x1,
- TMDS_CTL3_DATA_SEL2_VSYNC = 0x2,
- TMDS_CTL3_DATA_SEL3_RESERVED = 0x3,
- TMDS_CTL3_DATA_SEL4_HSYNC = 0x4,
- TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 0x5,
- TMDS_CTL3_DATA_SEL8_BLANK_TIME = 0x6,
- TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 0x7,
-} TMDS_CTL3_DATA_SEL;
-typedef enum DIG_FE_CNTL_SOURCE_SELECT {
- DIG_FE_SOURCE_FROM_FMT0 = 0x0,
- DIG_FE_SOURCE_FROM_FMT1 = 0x1,
- DIG_FE_SOURCE_FROM_FMT2 = 0x2,
- DIG_FE_SOURCE_FROM_FMT3 = 0x3,
- DIG_FE_SOURCE_FROM_FMT4 = 0x4,
- DIG_FE_SOURCE_FROM_FMT5 = 0x5,
-} DIG_FE_CNTL_SOURCE_SELECT;
-typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT {
- DIG_FE_STEREOSYNC_FROM_FMT0 = 0x0,
- DIG_FE_STEREOSYNC_FROM_FMT1 = 0x1,
- DIG_FE_STEREOSYNC_FROM_FMT2 = 0x2,
- DIG_FE_STEREOSYNC_FROM_FMT3 = 0x3,
- DIG_FE_STEREOSYNC_FROM_FMT4 = 0x4,
- DIG_FE_STEREOSYNC_FROM_FMT5 = 0x5,
-} DIG_FE_CNTL_STEREOSYNC_SELECT;
-typedef enum DIG_FIFO_READ_CLOCK_SRC {
- DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0x0,
- DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 0x1,
-} DIG_FIFO_READ_CLOCK_SRC;
-typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL {
- DIG_OUTPUT_CRC_ON_LINK0 = 0x0,
- DIG_OUTPUT_CRC_ON_LINK1 = 0x1,
-} DIG_OUTPUT_CRC_CNTL_LINK_SEL;
-typedef enum DIG_OUTPUT_CRC_DATA_SEL {
- DIG_OUTPUT_CRC_FOR_FULLFRAME = 0x0,
- DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 0x1,
- DIG_OUTPUT_CRC_FOR_VBI = 0x2,
- DIG_OUTPUT_CRC_FOR_AUDIO = 0x3,
-} DIG_OUTPUT_CRC_DATA_SEL;
-typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN {
- DIG_IN_NORMAL_OPERATION = 0x0,
- DIG_IN_DEBUG_MODE = 0x1,
-} DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN;
-typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL {
- DIG_10BIT_TEST_PATTERN = 0x0,
- DIG_ALTERNATING_TEST_PATTERN = 0x1,
-} DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL;
-typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN {
- DIG_TEST_PATTERN_NORMAL = 0x0,
- DIG_TEST_PATTERN_RANDOM = 0x1,
-} DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN;
-typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET {
- DIG_RANDOM_PATTERN_ENABLED = 0x0,
- DIG_RANDOM_PATTERN_RESETED = 0x1,
-} DIG_TEST_PATTERN_RANDOM_PATTERN_RESET;
-typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN {
- DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0x0,
- DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 0x1,
-} DIG_TEST_PATTERN_EXTERNAL_RESET_EN;
-typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT {
- DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0x0,
- DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 0x1,
-} DIG_RANDOM_PATTERN_SEED_RAN_PAT;
-typedef enum DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL {
- DIG_FIFO_USE_OVERWRITE_LEVEL = 0x0,
- DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 0x1,
-} DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL;
-typedef enum DIG_FIFO_ERROR_ACK {
- DIG_FIFO_ERROR_ACK_INT = 0x0,
- DIG_FIFO_ERROR_NOT_ACK = 0x1,
-} DIG_FIFO_ERROR_ACK;
-typedef enum DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE {
- DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0x0,
- DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 0x1,
-} DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE;
-typedef enum DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX {
- DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0x0,
- DIG_FIFO_FORCE_RECOMP_MINMAX = 0x1,
-} DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX;
-typedef enum DIG_DISPCLK_SWITCH_CNTL_SWITCH_POINT {
- DIG_DISPCLK_SWITCH_AT_EARLY_VBLANK = 0x0,
- DIG_DISPCLK_SWITCH_AT_FIRST_HSYNC = 0x1,
-} DIG_DISPCLK_SWITCH_CNTL_SWITCH_POINT;
-typedef enum DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK {
- DIG_DISPCLK_SWITCH_ALLOWED_ACK_INT = 0x0,
- DIG_DISPCLK_SWITCH_ALLOWED_INT_NOT_ACK = 0x1,
-} DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK;
-typedef enum DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK {
- DIG_DISPCLK_SWITCH_ALLOWED_MASK_INT = 0x0,
- DIG_DISPCLK_SWITCH_ALLOWED_INT_UNMASK = 0x1,
-} DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK;
-typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK {
- AFMT_INTERRUPT_DISABLE = 0x0,
- AFMT_INTERRUPT_ENABLE = 0x1,
-} AFMT_INTERRUPT_STATUS_CHG_MASK;
-typedef enum HDMI_GC_AVMUTE {
- HDMI_GC_AVMUTE_SET = 0x0,
- HDMI_GC_AVMUTE_UNSET = 0x1,
-} HDMI_GC_AVMUTE;
-typedef enum HDMI_DEFAULT_PAHSE {
- HDMI_DEFAULT_PHASE_IS_0 = 0x0,
- HDMI_DEFAULT_PHASE_IS_1 = 0x1,
-} HDMI_DEFAULT_PAHSE;
-typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD {
- AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS= 0x0,
- AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 0x1,
-} AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD;
-typedef enum AUDIO_LAYOUT_SELECT {
- AUDIO_LAYOUT_0 = 0x0,
- AUDIO_LAYOUT_1 = 0x1,
-} AUDIO_LAYOUT_SELECT;
-typedef enum AFMT_AUDIO_CRC_CONTROL_CONT {
- AFMT_AUDIO_CRC_ONESHOT = 0x0,
- AFMT_AUDIO_CRC_AUTO_RESTART = 0x1,
-} AFMT_AUDIO_CRC_CONTROL_CONT;
-typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE {
- AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0x0,
- AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 0x1,
-} AFMT_AUDIO_CRC_CONTROL_SOURCE;
-typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL {
- AFMT_AUDIO_CRC_CH0_SIG = 0x0,
- AFMT_AUDIO_CRC_CH1_SIG = 0x1,
- AFMT_AUDIO_CRC_CH2_SIG = 0x2,
- AFMT_AUDIO_CRC_CH3_SIG = 0x3,
- AFMT_AUDIO_CRC_CH4_SIG = 0x4,
- AFMT_AUDIO_CRC_CH5_SIG = 0x5,
- AFMT_AUDIO_CRC_CH6_SIG = 0x6,
- AFMT_AUDIO_CRC_CH7_SIG = 0x7,
- AFMT_AUDIO_CRC_RESERVED = 0x8,
- AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 0x9,
-} AFMT_AUDIO_CRC_CONTROL_CH_SEL;
-typedef enum AFMT_RAMP_CONTROL0_SIGN {
- AFMT_RAMP_SIGNED = 0x0,
- AFMT_RAMP_UNSIGNED = 0x1,
-} AFMT_RAMP_CONTROL0_SIGN;
-typedef enum AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND {
- AFMT_AUDIO_PACKET_SENT_DISABLED = 0x0,
- AFMT_AUDIO_PACKET_SENT_ENABLED = 0x1,
-} AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND;
-typedef enum AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS {
- AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED= 0x0,
- AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 0x1,
-} AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS;
-typedef enum AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE {
- AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK = 0x0,
- AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 0x1,
-} AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE;
-typedef enum AFMT_AUDIO_SRC_CONTROL_SELECT {
- AFMT_AUDIO_SRC_FROM_AZ_STREAM0 = 0x0,
- AFMT_AUDIO_SRC_FROM_AZ_STREAM1 = 0x1,
- AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 0x2,
- AFMT_AUDIO_SRC_FROM_AZ_STREAM3 = 0x3,
- AFMT_AUDIO_SRC_FROM_AZ_STREAM4 = 0x4,
- AFMT_AUDIO_SRC_FROM_AZ_STREAM5 = 0x5,
- AFMT_AUDIO_SRC_RESERVED = 0x6,
-} AFMT_AUDIO_SRC_CONTROL_SELECT;
-typedef enum DIG_BE_CNTL_MODE {
- DIG_BE_DP_SST_MODE = 0x0,
- DIG_BE_RESERVED1 = 0x1,
- DIG_BE_TMDS_DVI_MODE = 0x2,
- DIG_BE_TMDS_HDMI_MODE = 0x3,
- DIG_BE_SDVO_RESERVED = 0x4,
- DIG_BE_DP_MST_MODE = 0x5,
- DIG_BE_RESERVED2 = 0x6,
- DIG_BE_RESERVED3 = 0x7,
-} DIG_BE_CNTL_MODE;
-typedef enum DIG_BE_CNTL_HPD_SELECT {
- DIG_BE_CNTL_HPD1 = 0x0,
- DIG_BE_CNTL_HPD2 = 0x1,
- DIG_BE_CNTL_HPD3 = 0x2,
- DIG_BE_CNTL_HPD4 = 0x3,
- DIG_BE_CNTL_HPD5 = 0x4,
- DIG_BE_CNTL_HPD6 = 0x5,
-} DIG_BE_CNTL_HPD_SELECT;
-typedef enum LVTMA_RANDOM_PATTERN_SEED_RAN_PAT {
- LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS = 0x0,
- LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH = 0x1,
-} LVTMA_RANDOM_PATTERN_SEED_RAN_PAT;
-typedef enum TMDS_SYNC_PHASE {
- TMDS_NOT_SYNC_PHASE_ON_FRAME_START = 0x0,
- TMDS_SYNC_PHASE_ON_FRAME_START = 0x1,
-} TMDS_SYNC_PHASE;
-typedef enum TMDS_DATA_SYNCHRONIZATION_DSINTSEL {
- TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0x0,
- TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 0x1,
-} TMDS_DATA_SYNCHRONIZATION_DSINTSEL;
-typedef enum TMDS_TRANSMITTER_ENABLE_HPD_MASK {
- TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE = 0x0,
- TMDS_TRANSMITTER_HPD_MASK_OVERRIDE = 0x1,
-} TMDS_TRANSMITTER_ENABLE_HPD_MASK;
-typedef enum TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK {
- TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0x0,
- TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 0x1,
-} TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK;
-typedef enum TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK {
- TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0x0,
- TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 0x1,
-} TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK;
-typedef enum TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK {
- TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0x0,
- TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON= 0x1,
- TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 0x2,
- TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 0x3,
-} TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK;
-typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELA {
- TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK = 0x0,
- TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK = 0x1,
-} TMDS_TRANSMITTER_CONTROL_IDSCKSELA;
-typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELB {
- TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK = 0x0,
- TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK = 0x1,
-} TMDS_TRANSMITTER_CONTROL_IDSCKSELB;
-typedef enum TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN {
- TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE = 0x0,
- TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE = 0x1,
-} TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN;
-typedef enum TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK {
- TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD = 0x0,
- TMDS_TRANSMITTER_PLL_RST_ON_HPD = 0x1,
-} TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK;
-typedef enum TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS {
- TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK = 0x0,
- TMDS_TRANSMITTER_TMCLK_FROM_PADS = 0x1,
-} TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS;
-typedef enum TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS {
- TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK = 0x0,
- TMDS_TRANSMITTER_TDCLK_FROM_PADS = 0x1,
-} TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS;
-typedef enum TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN {
- TMDS_TRANSMITTER_PLLSEL_BY_HW = 0x0,
- TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW = 0x1,
-} TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN;
-typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA {
- TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT = 0x0,
- TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT = 0x1,
-} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA;
-typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB {
- TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT = 0x0,
- TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT = 0x1,
-} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB;
-typedef enum TMDS_REG_TEST_OUTPUTA_CNTLA {
- TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0 = 0x0,
- TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1 = 0x1,
- TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 0x2,
- TMDS_REG_TEST_OUTPUTA_CNTLA_NA = 0x3,
-} TMDS_REG_TEST_OUTPUTA_CNTLA;
-typedef enum TMDS_REG_TEST_OUTPUTB_CNTLB {
- TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0 = 0x0,
- TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1 = 0x1,
- TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 0x2,
- TMDS_REG_TEST_OUTPUTB_CNTLB_NA = 0x3,
-} TMDS_REG_TEST_OUTPUTB_CNTLB;
-typedef enum DP_LINK_TRAINING_COMPLETE {
- DP_LINK_TRAINING_NOT_COMPLETE = 0x0,
- DP_LINK_TRAINING_ALREADY_COMPLETE = 0x1,
-} DP_LINK_TRAINING_COMPLETE;
-typedef enum DP_EMBEDDED_PANEL_MODE {
- DP_EXTERNAL_PANEL = 0x0,
- DP_EMBEDDED_PANEL = 0x1,
-} DP_EMBEDDED_PANEL_MODE;
-typedef enum DP_PIXEL_ENCODING {
- DP_PIXEL_ENCODING_RGB444 = 0x0,
- DP_PIXEL_ENCODING_YCBCR422 = 0x1,
- DP_PIXEL_ENCODING_YCBCR444 = 0x2,
- DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 0x3,
- DP_PIXEL_ENCODING_Y_ONLY = 0x4,
- DP_PIXEL_ENCODING_YCBCR420 = 0x5,
- DP_PIXEL_ENCODING_RESERVED = 0x6,
-} DP_PIXEL_ENCODING;
-typedef enum DP_DYN_RANGE {
- DP_DYN_VESA_RANGE = 0x0,
- DP_DYN_CEA_RANGE = 0x1,
-} DP_DYN_RANGE;
-typedef enum DP_YCBCR_RANGE {
- DP_YCBCR_RANGE_BT601_5 = 0x0,
- DP_YCBCR_RANGE_BT709_5 = 0x1,
-} DP_YCBCR_RANGE;
-typedef enum DP_COMPONENT_DEPTH {
- DP_COMPONENT_DEPTH_6BPC = 0x0,
- DP_COMPONENT_DEPTH_8BPC = 0x1,
- DP_COMPONENT_DEPTH_10BPC = 0x2,
- DP_COMPONENT_DEPTH_12BPC = 0x3,
- DP_COMPONENT_DEPTH_16BPC = 0x4,
- DP_COMPONENT_DEPTH_RESERVED = 0x5,
-} DP_COMPONENT_DEPTH;
-typedef enum DP_MSA_MISC0_OVERRIDE_ENABLE {
- MSA_MISC0_OVERRIDE_DISABLE = 0x0,
- MSA_MISC0_OVERRIDE_ENABLE = 0x1,
-} DP_MSA_MISC0_OVERRIDE_ENABLE;
-typedef enum DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE {
- MSA_MISC1_BIT7_OVERRIDE_DISABLE = 0x0,
- MSA_MISC1_BIT7_OVERRIDE_ENABLE = 0x1,
-} DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE;
-typedef enum DP_UDI_LANES {
- DP_UDI_1_LANE = 0x0,
- DP_UDI_2_LANES = 0x1,
- DP_UDI_LANES_RESERVED = 0x2,
- DP_UDI_4_LANES = 0x3,
-} DP_UDI_LANES;
-typedef enum DP_VID_STREAM_DIS_DEFER {
- DP_VID_STREAM_DIS_NO_DEFER = 0x0,
- DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 0x1,
- DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 0x2,
-} DP_VID_STREAM_DIS_DEFER;
-typedef enum DP_STEER_OVERFLOW_ACK {
- DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0x0,
- DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 0x1,
-} DP_STEER_OVERFLOW_ACK;
-typedef enum DP_STEER_OVERFLOW_MASK {
- DP_STEER_OVERFLOW_MASKED = 0x0,
- DP_STEER_OVERFLOW_UNMASK = 0x1,
-} DP_STEER_OVERFLOW_MASK;
-typedef enum DP_TU_OVERFLOW_ACK {
- DP_TU_OVERFLOW_ACK_NO_EFFECT = 0x0,
- DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 0x1,
-} DP_TU_OVERFLOW_ACK;
-typedef enum DP_VID_TIMING_MODE {
- DP_VID_TIMING_MODE_ASYNC = 0x0,
- DP_VID_TIMING_MODE_SYNC = 0x1,
-} DP_VID_TIMING_MODE;
-typedef enum DP_VID_M_N_DOUBLE_BUFFER_MODE {
- DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0x0,
- DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 0x1,
-} DP_VID_M_N_DOUBLE_BUFFER_MODE;
-typedef enum DP_VID_M_N_GEN_EN {
- DP_VID_M_N_PROGRAMMED_VIA_REG = 0x0,
- DP_VID_M_N_CALC_AUTO = 0x1,
-} DP_VID_M_N_GEN_EN;
-typedef enum DP_VID_M_DOUBLE_VALUE_EN {
- DP_VID_M_INPUT_PIXEL_RATE = 0x0,
- DP_VID_M_DOUBLE_INPUT_PIXEL_RATE = 0x1,
-} DP_VID_M_DOUBLE_VALUE_EN;
-typedef enum DP_VID_ENHANCED_FRAME_MODE {
- VID_NORMAL_FRAME_MODE = 0x0,
- VID_ENHANCED_MODE = 0x1,
-} DP_VID_ENHANCED_FRAME_MODE;
-typedef enum DP_VID_MSA_TOP_FIELD_MODE {
- DP_TOP_FIELD_ONLY = 0x0,
- DP_TOP_PLUS_BOTTOM_FIELD = 0x1,
-} DP_VID_MSA_TOP_FIELD_MODE;
-typedef enum DP_VID_VBID_FIELD_POL {
- DP_VID_VBID_FIELD_POL_NORMAL = 0x0,
- DP_VID_VBID_FIELD_POL_INV = 0x1,
-} DP_VID_VBID_FIELD_POL;
-typedef enum DP_VID_STREAM_DISABLE_ACK {
- ID_STREAM_DISABLE_NO_ACK = 0x0,
- ID_STREAM_DISABLE_ACKED = 0x1,
-} DP_VID_STREAM_DISABLE_ACK;
-typedef enum DP_VID_STREAM_DISABLE_MASK {
- VID_STREAM_DISABLE_MASKED = 0x0,
- VID_STREAM_DISABLE_UNMASK = 0x1,
-} DP_VID_STREAM_DISABLE_MASK;
-typedef enum DPHY_ATEST_SEL_LANE0 {
- DPHY_ATEST_LANE0_PRBS_PATTERN = 0x0,
- DPHY_ATEST_LANE0_REG_PATTERN = 0x1,
-} DPHY_ATEST_SEL_LANE0;
-typedef enum DPHY_ATEST_SEL_LANE1 {
- DPHY_ATEST_LANE1_PRBS_PATTERN = 0x0,
- DPHY_ATEST_LANE1_REG_PATTERN = 0x1,
-} DPHY_ATEST_SEL_LANE1;
-typedef enum DPHY_ATEST_SEL_LANE2 {
- DPHY_ATEST_LANE2_PRBS_PATTERN = 0x0,
- DPHY_ATEST_LANE2_REG_PATTERN = 0x1,
-} DPHY_ATEST_SEL_LANE2;
-typedef enum DPHY_ATEST_SEL_LANE3 {
- DPHY_ATEST_LANE3_PRBS_PATTERN = 0x0,
- DPHY_ATEST_LANE3_REG_PATTERN = 0x1,
-} DPHY_ATEST_SEL_LANE3;
-typedef enum DPHY_BYPASS {
- DPHY_8B10B_OUTPUT = 0x0,
- DPHY_DBG_OUTPUT = 0x1,
-} DPHY_BYPASS;
-typedef enum DPHY_SKEW_BYPASS {
- DPHY_WITH_SKEW = 0x0,
- DPHY_NO_SKEW = 0x1,
-} DPHY_SKEW_BYPASS;
-typedef enum DPHY_TRAINING_PATTERN_SEL {
- DPHY_TRAINING_PATTERN_1 = 0x0,
- DPHY_TRAINING_PATTERN_2 = 0x1,
- DPHY_TRAINING_PATTERN_3 = 0x2,
- DPHY_TRAINING_PATTERN_4 = 0x3,
-} DPHY_TRAINING_PATTERN_SEL;
-typedef enum DPHY_8B10B_RESET {
- DPHY_8B10B_NOT_RESET = 0x0,
- DPHY_8B10B_RESETET = 0x1,
-} DPHY_8B10B_RESET;
-typedef enum DP_DPHY_8B10B_EXT_DISP {
- DP_DPHY_8B10B_EXT_DISP_ZERO = 0x0,
- DP_DPHY_8B10B_EXT_DISP_ONE = 0x1,
-} DP_DPHY_8B10B_EXT_DISP;
-typedef enum DPHY_8B10B_CUR_DISP {
- DPHY_8B10B_CUR_DISP_ZERO = 0x0,
- DPHY_8B10B_CUR_DISP_ONE = 0x1,
-} DPHY_8B10B_CUR_DISP;
-typedef enum DPHY_PRBS_EN {
- DPHY_PRBS_DISABLE = 0x0,
- DPHY_PRBS_ENABLE = 0x1,
-} DPHY_PRBS_EN;
-typedef enum DPHY_PRBS_SEL {
- DPHY_PRBS7_SELECTED = 0x0,
- DPHY_PRBS23_SELECTED = 0x1,
- DPHY_PRBS11_SELECTED = 0x2,
-} DPHY_PRBS_SEL;
-typedef enum DPHY_LOAD_BS_COUNT_START {
- DPHY_LOAD_BS_COUNT_STARTED = 0x0,
- DPHY_LOAD_BS_COUNT_NOT_STARTED = 0x1,
-} DPHY_LOAD_BS_COUNT_START;
-typedef enum DPHY_CRC_EN {
- DPHY_CRC_DISABLED = 0x0,
- DPHY_CRC_ENABLED = 0x1,
-} DPHY_CRC_EN;
-typedef enum DPHY_CRC_CONT_EN {
- DPHY_CRC_ONE_SHOT = 0x0,
- DPHY_CRC_CONTINUOUS = 0x1,
-} DPHY_CRC_CONT_EN;
-typedef enum DPHY_CRC_FIELD {
- DPHY_CRC_START_FROM_TOP_FIELD = 0x0,
- DPHY_CRC_START_FROM_BOTTOM_FIELD = 0x1,
-} DPHY_CRC_FIELD;
-typedef enum DPHY_CRC_SEL {
- DPHY_CRC_LANE0_SELECTED = 0x0,
- DPHY_CRC_LANE1_SELECTED = 0x1,
- DPHY_CRC_LANE2_SELECTED = 0x2,
- DPHY_CRC_LANE3_SELECTED = 0x3,
-} DPHY_CRC_SEL;
-typedef enum DPHY_RX_FAST_TRAINING_CAPABLE {
- DPHY_FAST_TRAINING_NOT_CAPABLE_0 = 0x0,
- DPHY_FAST_TRAINING_CAPABLE = 0x1,
-} DPHY_RX_FAST_TRAINING_CAPABLE;
-typedef enum DP_SEC_COLLISION_ACK {
- DP_SEC_COLLISION_ACK_NO_EFFECT = 0x0,
- DP_SEC_COLLISION_ACK_CLR_FLAG = 0x1,
-} DP_SEC_COLLISION_ACK;
-typedef enum DP_SEC_AUDIO_MUTE {
- DP_SEC_AUDIO_MUTE_HW_CTRL = 0x0,
- DP_SEC_AUDIO_MUTE_SW_CTRL = 0x1,
-} DP_SEC_AUDIO_MUTE;
-typedef enum DP_SEC_TIMESTAMP_MODE {
- DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE = 0x0,
- DP_SEC_TIMESTAMP_AUTO_CALC_MODE = 0x1,
-} DP_SEC_TIMESTAMP_MODE;
-typedef enum DP_SEC_ASP_PRIORITY {
- DP_SEC_ASP_LOW_PRIORITY = 0x0,
- DP_SEC_ASP_HIGH_PRIORITY = 0x1,
-} DP_SEC_ASP_PRIORITY;
-typedef enum DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE {
- DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ = 0x0,
- DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 0x1,
-} DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE;
-typedef enum DP_MSE_SAT_UPDATE_ACT {
- DP_MSE_SAT_UPDATE_NO_ACTION = 0x0,
- DP_MSE_SAT_UPDATE_WITH_TRIGGER = 0x1,
- DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER = 0x2,
-} DP_MSE_SAT_UPDATE_ACT;
-typedef enum DP_MSE_LINK_LINE {
- DP_MSE_LINK_LINE_32_MTP_LONG = 0x0,
- DP_MSE_LINK_LINE_64_MTP_LONG = 0x1,
- DP_MSE_LINK_LINE_128_MTP_LONG = 0x2,
- DP_MSE_LINK_LINE_256_MTP_LONG = 0x3,
-} DP_MSE_LINK_LINE;
-typedef enum DP_MSE_BLANK_CODE {
- DP_MSE_BLANK_CODE_SF_FILLED = 0x0,
- DP_MSE_BLANK_CODE_ZERO_FILLED = 0x1,
-} DP_MSE_BLANK_CODE;
-typedef enum DP_MSE_TIMESTAMP_MODE {
- DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0x0,
- DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE = 0x1,
-} DP_MSE_TIMESTAMP_MODE;
-typedef enum DP_MSE_ZERO_ENCODER {
- DP_MSE_NOT_ZERO_FE_ENCODER = 0x0,
- DP_MSE_ZERO_FE_ENCODER = 0x1,
-} DP_MSE_ZERO_ENCODER;
-typedef enum DP_MSE_OUTPUT_DPDBG_DATA {
- DP_MSE_OUTPUT_DPDBG_DATA_DIS = 0x0,
- DP_MSE_OUTPUT_DPDBG_DATA_EN = 0x1,
-} DP_MSE_OUTPUT_DPDBG_DATA;
-typedef enum DP_DPHY_HBR2_PATTERN_CONTROL_MODE {
- DP_DPHY_HBR2_PASS_THROUGH = 0x0,
- DP_DPHY_HBR2_PATTERN_1 = 0x1,
- DP_DPHY_HBR2_PATTERN_2_NEG = 0x2,
- DP_DPHY_HBR2_PATTERN_3 = 0x3,
- DP_DPHY_HBR2_PATTERN_2_POS = 0x6,
-} DP_DPHY_HBR2_PATTERN_CONTROL_MODE;
-typedef enum DPHY_CRC_MST_PHASE_ERROR_ACK {
- DPHY_CRC_MST_PHASE_ERROR_NO_ACK = 0x0,
- DPHY_CRC_MST_PHASE_ERROR_ACKED = 0x1,
-} DPHY_CRC_MST_PHASE_ERROR_ACK;
-typedef enum DPHY_SW_FAST_TRAINING_START {
- DPHY_SW_FAST_TRAINING_NOT_STARTED = 0x0,
- DPHY_SW_FAST_TRAINING_STARTED = 0x1,
-} DPHY_SW_FAST_TRAINING_START;
-typedef enum DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN {
- DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED= 0x0,
- DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 0x1,
-} DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN;
-typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_MASK {
- DP_DPHY_FAST_TRAINING_COMPLETE_MASKED = 0x0,
- DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 0x1,
-} DP_DPHY_FAST_TRAINING_COMPLETE_MASK;
-typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_ACK {
- DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0x0,
- DP_DPHY_FAST_TRAINING_COMPLETE_ACKED = 0x1,
-} DP_DPHY_FAST_TRAINING_COMPLETE_ACK;
-typedef enum DP_MSA_V_TIMING_OVERRIDE_EN {
- MSA_V_TIMING_OVERRIDE_DISABLED = 0x0,
- MSA_V_TIMING_OVERRIDE_ENABLED = 0x1,
-} DP_MSA_V_TIMING_OVERRIDE_EN;
-typedef enum DP_SEC_GSP0_PRIORITY {
- SEC_GSP0_PRIORITY_LOW = 0x0,
- SEC_GSP0_PRIORITY_HIGH = 0x1,
-} DP_SEC_GSP0_PRIORITY;
-typedef enum DP_SEC_GSP0_SEND {
- NOT_SENT = 0x0,
- FORCE_SENT = 0x1,
-} DP_SEC_GSP0_SEND;
-typedef enum DP_AUX_CONTROL_HPD_SEL {
- DP_AUX_CONTROL_HPD1_SELECTED = 0x0,
- DP_AUX_CONTROL_HPD2_SELECTED = 0x1,
- DP_AUX_CONTROL_HPD3_SELECTED = 0x2,
- DP_AUX_CONTROL_HPD4_SELECTED = 0x3,
- DP_AUX_CONTROL_HPD5_SELECTED = 0x4,
- DP_AUX_CONTROL_HPD6_SELECTED = 0x5,
-} DP_AUX_CONTROL_HPD_SEL;
-typedef enum DP_AUX_CONTROL_TEST_MODE {
- DP_AUX_CONTROL_TEST_MODE_DISABLE = 0x0,
- DP_AUX_CONTROL_TEST_MODE_ENABLE = 0x1,
-} DP_AUX_CONTROL_TEST_MODE;
-typedef enum DP_AUX_SW_CONTROL_SW_GO {
- DP_AUX_SW_CONTROL_SW__NOT_GO = 0x0,
- DP_AUX_SW_CONTROL_SW__GO = 0x1,
-} DP_AUX_SW_CONTROL_SW_GO;
-typedef enum DP_AUX_SW_CONTROL_LS_READ_TRIG {
- DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG = 0x0,
- DP_AUX_SW_CONTROL_LS_READ__TRIG = 0x1,
-} DP_AUX_SW_CONTROL_LS_READ_TRIG;
-typedef enum DP_AUX_ARB_CONTROL_ARB_PRIORITY {
- DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0x0,
- DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 0x1,
- DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 0x2,
- DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 0x3,
-} DP_AUX_ARB_CONTROL_ARB_PRIORITY;
-typedef enum DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ {
- DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ = 0x0,
- DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ = 0x1,
-} DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ;
-typedef enum DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG {
- DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0x0,
- DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG = 0x1,
-} DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG;
-typedef enum DP_AUX_INT_ACK {
- DP_AUX_INT__NOT_ACK = 0x0,
- DP_AUX_INT__ACK = 0x1,
-} DP_AUX_INT_ACK;
-typedef enum DP_AUX_LS_UPDATE_ACK {
- DP_AUX_INT_LS_UPDATE_NOT_ACK = 0x0,
- DP_AUX_INT_LS_UPDATE_ACK = 0x1,
-} DP_AUX_LS_UPDATE_ACK;
-typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL {
- DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK= 0x0,
- DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF= 0x1,
-} DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL;
-typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE {
- DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0x0,
- DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 0x1,
- DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 0x2,
- DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 0x3,
-} DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE;
-typedef enum DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN {
- DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__0US = 0x0,
- DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__8US = 0x1,
- DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__16US = 0x2,
- DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__24US = 0x3,
- DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__32US = 0x4,
- DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__40US = 0x5,
- DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__48US = 0x6,
- DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__56US = 0x7,
-} DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN;
-typedef enum DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY {
- DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0x0,
- DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US= 0x1,
- DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US= 0x2,
- DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US= 0x3,
- DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US= 0x4,
- DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US= 0x5,
-} DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY;
-typedef enum DP_AUX_DPHY_RX_CONTROL_START_WINDOW {
- DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0x0,
- DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 0x1,
- DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 0x2,
- DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD= 0x3,
- DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD= 0x4,
- DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD= 0x5,
- DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD= 0x6,
- DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD= 0x7,
-} DP_AUX_DPHY_RX_CONTROL_START_WINDOW;
-typedef enum DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW {
- DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD= 0x0,
- DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD= 0x1,
- DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD= 0x2,
- DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD= 0x3,
- DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD= 0x4,
- DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD= 0x5,
- DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD= 0x6,
- DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD= 0x7,
-} DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW;
-typedef enum DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN {
- DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES= 0x0,
- DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES= 0x1,
- DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES= 0x2,
- DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED= 0x3,
-} DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN;
-typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT {
- DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT= 0x0,
- DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT= 0x1,
-} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT;
-typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START {
- DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START= 0x0,
- DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START= 0x1,
-} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START;
-typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP {
- DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP= 0x0,
- DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP= 0x1,
-} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP;
-typedef enum DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN {
- DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS= 0x0,
- DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS= 0x1,
- DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS= 0x2,
- DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS= 0x3,
-} DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN;
-typedef enum DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN {
- DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_450US = 0x0,
- DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_500US = 0x1,
- DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_550US = 0x2,
- DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_600US = 0x3,
- DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_650US = 0x4,
- DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_700US = 0x5,
- DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_750US = 0x6,
- DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_800US = 0x7,
-} DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN;
-typedef enum DP_AUX_DPHY_RX_DETECTION_THRESHOLD {
- DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0x0,
- DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 0x1,
- DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 0x2,
- DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 0x3,
- DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 0x4,
- DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 0x5,
- DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 0x6,
- DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 0x7,
-} DP_AUX_DPHY_RX_DETECTION_THRESHOLD;
-typedef enum DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ {
- DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX= 0x0,
- DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX= 0x1,
-} DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ;
-typedef enum DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW {
- DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US= 0x0,
- DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US= 0x1,
- DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US= 0x2,
- DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US= 0x3,
-} DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW;
-typedef enum DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT {
- DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS= 0x0,
- DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS= 0x1,
- DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS= 0x2,
- DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED= 0x3,
-} DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT;
-typedef enum DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN {
- DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0= 0x0,
- DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64= 0x1,
- DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128= 0x2,
- DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256= 0x3,
-} DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN;
-typedef enum DP_AUX_ERR_OCCURRED_ACK {
- DP_AUX_ERR_OCCURRED__NOT_ACK = 0x0,
- DP_AUX_ERR_OCCURRED__ACK = 0x1,
-} DP_AUX_ERR_OCCURRED_ACK;
-typedef enum DP_AUX_POTENTIAL_ERR_REACHED_ACK {
- DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK = 0x0,
- DP_AUX_POTENTIAL_ERR_REACHED__ACK = 0x1,
-} DP_AUX_POTENTIAL_ERR_REACHED_ACK;
-typedef enum DP_AUX_DEFINITE_ERR_REACHED_ACK {
- ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0x0,
- ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK = 0x1,
-} DP_AUX_DEFINITE_ERR_REACHED_ACK;
-typedef enum DP_AUX_RESET {
- DP_AUX_RESET_DEASSERTED = 0x0,
- DP_AUX_RESET_ASSERTED = 0x1,
-} DP_AUX_RESET;
-typedef enum DP_AUX_RESET_DONE {
- DP_AUX_RESET_SEQUENCE_NOT_DONE = 0x0,
- DP_AUX_RESET_SEQUENCE_DONE = 0x1,
-} DP_AUX_RESET_DONE;
-typedef enum FBC_IDLE_MASK_MASK_BITS {
- FBC_IDLE_MASK_DISP_REG_UPDATE = 0x0,
- FBC_IDLE_MASK_RESERVED1 = 0x1,
- FBC_IDLE_MASK_FBC_GRPH_COMP_EN = 0x2,
- FBC_IDLE_MASK_FBC_MIN_COMPRESSION = 0x3,
- FBC_IDLE_MASK_FBC_ALPHA_COMP_EN = 0x4,
- FBC_IDLE_MASK_FBC_ZERO_ALPHA_CHUNK_SKIP_EN = 0x5,
- FBC_IDLE_MASK_FBC_FORCE_COPY_TO_COMP_BUF = 0x6,
- FBC_IDLE_MASK_RESERVED7 = 0x7,
- FBC_IDLE_MASK_RESERVED8 = 0x8,
- FBC_IDLE_MASK_RESERVED9 = 0x9,
- FBC_IDLE_MASK_RESERVED10 = 0xa,
- FBC_IDLE_MASK_RESERVED11 = 0xb,
- FBC_IDLE_MASK_RESERVED12 = 0xc,
- FBC_IDLE_MASK_RESERVED13 = 0xd,
- FBC_IDLE_MASK_RESERVED14 = 0xe,
- FBC_IDLE_MASK_RESERVED15 = 0xf,
- FBC_IDLE_MASK_RESERVED16 = 0x10,
- FBC_IDLE_MASK_RESERVED17 = 0x11,
- FBC_IDLE_MASK_RESERVED18 = 0x12,
- FBC_IDLE_MASK_RESERVED19 = 0x13,
- FBC_IDLE_MASK_RESERVED20 = 0x14,
- FBC_IDLE_MASK_RESERVED21 = 0x15,
- FBC_IDLE_MASK_RESERVED22 = 0x16,
- FBC_IDLE_MASK_RESERVED23 = 0x17,
- FBC_IDLE_MASK_MC_HIT_REGION_0 = 0x18,
- FBC_IDLE_MASK_MC_HIT_REGION_1 = 0x19,
- FBC_IDLE_MASK_MC_HIT_REGION_2 = 0x1a,
- FBC_IDLE_MASK_MC_HIT_REGION_3 = 0x1b,
- FBC_IDLE_MASK_MC_WRITE = 0x1c,
- FBC_IDLE_MASK_CG_STATIC_SCREEN = 0x1d,
- FBC_IDLE_MASK_RESERVED30 = 0x1e,
- FBC_IDLE_MASK_RESERVED31 = 0x1f,
-} FBC_IDLE_MASK_MASK_BITS;
-typedef enum FMT_CONTROL_PIXEL_ENCODING {
- FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0x0,
- FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 0x1,
- FMT_CONTROL_PIXEL_ENCODING_YCBCR420 = 0x2,
- FMT_CONTROL_PIXEL_ENCODING_RESERVED = 0x3,
-} FMT_CONTROL_PIXEL_ENCODING;
-typedef enum FMT_CONTROL_SUBSAMPLING_MODE {
- FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0x0,
- FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 0x1,
- FMT_CONTROL_SUBSAMPLING_MODE_3_TAP = 0x2,
- FMT_CONTROL_SUBSAMPLING_MODE_RESERVED = 0x3,
-} FMT_CONTROL_SUBSAMPLING_MODE;
-typedef enum FMT_CONTROL_SUBSAMPLING_ORDER {
- FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0x0,
- FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 0x1,
-} FMT_CONTROL_SUBSAMPLING_ORDER;
-typedef enum FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS {
- FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE = 0x0,
- FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE = 0x1,
-} FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS;
-typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE {
- FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0x0,
- FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 0x1,
-} FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE;
-typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH {
- FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0x0,
- FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 0x1,
- FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 0x2,
-} FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH;
-typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH {
- FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0x0,
- FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 0x1,
- FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 0x2,
-} FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH;
-typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH {
- FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP= 0x0,
- FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP= 0x1,
- FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP= 0x2,
-} FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH;
-typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL {
- FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0x0,
- FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 0x1,
-} FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL;
-typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL {
- FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0x0,
- FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 0x1,
- FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 0x2,
- FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 0x3,
-} FMT_BIT_DEPTH_CONTROL_25FRC_SEL;
-typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL {
- FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0x0,
- FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 0x1,
- FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 0x2,
- FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 0x3,
-} FMT_BIT_DEPTH_CONTROL_50FRC_SEL;
-typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL {
- FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0x0,
- FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 0x1,
- FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 0x2,
- FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 0x3,
-} FMT_BIT_DEPTH_CONTROL_75FRC_SEL;
-typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT {
- FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_LEGACY_HARDCODED_PATTERN= 0x0,
- FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_PROGRAMMABLE_PATTERN= 0x1,
-} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT;
-typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 {
- FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR= 0x0,
- FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB= 0x1,
-} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0;
-typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT {
- FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0x0,
- FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 0x1,
- FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 0x2,
- FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC = 0x3,
- FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 0x4,
- FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 0x5,
- FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 0x6,
- FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 0x7,
-} FMT_CLAMP_CNTL_COLOR_FORMAT;
-typedef enum FMT_CRC_CNTL_CONT_EN {
- FMT_CRC_CNTL_CONT_EN_ONE_SHOT = 0x0,
- FMT_CRC_CNTL_CONT_EN_CONT = 0x1,
-} FMT_CRC_CNTL_CONT_EN;
-typedef enum FMT_CRC_CNTL_INCLUDE_OVERSCAN {
- FMT_CRC_CNTL_INCLUDE_OVERSCAN_NOT_INCLUDE = 0x0,
- FMT_CRC_CNTL_INCLUDE_OVERSCAN_INCLUDE = 0x1,
-} FMT_CRC_CNTL_INCLUDE_OVERSCAN;
-typedef enum FMT_CRC_CNTL_ONLY_BLANKB {
- FMT_CRC_CNTL_ONLY_BLANKB_ENTIRE_FIELD = 0x0,
- FMT_CRC_CNTL_ONLY_BLANKB_NON_BLANK = 0x1,
-} FMT_CRC_CNTL_ONLY_BLANKB;
-typedef enum FMT_CRC_CNTL_PSR_MODE_ENABLE {
- FMT_CRC_CNTL_PSR_MODE_ENABLE_NORMAL = 0x0,
- FMT_CRC_CNTL_PSR_MODE_ENABLE_EDP_PSR_CRC = 0x1,
-} FMT_CRC_CNTL_PSR_MODE_ENABLE;
-typedef enum FMT_CRC_CNTL_INTERLACE_MODE {
- FMT_CRC_CNTL_INTERLACE_MODE_TOP = 0x0,
- FMT_CRC_CNTL_INTERLACE_MODE_BOTTOM = 0x1,
- FMT_CRC_CNTL_INTERLACE_MODE_BOTH_BOTTOM = 0x2,
- FMT_CRC_CNTL_INTERLACE_MODE_BOTH_EACH = 0x3,
-} FMT_CRC_CNTL_INTERLACE_MODE;
-typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE {
- FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ALL = 0x0,
- FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ODD_EVEN = 0x1,
-} FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE;
-typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT {
- FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_EVEN = 0x0,
- FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_ODD = 0x1,
-} FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT;
-typedef enum FMT_DEBUG_CNTL_COLOR_SELECT {
- FMT_DEBUG_CNTL_COLOR_SELECT_BLUE = 0x0,
- FMT_DEBUG_CNTL_COLOR_SELECT_GREEN = 0x1,
- FMT_DEBUG_CNTL_COLOR_SELECT_RED1 = 0x2,
- FMT_DEBUG_CNTL_COLOR_SELECT_RED2 = 0x3,
-} FMT_DEBUG_CNTL_COLOR_SELECT;
-typedef enum FMT_SPATIAL_DITHER_MODE {
- FMT_SPATIAL_DITHER_MODE_0 = 0x0,
- FMT_SPATIAL_DITHER_MODE_1 = 0x1,
- FMT_SPATIAL_DITHER_MODE_2 = 0x2,
- FMT_SPATIAL_DITHER_MODE_3 = 0x3,
-} FMT_SPATIAL_DITHER_MODE;
-typedef enum FMT_STEREOSYNC_OVR_POL {
- FMT_STEREOSYNC_OVR_POL_INVERTED = 0x0,
- FMT_STEREOSYNC_OVR_POL_NOT_INVERTED = 0x1,
-} FMT_STEREOSYNC_OVR_POL;
-typedef enum FMT_DYNAMIC_EXP_MODE {
- FMT_DYNAMIC_EXP_MODE_10to12 = 0x0,
- FMT_DYNAMIC_EXP_MODE_8to12 = 0x1,
-} FMT_DYNAMIC_EXP_MODE;
-typedef enum LB_DATA_FORMAT_PIXEL_DEPTH {
- LB_DATA_FORMAT_PIXEL_DEPTH_30BPP = 0x0,
- LB_DATA_FORMAT_PIXEL_DEPTH_24BPP = 0x1,
- LB_DATA_FORMAT_PIXEL_DEPTH_18BPP = 0x2,
- LB_DATA_FORMAT_PIXEL_DEPTH_36BPP = 0x3,
-} LB_DATA_FORMAT_PIXEL_DEPTH;
-typedef enum LB_DATA_FORMAT_PIXEL_EXPAN_MODE {
- LB_DATA_FORMAT_PIXEL_EXPAN_MODE_ZERO_PIXEL_EXPANSION= 0x0,
- LB_DATA_FORMAT_PIXEL_EXPAN_MODE_DYNAMIC_PIXEL_EXPANSION= 0x1,
-} LB_DATA_FORMAT_PIXEL_EXPAN_MODE;
-typedef enum LB_DATA_FORMAT_PIXEL_REDUCE_MODE {
- LB_DATA_FORMAT_PIXEL_REDUCE_MODE_TRUNCATION = 0x0,
- LB_DATA_FORMAT_PIXEL_REDUCE_MODE_ROUNDING = 0x1,
-} LB_DATA_FORMAT_PIXEL_REDUCE_MODE;
-typedef enum LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH {
- LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_36BPP = 0x0,
- LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_30BPP = 0x1,
-} LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH;
-typedef enum LB_DATA_FORMAT_INTERLEAVE_EN {
- LB_DATA_FORMAT_INTERLEAVE_DISABLE = 0x0,
- LB_DATA_FORMAT_INTERLEAVE_ENABLE = 0x1,
-} LB_DATA_FORMAT_INTERLEAVE_EN;
-typedef enum LB_DATA_FORMAT_PREFILL_EN {
- LB_DATA_FORMAT_PREFILL_DISABLE = 0x0,
- LB_DATA_FORMAT_PREFILL_ENABLE = 0x1,
-} LB_DATA_FORMAT_PREFILL_EN;
-typedef enum LB_DATA_FORMAT_REQUEST_MODE {
- LB_DATA_FORMAT_REQUEST_MODE_NORMAL = 0x0,
- LB_DATA_FORMAT_REQUEST_MODE_START_OF_LINE = 0x1,
-} LB_DATA_FORMAT_REQUEST_MODE;
-typedef enum LB_DATA_FORMAT_ALPHA_EN {
- LB_DATA_FORMAT_ALPHA_DISABLE = 0x0,
- LB_DATA_FORMAT_ALPHA_ENABLE = 0x1,
-} LB_DATA_FORMAT_ALPHA_EN;
-typedef enum LB_VLINE_START_END_VLINE_INV {
- LB_VLINE_START_END_VLINE_NORMAL = 0x0,
- LB_VLINE_START_END_VLINE_INVERSE = 0x1,
-} LB_VLINE_START_END_VLINE_INV;
-typedef enum LB_VLINE2_START_END_VLINE2_INV {
- LB_VLINE2_START_END_VLINE2_NORMAL = 0x0,
- LB_VLINE2_START_END_VLINE2_INVERSE = 0x1,
-} LB_VLINE2_START_END_VLINE2_INV;
-typedef enum LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK {
- LB_INTERRUPT_MASK_VBLANK_INTERRUPT_DISABLE = 0x0,
- LB_INTERRUPT_MASK_VBLANK_INTERRUPT_ENABLE = 0x1,
-} LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK;
-typedef enum LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK {
- LB_INTERRUPT_MASK_VLINE_INTERRUPT_DISABLE = 0x0,
- LB_INTERRUPT_MASK_VLINE_INTERRUPT_ENABLE = 0x1,
-} LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK;
-typedef enum LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK {
- LB_INTERRUPT_MASK_VLINE2_INTERRUPT_DISABLE = 0x0,
- LB_INTERRUPT_MASK_VLINE2_INTERRUPT_ENABLE = 0x1,
-} LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK;
-typedef enum LB_VLINE_STATUS_VLINE_ACK {
- LB_VLINE_STATUS_VLINE_NORMAL = 0x0,
- LB_VLINE_STATUS_VLINE_CLEAR = 0x1,
-} LB_VLINE_STATUS_VLINE_ACK;
-typedef enum LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE {
- LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_LEVEL_BASED = 0x0,
- LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_PULSE_BASED = 0x1,
-} LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE;
-typedef enum LB_VLINE2_STATUS_VLINE2_ACK {
- LB_VLINE2_STATUS_VLINE2_NORMAL = 0x0,
- LB_VLINE2_STATUS_VLINE2_CLEAR = 0x1,
-} LB_VLINE2_STATUS_VLINE2_ACK;
-typedef enum LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE {
- LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_LEVEL_BASED= 0x0,
- LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_PULSE_BASED= 0x1,
-} LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE;
-typedef enum LB_VBLANK_STATUS_VBLANK_ACK {
- LB_VBLANK_STATUS_VBLANK_NORMAL = 0x0,
- LB_VBLANK_STATUS_VBLANK_CLEAR = 0x1,
-} LB_VBLANK_STATUS_VBLANK_ACK;
-typedef enum LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE {
- LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_LEVEL_BASED= 0x0,
- LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_PULSE_BASED= 0x1,
-} LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE;
-typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL {
- LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_DISABLE = 0x0,
- LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK= 0x1,
- LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_POWERDOWN_RESET= 0x2,
- LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK_POWERDOWN_RESET= 0x3,
-} LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL;
-typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 {
- LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VBLANK = 0x0,
- LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VSYNC = 0x1,
-} LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2;
-typedef enum LB_SYNC_RESET_SEL_LB_SYNC_DURATION {
- LB_SYNC_RESET_SEL_LB_SYNC_DURATION_16_CLOCKS = 0x0,
- LB_SYNC_RESET_SEL_LB_SYNC_DURATION_32_CLOCKS = 0x1,
- LB_SYNC_RESET_SEL_LB_SYNC_DURATION_64_CLOCKS = 0x2,
- LB_SYNC_RESET_SEL_LB_SYNC_DURATION_128_CLOCKS = 0x3,
-} LB_SYNC_RESET_SEL_LB_SYNC_DURATION;
-typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN {
- LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_DISABLE = 0x0,
- LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_ENABLE = 0x1,
-} LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN;
-typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN {
- LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_DISABLE= 0x0,
- LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_ENABLE= 0x1,
-} LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN;
-typedef enum LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK {
- LB_BUFFER_STATUS_LB_BUFFER_EMPTY_NORMAL = 0x0,
- LB_BUFFER_STATUS_LB_BUFFER_EMPTY_RESET = 0x1,
-} LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK;
-typedef enum LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK {
- LB_BUFFER_STATUS_LB_BUFFER_FULL_NORMAL = 0x0,
- LB_BUFFER_STATUS_LB_BUFFER_FULL_RESET = 0x1,
-} LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK;
-typedef enum LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE {
- LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_REAL_FLIP = 0x2,
- LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_DUMMY_FLIP= 0x3,
-} LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE;
-typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET {
- LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_NORMAL= 0x0,
- LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACTIVE= 0x1,
-} LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET;
-typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK {
- LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED0= 0x0,
- LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED1= 0x1,
-} LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK;
-typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE {
- LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_NO_INSERT= 0x0,
- LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_DEBUG= 0x1,
- LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_HSYNC_MODE= 0x2,
-} LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE;
-typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE {
- LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_DISABLE= 0x0,
- LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_EN = 0x1,
-} LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE;
-typedef enum LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE {
- ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_MASTER= 0x1,
- ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_SLAVE= 0x2,
-} LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE;
-typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL {
- LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED0= 0x0,
- LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED1= 0x1,
-} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL;
-typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE {
- LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ONE= 0x0,
- LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ONE= 0x1,
-} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE;
-typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO {
- LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ZERO= 0x0,
- LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ZERO= 0x1,
-} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO;
-typedef enum LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN {
- LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED0= 0x0,
- LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED1= 0x1,
-} LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN;
-typedef enum LBV_PIXEL_DEPTH {
- PIXEL_DEPTH_30BPP = 0x0,
- PIXEL_DEPTH_24BPP = 0x1,
- PIXEL_DEPTH_18BPP = 0x2,
- PIXEL_DEPTH_38BPP = 0x3,
-} LBV_PIXEL_DEPTH;
-typedef enum LBV_PIXEL_EXPAN_MODE {
- PIXEL_EXPAN_MODE_ZERO_EXP = 0x0,
- PIXEL_EXPAN_MODE_DYN_EXP = 0x1,
-} LBV_PIXEL_EXPAN_MODE;
-typedef enum LBV_INTERLEAVE_EN {
- INTERLEAVE_DIS = 0x0,
- INTERLEAVE_EN = 0x1,
-} LBV_INTERLEAVE_EN;
-typedef enum LBV_PIXEL_REDUCE_MODE {
- PIXEL_REDUCE_MODE_TRUNCATION = 0x0,
- PIXEL_REDUCE_MODE_ROUNDING = 0x1,
-} LBV_PIXEL_REDUCE_MODE;
-typedef enum LBV_DYNAMIC_PIXEL_DEPTH {
- DYNAMIC_PIXEL_DEPTH_36BPP = 0x0,
- DYNAMIC_PIXEL_DEPTH_30BPP = 0x1,
-} LBV_DYNAMIC_PIXEL_DEPTH;
-typedef enum LBV_DITHER_EN {
- DITHER_DIS = 0x0,
- DITHER_EN = 0x1,
-} LBV_DITHER_EN;
-typedef enum LBV_DOWNSCALE_PREFETCH_EN {
- DOWNSCALE_PREFETCH_DIS = 0x0,
- DOWNSCALE_PREFETCH_EN = 0x1,
-} LBV_DOWNSCALE_PREFETCH_EN;
-typedef enum LBV_MEMORY_CONFIG {
- MEMORY_CONFIG_0 = 0x0,
- MEMORY_CONFIG_1 = 0x1,
- MEMORY_CONFIG_2 = 0x2,
- MEMORY_CONFIG_3 = 0x3,
-} LBV_MEMORY_CONFIG;
-typedef enum LBV_SYNC_RESET_SEL2 {
- SYNC_RESET_SEL2_VBLANK = 0x0,
- SYNC_RESET_SEL2_VSYNC = 0x1,
-} LBV_SYNC_RESET_SEL2;
-typedef enum LBV_SYNC_DURATION {
- SYNC_DURATION_16 = 0x0,
- SYNC_DURATION_32 = 0x1,
- SYNC_DURATION_64 = 0x2,
- SYNC_DURATION_128 = 0x3,
-} LBV_SYNC_DURATION;
-typedef enum SCL_C_RAM_TAP_PAIR_IDX {
- SCL_C_RAM_TAP_PAIR_ID0 = 0x0,
- SCL_C_RAM_TAP_PAIR_ID1 = 0x1,
- SCL_C_RAM_TAP_PAIR_ID2 = 0x2,
- SCL_C_RAM_TAP_PAIR_ID3 = 0x3,
- SCL_C_RAM_TAP_PAIR_ID4 = 0x4,
-} SCL_C_RAM_TAP_PAIR_IDX;
-typedef enum SCL_C_RAM_PHASE {
- SCL_C_RAM_PHASE_0 = 0x0,
- SCL_C_RAM_PHASE_1 = 0x1,
- SCL_C_RAM_PHASE_2 = 0x2,
- SCL_C_RAM_PHASE_3 = 0x3,
- SCL_C_RAM_PHASE_4 = 0x4,
- SCL_C_RAM_PHASE_5 = 0x5,
- SCL_C_RAM_PHASE_6 = 0x6,
- SCL_C_RAM_PHASE_7 = 0x7,
- SCL_C_RAM_PHASE_8 = 0x8,
-} SCL_C_RAM_PHASE;
-typedef enum SCL_C_RAM_FILTER_TYPE {
- SCL_C_RAM_FILTER_TYPE_VERT_LUMA_RGB_LUT = 0x0,
- SCL_C_RAM_FILTER_TYPE_VERT_CHROMA_LUT = 0x1,
- SCL_C_RAM_FILTER_TYPE_HORI_LUMA_RGB_LUT = 0x2,
- SCL_C_RAM_FILTER_TYPE_HORI_CHROMA_LUT = 0x3,
-} SCL_C_RAM_FILTER_TYPE;
-typedef enum SCL_MODE_SEL {
- SCL_MODE_RGB_BYPASS = 0x0,
- SCL_MODE_RGB_SCALING = 0x1,
- SCL_MODE_YCBCR_SCALING = 0x2,
- SCL_MODE_YCBCR_BYPASS = 0x3,
-} SCL_MODE_SEL;
-typedef enum SCL_PSCL_EN {
- SCL_PSCL_DISABLE = 0x0,
- SCL_PSCL_ENANBLE = 0x1,
-} SCL_PSCL_EN;
-typedef enum SCL_V_NUM_OF_TAPS {
- SCL_V_NUM_OF_TAPS_1 = 0x0,
- SCL_V_NUM_OF_TAPS_2 = 0x1,
- SCL_V_NUM_OF_TAPS_3 = 0x2,
- SCL_V_NUM_OF_TAPS_4 = 0x3,
- SCL_V_NUM_OF_TAPS_5 = 0x4,
- SCL_V_NUM_OF_TAPS_6 = 0x5,
-} SCL_V_NUM_OF_TAPS;
-typedef enum SCL_H_NUM_OF_TAPS {
- SCL_H_NUM_OF_TAPS_1 = 0x0,
- SCL_H_NUM_OF_TAPS_2 = 0x1,
- SCL_H_NUM_OF_TAPS_4 = 0x3,
- SCL_H_NUM_OF_TAPS_6 = 0x5,
- SCL_H_NUM_OF_TAPS_8 = 0x7,
- SCL_H_NUM_OF_TAPS_10 = 0x9,
-} SCL_H_NUM_OF_TAPS;
-typedef enum SCL_BOUNDARY_MODE {
- SCL_BOUNDARY_MODE_BLACK = 0x0,
- SCL_BOUNDARY_MODE_EDGE = 0x1,
-} SCL_BOUNDARY_MODE;
-typedef enum SCL_EARLY_EOL_MOD {
- SCL_EARLY_EOL_MODE_CRTC = 0x0,
- SCL_EARLY_EOL_MODE_INTERNAL = 0x1,
-} SCL_EARLY_EOL_MOD;
-typedef enum SCL_BYPASS_MODE {
- SCL_BYPASS_MODE_MC_MR = 0x0,
- SCL_BYPASS_MODE_AC_NR = 0x1,
- SCL_BYPASS_MODE_AC_AR = 0x2,
- SCL_BYPASS_MODE_RESERVED = 0x3,
-} SCL_BYPASS_MODE;
-typedef enum SCL_V_MANUAL_REPLICATE_FACTOR {
- SCL_V_MANUAL_REPLICATE_FACTOR_1 = 0x0,
- SCL_V_MANUAL_REPLICATE_FACTOR_2 = 0x1,
- SCL_V_MANUAL_REPLICATE_FACTOR_3 = 0x2,
- SCL_V_MANUAL_REPLICATE_FACTOR_4 = 0x3,
- SCL_V_MANUAL_REPLICATE_FACTOR_5 = 0x4,
- SCL_V_MANUAL_REPLICATE_FACTOR_6 = 0x5,
- SCL_V_MANUAL_REPLICATE_FACTOR_7 = 0x6,
- SCL_V_MANUAL_REPLICATE_FACTOR_8 = 0x7,
- SCL_V_MANUAL_REPLICATE_FACTOR_9 = 0x8,
- SCL_V_MANUAL_REPLICATE_FACTOR_10 = 0x9,
- SCL_V_MANUAL_REPLICATE_FACTOR_11 = 0xa,
- SCL_V_MANUAL_REPLICATE_FACTOR_12 = 0xb,
- SCL_V_MANUAL_REPLICATE_FACTOR_13 = 0xc,
- SCL_V_MANUAL_REPLICATE_FACTOR_14 = 0xd,
- SCL_V_MANUAL_REPLICATE_FACTOR_15 = 0xe,
- SCL_V_MANUAL_REPLICATE_FACTOR_16 = 0xf,
-} SCL_V_MANUAL_REPLICATE_FACTOR;
-typedef enum SCL_H_MANUAL_REPLICATE_FACTOR {
- SCL_H_MANUAL_REPLICATE_FACTOR_1 = 0x0,
- SCL_H_MANUAL_REPLICATE_FACTOR_2 = 0x1,
- SCL_H_MANUAL_REPLICATE_FACTOR_3 = 0x2,
- SCL_H_MANUAL_REPLICATE_FACTOR_4 = 0x3,
- SCL_H_MANUAL_REPLICATE_FACTOR_5 = 0x4,
- SCL_H_MANUAL_REPLICATE_FACTOR_6 = 0x5,
- SCL_H_MANUAL_REPLICATE_FACTOR_7 = 0x6,
- SCL_H_MANUAL_REPLICATE_FACTOR_8 = 0x7,
- SCL_H_MANUAL_REPLICATE_FACTOR_9 = 0x8,
- SCL_H_MANUAL_REPLICATE_FACTOR_10 = 0x9,
- SCL_H_MANUAL_REPLICATE_FACTOR_11 = 0xa,
- SCL_H_MANUAL_REPLICATE_FACTOR_12 = 0xb,
- SCL_H_MANUAL_REPLICATE_FACTOR_13 = 0xc,
- SCL_H_MANUAL_REPLICATE_FACTOR_14 = 0xd,
- SCL_H_MANUAL_REPLICATE_FACTOR_15 = 0xe,
- SCL_H_MANUAL_REPLICATE_FACTOR_16 = 0xf,
-} SCL_H_MANUAL_REPLICATE_FACTOR;
-typedef enum SCL_V_CALC_AUTO_RATIO_EN {
- SCL_V_CALC_AUTO_RATIO_DISABLE = 0x0,
- SCL_V_CALC_AUTO_RATIO_ENABLE = 0x1,
-} SCL_V_CALC_AUTO_RATIO_EN;
-typedef enum SCL_H_CALC_AUTO_RATIO_EN {
- SCL_H_CALC_AUTO_RATIO_DISABLE = 0x0,
- SCL_H_CALC_AUTO_RATIO_ENABLE = 0x1,
-} SCL_H_CALC_AUTO_RATIO_EN;
-typedef enum SCL_H_FILTER_PICK_NEAREST {
- SCL_H_FILTER_PICK_NEAREST_DISABLE = 0x0,
- SCL_H_FILTER_PICK_NEAREST_ENABLE = 0x1,
-} SCL_H_FILTER_PICK_NEAREST;
-typedef enum SCL_H_2TAP_HARDCODE_COEF_EN {
- SCL_H_2TAP_HARDCODE_COEF_DISABLE = 0x0,
- SCL_H_2TAP_HARDCODE_COEF_ENABLE = 0x1,
-} SCL_H_2TAP_HARDCODE_COEF_EN;
-typedef enum SCL_V_FILTER_PICK_NEAREST {
- SCL_V_FILTER_PICK_NEAREST_DISABLE = 0x0,
- SCL_V_FILTER_PICK_NEAREST_ENABLE = 0x1,
-} SCL_V_FILTER_PICK_NEAREST;
-typedef enum SCL_V_2TAP_HARDCODE_COEF_EN {
- SCL_V_2TAP_HARDCODE_COEF_DISABLE = 0x0,
- SCL_V_2TAP_HARDCODE_COEF_ENABLE = 0x1,
-} SCL_V_2TAP_HARDCODE_COEF_EN;
-typedef enum SCL_UPDATE_TAKEN {
- SCL_UPDATE_TAKEN_NO = 0x0,
- SCL_UPDATE_TAKEN_YES = 0x1,
-} SCL_UPDATE_TAKEN;
-typedef enum SCL_UPDATE_LOCK {
- SCL_UPDATE_UNLOCKED = 0x0,
- SCL_UPDATE_LOCKED = 0x1,
-} SCL_UPDATE_LOCK;
-typedef enum SCL_COEF_UPDATE_COMPLETE {
- SCL_COEF_UPDATE_NOT_COMPLETED = 0x0,
- SCL_COEF_UPDATE_COMPLETED = 0x1,
-} SCL_COEF_UPDATE_COMPLETE;
-typedef enum SCL_HF_SHARP_SCALE_FACTOR {
- SCL_HF_SHARP_SCALE_FACTOR_0 = 0x0,
- SCL_HF_SHARP_SCALE_FACTOR_1 = 0x1,
- SCL_HF_SHARP_SCALE_FACTOR_2 = 0x2,
- SCL_HF_SHARP_SCALE_FACTOR_3 = 0x3,
- SCL_HF_SHARP_SCALE_FACTOR_4 = 0x4,
- SCL_HF_SHARP_SCALE_FACTOR_5 = 0x5,
- SCL_HF_SHARP_SCALE_FACTOR_6 = 0x6,
- SCL_HF_SHARP_SCALE_FACTOR_7 = 0x7,
-} SCL_HF_SHARP_SCALE_FACTOR;
-typedef enum SCL_HF_SHARP_EN {
- SCL_HF_SHARP_DISABLE = 0x0,
- SCL_HF_SHARP_ENABLE = 0x1,
-} SCL_HF_SHARP_EN;
-typedef enum SCL_VF_SHARP_SCALE_FACTOR {
- SCL_VF_SHARP_SCALE_FACTOR_0 = 0x0,
- SCL_VF_SHARP_SCALE_FACTOR_1 = 0x1,
- SCL_VF_SHARP_SCALE_FACTOR_2 = 0x2,
- SCL_VF_SHARP_SCALE_FACTOR_3 = 0x3,
- SCL_VF_SHARP_SCALE_FACTOR_4 = 0x4,
- SCL_VF_SHARP_SCALE_FACTOR_5 = 0x5,
- SCL_VF_SHARP_SCALE_FACTOR_6 = 0x6,
- SCL_VF_SHARP_SCALE_FACTOR_7 = 0x7,
-} SCL_VF_SHARP_SCALE_FACTOR;
-typedef enum SCL_VF_SHARP_EN {
- SCL_VF_SHARP_DISABLE = 0x0,
- SCL_VF_SHARP_ENABLE = 0x1,
-} SCL_VF_SHARP_EN;
-typedef enum SCL_ALU_DISABLE {
- SCL_ALU_ENABLED = 0x0,
- SCL_ALU_DISABLED = 0x1,
-} SCL_ALU_DISABLE;
-typedef enum SCL_HOST_CONFLICT_MASK {
- SCL_HOST_CONFLICT_DISABLE_INTERRUPT = 0x0,
- SCL_HOST_CONFLICT_ENABLE_INTERRUPT = 0x1,
-} SCL_HOST_CONFLICT_MASK;
-typedef enum SCL_SCL_MODE_CHANGE_MASK {
- SCL_MODE_CHANGE_DISABLE_INTERRUPT = 0x0,
- SCL_MODE_CHANGE_ENABLE_INTERRUPT = 0x1,
-} SCL_SCL_MODE_CHANGE_MASK;
-typedef enum SCLV_MODE_SEL {
- SCLV_MODE_RGB_BYPASS = 0x0,
- SCLV_MODE_RGB_SCALING = 0x1,
- SCLV_MODE_YCBCR_SCALING = 0x2,
- SCLV_MODE_YCBCR_BYPASS = 0x3,
-} SCLV_MODE_SEL;
-typedef enum SCLV_INTERLACE_SOURCE {
- INTERLACE_SOURCE_PROGRESSIVE = 0x0,
- INTERLACE_SOURCE_INTERLEAVE = 0x1,
- INTERLACE_SOURCE_STACK = 0x2,
-} SCLV_INTERLACE_SOURCE;
-typedef enum SCLV_UPDATE_LOCK {
- UPDATE_UNLOCKED = 0x0,
- UPDATE_LOCKED = 0x1,
-} SCLV_UPDATE_LOCK;
-typedef enum SCLV_COEF_UPDATE_COMPLETE {
- COEF_UPDATE_NOT_COMPLETE = 0x0,
- COEF_UPDATE_COMPLETE = 0x1,
-} SCLV_COEF_UPDATE_COMPLETE;
-typedef enum COL_MAN_UPDATE_LOCK {
- COL_MAN_UPDATE_UNLOCKED = 0x0,
- COL_MAN_UPDATE_LOCKED = 0x1,
-} COL_MAN_UPDATE_LOCK;
-typedef enum COL_MAN_DISABLE_MULTIPLE_UPDATE {
- COL_MAN_MULTIPLE_UPDATE = 0x0,
- COL_MAN_MULTIPLE_UPDAT_EDISABLE = 0x1,
-} COL_MAN_DISABLE_MULTIPLE_UPDATE;
-typedef enum COL_MAN_INPUTCSC_MODE {
- INPUTCSC_MODE_BYPASS = 0x0,
- INPUTCSC_MODE_A = 0x1,
- INPUTCSC_MODE_B = 0x2,
- INPUTCSC_MODE_UNITY = 0x3,
-} COL_MAN_INPUTCSC_MODE;
-typedef enum COL_MAN_INPUTCSC_TYPE {
- INPUTCSC_TYPE_12_0 = 0x0,
- INPUTCSC_TYPE_10_2 = 0x1,
- INPUTCSC_TYPE_8_4 = 0x2,
-} COL_MAN_INPUTCSC_TYPE;
-typedef enum COL_MAN_INPUTCSC_CONVERT {
- INPUTCSC_ROUND = 0x0,
- INPUTCSC_TRUNCATE = 0x1,
-} COL_MAN_INPUTCSC_CONVERT;
-typedef enum COL_MAN_PRESCALE_MODE {
- PRESCALE_MODE_BYPASS = 0x0,
- PRESCALE_MODE_PROGRAM = 0x1,
- PRESCALE_MODE_UNITY = 0x2,
-} COL_MAN_PRESCALE_MODE;
-typedef enum COL_MAN_INPUT_GAMMA_MODE {
- INGAMMA_MODE_BYPASS = 0x0,
- INGAMMA_MODE_FIX = 0x1,
- INGAMMA_MODE_FLOAT = 0x2,
-} COL_MAN_INPUT_GAMMA_MODE;
-typedef enum COL_MAN_OUTPUT_CSC_MODE {
- COL_MAN_OUTPUT_CSC_BYPASS = 0x0,
- COL_MAN_OUTPUT_CSC_RGB = 0x1,
- COL_MAN_OUTPUT_CSC_YCrCb601 = 0x2,
- COL_MAN_OUTPUT_CSC_YCrCb709 = 0x3,
- COL_MAN_OUTPUT_CSC_A = 0x4,
- COL_MAN_OUTPUT_CSC_B = 0x5,
- COL_MAN_OUTPUT_CSC_UNITY = 0x6,
-} COL_MAN_OUTPUT_CSC_MODE;
-typedef enum COL_MAN_DENORM_CLAMP_CONTROL {
- DENORM_CLAMP_MODE_UNITY = 0x0,
- DENORM_CLAMP_MODE_8 = 0x1,
- DENORM_CLAMP_MODE_10 = 0x2,
- DENORM_CLAMP_MODE_12 = 0x3,
-} COL_MAN_DENORM_CLAMP_CONTROL;
-typedef enum COL_MAN_GAMMA_CORR_CONTROL {
- GAMMA_CORR_MODE_BYPASS = 0x0,
- GAMMA_CORR_MODE_A = 0x1,
- GAMMA_CORR_MODE_B = 0x2,
-} COL_MAN_GAMMA_CORR_CONTROL;
-typedef enum COL_MAN_GLOBAL_PASSTHROUGH_ENABLE {
- CM_GLOBAL_PASSTHROUGH_DISBALE = 0x0,
- CM_GLOBAL_PASSTHROUGH_ENABLE = 0x1,
-} COL_MAN_GLOBAL_PASSTHROUGH_ENABLE;
-typedef enum UNP_GRPH_EN {
- UNP_GRPH_DISABLED = 0x0,
- UNP_GRPH_ENABLED = 0x1,
-} UNP_GRPH_EN;
-typedef enum UNP_GRPH_DEPTH {
- UNP_GRPH_8BPP = 0x0,
- UNP_GRPH_16BPP = 0x1,
- UNP_GRPH_32BPP = 0x2,
-} UNP_GRPH_DEPTH;
-typedef enum UNP_GRPH_NUM_BANKS {
- UNP_GRPH_ADDR_SURF_2_BANK = 0x0,
- UNP_GRPH_ADDR_SURF_4_BANK = 0x1,
- UNP_GRPH_ADDR_SURF_8_BANK = 0x2,
- UNP_GRPH_ADDR_SURF_16_BANK = 0x3,
-} UNP_GRPH_NUM_BANKS;
-typedef enum UNP_GRPH_BANK_WIDTH {
- UNP_GRPH_ADDR_SURF_BANK_WIDTH_1 = 0x0,
- UNP_GRPH_ADDR_SURF_BANK_WIDTH_2 = 0x1,
- UNP_GRPH_ADDR_SURF_BANK_WIDTH_4 = 0x2,
- UNP_GRPH_ADDR_SURF_BANK_WIDTH_8 = 0x3,
-} UNP_GRPH_BANK_WIDTH;
-typedef enum UNP_GRPH_BANK_HEIGHT {
- UNP_GRPH_ADDR_SURF_BANK_HEIGHT_1 = 0x0,
- UNP_GRPH_ADDR_SURF_BANK_HEIGHT_2 = 0x1,
- UNP_GRPH_ADDR_SURF_BANK_HEIGHT_4 = 0x2,
- UNP_GRPH_ADDR_SURF_BANK_HEIGHT_8 = 0x3,
-} UNP_GRPH_BANK_HEIGHT;
-typedef enum UNP_GRPH_TILE_SPLIT {
- UNP_ADDR_SURF_TILE_SPLIT_64B = 0x0,
- UNP_ADDR_SURF_TILE_SPLIT_128B = 0x1,
- UNP_ADDR_SURF_TILE_SPLIT_256B = 0x2,
- UNP_ADDR_SURF_TILE_SPLIT_512B = 0x3,
- UNP_ADDR_SURF_TILE_SPLIT_1KB = 0x4,
- UNP_ADDR_SURF_TILE_SPLIT_2KB = 0x5,
- UNP_ADDR_SURF_TILE_SPLIT_4KB = 0x6,
-} UNP_GRPH_TILE_SPLIT;
-typedef enum UNP_GRPH_ADDRESS_TRANSLATION_ENABLE {
- UNP_GRPH_ADDRESS_TRANSLATION_ENABLE0 = 0x0,
- UNP_GRPH_ADDRESS_TRANSLATION_ENABLE1 = 0x1,
-} UNP_GRPH_ADDRESS_TRANSLATION_ENABLE;
-typedef enum UNP_GRPH_PRIVILEGED_ACCESS_ENABLE {
- UNP_GRPH_PRIVILEGED_ACCESS_DIS = 0x0,
- UNP_GRPH_PRIVILEGED_ACCESS_EN = 0x1,
-} UNP_GRPH_PRIVILEGED_ACCESS_ENABLE;
-typedef enum UNP_GRPH_MACRO_TILE_ASPECT {
- UNP_ADDR_SURF_MACRO_ASPECT_1 = 0x0,
- UNP_ADDR_SURF_MACRO_ASPECT_2 = 0x1,
- UNP_ADDR_SURF_MACRO_ASPECT_4 = 0x2,
- UNP_ADDR_SURF_MACRO_ASPECT_8 = 0x3,
-} UNP_GRPH_MACRO_TILE_ASPECT;
-typedef enum UNP_GRPH_COLOR_EXPANSION_MODE {
- UNP_GRPH_DYNAMIC_EXPANSION = 0x0,
- UNP_GRPH_ZERO_EXPANSION = 0x1,
-} UNP_GRPH_COLOR_EXPANSION_MODE;
-typedef enum UNP_VIDEO_FORMAT {
- UNP_VIDEO_FORMAT0 = 0x0,
- UNP_VIDEO_FORMAT1 = 0x1,
- UNP_VIDEO_FORMAT_YUV420_YCbCr = 0x2,
- UNP_VIDEO_FORMAT_YUV420_YCrCb = 0x3,
- UNP_VIDEO_FORMAT_YUV422_YCb = 0x4,
- UNP_VIDEO_FORMAT_YUV422_YCr = 0x5,
- UNP_VIDEO_FORMAT_YUV422_CbY = 0x6,
- UNP_VIDEO_FORMAT_YUV422_CrY = 0x7,
-} UNP_VIDEO_FORMAT;
-typedef enum UNP_GRPH_ENDIAN_SWAP {
- UNP_GRPH_ENDIAN_SWAP_NONE = 0x0,
- UNP_GRPH_ENDIAN_SWAP_8IN16 = 0x1,
- UNP_GRPH_ENDIAN_SWAP_8IN32 = 0x2,
- UNP_GRPH_ENDIAN_SWAP_8IN43 = 0x3,
-} UNP_GRPH_ENDIAN_SWAP;
-typedef enum UNP_GRPH_RED_CROSSBAR {
- UNP_GRPH_RED_CROSSBAR_R_Cr = 0x0,
- UNP_GRPH_RED_CROSSBAR_G_Y = 0x1,
- UNP_GRPH_RED_CROSSBAR_B_Cb = 0x2,
- UNP_GRPH_RED_CROSSBAR_A = 0x3,
-} UNP_GRPH_RED_CROSSBAR;
-typedef enum UNP_GRPH_GREEN_CROSSBAR {
- UNP_UNP_GRPH_GREEN_CROSSBAR_GY_AND_Y = 0x0,
- UNP_UNP_GRPH_GREEN_CROSSBAR_B_Cb_AND_C = 0x1,
- UNP_UNP_GRPH_GREEN_CROSSBAR_A = 0x2,
- UNP_UNP_GRPH_GREEN_CROSSBAR_R_Cr = 0x3,
-} UNP_GRPH_GREEN_CROSSBAR;
-typedef enum UNP_GRPH_BLUE_CROSSBAR {
- UNP_GRPH_BLUE_CROSSBAR_B_Cb_AND_C = 0x0,
- UNP_GRPH_BLUE_CROSSBAR_A = 0x1,
- UNP_GRPH_BLUE_CROSSBAR_R_Cr = 0x2,
- UNP_GRPH_BLUE_CROSSBAR_GY_AND_Y = 0x3,
-} UNP_GRPH_BLUE_CROSSBAR;
-typedef enum UNP_GRPH_MODE_UPDATE_LOCKG {
- UNP_GRPH_UPDATE_LOCK_0 = 0x0,
- UNP_GRPH_UPDATE_LOCK_1 = 0x1,
-} UNP_GRPH_MODE_UPDATE_LOCKG;
-typedef enum UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK {
- UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_0 = 0x0,
- UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_1 = 0x1,
-} UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK;
-typedef enum UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE {
- UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_0 = 0x0,
- UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_1 = 0x1,
-} UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE;
-typedef enum UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE {
- UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_0 = 0x0,
- UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_1 = 0x1,
-} UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE;
-typedef enum UNP_GRPH_STEREOSYNC_FLIP_EN {
- UNP_GRPH_STEREOSYNC_FLIP_DISABLE = 0x0,
- UNP_GRPH_STEREOSYNC_FLIP_ENABLE = 0x1,
-} UNP_GRPH_STEREOSYNC_FLIP_EN;
-typedef enum UNP_GRPH_STEREOSYNC_FLIP_MODE {
- UNP_GRPH_STEREOSYNC_FLIP_MODE_0 = 0x0,
- UNP_GRPH_STEREOSYNC_FLIP_MODE_1 = 0x1,
- UNP_GRPH_STEREOSYNC_FLIP_MODE_2 = 0x2,
- UNP_GRPH_STEREOSYNC_FLIP_MODE_3 = 0x3,
-} UNP_GRPH_STEREOSYNC_FLIP_MODE;
-typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_EN {
- UNP_GRPH_STACK_INTERLACE_FLIP_DISABLE = 0x0,
- UNP_GRPH_STACK_INTERLACE_FLIP_ENABLE = 0x1,
-} UNP_GRPH_STACK_INTERLACE_FLIP_EN;
-typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_MODE {
- UNP_GRPH_STACK_INTERLACE_FLIP_MODE_0 = 0x0,
- UNP_GRPH_STACK_INTERLACE_FLIP_MODE_1 = 0x1,
- UNP_GRPH_STACK_INTERLACE_FLIP_MODE_2 = 0x2,
- UNP_GRPH_STACK_INTERLACE_FLIP_MODE_3 = 0x3,
-} UNP_GRPH_STACK_INTERLACE_FLIP_MODE;
-typedef enum UNP_GRPH_STEREOSYNC_SELECT_DISABLE {
- UNP_GRPH_STEREOSYNC_SELECT_EN = 0x0,
- UNP_GRPH_STEREOSYNC_SELECT_DIS = 0x1,
-} UNP_GRPH_STEREOSYNC_SELECT_DISABLE;
-typedef enum UNP_CRC_SOURCE_SEL {
- UNP_CRC_SOURCE_SEL_NP_TO_LBV = 0x0,
- UNP_CRC_SOURCE_SEL_LOWER32 = 0x1,
- UNP_CRC_SOURCE_SEL_RESERVED = 0x2,
- UNP_CRC_SOURCE_SEL_LOWER16 = 0x3,
- UNP_CRC_SOURCE_SEL_UNP_TO_LBV = 0x4,
-} UNP_CRC_SOURCE_SEL;
-typedef enum UNP_CRC_LINE_SEL {
- UNP_CRC_LINE_SEL_RESERVED = 0x0,
- UNP_CRC_LINE_SEL_EVEN_ONLY = 0x1,
- UNP_CRC_LINE_SEL_ODD_ONLY = 0x2,
- UNP_CRC_LINE_SEL_ODD_EVEN = 0x3,
-} UNP_CRC_LINE_SEL;
-typedef enum UNP_ROTATION_ANGLE {
- UNP_ROTATION_ANGLE_0 = 0x0,
- UNP_ROTATION_ANGLE_90 = 0x1,
- UNP_ROTATION_ANGLE_180 = 0x2,
- UNP_ROTATION_ANGLE_270 = 0x3,
- UNP_ROTATION_ANGLE_0m = 0x4,
- UNP_ROTATION_ANGLE_90m = 0x5,
- UNP_ROTATION_ANGLE_180m = 0x6,
- UNP_ROTATION_ANGLE_270m = 0x7,
-} UNP_ROTATION_ANGLE;
-typedef enum UNP_PIXEL_DROP {
- UNP_PIXEL_NO_DROP = 0x0,
- UNP_PIXEL_DROPPING = 0x1,
-} UNP_PIXEL_DROP;
-typedef enum UNP_BUFFER_MODE {
- UNP_BUFFER_MODE_LUMA = 0x0,
- UNP_BUFFER_MODE_LUMA_CHROMA = 0x1,
-} UNP_BUFFER_MODE;
-typedef enum WATERMARK_MASK_CONTROL {
- WM_MASK_CONTROL_SET_A = 0x0,
- WM_MASK_CONTROL_SET_B = 0x1,
- WM_MASK_CONTROL_SET_C = 0x2,
- WM_MASK_CONTROL_SET_D = 0x3,
- WM_MASK_CONTROL_RESERVED1 = 0x4,
- WM_MASK_CONTROL_RESERVED2 = 0x5,
- WM_MASK_CONTROL_RESERVED3 = 0x6,
- WM_MASK_CONTROL_ACTIVE_SET = 0x7,
-} WATERMARK_MASK_CONTROL;
-typedef enum AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET {
- AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET= 0x0,
- AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET= 0x1,
-} AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET;
-typedef enum CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY {
- CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL= 0x0,
- CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6= 0x1,
- CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5= 0x2,
- CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4= 0x3,
- CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3= 0x4,
- CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2= 0x5,
- CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1= 0x6,
- CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0= 0x7,
-} CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY;
-typedef enum CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY {
- CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL= 0x0,
- CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6= 0x1,
- CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5= 0x2,
- CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4= 0x3,
- CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3= 0x4,
- CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2= 0x5,
- CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1= 0x6,
- CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0= 0x7,
-} CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY;
-typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL {
- GENERIC_AZ_CONTROLLER_REGISTER_DISABLE = 0x0,
- GENERIC_AZ_CONTROLLER_REGISTER_ENABLE = 0x1,
-} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL;
-typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED {
- GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED = 0x0,
- GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED = 0x1,
-} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED;
-typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS {
- GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET = 0x0,
- GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET = 0x1,
-} GENERIC_AZ_CONTROLLER_REGISTER_STATUS;
-typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED {
- GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED= 0x0,
- GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED= 0x1,
-} GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED;
-typedef enum AZ_GLOBAL_CAPABILITIES {
- AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED= 0x0,
- AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED= 0x1,
-} AZ_GLOBAL_CAPABILITIES;
-typedef enum GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE {
- ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE = 0x0,
- ACCEPT_UNSOLICITED_RESPONSE_ENABLE = 0x1,
-} GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE;
-typedef enum GLOBAL_CONTROL_FLUSH_CONTROL {
- FLUSH_CONTROL_FLUSH_NOT_STARTED = 0x0,
- FLUSH_CONTROL_FLUSH_STARTED = 0x1,
-} GLOBAL_CONTROL_FLUSH_CONTROL;
-typedef enum GLOBAL_CONTROL_CONTROLLER_RESET {
- CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET = 0x0,
- CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET = 0x1,
-} GLOBAL_CONTROL_CONTROLLER_RESET;
-typedef enum AZ_STATE_CHANGE_STATUS {
- AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT = 0x0,
- AZ_STATE_CHANGE_STATUS_CODEC_PRESENT = 0x1,
-} AZ_STATE_CHANGE_STATUS;
-typedef enum GLOBAL_STATUS_FLUSH_STATUS {
- GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED = 0x0,
- GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED = 0x1,
-} GLOBAL_STATUS_FLUSH_STATUS;
-typedef enum STREAM_0_SYNCHRONIZATION {
- STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x0,
- STREAM_0_SYNCHRONIZATION_STEAM_STOPPED = 0x1,
-} STREAM_0_SYNCHRONIZATION;
-typedef enum STREAM_1_SYNCHRONIZATION {
- STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x0,
- STREAM_1_SYNCHRONIZATION_STEAM_STOPPED = 0x1,
-} STREAM_1_SYNCHRONIZATION;
-typedef enum STREAM_2_SYNCHRONIZATION {
- STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x0,
- STREAM_2_SYNCHRONIZATION_STEAM_STOPPED = 0x1,
-} STREAM_2_SYNCHRONIZATION;
-typedef enum STREAM_3_SYNCHRONIZATION {
- STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x0,
- STREAM_3_SYNCHRONIZATION_STEAM_STOPPED = 0x1,
-} STREAM_3_SYNCHRONIZATION;
-typedef enum STREAM_4_SYNCHRONIZATION {
- STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x0,
- STREAM_4_SYNCHRONIZATION_STEAM_STOPPED = 0x1,
-} STREAM_4_SYNCHRONIZATION;
-typedef enum STREAM_5_SYNCHRONIZATION {
- STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x0,
- STREAM_5_SYNCHRONIZATION_STEAM_STOPPED = 0x1,
-} STREAM_5_SYNCHRONIZATION;
-typedef enum STREAM_6_SYNCHRONIZATION {
- STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
- STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
-} STREAM_6_SYNCHRONIZATION;
-typedef enum STREAM_7_SYNCHRONIZATION {
- STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
- STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
-} STREAM_7_SYNCHRONIZATION;
-typedef enum STREAM_8_SYNCHRONIZATION {
- STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
- STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
-} STREAM_8_SYNCHRONIZATION;
-typedef enum STREAM_9_SYNCHRONIZATION {
- STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
- STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
-} STREAM_9_SYNCHRONIZATION;
-typedef enum STREAM_10_SYNCHRONIZATION {
- STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
- STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
-} STREAM_10_SYNCHRONIZATION;
-typedef enum STREAM_11_SYNCHRONIZATION {
- STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
- STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
-} STREAM_11_SYNCHRONIZATION;
-typedef enum STREAM_12_SYNCHRONIZATION {
- STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
- STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
-} STREAM_12_SYNCHRONIZATION;
-typedef enum STREAM_13_SYNCHRONIZATION {
- STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
- STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
-} STREAM_13_SYNCHRONIZATION;
-typedef enum STREAM_14_SYNCHRONIZATION {
- STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
- STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
-} STREAM_14_SYNCHRONIZATION;
-typedef enum STREAM_15_SYNCHRONIZATION {
- STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
- STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
-} STREAM_15_SYNCHRONIZATION;
-typedef enum CORB_READ_POINTER_RESET {
- CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET = 0x0,
- CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET = 0x1,
-} CORB_READ_POINTER_RESET;
-typedef enum AZ_CORB_SIZE {
- AZ_CORB_SIZE_2ENTRIES_RESERVED = 0x0,
- AZ_CORB_SIZE_16ENTRIES_RESERVED = 0x1,
- AZ_CORB_SIZE_256ENTRIES = 0x2,
- AZ_CORB_SIZE_RESERVED = 0x3,
-} AZ_CORB_SIZE;
-typedef enum AZ_RIRB_WRITE_POINTER_RESET {
- AZ_RIRB_WRITE_POINTER_NOT_RESET = 0x0,
- AZ_RIRB_WRITE_POINTER_DO_RESET = 0x1,
-} AZ_RIRB_WRITE_POINTER_RESET;
-typedef enum RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL {
- RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED= 0x0,
- RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED= 0x1,
-} RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL;
-typedef enum RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL {
- RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED= 0x0,
- RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED= 0x1,
-} RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL;
-typedef enum AZ_RIRB_SIZE {
- AZ_RIRB_SIZE_2ENTRIES_RESERVED = 0x0,
- AZ_RIRB_SIZE_16ENTRIES_RESERVED = 0x1,
- AZ_RIRB_SIZE_256ENTRIES = 0x2,
- AZ_RIRB_SIZE_UNDEFINED = 0x3,
-} AZ_RIRB_SIZE;
-typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID {
- IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID= 0x0,
- IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID= 0x1,
-} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID;
-typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY {
- IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY= 0x0,
- IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY= 0x1,
-} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY;
-typedef enum DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE {
- DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE= 0x0,
- DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE= 0x1,
-} DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE;
-typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR {
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET= 0x0,
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET= 0x1,
-} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR;
-typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR {
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET= 0x0,
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET= 0x1,
-} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR;
-typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS {
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET= 0x0,
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET= 0x1,
-} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS;
-typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY {
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY= 0x0,
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY= 0x1,
-} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY;
-typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE {
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED= 0x0,
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED= 0x1,
-} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE;
-typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE {
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED= 0x0,
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED= 0x1,
-} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE;
-typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE {
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED= 0x0,
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED= 0x1,
-} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE;
-typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN {
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN= 0x0,
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN= 0x1,
-} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN;
-typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET {
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET= 0x0,
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET= 0x1,
-} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET;
-typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE {
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ= 0x0,
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ= 0x1,
-} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE;
-typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE {
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1= 0x0,
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2= 0x1,
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED= 0x2,
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4= 0x3,
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED= 0x4,
-} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE;
-typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR {
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1= 0x0,
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED= 0x1,
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3= 0x2,
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED= 0x3,
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED= 0x4,
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED= 0x5,
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED= 0x6,
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED= 0x7,
-} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR;
-typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE {
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED= 0x0,
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16= 0x1,
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20= 0x2,
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24= 0x3,
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED= 0x4,
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED= 0x5,
-} OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE;
-typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS {
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1= 0x0,
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2= 0x1,
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3= 0x2,
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4= 0x3,
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5= 0x4,
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6= 0x5,
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7= 0x6,
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8= 0x7,
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED= 0x8,
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED= 0x9,
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED= 0xa,
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED= 0xb,
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED= 0xc,
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED= 0xd,
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED= 0xe,
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED= 0xf,
-} OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS;
-typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM= 0x0,
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM= 0x1,
-} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
-typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ= 0x0,
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ= 0x1,
-} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
-typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1= 0x0,
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2= 0x1,
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED= 0x2,
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4= 0x3,
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED= 0x4,
-} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
-typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1= 0x0,
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED= 0x1,
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3= 0x2,
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED= 0x3,
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED= 0x4,
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED= 0x5,
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED= 0x6,
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED= 0x7,
-} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
-typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED= 0x0,
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16= 0x1,
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20= 0x2,
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24= 0x3,
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED= 0x4,
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED= 0x5,
-} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
-typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1= 0x0,
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2= 0x1,
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3= 0x2,
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4= 0x3,
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5= 0x4,
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6= 0x5,
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7= 0x6,
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8= 0x7,
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED= 0x8,
-} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
-typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L {
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET= 0x0,
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET= 0x1,
-} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L;
-typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO {
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET= 0x0,
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET= 0x1,
-} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO;
-typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO {
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET= 0x0,
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET= 0x1,
-} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO;
-typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY {
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET= 0x0,
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET= 0x1,
-} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY;
-typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE {
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET= 0x0,
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET= 0x1,
-} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE;
-typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG {
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON= 0x0,
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON= 0x1,
-} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG;
-typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V {
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO= 0x0,
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE= 0x1,
-} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V;
-typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED= 0x0,
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED= 0x1,
-} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
-typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE {
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE= 0x0,
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE= 0x1,
-} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE;
-typedef enum AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE {
- AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF= 0x0,
- AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN= 0x1,
-} AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE;
-typedef enum AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
- AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED= 0x0,
- AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED= 0x1,
-} AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
-typedef enum AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT {
- AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED= 0x0,
- AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN = 0x1,
-} AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT;
-typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE {
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED= 0x0,
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED= 0x1,
-} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE;
-typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE {
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED= 0x0,
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED= 0x1,
-} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE;
-typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE {
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED= 0x0,
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED= 0x1,
-} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE;
-typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE {
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED= 0x0,
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED= 0x1,
-} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE;
-typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED= 0x0,
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED= 0x1,
-} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
-typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED= 0x0,
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED= 0x1,
-} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
-typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED= 0x0,
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED= 0x1,
-} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
-typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED= 0x0,
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED= 0x1,
-} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
-typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE= 0x0,
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE= 0x1,
-} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
-typedef enum AZ_LATENCY_COUNTER_CONTROL {
- AZ_LATENCY_COUNTER_NO_RESET = 0x0,
- AZ_LATENCY_COUNTER_RESET_DONE = 0x1,
-} AZ_LATENCY_COUNTER_CONTROL;
-typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0,
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1,
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2,
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3,
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4,
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5,
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6,
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7,
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED= 0x8,
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9,
-} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
-typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY= 0x0,
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY= 0x1,
-} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
-typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0,
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1,
-} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
-typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG= 0x0,
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL= 0x1,
-} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
-typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0,
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1,
-} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
-typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0,
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1,
-} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
-typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES= 0x0,
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES= 0x1,
-} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
-typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING= 0x0,
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1,
-} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
-typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE= 0x0,
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE= 0x1,
-} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
-typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0,
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE= 0x1,
-} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
-typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0,
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1,
-} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
-typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER= 0x0,
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1,
-} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
-typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC= 0x0,
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO= 0x1,
-} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
-typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0,
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1,
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2,
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3,
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4,
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5,
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6,
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7,
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED= 0x8,
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9,
-} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
-typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY= 0x0,
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY= 0x1,
-} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
-typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0,
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1,
-} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
-typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG= 0x0,
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL= 0x1,
-} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
-typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0,
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1,
-} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
-typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0,
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1,
-} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
-typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES= 0x0,
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES= 0x1,
-} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
-typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING= 0x0,
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1,
-} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
-typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0,
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE= 0x1,
-} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
-typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0,
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1,
-} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
-typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT= 0x0,
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1,
-} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
-typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN= 0x0,
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN= 0x1,
-} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
-typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED= 0x0,
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED= 0x1,
-} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
-typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN= 0x0,
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN= 0x1,
-} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
-typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN= 0x0,
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN= 0x1,
-} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
-typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY= 0x0,
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY= 0x1,
-} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
-typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY= 0x0,
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY= 0x1,
-} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
-typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x0,
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x1,
-} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
-typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY= 0x0,
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY= 0x1,
-} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
-typedef enum AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE= 0x0,
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE= 0x1,
-} AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
-typedef enum AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
- AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY= 0x0,
- AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY= 0x1,
-} AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
-typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0,
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1,
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2,
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3,
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4,
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5,
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6,
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7,
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED= 0x8,
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9,
-} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
-typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY= 0x0,
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY= 0x1,
-} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
-typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0,
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1,
-} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
-typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG= 0x0,
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL= 0x1,
-} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
-typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0,
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1,
-} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
-typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0,
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1,
-} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
-typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES= 0x0,
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES= 0x1,
-} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
-typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING= 0x0,
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1,
-} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
-typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE= 0x0,
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE= 0x1,
-} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
-typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0,
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER= 0x1,
-} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
-typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0,
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1,
-} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
-typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER= 0x0,
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1,
-} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
-typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC= 0x0,
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO= 0x1,
-} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
-typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0,
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1,
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2,
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3,
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4,
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5,
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6,
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7,
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED= 0x8,
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9,
-} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
-typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP= 0x0,
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP= 0x1,
-} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
-typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0,
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1,
-} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
-typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG= 0x0,
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL= 0x1,
-} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
-typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0,
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1,
-} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
-typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0,
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1,
-} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
-typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES= 0x0,
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES= 0x1,
-} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
-typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING= 0x0,
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1,
-} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
-typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0,
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE= 0x1,
-} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
-typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0,
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1,
-} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
-typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER= 0x0,
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1,
-} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
-typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP {
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED= 0x0,
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED= 0x1,
-} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP;
-typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN= 0x0,
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN= 0x1,
-} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
-typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI {
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED= 0x0,
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED= 0x1,
-} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI;
-typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED= 0x0,
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED= 0x1,
-} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
-typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN= 0x0,
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN= 0x1,
-} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
-typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN= 0x0,
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN= 0x1,
-} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
-typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY= 0x0,
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY= 0x1,
-} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
-typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY= 0x0,
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY= 0x1,
-} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
-typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x0,
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x1,
-} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
-typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY= 0x0,
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY= 0x1,
-} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
-typedef enum AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY= 0x0,
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY= 0x1,
-} AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
-typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM= 0x0,
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM= 0x1,
-} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
-typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ= 0x0,
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ= 0x1,
-} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
-typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1= 0x0,
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2= 0x1,
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED= 0x2,
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4= 0x3,
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED= 0x4,
-} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
-typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1= 0x0,
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED= 0x1,
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3= 0x2,
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED= 0x3,
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED= 0x4,
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED= 0x5,
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED= 0x6,
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED= 0x7,
-} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
-typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED= 0x0,
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16= 0x1,
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20= 0x2,
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24= 0x3,
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED= 0x4,
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED= 0x5,
-} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
-typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1= 0x0,
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2= 0x1,
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3= 0x2,
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4= 0x3,
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5= 0x4,
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6= 0x5,
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7= 0x6,
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8= 0x7,
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED= 0x8,
-} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
-typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED= 0x0,
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED= 0x1,
-} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
-typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE {
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF= 0x0,
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN= 0x1,
-} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE;
-typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED= 0x0,
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED= 0x1,
-} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
-typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE {
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED= 0x0,
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED= 0x1,
-} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE;
-typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED= 0x0,
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED= 0x1,
-} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
-typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE {
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED= 0x0,
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED= 0x1,
-} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE;
-typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED= 0x0,
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED= 0x1,
-} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
-typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE {
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED= 0x0,
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED= 0x1,
-} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE;
-typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED= 0x0,
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED= 0x1,
-} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
-typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE {
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED= 0x0,
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED= 0x1,
-} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE;
-typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED= 0x0,
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED= 0x1,
-} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
-typedef enum BLND_CONTROL_BLND_MODE {
- BLND_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0x0,
- BLND_CONTROL_BLND_MODE_OTHER_PIPE_ONLY = 0x1,
- BLND_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 0x2,
- BLND_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 0x3,
-} BLND_CONTROL_BLND_MODE;
-typedef enum BLND_CONTROL_BLND_STEREO_TYPE {
- BLND_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO= 0x0,
- BLND_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO= 0x1,
- BLND_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO= 0x2,
- BLND_CONTROL_BLND_STEREO_TYPE_UNUSED = 0x3,
-} BLND_CONTROL_BLND_STEREO_TYPE;
-typedef enum BLND_CONTROL_BLND_STEREO_POLARITY {
- BLND_CONTROL_BLND_STEREO_POLARITY_LOW = 0x0,
- BLND_CONTROL_BLND_STEREO_POLARITY_HIGH = 0x1,
-} BLND_CONTROL_BLND_STEREO_POLARITY;
-typedef enum BLND_CONTROL_BLND_FEEDTHROUGH_EN {
- BLND_CONTROL_BLND_FEEDTHROUGH_EN_FALSE = 0x0,
- BLND_CONTROL_BLND_FEEDTHROUGH_EN_TRUE = 0x1,
-} BLND_CONTROL_BLND_FEEDTHROUGH_EN;
-typedef enum BLND_CONTROL_BLND_ALPHA_MODE {
- BLND_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0x0,
- BLND_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN= 0x1,
- BLND_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 0x2,
- BLND_CONTROL_BLND_ALPHA_MODE_UNUSED = 0x3,
-} BLND_CONTROL_BLND_ALPHA_MODE;
-typedef enum BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY {
- BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_FALSE = 0x0,
- BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_TRUE = 0x1,
-} BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY;
-typedef enum BLND_CONTROL_BLND_MULTIPLIED_MODE {
- BLND_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0x0,
- BLND_CONTROL_BLND_MULTIPLIED_MODE_TRUE = 0x1,
-} BLND_CONTROL_BLND_MULTIPLIED_MODE;
-typedef enum BLND_SM_CONTROL2_SM_MODE {
- BLND_SM_CONTROL2_SM_MODE_SINGLE_PLANE = 0x0,
- BLND_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 0x2,
- BLND_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 0x4,
- BLND_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING= 0x6,
-} BLND_SM_CONTROL2_SM_MODE;
-typedef enum BLND_SM_CONTROL2_SM_FRAME_ALTERNATE {
- BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0x0,
- BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 0x1,
-} BLND_SM_CONTROL2_SM_FRAME_ALTERNATE;
-typedef enum BLND_SM_CONTROL2_SM_FIELD_ALTERNATE {
- BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0x0,
- BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 0x1,
-} BLND_SM_CONTROL2_SM_FIELD_ALTERNATE;
-typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL {
- BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE= 0x0,
- BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED= 0x1,
- BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW= 0x2,
- BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH= 0x3,
-} BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL;
-typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL {
- BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x0,
- BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x1,
- BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x2,
- BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH= 0x3,
-} BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL;
-typedef enum BLND_CONTROL2_PTI_ENABLE {
- BLND_CONTROL2_PTI_ENABLE_FALSE = 0x0,
- BLND_CONTROL2_PTI_ENABLE_TRUE = 0x1,
-} BLND_CONTROL2_PTI_ENABLE;
-typedef enum BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN {
- BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0x0,
- BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 0x1,
-} BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN;
-typedef enum BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN {
- BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0x0,
- BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 0x1,
-} BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN;
-typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK {
- BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE= 0x0,
- BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE= 0x1,
-} BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK;
-typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK {
- BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE= 0x0,
- BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE= 0x1,
-} BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK;
-typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK {
- BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE= 0x0,
- BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE= 0x1,
-} BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK;
-typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK {
- BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE= 0x0,
- BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE= 0x1,
-} BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK;
-typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK {
- BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE= 0x0,
- BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE= 0x1,
-} BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK;
-typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK {
- BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE= 0x0,
- BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE= 0x1,
-} BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK;
-typedef enum BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK {
- BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x0,
- BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 0x1,
-} BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK;
-typedef enum BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK {
- BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0x0,
- BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x1,
-} BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK;
-typedef enum BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE {
- BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0x0,
- BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x1,
-} BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE;
-typedef enum BLND_DEBUG_BLND_CNV_MUX_SELECT {
- BLND_DEBUG_BLND_CNV_MUX_SELECT_LOW = 0x0,
- BLND_DEBUG_BLND_CNV_MUX_SELECT_HIGH = 0x1,
-} BLND_DEBUG_BLND_CNV_MUX_SELECT;
-typedef enum BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN {
- BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE= 0x0,
- BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE= 0x1,
-} BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN;
-typedef enum SurfaceEndian {
- ENDIAN_NONE = 0x0,
- ENDIAN_8IN16 = 0x1,
- ENDIAN_8IN32 = 0x2,
- ENDIAN_8IN64 = 0x3,
-} SurfaceEndian;
-typedef enum ArrayMode {
- ARRAY_LINEAR_GENERAL = 0x0,
- ARRAY_LINEAR_ALIGNED = 0x1,
- ARRAY_1D_TILED_THIN1 = 0x2,
- ARRAY_1D_TILED_THICK = 0x3,
- ARRAY_2D_TILED_THIN1 = 0x4,
- ARRAY_PRT_TILED_THIN1 = 0x5,
- ARRAY_PRT_2D_TILED_THIN1 = 0x6,
- ARRAY_2D_TILED_THICK = 0x7,
- ARRAY_2D_TILED_XTHICK = 0x8,
- ARRAY_PRT_TILED_THICK = 0x9,
- ARRAY_PRT_2D_TILED_THICK = 0xa,
- ARRAY_PRT_3D_TILED_THIN1 = 0xb,
- ARRAY_3D_TILED_THIN1 = 0xc,
- ARRAY_3D_TILED_THICK = 0xd,
- ARRAY_3D_TILED_XTHICK = 0xe,
- ARRAY_PRT_3D_TILED_THICK = 0xf,
-} ArrayMode;
-typedef enum PipeTiling {
- CONFIG_1_PIPE = 0x0,
- CONFIG_2_PIPE = 0x1,
- CONFIG_4_PIPE = 0x2,
- CONFIG_8_PIPE = 0x3,
-} PipeTiling;
-typedef enum BankTiling {
- CONFIG_4_BANK = 0x0,
- CONFIG_8_BANK = 0x1,
-} BankTiling;
-typedef enum GroupInterleave {
- CONFIG_256B_GROUP = 0x0,
- CONFIG_512B_GROUP = 0x1,
-} GroupInterleave;
-typedef enum RowTiling {
- CONFIG_1KB_ROW = 0x0,
- CONFIG_2KB_ROW = 0x1,
- CONFIG_4KB_ROW = 0x2,
- CONFIG_8KB_ROW = 0x3,
- CONFIG_1KB_ROW_OPT = 0x4,
- CONFIG_2KB_ROW_OPT = 0x5,
- CONFIG_4KB_ROW_OPT = 0x6,
- CONFIG_8KB_ROW_OPT = 0x7,
-} RowTiling;
-typedef enum BankSwapBytes {
- CONFIG_128B_SWAPS = 0x0,
- CONFIG_256B_SWAPS = 0x1,
- CONFIG_512B_SWAPS = 0x2,
- CONFIG_1KB_SWAPS = 0x3,
-} BankSwapBytes;
-typedef enum SampleSplitBytes {
- CONFIG_1KB_SPLIT = 0x0,
- CONFIG_2KB_SPLIT = 0x1,
- CONFIG_4KB_SPLIT = 0x2,
- CONFIG_8KB_SPLIT = 0x3,
-} SampleSplitBytes;
-typedef enum NumPipes {
- ADDR_CONFIG_1_PIPE = 0x0,
- ADDR_CONFIG_2_PIPE = 0x1,
- ADDR_CONFIG_4_PIPE = 0x2,
- ADDR_CONFIG_8_PIPE = 0x3,
-} NumPipes;
-typedef enum PipeInterleaveSize {
- ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
- ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
-} PipeInterleaveSize;
-typedef enum BankInterleaveSize {
- ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
- ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
- ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
- ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
-} BankInterleaveSize;
-typedef enum NumShaderEngines {
- ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
- ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
-} NumShaderEngines;
-typedef enum ShaderEngineTileSize {
- ADDR_CONFIG_SE_TILE_16 = 0x0,
- ADDR_CONFIG_SE_TILE_32 = 0x1,
-} ShaderEngineTileSize;
-typedef enum NumGPUs {
- ADDR_CONFIG_1_GPU = 0x0,
- ADDR_CONFIG_2_GPU = 0x1,
- ADDR_CONFIG_4_GPU = 0x2,
-} NumGPUs;
-typedef enum MultiGPUTileSize {
- ADDR_CONFIG_GPU_TILE_16 = 0x0,
- ADDR_CONFIG_GPU_TILE_32 = 0x1,
- ADDR_CONFIG_GPU_TILE_64 = 0x2,
- ADDR_CONFIG_GPU_TILE_128 = 0x3,
-} MultiGPUTileSize;
-typedef enum RowSize {
- ADDR_CONFIG_1KB_ROW = 0x0,
- ADDR_CONFIG_2KB_ROW = 0x1,
- ADDR_CONFIG_4KB_ROW = 0x2,
-} RowSize;
-typedef enum NumLowerPipes {
- ADDR_CONFIG_1_LOWER_PIPES = 0x0,
- ADDR_CONFIG_2_LOWER_PIPES = 0x1,
-} NumLowerPipes;
-typedef enum DebugBlockId {
- DBG_CLIENT_BLKID_RESERVED = 0x0,
- DBG_CLIENT_BLKID_dbg = 0x1,
- DBG_CLIENT_BLKID_scf2 = 0x2,
- DBG_CLIENT_BLKID_mcd5 = 0x3,
- DBG_CLIENT_BLKID_vmc = 0x4,
- DBG_CLIENT_BLKID_sx30 = 0x5,
- DBG_CLIENT_BLKID_mcd2 = 0x6,
- DBG_CLIENT_BLKID_bci1 = 0x7,
- DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0x8,
- DBG_CLIENT_BLKID_mcc0 = 0x9,
- DBG_CLIENT_BLKID_uvdf_2 = 0xa,
- DBG_CLIENT_BLKID_uvdf_3 = 0xb,
- DBG_CLIENT_BLKID_uvdt_0 = 0xc,
- DBG_CLIENT_BLKID_uvdi_0 = 0xd,
- DBG_CLIENT_BLKID_bci0 = 0xe,
- DBG_CLIENT_BLKID_vceb0_1 = 0xf,
- DBG_CLIENT_BLKID_cb100 = 0x10,
- DBG_CLIENT_BLKID_cb001 = 0x11,
- DBG_CLIENT_BLKID_mcd4 = 0x12,
- DBG_CLIENT_BLKID_tmonw00 = 0x13,
- DBG_CLIENT_BLKID_cb101 = 0x14,
- DBG_CLIENT_BLKID_sx10 = 0x15,
- DBG_CLIENT_BLKID_cb301 = 0x16,
- DBG_CLIENT_BLKID_tmonw01 = 0x17,
- DBG_CLIENT_BLKID_vcea0_0 = 0x18,
- DBG_CLIENT_BLKID_vcea0_1 = 0x19,
- DBG_CLIENT_BLKID_vcea0_2 = 0x1a,
- DBG_CLIENT_BLKID_vcea0_3 = 0x1b,
- DBG_CLIENT_BLKID_scf1 = 0x1c,
- DBG_CLIENT_BLKID_sx20 = 0x1d,
- DBG_CLIENT_BLKID_spim1 = 0x1e,
- DBG_CLIENT_BLKID_pa10 = 0x1f,
- DBG_CLIENT_BLKID_pa00 = 0x20,
- DBG_CLIENT_BLKID_gmcon = 0x21,
- DBG_CLIENT_BLKID_mcb = 0x22,
- DBG_CLIENT_BLKID_vgt0 = 0x23,
- DBG_CLIENT_BLKID_pc0 = 0x24,
- DBG_CLIENT_BLKID_bci2 = 0x25,
- DBG_CLIENT_BLKID_uvdb_0 = 0x26,
- DBG_CLIENT_BLKID_spim3 = 0x27,
- DBG_CLIENT_BLKID_cpc_0 = 0x28,
- DBG_CLIENT_BLKID_cpc_1 = 0x29,
- DBG_CLIENT_BLKID_uvdm_0 = 0x2a,
- DBG_CLIENT_BLKID_uvdm_1 = 0x2b,
- DBG_CLIENT_BLKID_uvdm_2 = 0x2c,
- DBG_CLIENT_BLKID_uvdm_3 = 0x2d,
- DBG_CLIENT_BLKID_cb000 = 0x2e,
- DBG_CLIENT_BLKID_spim0 = 0x2f,
- DBG_CLIENT_BLKID_mcc2 = 0x30,
- DBG_CLIENT_BLKID_ds0 = 0x31,
- DBG_CLIENT_BLKID_srbm = 0x32,
- DBG_CLIENT_BLKID_ih = 0x33,
- DBG_CLIENT_BLKID_sem = 0x34,
- DBG_CLIENT_BLKID_sdma_0 = 0x35,
- DBG_CLIENT_BLKID_sdma_1 = 0x36,
- DBG_CLIENT_BLKID_hdp = 0x37,
- DBG_CLIENT_BLKID_cb200 = 0x38,
- DBG_CLIENT_BLKID_scf3 = 0x39,
- DBG_CLIENT_BLKID_vceb1_0 = 0x3a,
- DBG_CLIENT_BLKID_vcea1_0 = 0x3b,
- DBG_CLIENT_BLKID_vcea1_1 = 0x3c,
- DBG_CLIENT_BLKID_vcea1_2 = 0x3d,
- DBG_CLIENT_BLKID_vcea1_3 = 0x3e,
- DBG_CLIENT_BLKID_bci3 = 0x3f,
- DBG_CLIENT_BLKID_mcd0 = 0x40,
- DBG_CLIENT_BLKID_pa11 = 0x41,
- DBG_CLIENT_BLKID_pa01 = 0x42,
- DBG_CLIENT_BLKID_cb201 = 0x43,
- DBG_CLIENT_BLKID_spim2 = 0x44,
- DBG_CLIENT_BLKID_vgt2 = 0x45,
- DBG_CLIENT_BLKID_pc2 = 0x46,
- DBG_CLIENT_BLKID_smu_0 = 0x47,
- DBG_CLIENT_BLKID_smu_1 = 0x48,
- DBG_CLIENT_BLKID_smu_2 = 0x49,
- DBG_CLIENT_BLKID_cb1 = 0x4a,
- DBG_CLIENT_BLKID_ia0 = 0x4b,
- DBG_CLIENT_BLKID_wd = 0x4c,
- DBG_CLIENT_BLKID_ia1 = 0x4d,
- DBG_CLIENT_BLKID_vcec1_0 = 0x4e,
- DBG_CLIENT_BLKID_scf0 = 0x4f,
- DBG_CLIENT_BLKID_vgt1 = 0x50,
- DBG_CLIENT_BLKID_pc1 = 0x51,
- DBG_CLIENT_BLKID_cb0 = 0x52,
- DBG_CLIENT_BLKID_gdc_one_0 = 0x53,
- DBG_CLIENT_BLKID_gdc_one_1 = 0x54,
- DBG_CLIENT_BLKID_gdc_one_2 = 0x55,
- DBG_CLIENT_BLKID_gdc_one_3 = 0x56,
- DBG_CLIENT_BLKID_gdc_one_4 = 0x57,
- DBG_CLIENT_BLKID_gdc_one_5 = 0x58,
- DBG_CLIENT_BLKID_gdc_one_6 = 0x59,
- DBG_CLIENT_BLKID_gdc_one_7 = 0x5a,
- DBG_CLIENT_BLKID_gdc_one_8 = 0x5b,
- DBG_CLIENT_BLKID_gdc_one_9 = 0x5c,
- DBG_CLIENT_BLKID_gdc_one_10 = 0x5d,
- DBG_CLIENT_BLKID_gdc_one_11 = 0x5e,
- DBG_CLIENT_BLKID_gdc_one_12 = 0x5f,
- DBG_CLIENT_BLKID_gdc_one_13 = 0x60,
- DBG_CLIENT_BLKID_gdc_one_14 = 0x61,
- DBG_CLIENT_BLKID_gdc_one_15 = 0x62,
- DBG_CLIENT_BLKID_gdc_one_16 = 0x63,
- DBG_CLIENT_BLKID_gdc_one_17 = 0x64,
- DBG_CLIENT_BLKID_gdc_one_18 = 0x65,
- DBG_CLIENT_BLKID_gdc_one_19 = 0x66,
- DBG_CLIENT_BLKID_gdc_one_20 = 0x67,
- DBG_CLIENT_BLKID_gdc_one_21 = 0x68,
- DBG_CLIENT_BLKID_gdc_one_22 = 0x69,
- DBG_CLIENT_BLKID_gdc_one_23 = 0x6a,
- DBG_CLIENT_BLKID_gdc_one_24 = 0x6b,
- DBG_CLIENT_BLKID_gdc_one_25 = 0x6c,
- DBG_CLIENT_BLKID_gdc_one_26 = 0x6d,
- DBG_CLIENT_BLKID_gdc_one_27 = 0x6e,
- DBG_CLIENT_BLKID_gdc_one_28 = 0x6f,
- DBG_CLIENT_BLKID_gdc_one_29 = 0x70,
- DBG_CLIENT_BLKID_gdc_one_30 = 0x71,
- DBG_CLIENT_BLKID_gdc_one_31 = 0x72,
- DBG_CLIENT_BLKID_gdc_one_32 = 0x73,
- DBG_CLIENT_BLKID_gdc_one_33 = 0x74,
- DBG_CLIENT_BLKID_gdc_one_34 = 0x75,
- DBG_CLIENT_BLKID_gdc_one_35 = 0x76,
- DBG_CLIENT_BLKID_vceb0_0 = 0x77,
- DBG_CLIENT_BLKID_vgt3 = 0x78,
- DBG_CLIENT_BLKID_pc3 = 0x79,
- DBG_CLIENT_BLKID_mcd3 = 0x7a,
- DBG_CLIENT_BLKID_uvdu_0 = 0x7b,
- DBG_CLIENT_BLKID_uvdu_1 = 0x7c,
- DBG_CLIENT_BLKID_uvdu_2 = 0x7d,
- DBG_CLIENT_BLKID_uvdu_3 = 0x7e,
- DBG_CLIENT_BLKID_uvdu_4 = 0x7f,
- DBG_CLIENT_BLKID_uvdu_5 = 0x80,
- DBG_CLIENT_BLKID_uvdu_6 = 0x81,
- DBG_CLIENT_BLKID_cb300 = 0x82,
- DBG_CLIENT_BLKID_mcd1 = 0x83,
- DBG_CLIENT_BLKID_sx00 = 0x84,
- DBG_CLIENT_BLKID_uvdf_0 = 0x85,
- DBG_CLIENT_BLKID_uvdf_1 = 0x86,
- DBG_CLIENT_BLKID_mcc3 = 0x87,
- DBG_CLIENT_BLKID_cpg_0 = 0x88,
- DBG_CLIENT_BLKID_cpg_1 = 0x89,
- DBG_CLIENT_BLKID_gck = 0x8a,
- DBG_CLIENT_BLKID_mcc1 = 0x8b,
- DBG_CLIENT_BLKID_cpf_0 = 0x8c,
- DBG_CLIENT_BLKID_cpf_1 = 0x8d,
- DBG_CLIENT_BLKID_rlc = 0x8e,
- DBG_CLIENT_BLKID_grbm = 0x8f,
- DBG_CLIENT_BLKID_sammsp = 0x90,
- DBG_CLIENT_BLKID_dci_pg = 0x91,
- DBG_CLIENT_BLKID_dci_0 = 0x92,
- DBG_CLIENT_BLKID_dccg0_0 = 0x93,
- DBG_CLIENT_BLKID_dccg0_1 = 0x94,
- DBG_CLIENT_BLKID_dccg0_2 = 0x95,
- DBG_CLIENT_BLKID_dccg0_3 = 0x96,
- DBG_CLIENT_BLKID_dccg0_4 = 0x97,
- DBG_CLIENT_BLKID_dccg0_5 = 0x98,
- DBG_CLIENT_BLKID_dccg0_6 = 0x99,
- DBG_CLIENT_BLKID_dccg0_7 = 0x9a,
- DBG_CLIENT_BLKID_dccg0_8 = 0x9b,
- DBG_CLIENT_BLKID_dcfe01_0 = 0x9c,
- DBG_CLIENT_BLKID_dcfe02_0 = 0x9d,
- DBG_CLIENT_BLKID_dcfe03_0 = 0x9e,
- DBG_CLIENT_BLKID_dcfe04_0 = 0x9f,
- DBG_CLIENT_BLKID_dcfe05_0 = 0xa0,
- DBG_CLIENT_BLKID_dcfe06_0 = 0xa1,
- DBG_CLIENT_BLKID_uvde_0 = 0xa2,
- DBG_CLIENT_BLKID_RESERVED_LAST = 0xa3,
-} DebugBlockId;
-typedef enum DebugBlockId_OLD {
- DBG_BLOCK_ID_RESERVED = 0x0,
- DBG_BLOCK_ID_DBG = 0x1,
- DBG_BLOCK_ID_VMC = 0x2,
- DBG_BLOCK_ID_PDMA = 0x3,
- DBG_BLOCK_ID_CG = 0x4,
- DBG_BLOCK_ID_SRBM = 0x5,
- DBG_BLOCK_ID_GRBM = 0x6,
- DBG_BLOCK_ID_RLC = 0x7,
- DBG_BLOCK_ID_CSC = 0x8,
- DBG_BLOCK_ID_SEM = 0x9,
- DBG_BLOCK_ID_IH = 0xa,
- DBG_BLOCK_ID_SC = 0xb,
- DBG_BLOCK_ID_SQ = 0xc,
- DBG_BLOCK_ID_AVP = 0xd,
- DBG_BLOCK_ID_GMCON = 0xe,
- DBG_BLOCK_ID_SMU = 0xf,
- DBG_BLOCK_ID_DMA0 = 0x10,
- DBG_BLOCK_ID_DMA1 = 0x11,
- DBG_BLOCK_ID_SPIM = 0x12,
- DBG_BLOCK_ID_GDS = 0x13,
- DBG_BLOCK_ID_SPIS = 0x14,
- DBG_BLOCK_ID_UNUSED0 = 0x15,
- DBG_BLOCK_ID_PA0 = 0x16,
- DBG_BLOCK_ID_PA1 = 0x17,
- DBG_BLOCK_ID_CP0 = 0x18,
- DBG_BLOCK_ID_CP1 = 0x19,
- DBG_BLOCK_ID_CP2 = 0x1a,
- DBG_BLOCK_ID_UNUSED1 = 0x1b,
- DBG_BLOCK_ID_UVDU = 0x1c,
- DBG_BLOCK_ID_UVDM = 0x1d,
- DBG_BLOCK_ID_VCE = 0x1e,
- DBG_BLOCK_ID_UNUSED2 = 0x1f,
- DBG_BLOCK_ID_VGT0 = 0x20,
- DBG_BLOCK_ID_VGT1 = 0x21,
- DBG_BLOCK_ID_IA = 0x22,
- DBG_BLOCK_ID_UNUSED3 = 0x23,
- DBG_BLOCK_ID_SCT0 = 0x24,
- DBG_BLOCK_ID_SCT1 = 0x25,
- DBG_BLOCK_ID_SPM0 = 0x26,
- DBG_BLOCK_ID_SPM1 = 0x27,
- DBG_BLOCK_ID_TCAA = 0x28,
- DBG_BLOCK_ID_TCAB = 0x29,
- DBG_BLOCK_ID_TCCA = 0x2a,
- DBG_BLOCK_ID_TCCB = 0x2b,
- DBG_BLOCK_ID_MCC0 = 0x2c,
- DBG_BLOCK_ID_MCC1 = 0x2d,
- DBG_BLOCK_ID_MCC2 = 0x2e,
- DBG_BLOCK_ID_MCC3 = 0x2f,
- DBG_BLOCK_ID_SX0 = 0x30,
- DBG_BLOCK_ID_SX1 = 0x31,
- DBG_BLOCK_ID_SX2 = 0x32,
- DBG_BLOCK_ID_SX3 = 0x33,
- DBG_BLOCK_ID_UNUSED4 = 0x34,
- DBG_BLOCK_ID_UNUSED5 = 0x35,
- DBG_BLOCK_ID_UNUSED6 = 0x36,
- DBG_BLOCK_ID_UNUSED7 = 0x37,
- DBG_BLOCK_ID_PC0 = 0x38,
- DBG_BLOCK_ID_PC1 = 0x39,
- DBG_BLOCK_ID_UNUSED8 = 0x3a,
- DBG_BLOCK_ID_UNUSED9 = 0x3b,
- DBG_BLOCK_ID_UNUSED10 = 0x3c,
- DBG_BLOCK_ID_UNUSED11 = 0x3d,
- DBG_BLOCK_ID_MCB = 0x3e,
- DBG_BLOCK_ID_UNUSED12 = 0x3f,
- DBG_BLOCK_ID_SCB0 = 0x40,
- DBG_BLOCK_ID_SCB1 = 0x41,
- DBG_BLOCK_ID_UNUSED13 = 0x42,
- DBG_BLOCK_ID_UNUSED14 = 0x43,
- DBG_BLOCK_ID_SCF0 = 0x44,
- DBG_BLOCK_ID_SCF1 = 0x45,
- DBG_BLOCK_ID_UNUSED15 = 0x46,
- DBG_BLOCK_ID_UNUSED16 = 0x47,
- DBG_BLOCK_ID_BCI0 = 0x48,
- DBG_BLOCK_ID_BCI1 = 0x49,
- DBG_BLOCK_ID_BCI2 = 0x4a,
- DBG_BLOCK_ID_BCI3 = 0x4b,
- DBG_BLOCK_ID_UNUSED17 = 0x4c,
- DBG_BLOCK_ID_UNUSED18 = 0x4d,
- DBG_BLOCK_ID_UNUSED19 = 0x4e,
- DBG_BLOCK_ID_UNUSED20 = 0x4f,
- DBG_BLOCK_ID_CB00 = 0x50,
- DBG_BLOCK_ID_CB01 = 0x51,
- DBG_BLOCK_ID_CB02 = 0x52,
- DBG_BLOCK_ID_CB03 = 0x53,
- DBG_BLOCK_ID_CB04 = 0x54,
- DBG_BLOCK_ID_UNUSED21 = 0x55,
- DBG_BLOCK_ID_UNUSED22 = 0x56,
- DBG_BLOCK_ID_UNUSED23 = 0x57,
- DBG_BLOCK_ID_CB10 = 0x58,
- DBG_BLOCK_ID_CB11 = 0x59,
- DBG_BLOCK_ID_CB12 = 0x5a,
- DBG_BLOCK_ID_CB13 = 0x5b,
- DBG_BLOCK_ID_CB14 = 0x5c,
- DBG_BLOCK_ID_UNUSED24 = 0x5d,
- DBG_BLOCK_ID_UNUSED25 = 0x5e,
- DBG_BLOCK_ID_UNUSED26 = 0x5f,
- DBG_BLOCK_ID_TCP0 = 0x60,
- DBG_BLOCK_ID_TCP1 = 0x61,
- DBG_BLOCK_ID_TCP2 = 0x62,
- DBG_BLOCK_ID_TCP3 = 0x63,
- DBG_BLOCK_ID_TCP4 = 0x64,
- DBG_BLOCK_ID_TCP5 = 0x65,
- DBG_BLOCK_ID_TCP6 = 0x66,
- DBG_BLOCK_ID_TCP7 = 0x67,
- DBG_BLOCK_ID_TCP8 = 0x68,
- DBG_BLOCK_ID_TCP9 = 0x69,
- DBG_BLOCK_ID_TCP10 = 0x6a,
- DBG_BLOCK_ID_TCP11 = 0x6b,
- DBG_BLOCK_ID_TCP12 = 0x6c,
- DBG_BLOCK_ID_TCP13 = 0x6d,
- DBG_BLOCK_ID_TCP14 = 0x6e,
- DBG_BLOCK_ID_TCP15 = 0x6f,
- DBG_BLOCK_ID_TCP16 = 0x70,
- DBG_BLOCK_ID_TCP17 = 0x71,
- DBG_BLOCK_ID_TCP18 = 0x72,
- DBG_BLOCK_ID_TCP19 = 0x73,
- DBG_BLOCK_ID_TCP20 = 0x74,
- DBG_BLOCK_ID_TCP21 = 0x75,
- DBG_BLOCK_ID_TCP22 = 0x76,
- DBG_BLOCK_ID_TCP23 = 0x77,
- DBG_BLOCK_ID_TCP_RESERVED0 = 0x78,
- DBG_BLOCK_ID_TCP_RESERVED1 = 0x79,
- DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a,
- DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b,
- DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c,
- DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d,
- DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e,
- DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f,
- DBG_BLOCK_ID_DB00 = 0x80,
- DBG_BLOCK_ID_DB01 = 0x81,
- DBG_BLOCK_ID_DB02 = 0x82,
- DBG_BLOCK_ID_DB03 = 0x83,
- DBG_BLOCK_ID_DB04 = 0x84,
- DBG_BLOCK_ID_UNUSED27 = 0x85,
- DBG_BLOCK_ID_UNUSED28 = 0x86,
- DBG_BLOCK_ID_UNUSED29 = 0x87,
- DBG_BLOCK_ID_DB10 = 0x88,
- DBG_BLOCK_ID_DB11 = 0x89,
- DBG_BLOCK_ID_DB12 = 0x8a,
- DBG_BLOCK_ID_DB13 = 0x8b,
- DBG_BLOCK_ID_DB14 = 0x8c,
- DBG_BLOCK_ID_UNUSED30 = 0x8d,
- DBG_BLOCK_ID_UNUSED31 = 0x8e,
- DBG_BLOCK_ID_UNUSED32 = 0x8f,
- DBG_BLOCK_ID_TCC0 = 0x90,
- DBG_BLOCK_ID_TCC1 = 0x91,
- DBG_BLOCK_ID_TCC2 = 0x92,
- DBG_BLOCK_ID_TCC3 = 0x93,
- DBG_BLOCK_ID_TCC4 = 0x94,
- DBG_BLOCK_ID_TCC5 = 0x95,
- DBG_BLOCK_ID_TCC6 = 0x96,
- DBG_BLOCK_ID_TCC7 = 0x97,
- DBG_BLOCK_ID_SPS00 = 0x98,
- DBG_BLOCK_ID_SPS01 = 0x99,
- DBG_BLOCK_ID_SPS02 = 0x9a,
- DBG_BLOCK_ID_SPS10 = 0x9b,
- DBG_BLOCK_ID_SPS11 = 0x9c,
- DBG_BLOCK_ID_SPS12 = 0x9d,
- DBG_BLOCK_ID_UNUSED33 = 0x9e,
- DBG_BLOCK_ID_UNUSED34 = 0x9f,
- DBG_BLOCK_ID_TA00 = 0xa0,
- DBG_BLOCK_ID_TA01 = 0xa1,
- DBG_BLOCK_ID_TA02 = 0xa2,
- DBG_BLOCK_ID_TA03 = 0xa3,
- DBG_BLOCK_ID_TA04 = 0xa4,
- DBG_BLOCK_ID_TA05 = 0xa5,
- DBG_BLOCK_ID_TA06 = 0xa6,
- DBG_BLOCK_ID_TA07 = 0xa7,
- DBG_BLOCK_ID_TA08 = 0xa8,
- DBG_BLOCK_ID_TA09 = 0xa9,
- DBG_BLOCK_ID_TA0A = 0xaa,
- DBG_BLOCK_ID_TA0B = 0xab,
- DBG_BLOCK_ID_UNUSED35 = 0xac,
- DBG_BLOCK_ID_UNUSED36 = 0xad,
- DBG_BLOCK_ID_UNUSED37 = 0xae,
- DBG_BLOCK_ID_UNUSED38 = 0xaf,
- DBG_BLOCK_ID_TA10 = 0xb0,
- DBG_BLOCK_ID_TA11 = 0xb1,
- DBG_BLOCK_ID_TA12 = 0xb2,
- DBG_BLOCK_ID_TA13 = 0xb3,
- DBG_BLOCK_ID_TA14 = 0xb4,
- DBG_BLOCK_ID_TA15 = 0xb5,
- DBG_BLOCK_ID_TA16 = 0xb6,
- DBG_BLOCK_ID_TA17 = 0xb7,
- DBG_BLOCK_ID_TA18 = 0xb8,
- DBG_BLOCK_ID_TA19 = 0xb9,
- DBG_BLOCK_ID_TA1A = 0xba,
- DBG_BLOCK_ID_TA1B = 0xbb,
- DBG_BLOCK_ID_UNUSED39 = 0xbc,
- DBG_BLOCK_ID_UNUSED40 = 0xbd,
- DBG_BLOCK_ID_UNUSED41 = 0xbe,
- DBG_BLOCK_ID_UNUSED42 = 0xbf,
- DBG_BLOCK_ID_TD00 = 0xc0,
- DBG_BLOCK_ID_TD01 = 0xc1,
- DBG_BLOCK_ID_TD02 = 0xc2,
- DBG_BLOCK_ID_TD03 = 0xc3,
- DBG_BLOCK_ID_TD04 = 0xc4,
- DBG_BLOCK_ID_TD05 = 0xc5,
- DBG_BLOCK_ID_TD06 = 0xc6,
- DBG_BLOCK_ID_TD07 = 0xc7,
- DBG_BLOCK_ID_TD08 = 0xc8,
- DBG_BLOCK_ID_TD09 = 0xc9,
- DBG_BLOCK_ID_TD0A = 0xca,
- DBG_BLOCK_ID_TD0B = 0xcb,
- DBG_BLOCK_ID_UNUSED43 = 0xcc,
- DBG_BLOCK_ID_UNUSED44 = 0xcd,
- DBG_BLOCK_ID_UNUSED45 = 0xce,
- DBG_BLOCK_ID_UNUSED46 = 0xcf,
- DBG_BLOCK_ID_TD10 = 0xd0,
- DBG_BLOCK_ID_TD11 = 0xd1,
- DBG_BLOCK_ID_TD12 = 0xd2,
- DBG_BLOCK_ID_TD13 = 0xd3,
- DBG_BLOCK_ID_TD14 = 0xd4,
- DBG_BLOCK_ID_TD15 = 0xd5,
- DBG_BLOCK_ID_TD16 = 0xd6,
- DBG_BLOCK_ID_TD17 = 0xd7,
- DBG_BLOCK_ID_TD18 = 0xd8,
- DBG_BLOCK_ID_TD19 = 0xd9,
- DBG_BLOCK_ID_TD1A = 0xda,
- DBG_BLOCK_ID_TD1B = 0xdb,
- DBG_BLOCK_ID_UNUSED47 = 0xdc,
- DBG_BLOCK_ID_UNUSED48 = 0xdd,
- DBG_BLOCK_ID_UNUSED49 = 0xde,
- DBG_BLOCK_ID_UNUSED50 = 0xdf,
- DBG_BLOCK_ID_MCD0 = 0xe0,
- DBG_BLOCK_ID_MCD1 = 0xe1,
- DBG_BLOCK_ID_MCD2 = 0xe2,
- DBG_BLOCK_ID_MCD3 = 0xe3,
- DBG_BLOCK_ID_MCD4 = 0xe4,
- DBG_BLOCK_ID_MCD5 = 0xe5,
- DBG_BLOCK_ID_UNUSED51 = 0xe6,
- DBG_BLOCK_ID_UNUSED52 = 0xe7,
-} DebugBlockId_OLD;
-typedef enum DebugBlockId_BY2 {
- DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
- DBG_BLOCK_ID_VMC_BY2 = 0x1,
- DBG_BLOCK_ID_CG_BY2 = 0x2,
- DBG_BLOCK_ID_GRBM_BY2 = 0x3,
- DBG_BLOCK_ID_CSC_BY2 = 0x4,
- DBG_BLOCK_ID_IH_BY2 = 0x5,
- DBG_BLOCK_ID_SQ_BY2 = 0x6,
- DBG_BLOCK_ID_GMCON_BY2 = 0x7,
- DBG_BLOCK_ID_DMA0_BY2 = 0x8,
- DBG_BLOCK_ID_SPIM_BY2 = 0x9,
- DBG_BLOCK_ID_SPIS_BY2 = 0xa,
- DBG_BLOCK_ID_PA0_BY2 = 0xb,
- DBG_BLOCK_ID_CP0_BY2 = 0xc,
- DBG_BLOCK_ID_CP2_BY2 = 0xd,
- DBG_BLOCK_ID_UVDU_BY2 = 0xe,
- DBG_BLOCK_ID_VCE_BY2 = 0xf,
- DBG_BLOCK_ID_VGT0_BY2 = 0x10,
- DBG_BLOCK_ID_IA_BY2 = 0x11,
- DBG_BLOCK_ID_SCT0_BY2 = 0x12,
- DBG_BLOCK_ID_SPM0_BY2 = 0x13,
- DBG_BLOCK_ID_TCAA_BY2 = 0x14,
- DBG_BLOCK_ID_TCCA_BY2 = 0x15,
- DBG_BLOCK_ID_MCC0_BY2 = 0x16,
- DBG_BLOCK_ID_MCC2_BY2 = 0x17,
- DBG_BLOCK_ID_SX0_BY2 = 0x18,
- DBG_BLOCK_ID_SX2_BY2 = 0x19,
- DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a,
- DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b,
- DBG_BLOCK_ID_PC0_BY2 = 0x1c,
- DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d,
- DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e,
- DBG_BLOCK_ID_MCB_BY2 = 0x1f,
- DBG_BLOCK_ID_SCB0_BY2 = 0x20,
- DBG_BLOCK_ID_UNUSED13_BY2 = 0x21,
- DBG_BLOCK_ID_SCF0_BY2 = 0x22,
- DBG_BLOCK_ID_UNUSED15_BY2 = 0x23,
- DBG_BLOCK_ID_BCI0_BY2 = 0x24,
- DBG_BLOCK_ID_BCI2_BY2 = 0x25,
- DBG_BLOCK_ID_UNUSED17_BY2 = 0x26,
- DBG_BLOCK_ID_UNUSED19_BY2 = 0x27,
- DBG_BLOCK_ID_CB00_BY2 = 0x28,
- DBG_BLOCK_ID_CB02_BY2 = 0x29,
- DBG_BLOCK_ID_CB04_BY2 = 0x2a,
- DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b,
- DBG_BLOCK_ID_CB10_BY2 = 0x2c,
- DBG_BLOCK_ID_CB12_BY2 = 0x2d,
- DBG_BLOCK_ID_CB14_BY2 = 0x2e,
- DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f,
- DBG_BLOCK_ID_TCP0_BY2 = 0x30,
- DBG_BLOCK_ID_TCP2_BY2 = 0x31,
- DBG_BLOCK_ID_TCP4_BY2 = 0x32,
- DBG_BLOCK_ID_TCP6_BY2 = 0x33,
- DBG_BLOCK_ID_TCP8_BY2 = 0x34,
- DBG_BLOCK_ID_TCP10_BY2 = 0x35,
- DBG_BLOCK_ID_TCP12_BY2 = 0x36,
- DBG_BLOCK_ID_TCP14_BY2 = 0x37,
- DBG_BLOCK_ID_TCP16_BY2 = 0x38,
- DBG_BLOCK_ID_TCP18_BY2 = 0x39,
- DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
- DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
- DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
- DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
- DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
- DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
- DBG_BLOCK_ID_DB00_BY2 = 0x40,
- DBG_BLOCK_ID_DB02_BY2 = 0x41,
- DBG_BLOCK_ID_DB04_BY2 = 0x42,
- DBG_BLOCK_ID_UNUSED28_BY2 = 0x43,
- DBG_BLOCK_ID_DB10_BY2 = 0x44,
- DBG_BLOCK_ID_DB12_BY2 = 0x45,
- DBG_BLOCK_ID_DB14_BY2 = 0x46,
- DBG_BLOCK_ID_UNUSED31_BY2 = 0x47,
- DBG_BLOCK_ID_TCC0_BY2 = 0x48,
- DBG_BLOCK_ID_TCC2_BY2 = 0x49,
- DBG_BLOCK_ID_TCC4_BY2 = 0x4a,
- DBG_BLOCK_ID_TCC6_BY2 = 0x4b,
- DBG_BLOCK_ID_SPS00_BY2 = 0x4c,
- DBG_BLOCK_ID_SPS02_BY2 = 0x4d,
- DBG_BLOCK_ID_SPS11_BY2 = 0x4e,
- DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f,
- DBG_BLOCK_ID_TA00_BY2 = 0x50,
- DBG_BLOCK_ID_TA02_BY2 = 0x51,
- DBG_BLOCK_ID_TA04_BY2 = 0x52,
- DBG_BLOCK_ID_TA06_BY2 = 0x53,
- DBG_BLOCK_ID_TA08_BY2 = 0x54,
- DBG_BLOCK_ID_TA0A_BY2 = 0x55,
- DBG_BLOCK_ID_UNUSED35_BY2 = 0x56,
- DBG_BLOCK_ID_UNUSED37_BY2 = 0x57,
- DBG_BLOCK_ID_TA10_BY2 = 0x58,
- DBG_BLOCK_ID_TA12_BY2 = 0x59,
- DBG_BLOCK_ID_TA14_BY2 = 0x5a,
- DBG_BLOCK_ID_TA16_BY2 = 0x5b,
- DBG_BLOCK_ID_TA18_BY2 = 0x5c,
- DBG_BLOCK_ID_TA1A_BY2 = 0x5d,
- DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e,
- DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f,
- DBG_BLOCK_ID_TD00_BY2 = 0x60,
- DBG_BLOCK_ID_TD02_BY2 = 0x61,
- DBG_BLOCK_ID_TD04_BY2 = 0x62,
- DBG_BLOCK_ID_TD06_BY2 = 0x63,
- DBG_BLOCK_ID_TD08_BY2 = 0x64,
- DBG_BLOCK_ID_TD0A_BY2 = 0x65,
- DBG_BLOCK_ID_UNUSED43_BY2 = 0x66,
- DBG_BLOCK_ID_UNUSED45_BY2 = 0x67,
- DBG_BLOCK_ID_TD10_BY2 = 0x68,
- DBG_BLOCK_ID_TD12_BY2 = 0x69,
- DBG_BLOCK_ID_TD14_BY2 = 0x6a,
- DBG_BLOCK_ID_TD16_BY2 = 0x6b,
- DBG_BLOCK_ID_TD18_BY2 = 0x6c,
- DBG_BLOCK_ID_TD1A_BY2 = 0x6d,
- DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e,
- DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f,
- DBG_BLOCK_ID_MCD0_BY2 = 0x70,
- DBG_BLOCK_ID_MCD2_BY2 = 0x71,
- DBG_BLOCK_ID_MCD4_BY2 = 0x72,
- DBG_BLOCK_ID_UNUSED51_BY2 = 0x73,
-} DebugBlockId_BY2;
-typedef enum DebugBlockId_BY4 {
- DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
- DBG_BLOCK_ID_CG_BY4 = 0x1,
- DBG_BLOCK_ID_CSC_BY4 = 0x2,
- DBG_BLOCK_ID_SQ_BY4 = 0x3,
- DBG_BLOCK_ID_DMA0_BY4 = 0x4,
- DBG_BLOCK_ID_SPIS_BY4 = 0x5,
- DBG_BLOCK_ID_CP0_BY4 = 0x6,
- DBG_BLOCK_ID_UVDU_BY4 = 0x7,
- DBG_BLOCK_ID_VGT0_BY4 = 0x8,
- DBG_BLOCK_ID_SCT0_BY4 = 0x9,
- DBG_BLOCK_ID_TCAA_BY4 = 0xa,
- DBG_BLOCK_ID_MCC0_BY4 = 0xb,
- DBG_BLOCK_ID_SX0_BY4 = 0xc,
- DBG_BLOCK_ID_UNUSED4_BY4 = 0xd,
- DBG_BLOCK_ID_PC0_BY4 = 0xe,
- DBG_BLOCK_ID_UNUSED10_BY4 = 0xf,
- DBG_BLOCK_ID_SCB0_BY4 = 0x10,
- DBG_BLOCK_ID_SCF0_BY4 = 0x11,
- DBG_BLOCK_ID_BCI0_BY4 = 0x12,
- DBG_BLOCK_ID_UNUSED17_BY4 = 0x13,
- DBG_BLOCK_ID_CB00_BY4 = 0x14,
- DBG_BLOCK_ID_CB04_BY4 = 0x15,
- DBG_BLOCK_ID_CB10_BY4 = 0x16,
- DBG_BLOCK_ID_CB14_BY4 = 0x17,
- DBG_BLOCK_ID_TCP0_BY4 = 0x18,
- DBG_BLOCK_ID_TCP4_BY4 = 0x19,
- DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
- DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
- DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
- DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
- DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
- DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
- DBG_BLOCK_ID_DB_BY4 = 0x20,
- DBG_BLOCK_ID_DB04_BY4 = 0x21,
- DBG_BLOCK_ID_DB10_BY4 = 0x22,
- DBG_BLOCK_ID_DB14_BY4 = 0x23,
- DBG_BLOCK_ID_TCC0_BY4 = 0x24,
- DBG_BLOCK_ID_TCC4_BY4 = 0x25,
- DBG_BLOCK_ID_SPS00_BY4 = 0x26,
- DBG_BLOCK_ID_SPS11_BY4 = 0x27,
- DBG_BLOCK_ID_TA00_BY4 = 0x28,
- DBG_BLOCK_ID_TA04_BY4 = 0x29,
- DBG_BLOCK_ID_TA08_BY4 = 0x2a,
- DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b,
- DBG_BLOCK_ID_TA10_BY4 = 0x2c,
- DBG_BLOCK_ID_TA14_BY4 = 0x2d,
- DBG_BLOCK_ID_TA18_BY4 = 0x2e,
- DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f,
- DBG_BLOCK_ID_TD00_BY4 = 0x30,
- DBG_BLOCK_ID_TD04_BY4 = 0x31,
- DBG_BLOCK_ID_TD08_BY4 = 0x32,
- DBG_BLOCK_ID_UNUSED43_BY4 = 0x33,
- DBG_BLOCK_ID_TD10_BY4 = 0x34,
- DBG_BLOCK_ID_TD14_BY4 = 0x35,
- DBG_BLOCK_ID_TD18_BY4 = 0x36,
- DBG_BLOCK_ID_UNUSED47_BY4 = 0x37,
- DBG_BLOCK_ID_MCD0_BY4 = 0x38,
- DBG_BLOCK_ID_MCD4_BY4 = 0x39,
-} DebugBlockId_BY4;
-typedef enum DebugBlockId_BY8 {
- DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
- DBG_BLOCK_ID_CSC_BY8 = 0x1,
- DBG_BLOCK_ID_DMA0_BY8 = 0x2,
- DBG_BLOCK_ID_CP0_BY8 = 0x3,
- DBG_BLOCK_ID_VGT0_BY8 = 0x4,
- DBG_BLOCK_ID_TCAA_BY8 = 0x5,
- DBG_BLOCK_ID_SX0_BY8 = 0x6,
- DBG_BLOCK_ID_PC0_BY8 = 0x7,
- DBG_BLOCK_ID_SCB0_BY8 = 0x8,
- DBG_BLOCK_ID_BCI0_BY8 = 0x9,
- DBG_BLOCK_ID_CB00_BY8 = 0xa,
- DBG_BLOCK_ID_CB10_BY8 = 0xb,
- DBG_BLOCK_ID_TCP0_BY8 = 0xc,
- DBG_BLOCK_ID_TCP8_BY8 = 0xd,
- DBG_BLOCK_ID_TCP16_BY8 = 0xe,
- DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
- DBG_BLOCK_ID_DB00_BY8 = 0x10,
- DBG_BLOCK_ID_DB10_BY8 = 0x11,
- DBG_BLOCK_ID_TCC0_BY8 = 0x12,
- DBG_BLOCK_ID_SPS00_BY8 = 0x13,
- DBG_BLOCK_ID_TA00_BY8 = 0x14,
- DBG_BLOCK_ID_TA08_BY8 = 0x15,
- DBG_BLOCK_ID_TA10_BY8 = 0x16,
- DBG_BLOCK_ID_TA18_BY8 = 0x17,
- DBG_BLOCK_ID_TD00_BY8 = 0x18,
- DBG_BLOCK_ID_TD08_BY8 = 0x19,
- DBG_BLOCK_ID_TD10_BY8 = 0x1a,
- DBG_BLOCK_ID_TD18_BY8 = 0x1b,
- DBG_BLOCK_ID_MCD0_BY8 = 0x1c,
-} DebugBlockId_BY8;
-typedef enum DebugBlockId_BY16 {
- DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
- DBG_BLOCK_ID_DMA0_BY16 = 0x1,
- DBG_BLOCK_ID_VGT0_BY16 = 0x2,
- DBG_BLOCK_ID_SX0_BY16 = 0x3,
- DBG_BLOCK_ID_SCB0_BY16 = 0x4,
- DBG_BLOCK_ID_CB00_BY16 = 0x5,
- DBG_BLOCK_ID_TCP0_BY16 = 0x6,
- DBG_BLOCK_ID_TCP16_BY16 = 0x7,
- DBG_BLOCK_ID_DB00_BY16 = 0x8,
- DBG_BLOCK_ID_TCC0_BY16 = 0x9,
- DBG_BLOCK_ID_TA00_BY16 = 0xa,
- DBG_BLOCK_ID_TA10_BY16 = 0xb,
- DBG_BLOCK_ID_TD00_BY16 = 0xc,
- DBG_BLOCK_ID_TD10_BY16 = 0xd,
- DBG_BLOCK_ID_MCD0_BY16 = 0xe,
-} DebugBlockId_BY16;
-typedef enum ColorTransform {
- DCC_CT_AUTO = 0x0,
- DCC_CT_NONE = 0x1,
- ABGR_TO_A_BG_G_RB = 0x2,
- BGRA_TO_BG_G_RB_A = 0x3,
-} ColorTransform;
-typedef enum CompareRef {
- REF_NEVER = 0x0,
- REF_LESS = 0x1,
- REF_EQUAL = 0x2,
- REF_LEQUAL = 0x3,
- REF_GREATER = 0x4,
- REF_NOTEQUAL = 0x5,
- REF_GEQUAL = 0x6,
- REF_ALWAYS = 0x7,
-} CompareRef;
-typedef enum ReadSize {
- READ_256_BITS = 0x0,
- READ_512_BITS = 0x1,
-} ReadSize;
-typedef enum DepthFormat {
- DEPTH_INVALID = 0x0,
- DEPTH_16 = 0x1,
- DEPTH_X8_24 = 0x2,
- DEPTH_8_24 = 0x3,
- DEPTH_X8_24_FLOAT = 0x4,
- DEPTH_8_24_FLOAT = 0x5,
- DEPTH_32_FLOAT = 0x6,
- DEPTH_X24_8_32_FLOAT = 0x7,
-} DepthFormat;
-typedef enum ZFormat {
- Z_INVALID = 0x0,
- Z_16 = 0x1,
- Z_24 = 0x2,
- Z_32_FLOAT = 0x3,
-} ZFormat;
-typedef enum StencilFormat {
- STENCIL_INVALID = 0x0,
- STENCIL_8 = 0x1,
-} StencilFormat;
-typedef enum CmaskMode {
- CMASK_CLEAR_NONE = 0x0,
- CMASK_CLEAR_ONE = 0x1,
- CMASK_CLEAR_ALL = 0x2,
- CMASK_ANY_EXPANDED = 0x3,
- CMASK_ALPHA0_FRAG1 = 0x4,
- CMASK_ALPHA0_FRAG2 = 0x5,
- CMASK_ALPHA0_FRAG4 = 0x6,
- CMASK_ALPHA0_FRAGS = 0x7,
- CMASK_ALPHA1_FRAG1 = 0x8,
- CMASK_ALPHA1_FRAG2 = 0x9,
- CMASK_ALPHA1_FRAG4 = 0xa,
- CMASK_ALPHA1_FRAGS = 0xb,
- CMASK_ALPHAX_FRAG1 = 0xc,
- CMASK_ALPHAX_FRAG2 = 0xd,
- CMASK_ALPHAX_FRAG4 = 0xe,
- CMASK_ALPHAX_FRAGS = 0xf,
-} CmaskMode;
-typedef enum QuadExportFormat {
- EXPORT_UNUSED = 0x0,
- EXPORT_32_R = 0x1,
- EXPORT_32_GR = 0x2,
- EXPORT_32_AR = 0x3,
- EXPORT_FP16_ABGR = 0x4,
- EXPORT_UNSIGNED16_ABGR = 0x5,
- EXPORT_SIGNED16_ABGR = 0x6,
- EXPORT_32_ABGR = 0x7,
-} QuadExportFormat;
-typedef enum QuadExportFormatOld {
- EXPORT_4P_32BPC_ABGR = 0x0,
- EXPORT_4P_16BPC_ABGR = 0x1,
- EXPORT_4P_32BPC_GR = 0x2,
- EXPORT_4P_32BPC_AR = 0x3,
- EXPORT_2P_32BPC_ABGR = 0x4,
- EXPORT_8P_32BPC_R = 0x5,
-} QuadExportFormatOld;
-typedef enum ColorFormat {
- COLOR_INVALID = 0x0,
- COLOR_8 = 0x1,
- COLOR_16 = 0x2,
- COLOR_8_8 = 0x3,
- COLOR_32 = 0x4,
- COLOR_16_16 = 0x5,
- COLOR_10_11_11 = 0x6,
- COLOR_11_11_10 = 0x7,
- COLOR_10_10_10_2 = 0x8,
- COLOR_2_10_10_10 = 0x9,
- COLOR_8_8_8_8 = 0xa,
- COLOR_32_32 = 0xb,
- COLOR_16_16_16_16 = 0xc,
- COLOR_RESERVED_13 = 0xd,
- COLOR_32_32_32_32 = 0xe,
- COLOR_RESERVED_15 = 0xf,
- COLOR_5_6_5 = 0x10,
- COLOR_1_5_5_5 = 0x11,
- COLOR_5_5_5_1 = 0x12,
- COLOR_4_4_4_4 = 0x13,
- COLOR_8_24 = 0x14,
- COLOR_24_8 = 0x15,
- COLOR_X24_8_32_FLOAT = 0x16,
- COLOR_RESERVED_23 = 0x17,
-} ColorFormat;
-typedef enum SurfaceFormat {
- FMT_INVALID = 0x0,
- FMT_8 = 0x1,
- FMT_16 = 0x2,
- FMT_8_8 = 0x3,
- FMT_32 = 0x4,
- FMT_16_16 = 0x5,
- FMT_10_11_11 = 0x6,
- FMT_11_11_10 = 0x7,
- FMT_10_10_10_2 = 0x8,
- FMT_2_10_10_10 = 0x9,
- FMT_8_8_8_8 = 0xa,
- FMT_32_32 = 0xb,
- FMT_16_16_16_16 = 0xc,
- FMT_32_32_32 = 0xd,
- FMT_32_32_32_32 = 0xe,
- FMT_RESERVED_4 = 0xf,
- FMT_5_6_5 = 0x10,
- FMT_1_5_5_5 = 0x11,
- FMT_5_5_5_1 = 0x12,
- FMT_4_4_4_4 = 0x13,
- FMT_8_24 = 0x14,
- FMT_24_8 = 0x15,
- FMT_X24_8_32_FLOAT = 0x16,
- FMT_RESERVED_33 = 0x17,
- FMT_11_11_10_FLOAT = 0x18,
- FMT_16_FLOAT = 0x19,
- FMT_32_FLOAT = 0x1a,
- FMT_16_16_FLOAT = 0x1b,
- FMT_8_24_FLOAT = 0x1c,
- FMT_24_8_FLOAT = 0x1d,
- FMT_32_32_FLOAT = 0x1e,
- FMT_10_11_11_FLOAT = 0x1f,
- FMT_16_16_16_16_FLOAT = 0x20,
- FMT_3_3_2 = 0x21,
- FMT_6_5_5 = 0x22,
- FMT_32_32_32_32_FLOAT = 0x23,
- FMT_RESERVED_36 = 0x24,
- FMT_1 = 0x25,
- FMT_1_REVERSED = 0x26,
- FMT_GB_GR = 0x27,
- FMT_BG_RG = 0x28,
- FMT_32_AS_8 = 0x29,
- FMT_32_AS_8_8 = 0x2a,
- FMT_5_9_9_9_SHAREDEXP = 0x2b,
- FMT_8_8_8 = 0x2c,
- FMT_16_16_16 = 0x2d,
- FMT_16_16_16_FLOAT = 0x2e,
- FMT_4_4 = 0x2f,
- FMT_32_32_32_FLOAT = 0x30,
- FMT_BC1 = 0x31,
- FMT_BC2 = 0x32,
- FMT_BC3 = 0x33,
- FMT_BC4 = 0x34,
- FMT_BC5 = 0x35,
- FMT_BC6 = 0x36,
- FMT_BC7 = 0x37,
- FMT_32_AS_32_32_32_32 = 0x38,
- FMT_APC3 = 0x39,
- FMT_APC4 = 0x3a,
- FMT_APC5 = 0x3b,
- FMT_APC6 = 0x3c,
- FMT_APC7 = 0x3d,
- FMT_CTX1 = 0x3e,
- FMT_RESERVED_63 = 0x3f,
-} SurfaceFormat;
-typedef enum BUF_DATA_FORMAT {
- BUF_DATA_FORMAT_INVALID = 0x0,
- BUF_DATA_FORMAT_8 = 0x1,
- BUF_DATA_FORMAT_16 = 0x2,
- BUF_DATA_FORMAT_8_8 = 0x3,
- BUF_DATA_FORMAT_32 = 0x4,
- BUF_DATA_FORMAT_16_16 = 0x5,
- BUF_DATA_FORMAT_10_11_11 = 0x6,
- BUF_DATA_FORMAT_11_11_10 = 0x7,
- BUF_DATA_FORMAT_10_10_10_2 = 0x8,
- BUF_DATA_FORMAT_2_10_10_10 = 0x9,
- BUF_DATA_FORMAT_8_8_8_8 = 0xa,
- BUF_DATA_FORMAT_32_32 = 0xb,
- BUF_DATA_FORMAT_16_16_16_16 = 0xc,
- BUF_DATA_FORMAT_32_32_32 = 0xd,
- BUF_DATA_FORMAT_32_32_32_32 = 0xe,
- BUF_DATA_FORMAT_RESERVED_15 = 0xf,
-} BUF_DATA_FORMAT;
-typedef enum IMG_DATA_FORMAT {
- IMG_DATA_FORMAT_INVALID = 0x0,
- IMG_DATA_FORMAT_8 = 0x1,
- IMG_DATA_FORMAT_16 = 0x2,
- IMG_DATA_FORMAT_8_8 = 0x3,
- IMG_DATA_FORMAT_32 = 0x4,
- IMG_DATA_FORMAT_16_16 = 0x5,
- IMG_DATA_FORMAT_10_11_11 = 0x6,
- IMG_DATA_FORMAT_11_11_10 = 0x7,
- IMG_DATA_FORMAT_10_10_10_2 = 0x8,
- IMG_DATA_FORMAT_2_10_10_10 = 0x9,
- IMG_DATA_FORMAT_8_8_8_8 = 0xa,
- IMG_DATA_FORMAT_32_32 = 0xb,
- IMG_DATA_FORMAT_16_16_16_16 = 0xc,
- IMG_DATA_FORMAT_32_32_32 = 0xd,
- IMG_DATA_FORMAT_32_32_32_32 = 0xe,
- IMG_DATA_FORMAT_RESERVED_15 = 0xf,
- IMG_DATA_FORMAT_5_6_5 = 0x10,
- IMG_DATA_FORMAT_1_5_5_5 = 0x11,
- IMG_DATA_FORMAT_5_5_5_1 = 0x12,
- IMG_DATA_FORMAT_4_4_4_4 = 0x13,
- IMG_DATA_FORMAT_8_24 = 0x14,
- IMG_DATA_FORMAT_24_8 = 0x15,
- IMG_DATA_FORMAT_X24_8_32 = 0x16,
- IMG_DATA_FORMAT_RESERVED_23 = 0x17,
- IMG_DATA_FORMAT_RESERVED_24 = 0x18,
- IMG_DATA_FORMAT_RESERVED_25 = 0x19,
- IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
- IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
- IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
- IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
- IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
- IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
- IMG_DATA_FORMAT_GB_GR = 0x20,
- IMG_DATA_FORMAT_BG_RG = 0x21,
- IMG_DATA_FORMAT_5_9_9_9 = 0x22,
- IMG_DATA_FORMAT_BC1 = 0x23,
- IMG_DATA_FORMAT_BC2 = 0x24,
- IMG_DATA_FORMAT_BC3 = 0x25,
- IMG_DATA_FORMAT_BC4 = 0x26,
- IMG_DATA_FORMAT_BC5 = 0x27,
- IMG_DATA_FORMAT_BC6 = 0x28,
- IMG_DATA_FORMAT_BC7 = 0x29,
- IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
- IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
- IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
- IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
- IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
- IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
- IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
- IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
- IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
- IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
- IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
- IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
- IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
- IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
- IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
- IMG_DATA_FORMAT_4_4 = 0x39,
- IMG_DATA_FORMAT_6_5_5 = 0x3a,
- IMG_DATA_FORMAT_1 = 0x3b,
- IMG_DATA_FORMAT_1_REVERSED = 0x3c,
- IMG_DATA_FORMAT_32_AS_8 = 0x3d,
- IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
- IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
-} IMG_DATA_FORMAT;
-typedef enum BUF_NUM_FORMAT {
- BUF_NUM_FORMAT_UNORM = 0x0,
- BUF_NUM_FORMAT_SNORM = 0x1,
- BUF_NUM_FORMAT_USCALED = 0x2,
- BUF_NUM_FORMAT_SSCALED = 0x3,
- BUF_NUM_FORMAT_UINT = 0x4,
- BUF_NUM_FORMAT_SINT = 0x5,
- BUF_NUM_FORMAT_RESERVED_6 = 0x6,
- BUF_NUM_FORMAT_FLOAT = 0x7,
-} BUF_NUM_FORMAT;
-typedef enum IMG_NUM_FORMAT {
- IMG_NUM_FORMAT_UNORM = 0x0,
- IMG_NUM_FORMAT_SNORM = 0x1,
- IMG_NUM_FORMAT_USCALED = 0x2,
- IMG_NUM_FORMAT_SSCALED = 0x3,
- IMG_NUM_FORMAT_UINT = 0x4,
- IMG_NUM_FORMAT_SINT = 0x5,
- IMG_NUM_FORMAT_RESERVED_6 = 0x6,
- IMG_NUM_FORMAT_FLOAT = 0x7,
- IMG_NUM_FORMAT_RESERVED_8 = 0x8,
- IMG_NUM_FORMAT_SRGB = 0x9,
- IMG_NUM_FORMAT_RESERVED_10 = 0xa,
- IMG_NUM_FORMAT_RESERVED_11 = 0xb,
- IMG_NUM_FORMAT_RESERVED_12 = 0xc,
- IMG_NUM_FORMAT_RESERVED_13 = 0xd,
- IMG_NUM_FORMAT_RESERVED_14 = 0xe,
- IMG_NUM_FORMAT_RESERVED_15 = 0xf,
-} IMG_NUM_FORMAT;
-typedef enum TileType {
- ARRAY_COLOR_TILE = 0x0,
- ARRAY_DEPTH_TILE = 0x1,
-} TileType;
-typedef enum NonDispTilingOrder {
- ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
- ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
-} NonDispTilingOrder;
-typedef enum MicroTileMode {
- ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
- ADDR_SURF_THIN_MICRO_TILING = 0x1,
- ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
- ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
- ADDR_SURF_THICK_MICRO_TILING = 0x4,
-} MicroTileMode;
-typedef enum TileSplit {
- ADDR_SURF_TILE_SPLIT_64B = 0x0,
- ADDR_SURF_TILE_SPLIT_128B = 0x1,
- ADDR_SURF_TILE_SPLIT_256B = 0x2,
- ADDR_SURF_TILE_SPLIT_512B = 0x3,
- ADDR_SURF_TILE_SPLIT_1KB = 0x4,
- ADDR_SURF_TILE_SPLIT_2KB = 0x5,
- ADDR_SURF_TILE_SPLIT_4KB = 0x6,
-} TileSplit;
-typedef enum SampleSplit {
- ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
- ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
- ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
- ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
-} SampleSplit;
-typedef enum PipeConfig {
- ADDR_SURF_P2 = 0x0,
- ADDR_SURF_P2_RESERVED0 = 0x1,
- ADDR_SURF_P2_RESERVED1 = 0x2,
- ADDR_SURF_P2_RESERVED2 = 0x3,
- ADDR_SURF_P4_8x16 = 0x4,
- ADDR_SURF_P4_16x16 = 0x5,
- ADDR_SURF_P4_16x32 = 0x6,
- ADDR_SURF_P4_32x32 = 0x7,
- ADDR_SURF_P8_16x16_8x16 = 0x8,
- ADDR_SURF_P8_16x32_8x16 = 0x9,
- ADDR_SURF_P8_32x32_8x16 = 0xa,
- ADDR_SURF_P8_16x32_16x16 = 0xb,
- ADDR_SURF_P8_32x32_16x16 = 0xc,
- ADDR_SURF_P8_32x32_16x32 = 0xd,
- ADDR_SURF_P8_32x64_32x32 = 0xe,
- ADDR_SURF_P8_RESERVED0 = 0xf,
- ADDR_SURF_P16_32x32_8x16 = 0x10,
- ADDR_SURF_P16_32x32_16x16 = 0x11,
-} PipeConfig;
-typedef enum NumBanks {
- ADDR_SURF_2_BANK = 0x0,
- ADDR_SURF_4_BANK = 0x1,
- ADDR_SURF_8_BANK = 0x2,
- ADDR_SURF_16_BANK = 0x3,
-} NumBanks;
-typedef enum BankWidth {
- ADDR_SURF_BANK_WIDTH_1 = 0x0,
- ADDR_SURF_BANK_WIDTH_2 = 0x1,
- ADDR_SURF_BANK_WIDTH_4 = 0x2,
- ADDR_SURF_BANK_WIDTH_8 = 0x3,
-} BankWidth;
-typedef enum BankHeight {
- ADDR_SURF_BANK_HEIGHT_1 = 0x0,
- ADDR_SURF_BANK_HEIGHT_2 = 0x1,
- ADDR_SURF_BANK_HEIGHT_4 = 0x2,
- ADDR_SURF_BANK_HEIGHT_8 = 0x3,
-} BankHeight;
-typedef enum BankWidthHeight {
- ADDR_SURF_BANK_WH_1 = 0x0,
- ADDR_SURF_BANK_WH_2 = 0x1,
- ADDR_SURF_BANK_WH_4 = 0x2,
- ADDR_SURF_BANK_WH_8 = 0x3,
-} BankWidthHeight;
-typedef enum MacroTileAspect {
- ADDR_SURF_MACRO_ASPECT_1 = 0x0,
- ADDR_SURF_MACRO_ASPECT_2 = 0x1,
- ADDR_SURF_MACRO_ASPECT_4 = 0x2,
- ADDR_SURF_MACRO_ASPECT_8 = 0x3,
-} MacroTileAspect;
-typedef enum GATCL1RequestType {
- GATCL1_TYPE_NORMAL = 0x0,
- GATCL1_TYPE_SHOOTDOWN = 0x1,
- GATCL1_TYPE_BYPASS = 0x2,
-} GATCL1RequestType;
-typedef enum TCC_CACHE_POLICIES {
- TCC_CACHE_POLICY_LRU = 0x0,
- TCC_CACHE_POLICY_STREAM = 0x1,
-} TCC_CACHE_POLICIES;
-typedef enum MTYPE {
- MTYPE_NC_NV = 0x0,
- MTYPE_NC = 0x1,
- MTYPE_CC = 0x2,
- MTYPE_UC = 0x3,
-} MTYPE;
-typedef enum PERFMON_COUNTER_MODE {
- PERFMON_COUNTER_MODE_ACCUM = 0x0,
- PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
- PERFMON_COUNTER_MODE_MAX = 0x2,
- PERFMON_COUNTER_MODE_DIRTY = 0x3,
- PERFMON_COUNTER_MODE_SAMPLE = 0x4,
- PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
- PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
- PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
- PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
- PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
- PERFMON_COUNTER_MODE_RESERVED = 0xf,
-} PERFMON_COUNTER_MODE;
-typedef enum PERFMON_SPM_MODE {
- PERFMON_SPM_MODE_OFF = 0x0,
- PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
- PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
- PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
- PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
- PERFMON_SPM_MODE_RESERVED_5 = 0x5,
- PERFMON_SPM_MODE_RESERVED_6 = 0x6,
- PERFMON_SPM_MODE_RESERVED_7 = 0x7,
- PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
- PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
- PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
-} PERFMON_SPM_MODE;
-typedef enum SurfaceTiling {
- ARRAY_LINEAR = 0x0,
- ARRAY_TILED = 0x1,
-} SurfaceTiling;
-typedef enum SurfaceArray {
- ARRAY_1D = 0x0,
- ARRAY_2D = 0x1,
- ARRAY_3D = 0x2,
- ARRAY_3D_SLICE = 0x3,
-} SurfaceArray;
-typedef enum ColorArray {
- ARRAY_2D_ALT_COLOR = 0x0,
- ARRAY_2D_COLOR = 0x1,
- ARRAY_3D_SLICE_COLOR = 0x3,
-} ColorArray;
-typedef enum DepthArray {
- ARRAY_2D_ALT_DEPTH = 0x0,
- ARRAY_2D_DEPTH = 0x1,
-} DepthArray;
-typedef enum ENUM_NUM_SIMD_PER_CU {
- NUM_SIMD_PER_CU = 0x4,
-} ENUM_NUM_SIMD_PER_CU;
-typedef enum MEM_PWR_FORCE_CTRL {
- NO_FORCE_REQUEST = 0x0,
- FORCE_LIGHT_SLEEP_REQUEST = 0x1,
- FORCE_DEEP_SLEEP_REQUEST = 0x2,
- FORCE_SHUT_DOWN_REQUEST = 0x3,
-} MEM_PWR_FORCE_CTRL;
-typedef enum MEM_PWR_FORCE_CTRL2 {
- NO_FORCE_REQ = 0x0,
- FORCE_LIGHT_SLEEP_REQ = 0x1,
-} MEM_PWR_FORCE_CTRL2;
-typedef enum MEM_PWR_DIS_CTRL {
- ENABLE_MEM_PWR_CTRL = 0x0,
- DISABLE_MEM_PWR_CTRL = 0x1,
-} MEM_PWR_DIS_CTRL;
-typedef enum MEM_PWR_SEL_CTRL {
- DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
- DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
- DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
-} MEM_PWR_SEL_CTRL;
-typedef enum MEM_PWR_SEL_CTRL2 {
- DYNAMIC_DEEP_SLEEP_EN = 0x0,
- DYNAMIC_LIGHT_SLEEP_EN = 0x1,
-} MEM_PWR_SEL_CTRL2;
-typedef enum HPD_INT_CONTROL_ACK {
- HPD_INT_CONTROL_ACK_0 = 0x0,
- HPD_INT_CONTROL_ACK_1 = 0x1,
-} HPD_INT_CONTROL_ACK;
-typedef enum HPD_INT_CONTROL_POLARITY {
- HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0x0,
- HPD_INT_CONTROL_GEN_INT_ON_CON = 0x1,
-} HPD_INT_CONTROL_POLARITY;
-typedef enum HPD_INT_CONTROL_RX_INT_ACK {
- HPD_INT_CONTROL_RX_INT_ACK_0 = 0x0,
- HPD_INT_CONTROL_RX_INT_ACK_1 = 0x1,
-} HPD_INT_CONTROL_RX_INT_ACK;
-typedef enum DPDBG_EN {
- DPDBG_DISABLE = 0x0,
- DPDBG_ENABLE = 0x1,
-} DPDBG_EN;
-typedef enum DPDBG_INPUT_EN {
- DPDBG_INPUT_DISABLE = 0x0,
- DPDBG_INPUT_ENABLE = 0x1,
-} DPDBG_INPUT_EN;
-typedef enum DPDBG_ERROR_DETECTION_MODE {
- DPDBG_ERROR_DETECTION_MODE_CSC = 0x0,
- DPDBG_ERROR_DETECTION_MODE_RS_ENCODING = 0x1,
-} DPDBG_ERROR_DETECTION_MODE;
-typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK {
- DPDBG_FIFO_OVERFLOW_INT_DISABLE = 0x0,
- DPDBG_FIFO_OVERFLOW_INT_ENABLE = 0x1,
-} DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK;
-typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE {
- DPDBG_FIFO_OVERFLOW_INT_LEVEL_BASED = 0x0,
- DPDBG_FIFO_OVERFLOW_INT_PULSE_BASED = 0x1,
-} DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE;
-typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK {
- DPDBG_FIFO_OVERFLOW_INT_NO_ACK = 0x0,
- DPDBG_FIFO_OVERFLOW_INT_CLEAR = 0x1,
-} DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK;
-typedef enum PM_ASSERT_RESET {
- PM_ASSERT_RESET_0 = 0x0,
- PM_ASSERT_RESET_1 = 0x1,
-} PM_ASSERT_RESET;
-typedef enum DAC_MUX_SELECT {
- DAC_MUX_SELECT_DACA = 0x0,
- DAC_MUX_SELECT_DACB = 0x1,
-} DAC_MUX_SELECT;
-typedef enum TMDS_DVO_MUX_SELECT {
- TMDS_DVO_MUX_SELECT_B = 0x0,
- TMDS_DVO_MUX_SELECT_G = 0x1,
- TMDS_DVO_MUX_SELECT_R = 0x2,
- TMDS_DVO_MUX_SELECT_RESERVED = 0x3,
-} TMDS_DVO_MUX_SELECT;
-typedef enum DACA_SOFT_RESET {
- DACA_SOFT_RESET_0 = 0x0,
- DACA_SOFT_RESET_1 = 0x1,
-} DACA_SOFT_RESET;
-typedef enum I2S0_SPDIF0_SOFT_RESET {
- I2S0_SPDIF0_SOFT_RESET_0 = 0x0,
- I2S0_SPDIF0_SOFT_RESET_1 = 0x1,
-} I2S0_SPDIF0_SOFT_RESET;
-typedef enum I2S1_SOFT_RESET {
- I2S1_SOFT_RESET_0 = 0x0,
- I2S1_SOFT_RESET_1 = 0x1,
-} I2S1_SOFT_RESET;
-typedef enum SPDIF1_SOFT_RESET {
- SPDIF1_SOFT_RESET_0 = 0x0,
- SPDIF1_SOFT_RESET_1 = 0x1,
-} SPDIF1_SOFT_RESET;
-typedef enum DB_CLK_SOFT_RESET {
- DB_CLK_SOFT_RESET_0 = 0x0,
- DB_CLK_SOFT_RESET_1 = 0x1,
-} DB_CLK_SOFT_RESET;
-typedef enum FMT0_SOFT_RESET {
- FMT0_SOFT_RESET_0 = 0x0,
- FMT0_SOFT_RESET_1 = 0x1,
-} FMT0_SOFT_RESET;
-typedef enum FMT1_SOFT_RESET {
- FMT1_SOFT_RESET_0 = 0x0,
- FMT1_SOFT_RESET_1 = 0x1,
-} FMT1_SOFT_RESET;
-typedef enum FMT2_SOFT_RESET {
- FMT2_SOFT_RESET_0 = 0x0,
- FMT2_SOFT_RESET_1 = 0x1,
-} FMT2_SOFT_RESET;
-typedef enum FMT3_SOFT_RESET {
- FMT3_SOFT_RESET_0 = 0x0,
- FMT3_SOFT_RESET_1 = 0x1,
-} FMT3_SOFT_RESET;
-typedef enum FMT4_SOFT_RESET {
- FMT4_SOFT_RESET_0 = 0x0,
- FMT4_SOFT_RESET_1 = 0x1,
-} FMT4_SOFT_RESET;
-typedef enum FMT5_SOFT_RESET {
- FMT5_SOFT_RESET_0 = 0x0,
- FMT5_SOFT_RESET_1 = 0x1,
-} FMT5_SOFT_RESET;
-typedef enum MVP_SOFT_RESET {
- MVP_SOFT_RESET_0 = 0x0,
- MVP_SOFT_RESET_1 = 0x1,
-} MVP_SOFT_RESET;
-typedef enum ABM_SOFT_RESET {
- ABM_SOFT_RESET_0 = 0x0,
- ABM_SOFT_RESET_1 = 0x1,
-} ABM_SOFT_RESET;
-typedef enum DVO_SOFT_RESET {
- DVO_SOFT_RESET_0 = 0x0,
- DVO_SOFT_RESET_1 = 0x1,
-} DVO_SOFT_RESET;
-typedef enum DIGA_FE_SOFT_RESET {
- DIGA_FE_SOFT_RESET_0 = 0x0,
- DIGA_FE_SOFT_RESET_1 = 0x1,
-} DIGA_FE_SOFT_RESET;
-typedef enum DIGA_BE_SOFT_RESET {
- DIGA_BE_SOFT_RESET_0 = 0x0,
- DIGA_BE_SOFT_RESET_1 = 0x1,
-} DIGA_BE_SOFT_RESET;
-typedef enum DIGB_FE_SOFT_RESET {
- DIGB_FE_SOFT_RESET_0 = 0x0,
- DIGB_FE_SOFT_RESET_1 = 0x1,
-} DIGB_FE_SOFT_RESET;
-typedef enum DIGB_BE_SOFT_RESET {
- DIGB_BE_SOFT_RESET_0 = 0x0,
- DIGB_BE_SOFT_RESET_1 = 0x1,
-} DIGB_BE_SOFT_RESET;
-typedef enum DIGC_FE_SOFT_RESET {
- DIGC_FE_SOFT_RESET_0 = 0x0,
- DIGC_FE_SOFT_RESET_1 = 0x1,
-} DIGC_FE_SOFT_RESET;
-typedef enum DIGC_BE_SOFT_RESET {
- DIGC_BE_SOFT_RESET_0 = 0x0,
- DIGC_BE_SOFT_RESET_1 = 0x1,
-} DIGC_BE_SOFT_RESET;
-typedef enum DIGD_FE_SOFT_RESET {
- DIGD_FE_SOFT_RESET_0 = 0x0,
- DIGD_FE_SOFT_RESET_1 = 0x1,
-} DIGD_FE_SOFT_RESET;
-typedef enum DIGD_BE_SOFT_RESET {
- DIGD_BE_SOFT_RESET_0 = 0x0,
- DIGD_BE_SOFT_RESET_1 = 0x1,
-} DIGD_BE_SOFT_RESET;
-typedef enum DIGE_FE_SOFT_RESET {
- DIGE_FE_SOFT_RESET_0 = 0x0,
- DIGE_FE_SOFT_RESET_1 = 0x1,
-} DIGE_FE_SOFT_RESET;
-typedef enum DIGE_BE_SOFT_RESET {
- DIGE_BE_SOFT_RESET_0 = 0x0,
- DIGE_BE_SOFT_RESET_1 = 0x1,
-} DIGE_BE_SOFT_RESET;
-typedef enum DIGF_FE_SOFT_RESET {
- DIGF_FE_SOFT_RESET_0 = 0x0,
- DIGF_FE_SOFT_RESET_1 = 0x1,
-} DIGF_FE_SOFT_RESET;
-typedef enum DIGF_BE_SOFT_RESET {
- DIGF_BE_SOFT_RESET_0 = 0x0,
- DIGF_BE_SOFT_RESET_1 = 0x1,
-} DIGF_BE_SOFT_RESET;
-typedef enum DIGG_FE_SOFT_RESET {
- DIGG_FE_SOFT_RESET_0 = 0x0,
- DIGG_FE_SOFT_RESET_1 = 0x1,
-} DIGG_FE_SOFT_RESET;
-typedef enum DIGG_BE_SOFT_RESET {
- DIGG_BE_SOFT_RESET_0 = 0x0,
- DIGG_BE_SOFT_RESET_1 = 0x1,
-} DIGG_BE_SOFT_RESET;
-typedef enum DPDBG_SOFT_RESET {
- DPDBG_SOFT_RESET_0 = 0x0,
- DPDBG_SOFT_RESET_1 = 0x1,
-} DPDBG_SOFT_RESET;
-typedef enum DIGLPA_FE_SOFT_RESET {
- DIGLPA_FE_SOFT_RESET_0 = 0x0,
- DIGLPA_FE_SOFT_RESET_1 = 0x1,
-} DIGLPA_FE_SOFT_RESET;
-typedef enum DIGLPA_BE_SOFT_RESET {
- DIGLPA_BE_SOFT_RESET_0 = 0x0,
- DIGLPA_BE_SOFT_RESET_1 = 0x1,
-} DIGLPA_BE_SOFT_RESET;
-typedef enum DIGLPB_FE_SOFT_RESET {
- DIGLPB_FE_SOFT_RESET_0 = 0x0,
- DIGLPB_FE_SOFT_RESET_1 = 0x1,
-} DIGLPB_FE_SOFT_RESET;
-typedef enum DIGLPB_BE_SOFT_RESET {
- DIGLPB_BE_SOFT_RESET_0 = 0x0,
- DIGLPB_BE_SOFT_RESET_1 = 0x1,
-} DIGLPB_BE_SOFT_RESET;
-typedef enum GENERICA_STEREOSYNC_SEL {
- GENERICA_STEREOSYNC_SEL_D1 = 0x0,
- GENERICA_STEREOSYNC_SEL_D2 = 0x1,
- GENERICA_STEREOSYNC_SEL_D3 = 0x2,
- GENERICA_STEREOSYNC_SEL_D4 = 0x3,
- GENERICA_STEREOSYNC_SEL_D5 = 0x4,
- GENERICA_STEREOSYNC_SEL_D6 = 0x5,
- GENERICA_STEREOSYNC_SEL_RESERVED = 0x6,
-} GENERICA_STEREOSYNC_SEL;
-typedef enum GENERICB_STEREOSYNC_SEL {
- GENERICB_STEREOSYNC_SEL_D1 = 0x0,
- GENERICB_STEREOSYNC_SEL_D2 = 0x1,
- GENERICB_STEREOSYNC_SEL_D3 = 0x2,
- GENERICB_STEREOSYNC_SEL_D4 = 0x3,
- GENERICB_STEREOSYNC_SEL_D5 = 0x4,
- GENERICB_STEREOSYNC_SEL_D6 = 0x5,
- GENERICB_STEREOSYNC_SEL_RESERVED = 0x6,
-} GENERICB_STEREOSYNC_SEL;
-typedef enum DCO_DBG_BLOCK_SEL {
- DCO_DBG_BLOCK_SEL_DCO = 0x0,
- DCO_DBG_BLOCK_SEL_ABM = 0x1,
- DCO_DBG_BLOCK_SEL_DVO = 0x2,
- DCO_DBG_BLOCK_SEL_DAC = 0x3,
- DCO_DBG_BLOCK_SEL_MVP = 0x4,
- DCO_DBG_BLOCK_SEL_FMT0 = 0x5,
- DCO_DBG_BLOCK_SEL_FMT1 = 0x6,
- DCO_DBG_BLOCK_SEL_FMT2 = 0x7,
- DCO_DBG_BLOCK_SEL_FMT3 = 0x8,
- DCO_DBG_BLOCK_SEL_FMT4 = 0x9,
- DCO_DBG_BLOCK_SEL_FMT5 = 0xa,
- DCO_DBG_BLOCK_SEL_DIGFE_A = 0xb,
- DCO_DBG_BLOCK_SEL_DIGFE_B = 0xc,
- DCO_DBG_BLOCK_SEL_DIGFE_C = 0xd,
- DCO_DBG_BLOCK_SEL_DIGFE_D = 0xe,
- DCO_DBG_BLOCK_SEL_DIGFE_E = 0xf,
- DCO_DBG_BLOCK_SEL_DIGFE_F = 0x10,
- DCO_DBG_BLOCK_SEL_DIGFE_G = 0x11,
- DCO_DBG_BLOCK_SEL_DIGA = 0x12,
- DCO_DBG_BLOCK_SEL_DIGB = 0x13,
- DCO_DBG_BLOCK_SEL_DIGC = 0x14,
- DCO_DBG_BLOCK_SEL_DIGD = 0x15,
- DCO_DBG_BLOCK_SEL_DIGE = 0x16,
- DCO_DBG_BLOCK_SEL_DIGF = 0x17,
- DCO_DBG_BLOCK_SEL_DIGG = 0x18,
- DCO_DBG_BLOCK_SEL_DPFE_A = 0x19,
- DCO_DBG_BLOCK_SEL_DPFE_B = 0x1a,
- DCO_DBG_BLOCK_SEL_DPFE_C = 0x1b,
- DCO_DBG_BLOCK_SEL_DPFE_D = 0x1c,
- DCO_DBG_BLOCK_SEL_DPFE_E = 0x1d,
- DCO_DBG_BLOCK_SEL_DPFE_F = 0x1e,
- DCO_DBG_BLOCK_SEL_DPFE_G = 0x1f,
- DCO_DBG_BLOCK_SEL_DPA = 0x20,
- DCO_DBG_BLOCK_SEL_DPB = 0x21,
- DCO_DBG_BLOCK_SEL_DPC = 0x22,
- DCO_DBG_BLOCK_SEL_DPD = 0x23,
- DCO_DBG_BLOCK_SEL_DPE = 0x24,
- DCO_DBG_BLOCK_SEL_DPF = 0x25,
- DCO_DBG_BLOCK_SEL_DPG = 0x26,
- DCO_DBG_BLOCK_SEL_AUX0 = 0x27,
- DCO_DBG_BLOCK_SEL_AUX1 = 0x28,
- DCO_DBG_BLOCK_SEL_AUX2 = 0x29,
- DCO_DBG_BLOCK_SEL_AUX3 = 0x2a,
- DCO_DBG_BLOCK_SEL_AUX4 = 0x2b,
- DCO_DBG_BLOCK_SEL_AUX5 = 0x2c,
- DCO_DBG_BLOCK_SEL_PERFMON_DCO = 0x2d,
- DCO_DBG_BLOCK_SEL_AUDIO_OUT = 0x2e,
- DCO_DBG_BLOCK_SEL_DIGLPFEA = 0x2f,
- DCO_DBG_BLOCK_SEL_DIGLPFEB = 0x30,
- DCO_DBG_BLOCK_SEL_DIGLPA = 0x31,
- DCO_DBG_BLOCK_SEL_DIGLPB = 0x32,
- DCO_DBG_BLOCK_SEL_DPLPFEA = 0x33,
- DCO_DBG_BLOCK_SEL_DPLPFEB = 0x34,
- DCO_DBG_BLOCK_SEL_DPLPA = 0x35,
- DCO_DBG_BLOCK_SEL_DPLPB = 0x36,
-} DCO_DBG_BLOCK_SEL;
-typedef enum DCO_DBG_CLOCK_SEL {
- DCO_DBG_CLOCK_SEL_DISPCLK = 0x0,
- DCO_DBG_CLOCK_SEL_SCLK = 0x1,
- DCO_DBG_CLOCK_SEL_MVPCLK = 0x2,
- DCO_DBG_CLOCK_SEL_DVOCLK = 0x3,
- DCO_DBG_CLOCK_SEL_DACCLK = 0x4,
- DCO_DBG_CLOCK_SEL_REFCLK = 0x5,
- DCO_DBG_CLOCK_SEL_SYMCLKA = 0x6,
- DCO_DBG_CLOCK_SEL_SYMCLKB = 0x7,
- DCO_DBG_CLOCK_SEL_SYMCLKC = 0x8,
- DCO_DBG_CLOCK_SEL_SYMCLKD = 0x9,
- DCO_DBG_CLOCK_SEL_SYMCLKE = 0xa,
- DCO_DBG_CLOCK_SEL_SYMCLKF = 0xb,
- DCO_DBG_CLOCK_SEL_SYMCLKG = 0xc,
- DCO_DBG_CLOCK_SEL_RESERVED = 0xd,
- DCO_DBG_CLOCK_SEL_AM0CLK = 0xe,
- DCO_DBG_CLOCK_SEL_AM1CLK = 0xf,
- DCO_DBG_CLOCK_SEL_AM2CLK = 0x10,
- DCO_DBG_CLOCK_SEL_SYMCLKLPA = 0x11,
- DCO_DBG_CLOCK_SEL_SYMCLKLPB = 0x12,
-} DCO_DBG_CLOCK_SEL;
-typedef enum DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE {
- DCO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL = 0x0,
- DCO_HDMI_RXSTATUS_TIMER_TYPE_PULSE = 0x1,
-} DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE;
-typedef enum FMT420_MEMORY_SOURCE_SEL {
- FMT420_MEMORY_SOURCE_SEL_FMT0 = 0x0,
- FMT420_MEMORY_SOURCE_SEL_FMT1 = 0x1,
- FMT420_MEMORY_SOURCE_SEL_FMT2 = 0x2,
- FMT420_MEMORY_SOURCE_SEL_FMT3 = 0x3,
- FMT420_MEMORY_SOURCE_SEL_FMT4 = 0x4,
- FMT420_MEMORY_SOURCE_SEL_FMT5 = 0x5,
- FMT420_MEMORY_SOURCE_SEL_FMT_RESERVED = 0x6,
-} FMT420_MEMORY_SOURCE_SEL;
-typedef enum DOUT_I2C_CONTROL_GO {
- DOUT_I2C_CONTROL_STOP_TRANSFER = 0x0,
- DOUT_I2C_CONTROL_START_TRANSFER = 0x1,
-} DOUT_I2C_CONTROL_GO;
-typedef enum DOUT_I2C_CONTROL_SOFT_RESET {
- DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0x0,
- DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER = 0x1,
-} DOUT_I2C_CONTROL_SOFT_RESET;
-typedef enum DOUT_I2C_CONTROL_SEND_RESET {
- DOUT_I2C_CONTROL__NOT_SEND_RESET = 0x0,
- DOUT_I2C_CONTROL__SEND_RESET = 0x1,
-} DOUT_I2C_CONTROL_SEND_RESET;
-typedef enum DOUT_I2C_CONTROL_SW_STATUS_RESET {
- DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS = 0x0,
- DOUT_I2C_CONTROL_RESET_SW_STATUS = 0x1,
-} DOUT_I2C_CONTROL_SW_STATUS_RESET;
-typedef enum DOUT_I2C_CONTROL_DDC_SELECT {
- DOUT_I2C_CONTROL_SELECT_DDC1 = 0x0,
- DOUT_I2C_CONTROL_SELECT_DDC2 = 0x1,
- DOUT_I2C_CONTROL_SELECT_DDC3 = 0x2,
- DOUT_I2C_CONTROL_SELECT_DDC4 = 0x3,
- DOUT_I2C_CONTROL_SELECT_DDC5 = 0x4,
- DOUT_I2C_CONTROL_SELECT_DDC6 = 0x5,
- DOUT_I2C_CONTROL_SELECT_DDCVGA = 0x6,
-} DOUT_I2C_CONTROL_DDC_SELECT;
-typedef enum DOUT_I2C_CONTROL_TRANSACTION_COUNT {
- DOUT_I2C_CONTROL_TRANS0 = 0x0,
- DOUT_I2C_CONTROL_TRANS0_TRANS1 = 0x1,
- DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2 = 0x2,
- DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3 = 0x3,
-} DOUT_I2C_CONTROL_TRANSACTION_COUNT;
-typedef enum DOUT_I2C_CONTROL_DBG_REF_SEL {
- DOUT_I2C_CONTROL_NORMAL_DEBUG = 0x0,
- DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG = 0x1,
-} DOUT_I2C_CONTROL_DBG_REF_SEL;
-typedef enum DOUT_I2C_ARBITRATION_SW_PRIORITY {
- DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL = 0x0,
- DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH = 0x1,
- DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 0x2,
- DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 0x3,
-} DOUT_I2C_ARBITRATION_SW_PRIORITY;
-typedef enum DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO {
- DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED = 0x0,
- DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED = 0x1,
-} DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO;
-typedef enum DOUT_I2C_ARBITRATION_ABORT_XFER {
- DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0x0,
- DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER = 0x1,
-} DOUT_I2C_ARBITRATION_ABORT_XFER;
-typedef enum DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ {
- DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0x0,
- DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ = 0x1,
-} DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ;
-typedef enum DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG {
- DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0x0,
- DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG = 0x1,
-} DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG;
-typedef enum DOUT_I2C_ACK {
- DOUT_I2C_NO_ACK = 0x0,
- DOUT_I2C_ACK_TO_CLEAN = 0x1,
-} DOUT_I2C_ACK;
-typedef enum DOUT_I2C_DDC_SPEED_THRESHOLD {
- DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO = 0x0,
- DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE= 0x1,
- DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE= 0x2,
- DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE= 0x3,
-} DOUT_I2C_DDC_SPEED_THRESHOLD;
-typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN {
- DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR= 0x0,
- DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA = 0x1,
-} DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN;
-typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL {
- DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS = 0x0,
- DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS = 0x1,
-} DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL;
-typedef enum DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE {
- DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT = 0x0,
- DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT = 0x1,
-} DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE;
-typedef enum DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN {
- DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR= 0x0,
- DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL = 0x1,
-} DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN;
-typedef enum DOUT_I2C_TRANSACTION_STOP_ON_NACK {
- DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS = 0x0,
- DOUT_I2C_TRANSACTION_STOP_ALL_TRANS = 0x1,
-} DOUT_I2C_TRANSACTION_STOP_ON_NACK;
-typedef enum DOUT_I2C_DATA_INDEX_WRITE {
- DOUT_I2C_DATA__NOT_INDEX_WRITE = 0x0,
- DOUT_I2C_DATA__INDEX_WRITE = 0x1,
-} DOUT_I2C_DATA_INDEX_WRITE;
-typedef enum DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET {
- DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION= 0x0,
- DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION= 0x1,
-} DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET;
-typedef enum DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE {
- DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL = 0x0,
- DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE = 0x1,
-} DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE;
-typedef enum BLNDV_CONTROL_BLND_MODE {
- BLNDV_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0x0,
- BLNDV_CONTROL_BLND_MODE_OTHER_PIPE_ONLY = 0x1,
- BLNDV_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 0x2,
- BLNDV_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 0x3,
-} BLNDV_CONTROL_BLND_MODE;
-typedef enum BLNDV_CONTROL_BLND_STEREO_TYPE {
- BLNDV_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO= 0x0,
- BLNDV_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO= 0x1,
- BLNDV_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO= 0x2,
- BLNDV_CONTROL_BLND_STEREO_TYPE_UNUSED = 0x3,
-} BLNDV_CONTROL_BLND_STEREO_TYPE;
-typedef enum BLNDV_CONTROL_BLND_STEREO_POLARITY {
- BLNDV_CONTROL_BLND_STEREO_POLARITY_LOW = 0x0,
- BLNDV_CONTROL_BLND_STEREO_POLARITY_HIGH = 0x1,
-} BLNDV_CONTROL_BLND_STEREO_POLARITY;
-typedef enum BLNDV_CONTROL_BLND_FEEDTHROUGH_EN {
- BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_FALSE = 0x0,
- BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_TRUE = 0x1,
-} BLNDV_CONTROL_BLND_FEEDTHROUGH_EN;
-typedef enum BLNDV_CONTROL_BLND_ALPHA_MODE {
- BLNDV_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA= 0x0,
- BLNDV_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN= 0x1,
- BLNDV_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 0x2,
- BLNDV_CONTROL_BLND_ALPHA_MODE_UNUSED = 0x3,
-} BLNDV_CONTROL_BLND_ALPHA_MODE;
-typedef enum BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY {
- BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_FALSE = 0x0,
- BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_TRUE = 0x1,
-} BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY;
-typedef enum BLNDV_CONTROL_BLND_MULTIPLIED_MODE {
- BLNDV_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0x0,
- BLNDV_CONTROL_BLND_MULTIPLIED_MODE_TRUE = 0x1,
-} BLNDV_CONTROL_BLND_MULTIPLIED_MODE;
-typedef enum BLNDV_SM_CONTROL2_SM_MODE {
- BLNDV_SM_CONTROL2_SM_MODE_SINGLE_PLANE = 0x0,
- BLNDV_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 0x2,
- BLNDV_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 0x4,
- BLNDV_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING= 0x6,
-} BLNDV_SM_CONTROL2_SM_MODE;
-typedef enum BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE {
- BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0x0,
- BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 0x1,
-} BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE;
-typedef enum BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE {
- BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0x0,
- BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 0x1,
-} BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE;
-typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL {
- BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE= 0x0,
- BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED= 0x1,
- BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW= 0x2,
- BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH= 0x3,
-} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL;
-typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL {
- BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x0,
- BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x1,
- BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW= 0x2,
- BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH= 0x3,
-} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL;
-typedef enum BLNDV_CONTROL2_PTI_ENABLE {
- BLNDV_CONTROL2_PTI_ENABLE_FALSE = 0x0,
- BLNDV_CONTROL2_PTI_ENABLE_TRUE = 0x1,
-} BLNDV_CONTROL2_PTI_ENABLE;
-typedef enum BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN {
- BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0x0,
- BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 0x1,
-} BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN;
-typedef enum BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN {
- BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0x0,
- BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 0x1,
-} BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN;
-typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK {
- BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE= 0x0,
- BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE= 0x1,
-} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK;
-typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK {
- BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE= 0x0,
- BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE= 0x1,
-} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK;
-typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK {
- BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE= 0x0,
- BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE= 0x1,
-} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK;
-typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK {
- BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE= 0x0,
- BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE= 0x1,
-} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK;
-typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK {
- BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE= 0x0,
- BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE= 0x1,
-} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK;
-typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK {
- BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE= 0x0,
- BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE= 0x1,
-} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK;
-typedef enum BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK {
- BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x0,
- BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 0x1,
-} BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK;
-typedef enum BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK {
- BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE= 0x0,
- BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x1,
-} BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK;
-typedef enum BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE {
- BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE= 0x0,
- BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x1,
-} BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE;
-typedef enum BLNDV_DEBUG_BLND_CNV_MUX_SELECT {
- BLNDV_DEBUG_BLND_CNV_MUX_SELECT_LOW = 0x0,
- BLNDV_DEBUG_BLND_CNV_MUX_SELECT_HIGH = 0x1,
-} BLNDV_DEBUG_BLND_CNV_MUX_SELECT;
-typedef enum BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN {
- BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE= 0x0,
- BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE= 0x1,
-} BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN;
-typedef enum DPCSTX_DBG_CFGCLK_SEL {
- DPCSTX_DBG_CFGCLK_SEL_DC_DPCS_INF = 0x0,
- DPCSTX_DBG_CFGCLK_SEL_DPCS_BPHY_INF = 0x1,
- DPCSTX_DBG_CFGCLK_SEL_CBUS_SLAVE = 0x2,
- DPCSTX_DBG_CFGCLK_SEL_CBUS_MASTER = 0x3,
-} DPCSTX_DBG_CFGCLK_SEL;
-typedef enum DPCSTX_TX_SYMCLK_SEL {
- DPCSTX_DBG_TX_SYMCLK_SEL_IN0 = 0x0,
- DPCSTX_DBG_TX_SYMCLK_SEL_IN1 = 0x1,
- DPCSTX_DBG_TX_SYMCLK_SEL_FIFO_WR = 0x2,
-} DPCSTX_TX_SYMCLK_SEL;
-typedef enum DPCSTX_TX_SYMCLK_DIV2_SEL {
- DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT0 = 0x0,
- DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT1 = 0x1,
- DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT2 = 0x2,
- DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT3 = 0x3,
- DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_FIFO_RD = 0x4,
- DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_INT = 0x5,
-} DPCSTX_TX_SYMCLK_DIV2_SEL;
-typedef enum DPCSTX_DBG_CLOCK_SEL {
- DPCSTX_DBG_CLOCK_SEL_DC_CFGCLK = 0x0,
- DPCSTX_DBG_CLOCK_SEL_PHY_CFGCLK = 0x1,
- DPCSTX_DBG_CLOCK_SEL_TXSYMCLK = 0x2,
-} DPCSTX_DBG_CLOCK_SEL;
-typedef enum DPCSTX_DVI_LINK_MODE {
- DPCSTX_DVI_LINK_MODE_NORMAL = 0x0,
- DPCSTX_DVI_LINK_MODE_DUAL_LINK_MASTER = 0x1,
- DPCSTX_DVI_LINK_MODE_DUAL_LINK_SLAVER = 0x2,
-} DPCSTX_DVI_LINK_MODE;
-
-#endif /* DCE_11_2_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_enum.h
deleted file mode 100644
index 6bea30ef3..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_enum.h
+++ /dev/null
@@ -1,1117 +0,0 @@
-/*
- * DCE_8_0 Register documentation
- *
- * Copyright (C) 2016 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef DCE_8_0_ENUM_H
-#define DCE_8_0_ENUM_H
-
-typedef enum SurfaceEndian {
- ENDIAN_NONE = 0x0,
- ENDIAN_8IN16 = 0x1,
- ENDIAN_8IN32 = 0x2,
- ENDIAN_8IN64 = 0x3,
-} SurfaceEndian;
-typedef enum ArrayMode {
- ARRAY_LINEAR_GENERAL = 0x0,
- ARRAY_LINEAR_ALIGNED = 0x1,
- ARRAY_1D_TILED_THIN1 = 0x2,
- ARRAY_1D_TILED_THICK = 0x3,
- ARRAY_2D_TILED_THIN1 = 0x4,
- ARRAY_PRT_TILED_THIN1 = 0x5,
- ARRAY_PRT_2D_TILED_THIN1 = 0x6,
- ARRAY_2D_TILED_THICK = 0x7,
- ARRAY_2D_TILED_XTHICK = 0x8,
- ARRAY_PRT_TILED_THICK = 0x9,
- ARRAY_PRT_2D_TILED_THICK = 0xa,
- ARRAY_PRT_3D_TILED_THIN1 = 0xb,
- ARRAY_3D_TILED_THIN1 = 0xc,
- ARRAY_3D_TILED_THICK = 0xd,
- ARRAY_3D_TILED_XTHICK = 0xe,
- ARRAY_PRT_3D_TILED_THICK = 0xf,
-} ArrayMode;
-typedef enum PipeTiling {
- CONFIG_1_PIPE = 0x0,
- CONFIG_2_PIPE = 0x1,
- CONFIG_4_PIPE = 0x2,
- CONFIG_8_PIPE = 0x3,
-} PipeTiling;
-typedef enum BankTiling {
- CONFIG_4_BANK = 0x0,
- CONFIG_8_BANK = 0x1,
-} BankTiling;
-typedef enum GroupInterleave {
- CONFIG_256B_GROUP = 0x0,
- CONFIG_512B_GROUP = 0x1,
-} GroupInterleave;
-typedef enum RowTiling {
- CONFIG_1KB_ROW = 0x0,
- CONFIG_2KB_ROW = 0x1,
- CONFIG_4KB_ROW = 0x2,
- CONFIG_8KB_ROW = 0x3,
- CONFIG_1KB_ROW_OPT = 0x4,
- CONFIG_2KB_ROW_OPT = 0x5,
- CONFIG_4KB_ROW_OPT = 0x6,
- CONFIG_8KB_ROW_OPT = 0x7,
-} RowTiling;
-typedef enum BankSwapBytes {
- CONFIG_128B_SWAPS = 0x0,
- CONFIG_256B_SWAPS = 0x1,
- CONFIG_512B_SWAPS = 0x2,
- CONFIG_1KB_SWAPS = 0x3,
-} BankSwapBytes;
-typedef enum SampleSplitBytes {
- CONFIG_1KB_SPLIT = 0x0,
- CONFIG_2KB_SPLIT = 0x1,
- CONFIG_4KB_SPLIT = 0x2,
- CONFIG_8KB_SPLIT = 0x3,
-} SampleSplitBytes;
-typedef enum NumPipes {
- ADDR_CONFIG_1_PIPE = 0x0,
- ADDR_CONFIG_2_PIPE = 0x1,
- ADDR_CONFIG_4_PIPE = 0x2,
- ADDR_CONFIG_8_PIPE = 0x3,
-} NumPipes;
-typedef enum PipeInterleaveSize {
- ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
- ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
-} PipeInterleaveSize;
-typedef enum BankInterleaveSize {
- ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
- ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
- ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
- ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
-} BankInterleaveSize;
-typedef enum NumShaderEngines {
- ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
- ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
-} NumShaderEngines;
-typedef enum ShaderEngineTileSize {
- ADDR_CONFIG_SE_TILE_16 = 0x0,
- ADDR_CONFIG_SE_TILE_32 = 0x1,
-} ShaderEngineTileSize;
-typedef enum NumGPUs {
- ADDR_CONFIG_1_GPU = 0x0,
- ADDR_CONFIG_2_GPU = 0x1,
- ADDR_CONFIG_4_GPU = 0x2,
-} NumGPUs;
-typedef enum MultiGPUTileSize {
- ADDR_CONFIG_GPU_TILE_16 = 0x0,
- ADDR_CONFIG_GPU_TILE_32 = 0x1,
- ADDR_CONFIG_GPU_TILE_64 = 0x2,
- ADDR_CONFIG_GPU_TILE_128 = 0x3,
-} MultiGPUTileSize;
-typedef enum RowSize {
- ADDR_CONFIG_1KB_ROW = 0x0,
- ADDR_CONFIG_2KB_ROW = 0x1,
- ADDR_CONFIG_4KB_ROW = 0x2,
-} RowSize;
-typedef enum NumLowerPipes {
- ADDR_CONFIG_1_LOWER_PIPES = 0x0,
- ADDR_CONFIG_2_LOWER_PIPES = 0x1,
-} NumLowerPipes;
-typedef enum DebugBlockId {
- DBG_CLIENT_BLKID_RESERVED = 0x0,
- DBG_CLIENT_BLKID_dbg = 0x1,
- DBG_CLIENT_BLKID_uvdu_0 = 0x2,
- DBG_CLIENT_BLKID_uvdu_1 = 0x3,
- DBG_CLIENT_BLKID_uvdu_2 = 0x4,
- DBG_CLIENT_BLKID_uvdu_3 = 0x5,
- DBG_CLIENT_BLKID_uvdu_4 = 0x6,
- DBG_CLIENT_BLKID_uvdu_5 = 0x7,
- DBG_CLIENT_BLKID_uvdu_6 = 0x8,
- DBG_CLIENT_BLKID_uvdm_0 = 0x9,
- DBG_CLIENT_BLKID_uvdm_1 = 0xa,
- DBG_CLIENT_BLKID_uvdm_2 = 0xb,
- DBG_CLIENT_BLKID_uvdm_3 = 0xc,
- DBG_CLIENT_BLKID_vcea_0 = 0xd,
- DBG_CLIENT_BLKID_vcea_1 = 0xe,
- DBG_CLIENT_BLKID_vcea_2 = 0xf,
- DBG_CLIENT_BLKID_vcea_3 = 0x10,
- DBG_CLIENT_BLKID_vcea_4 = 0x11,
- DBG_CLIENT_BLKID_vcea_5 = 0x12,
- DBG_CLIENT_BLKID_vcea_6 = 0x13,
- DBG_CLIENT_BLKID_vceb_0 = 0x14,
- DBG_CLIENT_BLKID_vceb_1 = 0x15,
- DBG_CLIENT_BLKID_vceb_2 = 0x16,
- DBG_CLIENT_BLKID_dco = 0x17,
- DBG_CLIENT_BLKID_xdma = 0x18,
- DBG_CLIENT_BLKID_smu_0 = 0x19,
- DBG_CLIENT_BLKID_smu_1 = 0x1a,
- DBG_CLIENT_BLKID_smu_2 = 0x1b,
- DBG_CLIENT_BLKID_gck = 0x1c,
- DBG_CLIENT_BLKID_tmonw0 = 0x1d,
- DBG_CLIENT_BLKID_tmonw1 = 0x1e,
- DBG_CLIENT_BLKID_grbm = 0x1f,
- DBG_CLIENT_BLKID_rlc = 0x20,
- DBG_CLIENT_BLKID_ds0 = 0x21,
- DBG_CLIENT_BLKID_cpg_0 = 0x22,
- DBG_CLIENT_BLKID_cpg_1 = 0x23,
- DBG_CLIENT_BLKID_cpc_0 = 0x24,
- DBG_CLIENT_BLKID_cpc_1 = 0x25,
- DBG_CLIENT_BLKID_cpf = 0x26,
- DBG_CLIENT_BLKID_scf0 = 0x27,
- DBG_CLIENT_BLKID_scf1 = 0x28,
- DBG_CLIENT_BLKID_scf2 = 0x29,
- DBG_CLIENT_BLKID_scf3 = 0x2a,
- DBG_CLIENT_BLKID_pc0 = 0x2b,
- DBG_CLIENT_BLKID_pc1 = 0x2c,
- DBG_CLIENT_BLKID_pc2 = 0x2d,
- DBG_CLIENT_BLKID_pc3 = 0x2e,
- DBG_CLIENT_BLKID_vgt0 = 0x2f,
- DBG_CLIENT_BLKID_vgt1 = 0x30,
- DBG_CLIENT_BLKID_vgt2 = 0x31,
- DBG_CLIENT_BLKID_vgt3 = 0x32,
- DBG_CLIENT_BLKID_sx00 = 0x33,
- DBG_CLIENT_BLKID_sx10 = 0x34,
- DBG_CLIENT_BLKID_sx20 = 0x35,
- DBG_CLIENT_BLKID_sx30 = 0x36,
- DBG_CLIENT_BLKID_cb001 = 0x37,
- DBG_CLIENT_BLKID_cb200 = 0x38,
- DBG_CLIENT_BLKID_cb201 = 0x39,
- DBG_CLIENT_BLKID_cbr0 = 0x3a,
- DBG_CLIENT_BLKID_cb000 = 0x3b,
- DBG_CLIENT_BLKID_cb101 = 0x3c,
- DBG_CLIENT_BLKID_cb300 = 0x3d,
- DBG_CLIENT_BLKID_cb301 = 0x3e,
- DBG_CLIENT_BLKID_cbr1 = 0x3f,
- DBG_CLIENT_BLKID_cb100 = 0x40,
- DBG_CLIENT_BLKID_ia0 = 0x41,
- DBG_CLIENT_BLKID_ia1 = 0x42,
- DBG_CLIENT_BLKID_bci0 = 0x43,
- DBG_CLIENT_BLKID_bci1 = 0x44,
- DBG_CLIENT_BLKID_bci2 = 0x45,
- DBG_CLIENT_BLKID_bci3 = 0x46,
- DBG_CLIENT_BLKID_pa0 = 0x47,
- DBG_CLIENT_BLKID_pa1 = 0x48,
- DBG_CLIENT_BLKID_spim0 = 0x49,
- DBG_CLIENT_BLKID_spim1 = 0x4a,
- DBG_CLIENT_BLKID_spim2 = 0x4b,
- DBG_CLIENT_BLKID_spim3 = 0x4c,
- DBG_CLIENT_BLKID_sdma = 0x4d,
- DBG_CLIENT_BLKID_ih = 0x4e,
- DBG_CLIENT_BLKID_sem = 0x4f,
- DBG_CLIENT_BLKID_srbm = 0x50,
- DBG_CLIENT_BLKID_hdp = 0x51,
- DBG_CLIENT_BLKID_acp_0 = 0x52,
- DBG_CLIENT_BLKID_acp_1 = 0x53,
- DBG_CLIENT_BLKID_sam = 0x54,
- DBG_CLIENT_BLKID_mcc0 = 0x55,
- DBG_CLIENT_BLKID_mcc1 = 0x56,
- DBG_CLIENT_BLKID_mcc2 = 0x57,
- DBG_CLIENT_BLKID_mcc3 = 0x58,
- DBG_CLIENT_BLKID_mcd0 = 0x59,
- DBG_CLIENT_BLKID_mcd1 = 0x5a,
- DBG_CLIENT_BLKID_mcd2 = 0x5b,
- DBG_CLIENT_BLKID_mcd3 = 0x5c,
- DBG_CLIENT_BLKID_mcb = 0x5d,
- DBG_CLIENT_BLKID_vmc = 0x5e,
- DBG_CLIENT_BLKID_gmcon = 0x5f,
- DBG_CLIENT_BLKID_gdc_0 = 0x60,
- DBG_CLIENT_BLKID_gdc_1 = 0x61,
- DBG_CLIENT_BLKID_gdc_2 = 0x62,
- DBG_CLIENT_BLKID_gdc_3 = 0x63,
- DBG_CLIENT_BLKID_gdc_4 = 0x64,
- DBG_CLIENT_BLKID_gdc_5 = 0x65,
- DBG_CLIENT_BLKID_gdc_6 = 0x66,
- DBG_CLIENT_BLKID_gdc_7 = 0x67,
- DBG_CLIENT_BLKID_gdc_8 = 0x68,
- DBG_CLIENT_BLKID_gdc_9 = 0x69,
- DBG_CLIENT_BLKID_gdc_10 = 0x6a,
- DBG_CLIENT_BLKID_gdc_11 = 0x6b,
- DBG_CLIENT_BLKID_gdc_12 = 0x6c,
- DBG_CLIENT_BLKID_gdc_13 = 0x6d,
- DBG_CLIENT_BLKID_gdc_14 = 0x6e,
- DBG_CLIENT_BLKID_gdc_15 = 0x6f,
- DBG_CLIENT_BLKID_gdc_16 = 0x70,
- DBG_CLIENT_BLKID_gdc_17 = 0x71,
- DBG_CLIENT_BLKID_gdc_18 = 0x72,
- DBG_CLIENT_BLKID_gdc_19 = 0x73,
- DBG_CLIENT_BLKID_gdc_20 = 0x74,
- DBG_CLIENT_BLKID_gdc_21 = 0x75,
- DBG_CLIENT_BLKID_gdc_22 = 0x76,
- DBG_CLIENT_BLKID_wd = 0x77,
- DBG_CLIENT_BLKID_sdma_0 = 0x78,
- DBG_CLIENT_BLKID_sdma_1 = 0x79,
-} DebugBlockId;
-typedef enum DebugBlockId_OLD {
- DBG_BLOCK_ID_RESERVED = 0x0,
- DBG_BLOCK_ID_DBG = 0x1,
- DBG_BLOCK_ID_VMC = 0x2,
- DBG_BLOCK_ID_PDMA = 0x3,
- DBG_BLOCK_ID_CG = 0x4,
- DBG_BLOCK_ID_SRBM = 0x5,
- DBG_BLOCK_ID_GRBM = 0x6,
- DBG_BLOCK_ID_RLC = 0x7,
- DBG_BLOCK_ID_CSC = 0x8,
- DBG_BLOCK_ID_SEM = 0x9,
- DBG_BLOCK_ID_IH = 0xa,
- DBG_BLOCK_ID_SC = 0xb,
- DBG_BLOCK_ID_SQ = 0xc,
- DBG_BLOCK_ID_AVP = 0xd,
- DBG_BLOCK_ID_GMCON = 0xe,
- DBG_BLOCK_ID_SMU = 0xf,
- DBG_BLOCK_ID_DMA0 = 0x10,
- DBG_BLOCK_ID_DMA1 = 0x11,
- DBG_BLOCK_ID_SPIM = 0x12,
- DBG_BLOCK_ID_GDS = 0x13,
- DBG_BLOCK_ID_SPIS = 0x14,
- DBG_BLOCK_ID_UNUSED0 = 0x15,
- DBG_BLOCK_ID_PA0 = 0x16,
- DBG_BLOCK_ID_PA1 = 0x17,
- DBG_BLOCK_ID_CP0 = 0x18,
- DBG_BLOCK_ID_CP1 = 0x19,
- DBG_BLOCK_ID_CP2 = 0x1a,
- DBG_BLOCK_ID_UNUSED1 = 0x1b,
- DBG_BLOCK_ID_UVDU = 0x1c,
- DBG_BLOCK_ID_UVDM = 0x1d,
- DBG_BLOCK_ID_VCE = 0x1e,
- DBG_BLOCK_ID_UNUSED2 = 0x1f,
- DBG_BLOCK_ID_VGT0 = 0x20,
- DBG_BLOCK_ID_VGT1 = 0x21,
- DBG_BLOCK_ID_IA = 0x22,
- DBG_BLOCK_ID_UNUSED3 = 0x23,
- DBG_BLOCK_ID_SCT0 = 0x24,
- DBG_BLOCK_ID_SCT1 = 0x25,
- DBG_BLOCK_ID_SPM0 = 0x26,
- DBG_BLOCK_ID_SPM1 = 0x27,
- DBG_BLOCK_ID_TCAA = 0x28,
- DBG_BLOCK_ID_TCAB = 0x29,
- DBG_BLOCK_ID_TCCA = 0x2a,
- DBG_BLOCK_ID_TCCB = 0x2b,
- DBG_BLOCK_ID_MCC0 = 0x2c,
- DBG_BLOCK_ID_MCC1 = 0x2d,
- DBG_BLOCK_ID_MCC2 = 0x2e,
- DBG_BLOCK_ID_MCC3 = 0x2f,
- DBG_BLOCK_ID_SX0 = 0x30,
- DBG_BLOCK_ID_SX1 = 0x31,
- DBG_BLOCK_ID_SX2 = 0x32,
- DBG_BLOCK_ID_SX3 = 0x33,
- DBG_BLOCK_ID_UNUSED4 = 0x34,
- DBG_BLOCK_ID_UNUSED5 = 0x35,
- DBG_BLOCK_ID_UNUSED6 = 0x36,
- DBG_BLOCK_ID_UNUSED7 = 0x37,
- DBG_BLOCK_ID_PC0 = 0x38,
- DBG_BLOCK_ID_PC1 = 0x39,
- DBG_BLOCK_ID_UNUSED8 = 0x3a,
- DBG_BLOCK_ID_UNUSED9 = 0x3b,
- DBG_BLOCK_ID_UNUSED10 = 0x3c,
- DBG_BLOCK_ID_UNUSED11 = 0x3d,
- DBG_BLOCK_ID_MCB = 0x3e,
- DBG_BLOCK_ID_UNUSED12 = 0x3f,
- DBG_BLOCK_ID_SCB0 = 0x40,
- DBG_BLOCK_ID_SCB1 = 0x41,
- DBG_BLOCK_ID_UNUSED13 = 0x42,
- DBG_BLOCK_ID_UNUSED14 = 0x43,
- DBG_BLOCK_ID_SCF0 = 0x44,
- DBG_BLOCK_ID_SCF1 = 0x45,
- DBG_BLOCK_ID_UNUSED15 = 0x46,
- DBG_BLOCK_ID_UNUSED16 = 0x47,
- DBG_BLOCK_ID_BCI0 = 0x48,
- DBG_BLOCK_ID_BCI1 = 0x49,
- DBG_BLOCK_ID_BCI2 = 0x4a,
- DBG_BLOCK_ID_BCI3 = 0x4b,
- DBG_BLOCK_ID_UNUSED17 = 0x4c,
- DBG_BLOCK_ID_UNUSED18 = 0x4d,
- DBG_BLOCK_ID_UNUSED19 = 0x4e,
- DBG_BLOCK_ID_UNUSED20 = 0x4f,
- DBG_BLOCK_ID_CB00 = 0x50,
- DBG_BLOCK_ID_CB01 = 0x51,
- DBG_BLOCK_ID_CB02 = 0x52,
- DBG_BLOCK_ID_CB03 = 0x53,
- DBG_BLOCK_ID_CB04 = 0x54,
- DBG_BLOCK_ID_UNUSED21 = 0x55,
- DBG_BLOCK_ID_UNUSED22 = 0x56,
- DBG_BLOCK_ID_UNUSED23 = 0x57,
- DBG_BLOCK_ID_CB10 = 0x58,
- DBG_BLOCK_ID_CB11 = 0x59,
- DBG_BLOCK_ID_CB12 = 0x5a,
- DBG_BLOCK_ID_CB13 = 0x5b,
- DBG_BLOCK_ID_CB14 = 0x5c,
- DBG_BLOCK_ID_UNUSED24 = 0x5d,
- DBG_BLOCK_ID_UNUSED25 = 0x5e,
- DBG_BLOCK_ID_UNUSED26 = 0x5f,
- DBG_BLOCK_ID_TCP0 = 0x60,
- DBG_BLOCK_ID_TCP1 = 0x61,
- DBG_BLOCK_ID_TCP2 = 0x62,
- DBG_BLOCK_ID_TCP3 = 0x63,
- DBG_BLOCK_ID_TCP4 = 0x64,
- DBG_BLOCK_ID_TCP5 = 0x65,
- DBG_BLOCK_ID_TCP6 = 0x66,
- DBG_BLOCK_ID_TCP7 = 0x67,
- DBG_BLOCK_ID_TCP8 = 0x68,
- DBG_BLOCK_ID_TCP9 = 0x69,
- DBG_BLOCK_ID_TCP10 = 0x6a,
- DBG_BLOCK_ID_TCP11 = 0x6b,
- DBG_BLOCK_ID_TCP12 = 0x6c,
- DBG_BLOCK_ID_TCP13 = 0x6d,
- DBG_BLOCK_ID_TCP14 = 0x6e,
- DBG_BLOCK_ID_TCP15 = 0x6f,
- DBG_BLOCK_ID_TCP16 = 0x70,
- DBG_BLOCK_ID_TCP17 = 0x71,
- DBG_BLOCK_ID_TCP18 = 0x72,
- DBG_BLOCK_ID_TCP19 = 0x73,
- DBG_BLOCK_ID_TCP20 = 0x74,
- DBG_BLOCK_ID_TCP21 = 0x75,
- DBG_BLOCK_ID_TCP22 = 0x76,
- DBG_BLOCK_ID_TCP23 = 0x77,
- DBG_BLOCK_ID_TCP_RESERVED0 = 0x78,
- DBG_BLOCK_ID_TCP_RESERVED1 = 0x79,
- DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a,
- DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b,
- DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c,
- DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d,
- DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e,
- DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f,
- DBG_BLOCK_ID_DB00 = 0x80,
- DBG_BLOCK_ID_DB01 = 0x81,
- DBG_BLOCK_ID_DB02 = 0x82,
- DBG_BLOCK_ID_DB03 = 0x83,
- DBG_BLOCK_ID_DB04 = 0x84,
- DBG_BLOCK_ID_UNUSED27 = 0x85,
- DBG_BLOCK_ID_UNUSED28 = 0x86,
- DBG_BLOCK_ID_UNUSED29 = 0x87,
- DBG_BLOCK_ID_DB10 = 0x88,
- DBG_BLOCK_ID_DB11 = 0x89,
- DBG_BLOCK_ID_DB12 = 0x8a,
- DBG_BLOCK_ID_DB13 = 0x8b,
- DBG_BLOCK_ID_DB14 = 0x8c,
- DBG_BLOCK_ID_UNUSED30 = 0x8d,
- DBG_BLOCK_ID_UNUSED31 = 0x8e,
- DBG_BLOCK_ID_UNUSED32 = 0x8f,
- DBG_BLOCK_ID_TCC0 = 0x90,
- DBG_BLOCK_ID_TCC1 = 0x91,
- DBG_BLOCK_ID_TCC2 = 0x92,
- DBG_BLOCK_ID_TCC3 = 0x93,
- DBG_BLOCK_ID_TCC4 = 0x94,
- DBG_BLOCK_ID_TCC5 = 0x95,
- DBG_BLOCK_ID_TCC6 = 0x96,
- DBG_BLOCK_ID_TCC7 = 0x97,
- DBG_BLOCK_ID_SPS00 = 0x98,
- DBG_BLOCK_ID_SPS01 = 0x99,
- DBG_BLOCK_ID_SPS02 = 0x9a,
- DBG_BLOCK_ID_SPS10 = 0x9b,
- DBG_BLOCK_ID_SPS11 = 0x9c,
- DBG_BLOCK_ID_SPS12 = 0x9d,
- DBG_BLOCK_ID_UNUSED33 = 0x9e,
- DBG_BLOCK_ID_UNUSED34 = 0x9f,
- DBG_BLOCK_ID_TA00 = 0xa0,
- DBG_BLOCK_ID_TA01 = 0xa1,
- DBG_BLOCK_ID_TA02 = 0xa2,
- DBG_BLOCK_ID_TA03 = 0xa3,
- DBG_BLOCK_ID_TA04 = 0xa4,
- DBG_BLOCK_ID_TA05 = 0xa5,
- DBG_BLOCK_ID_TA06 = 0xa6,
- DBG_BLOCK_ID_TA07 = 0xa7,
- DBG_BLOCK_ID_TA08 = 0xa8,
- DBG_BLOCK_ID_TA09 = 0xa9,
- DBG_BLOCK_ID_TA0A = 0xaa,
- DBG_BLOCK_ID_TA0B = 0xab,
- DBG_BLOCK_ID_UNUSED35 = 0xac,
- DBG_BLOCK_ID_UNUSED36 = 0xad,
- DBG_BLOCK_ID_UNUSED37 = 0xae,
- DBG_BLOCK_ID_UNUSED38 = 0xaf,
- DBG_BLOCK_ID_TA10 = 0xb0,
- DBG_BLOCK_ID_TA11 = 0xb1,
- DBG_BLOCK_ID_TA12 = 0xb2,
- DBG_BLOCK_ID_TA13 = 0xb3,
- DBG_BLOCK_ID_TA14 = 0xb4,
- DBG_BLOCK_ID_TA15 = 0xb5,
- DBG_BLOCK_ID_TA16 = 0xb6,
- DBG_BLOCK_ID_TA17 = 0xb7,
- DBG_BLOCK_ID_TA18 = 0xb8,
- DBG_BLOCK_ID_TA19 = 0xb9,
- DBG_BLOCK_ID_TA1A = 0xba,
- DBG_BLOCK_ID_TA1B = 0xbb,
- DBG_BLOCK_ID_UNUSED39 = 0xbc,
- DBG_BLOCK_ID_UNUSED40 = 0xbd,
- DBG_BLOCK_ID_UNUSED41 = 0xbe,
- DBG_BLOCK_ID_UNUSED42 = 0xbf,
- DBG_BLOCK_ID_TD00 = 0xc0,
- DBG_BLOCK_ID_TD01 = 0xc1,
- DBG_BLOCK_ID_TD02 = 0xc2,
- DBG_BLOCK_ID_TD03 = 0xc3,
- DBG_BLOCK_ID_TD04 = 0xc4,
- DBG_BLOCK_ID_TD05 = 0xc5,
- DBG_BLOCK_ID_TD06 = 0xc6,
- DBG_BLOCK_ID_TD07 = 0xc7,
- DBG_BLOCK_ID_TD08 = 0xc8,
- DBG_BLOCK_ID_TD09 = 0xc9,
- DBG_BLOCK_ID_TD0A = 0xca,
- DBG_BLOCK_ID_TD0B = 0xcb,
- DBG_BLOCK_ID_UNUSED43 = 0xcc,
- DBG_BLOCK_ID_UNUSED44 = 0xcd,
- DBG_BLOCK_ID_UNUSED45 = 0xce,
- DBG_BLOCK_ID_UNUSED46 = 0xcf,
- DBG_BLOCK_ID_TD10 = 0xd0,
- DBG_BLOCK_ID_TD11 = 0xd1,
- DBG_BLOCK_ID_TD12 = 0xd2,
- DBG_BLOCK_ID_TD13 = 0xd3,
- DBG_BLOCK_ID_TD14 = 0xd4,
- DBG_BLOCK_ID_TD15 = 0xd5,
- DBG_BLOCK_ID_TD16 = 0xd6,
- DBG_BLOCK_ID_TD17 = 0xd7,
- DBG_BLOCK_ID_TD18 = 0xd8,
- DBG_BLOCK_ID_TD19 = 0xd9,
- DBG_BLOCK_ID_TD1A = 0xda,
- DBG_BLOCK_ID_TD1B = 0xdb,
- DBG_BLOCK_ID_UNUSED47 = 0xdc,
- DBG_BLOCK_ID_UNUSED48 = 0xdd,
- DBG_BLOCK_ID_UNUSED49 = 0xde,
- DBG_BLOCK_ID_UNUSED50 = 0xdf,
- DBG_BLOCK_ID_MCD0 = 0xe0,
- DBG_BLOCK_ID_MCD1 = 0xe1,
- DBG_BLOCK_ID_MCD2 = 0xe2,
- DBG_BLOCK_ID_MCD3 = 0xe3,
- DBG_BLOCK_ID_MCD4 = 0xe4,
- DBG_BLOCK_ID_MCD5 = 0xe5,
- DBG_BLOCK_ID_UNUSED51 = 0xe6,
- DBG_BLOCK_ID_UNUSED52 = 0xe7,
-} DebugBlockId_OLD;
-typedef enum DebugBlockId_BY2 {
- DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
- DBG_BLOCK_ID_VMC_BY2 = 0x1,
- DBG_BLOCK_ID_CG_BY2 = 0x2,
- DBG_BLOCK_ID_GRBM_BY2 = 0x3,
- DBG_BLOCK_ID_CSC_BY2 = 0x4,
- DBG_BLOCK_ID_IH_BY2 = 0x5,
- DBG_BLOCK_ID_SQ_BY2 = 0x6,
- DBG_BLOCK_ID_GMCON_BY2 = 0x7,
- DBG_BLOCK_ID_DMA0_BY2 = 0x8,
- DBG_BLOCK_ID_SPIM_BY2 = 0x9,
- DBG_BLOCK_ID_SPIS_BY2 = 0xa,
- DBG_BLOCK_ID_PA0_BY2 = 0xb,
- DBG_BLOCK_ID_CP0_BY2 = 0xc,
- DBG_BLOCK_ID_CP2_BY2 = 0xd,
- DBG_BLOCK_ID_UVDU_BY2 = 0xe,
- DBG_BLOCK_ID_VCE_BY2 = 0xf,
- DBG_BLOCK_ID_VGT0_BY2 = 0x10,
- DBG_BLOCK_ID_IA_BY2 = 0x11,
- DBG_BLOCK_ID_SCT0_BY2 = 0x12,
- DBG_BLOCK_ID_SPM0_BY2 = 0x13,
- DBG_BLOCK_ID_TCAA_BY2 = 0x14,
- DBG_BLOCK_ID_TCCA_BY2 = 0x15,
- DBG_BLOCK_ID_MCC0_BY2 = 0x16,
- DBG_BLOCK_ID_MCC2_BY2 = 0x17,
- DBG_BLOCK_ID_SX0_BY2 = 0x18,
- DBG_BLOCK_ID_SX2_BY2 = 0x19,
- DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a,
- DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b,
- DBG_BLOCK_ID_PC0_BY2 = 0x1c,
- DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d,
- DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e,
- DBG_BLOCK_ID_MCB_BY2 = 0x1f,
- DBG_BLOCK_ID_SCB0_BY2 = 0x20,
- DBG_BLOCK_ID_UNUSED13_BY2 = 0x21,
- DBG_BLOCK_ID_SCF0_BY2 = 0x22,
- DBG_BLOCK_ID_UNUSED15_BY2 = 0x23,
- DBG_BLOCK_ID_BCI0_BY2 = 0x24,
- DBG_BLOCK_ID_BCI2_BY2 = 0x25,
- DBG_BLOCK_ID_UNUSED17_BY2 = 0x26,
- DBG_BLOCK_ID_UNUSED19_BY2 = 0x27,
- DBG_BLOCK_ID_CB00_BY2 = 0x28,
- DBG_BLOCK_ID_CB02_BY2 = 0x29,
- DBG_BLOCK_ID_CB04_BY2 = 0x2a,
- DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b,
- DBG_BLOCK_ID_CB10_BY2 = 0x2c,
- DBG_BLOCK_ID_CB12_BY2 = 0x2d,
- DBG_BLOCK_ID_CB14_BY2 = 0x2e,
- DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f,
- DBG_BLOCK_ID_TCP0_BY2 = 0x30,
- DBG_BLOCK_ID_TCP2_BY2 = 0x31,
- DBG_BLOCK_ID_TCP4_BY2 = 0x32,
- DBG_BLOCK_ID_TCP6_BY2 = 0x33,
- DBG_BLOCK_ID_TCP8_BY2 = 0x34,
- DBG_BLOCK_ID_TCP10_BY2 = 0x35,
- DBG_BLOCK_ID_TCP12_BY2 = 0x36,
- DBG_BLOCK_ID_TCP14_BY2 = 0x37,
- DBG_BLOCK_ID_TCP16_BY2 = 0x38,
- DBG_BLOCK_ID_TCP18_BY2 = 0x39,
- DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
- DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
- DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
- DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
- DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
- DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
- DBG_BLOCK_ID_DB00_BY2 = 0x40,
- DBG_BLOCK_ID_DB02_BY2 = 0x41,
- DBG_BLOCK_ID_DB04_BY2 = 0x42,
- DBG_BLOCK_ID_UNUSED28_BY2 = 0x43,
- DBG_BLOCK_ID_DB10_BY2 = 0x44,
- DBG_BLOCK_ID_DB12_BY2 = 0x45,
- DBG_BLOCK_ID_DB14_BY2 = 0x46,
- DBG_BLOCK_ID_UNUSED31_BY2 = 0x47,
- DBG_BLOCK_ID_TCC0_BY2 = 0x48,
- DBG_BLOCK_ID_TCC2_BY2 = 0x49,
- DBG_BLOCK_ID_TCC4_BY2 = 0x4a,
- DBG_BLOCK_ID_TCC6_BY2 = 0x4b,
- DBG_BLOCK_ID_SPS00_BY2 = 0x4c,
- DBG_BLOCK_ID_SPS02_BY2 = 0x4d,
- DBG_BLOCK_ID_SPS11_BY2 = 0x4e,
- DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f,
- DBG_BLOCK_ID_TA00_BY2 = 0x50,
- DBG_BLOCK_ID_TA02_BY2 = 0x51,
- DBG_BLOCK_ID_TA04_BY2 = 0x52,
- DBG_BLOCK_ID_TA06_BY2 = 0x53,
- DBG_BLOCK_ID_TA08_BY2 = 0x54,
- DBG_BLOCK_ID_TA0A_BY2 = 0x55,
- DBG_BLOCK_ID_UNUSED35_BY2 = 0x56,
- DBG_BLOCK_ID_UNUSED37_BY2 = 0x57,
- DBG_BLOCK_ID_TA10_BY2 = 0x58,
- DBG_BLOCK_ID_TA12_BY2 = 0x59,
- DBG_BLOCK_ID_TA14_BY2 = 0x5a,
- DBG_BLOCK_ID_TA16_BY2 = 0x5b,
- DBG_BLOCK_ID_TA18_BY2 = 0x5c,
- DBG_BLOCK_ID_TA1A_BY2 = 0x5d,
- DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e,
- DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f,
- DBG_BLOCK_ID_TD00_BY2 = 0x60,
- DBG_BLOCK_ID_TD02_BY2 = 0x61,
- DBG_BLOCK_ID_TD04_BY2 = 0x62,
- DBG_BLOCK_ID_TD06_BY2 = 0x63,
- DBG_BLOCK_ID_TD08_BY2 = 0x64,
- DBG_BLOCK_ID_TD0A_BY2 = 0x65,
- DBG_BLOCK_ID_UNUSED43_BY2 = 0x66,
- DBG_BLOCK_ID_UNUSED45_BY2 = 0x67,
- DBG_BLOCK_ID_TD10_BY2 = 0x68,
- DBG_BLOCK_ID_TD12_BY2 = 0x69,
- DBG_BLOCK_ID_TD14_BY2 = 0x6a,
- DBG_BLOCK_ID_TD16_BY2 = 0x6b,
- DBG_BLOCK_ID_TD18_BY2 = 0x6c,
- DBG_BLOCK_ID_TD1A_BY2 = 0x6d,
- DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e,
- DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f,
- DBG_BLOCK_ID_MCD0_BY2 = 0x70,
- DBG_BLOCK_ID_MCD2_BY2 = 0x71,
- DBG_BLOCK_ID_MCD4_BY2 = 0x72,
- DBG_BLOCK_ID_UNUSED51_BY2 = 0x73,
-} DebugBlockId_BY2;
-typedef enum DebugBlockId_BY4 {
- DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
- DBG_BLOCK_ID_CG_BY4 = 0x1,
- DBG_BLOCK_ID_CSC_BY4 = 0x2,
- DBG_BLOCK_ID_SQ_BY4 = 0x3,
- DBG_BLOCK_ID_DMA0_BY4 = 0x4,
- DBG_BLOCK_ID_SPIS_BY4 = 0x5,
- DBG_BLOCK_ID_CP0_BY4 = 0x6,
- DBG_BLOCK_ID_UVDU_BY4 = 0x7,
- DBG_BLOCK_ID_VGT0_BY4 = 0x8,
- DBG_BLOCK_ID_SCT0_BY4 = 0x9,
- DBG_BLOCK_ID_TCAA_BY4 = 0xa,
- DBG_BLOCK_ID_MCC0_BY4 = 0xb,
- DBG_BLOCK_ID_SX0_BY4 = 0xc,
- DBG_BLOCK_ID_UNUSED4_BY4 = 0xd,
- DBG_BLOCK_ID_PC0_BY4 = 0xe,
- DBG_BLOCK_ID_UNUSED10_BY4 = 0xf,
- DBG_BLOCK_ID_SCB0_BY4 = 0x10,
- DBG_BLOCK_ID_SCF0_BY4 = 0x11,
- DBG_BLOCK_ID_BCI0_BY4 = 0x12,
- DBG_BLOCK_ID_UNUSED17_BY4 = 0x13,
- DBG_BLOCK_ID_CB00_BY4 = 0x14,
- DBG_BLOCK_ID_CB04_BY4 = 0x15,
- DBG_BLOCK_ID_CB10_BY4 = 0x16,
- DBG_BLOCK_ID_CB14_BY4 = 0x17,
- DBG_BLOCK_ID_TCP0_BY4 = 0x18,
- DBG_BLOCK_ID_TCP4_BY4 = 0x19,
- DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
- DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
- DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
- DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
- DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
- DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
- DBG_BLOCK_ID_DB_BY4 = 0x20,
- DBG_BLOCK_ID_DB04_BY4 = 0x21,
- DBG_BLOCK_ID_DB10_BY4 = 0x22,
- DBG_BLOCK_ID_DB14_BY4 = 0x23,
- DBG_BLOCK_ID_TCC0_BY4 = 0x24,
- DBG_BLOCK_ID_TCC4_BY4 = 0x25,
- DBG_BLOCK_ID_SPS00_BY4 = 0x26,
- DBG_BLOCK_ID_SPS11_BY4 = 0x27,
- DBG_BLOCK_ID_TA00_BY4 = 0x28,
- DBG_BLOCK_ID_TA04_BY4 = 0x29,
- DBG_BLOCK_ID_TA08_BY4 = 0x2a,
- DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b,
- DBG_BLOCK_ID_TA10_BY4 = 0x2c,
- DBG_BLOCK_ID_TA14_BY4 = 0x2d,
- DBG_BLOCK_ID_TA18_BY4 = 0x2e,
- DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f,
- DBG_BLOCK_ID_TD00_BY4 = 0x30,
- DBG_BLOCK_ID_TD04_BY4 = 0x31,
- DBG_BLOCK_ID_TD08_BY4 = 0x32,
- DBG_BLOCK_ID_UNUSED43_BY4 = 0x33,
- DBG_BLOCK_ID_TD10_BY4 = 0x34,
- DBG_BLOCK_ID_TD14_BY4 = 0x35,
- DBG_BLOCK_ID_TD18_BY4 = 0x36,
- DBG_BLOCK_ID_UNUSED47_BY4 = 0x37,
- DBG_BLOCK_ID_MCD0_BY4 = 0x38,
- DBG_BLOCK_ID_MCD4_BY4 = 0x39,
-} DebugBlockId_BY4;
-typedef enum DebugBlockId_BY8 {
- DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
- DBG_BLOCK_ID_CSC_BY8 = 0x1,
- DBG_BLOCK_ID_DMA0_BY8 = 0x2,
- DBG_BLOCK_ID_CP0_BY8 = 0x3,
- DBG_BLOCK_ID_VGT0_BY8 = 0x4,
- DBG_BLOCK_ID_TCAA_BY8 = 0x5,
- DBG_BLOCK_ID_SX0_BY8 = 0x6,
- DBG_BLOCK_ID_PC0_BY8 = 0x7,
- DBG_BLOCK_ID_SCB0_BY8 = 0x8,
- DBG_BLOCK_ID_BCI0_BY8 = 0x9,
- DBG_BLOCK_ID_CB00_BY8 = 0xa,
- DBG_BLOCK_ID_CB10_BY8 = 0xb,
- DBG_BLOCK_ID_TCP0_BY8 = 0xc,
- DBG_BLOCK_ID_TCP8_BY8 = 0xd,
- DBG_BLOCK_ID_TCP16_BY8 = 0xe,
- DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
- DBG_BLOCK_ID_DB00_BY8 = 0x10,
- DBG_BLOCK_ID_DB10_BY8 = 0x11,
- DBG_BLOCK_ID_TCC0_BY8 = 0x12,
- DBG_BLOCK_ID_SPS00_BY8 = 0x13,
- DBG_BLOCK_ID_TA00_BY8 = 0x14,
- DBG_BLOCK_ID_TA08_BY8 = 0x15,
- DBG_BLOCK_ID_TA10_BY8 = 0x16,
- DBG_BLOCK_ID_TA18_BY8 = 0x17,
- DBG_BLOCK_ID_TD00_BY8 = 0x18,
- DBG_BLOCK_ID_TD08_BY8 = 0x19,
- DBG_BLOCK_ID_TD10_BY8 = 0x1a,
- DBG_BLOCK_ID_TD18_BY8 = 0x1b,
- DBG_BLOCK_ID_MCD0_BY8 = 0x1c,
-} DebugBlockId_BY8;
-typedef enum DebugBlockId_BY16 {
- DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
- DBG_BLOCK_ID_DMA0_BY16 = 0x1,
- DBG_BLOCK_ID_VGT0_BY16 = 0x2,
- DBG_BLOCK_ID_SX0_BY16 = 0x3,
- DBG_BLOCK_ID_SCB0_BY16 = 0x4,
- DBG_BLOCK_ID_CB00_BY16 = 0x5,
- DBG_BLOCK_ID_TCP0_BY16 = 0x6,
- DBG_BLOCK_ID_TCP16_BY16 = 0x7,
- DBG_BLOCK_ID_DB00_BY16 = 0x8,
- DBG_BLOCK_ID_TCC0_BY16 = 0x9,
- DBG_BLOCK_ID_TA00_BY16 = 0xa,
- DBG_BLOCK_ID_TA10_BY16 = 0xb,
- DBG_BLOCK_ID_TD00_BY16 = 0xc,
- DBG_BLOCK_ID_TD10_BY16 = 0xd,
- DBG_BLOCK_ID_MCD0_BY16 = 0xe,
-} DebugBlockId_BY16;
-typedef enum CompareRef {
- REF_NEVER = 0x0,
- REF_LESS = 0x1,
- REF_EQUAL = 0x2,
- REF_LEQUAL = 0x3,
- REF_GREATER = 0x4,
- REF_NOTEQUAL = 0x5,
- REF_GEQUAL = 0x6,
- REF_ALWAYS = 0x7,
-} CompareRef;
-typedef enum ReadSize {
- READ_256_BITS = 0x0,
- READ_512_BITS = 0x1,
-} ReadSize;
-typedef enum DepthFormat {
- DEPTH_INVALID = 0x0,
- DEPTH_16 = 0x1,
- DEPTH_X8_24 = 0x2,
- DEPTH_8_24 = 0x3,
- DEPTH_X8_24_FLOAT = 0x4,
- DEPTH_8_24_FLOAT = 0x5,
- DEPTH_32_FLOAT = 0x6,
- DEPTH_X24_8_32_FLOAT = 0x7,
-} DepthFormat;
-typedef enum ZFormat {
- Z_INVALID = 0x0,
- Z_16 = 0x1,
- Z_24 = 0x2,
- Z_32_FLOAT = 0x3,
-} ZFormat;
-typedef enum StencilFormat {
- STENCIL_INVALID = 0x0,
- STENCIL_8 = 0x1,
-} StencilFormat;
-typedef enum CmaskMode {
- CMASK_CLEAR_NONE = 0x0,
- CMASK_CLEAR_ONE = 0x1,
- CMASK_CLEAR_ALL = 0x2,
- CMASK_ANY_EXPANDED = 0x3,
- CMASK_ALPHA0_FRAG1 = 0x4,
- CMASK_ALPHA0_FRAG2 = 0x5,
- CMASK_ALPHA0_FRAG4 = 0x6,
- CMASK_ALPHA0_FRAGS = 0x7,
- CMASK_ALPHA1_FRAG1 = 0x8,
- CMASK_ALPHA1_FRAG2 = 0x9,
- CMASK_ALPHA1_FRAG4 = 0xa,
- CMASK_ALPHA1_FRAGS = 0xb,
- CMASK_ALPHAX_FRAG1 = 0xc,
- CMASK_ALPHAX_FRAG2 = 0xd,
- CMASK_ALPHAX_FRAG4 = 0xe,
- CMASK_ALPHAX_FRAGS = 0xf,
-} CmaskMode;
-typedef enum QuadExportFormat {
- EXPORT_UNUSED = 0x0,
- EXPORT_32_R = 0x1,
- EXPORT_32_GR = 0x2,
- EXPORT_32_AR = 0x3,
- EXPORT_FP16_ABGR = 0x4,
- EXPORT_UNSIGNED16_ABGR = 0x5,
- EXPORT_SIGNED16_ABGR = 0x6,
- EXPORT_32_ABGR = 0x7,
-} QuadExportFormat;
-typedef enum QuadExportFormatOld {
- EXPORT_4P_32BPC_ABGR = 0x0,
- EXPORT_4P_16BPC_ABGR = 0x1,
- EXPORT_4P_32BPC_GR = 0x2,
- EXPORT_4P_32BPC_AR = 0x3,
- EXPORT_2P_32BPC_ABGR = 0x4,
- EXPORT_8P_32BPC_R = 0x5,
-} QuadExportFormatOld;
-typedef enum ColorFormat {
- COLOR_INVALID = 0x0,
- COLOR_8 = 0x1,
- COLOR_16 = 0x2,
- COLOR_8_8 = 0x3,
- COLOR_32 = 0x4,
- COLOR_16_16 = 0x5,
- COLOR_10_11_11 = 0x6,
- COLOR_11_11_10 = 0x7,
- COLOR_10_10_10_2 = 0x8,
- COLOR_2_10_10_10 = 0x9,
- COLOR_8_8_8_8 = 0xa,
- COLOR_32_32 = 0xb,
- COLOR_16_16_16_16 = 0xc,
- COLOR_RESERVED_13 = 0xd,
- COLOR_32_32_32_32 = 0xe,
- COLOR_RESERVED_15 = 0xf,
- COLOR_5_6_5 = 0x10,
- COLOR_1_5_5_5 = 0x11,
- COLOR_5_5_5_1 = 0x12,
- COLOR_4_4_4_4 = 0x13,
- COLOR_8_24 = 0x14,
- COLOR_24_8 = 0x15,
- COLOR_X24_8_32_FLOAT = 0x16,
- COLOR_RESERVED_23 = 0x17,
-} ColorFormat;
-typedef enum SurfaceFormat {
- FMT_INVALID = 0x0,
- FMT_8 = 0x1,
- FMT_16 = 0x2,
- FMT_8_8 = 0x3,
- FMT_32 = 0x4,
- FMT_16_16 = 0x5,
- FMT_10_11_11 = 0x6,
- FMT_11_11_10 = 0x7,
- FMT_10_10_10_2 = 0x8,
- FMT_2_10_10_10 = 0x9,
- FMT_8_8_8_8 = 0xa,
- FMT_32_32 = 0xb,
- FMT_16_16_16_16 = 0xc,
- FMT_32_32_32 = 0xd,
- FMT_32_32_32_32 = 0xe,
- FMT_RESERVED_4 = 0xf,
- FMT_5_6_5 = 0x10,
- FMT_1_5_5_5 = 0x11,
- FMT_5_5_5_1 = 0x12,
- FMT_4_4_4_4 = 0x13,
- FMT_8_24 = 0x14,
- FMT_24_8 = 0x15,
- FMT_X24_8_32_FLOAT = 0x16,
- FMT_RESERVED_33 = 0x17,
- FMT_11_11_10_FLOAT = 0x18,
- FMT_16_FLOAT = 0x19,
- FMT_32_FLOAT = 0x1a,
- FMT_16_16_FLOAT = 0x1b,
- FMT_8_24_FLOAT = 0x1c,
- FMT_24_8_FLOAT = 0x1d,
- FMT_32_32_FLOAT = 0x1e,
- FMT_10_11_11_FLOAT = 0x1f,
- FMT_16_16_16_16_FLOAT = 0x20,
- FMT_3_3_2 = 0x21,
- FMT_6_5_5 = 0x22,
- FMT_32_32_32_32_FLOAT = 0x23,
- FMT_RESERVED_36 = 0x24,
- FMT_1 = 0x25,
- FMT_1_REVERSED = 0x26,
- FMT_GB_GR = 0x27,
- FMT_BG_RG = 0x28,
- FMT_32_AS_8 = 0x29,
- FMT_32_AS_8_8 = 0x2a,
- FMT_5_9_9_9_SHAREDEXP = 0x2b,
- FMT_8_8_8 = 0x2c,
- FMT_16_16_16 = 0x2d,
- FMT_16_16_16_FLOAT = 0x2e,
- FMT_4_4 = 0x2f,
- FMT_32_32_32_FLOAT = 0x30,
- FMT_BC1 = 0x31,
- FMT_BC2 = 0x32,
- FMT_BC3 = 0x33,
- FMT_BC4 = 0x34,
- FMT_BC5 = 0x35,
- FMT_BC6 = 0x36,
- FMT_BC7 = 0x37,
- FMT_32_AS_32_32_32_32 = 0x38,
- FMT_APC3 = 0x39,
- FMT_APC4 = 0x3a,
- FMT_APC5 = 0x3b,
- FMT_APC6 = 0x3c,
- FMT_APC7 = 0x3d,
- FMT_CTX1 = 0x3e,
- FMT_RESERVED_63 = 0x3f,
-} SurfaceFormat;
-typedef enum BUF_DATA_FORMAT {
- BUF_DATA_FORMAT_INVALID = 0x0,
- BUF_DATA_FORMAT_8 = 0x1,
- BUF_DATA_FORMAT_16 = 0x2,
- BUF_DATA_FORMAT_8_8 = 0x3,
- BUF_DATA_FORMAT_32 = 0x4,
- BUF_DATA_FORMAT_16_16 = 0x5,
- BUF_DATA_FORMAT_10_11_11 = 0x6,
- BUF_DATA_FORMAT_11_11_10 = 0x7,
- BUF_DATA_FORMAT_10_10_10_2 = 0x8,
- BUF_DATA_FORMAT_2_10_10_10 = 0x9,
- BUF_DATA_FORMAT_8_8_8_8 = 0xa,
- BUF_DATA_FORMAT_32_32 = 0xb,
- BUF_DATA_FORMAT_16_16_16_16 = 0xc,
- BUF_DATA_FORMAT_32_32_32 = 0xd,
- BUF_DATA_FORMAT_32_32_32_32 = 0xe,
- BUF_DATA_FORMAT_RESERVED_15 = 0xf,
-} BUF_DATA_FORMAT;
-typedef enum IMG_DATA_FORMAT {
- IMG_DATA_FORMAT_INVALID = 0x0,
- IMG_DATA_FORMAT_8 = 0x1,
- IMG_DATA_FORMAT_16 = 0x2,
- IMG_DATA_FORMAT_8_8 = 0x3,
- IMG_DATA_FORMAT_32 = 0x4,
- IMG_DATA_FORMAT_16_16 = 0x5,
- IMG_DATA_FORMAT_10_11_11 = 0x6,
- IMG_DATA_FORMAT_11_11_10 = 0x7,
- IMG_DATA_FORMAT_10_10_10_2 = 0x8,
- IMG_DATA_FORMAT_2_10_10_10 = 0x9,
- IMG_DATA_FORMAT_8_8_8_8 = 0xa,
- IMG_DATA_FORMAT_32_32 = 0xb,
- IMG_DATA_FORMAT_16_16_16_16 = 0xc,
- IMG_DATA_FORMAT_32_32_32 = 0xd,
- IMG_DATA_FORMAT_32_32_32_32 = 0xe,
- IMG_DATA_FORMAT_RESERVED_15 = 0xf,
- IMG_DATA_FORMAT_5_6_5 = 0x10,
- IMG_DATA_FORMAT_1_5_5_5 = 0x11,
- IMG_DATA_FORMAT_5_5_5_1 = 0x12,
- IMG_DATA_FORMAT_4_4_4_4 = 0x13,
- IMG_DATA_FORMAT_8_24 = 0x14,
- IMG_DATA_FORMAT_24_8 = 0x15,
- IMG_DATA_FORMAT_X24_8_32 = 0x16,
- IMG_DATA_FORMAT_RESERVED_23 = 0x17,
- IMG_DATA_FORMAT_RESERVED_24 = 0x18,
- IMG_DATA_FORMAT_RESERVED_25 = 0x19,
- IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
- IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
- IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
- IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
- IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
- IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
- IMG_DATA_FORMAT_GB_GR = 0x20,
- IMG_DATA_FORMAT_BG_RG = 0x21,
- IMG_DATA_FORMAT_5_9_9_9 = 0x22,
- IMG_DATA_FORMAT_BC1 = 0x23,
- IMG_DATA_FORMAT_BC2 = 0x24,
- IMG_DATA_FORMAT_BC3 = 0x25,
- IMG_DATA_FORMAT_BC4 = 0x26,
- IMG_DATA_FORMAT_BC5 = 0x27,
- IMG_DATA_FORMAT_BC6 = 0x28,
- IMG_DATA_FORMAT_BC7 = 0x29,
- IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
- IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
- IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
- IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
- IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
- IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
- IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
- IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
- IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
- IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
- IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
- IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
- IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
- IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
- IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
- IMG_DATA_FORMAT_4_4 = 0x39,
- IMG_DATA_FORMAT_6_5_5 = 0x3a,
- IMG_DATA_FORMAT_1 = 0x3b,
- IMG_DATA_FORMAT_1_REVERSED = 0x3c,
- IMG_DATA_FORMAT_32_AS_8 = 0x3d,
- IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
- IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
-} IMG_DATA_FORMAT;
-typedef enum BUF_NUM_FORMAT {
- BUF_NUM_FORMAT_UNORM = 0x0,
- BUF_NUM_FORMAT_SNORM = 0x1,
- BUF_NUM_FORMAT_USCALED = 0x2,
- BUF_NUM_FORMAT_SSCALED = 0x3,
- BUF_NUM_FORMAT_UINT = 0x4,
- BUF_NUM_FORMAT_SINT = 0x5,
- BUF_NUM_FORMAT_SNORM_OGL = 0x6,
- BUF_NUM_FORMAT_FLOAT = 0x7,
-} BUF_NUM_FORMAT;
-typedef enum IMG_NUM_FORMAT {
- IMG_NUM_FORMAT_UNORM = 0x0,
- IMG_NUM_FORMAT_SNORM = 0x1,
- IMG_NUM_FORMAT_USCALED = 0x2,
- IMG_NUM_FORMAT_SSCALED = 0x3,
- IMG_NUM_FORMAT_UINT = 0x4,
- IMG_NUM_FORMAT_SINT = 0x5,
- IMG_NUM_FORMAT_SNORM_OGL = 0x6,
- IMG_NUM_FORMAT_FLOAT = 0x7,
- IMG_NUM_FORMAT_RESERVED_8 = 0x8,
- IMG_NUM_FORMAT_SRGB = 0x9,
- IMG_NUM_FORMAT_UBNORM = 0xa,
- IMG_NUM_FORMAT_UBNORM_OGL = 0xb,
- IMG_NUM_FORMAT_UBINT = 0xc,
- IMG_NUM_FORMAT_UBSCALED = 0xd,
- IMG_NUM_FORMAT_RESERVED_14 = 0xe,
- IMG_NUM_FORMAT_RESERVED_15 = 0xf,
-} IMG_NUM_FORMAT;
-typedef enum TileType {
- ARRAY_COLOR_TILE = 0x0,
- ARRAY_DEPTH_TILE = 0x1,
-} TileType;
-typedef enum NonDispTilingOrder {
- ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
- ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
-} NonDispTilingOrder;
-typedef enum MicroTileMode {
- ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
- ADDR_SURF_THIN_MICRO_TILING = 0x1,
- ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
- ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
- ADDR_SURF_THICK_MICRO_TILING = 0x4,
-} MicroTileMode;
-typedef enum TileSplit {
- ADDR_SURF_TILE_SPLIT_64B = 0x0,
- ADDR_SURF_TILE_SPLIT_128B = 0x1,
- ADDR_SURF_TILE_SPLIT_256B = 0x2,
- ADDR_SURF_TILE_SPLIT_512B = 0x3,
- ADDR_SURF_TILE_SPLIT_1KB = 0x4,
- ADDR_SURF_TILE_SPLIT_2KB = 0x5,
- ADDR_SURF_TILE_SPLIT_4KB = 0x6,
-} TileSplit;
-typedef enum SampleSplit {
- ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
- ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
- ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
- ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
-} SampleSplit;
-typedef enum PipeConfig {
- ADDR_SURF_P2 = 0x0,
- ADDR_SURF_P2_RESERVED0 = 0x1,
- ADDR_SURF_P2_RESERVED1 = 0x2,
- ADDR_SURF_P2_RESERVED2 = 0x3,
- ADDR_SURF_P4_8x16 = 0x4,
- ADDR_SURF_P4_16x16 = 0x5,
- ADDR_SURF_P4_16x32 = 0x6,
- ADDR_SURF_P4_32x32 = 0x7,
- ADDR_SURF_P8_16x16_8x16 = 0x8,
- ADDR_SURF_P8_16x32_8x16 = 0x9,
- ADDR_SURF_P8_32x32_8x16 = 0xa,
- ADDR_SURF_P8_16x32_16x16 = 0xb,
- ADDR_SURF_P8_32x32_16x16 = 0xc,
- ADDR_SURF_P8_32x32_16x32 = 0xd,
- ADDR_SURF_P8_32x64_32x32 = 0xe,
-} PipeConfig;
-typedef enum NumBanks {
- ADDR_SURF_2_BANK = 0x0,
- ADDR_SURF_4_BANK = 0x1,
- ADDR_SURF_8_BANK = 0x2,
- ADDR_SURF_16_BANK = 0x3,
-} NumBanks;
-typedef enum BankWidth {
- ADDR_SURF_BANK_WIDTH_1 = 0x0,
- ADDR_SURF_BANK_WIDTH_2 = 0x1,
- ADDR_SURF_BANK_WIDTH_4 = 0x2,
- ADDR_SURF_BANK_WIDTH_8 = 0x3,
-} BankWidth;
-typedef enum BankHeight {
- ADDR_SURF_BANK_HEIGHT_1 = 0x0,
- ADDR_SURF_BANK_HEIGHT_2 = 0x1,
- ADDR_SURF_BANK_HEIGHT_4 = 0x2,
- ADDR_SURF_BANK_HEIGHT_8 = 0x3,
-} BankHeight;
-typedef enum BankWidthHeight {
- ADDR_SURF_BANK_WH_1 = 0x0,
- ADDR_SURF_BANK_WH_2 = 0x1,
- ADDR_SURF_BANK_WH_4 = 0x2,
- ADDR_SURF_BANK_WH_8 = 0x3,
-} BankWidthHeight;
-typedef enum MacroTileAspect {
- ADDR_SURF_MACRO_ASPECT_1 = 0x0,
- ADDR_SURF_MACRO_ASPECT_2 = 0x1,
- ADDR_SURF_MACRO_ASPECT_4 = 0x2,
- ADDR_SURF_MACRO_ASPECT_8 = 0x3,
-} MacroTileAspect;
-typedef enum TCC_CACHE_POLICIES {
- TCC_CACHE_POLICY_LRU = 0x0,
- TCC_CACHE_POLICY_STREAM = 0x1,
- TCC_CACHE_POLICY_BYPASS = 0x2,
-} TCC_CACHE_POLICIES;
-typedef enum PERFMON_COUNTER_MODE {
- PERFMON_COUNTER_MODE_ACCUM = 0x0,
- PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
- PERFMON_COUNTER_MODE_MAX = 0x2,
- PERFMON_COUNTER_MODE_DIRTY = 0x3,
- PERFMON_COUNTER_MODE_SAMPLE = 0x4,
- PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
- PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
- PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
- PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
- PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
- PERFMON_COUNTER_MODE_RESERVED = 0xf,
-} PERFMON_COUNTER_MODE;
-typedef enum PERFMON_SPM_MODE {
- PERFMON_SPM_MODE_OFF = 0x0,
- PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
- PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
- PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
- PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
- PERFMON_SPM_MODE_RESERVED_5 = 0x5,
- PERFMON_SPM_MODE_RESERVED_6 = 0x6,
- PERFMON_SPM_MODE_RESERVED_7 = 0x7,
- PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
- PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
- PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
-} PERFMON_SPM_MODE;
-typedef enum SurfaceTiling {
- ARRAY_LINEAR = 0x0,
- ARRAY_TILED = 0x1,
-} SurfaceTiling;
-typedef enum SurfaceArray {
- ARRAY_1D = 0x0,
- ARRAY_2D = 0x1,
- ARRAY_3D = 0x2,
- ARRAY_3D_SLICE = 0x3,
-} SurfaceArray;
-typedef enum ColorArray {
- ARRAY_2D_ALT_COLOR = 0x0,
- ARRAY_2D_COLOR = 0x1,
- ARRAY_3D_SLICE_COLOR = 0x3,
-} ColorArray;
-typedef enum DepthArray {
- ARRAY_2D_ALT_DEPTH = 0x0,
- ARRAY_2D_DEPTH = 0x1,
-} DepthArray;
-
-#endif /* DCE_8_0_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_1_offset.h
deleted file mode 100755
index f10e6168a..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_1_offset.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * Copyright 2025 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef _gc_12_1_1_OFFSET_HEADER
-#define _gc_12_1_1_OFFSET_HEADER
-
-
-
-// addressBlock: aigc_grbma_grbma_grbmadec
-// base address: 0x18000
-#define regGRBMA_GFX_INDEX 0x0011
-#define regGRBMA_GFX_INDEX_BASE_IDX 1
-
-
-// addressBlock: aigc_grbma_grbma_perfddec
-// base address: 0x19200
-#define regGRBMA_PERFCOUNTER0_LO 0x0480
-#define regGRBMA_PERFCOUNTER0_LO_BASE_IDX 1
-#define regGRBMA_PERFCOUNTER0_HI 0x0481
-#define regGRBMA_PERFCOUNTER0_HI_BASE_IDX 1
-#define regGRBMA_PERFCOUNTER1_LO 0x0482
-#define regGRBMA_PERFCOUNTER1_LO_BASE_IDX 1
-#define regGRBMA_PERFCOUNTER1_HI 0x0483
-#define regGRBMA_PERFCOUNTER1_HI_BASE_IDX 1
-
-
-// addressBlock: aigc_grbma_grbma_perfsdec
-// base address: 0x19300
-#define regGRBMA_PERFCOUNTER0_SELECT 0x04c0
-#define regGRBMA_PERFCOUNTER0_SELECT_BASE_IDX 1
-#define regGRBMA_PERFCOUNTER1_SELECT 0x04c1
-#define regGRBMA_PERFCOUNTER1_SELECT_BASE_IDX 1
-#define regAID_PERFMON_CNTL 0x04c2
-#define regAID_PERFMON_CNTL_BASE_IDX 1
-
-
-// addressBlock: aigc_gl2x_gfx_se_perfsdec
-// base address: 0x19300
-#define regGL2C_PERFCOUNTER0_SELECT 0x04e8
-#define regGL2C_PERFCOUNTER0_SELECT_BASE_IDX 1
-#define regGL2C_PERFCOUNTER0_SELECT1 0x04e9
-#define regGL2C_PERFCOUNTER0_SELECT1_BASE_IDX 1
-#define regGL2C_PERFCOUNTER1_SELECT 0x04ea
-#define regGL2C_PERFCOUNTER1_SELECT_BASE_IDX 1
-#define regGL2C_PERFCOUNTER1_SELECT1 0x04eb
-#define regGL2C_PERFCOUNTER1_SELECT1_BASE_IDX 1
-#define regGL2C_PERFCOUNTER2_SELECT 0x04ec
-#define regGL2C_PERFCOUNTER2_SELECT_BASE_IDX 1
-#define regGL2C_PERFCOUNTER2_SELECT1 0x04ed
-#define regGL2C_PERFCOUNTER2_SELECT1_BASE_IDX 1
-#define regGL2C_PERFCOUNTER3_SELECT 0x04ee
-#define regGL2C_PERFCOUNTER3_SELECT_BASE_IDX 1
-#define regGL2C_PERFCOUNTER3_SELECT1 0x04ef
-#define regGL2C_PERFCOUNTER3_SELECT1_BASE_IDX 1
-#define regGL2A_PERFCOUNTER0_SELECT 0x04f0
-#define regGL2A_PERFCOUNTER0_SELECT_BASE_IDX 1
-#define regGL2A_PERFCOUNTER0_SELECT1 0x04f1
-#define regGL2A_PERFCOUNTER0_SELECT1_BASE_IDX 1
-#define regGL2A_PERFCOUNTER1_SELECT 0x04f2
-#define regGL2A_PERFCOUNTER1_SELECT_BASE_IDX 1
-#define regGL2A_PERFCOUNTER1_SELECT1 0x04f3
-#define regGL2A_PERFCOUNTER1_SELECT1_BASE_IDX 1
-#define regGL2A_PERFCOUNTER2_SELECT 0x04f4
-#define regGL2A_PERFCOUNTER2_SELECT_BASE_IDX 1
-#define regGL2A_PERFCOUNTER2_SELECT1 0x04f5
-#define regGL2A_PERFCOUNTER2_SELECT1_BASE_IDX 1
-#define regGL2A_PERFCOUNTER3_SELECT 0x04f6
-#define regGL2A_PERFCOUNTER3_SELECT_BASE_IDX 1
-#define regGL2A_PERFCOUNTER3_SELECT1 0x04f7
-#define regGL2A_PERFCOUNTER3_SELECT1_BASE_IDX 1
-
-
-// addressBlock: aigc_gl2x_gfx_se_perfddec
-// base address: 0x19200
-#define regGL2C_PERFCOUNTER0_LO 0x04a0
-#define regGL2C_PERFCOUNTER0_LO_BASE_IDX 1
-#define regGL2C_PERFCOUNTER0_HI 0x04a1
-#define regGL2C_PERFCOUNTER0_HI_BASE_IDX 1
-#define regGL2C_PERFCOUNTER1_LO 0x04a2
-#define regGL2C_PERFCOUNTER1_LO_BASE_IDX 1
-#define regGL2C_PERFCOUNTER1_HI 0x04a3
-#define regGL2C_PERFCOUNTER1_HI_BASE_IDX 1
-#define regGL2C_PERFCOUNTER2_LO 0x04a4
-#define regGL2C_PERFCOUNTER2_LO_BASE_IDX 1
-#define regGL2C_PERFCOUNTER2_HI 0x04a5
-#define regGL2C_PERFCOUNTER2_HI_BASE_IDX 1
-#define regGL2C_PERFCOUNTER3_LO 0x04a6
-#define regGL2C_PERFCOUNTER3_LO_BASE_IDX 1
-#define regGL2C_PERFCOUNTER3_HI 0x04a7
-#define regGL2C_PERFCOUNTER3_HI_BASE_IDX 1
-#define regGL2A_PERFCOUNTER0_LO 0x04a8
-#define regGL2A_PERFCOUNTER0_LO_BASE_IDX 1
-#define regGL2A_PERFCOUNTER0_HI 0x04a9
-#define regGL2A_PERFCOUNTER0_HI_BASE_IDX 1
-#define regGL2A_PERFCOUNTER1_LO 0x04aa
-#define regGL2A_PERFCOUNTER1_LO_BASE_IDX 1
-#define regGL2A_PERFCOUNTER1_HI 0x04ab
-#define regGL2A_PERFCOUNTER1_HI_BASE_IDX 1
-#define regGL2A_PERFCOUNTER2_LO 0x04ac
-#define regGL2A_PERFCOUNTER2_LO_BASE_IDX 1
-#define regGL2A_PERFCOUNTER2_HI 0x04ad
-#define regGL2A_PERFCOUNTER2_HI_BASE_IDX 1
-#define regGL2A_PERFCOUNTER3_LO 0x04ae
-#define regGL2A_PERFCOUNTER3_LO_BASE_IDX 1
-#define regGL2A_PERFCOUNTER3_HI 0x04af
-#define regGL2A_PERFCOUNTER3_HI_BASE_IDX 1
-
-
-// addressBlock: aigc_gfx_gcea_se_gfx_se_perfsdec
-// base address: 0x19320
-#define regGC_EA_SE_PERFCOUNTER0_SELECT 0x04c8
-#define regGC_EA_SE_PERFCOUNTER0_SELECT_BASE_IDX 1
-#define regGC_EA_SE_PERFCOUNTER0_SELECT1 0x04c9
-#define regGC_EA_SE_PERFCOUNTER0_SELECT1_BASE_IDX 1
-#define regGC_EA_SE_PERFCOUNTER1_SELECT 0x04ca
-#define regGC_EA_SE_PERFCOUNTER1_SELECT_BASE_IDX 1
-
-
-// addressBlock: aigc_gfx_gcea_se_gfx_se_perfddec
-// base address: 0x19240
-#define regGC_EA_SE_PERFCOUNTER0_LO 0x0490
-#define regGC_EA_SE_PERFCOUNTER0_LO_BASE_IDX 1
-#define regGC_EA_SE_PERFCOUNTER0_HI 0x0491
-#define regGC_EA_SE_PERFCOUNTER0_HI_BASE_IDX 1
-#define regGC_EA_SE_PERFCOUNTER1_LO 0x0492
-#define regGC_EA_SE_PERFCOUNTER1_LO_BASE_IDX 1
-#define regGC_EA_SE_PERFCOUNTER1_HI 0x0493
-#define regGC_EA_SE_PERFCOUNTER1_HI_BASE_IDX 1
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_1_sh_mask.h
deleted file mode 100755
index 8d09c8150..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_1_sh_mask.h
+++ /dev/null
@@ -1,377 +0,0 @@
-/*
- * Copyright 2025 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef _gc_12_1_1_SH_MASK_HEADER
-#define _gc_12_1_1_SH_MASK_HEADER
-
-
-// addressBlock: aigc_grbma_grbma_grbmadec
-//GRBMA_GFX_INDEX
-#define GRBMA_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0
-#define GRBMA_GFX_INDEX__SA_INDEX__SHIFT 0x8
-#define GRBMA_GFX_INDEX__SE_INDEX__SHIFT 0x10
-#define GRBMA_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT 0x1d
-#define GRBMA_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e
-#define GRBMA_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f
-#define GRBMA_GFX_INDEX__INSTANCE_INDEX_MASK 0x0000007FL
-#define GRBMA_GFX_INDEX__SA_INDEX_MASK 0x00000300L
-#define GRBMA_GFX_INDEX__SE_INDEX_MASK 0x000F0000L
-#define GRBMA_GFX_INDEX__SA_BROADCAST_WRITES_MASK 0x20000000L
-#define GRBMA_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L
-#define GRBMA_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000L
-
-
-// addressBlock: aigc_grbma_grbma_perfddec
-//GRBMA_PERFCOUNTER0_LO
-#define GRBMA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define GRBMA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//GRBMA_PERFCOUNTER0_HI
-#define GRBMA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define GRBMA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//GRBMA_PERFCOUNTER1_LO
-#define GRBMA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define GRBMA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//GRBMA_PERFCOUNTER1_HI
-#define GRBMA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define GRBMA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-
-
-// addressBlock: aigc_grbma_grbma_perfsdec
-//GRBMA_PERFCOUNTER0_SELECT
-#define GRBMA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define GRBMA_PERFCOUNTER0_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x6
-#define GRBMA_PERFCOUNTER0_SELECT__GL1XCC_BUSY_USER_DEFINED_MASK__SHIFT 0x7
-#define GRBMA_PERFCOUNTER0_SELECT__PMR_BUSY_USER_DEFINED_MASK__SHIFT 0x8
-#define GRBMA_PERFCOUNTER0_SELECT__SC_CLEAN_USER_DEFINED_MASK__SHIFT 0x9
-#define GRBMA_PERFCOUNTER0_SELECT__WGS_BUSY_USER_DEFINED_MASK__SHIFT 0xa
-#define GRBMA_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
-#define GRBMA_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xc
-#define GRBMA_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
-#define GRBMA_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
-#define GRBMA_PERFCOUNTER0_SELECT__GL2C_BUSY_USER_DEFINED_MASK__SHIFT 0xf
-#define GRBMA_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
-#define GRBMA_PERFCOUNTER0_SELECT__XCAC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
-#define GRBMA_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
-#define GRBMA_PERFCOUNTER0_SELECT__GL2A_BUSY_USER_DEFINED_MASK__SHIFT 0x13
-#define GRBMA_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
-#define GRBMA_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
-#define GRBMA_PERFCOUNTER0_SELECT__EA_LINK_BUSY_USER_DEFINED_MASK__SHIFT 0x17
-#define GRBMA_PERFCOUNTER0_SELECT__AIGC_CAC_BUSY_USER_DEFINED_MASK__SHIFT 0x18
-#define GRBMA_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
-#define GRBMA_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
-#define GRBMA_PERFCOUNTER0_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
-#define GRBMA_PERFCOUNTER0_SELECT__GE_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
-#define GRBMA_PERFCOUNTER0_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x1d
-#define GRBMA_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e
-#define GRBMA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003FL
-#define GRBMA_PERFCOUNTER0_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x00000040L
-#define GRBMA_PERFCOUNTER0_SELECT__GL1XCC_BUSY_USER_DEFINED_MASK_MASK 0x00000080L
-#define GRBMA_PERFCOUNTER0_SELECT__PMR_BUSY_USER_DEFINED_MASK_MASK 0x00000100L
-#define GRBMA_PERFCOUNTER0_SELECT__SC_CLEAN_USER_DEFINED_MASK_MASK 0x00000200L
-#define GRBMA_PERFCOUNTER0_SELECT__WGS_BUSY_USER_DEFINED_MASK_MASK 0x00000400L
-#define GRBMA_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
-#define GRBMA_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00001000L
-#define GRBMA_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
-#define GRBMA_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L
-#define GRBMA_PERFCOUNTER0_SELECT__GL2C_BUSY_USER_DEFINED_MASK_MASK 0x00008000L
-#define GRBMA_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
-#define GRBMA_PERFCOUNTER0_SELECT__XCAC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
-#define GRBMA_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
-#define GRBMA_PERFCOUNTER0_SELECT__GL2A_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
-#define GRBMA_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
-#define GRBMA_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
-#define GRBMA_PERFCOUNTER0_SELECT__EA_LINK_BUSY_USER_DEFINED_MASK_MASK 0x00800000L
-#define GRBMA_PERFCOUNTER0_SELECT__AIGC_CAC_BUSY_USER_DEFINED_MASK_MASK 0x01000000L
-#define GRBMA_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L
-#define GRBMA_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L
-#define GRBMA_PERFCOUNTER0_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x08000000L
-#define GRBMA_PERFCOUNTER0_SELECT__GE_BUSY_USER_DEFINED_MASK_MASK 0x10000000L
-#define GRBMA_PERFCOUNTER0_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x20000000L
-#define GRBMA_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L
-//GRBMA_PERFCOUNTER1_SELECT
-#define GRBMA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define GRBMA_PERFCOUNTER1_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x6
-#define GRBMA_PERFCOUNTER1_SELECT__GL1XCC_BUSY_USER_DEFINED_MASK__SHIFT 0x7
-#define GRBMA_PERFCOUNTER1_SELECT__PMR_BUSY_USER_DEFINED_MASK__SHIFT 0x8
-#define GRBMA_PERFCOUNTER1_SELECT__SC_CLEAN_USER_DEFINED_MASK__SHIFT 0x9
-#define GRBMA_PERFCOUNTER1_SELECT__WGS_BUSY_USER_DEFINED_MASK__SHIFT 0xa
-#define GRBMA_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
-#define GRBMA_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xc
-#define GRBMA_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
-#define GRBMA_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
-#define GRBMA_PERFCOUNTER1_SELECT__GL2C_BUSY_USER_DEFINED_MASK__SHIFT 0xf
-#define GRBMA_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
-#define GRBMA_PERFCOUNTER1_SELECT__XCAC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
-#define GRBMA_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
-#define GRBMA_PERFCOUNTER1_SELECT__GL2A_BUSY_USER_DEFINED_MASK__SHIFT 0x13
-#define GRBMA_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
-#define GRBMA_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
-#define GRBMA_PERFCOUNTER1_SELECT__EA_LINK_BUSY_USER_DEFINED_MASK__SHIFT 0x17
-#define GRBMA_PERFCOUNTER1_SELECT__AIGC_CAC_BUSY_USER_DEFINED_MASK__SHIFT 0x18
-#define GRBMA_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
-#define GRBMA_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
-#define GRBMA_PERFCOUNTER1_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
-#define GRBMA_PERFCOUNTER1_SELECT__GE_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
-#define GRBMA_PERFCOUNTER1_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x1d
-#define GRBMA_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e
-#define GRBMA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003FL
-#define GRBMA_PERFCOUNTER1_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x00000040L
-#define GRBMA_PERFCOUNTER1_SELECT__GL1XCC_BUSY_USER_DEFINED_MASK_MASK 0x00000080L
-#define GRBMA_PERFCOUNTER1_SELECT__PMR_BUSY_USER_DEFINED_MASK_MASK 0x00000100L
-#define GRBMA_PERFCOUNTER1_SELECT__SC_CLEAN_USER_DEFINED_MASK_MASK 0x00000200L
-#define GRBMA_PERFCOUNTER1_SELECT__WGS_BUSY_USER_DEFINED_MASK_MASK 0x00000400L
-#define GRBMA_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
-#define GRBMA_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00001000L
-#define GRBMA_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
-#define GRBMA_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L
-#define GRBMA_PERFCOUNTER1_SELECT__GL2C_BUSY_USER_DEFINED_MASK_MASK 0x00008000L
-#define GRBMA_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
-#define GRBMA_PERFCOUNTER1_SELECT__XCAC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
-#define GRBMA_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
-#define GRBMA_PERFCOUNTER1_SELECT__GL2A_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
-#define GRBMA_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
-#define GRBMA_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
-#define GRBMA_PERFCOUNTER1_SELECT__EA_LINK_BUSY_USER_DEFINED_MASK_MASK 0x00800000L
-#define GRBMA_PERFCOUNTER1_SELECT__AIGC_CAC_BUSY_USER_DEFINED_MASK_MASK 0x01000000L
-#define GRBMA_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L
-#define GRBMA_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L
-#define GRBMA_PERFCOUNTER1_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x08000000L
-#define GRBMA_PERFCOUNTER1_SELECT__GE_BUSY_USER_DEFINED_MASK_MASK 0x10000000L
-#define GRBMA_PERFCOUNTER1_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x20000000L
-#define GRBMA_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L
-//AID_PERFMON_CNTL
-#define AID_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
-#define AID_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4
-#define AID_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8
-#define AID_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
-#define AID_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000FL
-#define AID_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0x000000F0L
-#define AID_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L
-#define AID_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L
-
-
-// addressBlock: aigc_gl2x_gfx_se_perfsdec
-//GL2C_PERFCOUNTER0_SELECT
-#define GL2C_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define GL2C_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define GL2C_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define GL2C_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
-#define GL2C_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define GL2C_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
-#define GL2C_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define GL2C_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define GL2C_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define GL2C_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
-//GL2C_PERFCOUNTER0_SELECT1
-#define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
-#define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//GL2C_PERFCOUNTER1_SELECT
-#define GL2C_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define GL2C_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
-#define GL2C_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
-#define GL2C_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
-#define GL2C_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define GL2C_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
-#define GL2C_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define GL2C_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define GL2C_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define GL2C_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
-//GL2C_PERFCOUNTER1_SELECT1
-#define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
-#define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
-#define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
-#define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//GL2C_PERFCOUNTER2_SELECT
-#define GL2C_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define GL2C_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
-#define GL2C_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
-#define GL2C_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
-#define GL2C_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
-#define GL2C_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
-#define GL2C_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define GL2C_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define GL2C_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define GL2C_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
-//GL2C_PERFCOUNTER2_SELECT1
-#define GL2C_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0
-#define GL2C_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
-#define GL2C_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18
-#define GL2C_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define GL2C_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define GL2C_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define GL2C_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define GL2C_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//GL2C_PERFCOUNTER3_SELECT
-#define GL2C_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define GL2C_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
-#define GL2C_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
-#define GL2C_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18
-#define GL2C_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
-#define GL2C_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
-#define GL2C_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define GL2C_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define GL2C_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define GL2C_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
-//GL2C_PERFCOUNTER3_SELECT1
-#define GL2C_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0
-#define GL2C_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa
-#define GL2C_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18
-#define GL2C_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define GL2C_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define GL2C_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define GL2C_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define GL2C_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//GL2A_PERFCOUNTER0_SELECT
-#define GL2A_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define GL2A_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define GL2A_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define GL2A_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
-#define GL2A_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define GL2A_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
-#define GL2A_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define GL2A_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define GL2A_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define GL2A_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
-//GL2A_PERFCOUNTER0_SELECT1
-#define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
-#define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//GL2A_PERFCOUNTER1_SELECT
-#define GL2A_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define GL2A_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
-#define GL2A_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
-#define GL2A_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
-#define GL2A_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define GL2A_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
-#define GL2A_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define GL2A_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define GL2A_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define GL2A_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
-//GL2A_PERFCOUNTER1_SELECT1
-#define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
-#define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
-#define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
-#define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//GL2A_PERFCOUNTER2_SELECT
-#define GL2A_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define GL2A_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
-#define GL2A_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
-#define GL2A_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
-#define GL2A_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
-#define GL2A_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
-#define GL2A_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define GL2A_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define GL2A_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define GL2A_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
-//GL2A_PERFCOUNTER2_SELECT1
-#define GL2A_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0
-#define GL2A_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
-#define GL2A_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18
-#define GL2A_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define GL2A_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define GL2A_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define GL2A_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define GL2A_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//GL2A_PERFCOUNTER3_SELECT
-#define GL2A_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define GL2A_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
-#define GL2A_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
-#define GL2A_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18
-#define GL2A_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
-#define GL2A_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
-#define GL2A_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define GL2A_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define GL2A_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define GL2A_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
-//GL2A_PERFCOUNTER3_SELECT1
-#define GL2A_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0
-#define GL2A_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa
-#define GL2A_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18
-#define GL2A_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define GL2A_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define GL2A_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define GL2A_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define GL2A_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L
-
-
-// addressBlock: aigc_gfx_gcea_se_gfx_se_perfsdec
-//GC_EA_SE_PERFCOUNTER0_SELECT
-#define GC_EA_SE_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define GC_EA_SE_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define GC_EA_SE_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define GC_EA_SE_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
-#define GC_EA_SE_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define GC_EA_SE_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
-#define GC_EA_SE_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define GC_EA_SE_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define GC_EA_SE_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define GC_EA_SE_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
-//GC_EA_SE_PERFCOUNTER0_SELECT1
-#define GC_EA_SE_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define GC_EA_SE_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define GC_EA_SE_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
-#define GC_EA_SE_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define GC_EA_SE_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define GC_EA_SE_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define GC_EA_SE_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define GC_EA_SE_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//GC_EA_SE_PERFCOUNTER1_SELECT
-#define GC_EA_SE_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define GC_EA_SE_PERFCOUNTER1_SELECT__COUNTER_MODE__SHIFT 0x1c
-#define GC_EA_SE_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
-#define GC_EA_SE_PERFCOUNTER1_SELECT__COUNTER_MODE_MASK 0xF0000000L
-
-
-// addressBlock: aigc_gfx_gcea_se_gfx_se_perfddec
-//GC_EA_SE_PERFCOUNTER0_LO
-#define GC_EA_SE_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define GC_EA_SE_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//GC_EA_SE_PERFCOUNTER0_HI
-#define GC_EA_SE_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define GC_EA_SE_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//GC_EA_SE_PERFCOUNTER1_LO
-#define GC_EA_SE_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define GC_EA_SE_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//GC_EA_SE_PERFCOUNTER1_HI
-#define GC_EA_SE_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define GC_EA_SE_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h
deleted file mode 100644
index b84bd0fa3..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h
+++ /dev/null
@@ -1,31176 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _gc_9_1_SH_MASK_HEADER
-#define _gc_9_1_SH_MASK_HEADER
-
-
-// addressBlock: gc_grbmdec
-//GRBM_CNTL
-#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0
-#define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f
-#define GRBM_CNTL__READ_TIMEOUT_MASK 0x000000FFL
-#define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000L
-//GRBM_SKEW_CNTL
-#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0
-#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6
-#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000003FL
-#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0x00000FC0L
-//GRBM_STATUS2
-#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0
-#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4
-#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5
-#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6
-#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7
-#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8
-#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9
-#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa
-#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb
-#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc
-#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd
-#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe
-#define GRBM_STATUS2__UTCL2_BUSY__SHIFT 0xf
-#define GRBM_STATUS2__EA_BUSY__SHIFT 0x10
-#define GRBM_STATUS2__RMI_BUSY__SHIFT 0x11
-#define GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT 0x12
-#define GRBM_STATUS2__CPF_RQ_PENDING__SHIFT 0x13
-#define GRBM_STATUS2__EA_LINK_BUSY__SHIFT 0x14
-#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18
-#define GRBM_STATUS2__TC_BUSY__SHIFT 0x19
-#define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT 0x1a
-#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c
-#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d
-#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e
-#define GRBM_STATUS2__CPAXI_BUSY__SHIFT 0x1f
-#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000FL
-#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x00000010L
-#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x00000020L
-#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x00000040L
-#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x00000080L
-#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x00000100L
-#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x00000200L
-#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x00000400L
-#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x00000800L
-#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x00001000L
-#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x00002000L
-#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x00004000L
-#define GRBM_STATUS2__UTCL2_BUSY_MASK 0x00008000L
-#define GRBM_STATUS2__EA_BUSY_MASK 0x00010000L
-#define GRBM_STATUS2__RMI_BUSY_MASK 0x00020000L
-#define GRBM_STATUS2__UTCL2_RQ_PENDING_MASK 0x00040000L
-#define GRBM_STATUS2__CPF_RQ_PENDING_MASK 0x00080000L
-#define GRBM_STATUS2__EA_LINK_BUSY_MASK 0x00100000L
-#define GRBM_STATUS2__RLC_BUSY_MASK 0x01000000L
-#define GRBM_STATUS2__TC_BUSY_MASK 0x02000000L
-#define GRBM_STATUS2__TCC_CC_RESIDENT_MASK 0x04000000L
-#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000L
-#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000L
-#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000L
-#define GRBM_STATUS2__CPAXI_BUSY_MASK 0x80000000L
-//GRBM_PWR_CNTL
-#define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0
-#define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2
-#define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4
-#define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6
-#define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe
-#define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf
-#define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x00000003L
-#define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0x0000000CL
-#define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x00000030L
-#define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0x000000C0L
-#define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x00004000L
-#define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x00008000L
-//GRBM_STATUS
-#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0
-#define GRBM_STATUS__RSMU_RQ_PENDING__SHIFT 0x5
-#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7
-#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8
-#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9
-#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc
-#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd
-#define GRBM_STATUS__TA_BUSY__SHIFT 0xe
-#define GRBM_STATUS__GDS_BUSY__SHIFT 0xf
-#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10
-#define GRBM_STATUS__VGT_BUSY__SHIFT 0x11
-#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12
-#define GRBM_STATUS__IA_BUSY__SHIFT 0x13
-#define GRBM_STATUS__SX_BUSY__SHIFT 0x14
-#define GRBM_STATUS__WD_BUSY__SHIFT 0x15
-#define GRBM_STATUS__SPI_BUSY__SHIFT 0x16
-#define GRBM_STATUS__BCI_BUSY__SHIFT 0x17
-#define GRBM_STATUS__SC_BUSY__SHIFT 0x18
-#define GRBM_STATUS__PA_BUSY__SHIFT 0x19
-#define GRBM_STATUS__DB_BUSY__SHIFT 0x1a
-#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c
-#define GRBM_STATUS__CP_BUSY__SHIFT 0x1d
-#define GRBM_STATUS__CB_BUSY__SHIFT 0x1e
-#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f
-#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000FL
-#define GRBM_STATUS__RSMU_RQ_PENDING_MASK 0x00000020L
-#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x00000080L
-#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x00000100L
-#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x00000200L
-#define GRBM_STATUS__DB_CLEAN_MASK 0x00001000L
-#define GRBM_STATUS__CB_CLEAN_MASK 0x00002000L
-#define GRBM_STATUS__TA_BUSY_MASK 0x00004000L
-#define GRBM_STATUS__GDS_BUSY_MASK 0x00008000L
-#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x00010000L
-#define GRBM_STATUS__VGT_BUSY_MASK 0x00020000L
-#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x00040000L
-#define GRBM_STATUS__IA_BUSY_MASK 0x00080000L
-#define GRBM_STATUS__SX_BUSY_MASK 0x00100000L
-#define GRBM_STATUS__WD_BUSY_MASK 0x00200000L
-#define GRBM_STATUS__SPI_BUSY_MASK 0x00400000L
-#define GRBM_STATUS__BCI_BUSY_MASK 0x00800000L
-#define GRBM_STATUS__SC_BUSY_MASK 0x01000000L
-#define GRBM_STATUS__PA_BUSY_MASK 0x02000000L
-#define GRBM_STATUS__DB_BUSY_MASK 0x04000000L
-#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000L
-#define GRBM_STATUS__CP_BUSY_MASK 0x20000000L
-#define GRBM_STATUS__CB_BUSY_MASK 0x40000000L
-#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000L
-//GRBM_STATUS_SE0
-#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1
-#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2
-#define GRBM_STATUS_SE0__RMI_BUSY__SHIFT 0x15
-#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16
-#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17
-#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18
-#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19
-#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a
-#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b
-#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d
-#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e
-#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f
-#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x00000002L
-#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x00000004L
-#define GRBM_STATUS_SE0__RMI_BUSY_MASK 0x00200000L
-#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x00400000L
-#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x00800000L
-#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x01000000L
-#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x02000000L
-#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x04000000L
-#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x08000000L
-#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000L
-#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000L
-#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000L
-//GRBM_STATUS_SE1
-#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1
-#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2
-#define GRBM_STATUS_SE1__RMI_BUSY__SHIFT 0x15
-#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16
-#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17
-#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18
-#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19
-#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a
-#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b
-#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d
-#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e
-#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f
-#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x00000002L
-#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x00000004L
-#define GRBM_STATUS_SE1__RMI_BUSY_MASK 0x00200000L
-#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x00400000L
-#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x00800000L
-#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x01000000L
-#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x02000000L
-#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x04000000L
-#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x08000000L
-#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000L
-#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000L
-#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000L
-//GRBM_SOFT_RESET
-#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0
-#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2
-#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10
-#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11
-#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12
-#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13
-#define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14
-#define GRBM_SOFT_RESET__SOFT_RESET_CPAXI__SHIFT 0x15
-#define GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT 0x16
-#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L
-#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x00000004L
-#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x00010000L
-#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x00020000L
-#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x00040000L
-#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x00080000L
-#define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x00100000L
-#define GRBM_SOFT_RESET__SOFT_RESET_CPAXI_MASK 0x00200000L
-#define GRBM_SOFT_RESET__SOFT_RESET_EA_MASK 0x00400000L
-//GRBM_CGTT_CLK_CNTL
-#define GRBM_CGTT_CLK_CNTL__ON_DELAY__SHIFT 0x0
-#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS__SHIFT 0x4
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
-#define GRBM_CGTT_CLK_CNTL__ON_DELAY_MASK 0x0000000FL
-#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
-//GRBM_GFX_CLKEN_CNTL
-#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
-#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
-#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000FL
-#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001F00L
-//GRBM_WAIT_IDLE_CLOCKS
-#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0
-#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0x000000FFL
-//GRBM_STATUS_SE2
-#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1
-#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2
-#define GRBM_STATUS_SE2__RMI_BUSY__SHIFT 0x15
-#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16
-#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17
-#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18
-#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19
-#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a
-#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b
-#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d
-#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e
-#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f
-#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x00000002L
-#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x00000004L
-#define GRBM_STATUS_SE2__RMI_BUSY_MASK 0x00200000L
-#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x00400000L
-#define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x00800000L
-#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x01000000L
-#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x02000000L
-#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x04000000L
-#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x08000000L
-#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000L
-#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000L
-#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000L
-//GRBM_STATUS_SE3
-#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1
-#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2
-#define GRBM_STATUS_SE3__RMI_BUSY__SHIFT 0x15
-#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16
-#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17
-#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18
-#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19
-#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a
-#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b
-#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d
-#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e
-#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f
-#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x00000002L
-#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x00000004L
-#define GRBM_STATUS_SE3__RMI_BUSY_MASK 0x00200000L
-#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x00400000L
-#define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x00800000L
-#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x01000000L
-#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x02000000L
-#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x04000000L
-#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x08000000L
-#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000L
-#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000L
-#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000L
-//GRBM_READ_ERROR
-#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2
-#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14
-#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16
-#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f
-#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x0003FFFCL
-#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x00300000L
-#define GRBM_READ_ERROR__READ_MEID_MASK 0x00C00000L
-#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L
-//GRBM_READ_ERROR2
-#define GRBM_READ_ERROR2__READ_REQUESTER_CPF__SHIFT 0x10
-#define GRBM_READ_ERROR2__READ_REQUESTER_RSMU__SHIFT 0x11
-#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12
-#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f
-#define GRBM_READ_ERROR2__READ_REQUESTER_CPF_MASK 0x00010000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_RSMU_MASK 0x00020000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x00040000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x00080000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x00100000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x00200000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x00400000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x00800000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x01000000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x02000000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x04000000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x08000000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000L
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000L
-//GRBM_INT_CNTL
-#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0
-#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13
-#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x00000001L
-#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x00080000L
-//GRBM_TRAP_OP
-#define GRBM_TRAP_OP__RW__SHIFT 0x0
-#define GRBM_TRAP_OP__RW_MASK 0x00000001L
-//GRBM_TRAP_ADDR
-#define GRBM_TRAP_ADDR__DATA__SHIFT 0x0
-#define GRBM_TRAP_ADDR__DATA_MASK 0x0003FFFFL
-//GRBM_TRAP_ADDR_MSK
-#define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0
-#define GRBM_TRAP_ADDR_MSK__DATA_MASK 0x0003FFFFL
-//GRBM_TRAP_WD
-#define GRBM_TRAP_WD__DATA__SHIFT 0x0
-#define GRBM_TRAP_WD__DATA_MASK 0xFFFFFFFFL
-//GRBM_TRAP_WD_MSK
-#define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0
-#define GRBM_TRAP_WD_MSK__DATA_MASK 0xFFFFFFFFL
-//GRBM_DSM_BYPASS
-#define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x0
-#define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x2
-#define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x00000003L
-#define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x00000004L
-//GRBM_WRITE_ERROR
-#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0
-#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU__SHIFT 0x1
-#define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2
-#define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x5
-#define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc
-#define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd
-#define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14
-#define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16
-#define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f
-#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x00000001L
-#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU_MASK 0x00000002L
-#define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x0000001CL
-#define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x000001E0L
-#define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x00001000L
-#define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x0001E000L
-#define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x00300000L
-#define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0x00C00000L
-#define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000L
-//GRBM_IOV_ERROR
-#define GRBM_IOV_ERROR__IOV_ADDR__SHIFT 0x2
-#define GRBM_IOV_ERROR__IOV_VFID__SHIFT 0x14
-#define GRBM_IOV_ERROR__IOV_VF__SHIFT 0x1a
-#define GRBM_IOV_ERROR__IOV_OP__SHIFT 0x1b
-#define GRBM_IOV_ERROR__IOV_ERROR__SHIFT 0x1f
-#define GRBM_IOV_ERROR__IOV_ADDR_MASK 0x000FFFFCL
-#define GRBM_IOV_ERROR__IOV_VFID_MASK 0x03F00000L
-#define GRBM_IOV_ERROR__IOV_VF_MASK 0x04000000L
-#define GRBM_IOV_ERROR__IOV_OP_MASK 0x08000000L
-#define GRBM_IOV_ERROR__IOV_ERROR_MASK 0x80000000L
-//GRBM_CHIP_REVISION
-#define GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0
-#define GRBM_CHIP_REVISION__CHIP_REVISION_MASK 0x000000FFL
-//GRBM_GFX_CNTL
-#define GRBM_GFX_CNTL__PIPEID__SHIFT 0x0
-#define GRBM_GFX_CNTL__MEID__SHIFT 0x2
-#define GRBM_GFX_CNTL__VMID__SHIFT 0x4
-#define GRBM_GFX_CNTL__QUEUEID__SHIFT 0x8
-#define GRBM_GFX_CNTL__PIPEID_MASK 0x00000003L
-#define GRBM_GFX_CNTL__MEID_MASK 0x0000000CL
-#define GRBM_GFX_CNTL__VMID_MASK 0x000000F0L
-#define GRBM_GFX_CNTL__QUEUEID_MASK 0x00000700L
-//GRBM_RSMU_CFG
-#define GRBM_RSMU_CFG__APERTURE_ID__SHIFT 0x0
-#define GRBM_RSMU_CFG__QOS__SHIFT 0xc
-#define GRBM_RSMU_CFG__POSTED_WR__SHIFT 0x10
-#define GRBM_RSMU_CFG__APERTURE_ID_MASK 0x00000FFFL
-#define GRBM_RSMU_CFG__QOS_MASK 0x0000F000L
-#define GRBM_RSMU_CFG__POSTED_WR_MASK 0x00010000L
-//GRBM_IH_CREDIT
-#define GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
-#define GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10
-#define GRBM_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
-#define GRBM_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L
-//GRBM_PWR_CNTL2
-#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT 0x10
-#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT 0x14
-#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK 0x00010000L
-#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK 0x00100000L
-//GRBM_UTCL2_INVAL_RANGE_START
-#define GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT 0x0
-#define GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK 0x0003FFFFL
-//GRBM_UTCL2_INVAL_RANGE_END
-#define GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT 0x0
-#define GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK 0x0003FFFFL
-//GRBM_RSMU_READ_ERROR
-#define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS__SHIFT 0x2
-#define GRBM_RSMU_READ_ERROR__RSMU_READ_VF__SHIFT 0x14
-#define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID__SHIFT 0x15
-#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE__SHIFT 0x1b
-#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR__SHIFT 0x1f
-#define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS_MASK 0x000FFFFCL
-#define GRBM_RSMU_READ_ERROR__RSMU_READ_VF_MASK 0x00100000L
-#define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID_MASK 0x07E00000L
-#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE_MASK 0x08000000L
-#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_MASK 0x80000000L
-//GRBM_CHICKEN_BITS
-#define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ__SHIFT 0x0
-#define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ_MASK 0x00000001L
-//GRBM_NOWHERE
-#define GRBM_NOWHERE__DATA__SHIFT 0x0
-#define GRBM_NOWHERE__DATA_MASK 0xFFFFFFFFL
-//GRBM_SCRATCH_REG0
-#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
-#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL
-//GRBM_SCRATCH_REG1
-#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
-#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL
-//GRBM_SCRATCH_REG2
-#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
-#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL
-//GRBM_SCRATCH_REG3
-#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
-#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL
-//GRBM_SCRATCH_REG4
-#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
-#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL
-//GRBM_SCRATCH_REG5
-#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
-#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL
-//GRBM_SCRATCH_REG6
-#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
-#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL
-//GRBM_SCRATCH_REG7
-#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
-#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL
-
-
-// addressBlock: gc_cpdec
-//CP_CPC_STATUS
-#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0
-#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1
-#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2
-#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3
-#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4
-#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5
-#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6
-#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7
-#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa
-#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb
-#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc
-#define CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT 0xd
-#define CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT 0xe
-#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d
-#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e
-#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f
-#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x00000001L
-#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x00000002L
-#define CP_CPC_STATUS__DC0_BUSY_MASK 0x00000004L
-#define CP_CPC_STATUS__DC1_BUSY_MASK 0x00000008L
-#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x00000010L
-#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x00000020L
-#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x00000040L
-#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x00000080L
-#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x00000400L
-#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x00000800L
-#define CP_CPC_STATUS__QU_BUSY_MASK 0x00001000L
-#define CP_CPC_STATUS__UTCL2IU_BUSY_MASK 0x00002000L
-#define CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK 0x00004000L
-#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000L
-#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000L
-#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000L
-//CP_CPC_BUSY_STAT
-#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0
-#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1
-#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2
-#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3
-#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4
-#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5
-#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6
-#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7
-#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8
-#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9
-#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa
-#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb
-#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc
-#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd
-#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10
-#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11
-#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12
-#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13
-#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14
-#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15
-#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16
-#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17
-#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18
-#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19
-#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a
-#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b
-#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c
-#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d
-#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x00000001L
-#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x00000002L
-#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x00000004L
-#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x00000008L
-#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x00000010L
-#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x00000020L
-#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x00000040L
-#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x00000080L
-#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x00000100L
-#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x00000200L
-#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x00000400L
-#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x00000800L
-#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x00001000L
-#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x00002000L
-#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x00010000L
-#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x00020000L
-#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x00040000L
-#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x00080000L
-#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x00100000L
-#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x00200000L
-#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x00400000L
-#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x00800000L
-#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x01000000L
-#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x02000000L
-#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x04000000L
-#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x08000000L
-#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000L
-#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000L
-//CP_CPC_STALLED_STAT1
-#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3
-#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4
-#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6
-#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8
-#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9
-#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa
-#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd
-#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10
-#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11
-#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12
-#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15
-#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x16
-#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x17
-#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT 0x18
-#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x00000008L
-#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x00000010L
-#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x00000040L
-#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x00000100L
-#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x00000200L
-#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x00000400L
-#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x00002000L
-#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x00010000L
-#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x00020000L
-#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x00040000L
-#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x00200000L
-#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00400000L
-#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00800000L
-#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK 0x01000000L
-//CP_CPF_STATUS
-#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0
-#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1
-#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4
-#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5
-#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6
-#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7
-#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8
-#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9
-#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa
-#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb
-#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc
-#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd
-#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe
-#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf
-#define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10
-#define CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT 0x11
-#define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a
-#define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b
-#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c
-#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e
-#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f
-#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x00000001L
-#define CP_CPF_STATUS__CSF_BUSY_MASK 0x00000002L
-#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x00000010L
-#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x00000020L
-#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x00000040L
-#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x00000080L
-#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x00000100L
-#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x00000200L
-#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x00000400L
-#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x00000800L
-#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x00001000L
-#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x00002000L
-#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x00004000L
-#define CP_CPF_STATUS__HQD_BUSY_MASK 0x00008000L
-#define CP_CPF_STATUS__PRT_BUSY_MASK 0x00010000L
-#define CP_CPF_STATUS__UTCL2IU_BUSY_MASK 0x00020000L
-#define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x04000000L
-#define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x08000000L
-#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000L
-#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000L
-#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000L
-//CP_CPF_BUSY_STAT
-#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
-#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1
-#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2
-#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3
-#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4
-#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5
-#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6
-#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7
-#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8
-#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9
-#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb
-#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc
-#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd
-#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe
-#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf
-#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10
-#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11
-#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12
-#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13
-#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14
-#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15
-#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16
-#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17
-#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18
-#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19
-#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a
-#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b
-#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c
-#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d
-#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e
-#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f
-#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L
-#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x00000002L
-#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x00000004L
-#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x00000008L
-#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x00000010L
-#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x00000020L
-#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x00000040L
-#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x00000080L
-#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x00000100L
-#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x00000200L
-#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x00000800L
-#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x00001000L
-#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x00002000L
-#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x00004000L
-#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x00008000L
-#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x00010000L
-#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x00020000L
-#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x00040000L
-#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x00080000L
-#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x00100000L
-#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x00200000L
-#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x00400000L
-#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x00800000L
-#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x01000000L
-#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x02000000L
-#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x04000000L
-#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x08000000L
-#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000L
-#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000L
-#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000L
-#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000L
-//CP_CPF_STALLED_STAT1
-#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0
-#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1
-#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2
-#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3
-#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5
-#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6
-#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x7
-#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x8
-#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS__SHIFT 0x9
-#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT 0xa
-#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE__SHIFT 0xb
-#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x00000001L
-#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x00000002L
-#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x00000004L
-#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x00000008L
-#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x00000020L
-#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x00000040L
-#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00000080L
-#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00000100L
-#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS_MASK 0x00000200L
-#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS_MASK 0x00000400L
-#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE_MASK 0x00000800L
-//CP_CPC_GRBM_FREE_COUNT
-#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
-#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL
-//CP_MEC_CNTL
-#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4
-#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10
-#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11
-#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12
-#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13
-#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14
-#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15
-#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c
-#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d
-#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e
-#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f
-#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x00000010L
-#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x00010000L
-#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x00020000L
-#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x00040000L
-#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x00080000L
-#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x00100000L
-#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x00200000L
-#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000L
-#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000L
-#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000L
-#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000L
-//CP_MEC_ME1_HEADER_DUMP
-#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
-#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL
-//CP_MEC_ME2_HEADER_DUMP
-#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
-#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL
-//CP_CPC_SCRATCH_INDEX
-#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
-#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL
-//CP_CPC_SCRATCH_DATA
-#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
-#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL
-//CP_CPF_GRBM_FREE_COUNT
-#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
-#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x00000007L
-//CP_CPC_HALT_HYST_COUNT
-#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0
-#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0x0000000FL
-//CP_PRT_LOD_STATS_CNTL0
-#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT 0x0
-#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK 0xFFFFFFFFL
-//CP_PRT_LOD_STATS_CNTL1
-#define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT 0x0
-#define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK 0xFFFFFFFFL
-//CP_PRT_LOD_STATS_CNTL2
-#define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT 0x0
-#define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK 0x000003FFL
-//CP_PRT_LOD_STATS_CNTL3
-#define CP_PRT_LOD_STATS_CNTL3__INTERVAL__SHIFT 0x2
-#define CP_PRT_LOD_STATS_CNTL3__RESET_CNT__SHIFT 0xa
-#define CP_PRT_LOD_STATS_CNTL3__RESET_FORCE__SHIFT 0x12
-#define CP_PRT_LOD_STATS_CNTL3__REPORT_AND_RESET__SHIFT 0x13
-#define CP_PRT_LOD_STATS_CNTL3__MC_VMID__SHIFT 0x17
-#define CP_PRT_LOD_STATS_CNTL3__CACHE_POLICY__SHIFT 0x1c
-#define CP_PRT_LOD_STATS_CNTL3__INTERVAL_MASK 0x000003FCL
-#define CP_PRT_LOD_STATS_CNTL3__RESET_CNT_MASK 0x0003FC00L
-#define CP_PRT_LOD_STATS_CNTL3__RESET_FORCE_MASK 0x00040000L
-#define CP_PRT_LOD_STATS_CNTL3__REPORT_AND_RESET_MASK 0x00080000L
-#define CP_PRT_LOD_STATS_CNTL3__MC_VMID_MASK 0x07800000L
-#define CP_PRT_LOD_STATS_CNTL3__CACHE_POLICY_MASK 0x10000000L
-//CP_CE_COMPARE_COUNT
-#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0
-#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xFFFFFFFFL
-//CP_CE_DE_COUNT
-#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
-#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL
-//CP_DE_CE_COUNT
-#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0
-#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL
-//CP_DE_LAST_INVAL_COUNT
-#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0
-#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xFFFFFFFFL
-//CP_DE_DE_COUNT
-#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
-#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL
-//CP_STALLED_STAT3
-#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
-#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1
-#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2
-#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3
-#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4
-#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5
-#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6
-#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7
-#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa
-#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb
-#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc
-#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd
-#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe
-#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf
-#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10
-#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11
-#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE__SHIFT 0x12
-#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x13
-#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS__SHIFT 0x14
-#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L
-#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x00000002L
-#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x00000004L
-#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x00000008L
-#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x00000010L
-#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x00000020L
-#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x00000040L
-#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x00000080L
-#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x00000400L
-#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x00000800L
-#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x00001000L
-#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x00002000L
-#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x00004000L
-#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x00008000L
-#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x00010000L
-#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00020000L
-#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE_MASK 0x00040000L
-#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS_MASK 0x00080000L
-#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS_MASK 0x00100000L
-//CP_STALLED_STAT1
-#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0
-#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2
-#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4
-#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa
-#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb
-#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc
-#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd
-#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe
-#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf
-#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17
-#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18
-#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19
-#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a
-#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b
-#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c
-#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d
-#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x00000001L
-#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x00000004L
-#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x00000010L
-#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x00000400L
-#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x00000800L
-#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x00001000L
-#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00002000L
-#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x00004000L
-#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x00008000L
-#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x00800000L
-#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x01000000L
-#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x02000000L
-#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x04000000L
-#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x08000000L
-#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000L
-#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000L
-//CP_STALLED_STAT2
-#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
-#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1
-#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2
-#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4
-#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5
-#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8
-#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9
-#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa
-#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb
-#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc
-#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd
-#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe
-#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf
-#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10
-#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11
-#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12
-#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13
-#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14
-#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15
-#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16
-#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17
-#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18
-#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19
-#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a
-#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b
-#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c
-#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d
-#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e
-#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f
-#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L
-#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x00000002L
-#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x00000004L
-#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x00000010L
-#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x00000020L
-#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x00000100L
-#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x00000200L
-#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x00000400L
-#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x00000800L
-#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x00001000L
-#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x00002000L
-#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x00004000L
-#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x00008000L
-#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00010000L
-#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00020000L
-#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x00040000L
-#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x00080000L
-#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00100000L
-#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x00200000L
-#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x00400000L
-#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x00800000L
-#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x01000000L
-#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x02000000L
-#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x04000000L
-#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x08000000L
-#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000L
-#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000L
-#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000L
-#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000L
-//CP_BUSY_STAT
-#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
-#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6
-#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7
-#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8
-#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9
-#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa
-#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc
-#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd
-#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe
-#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf
-#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11
-#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12
-#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13
-#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14
-#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15
-#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16
-#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L
-#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x00000040L
-#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x00000080L
-#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x00000100L
-#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x00000200L
-#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x00000400L
-#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x00001000L
-#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x00002000L
-#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x00004000L
-#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x00008000L
-#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x00020000L
-#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x00040000L
-#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x00080000L
-#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x00100000L
-#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x00200000L
-#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x00400000L
-//CP_STAT
-#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9
-#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa
-#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb
-#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc
-#define CP_STAT__DC_BUSY__SHIFT 0xd
-#define CP_STAT__UTCL2IU_BUSY__SHIFT 0xe
-#define CP_STAT__PFP_BUSY__SHIFT 0xf
-#define CP_STAT__MEQ_BUSY__SHIFT 0x10
-#define CP_STAT__ME_BUSY__SHIFT 0x11
-#define CP_STAT__QUERY_BUSY__SHIFT 0x12
-#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13
-#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14
-#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15
-#define CP_STAT__DMA_BUSY__SHIFT 0x16
-#define CP_STAT__RCIU_BUSY__SHIFT 0x17
-#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18
-#define CP_STAT__CE_BUSY__SHIFT 0x1a
-#define CP_STAT__TCIU_BUSY__SHIFT 0x1b
-#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c
-#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d
-#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e
-#define CP_STAT__CP_BUSY__SHIFT 0x1f
-#define CP_STAT__ROQ_RING_BUSY_MASK 0x00000200L
-#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x00000400L
-#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x00000800L
-#define CP_STAT__ROQ_STATE_BUSY_MASK 0x00001000L
-#define CP_STAT__DC_BUSY_MASK 0x00002000L
-#define CP_STAT__UTCL2IU_BUSY_MASK 0x00004000L
-#define CP_STAT__PFP_BUSY_MASK 0x00008000L
-#define CP_STAT__MEQ_BUSY_MASK 0x00010000L
-#define CP_STAT__ME_BUSY_MASK 0x00020000L
-#define CP_STAT__QUERY_BUSY_MASK 0x00040000L
-#define CP_STAT__SEMAPHORE_BUSY_MASK 0x00080000L
-#define CP_STAT__INTERRUPT_BUSY_MASK 0x00100000L
-#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x00200000L
-#define CP_STAT__DMA_BUSY_MASK 0x00400000L
-#define CP_STAT__RCIU_BUSY_MASK 0x00800000L
-#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x01000000L
-#define CP_STAT__CE_BUSY_MASK 0x04000000L
-#define CP_STAT__TCIU_BUSY_MASK 0x08000000L
-#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000L
-#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000L
-#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000L
-#define CP_STAT__CP_BUSY_MASK 0x80000000L
-//CP_ME_HEADER_DUMP
-#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0
-#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xFFFFFFFFL
-//CP_PFP_HEADER_DUMP
-#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0
-#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xFFFFFFFFL
-//CP_GRBM_FREE_COUNT
-#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
-#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8
-#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10
-#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL
-#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x00003F00L
-#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x003F0000L
-//CP_CE_HEADER_DUMP
-#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0
-#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xFFFFFFFFL
-//CP_PFP_INSTR_PNTR
-#define CP_PFP_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
-#define CP_PFP_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
-//CP_ME_INSTR_PNTR
-#define CP_ME_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
-#define CP_ME_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
-//CP_CE_INSTR_PNTR
-#define CP_CE_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
-#define CP_CE_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
-//CP_MEC1_INSTR_PNTR
-#define CP_MEC1_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
-#define CP_MEC1_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
-//CP_MEC2_INSTR_PNTR
-#define CP_MEC2_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
-#define CP_MEC2_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
-//CP_CSF_STAT
-#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8
-#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x0001FF00L
-//CP_ME_CNTL
-#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4
-#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6
-#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8
-#define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10
-#define CP_ME_CNTL__CE_PIPE1_RESET__SHIFT 0x11
-#define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12
-#define CP_ME_CNTL__PFP_PIPE1_RESET__SHIFT 0x13
-#define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14
-#define CP_ME_CNTL__ME_PIPE1_RESET__SHIFT 0x15
-#define CP_ME_CNTL__CE_HALT__SHIFT 0x18
-#define CP_ME_CNTL__CE_STEP__SHIFT 0x19
-#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a
-#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b
-#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c
-#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d
-#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x00000010L
-#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x00000040L
-#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x00000100L
-#define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x00010000L
-#define CP_ME_CNTL__CE_PIPE1_RESET_MASK 0x00020000L
-#define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x00040000L
-#define CP_ME_CNTL__PFP_PIPE1_RESET_MASK 0x00080000L
-#define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x00100000L
-#define CP_ME_CNTL__ME_PIPE1_RESET_MASK 0x00200000L
-#define CP_ME_CNTL__CE_HALT_MASK 0x01000000L
-#define CP_ME_CNTL__CE_STEP_MASK 0x02000000L
-#define CP_ME_CNTL__PFP_HALT_MASK 0x04000000L
-#define CP_ME_CNTL__PFP_STEP_MASK 0x08000000L
-#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L
-#define CP_ME_CNTL__ME_STEP_MASK 0x20000000L
-//CP_CNTX_STAT
-#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0
-#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8
-#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14
-#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c
-#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0x000000FFL
-#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x00000700L
-#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0x0FF00000L
-#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000L
-//CP_ME_PREEMPTION
-#define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0
-#define CP_ME_PREEMPTION__OBSOLETE_MASK 0x00000001L
-//CP_ROQ_THRESHOLDS
-#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0
-#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8
-#define CP_ROQ_THRESHOLDS__IB1_START_MASK 0x000000FFL
-#define CP_ROQ_THRESHOLDS__IB2_START_MASK 0x0000FF00L
-//CP_MEQ_STQ_THRESHOLD
-#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0
-#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0x000000FFL
-//CP_RB2_RPTR
-#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0
-#define CP_RB2_RPTR__RB_RPTR_MASK 0x000FFFFFL
-//CP_RB1_RPTR
-#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0
-#define CP_RB1_RPTR__RB_RPTR_MASK 0x000FFFFFL
-//CP_RB0_RPTR
-#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0
-#define CP_RB0_RPTR__RB_RPTR_MASK 0x000FFFFFL
-//CP_RB_RPTR
-#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0
-#define CP_RB_RPTR__RB_RPTR_MASK 0x000FFFFFL
-//CP_RB_WPTR_DELAY
-#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0
-#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c
-#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0FFFFFFFL
-#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xF0000000L
-//CP_RB_WPTR_POLL_CNTL
-#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0
-#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
-#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0x0000FFFFL
-#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
-//CP_ROQ1_THRESHOLDS
-#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0
-#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8
-#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10
-#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18
-#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0x000000FFL
-#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0x0000FF00L
-#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0x00FF0000L
-#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xFF000000L
-//CP_ROQ2_THRESHOLDS
-#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0
-#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8
-#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10
-#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18
-#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0x000000FFL
-#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0x0000FF00L
-#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x00FF0000L
-#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xFF000000L
-//CP_STQ_THRESHOLDS
-#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0
-#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8
-#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10
-#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0x000000FFL
-#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0x0000FF00L
-#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0x00FF0000L
-//CP_QUEUE_THRESHOLDS
-#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0
-#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8
-#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x0000003FL
-#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x00003F00L
-//CP_MEQ_THRESHOLDS
-#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0
-#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8
-#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0x000000FFL
-#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0x0000FF00L
-//CP_ROQ_AVAIL
-#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0
-#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10
-#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x000007FFL
-#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x07FF0000L
-//CP_STQ_AVAIL
-#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0
-#define CP_STQ_AVAIL__STQ_CNT_MASK 0x000001FFL
-//CP_ROQ2_AVAIL
-#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0
-#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x000007FFL
-//CP_MEQ_AVAIL
-#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0
-#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x000003FFL
-//CP_CMD_INDEX
-#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0
-#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc
-#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10
-#define CP_CMD_INDEX__CMD_INDEX_MASK 0x000007FFL
-#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x00003000L
-#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00070000L
-//CP_CMD_DATA
-#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0
-#define CP_CMD_DATA__CMD_DATA_MASK 0xFFFFFFFFL
-//CP_ROQ_RB_STAT
-#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0
-#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10
-#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x000003FFL
-#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x03FF0000L
-//CP_ROQ_IB1_STAT
-#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0
-#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10
-#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x000003FFL
-#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x03FF0000L
-//CP_ROQ_IB2_STAT
-#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0
-#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10
-#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x000003FFL
-#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x03FF0000L
-//CP_STQ_STAT
-#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0
-#define CP_STQ_STAT__STQ_RPTR_MASK 0x000003FFL
-//CP_STQ_WR_STAT
-#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0
-#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x000003FFL
-//CP_MEQ_STAT
-#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0
-#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10
-#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003FFL
-#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03FF0000L
-//CP_CEQ1_AVAIL
-#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0
-#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10
-#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x000007FFL
-#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x07FF0000L
-//CP_CEQ2_AVAIL
-#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0
-#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x000007FFL
-//CP_CE_ROQ_RB_STAT
-#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0
-#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10
-#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x000003FFL
-#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x03FF0000L
-//CP_CE_ROQ_IB1_STAT
-#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0
-#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10
-#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x000003FFL
-#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x03FF0000L
-//CP_CE_ROQ_IB2_STAT
-#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0
-#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10
-#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x000003FFL
-#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x03FF0000L
-#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16
-#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
-#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x00400000L
-#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L
-
-
-// addressBlock: gc_padec
-//VGT_VTX_VECT_EJECT_REG
-#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0
-#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x0000007FL
-//VGT_DMA_DATA_FIFO_DEPTH
-#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0
-#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH__SHIFT 0x9
-#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x000001FFL
-#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH_MASK 0x0007FE00L
-//VGT_DMA_REQ_FIFO_DEPTH
-#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0
-#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x0000003FL
-//VGT_DRAW_INIT_FIFO_DEPTH
-#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0
-#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x0000003FL
-//VGT_LAST_COPY_STATE
-#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
-#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10
-#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L
-#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00070000L
-//VGT_CACHE_INVALIDATION
-#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0
-#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT 0x4
-#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x5
-#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6
-#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9
-#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb
-#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc
-#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd
-#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10
-#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG__SHIFT 0x15
-#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1__SHIFT 0x16
-#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2__SHIFT 0x19
-#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE__SHIFT 0x1c
-#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI__SHIFT 0x1d
-#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x00000003L
-#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK 0x00000010L
-#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x00000020L
-#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0x000000C0L
-#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x00000200L
-#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x00000800L
-#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x00001000L
-#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x00002000L
-#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x001F0000L
-#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_MASK 0x00200000L
-#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1_MASK 0x01C00000L
-#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2_MASK 0x0E000000L
-#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE_MASK 0x10000000L
-#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI_MASK 0x20000000L
-//VGT_STRMOUT_DELAY
-#define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0
-#define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8
-#define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb
-#define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe
-#define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11
-#define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0x000000FFL
-#define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x00000700L
-#define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x00003800L
-#define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x0001C000L
-#define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0x000E0000L
-//VGT_FIFO_DEPTHS
-#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0
-#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7
-#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8
-#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT 0x16
-#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x0000007FL
-#define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x00000080L
-#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x003FFF00L
-#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK 0x0FC00000L
-//VGT_GS_VERTEX_REUSE
-#define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0
-#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x0000001FL
-//VGT_MC_LAT_CNTL
-#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0
-#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x0000000FL
-//IA_CNTL_STATUS
-#define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x0
-#define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x1
-#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x2
-#define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x3
-#define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x4
-#define IA_CNTL_STATUS__IA_BUSY_MASK 0x00000001L
-#define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x00000002L
-#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x00000004L
-#define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x00000008L
-#define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x00000010L
-//VGT_CNTL_STATUS
-#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x0
-#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x1
-#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x2
-#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x3
-#define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x4
-#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x5
-#define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x6
-#define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x7
-#define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x8
-#define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x9
-#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY__SHIFT 0xa
-#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x00000001L
-#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x00000002L
-#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x00000004L
-#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x00000008L
-#define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x00000010L
-#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x00000020L
-#define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x00000040L
-#define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x00000080L
-#define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x00000100L
-#define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x00000200L
-#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY_MASK 0x00000400L
-//WD_CNTL_STATUS
-#define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x0
-#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x1
-#define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x2
-#define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x3
-#define WD_CNTL_STATUS__WD_BUSY_MASK 0x00000001L
-#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x00000002L
-#define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x00000004L
-#define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x00000008L
-//CC_GC_PRIM_CONFIG
-#define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10
-#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18
-#define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L
-#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L
-//GC_USER_PRIM_CONFIG
-#define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10
-#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18
-#define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L
-#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L
-//WD_QOS
-#define WD_QOS__DRAW_STALL__SHIFT 0x0
-#define WD_QOS__DRAW_STALL_MASK 0x00000001L
-//WD_UTCL1_CNTL
-#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
-#define WD_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17
-#define WD_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
-#define WD_UTCL1_CNTL__BYPASS__SHIFT 0x19
-#define WD_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
-#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
-#define WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
-#define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
-#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
-#define WD_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L
-#define WD_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
-#define WD_UTCL1_CNTL__BYPASS_MASK 0x02000000L
-#define WD_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
-#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
-#define WD_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
-#define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
-//WD_UTCL1_STATUS
-#define WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
-#define WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
-#define WD_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
-#define WD_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
-#define WD_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
-#define WD_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
-#define WD_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
-#define WD_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
-#define WD_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
-#define WD_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
-#define WD_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
-#define WD_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
-//IA_UTCL1_CNTL
-#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
-#define IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17
-#define IA_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
-#define IA_UTCL1_CNTL__BYPASS__SHIFT 0x19
-#define IA_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
-#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
-#define IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
-#define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
-#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
-#define IA_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L
-#define IA_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
-#define IA_UTCL1_CNTL__BYPASS_MASK 0x02000000L
-#define IA_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
-#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
-#define IA_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
-#define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
-//IA_UTCL1_STATUS
-#define IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
-#define IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
-#define IA_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
-#define IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
-#define IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
-#define IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
-#define IA_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
-#define IA_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
-#define IA_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
-#define IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
-#define IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
-#define IA_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
-//VGT_SYS_CONFIG
-#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0
-#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1
-#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7
-#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x00000001L
-#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x0000007EL
-#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x00000080L
-//VGT_VS_MAX_WAVE_ID
-#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
-#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
-//VGT_GS_MAX_WAVE_ID
-#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
-#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
-//GFX_PIPE_CONTROL
-#define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0
-#define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd
-#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10
-#define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x00001FFFL
-#define GFX_PIPE_CONTROL__RESERVED_MASK 0x0000E000L
-#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x00010000L
-//CC_GC_SHADER_ARRAY_CONFIG
-#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10
-#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xFFFF0000L
-//GC_USER_SHADER_ARRAY_CONFIG
-#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10
-#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xFFFF0000L
-//VGT_DMA_PRIMITIVE_TYPE
-#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0
-#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL
-//VGT_DMA_CONTROL
-#define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0
-#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11
-#define VGT_DMA_CONTROL__SWITCH_ON_EOI__SHIFT 0x13
-#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14
-#define VGT_DMA_CONTROL__EN_INST_OPT_BASIC__SHIFT 0x15
-#define VGT_DMA_CONTROL__EN_INST_OPT_ADV__SHIFT 0x16
-#define VGT_DMA_CONTROL__HW_USE_ONLY__SHIFT 0x17
-#define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0x0000FFFFL
-#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x00020000L
-#define VGT_DMA_CONTROL__SWITCH_ON_EOI_MASK 0x00080000L
-#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x00100000L
-#define VGT_DMA_CONTROL__EN_INST_OPT_BASIC_MASK 0x00200000L
-#define VGT_DMA_CONTROL__EN_INST_OPT_ADV_MASK 0x00400000L
-#define VGT_DMA_CONTROL__HW_USE_ONLY_MASK 0x00800000L
-//VGT_DMA_LS_HS_CONFIG
-#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8
-#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L
-//WD_BUF_RESOURCE_1
-#define WD_BUF_RESOURCE_1__POS_BUF_SIZE__SHIFT 0x0
-#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE__SHIFT 0x10
-#define WD_BUF_RESOURCE_1__POS_BUF_SIZE_MASK 0x0000FFFFL
-#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE_MASK 0xFFFF0000L
-//WD_BUF_RESOURCE_2
-#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE__SHIFT 0x0
-#define WD_BUF_RESOURCE_2__ADDR_MODE__SHIFT 0xf
-#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE__SHIFT 0x10
-#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE_MASK 0x00001FFFL
-#define WD_BUF_RESOURCE_2__ADDR_MODE_MASK 0x00008000L
-#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE_MASK 0xFFFF0000L
-//PA_CL_CNTL_STATUS
-#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT 0x0
-#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED__SHIFT 0x1
-#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED__SHIFT 0x2
-#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED_MASK 0x00000001L
-#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED_MASK 0x00000002L
-#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED_MASK 0x00000004L
-//PA_CL_ENHANCE
-#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0
-#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1
-#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3
-#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4
-#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT 0x6
-#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT 0x7
-#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT 0x8
-#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT 0x9
-#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT 0xb
-#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT 0xc
-#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT 0xe
-#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c
-#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d
-#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e
-#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f
-#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L
-#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x00000006L
-#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x00000008L
-#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x00000010L
-#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK 0x00000040L
-#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK 0x00000080L
-#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK 0x00000100L
-#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK 0x00000600L
-#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK 0x00000800L
-#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK 0x00003000L
-#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK 0x0001C000L
-#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L
-#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L
-#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L
-#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L
-//PA_SU_CNTL_STATUS
-#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f
-#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L
-//PA_SC_FIFO_DEPTH_CNTL
-#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0
-#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x000003FFL
-//PA_SC_P3D_TRAP_SCREEN_HV_LOCK
-#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
-#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L
-//PA_SC_HP3D_TRAP_SCREEN_HV_LOCK
-#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
-#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L
-//PA_SC_TRAP_SCREEN_HV_LOCK
-#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
-#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L
-//PA_SC_FORCE_EOV_MAX_CNTS
-#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0
-#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10
-#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0x0000FFFFL
-#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xFFFF0000L
-//PA_SC_BINNER_EVENT_CNTL_0
-#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT 0x0
-#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT 0x2
-#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT 0x4
-#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT 0x6
-#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT 0x8
-#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT 0xa
-#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT 0xc
-#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT 0xe
-#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT 0x10
-#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9__SHIFT 0x12
-#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT 0x14
-#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT 0x16
-#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT 0x18
-#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT 0x1a
-#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT 0x1c
-#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT 0x1e
-#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK 0x00000003L
-#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK 0x0000000CL
-#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK 0x00000030L
-#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK 0x000000C0L
-#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK 0x00000300L
-#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK 0x00000C00L
-#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK 0x00003000L
-#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK 0x0000C000L
-#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK 0x00030000L
-#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9_MASK 0x000C0000L
-#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK 0x00300000L
-#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK 0x00C00000L
-#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK 0x03000000L
-#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK 0x0C000000L
-#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK 0x30000000L
-#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK 0xC0000000L
-//PA_SC_BINNER_EVENT_CNTL_1
-#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT 0x0
-#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT 0x2
-#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT 0x4
-#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT 0x6
-#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT 0x8
-#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE__SHIFT 0xa
-#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT 0xc
-#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT 0xe
-#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT 0x10
-#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT 0x12
-#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT 0x14
-#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT 0x16
-#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT 0x18
-#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT__SHIFT 0x1a
-#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT 0x1c
-#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT 0x1e
-#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK 0x00000003L
-#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK 0x0000000CL
-#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK 0x00000030L
-#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK 0x000000C0L
-#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK 0x00000300L
-#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE_MASK 0x00000C00L
-#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK 0x00003000L
-#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK 0x0000C000L
-#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK 0x00030000L
-#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK 0x000C0000L
-#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK 0x00300000L
-#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK 0x00C00000L
-#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK 0x03000000L
-#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT_MASK 0x0C000000L
-#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK 0x30000000L
-#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK 0xC0000000L
-//PA_SC_BINNER_EVENT_CNTL_2
-#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT 0x0
-#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT 0x2
-#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT 0x4
-#define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE__SHIFT 0x6
-#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT 0x8
-#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT 0xa
-#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT 0xc
-#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT 0xe
-#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT 0x10
-#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS__SHIFT 0x12
-#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT 0x14
-#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT 0x16
-#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT 0x18
-#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT 0x1a
-#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT 0x1c
-#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT 0x1e
-#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK 0x00000003L
-#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK 0x0000000CL
-#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK 0x00000030L
-#define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE_MASK 0x000000C0L
-#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK 0x00000300L
-#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK 0x00000C00L
-#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK 0x00003000L
-#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK 0x0000C000L
-#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK 0x00030000L
-#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS_MASK 0x000C0000L
-#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK 0x00300000L
-#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK 0x00C00000L
-#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK 0x03000000L
-#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK 0x0C000000L
-#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK 0x30000000L
-#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK 0xC0000000L
-//PA_SC_BINNER_EVENT_CNTL_3
-#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT 0x0
-#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT 0x2
-#define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST__SHIFT 0x4
-#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT 0x6
-#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT 0x8
-#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT 0xa
-#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH__SHIFT 0xc
-#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT 0xe
-#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT 0x10
-#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT 0x12
-#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT 0x14
-#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT 0x16
-#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT 0x18
-#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT 0x1a
-#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE__SHIFT 0x1c
-#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63__SHIFT 0x1e
-#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK 0x00000003L
-#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK 0x0000000CL
-#define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST_MASK 0x00000030L
-#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK 0x000000C0L
-#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK 0x00000300L
-#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK 0x00000C00L
-#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH_MASK 0x00003000L
-#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK 0x0000C000L
-#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK 0x00030000L
-#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK 0x000C0000L
-#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK 0x00300000L
-#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK 0x00C00000L
-#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK 0x03000000L
-#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK 0x0C000000L
-#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE_MASK 0x30000000L
-#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63_MASK 0xC0000000L
-//PA_SC_BINNER_TIMEOUT_COUNTER
-#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT 0x0
-#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK 0xFFFFFFFFL
-//PA_SC_BINNER_PERF_CNTL_0
-#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0x0
-#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0xa
-#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x14
-#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x17
-#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000003FFL
-#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000FFC00L
-#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x00700000L
-#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x03800000L
-//PA_SC_BINNER_PERF_CNTL_1
-#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x0
-#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x5
-#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT 0xa
-#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x0000001FL
-#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x000003E0L
-#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK 0x03FFFC00L
-//PA_SC_BINNER_PERF_CNTL_2
-#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT 0x0
-#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT 0xb
-#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK 0x000007FFL
-#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK 0x003FF800L
-//PA_SC_BINNER_PERF_CNTL_3
-#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT 0x0
-#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK 0xFFFFFFFFL
-//PA_SC_FIFO_SIZE
-#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0
-#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6
-#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf
-#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x15
-#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x0000003FL
-#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x00007FC0L
-#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x001F8000L
-#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xFFE00000L
-//PA_SC_IF_FIFO_SIZE
-#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0
-#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6
-#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc
-#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12
-#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x0000003FL
-#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0x00000FC0L
-#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x0003F000L
-#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0x00FC0000L
-//PA_SC_PKR_WAVE_TABLE_CNTL
-#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT 0x0
-#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL
-//PA_UTCL1_CNTL1
-#define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
-#define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1
-#define PA_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
-#define PA_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
-#define PA_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
-#define PA_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
-#define PA_UTCL1_CNTL1__SPARE__SHIFT 0x10
-#define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
-#define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
-#define PA_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13
-#define PA_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17
-#define PA_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18
-#define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID__SHIFT 0x19
-#define PA_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
-#define PA_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
-#define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
-#define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
-#define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
-#define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L
-#define PA_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
-#define PA_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
-#define PA_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
-#define PA_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
-#define PA_UTCL1_CNTL1__SPARE_MASK 0x00010000L
-#define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
-#define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
-#define PA_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L
-#define PA_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L
-#define PA_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L
-#define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID_MASK 0x02000000L
-#define PA_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
-#define PA_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
-#define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
-#define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
-//PA_UTCL1_CNTL2
-#define PA_UTCL1_CNTL2__SPARE1__SHIFT 0x0
-#define PA_UTCL1_CNTL2__SPARE2__SHIFT 0x8
-#define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
-#define PA_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
-#define PA_UTCL1_CNTL2__SPARE3__SHIFT 0xb
-#define PA_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
-#define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT__SHIFT 0xd
-#define PA_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
-#define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
-#define PA_UTCL1_CNTL2__SPARE4__SHIFT 0x10
-#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
-#define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13
-#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14
-#define PA_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15
-#define PA_UTCL1_CNTL2__SPARE5__SHIFT 0x19
-#define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
-#define PA_UTCL1_CNTL2__RESERVED__SHIFT 0x1b
-#define PA_UTCL1_CNTL2__SPARE1_MASK 0x000000FFL
-#define PA_UTCL1_CNTL2__SPARE2_MASK 0x00000100L
-#define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
-#define PA_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
-#define PA_UTCL1_CNTL2__SPARE3_MASK 0x00000800L
-#define PA_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
-#define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT_MASK 0x00002000L
-#define PA_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
-#define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
-#define PA_UTCL1_CNTL2__SPARE4_MASK 0x00030000L
-#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
-#define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L
-#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
-#define PA_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L
-#define PA_UTCL1_CNTL2__SPARE5_MASK 0x02000000L
-#define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
-#define PA_UTCL1_CNTL2__RESERVED_MASK 0xF8000000L
-//PA_SIDEBAND_REQUEST_DELAYS
-#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY__SHIFT 0x0
-#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY__SHIFT 0x10
-#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY_MASK 0x0000FFFFL
-#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY_MASK 0xFFFF0000L
-//PA_SC_ENHANCE
-#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0
-#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1
-#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2
-#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3
-#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4
-#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5
-#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x6
-#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x7
-#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0x8
-#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0x9
-#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xa
-#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xb
-#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xc
-#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xd
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0xe
-#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0xf
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x10
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x11
-#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x12
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x13
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x14
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x15
-#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x16
-#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x17
-#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18
-#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x19
-#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1a
-#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1b
-#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c
-#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT 0x1d
-#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x00000001L
-#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x00000002L
-#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x00000004L
-#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x00000008L
-#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x00000010L
-#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x00000020L
-#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x00000040L
-#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x00000080L
-#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x00000100L
-#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x00000200L
-#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x00000400L
-#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x00000800L
-#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x00001000L
-#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x00002000L
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x00004000L
-#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x00008000L
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x00010000L
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x00020000L
-#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x00040000L
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x00080000L
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x00100000L
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x00200000L
-#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x00400000L
-#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x00800000L
-#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L
-#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x02000000L
-#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x04000000L
-#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x08000000L
-#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK 0x10000000L
-#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK 0x20000000L
-//PA_SC_ENHANCE_1
-#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT 0x0
-#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT 0x1
-#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT 0x3
-#define PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT 0x4
-#define PA_SC_ENHANCE_1__ECO_SPARE0__SHIFT 0x5
-#define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT 0x6
-#define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT 0x7
-#define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT 0x8
-#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT 0x9
-#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT 0xa
-#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT 0xb
-#define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT 0xd
-#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE__SHIFT 0xe
-#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION__SHIFT 0xf
-#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT 0x10
-#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING__SHIFT 0x11
-#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT 0x12
-#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT 0x13
-#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT 0x14
-#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT 0x15
-#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT 0x16
-#define PA_SC_ENHANCE_1__RSVD__SHIFT 0x17
-#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK 0x00000001L
-#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK 0x00000006L
-#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK 0x00000008L
-#define PA_SC_ENHANCE_1__BYPASS_PBB_MASK 0x00000010L
-#define PA_SC_ENHANCE_1__ECO_SPARE0_MASK 0x00000020L
-#define PA_SC_ENHANCE_1__ECO_SPARE1_MASK 0x00000040L
-#define PA_SC_ENHANCE_1__ECO_SPARE2_MASK 0x00000080L
-#define PA_SC_ENHANCE_1__ECO_SPARE3_MASK 0x00000100L
-#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK 0x00000200L
-#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK 0x00000400L
-#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK 0x00000800L
-#define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK 0x00002000L
-#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE_MASK 0x00004000L
-#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION_MASK 0x00008000L
-#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK 0x00010000L
-#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING_MASK 0x00020000L
-#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK 0x00040000L
-#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK 0x00080000L
-#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK 0x00100000L
-#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK 0x00200000L
-#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK 0x00400000L
-#define PA_SC_ENHANCE_1__RSVD_MASK 0xFF800000L
-//PA_SC_DSM_CNTL
-#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x0
-#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT 0x1
-#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK 0x00000001L
-#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK 0x00000002L
-//PA_SC_TILE_STEERING_CREST_OVERRIDE
-#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT 0x0
-#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT 0x1
-#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT 0x5
-#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK 0x00000001L
-#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK 0x00000006L
-#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK 0x00000060L
-
-
-// addressBlock: gc_sqdec
-//SQ_CONFIG
-#define SQ_CONFIG__UNUSED__SHIFT 0x0
-#define SQ_CONFIG__OVERRIDE_ALU_BUSY__SHIFT 0x7
-#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY__SHIFT 0xb
-#define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0xc
-#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0xd
-#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0xe
-#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0xf
-#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE__SHIFT 0x10
-#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE__SHIFT 0x11
-#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT 0x12
-#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT 0x13
-#define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT 0x15
-#define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP__SHIFT 0x1c
-#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING__SHIFT 0x1d
-#define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE__SHIFT 0x1e
-#define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE__SHIFT 0x1f
-#define SQ_CONFIG__UNUSED_MASK 0x0000007FL
-#define SQ_CONFIG__OVERRIDE_ALU_BUSY_MASK 0x00000080L
-#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY_MASK 0x00000800L
-#define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x00001000L
-#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x00002000L
-#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x00004000L
-#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x00008000L
-#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE_MASK 0x00010000L
-#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE_MASK 0x00020000L
-#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK 0x00040000L
-#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK 0x00180000L
-#define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK 0x0FE00000L
-#define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP_MASK 0x10000000L
-#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING_MASK 0x20000000L
-#define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE_MASK 0x40000000L
-#define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE_MASK 0x80000000L
-//SQC_CONFIG
-#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0
-#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2
-#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4
-#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6
-#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7
-#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8
-#define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x9
-#define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0xa
-#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb
-#define SQC_CONFIG__EVICT_LRU__SHIFT 0xc
-#define SQC_CONFIG__FORCE_2_BANK__SHIFT 0xe
-#define SQC_CONFIG__FORCE_1_BANK__SHIFT 0xf
-#define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0x10
-#define SQC_CONFIG__INST_PRF_COUNT__SHIFT 0x18
-#define SQC_CONFIG__INST_PRF_FILTER_DIS__SHIFT 0x1a
-#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x00000003L
-#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0x0000000CL
-#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x00000030L
-#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x00000040L
-#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x00000080L
-#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x00000100L
-#define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x00000200L
-#define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x00000400L
-#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x00000800L
-#define SQC_CONFIG__EVICT_LRU_MASK 0x00003000L
-#define SQC_CONFIG__FORCE_2_BANK_MASK 0x00004000L
-#define SQC_CONFIG__FORCE_1_BANK_MASK 0x00008000L
-#define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0x00FF0000L
-#define SQC_CONFIG__INST_PRF_COUNT_MASK 0x03000000L
-#define SQC_CONFIG__INST_PRF_FILTER_DIS_MASK 0x04000000L
-//LDS_CONFIG
-#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING__SHIFT 0x0
-#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING_MASK 0x00000001L
-//SQ_RANDOM_WAVE_PRI
-#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0
-#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7
-#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa
-#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x0000007FL
-#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x00000380L
-#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x007FFC00L
-//SQ_REG_CREDITS
-#define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x0
-#define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x8
-#define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x1c
-#define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x1d
-#define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x1e
-#define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x1f
-#define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x0000003FL
-#define SQ_REG_CREDITS__CMD_CREDITS_MASK 0x00000F00L
-#define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000L
-#define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000L
-#define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000L
-#define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000L
-//SQ_FIFO_SIZES
-#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0
-#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8
-#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x10
-#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12
-#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0x0000000FL
-#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0x00000F00L
-#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x00030000L
-#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0x000C0000L
-//SQ_DSM_CNTL
-#define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x0
-#define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x1
-#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2
-#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x3
-#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x8
-#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x9
-#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa
-#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x10
-#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x11
-#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x12
-#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x13
-#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14
-#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x15
-#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x18
-#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x19
-#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x1a
-#define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x00000001L
-#define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x00000002L
-#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x00000004L
-#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x00000008L
-#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x00000100L
-#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x00000200L
-#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x00000400L
-#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x00010000L
-#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x00020000L
-#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x00040000L
-#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x00080000L
-#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x00100000L
-#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x00200000L
-#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x01000000L
-#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x02000000L
-#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x04000000L
-//SQ_DSM_CNTL2
-#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY__SHIFT 0x2
-#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT__SHIFT 0x3
-#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY__SHIFT 0x5
-#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT__SHIFT 0x6
-#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY__SHIFT 0x8
-#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT__SHIFT 0x9
-#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY__SHIFT 0xb
-#define SQ_DSM_CNTL2__LDS_INJECT_DELAY__SHIFT 0xe
-#define SQ_DSM_CNTL2__SP_INJECT_DELAY__SHIFT 0x14
-#define SQ_DSM_CNTL2__SQ_INJECT_DELAY__SHIFT 0x1a
-#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT_MASK 0x00000018L
-#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY_MASK 0x00000020L
-#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT_MASK 0x000000C0L
-#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY_MASK 0x00000100L
-#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT_MASK 0x00000600L
-#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY_MASK 0x00000800L
-#define SQ_DSM_CNTL2__LDS_INJECT_DELAY_MASK 0x000FC000L
-#define SQ_DSM_CNTL2__SP_INJECT_DELAY_MASK 0x03F00000L
-#define SQ_DSM_CNTL2__SQ_INJECT_DELAY_MASK 0xFC000000L
-//SQ_RUNTIME_CONFIG
-#define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST__SHIFT 0x0
-#define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST_MASK 0x00000001L
-//SH_MEM_BASES
-#define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0
-#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10
-#define SH_MEM_BASES__PRIVATE_BASE_MASK 0x0000FFFFL
-#define SH_MEM_BASES__SHARED_BASE_MASK 0xFFFF0000L
-//SH_MEM_CONFIG
-#define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x0
-#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x3
-#define SH_MEM_CONFIG__RETRY_DISABLE__SHIFT 0xc
-#define SH_MEM_CONFIG__PRIVATE_NV__SHIFT 0xd
-#define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x00000001L
-#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x00000018L
-#define SH_MEM_CONFIG__RETRY_DISABLE_MASK 0x00001000L
-#define SH_MEM_CONFIG__PRIVATE_NV_MASK 0x00002000L
-//CC_GC_SHADER_RATE_CONFIG
-#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1
-#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3
-#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4
-#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L
-#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L
-#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L
-//GC_USER_SHADER_RATE_CONFIG
-#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1
-#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3
-#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4
-#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L
-#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L
-#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L
-//SQ_INTERRUPT_AUTO_MASK
-#define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0
-#define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0x00FFFFFFL
-//SQ_INTERRUPT_MSG_CTRL
-#define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0
-#define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x00000001L
-//SQ_UTCL1_CNTL1
-#define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
-#define SQ_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
-#define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
-#define SQ_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
-#define SQ_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
-#define SQ_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
-#define SQ_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10
-#define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
-#define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
-#define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13
-#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17
-#define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18
-#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL__SHIFT 0x19
-#define SQ_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
-#define SQ_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
-#define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
-#define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
-#define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
-#define SQ_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
-#define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
-#define SQ_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
-#define SQ_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
-#define SQ_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
-#define SQ_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L
-#define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
-#define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
-#define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L
-#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L
-#define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L
-#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_MASK 0x02000000L
-#define SQ_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
-#define SQ_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
-#define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
-#define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
-//SQ_UTCL1_CNTL2
-#define SQ_UTCL1_CNTL2__SPARE__SHIFT 0x0
-#define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8
-#define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
-#define SQ_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
-#define SQ_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb
-#define SQ_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
-#define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
-#define SQ_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
-#define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
-#define SQ_UTCL1_CNTL2__RETRY_TIMER__SHIFT 0x10
-#define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
-#define SQ_UTCL1_CNTL2__PREFETCH_PAGE__SHIFT 0x1c
-#define SQ_UTCL1_CNTL2__SPARE_MASK 0x000000FFL
-#define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L
-#define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
-#define SQ_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
-#define SQ_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L
-#define SQ_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
-#define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
-#define SQ_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
-#define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
-#define SQ_UTCL1_CNTL2__RETRY_TIMER_MASK 0x007F0000L
-#define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
-#define SQ_UTCL1_CNTL2__PREFETCH_PAGE_MASK 0xF0000000L
-//SQ_UTCL1_STATUS
-#define SQ_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
-#define SQ_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
-#define SQ_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
-#define SQ_UTCL1_STATUS__RESERVED__SHIFT 0x3
-#define SQ_UTCL1_STATUS__UNUSED__SHIFT 0x10
-#define SQ_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
-#define SQ_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
-#define SQ_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
-#define SQ_UTCL1_STATUS__RESERVED_MASK 0x0000FFF8L
-#define SQ_UTCL1_STATUS__UNUSED_MASK 0xFFFF0000L
-//SQ_SHADER_TBA_LO
-#define SQ_SHADER_TBA_LO__ADDR_LO__SHIFT 0x0
-#define SQ_SHADER_TBA_LO__ADDR_LO_MASK 0xFFFFFFFFL
-//SQ_SHADER_TBA_HI
-#define SQ_SHADER_TBA_HI__ADDR_HI__SHIFT 0x0
-#define SQ_SHADER_TBA_HI__ADDR_HI_MASK 0x000000FFL
-//SQ_SHADER_TMA_LO
-#define SQ_SHADER_TMA_LO__ADDR_LO__SHIFT 0x0
-#define SQ_SHADER_TMA_LO__ADDR_LO_MASK 0xFFFFFFFFL
-//SQ_SHADER_TMA_HI
-#define SQ_SHADER_TMA_HI__ADDR_HI__SHIFT 0x0
-#define SQ_SHADER_TMA_HI__ADDR_HI_MASK 0x000000FFL
-//SQC_DSM_CNTL
-#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x0
-#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x2
-#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x3
-#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x5
-#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x6
-#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8
-#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x9
-#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0xb
-#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0xc
-#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0xe
-#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0xf
-#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x11
-#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x12
-#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14
-#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00000003L
-#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000004L
-#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000018L
-#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000020L
-#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L
-#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L
-#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000600L
-#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000800L
-#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00003000L
-#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00004000L
-#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00018000L
-#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00020000L
-#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L
-#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L
-//SQC_DSM_CNTLA
-#define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0
-#define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x2
-#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x3
-#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x5
-#define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6
-#define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8
-#define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x9
-#define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb
-#define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0xc
-#define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xe
-#define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0xf
-#define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x11
-#define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x12
-#define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14
-#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x15
-#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x17
-#define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x18
-#define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x1a
-#define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L
-#define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
-#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L
-#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L
-#define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L
-#define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L
-#define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L
-#define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
-#define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L
-#define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
-#define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L
-#define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L
-#define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L
-#define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L
-#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L
-#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L
-#define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L
-#define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L
-//SQC_DSM_CNTLB
-#define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0
-#define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x2
-#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x3
-#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x5
-#define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6
-#define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8
-#define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x9
-#define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb
-#define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0xc
-#define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xe
-#define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0xf
-#define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x11
-#define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x12
-#define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14
-#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x15
-#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x17
-#define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x18
-#define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x1a
-#define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L
-#define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
-#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L
-#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L
-#define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L
-#define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L
-#define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L
-#define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
-#define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L
-#define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
-#define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L
-#define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L
-#define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L
-#define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L
-#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L
-#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L
-#define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L
-#define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L
-//SQC_DSM_CNTL2
-#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x2
-#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x3
-#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x5
-#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x6
-#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x8
-#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x9
-#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0xb
-#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0xc
-#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0xe
-#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0xf
-#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x11
-#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x12
-#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x14
-#define SQC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
-#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000018L
-#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000020L
-#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L
-#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000100L
-#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000600L
-#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000800L
-#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L
-#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00004000L
-#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00018000L
-#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00020000L
-#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L
-#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00100000L
-#define SQC_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
-//SQC_DSM_CNTL2A
-#define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x2
-#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x3
-#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x5
-#define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6
-#define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8
-#define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9
-#define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0xb
-#define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc
-#define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe
-#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xf
-#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x11
-#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x12
-#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x14
-#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15
-#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x17
-#define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18
-#define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a
-#define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L
-#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L
-#define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L
-#define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L
-#define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L
-#define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L
-#define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L
-#define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L
-#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L
-#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L
-#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L
-#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L
-#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L
-#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L
-#define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L
-#define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L
-//SQC_DSM_CNTL2B
-#define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x2
-#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x3
-#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x5
-#define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6
-#define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8
-#define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9
-#define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0xb
-#define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc
-#define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe
-#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xf
-#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x11
-#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x12
-#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x14
-#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15
-#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x17
-#define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18
-#define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a
-#define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L
-#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L
-#define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L
-#define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L
-#define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L
-#define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L
-#define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L
-#define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L
-#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L
-#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L
-#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L
-#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L
-#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L
-#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L
-#define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L
-#define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L
-//SQC_EDC_FUE_CNTL
-#define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x0
-#define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x10
-#define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000FFFFL
-#define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xFFFF0000L
-//SQC_EDC_CNT2
-#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x0
-#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT__SHIFT 0x2
-#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0x4
-#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT__SHIFT 0x6
-#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x8
-#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT__SHIFT 0xa
-#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0xc
-#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT__SHIFT 0xe
-#define SQC_EDC_CNT2__INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT__SHIFT 0x10
-#define SQC_EDC_CNT2__INST_BANKA_MISS_FIFO_SED_COUNT__SHIFT 0x12
-#define SQC_EDC_CNT2__DATA_BANKA_HIT_FIFO_SED_COUNT__SHIFT 0x14
-#define SQC_EDC_CNT2__DATA_BANKA_MISS_FIFO_SED_COUNT__SHIFT 0x16
-#define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT__SHIFT 0x18
-#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x1a
-#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT__SHIFT 0x1c
-#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000003L
-#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT_MASK 0x0000000CL
-#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00000030L
-#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT_MASK 0x000000C0L
-#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000300L
-#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT_MASK 0x00000C00L
-#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00003000L
-#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT_MASK 0x0000C000L
-#define SQC_EDC_CNT2__INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT_MASK 0x00030000L
-#define SQC_EDC_CNT2__INST_BANKA_MISS_FIFO_SED_COUNT_MASK 0x000C0000L
-#define SQC_EDC_CNT2__DATA_BANKA_HIT_FIFO_SED_COUNT_MASK 0x00300000L
-#define SQC_EDC_CNT2__DATA_BANKA_MISS_FIFO_SED_COUNT_MASK 0x00C00000L
-#define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT_MASK 0x03000000L
-#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT_MASK 0x0C000000L
-#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT_MASK 0x30000000L
-//SQC_EDC_CNT3
-#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x0
-#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT__SHIFT 0x2
-#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0x4
-#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT__SHIFT 0x6
-#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x8
-#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT__SHIFT 0xa
-#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0xc
-#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT__SHIFT 0xe
-#define SQC_EDC_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT__SHIFT 0x10
-#define SQC_EDC_CNT3__INST_BANKB_MISS_FIFO_SED_COUNT__SHIFT 0x12
-#define SQC_EDC_CNT3__DATA_BANKB_HIT_FIFO_SED_COUNT__SHIFT 0x14
-#define SQC_EDC_CNT3__DATA_BANKB_MISS_FIFO_SED_COUNT__SHIFT 0x16
-#define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT__SHIFT 0x18
-#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000003L
-#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT_MASK 0x0000000CL
-#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00000030L
-#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT_MASK 0x000000C0L
-#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000300L
-#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT_MASK 0x00000C00L
-#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00003000L
-#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT_MASK 0x0000C000L
-#define SQC_EDC_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT_MASK 0x00030000L
-#define SQC_EDC_CNT3__INST_BANKB_MISS_FIFO_SED_COUNT_MASK 0x000C0000L
-#define SQC_EDC_CNT3__DATA_BANKB_HIT_FIFO_SED_COUNT_MASK 0x00300000L
-#define SQC_EDC_CNT3__DATA_BANKB_MISS_FIFO_SED_COUNT_MASK 0x00C00000L
-#define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT_MASK 0x03000000L
-//SQ_REG_TIMESTAMP
-#define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT 0x0
-#define SQ_REG_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL
-//SQ_CMD_TIMESTAMP
-#define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0
-#define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL
-//SQ_IND_INDEX
-#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0
-#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4
-#define SQ_IND_INDEX__THREAD_ID__SHIFT 0x6
-#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xc
-#define SQ_IND_INDEX__FORCE_READ__SHIFT 0xd
-#define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0xe
-#define SQ_IND_INDEX__UNINDEXED__SHIFT 0xf
-#define SQ_IND_INDEX__INDEX__SHIFT 0x10
-#define SQ_IND_INDEX__WAVE_ID_MASK 0x0000000FL
-#define SQ_IND_INDEX__SIMD_ID_MASK 0x00000030L
-#define SQ_IND_INDEX__THREAD_ID_MASK 0x00000FC0L
-#define SQ_IND_INDEX__AUTO_INCR_MASK 0x00001000L
-#define SQ_IND_INDEX__FORCE_READ_MASK 0x00002000L
-#define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x00004000L
-#define SQ_IND_INDEX__UNINDEXED_MASK 0x00008000L
-#define SQ_IND_INDEX__INDEX_MASK 0xFFFF0000L
-//SQ_IND_DATA
-#define SQ_IND_DATA__DATA__SHIFT 0x0
-#define SQ_IND_DATA__DATA_MASK 0xFFFFFFFFL
-//SQ_CMD
-#define SQ_CMD__CMD__SHIFT 0x0
-#define SQ_CMD__MODE__SHIFT 0x4
-#define SQ_CMD__CHECK_VMID__SHIFT 0x7
-#define SQ_CMD__DATA__SHIFT 0x8
-#define SQ_CMD__WAVE_ID__SHIFT 0x10
-#define SQ_CMD__SIMD_ID__SHIFT 0x14
-#define SQ_CMD__QUEUE_ID__SHIFT 0x18
-#define SQ_CMD__VM_ID__SHIFT 0x1c
-#define SQ_CMD__CMD_MASK 0x00000007L
-#define SQ_CMD__MODE_MASK 0x00000070L
-#define SQ_CMD__CHECK_VMID_MASK 0x00000080L
-#define SQ_CMD__DATA_MASK 0x00000F00L
-#define SQ_CMD__WAVE_ID_MASK 0x000F0000L
-#define SQ_CMD__SIMD_ID_MASK 0x00300000L
-#define SQ_CMD__QUEUE_ID_MASK 0x07000000L
-#define SQ_CMD__VM_ID_MASK 0xF0000000L
-//SQ_TIME_HI
-#define SQ_TIME_HI__TIME__SHIFT 0x0
-#define SQ_TIME_HI__TIME_MASK 0xFFFFFFFFL
-//SQ_TIME_LO
-#define SQ_TIME_LO__TIME__SHIFT 0x0
-#define SQ_TIME_LO__TIME_MASK 0xFFFFFFFFL
-//SQ_DS_0
-#define SQ_DS_0__OFFSET0__SHIFT 0x0
-#define SQ_DS_0__OFFSET1__SHIFT 0x8
-#define SQ_DS_0__GDS__SHIFT 0x10
-#define SQ_DS_0__OP__SHIFT 0x11
-#define SQ_DS_0__ENCODING__SHIFT 0x1a
-#define SQ_DS_0__OFFSET0_MASK 0x000000FFL
-#define SQ_DS_0__OFFSET1_MASK 0x0000FF00L
-#define SQ_DS_0__GDS_MASK 0x00010000L
-#define SQ_DS_0__OP_MASK 0x01FE0000L
-#define SQ_DS_0__ENCODING_MASK 0xFC000000L
-//SQ_DS_1
-#define SQ_DS_1__ADDR__SHIFT 0x0
-#define SQ_DS_1__DATA0__SHIFT 0x8
-#define SQ_DS_1__DATA1__SHIFT 0x10
-#define SQ_DS_1__VDST__SHIFT 0x18
-#define SQ_DS_1__ADDR_MASK 0x000000FFL
-#define SQ_DS_1__DATA0_MASK 0x0000FF00L
-#define SQ_DS_1__DATA1_MASK 0x00FF0000L
-#define SQ_DS_1__VDST_MASK 0xFF000000L
-//SQ_EXP_0
-#define SQ_EXP_0__EN__SHIFT 0x0
-#define SQ_EXP_0__TGT__SHIFT 0x4
-#define SQ_EXP_0__COMPR__SHIFT 0xa
-#define SQ_EXP_0__DONE__SHIFT 0xb
-#define SQ_EXP_0__VM__SHIFT 0xc
-#define SQ_EXP_0__ENCODING__SHIFT 0x1a
-#define SQ_EXP_0__EN_MASK 0x0000000FL
-#define SQ_EXP_0__TGT_MASK 0x000003F0L
-#define SQ_EXP_0__COMPR_MASK 0x00000400L
-#define SQ_EXP_0__DONE_MASK 0x00000800L
-#define SQ_EXP_0__VM_MASK 0x00001000L
-#define SQ_EXP_0__ENCODING_MASK 0xFC000000L
-//SQ_EXP_1
-#define SQ_EXP_1__VSRC0__SHIFT 0x0
-#define SQ_EXP_1__VSRC1__SHIFT 0x8
-#define SQ_EXP_1__VSRC2__SHIFT 0x10
-#define SQ_EXP_1__VSRC3__SHIFT 0x18
-#define SQ_EXP_1__VSRC0_MASK 0x000000FFL
-#define SQ_EXP_1__VSRC1_MASK 0x0000FF00L
-#define SQ_EXP_1__VSRC2_MASK 0x00FF0000L
-#define SQ_EXP_1__VSRC3_MASK 0xFF000000L
-//SQ_FLAT_0
-#define SQ_FLAT_0__OFFSET__SHIFT 0x0
-#define SQ_FLAT_0__LDS__SHIFT 0xd
-#define SQ_FLAT_0__SEG__SHIFT 0xe
-#define SQ_FLAT_0__GLC__SHIFT 0x10
-#define SQ_FLAT_0__SLC__SHIFT 0x11
-#define SQ_FLAT_0__OP__SHIFT 0x12
-#define SQ_FLAT_0__ENCODING__SHIFT 0x1a
-#define SQ_FLAT_0__OFFSET_MASK 0x00000FFFL
-#define SQ_FLAT_0__LDS_MASK 0x00002000L
-#define SQ_FLAT_0__SEG_MASK 0x0000C000L
-#define SQ_FLAT_0__GLC_MASK 0x00010000L
-#define SQ_FLAT_0__SLC_MASK 0x00020000L
-#define SQ_FLAT_0__OP_MASK 0x01FC0000L
-#define SQ_FLAT_0__ENCODING_MASK 0xFC000000L
-//SQ_FLAT_1
-#define SQ_FLAT_1__ADDR__SHIFT 0x0
-#define SQ_FLAT_1__DATA__SHIFT 0x8
-#define SQ_FLAT_1__SADDR__SHIFT 0x10
-#define SQ_FLAT_1__NV__SHIFT 0x17
-#define SQ_FLAT_1__VDST__SHIFT 0x18
-#define SQ_FLAT_1__ADDR_MASK 0x000000FFL
-#define SQ_FLAT_1__DATA_MASK 0x0000FF00L
-#define SQ_FLAT_1__SADDR_MASK 0x007F0000L
-#define SQ_FLAT_1__NV_MASK 0x00800000L
-#define SQ_FLAT_1__VDST_MASK 0xFF000000L
-//SQ_GLBL_0
-#define SQ_GLBL_0__OFFSET__SHIFT 0x0
-#define SQ_GLBL_0__LDS__SHIFT 0xd
-#define SQ_GLBL_0__SEG__SHIFT 0xe
-#define SQ_GLBL_0__GLC__SHIFT 0x10
-#define SQ_GLBL_0__SLC__SHIFT 0x11
-#define SQ_GLBL_0__OP__SHIFT 0x12
-#define SQ_GLBL_0__ENCODING__SHIFT 0x1a
-#define SQ_GLBL_0__OFFSET_MASK 0x00001FFFL
-#define SQ_GLBL_0__LDS_MASK 0x00002000L
-#define SQ_GLBL_0__SEG_MASK 0x0000C000L
-#define SQ_GLBL_0__GLC_MASK 0x00010000L
-#define SQ_GLBL_0__SLC_MASK 0x00020000L
-#define SQ_GLBL_0__OP_MASK 0x01FC0000L
-#define SQ_GLBL_0__ENCODING_MASK 0xFC000000L
-//SQ_GLBL_1
-#define SQ_GLBL_1__ADDR__SHIFT 0x0
-#define SQ_GLBL_1__DATA__SHIFT 0x8
-#define SQ_GLBL_1__SADDR__SHIFT 0x10
-#define SQ_GLBL_1__NV__SHIFT 0x17
-#define SQ_GLBL_1__VDST__SHIFT 0x18
-#define SQ_GLBL_1__ADDR_MASK 0x000000FFL
-#define SQ_GLBL_1__DATA_MASK 0x0000FF00L
-#define SQ_GLBL_1__SADDR_MASK 0x007F0000L
-#define SQ_GLBL_1__NV_MASK 0x00800000L
-#define SQ_GLBL_1__VDST_MASK 0xFF000000L
-//SQ_INST
-#define SQ_INST__ENCODING__SHIFT 0x0
-#define SQ_INST__ENCODING_MASK 0xFFFFFFFFL
-//SQ_MIMG_0
-#define SQ_MIMG_0__OPM__SHIFT 0x0
-#define SQ_MIMG_0__DMASK__SHIFT 0x8
-#define SQ_MIMG_0__UNORM__SHIFT 0xc
-#define SQ_MIMG_0__GLC__SHIFT 0xd
-#define SQ_MIMG_0__DA__SHIFT 0xe
-#define SQ_MIMG_0__A16__SHIFT 0xf
-#define SQ_MIMG_0__TFE__SHIFT 0x10
-#define SQ_MIMG_0__LWE__SHIFT 0x11
-#define SQ_MIMG_0__OP__SHIFT 0x12
-#define SQ_MIMG_0__SLC__SHIFT 0x19
-#define SQ_MIMG_0__ENCODING__SHIFT 0x1a
-#define SQ_MIMG_0__OPM_MASK 0x00000001L
-#define SQ_MIMG_0__DMASK_MASK 0x00000F00L
-#define SQ_MIMG_0__UNORM_MASK 0x00001000L
-#define SQ_MIMG_0__GLC_MASK 0x00002000L
-#define SQ_MIMG_0__DA_MASK 0x00004000L
-#define SQ_MIMG_0__A16_MASK 0x00008000L
-#define SQ_MIMG_0__TFE_MASK 0x00010000L
-#define SQ_MIMG_0__LWE_MASK 0x00020000L
-#define SQ_MIMG_0__OP_MASK 0x01FC0000L
-#define SQ_MIMG_0__SLC_MASK 0x02000000L
-#define SQ_MIMG_0__ENCODING_MASK 0xFC000000L
-//SQ_MIMG_1
-#define SQ_MIMG_1__VADDR__SHIFT 0x0
-#define SQ_MIMG_1__VDATA__SHIFT 0x8
-#define SQ_MIMG_1__SRSRC__SHIFT 0x10
-#define SQ_MIMG_1__SSAMP__SHIFT 0x15
-#define SQ_MIMG_1__D16__SHIFT 0x1f
-#define SQ_MIMG_1__VADDR_MASK 0x000000FFL
-#define SQ_MIMG_1__VDATA_MASK 0x0000FF00L
-#define SQ_MIMG_1__SRSRC_MASK 0x001F0000L
-#define SQ_MIMG_1__SSAMP_MASK 0x03E00000L
-#define SQ_MIMG_1__D16_MASK 0x80000000L
-//SQ_MTBUF_0
-#define SQ_MTBUF_0__OFFSET__SHIFT 0x0
-#define SQ_MTBUF_0__OFFEN__SHIFT 0xc
-#define SQ_MTBUF_0__IDXEN__SHIFT 0xd
-#define SQ_MTBUF_0__GLC__SHIFT 0xe
-#define SQ_MTBUF_0__OP__SHIFT 0xf
-#define SQ_MTBUF_0__DFMT__SHIFT 0x13
-#define SQ_MTBUF_0__NFMT__SHIFT 0x17
-#define SQ_MTBUF_0__ENCODING__SHIFT 0x1a
-#define SQ_MTBUF_0__OFFSET_MASK 0x00000FFFL
-#define SQ_MTBUF_0__OFFEN_MASK 0x00001000L
-#define SQ_MTBUF_0__IDXEN_MASK 0x00002000L
-#define SQ_MTBUF_0__GLC_MASK 0x00004000L
-#define SQ_MTBUF_0__OP_MASK 0x00078000L
-#define SQ_MTBUF_0__DFMT_MASK 0x00780000L
-#define SQ_MTBUF_0__NFMT_MASK 0x03800000L
-#define SQ_MTBUF_0__ENCODING_MASK 0xFC000000L
-//SQ_MTBUF_1
-#define SQ_MTBUF_1__VADDR__SHIFT 0x0
-#define SQ_MTBUF_1__VDATA__SHIFT 0x8
-#define SQ_MTBUF_1__SRSRC__SHIFT 0x10
-#define SQ_MTBUF_1__SLC__SHIFT 0x16
-#define SQ_MTBUF_1__TFE__SHIFT 0x17
-#define SQ_MTBUF_1__SOFFSET__SHIFT 0x18
-#define SQ_MTBUF_1__VADDR_MASK 0x000000FFL
-#define SQ_MTBUF_1__VDATA_MASK 0x0000FF00L
-#define SQ_MTBUF_1__SRSRC_MASK 0x001F0000L
-#define SQ_MTBUF_1__SLC_MASK 0x00400000L
-#define SQ_MTBUF_1__TFE_MASK 0x00800000L
-#define SQ_MTBUF_1__SOFFSET_MASK 0xFF000000L
-//SQ_MUBUF_0
-#define SQ_MUBUF_0__OFFSET__SHIFT 0x0
-#define SQ_MUBUF_0__OFFEN__SHIFT 0xc
-#define SQ_MUBUF_0__IDXEN__SHIFT 0xd
-#define SQ_MUBUF_0__GLC__SHIFT 0xe
-#define SQ_MUBUF_0__LDS__SHIFT 0x10
-#define SQ_MUBUF_0__SLC__SHIFT 0x11
-#define SQ_MUBUF_0__OP__SHIFT 0x12
-#define SQ_MUBUF_0__ENCODING__SHIFT 0x1a
-#define SQ_MUBUF_0__OFFSET_MASK 0x00000FFFL
-#define SQ_MUBUF_0__OFFEN_MASK 0x00001000L
-#define SQ_MUBUF_0__IDXEN_MASK 0x00002000L
-#define SQ_MUBUF_0__GLC_MASK 0x00004000L
-#define SQ_MUBUF_0__LDS_MASK 0x00010000L
-#define SQ_MUBUF_0__SLC_MASK 0x00020000L
-#define SQ_MUBUF_0__OP_MASK 0x01FC0000L
-#define SQ_MUBUF_0__ENCODING_MASK 0xFC000000L
-//SQ_MUBUF_1
-#define SQ_MUBUF_1__VADDR__SHIFT 0x0
-#define SQ_MUBUF_1__VDATA__SHIFT 0x8
-#define SQ_MUBUF_1__SRSRC__SHIFT 0x10
-#define SQ_MUBUF_1__TFE__SHIFT 0x17
-#define SQ_MUBUF_1__SOFFSET__SHIFT 0x18
-#define SQ_MUBUF_1__VADDR_MASK 0x000000FFL
-#define SQ_MUBUF_1__VDATA_MASK 0x0000FF00L
-#define SQ_MUBUF_1__SRSRC_MASK 0x001F0000L
-#define SQ_MUBUF_1__TFE_MASK 0x00800000L
-#define SQ_MUBUF_1__SOFFSET_MASK 0xFF000000L
-//SQ_SCRATCH_0
-#define SQ_SCRATCH_0__OFFSET__SHIFT 0x0
-#define SQ_SCRATCH_0__LDS__SHIFT 0xd
-#define SQ_SCRATCH_0__SEG__SHIFT 0xe
-#define SQ_SCRATCH_0__GLC__SHIFT 0x10
-#define SQ_SCRATCH_0__SLC__SHIFT 0x11
-#define SQ_SCRATCH_0__OP__SHIFT 0x12
-#define SQ_SCRATCH_0__ENCODING__SHIFT 0x1a
-#define SQ_SCRATCH_0__OFFSET_MASK 0x00001FFFL
-#define SQ_SCRATCH_0__LDS_MASK 0x00002000L
-#define SQ_SCRATCH_0__SEG_MASK 0x0000C000L
-#define SQ_SCRATCH_0__GLC_MASK 0x00010000L
-#define SQ_SCRATCH_0__SLC_MASK 0x00020000L
-#define SQ_SCRATCH_0__OP_MASK 0x01FC0000L
-#define SQ_SCRATCH_0__ENCODING_MASK 0xFC000000L
-//SQ_SCRATCH_1
-#define SQ_SCRATCH_1__ADDR__SHIFT 0x0
-#define SQ_SCRATCH_1__DATA__SHIFT 0x8
-#define SQ_SCRATCH_1__SADDR__SHIFT 0x10
-#define SQ_SCRATCH_1__NV__SHIFT 0x17
-#define SQ_SCRATCH_1__VDST__SHIFT 0x18
-#define SQ_SCRATCH_1__ADDR_MASK 0x000000FFL
-#define SQ_SCRATCH_1__DATA_MASK 0x0000FF00L
-#define SQ_SCRATCH_1__SADDR_MASK 0x007F0000L
-#define SQ_SCRATCH_1__NV_MASK 0x00800000L
-#define SQ_SCRATCH_1__VDST_MASK 0xFF000000L
-//SQ_SMEM_0
-#define SQ_SMEM_0__SBASE__SHIFT 0x0
-#define SQ_SMEM_0__SDATA__SHIFT 0x6
-#define SQ_SMEM_0__SOFFSET_EN__SHIFT 0xe
-#define SQ_SMEM_0__NV__SHIFT 0xf
-#define SQ_SMEM_0__GLC__SHIFT 0x10
-#define SQ_SMEM_0__IMM__SHIFT 0x11
-#define SQ_SMEM_0__OP__SHIFT 0x12
-#define SQ_SMEM_0__ENCODING__SHIFT 0x1a
-#define SQ_SMEM_0__SBASE_MASK 0x0000003FL
-#define SQ_SMEM_0__SDATA_MASK 0x00001FC0L
-#define SQ_SMEM_0__SOFFSET_EN_MASK 0x00004000L
-#define SQ_SMEM_0__NV_MASK 0x00008000L
-#define SQ_SMEM_0__GLC_MASK 0x00010000L
-#define SQ_SMEM_0__IMM_MASK 0x00020000L
-#define SQ_SMEM_0__OP_MASK 0x03FC0000L
-#define SQ_SMEM_0__ENCODING_MASK 0xFC000000L
-//SQ_SMEM_1
-#define SQ_SMEM_1__OFFSET__SHIFT 0x0
-#define SQ_SMEM_1__SOFFSET__SHIFT 0x19
-#define SQ_SMEM_1__OFFSET_MASK 0x001FFFFFL
-#define SQ_SMEM_1__SOFFSET_MASK 0xFE000000L
-//SQ_SOP1
-#define SQ_SOP1__SSRC0__SHIFT 0x0
-#define SQ_SOP1__OP__SHIFT 0x8
-#define SQ_SOP1__SDST__SHIFT 0x10
-#define SQ_SOP1__ENCODING__SHIFT 0x17
-#define SQ_SOP1__SSRC0_MASK 0x000000FFL
-#define SQ_SOP1__OP_MASK 0x0000FF00L
-#define SQ_SOP1__SDST_MASK 0x007F0000L
-#define SQ_SOP1__ENCODING_MASK 0xFF800000L
-//SQ_SOP2
-#define SQ_SOP2__SSRC0__SHIFT 0x0
-#define SQ_SOP2__SSRC1__SHIFT 0x8
-#define SQ_SOP2__SDST__SHIFT 0x10
-#define SQ_SOP2__OP__SHIFT 0x17
-#define SQ_SOP2__ENCODING__SHIFT 0x1e
-#define SQ_SOP2__SSRC0_MASK 0x000000FFL
-#define SQ_SOP2__SSRC1_MASK 0x0000FF00L
-#define SQ_SOP2__SDST_MASK 0x007F0000L
-#define SQ_SOP2__OP_MASK 0x3F800000L
-#define SQ_SOP2__ENCODING_MASK 0xC0000000L
-//SQ_SOPC
-#define SQ_SOPC__SSRC0__SHIFT 0x0
-#define SQ_SOPC__SSRC1__SHIFT 0x8
-#define SQ_SOPC__OP__SHIFT 0x10
-#define SQ_SOPC__ENCODING__SHIFT 0x17
-#define SQ_SOPC__SSRC0_MASK 0x000000FFL
-#define SQ_SOPC__SSRC1_MASK 0x0000FF00L
-#define SQ_SOPC__OP_MASK 0x007F0000L
-#define SQ_SOPC__ENCODING_MASK 0xFF800000L
-//SQ_SOPK
-#define SQ_SOPK__SIMM16__SHIFT 0x0
-#define SQ_SOPK__SDST__SHIFT 0x10
-#define SQ_SOPK__OP__SHIFT 0x17
-#define SQ_SOPK__ENCODING__SHIFT 0x1c
-#define SQ_SOPK__SIMM16_MASK 0x0000FFFFL
-#define SQ_SOPK__SDST_MASK 0x007F0000L
-#define SQ_SOPK__OP_MASK 0x0F800000L
-#define SQ_SOPK__ENCODING_MASK 0xF0000000L
-//SQ_SOPP
-#define SQ_SOPP__SIMM16__SHIFT 0x0
-#define SQ_SOPP__OP__SHIFT 0x10
-#define SQ_SOPP__ENCODING__SHIFT 0x17
-#define SQ_SOPP__SIMM16_MASK 0x0000FFFFL
-#define SQ_SOPP__OP_MASK 0x007F0000L
-#define SQ_SOPP__ENCODING_MASK 0xFF800000L
-//SQ_VINTRP
-#define SQ_VINTRP__VSRC__SHIFT 0x0
-#define SQ_VINTRP__ATTRCHAN__SHIFT 0x8
-#define SQ_VINTRP__ATTR__SHIFT 0xa
-#define SQ_VINTRP__OP__SHIFT 0x10
-#define SQ_VINTRP__VDST__SHIFT 0x12
-#define SQ_VINTRP__ENCODING__SHIFT 0x1a
-#define SQ_VINTRP__VSRC_MASK 0x000000FFL
-#define SQ_VINTRP__ATTRCHAN_MASK 0x00000300L
-#define SQ_VINTRP__ATTR_MASK 0x0000FC00L
-#define SQ_VINTRP__OP_MASK 0x00030000L
-#define SQ_VINTRP__VDST_MASK 0x03FC0000L
-#define SQ_VINTRP__ENCODING_MASK 0xFC000000L
-//SQ_VOP1
-#define SQ_VOP1__SRC0__SHIFT 0x0
-#define SQ_VOP1__OP__SHIFT 0x9
-#define SQ_VOP1__VDST__SHIFT 0x11
-#define SQ_VOP1__ENCODING__SHIFT 0x19
-#define SQ_VOP1__SRC0_MASK 0x000001FFL
-#define SQ_VOP1__OP_MASK 0x0001FE00L
-#define SQ_VOP1__VDST_MASK 0x01FE0000L
-#define SQ_VOP1__ENCODING_MASK 0xFE000000L
-//SQ_VOP2
-#define SQ_VOP2__SRC0__SHIFT 0x0
-#define SQ_VOP2__VSRC1__SHIFT 0x9
-#define SQ_VOP2__VDST__SHIFT 0x11
-#define SQ_VOP2__OP__SHIFT 0x19
-#define SQ_VOP2__ENCODING__SHIFT 0x1f
-#define SQ_VOP2__SRC0_MASK 0x000001FFL
-#define SQ_VOP2__VSRC1_MASK 0x0001FE00L
-#define SQ_VOP2__VDST_MASK 0x01FE0000L
-#define SQ_VOP2__OP_MASK 0x7E000000L
-#define SQ_VOP2__ENCODING_MASK 0x80000000L
-//SQ_VOP3P_0
-#define SQ_VOP3P_0__VDST__SHIFT 0x0
-#define SQ_VOP3P_0__NEG_HI__SHIFT 0x8
-#define SQ_VOP3P_0__OP_SEL__SHIFT 0xb
-#define SQ_VOP3P_0__OP_SEL_HI_2__SHIFT 0xe
-#define SQ_VOP3P_0__CLAMP__SHIFT 0xf
-#define SQ_VOP3P_0__OP__SHIFT 0x10
-#define SQ_VOP3P_0__ENCODING__SHIFT 0x17
-#define SQ_VOP3P_0__VDST_MASK 0x000000FFL
-#define SQ_VOP3P_0__NEG_HI_MASK 0x00000700L
-#define SQ_VOP3P_0__OP_SEL_MASK 0x00003800L
-#define SQ_VOP3P_0__OP_SEL_HI_2_MASK 0x00004000L
-#define SQ_VOP3P_0__CLAMP_MASK 0x00008000L
-#define SQ_VOP3P_0__OP_MASK 0x007F0000L
-#define SQ_VOP3P_0__ENCODING_MASK 0xFF800000L
-//SQ_VOP3P_1
-#define SQ_VOP3P_1__SRC0__SHIFT 0x0
-#define SQ_VOP3P_1__SRC1__SHIFT 0x9
-#define SQ_VOP3P_1__SRC2__SHIFT 0x12
-#define SQ_VOP3P_1__OP_SEL_HI__SHIFT 0x1b
-#define SQ_VOP3P_1__NEG__SHIFT 0x1d
-#define SQ_VOP3P_1__SRC0_MASK 0x000001FFL
-#define SQ_VOP3P_1__SRC1_MASK 0x0003FE00L
-#define SQ_VOP3P_1__SRC2_MASK 0x07FC0000L
-#define SQ_VOP3P_1__OP_SEL_HI_MASK 0x18000000L
-#define SQ_VOP3P_1__NEG_MASK 0xE0000000L
-//SQ_VOP3_0
-#define SQ_VOP3_0__VDST__SHIFT 0x0
-#define SQ_VOP3_0__ABS__SHIFT 0x8
-#define SQ_VOP3_0__OP_SEL__SHIFT 0xb
-#define SQ_VOP3_0__CLAMP__SHIFT 0xf
-#define SQ_VOP3_0__OP__SHIFT 0x10
-#define SQ_VOP3_0__ENCODING__SHIFT 0x1a
-#define SQ_VOP3_0__VDST_MASK 0x000000FFL
-#define SQ_VOP3_0__ABS_MASK 0x00000700L
-#define SQ_VOP3_0__OP_SEL_MASK 0x00007800L
-#define SQ_VOP3_0__CLAMP_MASK 0x00008000L
-#define SQ_VOP3_0__OP_MASK 0x03FF0000L
-#define SQ_VOP3_0__ENCODING_MASK 0xFC000000L
-//SQ_VOP3_0_SDST_ENC
-#define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x0
-#define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x8
-#define SQ_VOP3_0_SDST_ENC__CLAMP__SHIFT 0xf
-#define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x10
-#define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x1a
-#define SQ_VOP3_0_SDST_ENC__VDST_MASK 0x000000FFL
-#define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x00007F00L
-#define SQ_VOP3_0_SDST_ENC__CLAMP_MASK 0x00008000L
-#define SQ_VOP3_0_SDST_ENC__OP_MASK 0x03FF0000L
-#define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xFC000000L
-//SQ_VOP3_1
-#define SQ_VOP3_1__SRC0__SHIFT 0x0
-#define SQ_VOP3_1__SRC1__SHIFT 0x9
-#define SQ_VOP3_1__SRC2__SHIFT 0x12
-#define SQ_VOP3_1__OMOD__SHIFT 0x1b
-#define SQ_VOP3_1__NEG__SHIFT 0x1d
-#define SQ_VOP3_1__SRC0_MASK 0x000001FFL
-#define SQ_VOP3_1__SRC1_MASK 0x0003FE00L
-#define SQ_VOP3_1__SRC2_MASK 0x07FC0000L
-#define SQ_VOP3_1__OMOD_MASK 0x18000000L
-#define SQ_VOP3_1__NEG_MASK 0xE0000000L
-//SQ_VOPC
-#define SQ_VOPC__SRC0__SHIFT 0x0
-#define SQ_VOPC__VSRC1__SHIFT 0x9
-#define SQ_VOPC__OP__SHIFT 0x11
-#define SQ_VOPC__ENCODING__SHIFT 0x19
-#define SQ_VOPC__SRC0_MASK 0x000001FFL
-#define SQ_VOPC__VSRC1_MASK 0x0001FE00L
-#define SQ_VOPC__OP_MASK 0x01FE0000L
-#define SQ_VOPC__ENCODING_MASK 0xFE000000L
-//SQ_VOP_DPP
-#define SQ_VOP_DPP__SRC0__SHIFT 0x0
-#define SQ_VOP_DPP__DPP_CTRL__SHIFT 0x8
-#define SQ_VOP_DPP__BOUND_CTRL__SHIFT 0x13
-#define SQ_VOP_DPP__SRC0_NEG__SHIFT 0x14
-#define SQ_VOP_DPP__SRC0_ABS__SHIFT 0x15
-#define SQ_VOP_DPP__SRC1_NEG__SHIFT 0x16
-#define SQ_VOP_DPP__SRC1_ABS__SHIFT 0x17
-#define SQ_VOP_DPP__BANK_MASK__SHIFT 0x18
-#define SQ_VOP_DPP__ROW_MASK__SHIFT 0x1c
-#define SQ_VOP_DPP__SRC0_MASK 0x000000FFL
-#define SQ_VOP_DPP__DPP_CTRL_MASK 0x0001FF00L
-#define SQ_VOP_DPP__BOUND_CTRL_MASK 0x00080000L
-#define SQ_VOP_DPP__SRC0_NEG_MASK 0x00100000L
-#define SQ_VOP_DPP__SRC0_ABS_MASK 0x00200000L
-#define SQ_VOP_DPP__SRC1_NEG_MASK 0x00400000L
-#define SQ_VOP_DPP__SRC1_ABS_MASK 0x00800000L
-#define SQ_VOP_DPP__BANK_MASK_MASK 0x0F000000L
-#define SQ_VOP_DPP__ROW_MASK_MASK 0xF0000000L
-//SQ_VOP_SDWA
-#define SQ_VOP_SDWA__SRC0__SHIFT 0x0
-#define SQ_VOP_SDWA__DST_SEL__SHIFT 0x8
-#define SQ_VOP_SDWA__DST_UNUSED__SHIFT 0xb
-#define SQ_VOP_SDWA__CLAMP__SHIFT 0xd
-#define SQ_VOP_SDWA__OMOD__SHIFT 0xe
-#define SQ_VOP_SDWA__SRC0_SEL__SHIFT 0x10
-#define SQ_VOP_SDWA__SRC0_SEXT__SHIFT 0x13
-#define SQ_VOP_SDWA__SRC0_NEG__SHIFT 0x14
-#define SQ_VOP_SDWA__SRC0_ABS__SHIFT 0x15
-#define SQ_VOP_SDWA__S0__SHIFT 0x17
-#define SQ_VOP_SDWA__SRC1_SEL__SHIFT 0x18
-#define SQ_VOP_SDWA__SRC1_SEXT__SHIFT 0x1b
-#define SQ_VOP_SDWA__SRC1_NEG__SHIFT 0x1c
-#define SQ_VOP_SDWA__SRC1_ABS__SHIFT 0x1d
-#define SQ_VOP_SDWA__S1__SHIFT 0x1f
-#define SQ_VOP_SDWA__SRC0_MASK 0x000000FFL
-#define SQ_VOP_SDWA__DST_SEL_MASK 0x00000700L
-#define SQ_VOP_SDWA__DST_UNUSED_MASK 0x00001800L
-#define SQ_VOP_SDWA__CLAMP_MASK 0x00002000L
-#define SQ_VOP_SDWA__OMOD_MASK 0x0000C000L
-#define SQ_VOP_SDWA__SRC0_SEL_MASK 0x00070000L
-#define SQ_VOP_SDWA__SRC0_SEXT_MASK 0x00080000L
-#define SQ_VOP_SDWA__SRC0_NEG_MASK 0x00100000L
-#define SQ_VOP_SDWA__SRC0_ABS_MASK 0x00200000L
-#define SQ_VOP_SDWA__S0_MASK 0x00800000L
-#define SQ_VOP_SDWA__SRC1_SEL_MASK 0x07000000L
-#define SQ_VOP_SDWA__SRC1_SEXT_MASK 0x08000000L
-#define SQ_VOP_SDWA__SRC1_NEG_MASK 0x10000000L
-#define SQ_VOP_SDWA__SRC1_ABS_MASK 0x20000000L
-#define SQ_VOP_SDWA__S1_MASK 0x80000000L
-//SQ_VOP_SDWA_SDST_ENC
-#define SQ_VOP_SDWA_SDST_ENC__SRC0__SHIFT 0x0
-#define SQ_VOP_SDWA_SDST_ENC__SDST__SHIFT 0x8
-#define SQ_VOP_SDWA_SDST_ENC__SD__SHIFT 0xf
-#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL__SHIFT 0x10
-#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT__SHIFT 0x13
-#define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG__SHIFT 0x14
-#define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS__SHIFT 0x15
-#define SQ_VOP_SDWA_SDST_ENC__S0__SHIFT 0x17
-#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL__SHIFT 0x18
-#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT__SHIFT 0x1b
-#define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG__SHIFT 0x1c
-#define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS__SHIFT 0x1d
-#define SQ_VOP_SDWA_SDST_ENC__S1__SHIFT 0x1f
-#define SQ_VOP_SDWA_SDST_ENC__SRC0_MASK 0x000000FFL
-#define SQ_VOP_SDWA_SDST_ENC__SDST_MASK 0x00007F00L
-#define SQ_VOP_SDWA_SDST_ENC__SD_MASK 0x00008000L
-#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL_MASK 0x00070000L
-#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT_MASK 0x00080000L
-#define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG_MASK 0x00100000L
-#define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS_MASK 0x00200000L
-#define SQ_VOP_SDWA_SDST_ENC__S0_MASK 0x00800000L
-#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL_MASK 0x07000000L
-#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT_MASK 0x08000000L
-#define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG_MASK 0x10000000L
-#define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS_MASK 0x20000000L
-#define SQ_VOP_SDWA_SDST_ENC__S1_MASK 0x80000000L
-//SQ_LB_CTR_CTRL
-#define SQ_LB_CTR_CTRL__START__SHIFT 0x0
-#define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1
-#define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2
-#define SQ_LB_CTR_CTRL__START_MASK 0x00000001L
-#define SQ_LB_CTR_CTRL__LOAD_MASK 0x00000002L
-#define SQ_LB_CTR_CTRL__CLEAR_MASK 0x00000004L
-//SQ_LB_DATA0
-#define SQ_LB_DATA0__DATA__SHIFT 0x0
-#define SQ_LB_DATA0__DATA_MASK 0xFFFFFFFFL
-//SQ_LB_DATA1
-#define SQ_LB_DATA1__DATA__SHIFT 0x0
-#define SQ_LB_DATA1__DATA_MASK 0xFFFFFFFFL
-//SQ_LB_DATA2
-#define SQ_LB_DATA2__DATA__SHIFT 0x0
-#define SQ_LB_DATA2__DATA_MASK 0xFFFFFFFFL
-//SQ_LB_DATA3
-#define SQ_LB_DATA3__DATA__SHIFT 0x0
-#define SQ_LB_DATA3__DATA_MASK 0xFFFFFFFFL
-//SQ_LB_CTR_SEL
-#define SQ_LB_CTR_SEL__SEL0__SHIFT 0x0
-#define SQ_LB_CTR_SEL__SEL1__SHIFT 0x4
-#define SQ_LB_CTR_SEL__SEL2__SHIFT 0x8
-#define SQ_LB_CTR_SEL__SEL3__SHIFT 0xc
-#define SQ_LB_CTR_SEL__SEL0_MASK 0x0000000FL
-#define SQ_LB_CTR_SEL__SEL1_MASK 0x000000F0L
-#define SQ_LB_CTR_SEL__SEL2_MASK 0x00000F00L
-#define SQ_LB_CTR_SEL__SEL3_MASK 0x0000F000L
-//SQ_LB_CTR0_CU
-#define SQ_LB_CTR0_CU__SH0_MASK__SHIFT 0x0
-#define SQ_LB_CTR0_CU__SH1_MASK__SHIFT 0x10
-#define SQ_LB_CTR0_CU__SH0_MASK_MASK 0x0000FFFFL
-#define SQ_LB_CTR0_CU__SH1_MASK_MASK 0xFFFF0000L
-//SQ_LB_CTR1_CU
-#define SQ_LB_CTR1_CU__SH0_MASK__SHIFT 0x0
-#define SQ_LB_CTR1_CU__SH1_MASK__SHIFT 0x10
-#define SQ_LB_CTR1_CU__SH0_MASK_MASK 0x0000FFFFL
-#define SQ_LB_CTR1_CU__SH1_MASK_MASK 0xFFFF0000L
-//SQ_LB_CTR2_CU
-#define SQ_LB_CTR2_CU__SH0_MASK__SHIFT 0x0
-#define SQ_LB_CTR2_CU__SH1_MASK__SHIFT 0x10
-#define SQ_LB_CTR2_CU__SH0_MASK_MASK 0x0000FFFFL
-#define SQ_LB_CTR2_CU__SH1_MASK_MASK 0xFFFF0000L
-//SQ_LB_CTR3_CU
-#define SQ_LB_CTR3_CU__SH0_MASK__SHIFT 0x0
-#define SQ_LB_CTR3_CU__SH1_MASK__SHIFT 0x10
-#define SQ_LB_CTR3_CU__SH0_MASK_MASK 0x0000FFFFL
-#define SQ_LB_CTR3_CU__SH1_MASK_MASK 0xFFFF0000L
-//SQC_EDC_CNT
-#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x0
-#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x2
-#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x4
-#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT__SHIFT 0x6
-#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x8
-#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT__SHIFT 0xa
-#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT__SHIFT 0xc
-#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT__SHIFT 0xe
-#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x10
-#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x12
-#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x14
-#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT__SHIFT 0x16
-#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x18
-#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x1a
-#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x1c
-#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT__SHIFT 0x1e
-#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000003L
-#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT_MASK 0x0000000CL
-#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT_MASK 0x00000030L
-#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT_MASK 0x000000C0L
-#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000300L
-#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT_MASK 0x00000C00L
-#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT_MASK 0x00003000L
-#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT_MASK 0x0000C000L
-#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00030000L
-#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT_MASK 0x000C0000L
-#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT_MASK 0x00300000L
-#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT_MASK 0x00C00000L
-#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT_MASK 0x03000000L
-#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT_MASK 0x0C000000L
-#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT_MASK 0x30000000L
-#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT_MASK 0xC0000000L
-//SQ_EDC_SEC_CNT
-#define SQ_EDC_SEC_CNT__LDS_SEC__SHIFT 0x0
-#define SQ_EDC_SEC_CNT__SGPR_SEC__SHIFT 0x8
-#define SQ_EDC_SEC_CNT__VGPR_SEC__SHIFT 0x10
-#define SQ_EDC_SEC_CNT__LDS_SEC_MASK 0x000000FFL
-#define SQ_EDC_SEC_CNT__SGPR_SEC_MASK 0x0000FF00L
-#define SQ_EDC_SEC_CNT__VGPR_SEC_MASK 0x00FF0000L
-//SQ_EDC_DED_CNT
-#define SQ_EDC_DED_CNT__LDS_DED__SHIFT 0x0
-#define SQ_EDC_DED_CNT__SGPR_DED__SHIFT 0x8
-#define SQ_EDC_DED_CNT__VGPR_DED__SHIFT 0x10
-#define SQ_EDC_DED_CNT__LDS_DED_MASK 0x000000FFL
-#define SQ_EDC_DED_CNT__SGPR_DED_MASK 0x0000FF00L
-#define SQ_EDC_DED_CNT__VGPR_DED_MASK 0x00FF0000L
-//SQ_EDC_INFO
-#define SQ_EDC_INFO__WAVE_ID__SHIFT 0x0
-#define SQ_EDC_INFO__SIMD_ID__SHIFT 0x4
-#define SQ_EDC_INFO__SOURCE__SHIFT 0x6
-#define SQ_EDC_INFO__VM_ID__SHIFT 0x9
-#define SQ_EDC_INFO__WAVE_ID_MASK 0x0000000FL
-#define SQ_EDC_INFO__SIMD_ID_MASK 0x00000030L
-#define SQ_EDC_INFO__SOURCE_MASK 0x000001C0L
-#define SQ_EDC_INFO__VM_ID_MASK 0x00001E00L
-//SQ_EDC_CNT
-#define SQ_EDC_CNT__LDS_D_SEC_COUNT__SHIFT 0x0
-#define SQ_EDC_CNT__LDS_D_DED_COUNT__SHIFT 0x2
-#define SQ_EDC_CNT__LDS_I_SEC_COUNT__SHIFT 0x4
-#define SQ_EDC_CNT__LDS_I_DED_COUNT__SHIFT 0x6
-#define SQ_EDC_CNT__SGPR_SEC_COUNT__SHIFT 0x8
-#define SQ_EDC_CNT__SGPR_DED_COUNT__SHIFT 0xa
-#define SQ_EDC_CNT__VGPR0_SEC_COUNT__SHIFT 0xc
-#define SQ_EDC_CNT__VGPR0_DED_COUNT__SHIFT 0xe
-#define SQ_EDC_CNT__VGPR1_SEC_COUNT__SHIFT 0x10
-#define SQ_EDC_CNT__VGPR1_DED_COUNT__SHIFT 0x12
-#define SQ_EDC_CNT__VGPR2_SEC_COUNT__SHIFT 0x14
-#define SQ_EDC_CNT__VGPR2_DED_COUNT__SHIFT 0x16
-#define SQ_EDC_CNT__VGPR3_SEC_COUNT__SHIFT 0x18
-#define SQ_EDC_CNT__VGPR3_DED_COUNT__SHIFT 0x1a
-#define SQ_EDC_CNT__LDS_D_SEC_COUNT_MASK 0x00000003L
-#define SQ_EDC_CNT__LDS_D_DED_COUNT_MASK 0x0000000CL
-#define SQ_EDC_CNT__LDS_I_SEC_COUNT_MASK 0x00000030L
-#define SQ_EDC_CNT__LDS_I_DED_COUNT_MASK 0x000000C0L
-#define SQ_EDC_CNT__SGPR_SEC_COUNT_MASK 0x00000300L
-#define SQ_EDC_CNT__SGPR_DED_COUNT_MASK 0x00000C00L
-#define SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK 0x00003000L
-#define SQ_EDC_CNT__VGPR0_DED_COUNT_MASK 0x0000C000L
-#define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK 0x00030000L
-#define SQ_EDC_CNT__VGPR1_DED_COUNT_MASK 0x000C0000L
-#define SQ_EDC_CNT__VGPR2_SEC_COUNT_MASK 0x00300000L
-#define SQ_EDC_CNT__VGPR2_DED_COUNT_MASK 0x00C00000L
-#define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK 0x03000000L
-#define SQ_EDC_CNT__VGPR3_DED_COUNT_MASK 0x0C000000L
-//SQ_EDC_FUE_CNTL
-#define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x0
-#define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x10
-#define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000FFFFL
-#define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xFFFF0000L
-//SQ_THREAD_TRACE_WORD_CMN
-#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0x000FL
-#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x0010L
-//SQ_THREAD_TRACE_WORD_EVENT
-#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x6
-#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0xa
-#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0x000FL
-#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x0010L
-#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x0020L
-#define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x01C0L
-#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0xFC00L
-//SQ_THREAD_TRACE_WORD_INST
-#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x9
-#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0xb
-#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0x000FL
-#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x0010L
-#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x01E0L
-#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x0600L
-#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0xF800L
-//SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x9
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR__SHIFT 0xf
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x10
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x00000010L
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x000001E0L
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x00000600L
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR_MASK 0x00008000L
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xFFFF0000L
-//SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x6
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0xa
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0xe
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x10
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x00000010L
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x00000020L
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x000003C0L
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x00003C00L
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0x0000C000L
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xFFFF0000L
-//SQ_THREAD_TRACE_WORD_ISSUE
-#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x8
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0xa
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0xc
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0xe
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x10
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x12
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x14
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x16
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x18
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x1a
-#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0x0000000FL
-#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x00000010L
-#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x00000060L
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x00000300L
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0x00000C00L
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x00003000L
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0x0000C000L
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x00030000L
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0x000C0000L
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x00300000L
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0x00C00000L
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x03000000L
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0x0C000000L
-//SQ_THREAD_TRACE_WORD_MISC
-#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0xc
-#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0xd
-#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0x000FL
-#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0x0FF0L
-#define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x1000L
-#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0xE000L
-//SQ_THREAD_TRACE_WORD_PERF_1_OF_2
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x6
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0xa
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0xc
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x19
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x00000010L
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x00000020L
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x000003C0L
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0x00000C00L
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x01FFF000L
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xFE000000L
-//SQ_THREAD_TRACE_WORD_REG_1_OF_2
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x7
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x9
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0xa
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0xe
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0xf
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x10
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x00000010L
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x00000060L
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x00000180L
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x00000200L
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x00001C00L
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x00004000L
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x00008000L
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xFFFF0000L
-//SQ_THREAD_TRACE_WORD_REG_2_OF_2
-#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xFFFFFFFFL
-//SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT 0x7
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT 0x9
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT 0x10
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK 0x00000010L
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK 0x00000060L
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK 0x00000180L
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK 0x0000FE00L
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK 0xFFFF0000L
-//SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2
-#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK 0x0000FFFFL
-//SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2
-#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x10
-#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
-#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xFFFF0000L
-//SQ_THREAD_TRACE_WORD_WAVE
-#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x6
-#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0xa
-#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0xe
-#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0x000FL
-#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x0010L
-#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x0020L
-#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x03C0L
-#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x3C00L
-#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0xC000L
-//SQ_THREAD_TRACE_WORD_WAVE_START
-#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x6
-#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0xa
-#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0xe
-#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x10
-#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x15
-#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x16
-#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x1d
-#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0x0000000FL
-#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x00000010L
-#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x00000020L
-#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x000003C0L
-#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x00003C00L
-#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0x0000C000L
-#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x001F0000L
-#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x00200000L
-#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1FC00000L
-#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xE0000000L
-//SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2
-#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0x00FFFFFFL
-//SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0xFFFFL
-//SQ_THREAD_TRACE_WORD_PERF_2_OF_2
-#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x6
-#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x13
-#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x0000003FL
-#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x0007FFC0L
-#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xFFF80000L
-//SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2
-#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xFFFFFFFFL
-//SQ_WREXEC_EXEC_HI
-#define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT 0x0
-#define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT 0x1a
-#define SQ_WREXEC_EXEC_HI__ATC__SHIFT 0x1b
-#define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT 0x1c
-#define SQ_WREXEC_EXEC_HI__MSB__SHIFT 0x1f
-#define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK 0x0000FFFFL
-#define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK 0x04000000L
-#define SQ_WREXEC_EXEC_HI__ATC_MASK 0x08000000L
-#define SQ_WREXEC_EXEC_HI__MTYPE_MASK 0x70000000L
-#define SQ_WREXEC_EXEC_HI__MSB_MASK 0x80000000L
-//SQ_WREXEC_EXEC_LO
-#define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT 0x0
-#define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK 0xFFFFFFFFL
-//SQ_BUF_RSRC_WORD0
-#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0
-#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xFFFFFFFFL
-//SQ_BUF_RSRC_WORD1
-#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0
-#define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x10
-#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x1e
-#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x1f
-#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x0000FFFFL
-#define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3FFF0000L
-#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000L
-#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000L
-//SQ_BUF_RSRC_WORD2
-#define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x0
-#define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xFFFFFFFFL
-//SQ_BUF_RSRC_WORD3
-#define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x0
-#define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3
-#define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6
-#define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x9
-#define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0xc
-#define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0xf
-#define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE__SHIFT 0x13
-#define SQ_BUF_RSRC_WORD3__USER_VM_MODE__SHIFT 0x14
-#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x15
-#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x17
-#define SQ_BUF_RSRC_WORD3__NV__SHIFT 0x1b
-#define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x1e
-#define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L
-#define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L
-#define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x000001C0L
-#define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0x00000E00L
-#define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x00007000L
-#define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x00078000L
-#define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE_MASK 0x00080000L
-#define SQ_BUF_RSRC_WORD3__USER_VM_MODE_MASK 0x00100000L
-#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x00600000L
-#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x00800000L
-#define SQ_BUF_RSRC_WORD3__NV_MASK 0x08000000L
-#define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xC0000000L
-//SQ_IMG_RSRC_WORD0
-#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0
-#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xFFFFFFFFL
-//SQ_IMG_RSRC_WORD1
-#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0
-#define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x8
-#define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x14
-#define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x1a
-#define SQ_IMG_RSRC_WORD1__NV__SHIFT 0x1e
-#define SQ_IMG_RSRC_WORD1__META_DIRECT__SHIFT 0x1f
-#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x000000FFL
-#define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0x000FFF00L
-#define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x03F00000L
-#define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3C000000L
-#define SQ_IMG_RSRC_WORD1__NV_MASK 0x40000000L
-#define SQ_IMG_RSRC_WORD1__META_DIRECT_MASK 0x80000000L
-//SQ_IMG_RSRC_WORD2
-#define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x0
-#define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0xe
-#define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x1c
-#define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x00003FFFL
-#define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0x0FFFC000L
-#define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000L
-//SQ_IMG_RSRC_WORD3
-#define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x0
-#define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3
-#define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6
-#define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x9
-#define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0xc
-#define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x10
-#define SQ_IMG_RSRC_WORD3__SW_MODE__SHIFT 0x14
-#define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x1c
-#define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L
-#define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L
-#define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x000001C0L
-#define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0x00000E00L
-#define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0x0000F000L
-#define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0x000F0000L
-#define SQ_IMG_RSRC_WORD3__SW_MODE_MASK 0x01F00000L
-#define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xF0000000L
-//SQ_IMG_RSRC_WORD4
-#define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x0
-#define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0xd
-#define SQ_IMG_RSRC_WORD4__BC_SWIZZLE__SHIFT 0x1d
-#define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x00001FFFL
-#define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x1FFFE000L
-#define SQ_IMG_RSRC_WORD4__BC_SWIZZLE_MASK 0xE0000000L
-//SQ_IMG_RSRC_WORD5
-#define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x0
-#define SQ_IMG_RSRC_WORD5__ARRAY_PITCH__SHIFT 0xd
-#define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS__SHIFT 0x11
-#define SQ_IMG_RSRC_WORD5__META_LINEAR__SHIFT 0x19
-#define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED__SHIFT 0x1a
-#define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED__SHIFT 0x1b
-#define SQ_IMG_RSRC_WORD5__MAX_MIP__SHIFT 0x1c
-#define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x00001FFFL
-#define SQ_IMG_RSRC_WORD5__ARRAY_PITCH_MASK 0x0001E000L
-#define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS_MASK 0x01FE0000L
-#define SQ_IMG_RSRC_WORD5__META_LINEAR_MASK 0x02000000L
-#define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED_MASK 0x04000000L
-#define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED_MASK 0x08000000L
-#define SQ_IMG_RSRC_WORD5__MAX_MIP_MASK 0xF0000000L
-//SQ_IMG_RSRC_WORD6
-#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x0
-#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0xc
-#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x14
-#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN__SHIFT 0x15
-#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB__SHIFT 0x16
-#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM__SHIFT 0x17
-#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS__SHIFT 0x18
-#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS__SHIFT 0x1c
-#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0x00000FFFL
-#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0x000FF000L
-#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x00100000L
-#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN_MASK 0x00200000L
-#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB_MASK 0x00400000L
-#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM_MASK 0x00800000L
-#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS_MASK 0x0F000000L
-#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS_MASK 0xF0000000L
-//SQ_IMG_RSRC_WORD7
-#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS__SHIFT 0x0
-#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS_MASK 0xFFFFFFFFL
-//SQ_IMG_SAMP_WORD0
-#define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x0
-#define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x3
-#define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x6
-#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x9
-#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0xc
-#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0xf
-#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x10
-#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x13
-#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x14
-#define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x15
-#define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x1b
-#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x1c
-#define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x1d
-#define SQ_IMG_SAMP_WORD0__COMPAT_MODE__SHIFT 0x1f
-#define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x00000007L
-#define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x00000038L
-#define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x000001C0L
-#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0x00000E00L
-#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x00007000L
-#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x00008000L
-#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x00070000L
-#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x00080000L
-#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x00100000L
-#define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x07E00000L
-#define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x08000000L
-#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000L
-#define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000L
-#define SQ_IMG_SAMP_WORD0__COMPAT_MODE_MASK 0x80000000L
-//SQ_IMG_SAMP_WORD1
-#define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x0
-#define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0xc
-#define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x18
-#define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x1c
-#define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0x00000FFFL
-#define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0x00FFF000L
-#define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0x0F000000L
-#define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xF0000000L
-//SQ_IMG_SAMP_WORD2
-#define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x0
-#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0xe
-#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x14
-#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x16
-#define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x18
-#define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x1a
-#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x1c
-#define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT__SHIFT 0x1d
-#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x1e
-#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE__SHIFT 0x1f
-#define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x00003FFFL
-#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0x000FC000L
-#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x00300000L
-#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0x00C00000L
-#define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x03000000L
-#define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0x0C000000L
-#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000L
-#define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT_MASK 0x20000000L
-#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000L
-#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE_MASK 0x80000000L
-//SQ_IMG_SAMP_WORD3
-#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x0
-#define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA__SHIFT 0xc
-#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x1e
-#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0x00000FFFL
-#define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA_MASK 0x00001000L
-#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xC0000000L
-//SQ_FLAT_SCRATCH_WORD0
-#define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT 0x0
-#define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK 0x0007FFFFL
-//SQ_FLAT_SCRATCH_WORD1
-#define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT 0x0
-#define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK 0x00FFFFFFL
-//SQ_M0_GPR_IDX_WORD
-#define SQ_M0_GPR_IDX_WORD__INDEX__SHIFT 0x0
-#define SQ_M0_GPR_IDX_WORD__VSRC0_REL__SHIFT 0xc
-#define SQ_M0_GPR_IDX_WORD__VSRC1_REL__SHIFT 0xd
-#define SQ_M0_GPR_IDX_WORD__VSRC2_REL__SHIFT 0xe
-#define SQ_M0_GPR_IDX_WORD__VDST_REL__SHIFT 0xf
-#define SQ_M0_GPR_IDX_WORD__INDEX_MASK 0x000000FFL
-#define SQ_M0_GPR_IDX_WORD__VSRC0_REL_MASK 0x00001000L
-#define SQ_M0_GPR_IDX_WORD__VSRC1_REL_MASK 0x00002000L
-#define SQ_M0_GPR_IDX_WORD__VSRC2_REL_MASK 0x00004000L
-#define SQ_M0_GPR_IDX_WORD__VDST_REL_MASK 0x00008000L
-//SQC_ICACHE_UTCL1_CNTL1
-#define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
-#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
-#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
-#define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
-#define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
-#define SQC_ICACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
-#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
-#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
-#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13
-#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17
-#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18
-#define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
-#define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
-#define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
-#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
-#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
-#define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
-#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
-#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
-#define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
-#define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
-#define SQC_ICACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
-#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
-#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
-#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L
-#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L
-#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L
-#define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
-#define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
-#define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
-#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
-#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
-//SQC_ICACHE_UTCL1_CNTL2
-#define SQC_ICACHE_UTCL1_CNTL2__SPARE__SHIFT 0x0
-#define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8
-#define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
-#define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
-#define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb
-#define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
-#define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
-#define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
-#define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
-#define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x10
-#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
-#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13
-#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14
-#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15
-#define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
-#define SQC_ICACHE_UTCL1_CNTL2__SPARE_MASK 0x000000FFL
-#define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L
-#define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
-#define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
-#define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L
-#define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
-#define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
-#define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
-#define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
-#define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L
-#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
-#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L
-#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
-#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L
-#define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
-//SQC_DCACHE_UTCL1_CNTL1
-#define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
-#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
-#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
-#define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
-#define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
-#define SQC_DCACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
-#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
-#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
-#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13
-#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17
-#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18
-#define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
-#define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
-#define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
-#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
-#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
-#define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
-#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
-#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
-#define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
-#define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
-#define SQC_DCACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
-#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
-#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
-#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L
-#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L
-#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L
-#define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
-#define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
-#define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
-#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
-#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
-//SQC_DCACHE_UTCL1_CNTL2
-#define SQC_DCACHE_UTCL1_CNTL2__SPARE__SHIFT 0x0
-#define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8
-#define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
-#define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
-#define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb
-#define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
-#define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
-#define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
-#define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
-#define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x10
-#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
-#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13
-#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14
-#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15
-#define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
-#define SQC_DCACHE_UTCL1_CNTL2__SPARE_MASK 0x000000FFL
-#define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L
-#define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
-#define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
-#define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L
-#define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
-#define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
-#define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
-#define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
-#define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L
-#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
-#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L
-#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
-#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L
-#define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
-//SQC_ICACHE_UTCL1_STATUS
-#define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
-#define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
-#define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
-#define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
-#define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
-#define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
-//SQC_DCACHE_UTCL1_STATUS
-#define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
-#define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
-#define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
-#define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
-#define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
-#define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
-
-
-// addressBlock: gc_shsdec
-//SX_DEBUG_1
-#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0
-#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x8
-#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x9
-#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0xa
-#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT__SHIFT 0xb
-#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT__SHIFT 0xc
-#define SX_DEBUG_1__PC_CFG__SHIFT 0xd
-#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0xe
-#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x0000007FL
-#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x00000100L
-#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS_MASK 0x00000200L
-#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x00000400L
-#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT_MASK 0x00000800L
-#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT_MASK 0x00001000L
-#define SX_DEBUG_1__PC_CFG_MASK 0x00002000L
-#define SX_DEBUG_1__DEBUG_DATA_MASK 0xFFFFC000L
-//SPI_PS_MAX_WAVE_ID
-#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
-#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID__SHIFT 0x10
-#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
-#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID_MASK 0x03FF0000L
-//SPI_START_PHASE
-#define SPI_START_PHASE__VGPR_START_PHASE__SHIFT 0x0
-#define SPI_START_PHASE__SGPR_START_PHASE__SHIFT 0x2
-#define SPI_START_PHASE__WAVE_START_PHASE__SHIFT 0x4
-#define SPI_START_PHASE__VGPR_START_PHASE_MASK 0x00000003L
-#define SPI_START_PHASE__SGPR_START_PHASE_MASK 0x0000000CL
-#define SPI_START_PHASE__WAVE_START_PHASE_MASK 0x00000030L
-//SPI_GFX_CNTL
-#define SPI_GFX_CNTL__RESET_COUNTS__SHIFT 0x0
-#define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x00000001L
-//SPI_DSM_CNTL
-#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA__SHIFT 0x0
-#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
-#define SPI_DSM_CNTL__UNUSED__SHIFT 0x3
-#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
-#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
-#define SPI_DSM_CNTL__UNUSED_MASK 0xFFFFFFF8L
-//SPI_DSM_CNTL2
-#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY__SHIFT 0x2
-#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY__SHIFT 0x4
-#define SPI_DSM_CNTL2__UNUSED__SHIFT 0xa
-#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY_MASK 0x000003F0L
-#define SPI_DSM_CNTL2__UNUSED_MASK 0xFFFFFC00L
-//SPI_EDC_CNT
-#define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT__SHIFT 0x0
-#define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT_MASK 0x00000003L
-//SPI_CONFIG_PS_CU_EN
-#define SPI_CONFIG_PS_CU_EN__ENABLE__SHIFT 0x0
-#define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN__SHIFT 0x1
-#define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN__SHIFT 0x10
-#define SPI_CONFIG_PS_CU_EN__ENABLE_MASK 0x00000001L
-#define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN_MASK 0x0000FFFEL
-#define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN_MASK 0xFFFF0000L
-//SPI_WF_LIFETIME_CNTL
-#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0
-#define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4
-#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0x0000000FL
-#define SPI_WF_LIFETIME_CNTL__EN_MASK 0x00000010L
-//SPI_WF_LIFETIME_LIMIT_0
-#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000L
-//SPI_WF_LIFETIME_LIMIT_1
-#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000L
-//SPI_WF_LIFETIME_LIMIT_2
-#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000L
-//SPI_WF_LIFETIME_LIMIT_3
-#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000L
-//SPI_WF_LIFETIME_LIMIT_4
-#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000L
-//SPI_WF_LIFETIME_LIMIT_5
-#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000L
-//SPI_WF_LIFETIME_LIMIT_6
-#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK 0x80000000L
-//SPI_WF_LIFETIME_LIMIT_7
-#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK 0x80000000L
-//SPI_WF_LIFETIME_LIMIT_8
-#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK 0x80000000L
-//SPI_WF_LIFETIME_LIMIT_9
-#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_0
-#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_1
-#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_2
-#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_3
-#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_4
-#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_5
-#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_6
-#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_7
-#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_8
-#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_9
-#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_10
-#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_11
-#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_12
-#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_13
-#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_14
-#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_15
-#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_16
-#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_17
-#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_18
-#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_19
-#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000L
-//SPI_WF_LIFETIME_STATUS_20
-#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7FFFFFFFL
-#define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000L
-//SPI_LB_CTR_CTRL
-#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0
-#define SPI_LB_CTR_CTRL__WAVES_SELECT__SHIFT 0x1
-#define SPI_LB_CTR_CTRL__CLEAR_ON_READ__SHIFT 0x3
-#define SPI_LB_CTR_CTRL__RESET_COUNTS__SHIFT 0x4
-#define SPI_LB_CTR_CTRL__LOAD_MASK 0x00000001L
-#define SPI_LB_CTR_CTRL__WAVES_SELECT_MASK 0x00000006L
-#define SPI_LB_CTR_CTRL__CLEAR_ON_READ_MASK 0x00000008L
-#define SPI_LB_CTR_CTRL__RESET_COUNTS_MASK 0x00000010L
-//SPI_LB_CU_MASK
-#define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x0
-#define SPI_LB_CU_MASK__CU_MASK_MASK 0xFFFFL
-//SPI_LB_DATA_REG
-#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0
-#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xFFFFFFFFL
-//SPI_PG_ENABLE_STATIC_CU_MASK
-#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x0
-#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0xFFFFL
-//SPI_GDS_CREDITS
-#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0
-#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8
-#define SPI_GDS_CREDITS__UNUSED__SHIFT 0x10
-#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0x000000FFL
-#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0x0000FF00L
-#define SPI_GDS_CREDITS__UNUSED_MASK 0xFFFF0000L
-//SPI_SX_EXPORT_BUFFER_SIZES
-#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0
-#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10
-#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0x0000FFFFL
-#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xFFFF0000L
-//SPI_SX_SCOREBOARD_BUFFER_SIZES
-#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0
-#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10
-#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0x0000FFFFL
-#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xFFFF0000L
-//SPI_CSQ_WF_ACTIVE_STATUS
-#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0
-#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xFFFFFFFFL
-//SPI_CSQ_WF_ACTIVE_COUNT_0
-#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0
-#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS__SHIFT 0x10
-#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000007FFL
-#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS_MASK 0x07FF0000L
-//SPI_CSQ_WF_ACTIVE_COUNT_1
-#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0
-#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS__SHIFT 0x10
-#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000007FFL
-#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS_MASK 0x07FF0000L
-//SPI_CSQ_WF_ACTIVE_COUNT_2
-#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0
-#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS__SHIFT 0x10
-#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x000007FFL
-#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS_MASK 0x07FF0000L
-//SPI_CSQ_WF_ACTIVE_COUNT_3
-#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0
-#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS__SHIFT 0x10
-#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x000007FFL
-#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS_MASK 0x07FF0000L
-//SPI_CSQ_WF_ACTIVE_COUNT_4
-#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0
-#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS__SHIFT 0x10
-#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x000007FFL
-#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS_MASK 0x07FF0000L
-//SPI_CSQ_WF_ACTIVE_COUNT_5
-#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0
-#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS__SHIFT 0x10
-#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x000007FFL
-#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS_MASK 0x07FF0000L
-//SPI_CSQ_WF_ACTIVE_COUNT_6
-#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0
-#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS__SHIFT 0x10
-#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x000007FFL
-#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS_MASK 0x07FF0000L
-//SPI_CSQ_WF_ACTIVE_COUNT_7
-#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0
-#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS__SHIFT 0x10
-#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x000007FFL
-#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS_MASK 0x07FF0000L
-//SPI_LB_DATA_WAVES
-#define SPI_LB_DATA_WAVES__COUNT0__SHIFT 0x0
-#define SPI_LB_DATA_WAVES__COUNT1__SHIFT 0x10
-#define SPI_LB_DATA_WAVES__COUNT0_MASK 0x0000FFFFL
-#define SPI_LB_DATA_WAVES__COUNT1_MASK 0xFFFF0000L
-//SPI_LB_DATA_PERCU_WAVE_HSGS
-#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS__SHIFT 0x0
-#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS__SHIFT 0x10
-#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS_MASK 0x0000FFFFL
-#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS_MASK 0xFFFF0000L
-//SPI_LB_DATA_PERCU_WAVE_VSPS
-#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS__SHIFT 0x0
-#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS__SHIFT 0x10
-#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS_MASK 0x0000FFFFL
-#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS_MASK 0xFFFF0000L
-//SPI_LB_DATA_PERCU_WAVE_CS
-#define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE__SHIFT 0x0
-#define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE_MASK 0xFFFFL
-//SPI_P0_TRAP_SCREEN_PSBA_LO
-#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0
-#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL
-//SPI_P0_TRAP_SCREEN_PSBA_HI
-#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0
-#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL
-//SPI_P0_TRAP_SCREEN_PSMA_LO
-#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0
-#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL
-//SPI_P0_TRAP_SCREEN_PSMA_HI
-#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0
-#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL
-//SPI_P0_TRAP_SCREEN_GPR_MIN
-#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
-#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6
-#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL
-#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L
-//SPI_P1_TRAP_SCREEN_PSBA_LO
-#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0
-#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL
-//SPI_P1_TRAP_SCREEN_PSBA_HI
-#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0
-#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL
-//SPI_P1_TRAP_SCREEN_PSMA_LO
-#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0
-#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL
-//SPI_P1_TRAP_SCREEN_PSMA_HI
-#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0
-#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL
-//SPI_P1_TRAP_SCREEN_GPR_MIN
-#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
-#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6
-#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL
-#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L
-
-
-// addressBlock: gc_tpdec
-//TD_CNTL
-#define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x0
-#define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x4
-#define TD_CNTL__PAD_STALL_EN__SHIFT 0x8
-#define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x9
-#define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0xb
-#define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT 0xf
-#define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x10
-#define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x12
-#define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x13
-#define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x14
-#define TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT 0x15
-#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT__SHIFT 0x17
-#define TD_CNTL__DISABLE_MM_QNAN_COMPARE_RESULT__SHIFT 0x18
-#define TD_CNTL__SYNC_PHASE_SH_MASK 0x00000003L
-#define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x00000030L
-#define TD_CNTL__PAD_STALL_EN_MASK 0x00000100L
-#define TD_CNTL__EXTEND_LDS_STALL_MASK 0x00000600L
-#define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x00001800L
-#define TD_CNTL__PRECISION_COMPATIBILITY_MASK 0x00008000L
-#define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x00010000L
-#define TD_CNTL__LD_FLOAT_MODE_MASK 0x00040000L
-#define TD_CNTL__GATHER4_DX9_MODE_MASK 0x00080000L
-#define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x00100000L
-#define TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK 0x00200000L
-#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT_MASK 0x00800000L
-#define TD_CNTL__DISABLE_MM_QNAN_COMPARE_RESULT_MASK 0x01000000L
-//TD_STATUS
-#define TD_STATUS__BUSY__SHIFT 0x1f
-#define TD_STATUS__BUSY_MASK 0x80000000L
-//TD_DSM_CNTL
-#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA__SHIFT 0x0
-#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE__SHIFT 0x2
-#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA__SHIFT 0x3
-#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE__SHIFT 0x5
-#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6
-#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8
-#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA_MASK 0x00000003L
-#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE_MASK 0x00000004L
-#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA_MASK 0x00000018L
-#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE_MASK 0x00000020L
-#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L
-#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L
-//TD_DSM_CNTL2
-#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY__SHIFT 0x2
-#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT__SHIFT 0x3
-#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY__SHIFT 0x5
-#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6
-#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8
-#define TD_DSM_CNTL2__TD_INJECT_DELAY__SHIFT 0x1a
-#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT_MASK 0x00000018L
-#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY_MASK 0x00000020L
-#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L
-#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L
-#define TD_DSM_CNTL2__TD_INJECT_DELAY_MASK 0xFC000000L
-//TD_SCRATCH
-#define TD_SCRATCH__SCRATCH__SHIFT 0x0
-#define TD_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL
-//TA_CNTL
-#define TA_CNTL__FX_XNACK_CREDIT__SHIFT 0x0
-#define TA_CNTL__SQ_XNACK_CREDIT__SHIFT 0x9
-#define TA_CNTL__TC_DATA_CREDIT__SHIFT 0xd
-#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10
-#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16
-#define TA_CNTL__FX_XNACK_CREDIT_MASK 0x0000007FL
-#define TA_CNTL__SQ_XNACK_CREDIT_MASK 0x00001E00L
-#define TA_CNTL__TC_DATA_CREDIT_MASK 0x0000E000L
-#define TA_CNTL__ALIGNER_CREDIT_MASK 0x001F0000L
-#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xFFC00000L
-//TA_CNTL_AUX
-#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0
-#define TA_CNTL_AUX__RESERVED__SHIFT 0x1
-#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE__SHIFT 0x5
-#define TA_CNTL_AUX__GATHERH_DST_SEL__SHIFT 0x6
-#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE__SHIFT 0x7
-#define TA_CNTL_AUX__NONIMG_ANISO_BYPASS__SHIFT 0x9
-#define TA_CNTL_AUX__ANISO_HALF_THRESH__SHIFT 0xa
-#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS__SHIFT 0xc
-#define TA_CNTL_AUX__ANISO_STEP_ORDER__SHIFT 0xd
-#define TA_CNTL_AUX__ANISO_STEP__SHIFT 0xe
-#define TA_CNTL_AUX__MINMAG_UNNORM__SHIFT 0xf
-#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10
-#define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT 0x11
-#define TA_CNTL_AUX__ANISO_TAP__SHIFT 0x12
-#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE__SHIFT 0x13
-#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE__SHIFT 0x14
-#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE__SHIFT 0x15
-#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE__SHIFT 0x16
-#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE__SHIFT 0x17
-#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE__SHIFT 0x18
-#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE__SHIFT 0x19
-#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE__SHIFT 0x1a
-#define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE__SHIFT 0x1b
-#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP__SHIFT 0x1c
-#define TA_CNTL_AUX__TRUNC_SMALL_NEG__SHIFT 0x1d
-#define TA_CNTL_AUX__ARRAY_ROUND_MODE__SHIFT 0x1e
-#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x00000001L
-#define TA_CNTL_AUX__RESERVED_MASK 0x0000000EL
-#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE_MASK 0x00000020L
-#define TA_CNTL_AUX__GATHERH_DST_SEL_MASK 0x00000040L
-#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE_MASK 0x00000080L
-#define TA_CNTL_AUX__NONIMG_ANISO_BYPASS_MASK 0x00000200L
-#define TA_CNTL_AUX__ANISO_HALF_THRESH_MASK 0x00000C00L
-#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS_MASK 0x00001000L
-#define TA_CNTL_AUX__ANISO_STEP_ORDER_MASK 0x00002000L
-#define TA_CNTL_AUX__ANISO_STEP_MASK 0x00004000L
-#define TA_CNTL_AUX__MINMAG_UNNORM_MASK 0x00008000L
-#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x00010000L
-#define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK 0x00020000L
-#define TA_CNTL_AUX__ANISO_TAP_MASK 0x00040000L
-#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE_MASK 0x00080000L
-#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE_MASK 0x00100000L
-#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE_MASK 0x00200000L
-#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE_MASK 0x00400000L
-#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE_MASK 0x00800000L
-#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE_MASK 0x01000000L
-#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE_MASK 0x02000000L
-#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE_MASK 0x04000000L
-#define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE_MASK 0x08000000L
-#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP_MASK 0x10000000L
-#define TA_CNTL_AUX__TRUNC_SMALL_NEG_MASK 0x20000000L
-#define TA_CNTL_AUX__ARRAY_ROUND_MODE_MASK 0xC0000000L
-//TA_RESERVED_010C
-#define TA_RESERVED_010C__Unused__SHIFT 0x0
-#define TA_RESERVED_010C__Unused_MASK 0xFFFFFFFFL
-//TA_STATUS
-#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc
-#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd
-#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe
-#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10
-#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11
-#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12
-#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14
-#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15
-#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16
-#define TA_STATUS__IN_BUSY__SHIFT 0x18
-#define TA_STATUS__FG_BUSY__SHIFT 0x19
-#define TA_STATUS__LA_BUSY__SHIFT 0x1a
-#define TA_STATUS__FL_BUSY__SHIFT 0x1b
-#define TA_STATUS__TA_BUSY__SHIFT 0x1c
-#define TA_STATUS__FA_BUSY__SHIFT 0x1d
-#define TA_STATUS__AL_BUSY__SHIFT 0x1e
-#define TA_STATUS__BUSY__SHIFT 0x1f
-#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x00001000L
-#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x00002000L
-#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x00004000L
-#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x00010000L
-#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x00020000L
-#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x00040000L
-#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x00100000L
-#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x00200000L
-#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x00400000L
-#define TA_STATUS__IN_BUSY_MASK 0x01000000L
-#define TA_STATUS__FG_BUSY_MASK 0x02000000L
-#define TA_STATUS__LA_BUSY_MASK 0x04000000L
-#define TA_STATUS__FL_BUSY_MASK 0x08000000L
-#define TA_STATUS__TA_BUSY_MASK 0x10000000L
-#define TA_STATUS__FA_BUSY_MASK 0x20000000L
-#define TA_STATUS__AL_BUSY_MASK 0x40000000L
-#define TA_STATUS__BUSY_MASK 0x80000000L
-//TA_SCRATCH
-#define TA_SCRATCH__SCRATCH__SHIFT 0x0
-#define TA_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL
-
-
-// addressBlock: gc_gdsdec
-//GDS_CONFIG
-#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x1
-#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3
-#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5
-#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x7
-#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x00000006L
-#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x00000018L
-#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x00000060L
-#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x00000180L
-//GDS_CNTL_STATUS
-#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0
-#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1
-#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2
-#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x3
-#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x4
-#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5
-#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x6
-#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT 0x7
-#define GDS_CNTL_STATUS__DS_BUSY__SHIFT 0x8
-#define GDS_CNTL_STATUS__GWS_BUSY__SHIFT 0x9
-#define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0xa
-#define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT 0xb
-#define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT 0xc
-#define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT 0xd
-#define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT 0xe
-#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x00000001L
-#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x00000002L
-#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x00000004L
-#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x00000008L
-#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x00000010L
-#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x00000020L
-#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x00000040L
-#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK 0x00000080L
-#define GDS_CNTL_STATUS__DS_BUSY_MASK 0x00000100L
-#define GDS_CNTL_STATUS__GWS_BUSY_MASK 0x00000200L
-#define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK 0x00000400L
-#define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK 0x00000800L
-#define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK 0x00001000L
-#define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK 0x00002000L
-#define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK 0x00004000L
-//GDS_ENHANCE2
-#define GDS_ENHANCE2__MISC__SHIFT 0x0
-#define GDS_ENHANCE2__UNUSED__SHIFT 0x10
-#define GDS_ENHANCE2__MISC_MASK 0x0000FFFFL
-#define GDS_ENHANCE2__UNUSED_MASK 0xFFFF0000L
-//GDS_PROTECTION_FAULT
-#define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0
-#define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1
-#define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2
-#define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x3
-#define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x6
-#define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa
-#define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xc
-#define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x10
-#define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L
-#define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L
-#define GDS_PROTECTION_FAULT__GRBM_MASK 0x00000004L
-#define GDS_PROTECTION_FAULT__SH_ID_MASK 0x00000038L
-#define GDS_PROTECTION_FAULT__CU_ID_MASK 0x000003C0L
-#define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0x00000C00L
-#define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0x0000F000L
-#define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L
-//GDS_VM_PROTECTION_FAULT
-#define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0
-#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1
-#define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2
-#define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3
-#define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4
-#define GDS_VM_PROTECTION_FAULT__TMZ__SHIFT 0x5
-#define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8
-#define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10
-#define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L
-#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L
-#define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x00000004L
-#define GDS_VM_PROTECTION_FAULT__OA_MASK 0x00000008L
-#define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x00000010L
-#define GDS_VM_PROTECTION_FAULT__TMZ_MASK 0x00000020L
-#define GDS_VM_PROTECTION_FAULT__VMID_MASK 0x00000F00L
-#define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L
-//GDS_EDC_CNT
-#define GDS_EDC_CNT__GDS_MEM_DED__SHIFT 0x0
-#define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED__SHIFT 0x2
-#define GDS_EDC_CNT__GDS_MEM_SEC__SHIFT 0x4
-#define GDS_EDC_CNT__UNUSED__SHIFT 0x6
-#define GDS_EDC_CNT__GDS_MEM_DED_MASK 0x00000003L
-#define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED_MASK 0x0000000CL
-#define GDS_EDC_CNT__GDS_MEM_SEC_MASK 0x00000030L
-#define GDS_EDC_CNT__UNUSED_MASK 0xFFFFFFC0L
-//GDS_EDC_GRBM_CNT
-#define GDS_EDC_GRBM_CNT__DED__SHIFT 0x0
-#define GDS_EDC_GRBM_CNT__SEC__SHIFT 0x2
-#define GDS_EDC_GRBM_CNT__UNUSED__SHIFT 0x4
-#define GDS_EDC_GRBM_CNT__DED_MASK 0x00000003L
-#define GDS_EDC_GRBM_CNT__SEC_MASK 0x0000000CL
-#define GDS_EDC_GRBM_CNT__UNUSED_MASK 0xFFFFFFF0L
-//GDS_EDC_OA_DED
-#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0
-#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1
-#define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT 0x2
-#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED__SHIFT 0x3
-#define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT 0x4
-#define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT 0x5
-#define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT 0x6
-#define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT 0x7
-#define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT 0x8
-#define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT 0x9
-#define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT 0xa
-#define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT 0xb
-#define GDS_EDC_OA_DED__UNUSED1__SHIFT 0xc
-#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x00000001L
-#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x00000002L
-#define GDS_EDC_OA_DED__ME0_CS_DED_MASK 0x00000004L
-#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED_MASK 0x00000008L
-#define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK 0x00000010L
-#define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK 0x00000020L
-#define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK 0x00000040L
-#define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK 0x00000080L
-#define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK 0x00000100L
-#define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK 0x00000200L
-#define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK 0x00000400L
-#define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK 0x00000800L
-#define GDS_EDC_OA_DED__UNUSED1_MASK 0xFFFFF000L
-//GDS_DSM_CNTL
-#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0__SHIFT 0x0
-#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1__SHIFT 0x1
-#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
-#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0__SHIFT 0x3
-#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1__SHIFT 0x4
-#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE__SHIFT 0x5
-#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0__SHIFT 0x6
-#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1__SHIFT 0x7
-#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x8
-#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0__SHIFT 0x9
-#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1__SHIFT 0xa
-#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb
-#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0__SHIFT 0xc
-#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1__SHIFT 0xd
-#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
-#define GDS_DSM_CNTL__UNUSED__SHIFT 0xf
-#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0_MASK 0x00000001L
-#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1_MASK 0x00000002L
-#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
-#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0_MASK 0x00000008L
-#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1_MASK 0x00000010L
-#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE_MASK 0x00000020L
-#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0_MASK 0x00000040L
-#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1_MASK 0x00000080L
-#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
-#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0_MASK 0x00000200L
-#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1_MASK 0x00000400L
-#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
-#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0_MASK 0x00001000L
-#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1_MASK 0x00002000L
-#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
-#define GDS_DSM_CNTL__UNUSED_MASK 0xFFFF8000L
-//GDS_EDC_OA_PHY_CNT
-#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC__SHIFT 0x0
-#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED__SHIFT 0x2
-#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC__SHIFT 0x4
-#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED__SHIFT 0x6
-#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED__SHIFT 0x8
-#define GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT 0xa
-#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC_MASK 0x00000003L
-#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED_MASK 0x0000000CL
-#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC_MASK 0x00000030L
-#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED_MASK 0x000000C0L
-#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED_MASK 0x00000300L
-#define GDS_EDC_OA_PHY_CNT__UNUSED1_MASK 0xFFFFFC00L
-//GDS_EDC_OA_PIPE_CNT
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC__SHIFT 0x0
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED__SHIFT 0x2
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC__SHIFT 0x4
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED__SHIFT 0x6
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC__SHIFT 0x8
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT 0xa
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC__SHIFT 0xc
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED__SHIFT 0xe
-#define GDS_EDC_OA_PIPE_CNT__UNUSED__SHIFT 0x10
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC_MASK 0x00000003L
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED_MASK 0x0000000CL
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC_MASK 0x00000030L
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED_MASK 0x000000C0L
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC_MASK 0x00000300L
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED_MASK 0x00000C00L
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC_MASK 0x00003000L
-#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED_MASK 0x0000C000L
-#define GDS_EDC_OA_PIPE_CNT__UNUSED_MASK 0xFFFF0000L
-//GDS_DSM_CNTL2
-#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY__SHIFT 0x2
-#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT__SHIFT 0x3
-#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY__SHIFT 0x5
-#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT__SHIFT 0x6
-#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY__SHIFT 0x8
-#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9
-#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY__SHIFT 0xb
-#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT__SHIFT 0xc
-#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY__SHIFT 0xe
-#define GDS_DSM_CNTL2__UNUSED__SHIFT 0xf
-#define GDS_DSM_CNTL2__GDS_INJECT_DELAY__SHIFT 0x1a
-#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT_MASK 0x00000018L
-#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY_MASK 0x00000020L
-#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
-#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY_MASK 0x00000100L
-#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L
-#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L
-#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
-#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY_MASK 0x00004000L
-#define GDS_DSM_CNTL2__UNUSED_MASK 0x03FF8000L
-#define GDS_DSM_CNTL2__GDS_INJECT_DELAY_MASK 0xFC000000L
-//GDS_WD_GDS_CSB
-#define GDS_WD_GDS_CSB__COUNTER__SHIFT 0x0
-#define GDS_WD_GDS_CSB__UNUSED__SHIFT 0xd
-#define GDS_WD_GDS_CSB__COUNTER_MASK 0x00001FFFL
-#define GDS_WD_GDS_CSB__UNUSED_MASK 0xFFFFE000L
-
-
-// addressBlock: gc_rbdec
-//DB_DEBUG
-#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0
-#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1
-#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2
-#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3
-#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4
-#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6
-#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7
-#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8
-#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa
-#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc
-#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe
-#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf
-#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10
-#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11
-#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12
-#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13
-#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15
-#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16
-#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17
-#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18
-#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c
-#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d
-#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e
-#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f
-#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x00000001L
-#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x00000002L
-#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x00000004L
-#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x00000008L
-#define DB_DEBUG__FORCE_Z_MODE_MASK 0x00000030L
-#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x00000040L
-#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x00000080L
-#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x00000300L
-#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0x00000C00L
-#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x00003000L
-#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x00004000L
-#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x00008000L
-#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x00010000L
-#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x00020000L
-#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x00040000L
-#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x00180000L
-#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x00200000L
-#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x00400000L
-#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x00800000L
-#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0x0F000000L
-#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000L
-#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000L
-#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000L
-#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000L
-//DB_DEBUG2
-#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0
-#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1
-#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2
-#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3
-#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4
-#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL__SHIFT 0x5
-#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ__SHIFT 0x6
-#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL__SHIFT 0x7
-#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE__SHIFT 0x8
-#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9
-#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe
-#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0xf
-#define DB_DEBUG2__RESERVED__SHIFT 0x10
-#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11
-#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12
-#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13
-#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c
-#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d
-#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e
-#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f
-#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x00000001L
-#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x00000002L
-#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x00000004L
-#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x00000008L
-#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x00000010L
-#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_MASK 0x00000020L
-#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ_MASK 0x00000040L
-#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL_MASK 0x00000080L
-#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE_MASK 0x00000100L
-#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x00003E00L
-#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x00004000L
-#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x00008000L
-#define DB_DEBUG2__RESERVED_MASK 0x00010000L
-#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x00020000L
-#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x00040000L
-#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x00080000L
-#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000L
-#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000L
-#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000L
-#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000L
-//DB_DEBUG3
-#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION__SHIFT 0x0
-#define DB_DEBUG3__ROUND_ZRANGE_CORRECTION__SHIFT 0x1
-#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2
-#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3
-#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4
-#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5
-#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6
-#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7
-#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8
-#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9
-#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa
-#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb
-#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc
-#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd
-#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe
-#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf
-#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x10
-#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11
-#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12
-#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13
-#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14
-#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15
-#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16
-#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17
-#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18
-#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19
-#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a
-#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b
-#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c
-#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d
-#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE__SHIFT 0x1e
-#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK__SHIFT 0x1f
-#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION_MASK 0x00000001L
-#define DB_DEBUG3__ROUND_ZRANGE_CORRECTION_MASK 0x00000002L
-#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x00000004L
-#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x00000008L
-#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x00000010L
-#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x00000020L
-#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x00000040L
-#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x00000080L
-#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x00000100L
-#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x00000200L
-#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x00000400L
-#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x00000800L
-#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x00001000L
-#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x00002000L
-#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x00004000L
-#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x00008000L
-#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x00010000L
-#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x00020000L
-#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x00040000L
-#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x00080000L
-#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x00100000L
-#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x00200000L
-#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x00400000L
-#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x00800000L
-#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x01000000L
-#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x02000000L
-#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x04000000L
-#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x08000000L
-#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000L
-#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000L
-#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE_MASK 0x40000000L
-#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK_MASK 0x80000000L
-//DB_DEBUG4
-#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0
-#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1
-#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2
-#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3
-#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF__SHIFT 0x4
-#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT 0x5
-#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE__SHIFT 0x6
-#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN__SHIFT 0x7
-#define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS__SHIFT 0x8
-#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR__SHIFT 0x9
-#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR__SHIFT 0xa
-#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR__SHIFT 0xb
-#define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK__SHIFT 0xc
-#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP__SHIFT 0xd
-#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION__SHIFT 0xe
-#define DB_DEBUG4__DISABLE_TS_WRITE_L0__SHIFT 0xf
-#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE__SHIFT 0x10
-#define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT__SHIFT 0x11
-#define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT__SHIFT 0x12
-#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x13
-#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x00000001L
-#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x00000002L
-#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x00000004L
-#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x00000008L
-#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF_MASK 0x00000010L
-#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK 0x00000020L
-#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE_MASK 0x00000040L
-#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN_MASK 0x00000080L
-#define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS_MASK 0x00000100L
-#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR_MASK 0x00000200L
-#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR_MASK 0x00000400L
-#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR_MASK 0x00000800L
-#define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK_MASK 0x00001000L
-#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP_MASK 0x00002000L
-#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION_MASK 0x00004000L
-#define DB_DEBUG4__DISABLE_TS_WRITE_L0_MASK 0x00008000L
-#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE_MASK 0x00010000L
-#define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT_MASK 0x00020000L
-#define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT_MASK 0x00040000L
-#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0xFFF80000L
-//DB_CREDIT_LIMIT
-#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0
-#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5
-#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa
-#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18
-#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x0000001FL
-#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x000003E0L
-#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x00001C00L
-#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7F000000L
-//DB_WATERMARKS
-#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0
-#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x5
-#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0xb
-#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0xf
-#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x14
-#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x1e
-#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x1f
-#define DB_WATERMARKS__DEPTH_FREE_MASK 0x0000001FL
-#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x000007E0L
-#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x00007800L
-#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0x000F8000L
-#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x0FF00000L
-#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000L
-#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000L
-//DB_SUBTILE_CONTROL
-#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0
-#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2
-#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4
-#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6
-#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8
-#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa
-#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc
-#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe
-#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10
-#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12
-#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x00000003L
-#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0x0000000CL
-#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x00000030L
-#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0x000000C0L
-#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x00000300L
-#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0x00000C00L
-#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x00003000L
-#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0x0000C000L
-#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x00030000L
-#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0x000C0000L
-//DB_FREE_CACHELINES
-#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0
-#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x7
-#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0xe
-#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x14
-#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x18
-#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x0000007FL
-#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x00003F80L
-#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x000FC000L
-#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x00F00000L
-#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xFF000000L
-//DB_FIFO_DEPTH1
-#define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS__SHIFT 0x0
-#define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS__SHIFT 0x5
-#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa
-#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x10
-#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x15
-#define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS_MASK 0x0000001FL
-#define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS_MASK 0x000003E0L
-#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0x0000FC00L
-#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x001F0000L
-#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1FE00000L
-//DB_FIFO_DEPTH2
-#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0
-#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8
-#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0xf
-#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19
-#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0x000000FFL
-#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x00007F00L
-#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x01FF8000L
-#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xFE000000L
-//DB_EXCEPTION_CONTROL
-#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE__SHIFT 0x0
-#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE__SHIFT 0x1
-#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE__SHIFT 0x2
-#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE_MASK 0x00000001L
-#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE_MASK 0x00000002L
-#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE_MASK 0x00000004L
-//DB_RING_CONTROL
-#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0
-#define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x00000003L
-//DB_MEM_ARB_WATERMARKS
-#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK__SHIFT 0x0
-#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK__SHIFT 0x8
-#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK__SHIFT 0x10
-#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK__SHIFT 0x18
-#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK_MASK 0x00000007L
-#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK_MASK 0x00000700L
-#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK_MASK 0x00070000L
-#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK_MASK 0x07000000L
-//DB_RMI_CACHE_POLICY
-#define DB_RMI_CACHE_POLICY__Z_RD__SHIFT 0x0
-#define DB_RMI_CACHE_POLICY__S_RD__SHIFT 0x1
-#define DB_RMI_CACHE_POLICY__HTILE_RD__SHIFT 0x2
-#define DB_RMI_CACHE_POLICY__Z_WR__SHIFT 0x8
-#define DB_RMI_CACHE_POLICY__S_WR__SHIFT 0x9
-#define DB_RMI_CACHE_POLICY__HTILE_WR__SHIFT 0xa
-#define DB_RMI_CACHE_POLICY__ZPCPSD_WR__SHIFT 0xb
-#define DB_RMI_CACHE_POLICY__CC_RD__SHIFT 0x10
-#define DB_RMI_CACHE_POLICY__FMASK_RD__SHIFT 0x11
-#define DB_RMI_CACHE_POLICY__CMASK_RD__SHIFT 0x12
-#define DB_RMI_CACHE_POLICY__DCC_RD__SHIFT 0x13
-#define DB_RMI_CACHE_POLICY__CC_WR__SHIFT 0x18
-#define DB_RMI_CACHE_POLICY__FMASK_WR__SHIFT 0x19
-#define DB_RMI_CACHE_POLICY__CMASK_WR__SHIFT 0x1a
-#define DB_RMI_CACHE_POLICY__DCC_WR__SHIFT 0x1b
-#define DB_RMI_CACHE_POLICY__Z_RD_MASK 0x00000001L
-#define DB_RMI_CACHE_POLICY__S_RD_MASK 0x00000002L
-#define DB_RMI_CACHE_POLICY__HTILE_RD_MASK 0x00000004L
-#define DB_RMI_CACHE_POLICY__Z_WR_MASK 0x00000100L
-#define DB_RMI_CACHE_POLICY__S_WR_MASK 0x00000200L
-#define DB_RMI_CACHE_POLICY__HTILE_WR_MASK 0x00000400L
-#define DB_RMI_CACHE_POLICY__ZPCPSD_WR_MASK 0x00000800L
-#define DB_RMI_CACHE_POLICY__CC_RD_MASK 0x00010000L
-#define DB_RMI_CACHE_POLICY__FMASK_RD_MASK 0x00020000L
-#define DB_RMI_CACHE_POLICY__CMASK_RD_MASK 0x00040000L
-#define DB_RMI_CACHE_POLICY__DCC_RD_MASK 0x00080000L
-#define DB_RMI_CACHE_POLICY__CC_WR_MASK 0x01000000L
-#define DB_RMI_CACHE_POLICY__FMASK_WR_MASK 0x02000000L
-#define DB_RMI_CACHE_POLICY__CMASK_WR_MASK 0x04000000L
-#define DB_RMI_CACHE_POLICY__DCC_WR_MASK 0x08000000L
-//DB_DFSM_CONFIG
-#define DB_DFSM_CONFIG__BYPASS_DFSM__SHIFT 0x0
-#define DB_DFSM_CONFIG__DISABLE_PUNCHOUT__SHIFT 0x1
-#define DB_DFSM_CONFIG__DISABLE_POPS__SHIFT 0x2
-#define DB_DFSM_CONFIG__FORCE_FLUSH__SHIFT 0x3
-#define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH__SHIFT 0x8
-#define DB_DFSM_CONFIG__BYPASS_DFSM_MASK 0x00000001L
-#define DB_DFSM_CONFIG__DISABLE_PUNCHOUT_MASK 0x00000002L
-#define DB_DFSM_CONFIG__DISABLE_POPS_MASK 0x00000004L
-#define DB_DFSM_CONFIG__FORCE_FLUSH_MASK 0x00000008L
-#define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH_MASK 0x00007F00L
-//DB_DFSM_WATERMARK
-#define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK__SHIFT 0x0
-#define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK__SHIFT 0x10
-#define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK_MASK 0x0000FFFFL
-#define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK_MASK 0xFFFF0000L
-//DB_DFSM_TILES_IN_FLIGHT
-#define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0
-#define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT__SHIFT 0x10
-#define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL
-#define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT_MASK 0xFFFF0000L
-//DB_DFSM_PRIMS_IN_FLIGHT
-#define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0
-#define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT__SHIFT 0x10
-#define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL
-#define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT_MASK 0xFFFF0000L
-//DB_DFSM_WATCHDOG
-#define DB_DFSM_WATCHDOG__TIMER_TARGET__SHIFT 0x0
-#define DB_DFSM_WATCHDOG__TIMER_TARGET_MASK 0xFFFFFFFFL
-//DB_DFSM_FLUSH_ENABLE
-#define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS__SHIFT 0x0
-#define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU__SHIFT 0x18
-#define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS__SHIFT 0x1c
-#define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS_MASK 0x000003FFL
-#define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU_MASK 0x0F000000L
-#define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS_MASK 0xF0000000L
-//DB_DFSM_FLUSH_AUX_EVENT
-#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A__SHIFT 0x0
-#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B__SHIFT 0x8
-#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C__SHIFT 0x10
-#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D__SHIFT 0x18
-#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A_MASK 0x000000FFL
-#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B_MASK 0x0000FF00L
-#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C_MASK 0x00FF0000L
-#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D_MASK 0xFF000000L
-//CC_RB_REDUNDANCY
-#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
-#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
-#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
-#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
-#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L
-#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L
-#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L
-#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L
-//CC_RB_BACKEND_DISABLE
-#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
-#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L
-//GB_ADDR_CONFIG
-#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
-#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
-#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6
-#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
-#define GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
-#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
-#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
-#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15
-#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
-#define GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a
-#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
-#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
-#define GB_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f
-#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
-#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
-#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
-#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
-#define GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
-#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
-#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
-#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L
-#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
-#define GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L
-#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
-#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
-#define GB_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L
-//GB_BACKEND_MAP
-#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0
-#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xFFFFFFFFL
-//GB_GPU_ID
-#define GB_GPU_ID__GPU_ID__SHIFT 0x0
-#define GB_GPU_ID__GPU_ID_MASK 0x0000000FL
-//CC_RB_DAISY_CHAIN
-#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0
-#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4
-#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8
-#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc
-#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10
-#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14
-#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18
-#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c
-#define CC_RB_DAISY_CHAIN__RB_0_MASK 0x0000000FL
-#define CC_RB_DAISY_CHAIN__RB_1_MASK 0x000000F0L
-#define CC_RB_DAISY_CHAIN__RB_2_MASK 0x00000F00L
-#define CC_RB_DAISY_CHAIN__RB_3_MASK 0x0000F000L
-#define CC_RB_DAISY_CHAIN__RB_4_MASK 0x000F0000L
-#define CC_RB_DAISY_CHAIN__RB_5_MASK 0x00F00000L
-#define CC_RB_DAISY_CHAIN__RB_6_MASK 0x0F000000L
-#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xF0000000L
-//GB_ADDR_CONFIG_READ
-#define GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0
-#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
-#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6
-#define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8
-#define GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc
-#define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
-#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13
-#define GB_ADDR_CONFIG_READ__NUM_GPUS__SHIFT 0x15
-#define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE__SHIFT 0x18
-#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a
-#define GB_ADDR_CONFIG_READ__ROW_SIZE__SHIFT 0x1c
-#define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES__SHIFT 0x1e
-#define GB_ADDR_CONFIG_READ__SE_ENABLE__SHIFT 0x1f
-#define GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L
-#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
-#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
-#define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
-#define GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L
-#define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
-#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L
-#define GB_ADDR_CONFIG_READ__NUM_GPUS_MASK 0x00E00000L
-#define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
-#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L
-#define GB_ADDR_CONFIG_READ__ROW_SIZE_MASK 0x30000000L
-#define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES_MASK 0x40000000L
-#define GB_ADDR_CONFIG_READ__SE_ENABLE_MASK 0x80000000L
-//GB_TILE_MODE0
-#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE1
-#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE2
-#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE3
-#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE4
-#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE5
-#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE6
-#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE7
-#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE8
-#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE9
-#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE10
-#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE11
-#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE12
-#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE13
-#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE14
-#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE15
-#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE16
-#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE17
-#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE18
-#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE19
-#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE20
-#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE21
-#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE22
-#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE23
-#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE24
-#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE25
-#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE26
-#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE27
-#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE28
-#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE29
-#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE30
-#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_TILE_MODE31
-#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x0000003CL
-#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x000007C0L
-#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x00003800L
-#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
-#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x06000000L
-//GB_MACROTILE_MODE0
-#define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x00000003L
-#define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0x0000000CL
-#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x00000030L
-#define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0x000000C0L
-//GB_MACROTILE_MODE1
-#define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x00000003L
-#define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0x0000000CL
-#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x00000030L
-#define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0x000000C0L
-//GB_MACROTILE_MODE2
-#define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x00000003L
-#define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0x0000000CL
-#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x00000030L
-#define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0x000000C0L
-//GB_MACROTILE_MODE3
-#define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x00000003L
-#define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0x0000000CL
-#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x00000030L
-#define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0x000000C0L
-//GB_MACROTILE_MODE4
-#define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x00000003L
-#define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0x0000000CL
-#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x00000030L
-#define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0x000000C0L
-//GB_MACROTILE_MODE5
-#define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x00000003L
-#define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0x0000000CL
-#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x00000030L
-#define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0x000000C0L
-//GB_MACROTILE_MODE6
-#define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x00000003L
-#define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0x0000000CL
-#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x00000030L
-#define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0x000000C0L
-//GB_MACROTILE_MODE7
-#define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x00000003L
-#define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0x0000000CL
-#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x00000030L
-#define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0x000000C0L
-//GB_MACROTILE_MODE8
-#define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x00000003L
-#define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0x0000000CL
-#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x00000030L
-#define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0x000000C0L
-//GB_MACROTILE_MODE9
-#define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x00000003L
-#define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0x0000000CL
-#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x00000030L
-#define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0x000000C0L
-//GB_MACROTILE_MODE10
-#define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x00000003L
-#define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0x0000000CL
-#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x00000030L
-#define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0x000000C0L
-//GB_MACROTILE_MODE11
-#define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x00000003L
-#define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0x0000000CL
-#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x00000030L
-#define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0x000000C0L
-//GB_MACROTILE_MODE12
-#define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x00000003L
-#define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0x0000000CL
-#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x00000030L
-#define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0x000000C0L
-//GB_MACROTILE_MODE13
-#define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x00000003L
-#define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0x0000000CL
-#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x00000030L
-#define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0x000000C0L
-//GB_MACROTILE_MODE14
-#define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x00000003L
-#define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0x0000000CL
-#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x00000030L
-#define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0x000000C0L
-//GB_MACROTILE_MODE15
-#define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x00000003L
-#define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0x0000000CL
-#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x00000030L
-#define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0x000000C0L
-//CB_HW_CONTROL
-#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0
-#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6
-#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc
-#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10
-#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12
-#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13
-#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14
-#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15
-#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16
-#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17
-#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18
-#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19
-#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a
-#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b
-#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c
-#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d
-#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e
-#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f
-#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0x0000000FL
-#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x000003C0L
-#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0x0000F000L
-#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x00010000L
-#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x00040000L
-#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x00080000L
-#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x00100000L
-#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x00200000L
-#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x00400000L
-#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x00800000L
-#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x01000000L
-#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x02000000L
-#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x04000000L
-#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x08000000L
-#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000L
-#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000L
-#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000L
-#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000L
-//CB_HW_CONTROL_1
-#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0
-#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5
-#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb
-#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11
-#define CB_HW_CONTROL_1__RMI_CREDITS__SHIFT 0x1a
-#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x0000001FL
-#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x000007E0L
-#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x0001F800L
-#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x03FE0000L
-#define CB_HW_CONTROL_1__RMI_CREDITS_MASK 0xFC000000L
-//CB_HW_CONTROL_2
-#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0
-#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8
-#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf
-#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT 0x18
-#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x1c
-#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0x000000FFL
-#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x00007F00L
-#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x007F8000L
-#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK 0x0F000000L
-#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xF0000000L
-//CB_HW_CONTROL_3
-#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0
-#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT 0x1
-#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT 0x2
-#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT 0x3
-#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT 0x4
-#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT 0x5
-#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD__SHIFT 0x6
-#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT 0x7
-#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT 0x8
-#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT 0x9
-#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT 0xa
-#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION__SHIFT 0xb
-#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967__SHIFT 0xc
-#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657__SHIFT 0xd
-#define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542__SHIFT 0xe
-#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH__SHIFT 0xf
-#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH__SHIFT 0x10
-#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC__SHIFT 0x11
-#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC__SHIFT 0x12
-#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC__SHIFT 0x13
-#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM__SHIFT 0x14
-#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC__SHIFT 0x15
-#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC__SHIFT 0x16
-#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC__SHIFT 0x17
-#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM__SHIFT 0x18
-#define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT__SHIFT 0x19
-#define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING__SHIFT 0x1a
-#define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX__SHIFT 0x1b
-#define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS__SHIFT 0x1c
-#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x00000001L
-#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK 0x00000002L
-#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK 0x00000004L
-#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK 0x00000008L
-#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK 0x00000010L
-#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK 0x00000020L
-#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD_MASK 0x00000040L
-#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK 0x00000080L
-#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK 0x00000100L
-#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK 0x00000200L
-#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK 0x00000400L
-#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION_MASK 0x00000800L
-#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967_MASK 0x00001000L
-#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657_MASK 0x00002000L
-#define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542_MASK 0x00004000L
-#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH_MASK 0x00008000L
-#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH_MASK 0x00010000L
-#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC_MASK 0x00020000L
-#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC_MASK 0x00040000L
-#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC_MASK 0x00080000L
-#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM_MASK 0x00100000L
-#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC_MASK 0x00200000L
-#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC_MASK 0x00400000L
-#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC_MASK 0x00800000L
-#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM_MASK 0x01000000L
-#define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT_MASK 0x02000000L
-#define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING_MASK 0x04000000L
-#define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX_MASK 0x08000000L
-#define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS_MASK 0x30000000L
-//CB_HW_MEM_ARBITER_RD
-#define CB_HW_MEM_ARBITER_RD__MODE__SHIFT 0x0
-#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE__SHIFT 0x2
-#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE__SHIFT 0x6
-#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC__SHIFT 0xa
-#define CB_HW_MEM_ARBITER_RD__WEIGHT_FC__SHIFT 0xc
-#define CB_HW_MEM_ARBITER_RD__WEIGHT_CM__SHIFT 0xe
-#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC__SHIFT 0x10
-#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS__SHIFT 0x12
-#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS__SHIFT 0x14
-#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS__SHIFT 0x16
-#define CB_HW_MEM_ARBITER_RD__SCALE_AGE__SHIFT 0x17
-#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT__SHIFT 0x1a
-#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d
-#define CB_HW_MEM_ARBITER_RD__MODE_MASK 0x00000003L
-#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE_MASK 0x0000003CL
-#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE_MASK 0x000003C0L
-#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC_MASK 0x00000C00L
-#define CB_HW_MEM_ARBITER_RD__WEIGHT_FC_MASK 0x00003000L
-#define CB_HW_MEM_ARBITER_RD__WEIGHT_CM_MASK 0x0000C000L
-#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC_MASK 0x00030000L
-#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS_MASK 0x000C0000L
-#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS_MASK 0x00300000L
-#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS_MASK 0x00400000L
-#define CB_HW_MEM_ARBITER_RD__SCALE_AGE_MASK 0x03800000L
-#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT_MASK 0x1C000000L
-#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L
-//CB_HW_MEM_ARBITER_WR
-#define CB_HW_MEM_ARBITER_WR__MODE__SHIFT 0x0
-#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE__SHIFT 0x2
-#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE__SHIFT 0x6
-#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC__SHIFT 0xa
-#define CB_HW_MEM_ARBITER_WR__WEIGHT_FC__SHIFT 0xc
-#define CB_HW_MEM_ARBITER_WR__WEIGHT_CM__SHIFT 0xe
-#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC__SHIFT 0x10
-#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS__SHIFT 0x12
-#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS__SHIFT 0x14
-#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK__SHIFT 0x16
-#define CB_HW_MEM_ARBITER_WR__SCALE_AGE__SHIFT 0x17
-#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT__SHIFT 0x1a
-#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d
-#define CB_HW_MEM_ARBITER_WR__MODE_MASK 0x00000003L
-#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE_MASK 0x0000003CL
-#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE_MASK 0x000003C0L
-#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC_MASK 0x00000C00L
-#define CB_HW_MEM_ARBITER_WR__WEIGHT_FC_MASK 0x00003000L
-#define CB_HW_MEM_ARBITER_WR__WEIGHT_CM_MASK 0x0000C000L
-#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC_MASK 0x00030000L
-#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS_MASK 0x000C0000L
-#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS_MASK 0x00300000L
-#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK_MASK 0x00400000L
-#define CB_HW_MEM_ARBITER_WR__SCALE_AGE_MASK 0x03800000L
-#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT_MASK 0x1C000000L
-#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L
-//CB_DCC_CONFIG
-#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT 0x0
-#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT 0x5
-#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT 0x6
-#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT 0x8
-#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT 0x10
-#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT__SHIFT 0x18
-#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT 0x1c
-#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK 0x0000001FL
-#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK 0x00000020L
-#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK 0x00000040L
-#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK 0x0000FF00L
-#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK 0x007F0000L
-#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT_MASK 0x0F000000L
-#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK 0xF0000000L
-//GC_USER_RB_REDUNDANCY
-#define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
-#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
-#define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
-#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
-#define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L
-#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L
-#define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L
-#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L
-//GC_USER_RB_BACKEND_DISABLE
-#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
-#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L
-
-
-// addressBlock: gc_ea_gceadec2
-//GCEA_EDC_CNT
-#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0
-#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2
-#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4
-#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6
-#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8
-#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa
-#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc
-#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe
-#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10
-#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12
-#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14
-#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16
-#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18
-#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a
-#define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c
-#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
-#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
-#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
-#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
-#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
-#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
-#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L
-#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L
-#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L
-#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L
-#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L
-#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L
-#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L
-#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L
-#define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L
-//GCEA_EDC_CNT2
-#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0
-#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2
-#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4
-#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6
-#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8
-#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa
-#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc
-#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe
-#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
-#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
-#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
-#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
-#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
-#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
-#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L
-#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L
-//GCEA_DSM_CNTL
-#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0
-#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
-#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3
-#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5
-#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6
-#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8
-#define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9
-#define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb
-#define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc
-#define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
-#define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf
-#define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11
-#define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12
-#define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14
-#define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15
-#define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17
-#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
-#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
-#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L
-#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L
-#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L
-#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
-#define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L
-#define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
-#define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L
-#define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
-#define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L
-#define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L
-#define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L
-#define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L
-#define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L
-#define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L
-//GCEA_DSM_CNTLA
-#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0
-#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
-#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3
-#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5
-#define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6
-#define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8
-#define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9
-#define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb
-#define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc
-#define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
-#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf
-#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11
-#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12
-#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14
-#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
-#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
-#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L
-#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L
-#define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L
-#define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
-#define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L
-#define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
-#define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L
-#define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
-#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L
-#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L
-#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L
-#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L
-//GCEA_DSM_CNTLB
-//GCEA_DSM_CNTL2
-#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2
-#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3
-#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5
-#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6
-#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8
-#define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9
-#define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb
-#define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc
-#define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe
-#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf
-#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11
-#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12
-#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14
-#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15
-#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17
-#define GCEA_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
-#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L
-#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L
-#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
-#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L
-#define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L
-#define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L
-#define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
-#define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L
-#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L
-#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L
-#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L
-#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L
-#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L
-#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L
-#define GCEA_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
-//GCEA_DSM_CNTL2A
-#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2
-#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3
-#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5
-#define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6
-#define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8
-#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9
-#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb
-#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc
-#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe
-#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf
-#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11
-#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12
-#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14
-#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L
-#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L
-#define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
-#define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L
-#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L
-#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L
-#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
-#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L
-#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L
-#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L
-#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L
-#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L
-//GCEA_DSM_CNTL2B
-//GCEA_TCC_XBR_CREDITS
-#define GCEA_TCC_XBR_CREDITS__DRAM_RD_LIMIT__SHIFT 0x0
-#define GCEA_TCC_XBR_CREDITS__DRAM_RD_RESERVE__SHIFT 0x6
-#define GCEA_TCC_XBR_CREDITS__IO_RD_LIMIT__SHIFT 0x8
-#define GCEA_TCC_XBR_CREDITS__IO_RD_RESERVE__SHIFT 0xe
-#define GCEA_TCC_XBR_CREDITS__DRAM_WR_LIMIT__SHIFT 0x10
-#define GCEA_TCC_XBR_CREDITS__DRAM_WR_RESERVE__SHIFT 0x16
-#define GCEA_TCC_XBR_CREDITS__IO_WR_LIMIT__SHIFT 0x18
-#define GCEA_TCC_XBR_CREDITS__IO_WR_RESERVE__SHIFT 0x1e
-#define GCEA_TCC_XBR_CREDITS__DRAM_RD_LIMIT_MASK 0x0000003FL
-#define GCEA_TCC_XBR_CREDITS__DRAM_RD_RESERVE_MASK 0x000000C0L
-#define GCEA_TCC_XBR_CREDITS__IO_RD_LIMIT_MASK 0x00003F00L
-#define GCEA_TCC_XBR_CREDITS__IO_RD_RESERVE_MASK 0x0000C000L
-#define GCEA_TCC_XBR_CREDITS__DRAM_WR_LIMIT_MASK 0x003F0000L
-#define GCEA_TCC_XBR_CREDITS__DRAM_WR_RESERVE_MASK 0x00C00000L
-#define GCEA_TCC_XBR_CREDITS__IO_WR_LIMIT_MASK 0x3F000000L
-#define GCEA_TCC_XBR_CREDITS__IO_WR_RESERVE_MASK 0xC0000000L
-//GCEA_TCC_XBR_MAXBURST
-#define GCEA_TCC_XBR_MAXBURST__DRAM_RD__SHIFT 0x0
-#define GCEA_TCC_XBR_MAXBURST__IO_RD__SHIFT 0x4
-#define GCEA_TCC_XBR_MAXBURST__DRAM_WR__SHIFT 0x8
-#define GCEA_TCC_XBR_MAXBURST__IO_WR__SHIFT 0xc
-#define GCEA_TCC_XBR_MAXBURST__DRAM_RD_MASK 0x0000000FL
-#define GCEA_TCC_XBR_MAXBURST__IO_RD_MASK 0x000000F0L
-#define GCEA_TCC_XBR_MAXBURST__DRAM_WR_MASK 0x00000F00L
-#define GCEA_TCC_XBR_MAXBURST__IO_WR_MASK 0x0000F000L
-//GCEA_PROBE_CNTL
-#define GCEA_PROBE_CNTL__REQ2RSP_DELAY__SHIFT 0x0
-#define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE__SHIFT 0x5
-#define GCEA_PROBE_CNTL__REQ2RSP_DELAY_MASK 0x0000001FL
-#define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE_MASK 0x00000020L
-//GCEA_PROBE_MAP
-#define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTTCC__SHIFT 0x0
-#define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTTCC__SHIFT 0x1
-#define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTTCC__SHIFT 0x2
-#define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTTCC__SHIFT 0x3
-#define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTTCC__SHIFT 0x4
-#define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTTCC__SHIFT 0x5
-#define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTTCC__SHIFT 0x6
-#define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTTCC__SHIFT 0x7
-#define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTTCC__SHIFT 0x8
-#define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTTCC__SHIFT 0x9
-#define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTTCC__SHIFT 0xa
-#define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTTCC__SHIFT 0xb
-#define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTTCC__SHIFT 0xc
-#define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTTCC__SHIFT 0xd
-#define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTTCC__SHIFT 0xe
-#define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTTCC__SHIFT 0xf
-#define GCEA_PROBE_MAP__INTLV_SIZE__SHIFT 0x10
-#define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTTCC_MASK 0x00000001L
-#define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTTCC_MASK 0x00000002L
-#define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTTCC_MASK 0x00000004L
-#define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTTCC_MASK 0x00000008L
-#define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTTCC_MASK 0x00000010L
-#define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTTCC_MASK 0x00000020L
-#define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTTCC_MASK 0x00000040L
-#define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTTCC_MASK 0x00000080L
-#define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTTCC_MASK 0x00000100L
-#define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTTCC_MASK 0x00000200L
-#define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTTCC_MASK 0x00000400L
-#define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTTCC_MASK 0x00000800L
-#define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTTCC_MASK 0x00001000L
-#define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTTCC_MASK 0x00002000L
-#define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTTCC_MASK 0x00004000L
-#define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTTCC_MASK 0x00008000L
-#define GCEA_PROBE_MAP__INTLV_SIZE_MASK 0x00030000L
-//GCEA_ERR_STATUS
-#define GCEA_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0
-#define GCEA_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4
-#define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0x8
-#define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0x9
-#define GCEA_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xa
-#define GCEA_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL
-#define GCEA_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L
-#define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000100L
-#define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000200L
-#define GCEA_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00000400L
-//GCEA_MISC2
-#define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0
-#define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1
-#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2
-#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7
-#define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L
-#define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L
-#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL
-#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L
-//GCEA_SDP_BACKDOOR_CMDCREDITS0
-#define GCEA_SDP_BACKDOOR_CMDCREDITS0__CREDITS_RECEIVED__SHIFT 0x0
-#define GCEA_SDP_BACKDOOR_CMDCREDITS0__CREDITS_RECEIVED_MASK 0xFFFFFFFFL
-//GCEA_SDP_BACKDOOR_CMDCREDITS1
-#define GCEA_SDP_BACKDOOR_CMDCREDITS1__CREDITS_RECEIVED__SHIFT 0x0
-#define GCEA_SDP_BACKDOOR_CMDCREDITS1__CREDITS_RECEIVED_MASK 0x7FFFFFFFL
-//GCEA_SDP_BACKDOOR_DATACREDITS0
-#define GCEA_SDP_BACKDOOR_DATACREDITS0__CREDITS_RECEIVED__SHIFT 0x0
-#define GCEA_SDP_BACKDOOR_DATACREDITS0__CREDITS_RECEIVED_MASK 0xFFFFFFFFL
-//GCEA_SDP_BACKDOOR_DATACREDITS1
-#define GCEA_SDP_BACKDOOR_DATACREDITS1__CREDITS_RECEIVED__SHIFT 0x0
-#define GCEA_SDP_BACKDOOR_DATACREDITS1__CREDITS_RECEIVED_MASK 0x7FFFFFFFL
-//GCEA_SDP_BACKDOOR_MISCCREDITS
-#define GCEA_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED__SHIFT 0x0
-#define GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED__SHIFT 0x8
-#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED__SHIFT 0x10
-#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED__SHIFT 0x17
-#define GCEA_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED_MASK 0x000000FFL
-#define GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED_MASK 0x0000FF00L
-#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED_MASK 0x007F0000L
-#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED_MASK 0x3F800000L
-//GCEA_SDP_ENABLE
-#define GCEA_SDP_ENABLE__ENABLE__SHIFT 0x0
-#define GCEA_SDP_ENABLE__ENABLE_MASK 0x00000001L
-
-
-// addressBlock: gc_rmi_rmidec
-//RMI_GENERAL_CNTL
-#define RMI_GENERAL_CNTL__BURST_DISABLE__SHIFT 0x0
-#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE__SHIFT 0x1
-#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG__SHIFT 0x11
-#define RMI_GENERAL_CNTL__RB0_HARVEST_EN__SHIFT 0x13
-#define RMI_GENERAL_CNTL__RB1_HARVEST_EN__SHIFT 0x14
-#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE__SHIFT 0x15
-#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE__SHIFT 0x19
-#define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK__SHIFT 0x1a
-#define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK__SHIFT 0x1b
-#define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK__SHIFT 0x1c
-#define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK__SHIFT 0x1d
-#define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK__SHIFT 0x1e
-#define RMI_GENERAL_CNTL__BURST_DISABLE_MASK 0x00000001L
-#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE_MASK 0x0001FFFEL
-#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_MASK 0x00060000L
-#define RMI_GENERAL_CNTL__RB0_HARVEST_EN_MASK 0x00080000L
-#define RMI_GENERAL_CNTL__RB1_HARVEST_EN_MASK 0x00100000L
-#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE_MASK 0x01E00000L
-#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE_MASK 0x02000000L
-#define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK_MASK 0x04000000L
-#define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK_MASK 0x08000000L
-#define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK_MASK 0x10000000L
-#define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK_MASK 0x20000000L
-#define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK_MASK 0x40000000L
-//RMI_GENERAL_CNTL1
-#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE__SHIFT 0x0
-#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE__SHIFT 0x4
-#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE__SHIFT 0x6
-#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK__SHIFT 0x8
-#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE__SHIFT 0x9
-#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE__SHIFT 0xa
-#define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN__SHIFT 0xb
-#define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN__SHIFT 0xc
-#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE_MASK 0x0000000FL
-#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE_MASK 0x00000030L
-#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE_MASK 0x000000C0L
-#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK_MASK 0x00000100L
-#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE_MASK 0x00000200L
-#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_MASK 0x00000400L
-#define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN_MASK 0x00000800L
-#define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN_MASK 0x00001000L
-//RMI_GENERAL_STATUS
-#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED__SHIFT 0x0
-#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR__SHIFT 0x1
-#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR__SHIFT 0x2
-#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR__SHIFT 0x3
-#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR__SHIFT 0x4
-#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY__SHIFT 0x5
-#define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY__SHIFT 0x6
-#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY__SHIFT 0x7
-#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY__SHIFT 0x8
-#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY__SHIFT 0x9
-#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT 0xa
-#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xb
-#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xc
-#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY__SHIFT 0xd
-#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY__SHIFT 0xe
-#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY__SHIFT 0xf
-#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x10
-#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x11
-#define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY__SHIFT 0x12
-#define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY__SHIFT 0x13
-#define RMI_GENERAL_STATUS__RMI_XNACK_BUSY__SHIFT 0x14
-#define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED__SHIFT 0x15
-#define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY__SHIFT 0x1d
-#define RMI_GENERAL_STATUS__XNACK_FIFO_FULL__SHIFT 0x1e
-#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR__SHIFT 0x1f
-#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED_MASK 0x00000001L
-#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR_MASK 0x00000002L
-#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR_MASK 0x00000004L
-#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR_MASK 0x00000008L
-#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR_MASK 0x00000010L
-#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY_MASK 0x00000020L
-#define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY_MASK 0x00000040L
-#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY_MASK 0x00000080L
-#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY_MASK 0x00000100L
-#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY_MASK 0x00000200L
-#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY_MASK 0x00000400L
-#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00000800L
-#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00001000L
-#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY_MASK 0x00002000L
-#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY_MASK 0x00004000L
-#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY_MASK 0x00008000L
-#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00010000L
-#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00020000L
-#define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY_MASK 0x00040000L
-#define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY_MASK 0x00080000L
-#define RMI_GENERAL_STATUS__RMI_XNACK_BUSY_MASK 0x00100000L
-#define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED_MASK 0x1FE00000L
-#define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY_MASK 0x20000000L
-#define RMI_GENERAL_STATUS__XNACK_FIFO_FULL_MASK 0x40000000L
-#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK 0x80000000L
-//RMI_SUBBLOCK_STATUS0
-#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0__SHIFT 0x0
-#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0__SHIFT 0x7
-#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0__SHIFT 0x8
-#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1__SHIFT 0x9
-#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1__SHIFT 0x10
-#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1__SHIFT 0x11
-#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT__SHIFT 0x12
-#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0_MASK 0x0000007FL
-#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0_MASK 0x00000080L
-#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0_MASK 0x00000100L
-#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1_MASK 0x0000FE00L
-#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1_MASK 0x00010000L
-#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1_MASK 0x00020000L
-#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT_MASK 0x0FFC0000L
-//RMI_SUBBLOCK_STATUS1
-#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE__SHIFT 0x0
-#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT 0xa
-#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT__SHIFT 0x14
-#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE_MASK 0x000003FFL
-#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE_MASK 0x000FFC00L
-#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT_MASK 0x3FF00000L
-//RMI_SUBBLOCK_STATUS2
-#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED__SHIFT 0x0
-#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED__SHIFT 0x9
-#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED_MASK 0x000001FFL
-#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED_MASK 0x0003FE00L
-//RMI_SUBBLOCK_STATUS3
-#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL__SHIFT 0x0
-#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT 0xa
-#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL_MASK 0x000003FFL
-#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL_MASK 0x000FFC00L
-//RMI_XBAR_CONFIG
-#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE__SHIFT 0x0
-#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE__SHIFT 0x2
-#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE__SHIFT 0x6
-#define RMI_XBAR_CONFIG__ARBITER_DIS__SHIFT 0x7
-#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ__SHIFT 0x8
-#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE__SHIFT 0xc
-#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0__SHIFT 0xd
-#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1__SHIFT 0xe
-#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE_MASK 0x00000003L
-#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE_MASK 0x0000003CL
-#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE_MASK 0x00000040L
-#define RMI_XBAR_CONFIG__ARBITER_DIS_MASK 0x00000080L
-#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_MASK 0x00000F00L
-#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE_MASK 0x00001000L
-#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0_MASK 0x00002000L
-#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1_MASK 0x00004000L
-//RMI_PROBE_POP_LOGIC_CNTL
-#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH__SHIFT 0x0
-#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS__SHIFT 0x7
-#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2__SHIFT 0x8
-#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT 0xa
-#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS__SHIFT 0x11
-#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH_MASK 0x0000007FL
-#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS_MASK 0x00000080L
-#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2_MASK 0x00000300L
-#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH_MASK 0x0001FC00L
-#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS_MASK 0x00020000L
-//RMI_UTC_XNACK_N_MISC_CNTL
-#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC__SHIFT 0x0
-#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE__SHIFT 0x8
-#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE__SHIFT 0xc
-#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE__SHIFT 0xd
-#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC_MASK 0x000000FFL
-#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE_MASK 0x00000F00L
-#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE_MASK 0x00001000L
-#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE_MASK 0x00002000L
-//RMI_DEMUX_CNTL
-#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL__SHIFT 0x0
-#define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x1
-#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x4
-#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x6
-#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE__SHIFT 0xe
-#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL__SHIFT 0x10
-#define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x11
-#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x14
-#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x16
-#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE__SHIFT 0x1e
-#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_MASK 0x00000001L
-#define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000002L
-#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE_MASK 0x00000030L
-#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE_MASK 0x00003FC0L
-#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_MASK 0x0000C000L
-#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_MASK 0x00010000L
-#define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00020000L
-#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00300000L
-#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE_MASK 0x3FC00000L
-#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_MASK 0xC0000000L
-//RMI_UTCL1_CNTL1
-#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
-#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
-#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
-#define RMI_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
-#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
-#define RMI_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
-#define RMI_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10
-#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
-#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
-#define RMI_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13
-#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17
-#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18
-#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
-#define RMI_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
-#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
-#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
-#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
-#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
-#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
-#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
-#define RMI_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
-#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
-#define RMI_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
-#define RMI_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L
-#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
-#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
-#define RMI_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L
-#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L
-#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L
-#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
-#define RMI_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
-#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
-#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
-#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
-//RMI_UTCL1_CNTL2
-#define RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT 0x0
-#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
-#define RMI_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
-#define RMI_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb
-#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
-#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
-#define RMI_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
-#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
-#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE__SHIFT 0x10
-#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
-#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR__SHIFT 0x13
-#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID__SHIFT 0x14
-#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID__SHIFT 0x15
-#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ__SHIFT 0x19
-#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
-#define RMI_UTCL1_CNTL2__UTC_SPARE_MASK 0x000000FFL
-#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
-#define RMI_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
-#define RMI_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L
-#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
-#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
-#define RMI_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
-#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
-#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE_MASK 0x00030000L
-#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
-#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK 0x00080000L
-#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
-#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID_MASK 0x01E00000L
-#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ_MASK 0x02000000L
-#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
-//RMI_UTC_UNIT_CONFIG
-//RMI_TCIW_FORMATTER0_CNTL
-#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE__SHIFT 0x0
-#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW__SHIFT 0x1
-#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9
-#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA__SHIFT 0x13
-#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b
-#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE__SHIFT 0x1c
-#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS__SHIFT 0x1d
-#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST__SHIFT 0x1e
-#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA__SHIFT 0x1f
-#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE_MASK 0x00000001L
-#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW_MASK 0x000001FEL
-#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L
-#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_MASK 0x07F80000L
-#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L
-#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE_MASK 0x10000000L
-#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS_MASK 0x20000000L
-#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST_MASK 0x40000000L
-#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA_MASK 0x80000000L
-//RMI_TCIW_FORMATTER1_CNTL
-#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE__SHIFT 0x0
-#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW__SHIFT 0x1
-#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9
-#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA__SHIFT 0x13
-#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b
-#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE__SHIFT 0x1c
-#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS__SHIFT 0x1d
-#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST__SHIFT 0x1e
-#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA__SHIFT 0x1f
-#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE_MASK 0x00000001L
-#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW_MASK 0x000001FEL
-#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L
-#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_MASK 0x07F80000L
-#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L
-#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE_MASK 0x10000000L
-#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS_MASK 0x20000000L
-#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST_MASK 0x40000000L
-#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA_MASK 0x80000000L
-//RMI_SCOREBOARD_CNTL
-#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH__SHIFT 0x0
-#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0__SHIFT 0x1
-#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH__SHIFT 0x2
-#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1__SHIFT 0x3
-#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1__SHIFT 0x4
-#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN__SHIFT 0x5
-#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE__SHIFT 0x6
-#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0__SHIFT 0x7
-#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN__SHIFT 0x8
-#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE__SHIFT 0x9
-#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH_MASK 0x00000001L
-#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0_MASK 0x00000002L
-#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH_MASK 0x00000004L
-#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1_MASK 0x00000008L
-#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1_MASK 0x00000010L
-#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN_MASK 0x00000020L
-#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE_MASK 0x00000040L
-#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0_MASK 0x00000080L
-#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN_MASK 0x00000100L
-#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE_MASK 0x001FFE00L
-//RMI_SCOREBOARD_STATUS0
-#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID__SHIFT 0x0
-#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG__SHIFT 0x1
-#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID__SHIFT 0x2
-#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE__SHIFT 0x12
-#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE__SHIFT 0x13
-#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE__SHIFT 0x14
-#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE__SHIFT 0x15
-#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID_MASK 0x00000001L
-#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG_MASK 0x00000002L
-#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID_MASK 0x0003FFFCL
-#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE_MASK 0x00040000L
-#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE_MASK 0x00080000L
-#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE_MASK 0x00100000L
-#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE_MASK 0x00200000L
-//RMI_SCOREBOARD_STATUS1
-#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0__SHIFT 0x0
-#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0__SHIFT 0xc
-#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0__SHIFT 0xd
-#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED__SHIFT 0xe
-#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1__SHIFT 0xf
-#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1__SHIFT 0x1b
-#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1__SHIFT 0x1c
-#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1__SHIFT 0x1d
-#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0__SHIFT 0x1e
-#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0_MASK 0x00000FFFL
-#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0_MASK 0x00001000L
-#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0_MASK 0x00002000L
-#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED_MASK 0x00004000L
-#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1_MASK 0x07FF8000L
-#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1_MASK 0x08000000L
-#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1_MASK 0x10000000L
-#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1_MASK 0x20000000L
-#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0_MASK 0x40000000L
-//RMI_SCOREBOARD_STATUS2
-#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0__SHIFT 0x0
-#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0__SHIFT 0xc
-#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1__SHIFT 0xd
-#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1__SHIFT 0x19
-#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1__SHIFT 0x1a
-#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0__SHIFT 0x1b
-#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0__SHIFT 0x1c
-#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1__SHIFT 0x1d
-#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0__SHIFT 0x1e
-#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1__SHIFT 0x1f
-#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0_MASK 0x00000FFFL
-#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0_MASK 0x00001000L
-#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1_MASK 0x01FFE000L
-#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1_MASK 0x02000000L
-#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1_MASK 0x04000000L
-#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0_MASK 0x08000000L
-#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0_MASK 0x10000000L
-#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1_MASK 0x20000000L
-#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0_MASK 0x40000000L
-#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1_MASK 0x80000000L
-//RMI_XBAR_ARBITER_CONFIG
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE__SHIFT 0x0
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x2
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL__SHIFT 0x3
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x4
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x6
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x8
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE__SHIFT 0x10
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x12
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL__SHIFT 0x13
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x14
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x16
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x18
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_MASK 0x00000003L
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00000004L
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_MASK 0x00000008L
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000010L
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE_MASK 0x000000C0L
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE_MASK 0x0000FF00L
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_MASK 0x00030000L
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00040000L
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_MASK 0x00080000L
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00100000L
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00C00000L
-#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE_MASK 0xFF000000L
-//RMI_XBAR_ARBITER_CONFIG_1
-#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD__SHIFT 0x0
-#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR__SHIFT 0x8
-#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD__SHIFT 0x10
-#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR__SHIFT 0x18
-#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD_MASK 0x000000FFL
-#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR_MASK 0x0000FF00L
-#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD_MASK 0x00FF0000L
-#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR_MASK 0xFF000000L
-//RMI_CLOCK_CNTRL
-#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK__SHIFT 0x0
-#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK__SHIFT 0x5
-#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT 0xa
-#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK__SHIFT 0xf
-#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK__SHIFT 0x14
-#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK__SHIFT 0x19
-#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK_MASK 0x0000001FL
-#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK_MASK 0x000003E0L
-#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK_MASK 0x00007C00L
-#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK_MASK 0x000F8000L
-#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK_MASK 0x01F00000L
-#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK_MASK 0x3E000000L
-//RMI_UTCL1_STATUS
-#define RMI_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
-#define RMI_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
-#define RMI_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
-#define RMI_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
-#define RMI_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
-#define RMI_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
-//RMI_SPARE
-#define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING__SHIFT 0x0
-#define RMI_SPARE__SPARE_BIT_1__SHIFT 0x1
-#define RMI_SPARE__SPARE_BIT_2__SHIFT 0x2
-#define RMI_SPARE__SPARE_BIT_3__SHIFT 0x3
-#define RMI_SPARE__SPARE_BIT_4__SHIFT 0x4
-#define RMI_SPARE__SPARE_BIT_5__SHIFT 0x5
-#define RMI_SPARE__SPARE_BIT_6__SHIFT 0x6
-#define RMI_SPARE__SPARE_BIT_7__SHIFT 0x7
-#define RMI_SPARE__SPARE_BIT_8_0__SHIFT 0x8
-#define RMI_SPARE__SPARE_BIT_16_0__SHIFT 0x10
-#define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING_MASK 0x00000001L
-#define RMI_SPARE__SPARE_BIT_1_MASK 0x00000002L
-#define RMI_SPARE__SPARE_BIT_2_MASK 0x00000004L
-#define RMI_SPARE__SPARE_BIT_3_MASK 0x00000008L
-#define RMI_SPARE__SPARE_BIT_4_MASK 0x00000010L
-#define RMI_SPARE__SPARE_BIT_5_MASK 0x00000020L
-#define RMI_SPARE__SPARE_BIT_6_MASK 0x00000040L
-#define RMI_SPARE__SPARE_BIT_7_MASK 0x00000080L
-#define RMI_SPARE__SPARE_BIT_8_0_MASK 0x0000FF00L
-#define RMI_SPARE__SPARE_BIT_16_0_MASK 0xFFFF0000L
-//RMI_SPARE_1
-#define RMI_SPARE_1__SPARE_BIT_8__SHIFT 0x0
-#define RMI_SPARE_1__SPARE_BIT_9__SHIFT 0x1
-#define RMI_SPARE_1__SPARE_BIT_10__SHIFT 0x2
-#define RMI_SPARE_1__SPARE_BIT_11__SHIFT 0x3
-#define RMI_SPARE_1__SPARE_BIT_12__SHIFT 0x4
-#define RMI_SPARE_1__SPARE_BIT_13__SHIFT 0x5
-#define RMI_SPARE_1__SPARE_BIT_14__SHIFT 0x6
-#define RMI_SPARE_1__SPARE_BIT_15__SHIFT 0x7
-#define RMI_SPARE_1__SPARE_BIT_8_1__SHIFT 0x8
-#define RMI_SPARE_1__SPARE_BIT_16_1__SHIFT 0x10
-#define RMI_SPARE_1__SPARE_BIT_8_MASK 0x00000001L
-#define RMI_SPARE_1__SPARE_BIT_9_MASK 0x00000002L
-#define RMI_SPARE_1__SPARE_BIT_10_MASK 0x00000004L
-#define RMI_SPARE_1__SPARE_BIT_11_MASK 0x00000008L
-#define RMI_SPARE_1__SPARE_BIT_12_MASK 0x00000010L
-#define RMI_SPARE_1__SPARE_BIT_13_MASK 0x00000020L
-#define RMI_SPARE_1__SPARE_BIT_14_MASK 0x00000040L
-#define RMI_SPARE_1__SPARE_BIT_15_MASK 0x00000080L
-#define RMI_SPARE_1__SPARE_BIT_8_1_MASK 0x0000FF00L
-#define RMI_SPARE_1__SPARE_BIT_16_1_MASK 0xFFFF0000L
-//RMI_SPARE_2
-#define RMI_SPARE_2__SPARE_BIT_16__SHIFT 0x0
-#define RMI_SPARE_2__SPARE_BIT_17__SHIFT 0x1
-#define RMI_SPARE_2__SPARE_BIT_18__SHIFT 0x2
-#define RMI_SPARE_2__SPARE_BIT_19__SHIFT 0x3
-#define RMI_SPARE_2__SPARE_BIT_20__SHIFT 0x4
-#define RMI_SPARE_2__SPARE_BIT_21__SHIFT 0x5
-#define RMI_SPARE_2__SPARE_BIT_22__SHIFT 0x6
-#define RMI_SPARE_2__SPARE_BIT_23__SHIFT 0x7
-#define RMI_SPARE_2__SPARE_BIT_4_0__SHIFT 0x8
-#define RMI_SPARE_2__SPARE_BIT_4_1__SHIFT 0xc
-#define RMI_SPARE_2__SPARE_BIT_8_2__SHIFT 0x10
-#define RMI_SPARE_2__SPARE_BIT_8_3__SHIFT 0x18
-#define RMI_SPARE_2__SPARE_BIT_16_MASK 0x00000001L
-#define RMI_SPARE_2__SPARE_BIT_17_MASK 0x00000002L
-#define RMI_SPARE_2__SPARE_BIT_18_MASK 0x00000004L
-#define RMI_SPARE_2__SPARE_BIT_19_MASK 0x00000008L
-#define RMI_SPARE_2__SPARE_BIT_20_MASK 0x00000010L
-#define RMI_SPARE_2__SPARE_BIT_21_MASK 0x00000020L
-#define RMI_SPARE_2__SPARE_BIT_22_MASK 0x00000040L
-#define RMI_SPARE_2__SPARE_BIT_23_MASK 0x00000080L
-#define RMI_SPARE_2__SPARE_BIT_4_0_MASK 0x00000F00L
-#define RMI_SPARE_2__SPARE_BIT_4_1_MASK 0x0000F000L
-#define RMI_SPARE_2__SPARE_BIT_8_2_MASK 0x00FF0000L
-#define RMI_SPARE_2__SPARE_BIT_8_3_MASK 0xFF000000L
-
-
-// addressBlock: gc_dbgu_gfx_dbgudec
-//port_a_addr
-#define port_a_addr__Index__SHIFT 0x0
-#define port_a_addr__Reserved__SHIFT 0x8
-#define port_a_addr__ReadEnable__SHIFT 0x1f
-#define port_a_addr__Index_MASK 0x000000FFL
-#define port_a_addr__Reserved_MASK 0x7FFFFF00L
-#define port_a_addr__ReadEnable_MASK 0x80000000L
-//port_a_data_lo
-#define port_a_data_lo__Data__SHIFT 0x0
-#define port_a_data_lo__Data_MASK 0xFFFFFFFFL
-//port_a_data_hi
-#define port_a_data_hi__Data__SHIFT 0x0
-#define port_a_data_hi__Data_MASK 0xFFFFFFFFL
-//port_b_addr
-#define port_b_addr__Index__SHIFT 0x0
-#define port_b_addr__Reserved__SHIFT 0x8
-#define port_b_addr__ReadEnable__SHIFT 0x1f
-#define port_b_addr__Index_MASK 0x000000FFL
-#define port_b_addr__Reserved_MASK 0x7FFFFF00L
-#define port_b_addr__ReadEnable_MASK 0x80000000L
-//port_b_data_lo
-#define port_b_data_lo__Data__SHIFT 0x0
-#define port_b_data_lo__Data_MASK 0xFFFFFFFFL
-//port_b_data_hi
-#define port_b_data_hi__Data__SHIFT 0x0
-#define port_b_data_hi__Data_MASK 0xFFFFFFFFL
-//port_c_addr
-#define port_c_addr__Index__SHIFT 0x0
-#define port_c_addr__Reserved__SHIFT 0x8
-#define port_c_addr__ReadEnable__SHIFT 0x1f
-#define port_c_addr__Index_MASK 0x000000FFL
-#define port_c_addr__Reserved_MASK 0x7FFFFF00L
-#define port_c_addr__ReadEnable_MASK 0x80000000L
-//port_c_data_lo
-#define port_c_data_lo__Data__SHIFT 0x0
-#define port_c_data_lo__Data_MASK 0xFFFFFFFFL
-//port_c_data_hi
-#define port_c_data_hi__Data__SHIFT 0x0
-#define port_c_data_hi__Data_MASK 0xFFFFFFFFL
-//port_d_addr
-#define port_d_addr__Index__SHIFT 0x0
-#define port_d_addr__Reserved__SHIFT 0x8
-#define port_d_addr__ReadEnable__SHIFT 0x1f
-#define port_d_addr__Index_MASK 0x000000FFL
-#define port_d_addr__Reserved_MASK 0x7FFFFF00L
-#define port_d_addr__ReadEnable_MASK 0x80000000L
-//port_d_data_lo
-#define port_d_data_lo__Data__SHIFT 0x0
-#define port_d_data_lo__Data_MASK 0xFFFFFFFFL
-//port_d_data_hi
-#define port_d_data_hi__Data__SHIFT 0x0
-#define port_d_data_hi__Data_MASK 0xFFFFFFFFL
-
-
-// addressBlock: gc_utcl2_atcl2dec
-//ATC_L2_CNTL
-#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0
-#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3
-#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6
-#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7
-#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x8
-#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
-#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L
-#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L
-#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L
-#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L
-#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00000700L
-#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L
-//ATC_L2_CNTL2
-#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0
-#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6
-#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8
-#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9
-#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc
-#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf
-#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL
-#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L
-#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000100L
-#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00000E00L
-#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00007000L
-#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x001F8000L
-//ATC_L2_CACHE_DATA0
-#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0
-#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1
-#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2
-#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x17
-#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L
-#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L
-#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x007FFFFCL
-#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x07800000L
-//ATC_L2_CACHE_DATA1
-#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0
-#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL
-//ATC_L2_CACHE_DATA2
-#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0
-#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL
-//ATC_L2_CNTL3
-#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x0
-#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x3
-#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x00000007L
-#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x000001F8L
-//ATC_L2_STATUS
-#define ATC_L2_STATUS__BUSY__SHIFT 0x0
-#define ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1
-#define ATC_L2_STATUS__BUSY_MASK 0x00000001L
-#define ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3FFFFFFEL
-//ATC_L2_STATUS2
-#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0
-#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8
-#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL
-#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L
-//ATC_L2_MISC_CG
-#define ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6
-#define ATC_L2_MISC_CG__ENABLE__SHIFT 0x12
-#define ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13
-#define ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L
-#define ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L
-#define ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L
-//ATC_L2_MEM_POWER_LS
-#define ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
-#define ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
-#define ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL
-#define ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L
-//ATC_L2_CGTT_CLK_CTRL
-#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
-#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10
-#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18
-#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
-#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
-#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
-
-
-// addressBlock: gc_utcl2_vml2pfdec
-//VM_L2_CNTL
-#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0
-#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1
-#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2
-#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4
-#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8
-#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9
-#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa
-#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
-#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc
-#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf
-#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12
-#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13
-#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15
-#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a
-#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L
-#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L
-#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL
-#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L
-#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L
-#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L
-#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L
-#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L
-#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L
-#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L
-#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L
-#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L
-#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L
-#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L
-//VM_L2_CNTL2
-#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0
-#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1
-#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15
-#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16
-#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17
-#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a
-#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c
-#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L
-#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L
-#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L
-#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L
-#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L
-#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L
-#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L
-//VM_L2_CNTL3
-#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0
-#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6
-#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8
-#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf
-#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14
-#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15
-#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18
-#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c
-#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d
-#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e
-#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f
-#define VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL
-#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L
-#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L
-#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L
-#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L
-#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L
-#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L
-#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L
-#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L
-#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L
-#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L
-//VM_L2_STATUS
-#define VM_L2_STATUS__L2_BUSY__SHIFT 0x0
-#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1
-#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11
-#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12
-#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13
-#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14
-#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15
-#define VM_L2_STATUS__L2_BUSY_MASK 0x00000001L
-#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL
-#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L
-#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L
-#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L
-#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L
-#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L
-//VM_DUMMY_PAGE_FAULT_CNTL
-#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0
-#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1
-#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2
-#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L
-#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L
-#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL
-//VM_DUMMY_PAGE_FAULT_ADDR_LO32
-#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0
-#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
-//VM_DUMMY_PAGE_FAULT_ADDR_HI32
-#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0
-#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL
-//VM_L2_PROTECTION_FAULT_CNTL
-#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
-#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1
-#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2
-#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3
-#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
-#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5
-#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6
-#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
-#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8
-#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9
-#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb
-#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd
-#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d
-#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e
-#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f
-#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L
-#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L
-#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L
-#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L
-#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L
-#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L
-#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L
-#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L
-#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L
-#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L
-#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L
-#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L
-#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L
-#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L
-#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L
-//VM_L2_PROTECTION_FAULT_CNTL2
-#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0
-#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10
-#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11
-#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12
-#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13
-#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL
-#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L
-#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L
-#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L
-#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L
-//VM_L2_PROTECTION_FAULT_MM_CNTL3
-#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0
-#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL
-//VM_L2_PROTECTION_FAULT_MM_CNTL4
-#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0
-#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL
-//VM_L2_PROTECTION_FAULT_STATUS
-#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0
-#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1
-#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4
-#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8
-#define VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9
-#define VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12
-#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13
-#define VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14
-#define VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18
-#define VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19
-#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L
-#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL
-#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L
-#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L
-#define VM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L
-#define VM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L
-#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L
-#define VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L
-#define VM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L
-#define VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L
-//VM_L2_PROTECTION_FAULT_ADDR_LO32
-#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0
-#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
-//VM_L2_PROTECTION_FAULT_ADDR_HI32
-#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0
-#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL
-//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32
-#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0
-#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
-//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32
-#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0
-#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL
-//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32
-#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32
-#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32
-#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32
-#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32
-#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0
-#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL
-//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32
-#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0
-#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL
-//VM_L2_CNTL4
-#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0
-#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6
-#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7
-#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8
-#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12
-#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c
-#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL
-#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L
-#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L
-#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L
-#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L
-#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L
-//VM_L2_MM_GROUP_RT_CLASSES
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L
-//VM_L2_BANK_SELECT_RESERVED_CID
-#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0
-#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
-#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14
-#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18
-#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19
-#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL
-#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L
-#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L
-#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L
-#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L
-//VM_L2_BANK_SELECT_RESERVED_CID2
-#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0
-#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
-#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14
-#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18
-#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19
-#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL
-#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L
-#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L
-#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L
-#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L
-//VM_L2_CACHE_PARITY_CNTL
-#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0
-#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1
-#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2
-#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3
-#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4
-#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5
-#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6
-#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9
-#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc
-#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L
-#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L
-#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L
-#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L
-#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L
-#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L
-#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L
-#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L
-#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L
-//VM_L2_CGTT_CLK_CTRL
-#define VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
-#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10
-#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18
-#define VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
-#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
-#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
-
-
-// addressBlock: gc_utcl2_vml2vcdec
-//VM_CONTEXT0_CNTL
-#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT1_CNTL
-#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT2_CNTL
-#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT3_CNTL
-#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT4_CNTL
-#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT5_CNTL
-#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT6_CNTL
-#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT7_CNTL
-#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT8_CNTL
-#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT9_CNTL
-#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT10_CNTL
-#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT11_CNTL
-#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT12_CNTL
-#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT13_CNTL
-#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT14_CNTL
-#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT15_CNTL
-#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXTS_DISABLE
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L
-//VM_INVALIDATE_ENG0_SEM
-#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG1_SEM
-#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG2_SEM
-#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG3_SEM
-#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG4_SEM
-#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG5_SEM
-#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG6_SEM
-#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG7_SEM
-#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG8_SEM
-#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG9_SEM
-#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG10_SEM
-#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG11_SEM
-#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG12_SEM
-#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG13_SEM
-#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG14_SEM
-#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG15_SEM
-#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG16_SEM
-#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG17_SEM
-#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG0_REQ
-#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG1_REQ
-#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG2_REQ
-#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG3_REQ
-#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG4_REQ
-#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG5_REQ
-#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG6_REQ
-#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG7_REQ
-#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG8_REQ
-#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG9_REQ
-#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG10_REQ
-#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG11_REQ
-#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG12_REQ
-#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG13_REQ
-#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG14_REQ
-#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG15_REQ
-#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG16_REQ
-#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG17_REQ
-#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG0_ACK
-#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG1_ACK
-#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG2_ACK
-#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG3_ACK
-#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG4_ACK
-#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG5_ACK
-#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG6_ACK
-#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG7_ACK
-#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG8_ACK
-#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG9_ACK
-#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG10_ACK
-#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG11_ACK
-#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG12_ACK
-#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG13_ACK
-#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG14_ACK
-#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG15_ACK
-#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG16_ACK
-#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG17_ACK
-#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG0_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG0_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG1_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG1_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG2_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG2_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG3_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG3_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG4_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG4_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG5_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG5_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG6_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG6_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG7_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG7_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG8_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG8_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG9_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG9_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG10_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG10_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG11_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG11_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG12_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG12_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG13_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG13_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG14_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG14_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG15_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG15_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG16_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG16_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG17_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG17_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-
-
-// addressBlock: gc_utcl2_vmsharedpfdec
-//MC_VM_NB_MMIOBASE
-#define MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0
-#define MC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL
-//MC_VM_NB_MMIOLIMIT
-#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0
-#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL
-//MC_VM_NB_PCI_CTRL
-#define MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17
-#define MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L
-//MC_VM_NB_PCI_ARB
-#define MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3
-#define MC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L
-//MC_VM_NB_TOP_OF_DRAM_SLOT1
-#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17
-#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L
-//MC_VM_NB_LOWER_TOP_OF_DRAM2
-#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0
-#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17
-#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L
-#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L
-//MC_VM_NB_UPPER_TOP_OF_DRAM2
-#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0
-#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL
-//MC_VM_FB_OFFSET
-#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0
-#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL
-//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
-#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0
-#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL
-//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
-#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0
-#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL
-//MC_VM_STEERING
-#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0
-#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L
-//MC_SHARED_VIRT_RESET_REQ
-#define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0
-#define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f
-#define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL
-#define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L
-//MC_MEM_POWER_LS
-#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
-#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
-#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL
-#define MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L
-//MC_VM_CACHEABLE_DRAM_ADDRESS_START
-#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0
-#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL
-//MC_VM_CACHEABLE_DRAM_ADDRESS_END
-#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0
-#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL
-//MC_VM_APT_CNTL
-#define MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0
-#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1
-#define MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L
-#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L
-//MC_VM_LOCAL_HBM_ADDRESS_START
-#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0
-#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL
-//MC_VM_LOCAL_HBM_ADDRESS_END
-#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0
-#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL
-//MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL
-#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0
-#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L
-
-
-// addressBlock: gc_utcl2_vmsharedvcdec
-//MC_VM_FB_LOCATION_BASE
-#define MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0
-#define MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL
-//MC_VM_FB_LOCATION_TOP
-#define MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0
-#define MC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL
-//MC_VM_AGP_TOP
-#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0
-#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL
-//MC_VM_AGP_BOT
-#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0
-#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL
-//MC_VM_AGP_BASE
-#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0
-#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL
-//MC_VM_SYSTEM_APERTURE_LOW_ADDR
-#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0
-#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL
-//MC_VM_SYSTEM_APERTURE_HIGH_ADDR
-#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0
-#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL
-//MC_VM_MX_L1_TLB_CNTL
-#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0
-#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3
-#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5
-#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6
-#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7
-#define MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb
-#define MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT 0xd
-#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L
-#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L
-#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L
-#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L
-#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L
-#define MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L
-#define MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK 0x00002000L
-
-
-// addressBlock: gc_ea_gceadec
-//GCEA_DRAM_RD_CLI2GRP_MAP0
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
-#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
-//GCEA_DRAM_RD_CLI2GRP_MAP1
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
-#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
-//GCEA_DRAM_WR_CLI2GRP_MAP0
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
-#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
-//GCEA_DRAM_WR_CLI2GRP_MAP1
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
-#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
-//GCEA_DRAM_RD_GRP2VC_MAP
-#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
-#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
-#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
-#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
-#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
-#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
-#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
-#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
-//GCEA_DRAM_WR_GRP2VC_MAP
-#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
-#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
-#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
-#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
-#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
-#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
-#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
-#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
-//GCEA_DRAM_RD_LAZY
-#define GCEA_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0
-#define GCEA_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3
-#define GCEA_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6
-#define GCEA_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9
-#define GCEA_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L
-#define GCEA_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L
-#define GCEA_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L
-#define GCEA_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L
-//GCEA_DRAM_WR_LAZY
-#define GCEA_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0
-#define GCEA_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3
-#define GCEA_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6
-#define GCEA_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9
-#define GCEA_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L
-#define GCEA_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L
-#define GCEA_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L
-#define GCEA_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L
-//GCEA_DRAM_RD_CAM_CNTL
-#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
-#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
-#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
-#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
-#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
-#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
-#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
-#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
-#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
-#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
-#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
-#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
-#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
-#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
-#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
-#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
-//GCEA_DRAM_WR_CAM_CNTL
-#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
-#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
-#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
-#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
-#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
-#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
-#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
-#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
-#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
-#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
-#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
-#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
-#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
-#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
-#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
-#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
-//GCEA_DRAM_PAGE_BURST
-#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0
-#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8
-#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10
-#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18
-#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL
-#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
-#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
-#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L
-//GCEA_DRAM_RD_PRI_AGE
-#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
-#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
-#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
-#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
-#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
-#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
-#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
-#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
-#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
-#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
-#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
-#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
-#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
-#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
-#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
-#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
-//GCEA_DRAM_WR_PRI_AGE
-#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
-#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
-#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
-#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
-#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
-#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
-#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
-#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
-#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
-#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
-#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
-#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
-#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
-#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
-#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
-#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
-//GCEA_DRAM_RD_PRI_QUEUING
-#define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
-#define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
-#define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
-#define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
-#define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
-#define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
-#define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
-#define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
-//GCEA_DRAM_WR_PRI_QUEUING
-#define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
-#define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
-#define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
-#define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
-#define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
-#define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
-#define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
-#define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
-//GCEA_DRAM_RD_PRI_FIXED
-#define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
-#define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
-#define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
-#define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
-#define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
-#define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
-#define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
-#define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
-//GCEA_DRAM_WR_PRI_FIXED
-#define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
-#define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
-#define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
-#define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
-#define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
-#define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
-#define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
-#define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
-//GCEA_DRAM_RD_PRI_URGENCY
-#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
-#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
-#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
-#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
-#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
-#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
-#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
-#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
-#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
-#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
-#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
-#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
-#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
-#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
-#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
-#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
-//GCEA_DRAM_WR_PRI_URGENCY
-#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
-#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
-#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
-#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
-#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
-#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
-#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
-#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
-#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
-#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
-#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
-#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
-#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
-#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
-#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
-#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
-//GCEA_DRAM_RD_PRI_QUANT_PRI1
-#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
-#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
-#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
-#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
-#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
-//GCEA_DRAM_RD_PRI_QUANT_PRI2
-#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
-#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
-#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
-#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
-#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
-//GCEA_DRAM_RD_PRI_QUANT_PRI3
-#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
-#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
-#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
-#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
-#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
-//GCEA_DRAM_WR_PRI_QUANT_PRI1
-#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
-#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
-#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
-#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
-#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
-//GCEA_DRAM_WR_PRI_QUANT_PRI2
-#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
-#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
-#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
-#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
-#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
-//GCEA_DRAM_WR_PRI_QUANT_PRI3
-#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
-#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
-#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
-#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
-#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
-//GCEA_ADDRNORM_BASE_ADDR0
-#define GCEA_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0
-#define GCEA_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1
-#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x4
-#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x8
-#define GCEA_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc
-#define GCEA_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L
-#define GCEA_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
-#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x000000F0L
-#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000700L
-#define GCEA_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L
-//GCEA_ADDRNORM_LIMIT_ADDR0
-#define GCEA_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0
-#define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8
-#define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES__SHIFT 0xa
-#define GCEA_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc
-#define GCEA_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000000FL
-#define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L
-#define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES_MASK 0x00000C00L
-#define GCEA_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L
-//GCEA_ADDRNORM_BASE_ADDR1
-#define GCEA_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0
-#define GCEA_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1
-#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x4
-#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x8
-#define GCEA_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc
-#define GCEA_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L
-#define GCEA_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
-#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x000000F0L
-#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000700L
-#define GCEA_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L
-//GCEA_ADDRNORM_LIMIT_ADDR1
-#define GCEA_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0
-#define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8
-#define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES__SHIFT 0xa
-#define GCEA_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc
-#define GCEA_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000000FL
-#define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L
-#define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES_MASK 0x00000C00L
-#define GCEA_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L
-//GCEA_ADDRNORM_OFFSET_ADDR1
-#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0
-#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14
-#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L
-#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L
-//GCEA_ADDRNORM_HOLE_CNTL
-#define GCEA_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0
-#define GCEA_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7
-#define GCEA_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L
-#define GCEA_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L
-//GCEA_ADDRDEC_BANK_CFG
-#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0
-#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x5
-#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa
-#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xd
-#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x10
-#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x11
-#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001FL
-#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003E0L
-#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001C00L
-#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000E000L
-#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L
-#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L
-//GCEA_ADDRDEC_MISC_CFG
-#define GCEA_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0
-#define GCEA_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1
-#define GCEA_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2
-#define GCEA_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x3
-#define GCEA_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x4
-#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8
-#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9
-#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc
-#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x10
-#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x14
-#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x16
-#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x18
-#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1b
-#define GCEA_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L
-#define GCEA_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L
-#define GCEA_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L
-#define GCEA_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L
-#define GCEA_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L
-#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L
-#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L
-#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0000F000L
-#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x000F0000L
-#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00300000L
-#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x00C00000L
-#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x07000000L
-#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0x38000000L
-//GCEA_ADDRDECDRAM_ADDR_HASH_BANK0
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L
-//GCEA_ADDRDECDRAM_ADDR_HASH_BANK1
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L
-//GCEA_ADDRDECDRAM_ADDR_HASH_BANK2
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L
-//GCEA_ADDRDECDRAM_ADDR_HASH_BANK3
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L
-//GCEA_ADDRDECDRAM_ADDR_HASH_BANK4
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL
-#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L
-//GCEA_ADDRDECDRAM_ADDR_HASH_PC
-#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1
-#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe
-#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL
-#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L
-//GCEA_ADDRDECDRAM_ADDR_HASH_PC2
-#define GCEA_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0
-#define GCEA_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000001FL
-//GCEA_ADDRDECDRAM_ADDR_HASH_CS0
-#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1
-#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL
-//GCEA_ADDRDECDRAM_ADDR_HASH_CS1
-#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1
-#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL
-//GCEA_ADDRDECDRAM_HARVEST_ENABLE
-#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0
-#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1
-#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2
-#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3
-#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L
-#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L
-#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L
-#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L
-//GCEA_ADDRDEC0_BASE_ADDR_CS0
-#define GCEA_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
-#define GCEA_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC0_BASE_ADDR_CS1
-#define GCEA_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
-#define GCEA_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC0_BASE_ADDR_CS2
-#define GCEA_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
-#define GCEA_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC0_BASE_ADDR_CS3
-#define GCEA_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
-#define GCEA_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC0_BASE_ADDR_SECCS0
-#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
-#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC0_BASE_ADDR_SECCS1
-#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
-#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC0_BASE_ADDR_SECCS2
-#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
-#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC0_BASE_ADDR_SECCS3
-#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
-#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC0_ADDR_MASK_CS01
-#define GCEA_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
-#define GCEA_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC0_ADDR_MASK_CS23
-#define GCEA_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
-#define GCEA_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC0_ADDR_MASK_SECCS01
-#define GCEA_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
-#define GCEA_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC0_ADDR_MASK_SECCS23
-#define GCEA_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
-#define GCEA_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC0_ADDR_CFG_CS01
-#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2
-#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
-#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
-#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
-#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
-#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
-#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL
-#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
-#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
-#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
-#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
-#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
-//GCEA_ADDRDEC0_ADDR_CFG_CS23
-#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2
-#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
-#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
-#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
-#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
-#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
-#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL
-#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
-#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
-#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
-#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
-#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
-//GCEA_ADDRDEC0_ADDR_SEL_CS01
-#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0
-#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4
-#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8
-#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc
-#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10
-#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
-#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
-#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
-#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
-#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
-#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
-#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L
-#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
-#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
-//GCEA_ADDRDEC0_ADDR_SEL_CS23
-#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0
-#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4
-#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8
-#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc
-#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10
-#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
-#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
-#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
-#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
-#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
-#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
-#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L
-#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
-#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
-//GCEA_ADDRDEC0_COL_SEL_LO_CS01
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
-//GCEA_ADDRDEC0_COL_SEL_LO_CS23
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
-#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
-//GCEA_ADDRDEC0_COL_SEL_HI_CS01
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
-//GCEA_ADDRDEC0_COL_SEL_HI_CS23
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
-#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
-//GCEA_ADDRDEC0_RM_SEL_CS01
-#define GCEA_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0
-#define GCEA_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4
-#define GCEA_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8
-#define GCEA_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
-#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
-#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
-#define GCEA_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL
-#define GCEA_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L
-#define GCEA_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L
-#define GCEA_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
-#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
-#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
-//GCEA_ADDRDEC0_RM_SEL_CS23
-#define GCEA_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0
-#define GCEA_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4
-#define GCEA_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8
-#define GCEA_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
-#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
-#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
-#define GCEA_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL
-#define GCEA_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L
-#define GCEA_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L
-#define GCEA_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
-#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
-#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
-//GCEA_ADDRDEC0_RM_SEL_SECCS01
-#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0
-#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4
-#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8
-#define GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
-#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
-#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
-#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
-#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
-#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
-#define GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
-#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
-#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
-//GCEA_ADDRDEC0_RM_SEL_SECCS23
-#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0
-#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4
-#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8
-#define GCEA_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
-#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
-#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
-#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
-#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
-#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
-#define GCEA_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
-#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
-#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
-//GCEA_ADDRDEC1_BASE_ADDR_CS0
-#define GCEA_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
-#define GCEA_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC1_BASE_ADDR_CS1
-#define GCEA_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
-#define GCEA_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC1_BASE_ADDR_CS2
-#define GCEA_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
-#define GCEA_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC1_BASE_ADDR_CS3
-#define GCEA_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
-#define GCEA_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC1_BASE_ADDR_SECCS0
-#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
-#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC1_BASE_ADDR_SECCS1
-#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
-#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC1_BASE_ADDR_SECCS2
-#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
-#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC1_BASE_ADDR_SECCS3
-#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0
-#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
-#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L
-#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC1_ADDR_MASK_CS01
-#define GCEA_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
-#define GCEA_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC1_ADDR_MASK_CS23
-#define GCEA_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
-#define GCEA_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC1_ADDR_MASK_SECCS01
-#define GCEA_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
-#define GCEA_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC1_ADDR_MASK_SECCS23
-#define GCEA_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
-#define GCEA_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
-//GCEA_ADDRDEC1_ADDR_CFG_CS01
-#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2
-#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
-#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
-#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
-#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
-#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
-#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL
-#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
-#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
-#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
-#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
-#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
-//GCEA_ADDRDEC1_ADDR_CFG_CS23
-#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2
-#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
-#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
-#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
-#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
-#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
-#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL
-#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
-#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
-#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
-#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
-#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
-//GCEA_ADDRDEC1_ADDR_SEL_CS01
-#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0
-#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4
-#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8
-#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc
-#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10
-#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
-#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
-#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
-#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
-#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
-#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
-#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L
-#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
-#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
-//GCEA_ADDRDEC1_ADDR_SEL_CS23
-#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0
-#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4
-#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8
-#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc
-#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10
-#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
-#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
-#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
-#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
-#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
-#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
-#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L
-#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
-#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
-//GCEA_ADDRDEC1_COL_SEL_LO_CS01
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
-//GCEA_ADDRDEC1_COL_SEL_LO_CS23
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
-#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
-//GCEA_ADDRDEC1_COL_SEL_HI_CS01
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
-//GCEA_ADDRDEC1_COL_SEL_HI_CS23
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
-#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
-//GCEA_ADDRDEC1_RM_SEL_CS01
-#define GCEA_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0
-#define GCEA_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4
-#define GCEA_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8
-#define GCEA_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
-#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
-#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
-#define GCEA_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL
-#define GCEA_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L
-#define GCEA_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L
-#define GCEA_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
-#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
-#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
-//GCEA_ADDRDEC1_RM_SEL_CS23
-#define GCEA_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0
-#define GCEA_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4
-#define GCEA_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8
-#define GCEA_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
-#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
-#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
-#define GCEA_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL
-#define GCEA_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L
-#define GCEA_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L
-#define GCEA_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
-#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
-#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
-//GCEA_ADDRDEC1_RM_SEL_SECCS01
-#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0
-#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4
-#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8
-#define GCEA_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
-#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
-#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
-#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
-#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
-#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
-#define GCEA_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
-#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
-#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
-//GCEA_ADDRDEC1_RM_SEL_SECCS23
-#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0
-#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4
-#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8
-#define GCEA_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
-#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
-#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
-#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
-#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
-#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
-#define GCEA_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
-#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
-#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
-//GCEA_IO_RD_CLI2GRP_MAP0
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
-#define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
-//GCEA_IO_RD_CLI2GRP_MAP1
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
-#define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
-//GCEA_IO_WR_CLI2GRP_MAP0
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
-#define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
-//GCEA_IO_WR_CLI2GRP_MAP1
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
-#define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
-//GCEA_IO_RD_COMBINE_FLUSH
-#define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0
-#define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4
-#define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8
-#define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc
-#define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL
-#define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L
-#define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L
-#define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L
-//GCEA_IO_WR_COMBINE_FLUSH
-#define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0
-#define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4
-#define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8
-#define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc
-#define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL
-#define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L
-#define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L
-#define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L
-//GCEA_IO_GROUP_BURST
-#define GCEA_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0
-#define GCEA_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8
-#define GCEA_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10
-#define GCEA_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18
-#define GCEA_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL
-#define GCEA_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
-#define GCEA_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
-#define GCEA_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L
-//GCEA_IO_RD_PRI_AGE
-#define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
-#define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
-#define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
-#define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
-#define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
-#define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
-#define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
-#define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
-#define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
-#define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
-#define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
-#define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
-#define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
-#define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
-#define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
-#define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
-//GCEA_IO_WR_PRI_AGE
-#define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
-#define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
-#define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
-#define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
-#define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
-#define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
-#define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
-#define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
-#define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
-#define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
-#define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
-#define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
-#define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
-#define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
-#define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
-#define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
-//GCEA_IO_RD_PRI_QUEUING
-#define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
-#define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
-#define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
-#define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
-#define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
-#define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
-#define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
-#define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
-//GCEA_IO_WR_PRI_QUEUING
-#define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
-#define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
-#define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
-#define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
-#define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
-#define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
-#define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
-#define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
-//GCEA_IO_RD_PRI_FIXED
-#define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
-#define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
-#define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
-#define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
-#define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
-#define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
-#define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
-#define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
-//GCEA_IO_WR_PRI_FIXED
-#define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
-#define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
-#define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
-#define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
-#define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
-#define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
-#define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
-#define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
-//GCEA_IO_RD_PRI_URGENCY
-#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
-#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
-#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
-#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
-#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
-#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
-#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
-#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
-#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
-#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
-#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
-#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
-#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
-#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
-#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
-#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
-//GCEA_IO_WR_PRI_URGENCY
-#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
-#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
-#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
-#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
-#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
-#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
-#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
-#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
-#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
-#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
-#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
-#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
-#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
-#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
-#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
-#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
-//GCEA_IO_RD_PRI_URGENCY_MASK
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L
-#define GCEA_IO_RD_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L
-//GCEA_IO_WR_PRI_URGENCY_MASK
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L
-#define GCEA_IO_WR_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L
-//GCEA_IO_RD_PRI_QUANT_PRI1
-#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
-#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
-#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
-#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
-#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
-//GCEA_IO_RD_PRI_QUANT_PRI2
-#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
-#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
-#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
-#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
-#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
-//GCEA_IO_RD_PRI_QUANT_PRI3
-#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
-#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
-#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
-#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
-#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
-//GCEA_IO_WR_PRI_QUANT_PRI1
-#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
-#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
-#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
-#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
-#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
-//GCEA_IO_WR_PRI_QUANT_PRI2
-#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
-#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
-#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
-#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
-#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
-//GCEA_IO_WR_PRI_QUANT_PRI3
-#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
-#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
-#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
-#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
-#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
-//GCEA_SDP_ARB_DRAM
-#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0
-#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8
-#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10
-#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11
-#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12
-#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13
-#define GCEA_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14
-#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL
-#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L
-#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L
-#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L
-#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L
-#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L
-#define GCEA_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L
-//GCEA_SDP_ARB_FINAL
-#define GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0
-#define GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5
-#define GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa
-#define GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf
-#define GCEA_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11
-#define GCEA_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12
-#define GCEA_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13
-#define GCEA_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14
-#define GCEA_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15
-#define GCEA_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16
-#define GCEA_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17
-#define GCEA_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18
-#define GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19
-#define GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a
-#define GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL
-#define GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L
-#define GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L
-#define GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L
-#define GCEA_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L
-#define GCEA_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L
-#define GCEA_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L
-#define GCEA_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L
-#define GCEA_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L
-#define GCEA_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L
-#define GCEA_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L
-#define GCEA_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L
-#define GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L
-#define GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L
-//GCEA_SDP_DRAM_PRIORITY
-#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0
-#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4
-#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8
-#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc
-#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10
-#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14
-#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18
-#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c
-#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL
-#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L
-#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L
-#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L
-#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L
-#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L
-#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L
-#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L
-//GCEA_SDP_IO_PRIORITY
-#define GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0
-#define GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4
-#define GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8
-#define GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc
-#define GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10
-#define GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14
-#define GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18
-#define GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c
-#define GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL
-#define GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L
-#define GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L
-#define GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L
-#define GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L
-#define GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L
-#define GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L
-#define GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L
-//GCEA_SDP_CREDITS
-#define GCEA_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0
-#define GCEA_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8
-#define GCEA_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10
-#define GCEA_SDP_CREDITS__PRB_REQ_CREDITS__SHIFT 0x18
-#define GCEA_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL
-#define GCEA_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L
-#define GCEA_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L
-#define GCEA_SDP_CREDITS__PRB_REQ_CREDITS_MASK 0x3F000000L
-//GCEA_SDP_TAG_RESERVE0
-#define GCEA_SDP_TAG_RESERVE0__VC0__SHIFT 0x0
-#define GCEA_SDP_TAG_RESERVE0__VC1__SHIFT 0x8
-#define GCEA_SDP_TAG_RESERVE0__VC2__SHIFT 0x10
-#define GCEA_SDP_TAG_RESERVE0__VC3__SHIFT 0x18
-#define GCEA_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL
-#define GCEA_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L
-#define GCEA_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L
-#define GCEA_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L
-//GCEA_SDP_TAG_RESERVE1
-#define GCEA_SDP_TAG_RESERVE1__VC4__SHIFT 0x0
-#define GCEA_SDP_TAG_RESERVE1__VC5__SHIFT 0x8
-#define GCEA_SDP_TAG_RESERVE1__VC6__SHIFT 0x10
-#define GCEA_SDP_TAG_RESERVE1__VC7__SHIFT 0x18
-#define GCEA_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL
-#define GCEA_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L
-#define GCEA_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L
-#define GCEA_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L
-//GCEA_SDP_VCC_RESERVE0
-#define GCEA_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0
-#define GCEA_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6
-#define GCEA_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc
-#define GCEA_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12
-#define GCEA_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18
-#define GCEA_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL
-#define GCEA_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L
-#define GCEA_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L
-#define GCEA_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L
-#define GCEA_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L
-//GCEA_SDP_VCC_RESERVE1
-#define GCEA_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0
-#define GCEA_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6
-#define GCEA_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc
-#define GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f
-#define GCEA_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL
-#define GCEA_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L
-#define GCEA_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L
-#define GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L
-//GCEA_SDP_VCD_RESERVE0
-#define GCEA_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0
-#define GCEA_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6
-#define GCEA_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc
-#define GCEA_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12
-#define GCEA_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18
-#define GCEA_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL
-#define GCEA_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L
-#define GCEA_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L
-#define GCEA_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L
-#define GCEA_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L
-//GCEA_SDP_VCD_RESERVE1
-#define GCEA_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0
-#define GCEA_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6
-#define GCEA_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc
-#define GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f
-#define GCEA_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL
-#define GCEA_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L
-#define GCEA_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L
-#define GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L
-//GCEA_SDP_REQ_CNTL
-#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0
-#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1
-#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2
-#define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3
-#define GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4
-#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L
-#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L
-#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L
-#define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L
-#define GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L
-//GCEA_MISC
-#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0
-#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1
-#define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2
-#define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3
-#define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4
-#define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5
-#define GCEA_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6
-#define GCEA_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7
-#define GCEA_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8
-#define GCEA_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9
-#define GCEA_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa
-#define GCEA_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb
-#define GCEA_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc
-#define GCEA_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd
-#define GCEA_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe
-#define GCEA_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf
-#define GCEA_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11
-#define GCEA_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13
-#define GCEA_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15
-#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a
-#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b
-#define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c
-#define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d
-#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e
-#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f
-#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L
-#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L
-#define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L
-#define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L
-#define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L
-#define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L
-#define GCEA_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L
-#define GCEA_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L
-#define GCEA_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L
-#define GCEA_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L
-#define GCEA_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L
-#define GCEA_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L
-#define GCEA_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L
-#define GCEA_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L
-#define GCEA_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L
-#define GCEA_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L
-#define GCEA_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L
-#define GCEA_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L
-#define GCEA_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L
-#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L
-#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L
-#define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L
-#define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L
-#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L
-#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L
-//GCEA_LATENCY_SAMPLING
-#define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0
-#define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1
-#define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2
-#define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3
-#define GCEA_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4
-#define GCEA_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5
-#define GCEA_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6
-#define GCEA_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7
-#define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8
-#define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9
-#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa
-#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb
-#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc
-#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd
-#define GCEA_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe
-#define GCEA_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16
-#define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L
-#define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L
-#define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L
-#define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L
-#define GCEA_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L
-#define GCEA_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L
-#define GCEA_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L
-#define GCEA_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L
-#define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L
-#define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L
-#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L
-#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L
-#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L
-#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L
-#define GCEA_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L
-#define GCEA_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L
-//GCEA_PERFCOUNTER_LO
-#define GCEA_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
-#define GCEA_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
-//GCEA_PERFCOUNTER_HI
-#define GCEA_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
-#define GCEA_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
-#define GCEA_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
-#define GCEA_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
-//GCEA_PERFCOUNTER0_CFG
-#define GCEA_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
-#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
-#define GCEA_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
-#define GCEA_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
-#define GCEA_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
-#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
-#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define GCEA_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
-#define GCEA_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
-#define GCEA_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
-//GCEA_PERFCOUNTER1_CFG
-#define GCEA_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
-#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
-#define GCEA_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
-#define GCEA_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
-#define GCEA_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
-#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
-#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define GCEA_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
-#define GCEA_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
-#define GCEA_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
-//GCEA_PERFCOUNTER_RSLT_CNTL
-#define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
-#define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
-#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
-#define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
-#define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
-#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
-#define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
-#define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
-#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
-#define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
-#define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
-#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
-
-
-// addressBlock: gc_tcdec
-//TCP_INVALIDATE
-#define TCP_INVALIDATE__START__SHIFT 0x0
-#define TCP_INVALIDATE__START_MASK 0x00000001L
-//TCP_STATUS
-#define TCP_STATUS__TCP_BUSY__SHIFT 0x0
-#define TCP_STATUS__INPUT_BUSY__SHIFT 0x1
-#define TCP_STATUS__ADRS_BUSY__SHIFT 0x2
-#define TCP_STATUS__TAGRAMS_BUSY__SHIFT 0x3
-#define TCP_STATUS__CNTRL_BUSY__SHIFT 0x4
-#define TCP_STATUS__LFIFO_BUSY__SHIFT 0x5
-#define TCP_STATUS__READ_BUSY__SHIFT 0x6
-#define TCP_STATUS__FORMAT_BUSY__SHIFT 0x7
-#define TCP_STATUS__VM_BUSY__SHIFT 0x8
-#define TCP_STATUS__TCP_BUSY_MASK 0x00000001L
-#define TCP_STATUS__INPUT_BUSY_MASK 0x00000002L
-#define TCP_STATUS__ADRS_BUSY_MASK 0x00000004L
-#define TCP_STATUS__TAGRAMS_BUSY_MASK 0x00000008L
-#define TCP_STATUS__CNTRL_BUSY_MASK 0x00000010L
-#define TCP_STATUS__LFIFO_BUSY_MASK 0x00000020L
-#define TCP_STATUS__READ_BUSY_MASK 0x00000040L
-#define TCP_STATUS__FORMAT_BUSY_MASK 0x00000080L
-#define TCP_STATUS__VM_BUSY_MASK 0x00000100L
-//TCP_CNTL
-#define TCP_CNTL__FORCE_HIT__SHIFT 0x0
-#define TCP_CNTL__FORCE_MISS__SHIFT 0x1
-#define TCP_CNTL__L1_SIZE__SHIFT 0x2
-#define TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT 0x4
-#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT 0x5
-#define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0xf
-#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT 0x16
-#define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x1c
-#define TCP_CNTL__INV_ALL_VMIDS__SHIFT 0x1d
-#define TCP_CNTL__ASTC_VE_MSB_TOLERANT__SHIFT 0x1e
-#define TCP_CNTL__FORCE_HIT_MASK 0x00000001L
-#define TCP_CNTL__FORCE_MISS_MASK 0x00000002L
-#define TCP_CNTL__L1_SIZE_MASK 0x0000000CL
-#define TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK 0x00000010L
-#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK 0x00000020L
-#define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x001F8000L
-#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK 0x0FC00000L
-#define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000L
-#define TCP_CNTL__INV_ALL_VMIDS_MASK 0x20000000L
-#define TCP_CNTL__ASTC_VE_MSB_TOLERANT_MASK 0x40000000L
-//TCP_CHAN_STEER_LO
-#define TCP_CHAN_STEER_LO__CHAN0__SHIFT 0x0
-#define TCP_CHAN_STEER_LO__CHAN1__SHIFT 0x4
-#define TCP_CHAN_STEER_LO__CHAN2__SHIFT 0x8
-#define TCP_CHAN_STEER_LO__CHAN3__SHIFT 0xc
-#define TCP_CHAN_STEER_LO__CHAN4__SHIFT 0x10
-#define TCP_CHAN_STEER_LO__CHAN5__SHIFT 0x14
-#define TCP_CHAN_STEER_LO__CHAN6__SHIFT 0x18
-#define TCP_CHAN_STEER_LO__CHAN7__SHIFT 0x1c
-#define TCP_CHAN_STEER_LO__CHAN0_MASK 0x0000000FL
-#define TCP_CHAN_STEER_LO__CHAN1_MASK 0x000000F0L
-#define TCP_CHAN_STEER_LO__CHAN2_MASK 0x00000F00L
-#define TCP_CHAN_STEER_LO__CHAN3_MASK 0x0000F000L
-#define TCP_CHAN_STEER_LO__CHAN4_MASK 0x000F0000L
-#define TCP_CHAN_STEER_LO__CHAN5_MASK 0x00F00000L
-#define TCP_CHAN_STEER_LO__CHAN6_MASK 0x0F000000L
-#define TCP_CHAN_STEER_LO__CHAN7_MASK 0xF0000000L
-//TCP_CHAN_STEER_HI
-#define TCP_CHAN_STEER_HI__CHAN8__SHIFT 0x0
-#define TCP_CHAN_STEER_HI__CHAN9__SHIFT 0x4
-#define TCP_CHAN_STEER_HI__CHANA__SHIFT 0x8
-#define TCP_CHAN_STEER_HI__CHANB__SHIFT 0xc
-#define TCP_CHAN_STEER_HI__CHANC__SHIFT 0x10
-#define TCP_CHAN_STEER_HI__CHAND__SHIFT 0x14
-#define TCP_CHAN_STEER_HI__CHANE__SHIFT 0x18
-#define TCP_CHAN_STEER_HI__CHANF__SHIFT 0x1c
-#define TCP_CHAN_STEER_HI__CHAN8_MASK 0x0000000FL
-#define TCP_CHAN_STEER_HI__CHAN9_MASK 0x000000F0L
-#define TCP_CHAN_STEER_HI__CHANA_MASK 0x00000F00L
-#define TCP_CHAN_STEER_HI__CHANB_MASK 0x0000F000L
-#define TCP_CHAN_STEER_HI__CHANC_MASK 0x000F0000L
-#define TCP_CHAN_STEER_HI__CHAND_MASK 0x00F00000L
-#define TCP_CHAN_STEER_HI__CHANE_MASK 0x0F000000L
-#define TCP_CHAN_STEER_HI__CHANF_MASK 0xF0000000L
-//TCP_ADDR_CONFIG
-#define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT 0x0
-#define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT 0x4
-#define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT 0x6
-#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT 0x9
-#define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0x0000000FL
-#define TCP_ADDR_CONFIG__NUM_BANKS_MASK 0x00000030L
-#define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK 0x000001C0L
-#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK 0x00000200L
-//TCP_CREDIT
-#define TCP_CREDIT__LFIFO_CREDIT__SHIFT 0x0
-#define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x10
-#define TCP_CREDIT__TD_CREDIT__SHIFT 0x1d
-#define TCP_CREDIT__LFIFO_CREDIT_MASK 0x000003FFL
-#define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x007F0000L
-#define TCP_CREDIT__TD_CREDIT_MASK 0xE0000000L
-//TCP_BUFFER_ADDR_HASH_CNTL
-#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT 0x0
-#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT 0x8
-#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT 0x10
-#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT 0x18
-#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK 0x00000007L
-#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK 0x00000700L
-#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK 0x00070000L
-#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK 0x07000000L
-//TCP_EDC_CNT
-#define TCP_EDC_CNT__SEC_COUNT__SHIFT 0x0
-#define TCP_EDC_CNT__LFIFO_SED_COUNT__SHIFT 0x8
-#define TCP_EDC_CNT__DED_COUNT__SHIFT 0x10
-#define TCP_EDC_CNT__SEC_COUNT_MASK 0x000000FFL
-#define TCP_EDC_CNT__LFIFO_SED_COUNT_MASK 0x0000FF00L
-#define TCP_EDC_CNT__DED_COUNT_MASK 0x00FF0000L
-//TC_CFG_L1_LOAD_POLICY0
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT 0x0
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT 0x2
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT 0x4
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT 0x6
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT 0x8
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT 0xa
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT 0xc
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT 0xe
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT 0x10
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT 0x12
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT 0x14
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT 0x16
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT 0x18
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT 0x1a
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT 0x1c
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT 0x1e
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK 0x00000003L
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK 0x0000000CL
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK 0x00000030L
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK 0x000000C0L
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK 0x00000300L
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK 0x00000C00L
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK 0x00003000L
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK 0x0000C000L
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK 0x00030000L
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK 0x000C0000L
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK 0x00300000L
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK 0x00C00000L
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK 0x03000000L
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK 0x0C000000L
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK 0x30000000L
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK 0xC0000000L
-//TC_CFG_L1_LOAD_POLICY1
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT 0x0
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT 0x2
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT 0x4
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT 0x6
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT 0x8
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT 0xa
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT 0xc
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT 0xe
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT 0x10
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT 0x12
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT 0x14
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT 0x16
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT 0x18
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT 0x1a
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT 0x1c
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT 0x1e
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK 0x00000003L
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK 0x0000000CL
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK 0x00000030L
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK 0x000000C0L
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK 0x00000300L
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK 0x00000C00L
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK 0x00003000L
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK 0x0000C000L
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK 0x00030000L
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK 0x000C0000L
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK 0x00300000L
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK 0x00C00000L
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK 0x03000000L
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK 0x0C000000L
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK 0x30000000L
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK 0xC0000000L
-//TC_CFG_L1_STORE_POLICY
-#define TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT 0x0
-#define TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT 0x1
-#define TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT 0x2
-#define TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT 0x3
-#define TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT 0x4
-#define TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT 0x5
-#define TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT 0x6
-#define TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT 0x7
-#define TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT 0x8
-#define TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT 0x9
-#define TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT 0xa
-#define TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT 0xb
-#define TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT 0xc
-#define TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT 0xd
-#define TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT 0xe
-#define TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT 0xf
-#define TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT 0x10
-#define TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT 0x11
-#define TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT 0x12
-#define TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT 0x13
-#define TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT 0x14
-#define TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT 0x15
-#define TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT 0x16
-#define TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT 0x17
-#define TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT 0x18
-#define TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT 0x19
-#define TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT 0x1a
-#define TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT 0x1b
-#define TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT 0x1c
-#define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT 0x1d
-#define TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT 0x1e
-#define TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT 0x1f
-#define TC_CFG_L1_STORE_POLICY__POLICY_0_MASK 0x00000001L
-#define TC_CFG_L1_STORE_POLICY__POLICY_1_MASK 0x00000002L
-#define TC_CFG_L1_STORE_POLICY__POLICY_2_MASK 0x00000004L
-#define TC_CFG_L1_STORE_POLICY__POLICY_3_MASK 0x00000008L
-#define TC_CFG_L1_STORE_POLICY__POLICY_4_MASK 0x00000010L
-#define TC_CFG_L1_STORE_POLICY__POLICY_5_MASK 0x00000020L
-#define TC_CFG_L1_STORE_POLICY__POLICY_6_MASK 0x00000040L
-#define TC_CFG_L1_STORE_POLICY__POLICY_7_MASK 0x00000080L
-#define TC_CFG_L1_STORE_POLICY__POLICY_8_MASK 0x00000100L
-#define TC_CFG_L1_STORE_POLICY__POLICY_9_MASK 0x00000200L
-#define TC_CFG_L1_STORE_POLICY__POLICY_10_MASK 0x00000400L
-#define TC_CFG_L1_STORE_POLICY__POLICY_11_MASK 0x00000800L
-#define TC_CFG_L1_STORE_POLICY__POLICY_12_MASK 0x00001000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_13_MASK 0x00002000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_14_MASK 0x00004000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_15_MASK 0x00008000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_16_MASK 0x00010000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_17_MASK 0x00020000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_18_MASK 0x00040000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_19_MASK 0x00080000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_20_MASK 0x00100000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_21_MASK 0x00200000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_22_MASK 0x00400000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_23_MASK 0x00800000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_24_MASK 0x01000000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_25_MASK 0x02000000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_26_MASK 0x04000000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_27_MASK 0x08000000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_28_MASK 0x10000000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_29_MASK 0x20000000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_30_MASK 0x40000000L
-#define TC_CFG_L1_STORE_POLICY__POLICY_31_MASK 0x80000000L
-//TC_CFG_L2_LOAD_POLICY0
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT 0x0
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT 0x2
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT 0x4
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT 0x6
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT 0x8
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT 0xa
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT 0xc
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT 0xe
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT 0x10
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT 0x12
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT 0x14
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT 0x16
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT 0x18
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT 0x1a
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT 0x1c
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT 0x1e
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK 0x00000003L
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK 0x0000000CL
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK 0x00000030L
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK 0x000000C0L
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK 0x00000300L
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK 0x00000C00L
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK 0x00003000L
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK 0x0000C000L
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK 0x00030000L
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK 0x000C0000L
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK 0x00300000L
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK 0x00C00000L
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK 0x03000000L
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK 0x0C000000L
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK 0x30000000L
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK 0xC0000000L
-//TC_CFG_L2_LOAD_POLICY1
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT 0x0
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT 0x2
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT 0x4
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT 0x6
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT 0x8
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT 0xa
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT 0xc
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT 0xe
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT 0x10
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT 0x12
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT 0x14
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT 0x16
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT 0x18
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT 0x1a
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT 0x1c
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT 0x1e
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK 0x00000003L
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK 0x0000000CL
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK 0x00000030L
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK 0x000000C0L
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK 0x00000300L
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK 0x00000C00L
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK 0x00003000L
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK 0x0000C000L
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK 0x00030000L
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK 0x000C0000L
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK 0x00300000L
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK 0x00C00000L
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK 0x03000000L
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK 0x0C000000L
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK 0x30000000L
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK 0xC0000000L
-//TC_CFG_L2_STORE_POLICY0
-#define TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT 0x0
-#define TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT 0x2
-#define TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT 0x4
-#define TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT 0x6
-#define TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT 0x8
-#define TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT 0xa
-#define TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT 0xc
-#define TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT 0xe
-#define TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT 0x10
-#define TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT 0x12
-#define TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT 0x14
-#define TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT 0x16
-#define TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT 0x18
-#define TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT 0x1a
-#define TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT 0x1c
-#define TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT 0x1e
-#define TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK 0x00000003L
-#define TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK 0x0000000CL
-#define TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK 0x00000030L
-#define TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK 0x000000C0L
-#define TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK 0x00000300L
-#define TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK 0x00000C00L
-#define TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK 0x00003000L
-#define TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK 0x0000C000L
-#define TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK 0x00030000L
-#define TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK 0x000C0000L
-#define TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK 0x00300000L
-#define TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK 0x00C00000L
-#define TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK 0x03000000L
-#define TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK 0x0C000000L
-#define TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK 0x30000000L
-#define TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK 0xC0000000L
-//TC_CFG_L2_STORE_POLICY1
-#define TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT 0x0
-#define TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT 0x2
-#define TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT 0x4
-#define TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT 0x6
-#define TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT 0x8
-#define TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT 0xa
-#define TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT 0xc
-#define TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT 0xe
-#define TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT 0x10
-#define TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT 0x12
-#define TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT 0x14
-#define TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT 0x16
-#define TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT 0x18
-#define TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT 0x1a
-#define TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT 0x1c
-#define TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT 0x1e
-#define TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK 0x00000003L
-#define TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK 0x0000000CL
-#define TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK 0x00000030L
-#define TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK 0x000000C0L
-#define TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK 0x00000300L
-#define TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK 0x00000C00L
-#define TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK 0x00003000L
-#define TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK 0x0000C000L
-#define TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK 0x00030000L
-#define TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK 0x000C0000L
-#define TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK 0x00300000L
-#define TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK 0x00C00000L
-#define TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK 0x03000000L
-#define TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK 0x0C000000L
-#define TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK 0x30000000L
-#define TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK 0xC0000000L
-//TC_CFG_L2_ATOMIC_POLICY
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT 0x0
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT 0x2
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT 0x4
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT 0x6
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT 0x8
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT 0xa
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT 0xc
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT 0xe
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT 0x10
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT 0x12
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT 0x14
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT 0x16
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT 0x18
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT 0x1a
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT 0x1c
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT 0x1e
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK 0x00000003L
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK 0x0000000CL
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK 0x00000030L
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK 0x000000C0L
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK 0x00000300L
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK 0x00000C00L
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK 0x00003000L
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK 0x0000C000L
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK 0x00030000L
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK 0x000C0000L
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK 0x00300000L
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK 0x00C00000L
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK 0x03000000L
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK 0x0C000000L
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK 0x30000000L
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK 0xC0000000L
-//TC_CFG_L1_VOLATILE
-#define TC_CFG_L1_VOLATILE__VOL__SHIFT 0x0
-#define TC_CFG_L1_VOLATILE__VOL_MASK 0x0000000FL
-//TC_CFG_L2_VOLATILE
-#define TC_CFG_L2_VOLATILE__VOL__SHIFT 0x0
-#define TC_CFG_L2_VOLATILE__VOL_MASK 0x0000000FL
-//TCI_STATUS
-#define TCI_STATUS__TCI_BUSY__SHIFT 0x0
-#define TCI_STATUS__TCI_BUSY_MASK 0x00000001L
-//TCI_CNTL_1
-#define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x0
-#define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x10
-#define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x18
-#define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0x0000FFFFL
-#define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0x00FF0000L
-#define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xFF000000L
-//TCI_CNTL_2
-#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x0
-#define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x1
-#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x00000001L
-#define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x000001FEL
-//TCC_CTRL
-#define TCC_CTRL__CACHE_SIZE__SHIFT 0x0
-#define TCC_CTRL__RATE__SHIFT 0x2
-#define TCC_CTRL__WRITEBACK_MARGIN__SHIFT 0x4
-#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE__SHIFT 0x8
-#define TCC_CTRL__SRC_FIFO_SIZE__SHIFT 0xc
-#define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10
-#define TCC_CTRL__LINEAR_SET_HASH__SHIFT 0x15
-#define TCC_CTRL__MDC_SIZE__SHIFT 0x18
-#define TCC_CTRL__MDC_SECTOR_SIZE__SHIFT 0x1a
-#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE__SHIFT 0x1c
-#define TCC_CTRL__CACHE_SIZE_MASK 0x00000003L
-#define TCC_CTRL__RATE_MASK 0x0000000CL
-#define TCC_CTRL__WRITEBACK_MARGIN_MASK 0x000000F0L
-#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK 0x00000F00L
-#define TCC_CTRL__SRC_FIFO_SIZE_MASK 0x0000F000L
-#define TCC_CTRL__LATENCY_FIFO_SIZE_MASK 0x000F0000L
-#define TCC_CTRL__LINEAR_SET_HASH_MASK 0x00200000L
-#define TCC_CTRL__MDC_SIZE_MASK 0x03000000L
-#define TCC_CTRL__MDC_SECTOR_SIZE_MASK 0x0C000000L
-#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE_MASK 0xF0000000L
-//TCC_CTRL2
-#define TCC_CTRL2__PROBE_FIFO_SIZE__SHIFT 0x0
-#define TCC_CTRL2__PROBE_FIFO_SIZE_MASK 0x0000000FL
-//TCC_EDC_CNT
-#define TCC_EDC_CNT__CACHE_DATA_SEC_COUNT__SHIFT 0x0
-#define TCC_EDC_CNT__CACHE_DATA_DED_COUNT__SHIFT 0x2
-#define TCC_EDC_CNT__CACHE_DIRTY_SEC_COUNT__SHIFT 0x4
-#define TCC_EDC_CNT__CACHE_DIRTY_DED_COUNT__SHIFT 0x6
-#define TCC_EDC_CNT__HIGH_RATE_TAG_SEC_COUNT__SHIFT 0x8
-#define TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT__SHIFT 0xa
-#define TCC_EDC_CNT__LOW_RATE_TAG_SEC_COUNT__SHIFT 0xc
-#define TCC_EDC_CNT__LOW_RATE_TAG_DED_COUNT__SHIFT 0xe
-#define TCC_EDC_CNT__SRC_FIFO_SEC_COUNT__SHIFT 0x10
-#define TCC_EDC_CNT__SRC_FIFO_DED_COUNT__SHIFT 0x12
-#define TCC_EDC_CNT__IN_USE_DEC_SED_COUNT__SHIFT 0x14
-#define TCC_EDC_CNT__IN_USE_TRANSFER_SED_COUNT__SHIFT 0x16
-#define TCC_EDC_CNT__LATENCY_FIFO_SED_COUNT__SHIFT 0x18
-#define TCC_EDC_CNT__RETURN_DATA_SED_COUNT__SHIFT 0x1a
-#define TCC_EDC_CNT__RETURN_CONTROL_SED_COUNT__SHIFT 0x1c
-#define TCC_EDC_CNT__UC_ATOMIC_FIFO_SED_COUNT__SHIFT 0x1e
-#define TCC_EDC_CNT__CACHE_DATA_SEC_COUNT_MASK 0x00000003L
-#define TCC_EDC_CNT__CACHE_DATA_DED_COUNT_MASK 0x0000000CL
-#define TCC_EDC_CNT__CACHE_DIRTY_SEC_COUNT_MASK 0x00000030L
-#define TCC_EDC_CNT__CACHE_DIRTY_DED_COUNT_MASK 0x000000C0L
-#define TCC_EDC_CNT__HIGH_RATE_TAG_SEC_COUNT_MASK 0x00000300L
-#define TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT_MASK 0x00000C00L
-#define TCC_EDC_CNT__LOW_RATE_TAG_SEC_COUNT_MASK 0x00003000L
-#define TCC_EDC_CNT__LOW_RATE_TAG_DED_COUNT_MASK 0x0000C000L
-#define TCC_EDC_CNT__SRC_FIFO_SEC_COUNT_MASK 0x00030000L
-#define TCC_EDC_CNT__SRC_FIFO_DED_COUNT_MASK 0x000C0000L
-#define TCC_EDC_CNT__IN_USE_DEC_SED_COUNT_MASK 0x00300000L
-#define TCC_EDC_CNT__IN_USE_TRANSFER_SED_COUNT_MASK 0x00C00000L
-#define TCC_EDC_CNT__LATENCY_FIFO_SED_COUNT_MASK 0x03000000L
-#define TCC_EDC_CNT__RETURN_DATA_SED_COUNT_MASK 0x0C000000L
-#define TCC_EDC_CNT__RETURN_CONTROL_SED_COUNT_MASK 0x30000000L
-#define TCC_EDC_CNT__UC_ATOMIC_FIFO_SED_COUNT_MASK 0xC0000000L
-//TCC_EDC_CNT2
-#define TCC_EDC_CNT2__WRITE_RETURN_SED_COUNT__SHIFT 0x0
-#define TCC_EDC_CNT2__WRITE_CACHE_READ_SED_COUNT__SHIFT 0x2
-#define TCC_EDC_CNT2__SRC_FIFO_NEXT_RAM_SED_COUNT__SHIFT 0x4
-#define TCC_EDC_CNT2__LATENCY_FIFO_NEXT_RAM_SED_COUNT__SHIFT 0x6
-#define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SED_COUNT__SHIFT 0x8
-#define TCC_EDC_CNT2__WRITE_RETURN_SED_COUNT_MASK 0x00000003L
-#define TCC_EDC_CNT2__WRITE_CACHE_READ_SED_COUNT_MASK 0x0000000CL
-#define TCC_EDC_CNT2__SRC_FIFO_NEXT_RAM_SED_COUNT_MASK 0x00000030L
-#define TCC_EDC_CNT2__LATENCY_FIFO_NEXT_RAM_SED_COUNT_MASK 0x000000C0L
-#define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SED_COUNT_MASK 0x00000300L
-//TCC_REDUNDANCY
-#define TCC_REDUNDANCY__MC_SEL0__SHIFT 0x0
-#define TCC_REDUNDANCY__MC_SEL1__SHIFT 0x1
-#define TCC_REDUNDANCY__MC_SEL0_MASK 0x00000001L
-#define TCC_REDUNDANCY__MC_SEL1_MASK 0x00000002L
-//TCC_EXE_DISABLE
-#define TCC_EXE_DISABLE__EXE_DISABLE__SHIFT 0x1
-#define TCC_EXE_DISABLE__EXE_DISABLE_MASK 0x00000002L
-//TCC_DSM_CNTL
-#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL__SHIFT 0x0
-#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE__SHIFT 0x2
-#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL__SHIFT 0x3
-#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE__SHIFT 0x5
-#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL__SHIFT 0x6
-#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE__SHIFT 0x8
-#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL__SHIFT 0x9
-#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE__SHIFT 0xb
-#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL__SHIFT 0xc
-#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE__SHIFT 0xe
-#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL__SHIFT 0xf
-#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE__SHIFT 0x11
-#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT 0x12
-#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT 0x14
-#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT 0x15
-#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT 0x17
-#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL__SHIFT 0x18
-#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE__SHIFT 0x1a
-#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL__SHIFT 0x1b
-#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE__SHIFT 0x1d
-#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL_MASK 0x00000003L
-#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L
-#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL_MASK 0x00000018L
-#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L
-#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL_MASK 0x000000C0L
-#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L
-#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL_MASK 0x00000600L
-#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L
-#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL_MASK 0x00003000L
-#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L
-#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL_MASK 0x00018000L
-#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L
-#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL_MASK 0x000C0000L
-#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L
-#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL_MASK 0x00600000L
-#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L
-#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL_MASK 0x03000000L
-#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE_MASK 0x04000000L
-#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL_MASK 0x18000000L
-#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE_MASK 0x20000000L
-//TCC_DSM_CNTLA
-#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x0
-#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x2
-#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x3
-#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x5
-#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL__SHIFT 0x6
-#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE__SHIFT 0x8
-#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL__SHIFT 0x9
-#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE__SHIFT 0xb
-#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL__SHIFT 0xc
-#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0xe
-#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL__SHIFT 0xf
-#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x11
-#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x12
-#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x14
-#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x15
-#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x17
-#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL__SHIFT 0x18
-#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE__SHIFT 0x1a
-#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL__SHIFT 0x1b
-#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE__SHIFT 0x1d
-#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL_MASK 0x00000003L
-#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L
-#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL_MASK 0x00000018L
-#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L
-#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL_MASK 0x000000C0L
-#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L
-#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL_MASK 0x00000600L
-#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L
-#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL_MASK 0x00003000L
-#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L
-#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL_MASK 0x00018000L
-#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L
-#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL_MASK 0x000C0000L
-#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L
-#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL_MASK 0x00600000L
-#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L
-#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL_MASK 0x03000000L
-#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE_MASK 0x04000000L
-#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL_MASK 0x18000000L
-#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE_MASK 0x20000000L
-//TCC_DSM_CNTL2
-#define TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY__SHIFT 0x2
-#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT__SHIFT 0x3
-#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY__SHIFT 0x5
-#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT__SHIFT 0x6
-#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY__SHIFT 0x8
-#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT__SHIFT 0x9
-#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY__SHIFT 0xb
-#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT__SHIFT 0xc
-#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY__SHIFT 0xe
-#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT__SHIFT 0xf
-#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY__SHIFT 0x11
-#define TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT 0x12
-#define TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY__SHIFT 0x14
-#define TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT 0x15
-#define TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY__SHIFT 0x17
-#define TCC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
-#define TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT_MASK 0x00000018L
-#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY_MASK 0x00000020L
-#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT_MASK 0x000000C0L
-#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY_MASK 0x00000100L
-#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT_MASK 0x00000600L
-#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY_MASK 0x00000800L
-#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT_MASK 0x00003000L
-#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY_MASK 0x00004000L
-#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT_MASK 0x00018000L
-#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY_MASK 0x00020000L
-#define TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT_MASK 0x000C0000L
-#define TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY_MASK 0x00100000L
-#define TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT_MASK 0x00600000L
-#define TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY_MASK 0x00800000L
-#define TCC_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
-//TCC_DSM_CNTL2A
-#define TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY__SHIFT 0x2
-#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT__SHIFT 0x3
-#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY__SHIFT 0x5
-#define TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT__SHIFT 0x6
-#define TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY__SHIFT 0x8
-#define TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT__SHIFT 0x9
-#define TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY__SHIFT 0xb
-#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xc
-#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY__SHIFT 0xe
-#define TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT__SHIFT 0xf
-#define TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY__SHIFT 0x11
-#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT__SHIFT 0x12
-#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY__SHIFT 0x14
-#define TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x15
-#define TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY__SHIFT 0x17
-#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18
-#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a
-#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x1b
-#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY__SHIFT 0x1d
-#define TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT_MASK 0x00000018L
-#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY_MASK 0x00000020L
-#define TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT_MASK 0x000000C0L
-#define TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY_MASK 0x00000100L
-#define TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT_MASK 0x00000600L
-#define TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY_MASK 0x00000800L
-#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L
-#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY_MASK 0x00004000L
-#define TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT_MASK 0x00018000L
-#define TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY_MASK 0x00020000L
-#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT_MASK 0x000C0000L
-#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY_MASK 0x00100000L
-#define TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT_MASK 0x00600000L
-#define TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY_MASK 0x00800000L
-#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L
-#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L
-#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT_MASK 0x18000000L
-#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY_MASK 0x20000000L
-//TCC_DSM_CNTL2B
-#define TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY__SHIFT 0x2
-#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x3
-#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY__SHIFT 0x5
-#define TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT_MASK 0x00000018L
-#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY_MASK 0x00000020L
-//TCC_WBINVL2
-#define TCC_WBINVL2__DONE__SHIFT 0x4
-#define TCC_WBINVL2__DONE_MASK 0x00000010L
-//TCC_SOFT_RESET
-#define TCC_SOFT_RESET__HALT_FOR_RESET__SHIFT 0x0
-#define TCC_SOFT_RESET__HALT_FOR_RESET_MASK 0x00000001L
-//TCA_CTRL
-#define TCA_CTRL__HOLE_TIMEOUT__SHIFT 0x0
-#define TCA_CTRL__RB_STILL_4_PHASE__SHIFT 0x4
-#define TCA_CTRL__RB_AS_TCI__SHIFT 0x5
-#define TCA_CTRL__DISABLE_UTCL2_PRIORITY__SHIFT 0x6
-#define TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER__SHIFT 0x7
-#define TCA_CTRL__HOLE_TIMEOUT_MASK 0x0000000FL
-#define TCA_CTRL__RB_STILL_4_PHASE_MASK 0x00000010L
-#define TCA_CTRL__RB_AS_TCI_MASK 0x00000020L
-#define TCA_CTRL__DISABLE_UTCL2_PRIORITY_MASK 0x00000040L
-#define TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER_MASK 0x00000080L
-//TCA_BURST_MASK
-#define TCA_BURST_MASK__ADDR_MASK__SHIFT 0x0
-#define TCA_BURST_MASK__ADDR_MASK_MASK 0xFFFFFFFFL
-//TCA_BURST_CTRL
-#define TCA_BURST_CTRL__MAX_BURST__SHIFT 0x0
-#define TCA_BURST_CTRL__RB_DISABLE__SHIFT 0x3
-#define TCA_BURST_CTRL__TCP_DISABLE__SHIFT 0x4
-#define TCA_BURST_CTRL__SQC_DISABLE__SHIFT 0x5
-#define TCA_BURST_CTRL__CPF_DISABLE__SHIFT 0x6
-#define TCA_BURST_CTRL__CPG_DISABLE__SHIFT 0x7
-#define TCA_BURST_CTRL__IA_DISABLE__SHIFT 0x8
-#define TCA_BURST_CTRL__WD_DISABLE__SHIFT 0x9
-#define TCA_BURST_CTRL__SQG_DISABLE__SHIFT 0xa
-#define TCA_BURST_CTRL__UTCL2_DISABLE__SHIFT 0xb
-#define TCA_BURST_CTRL__TPI_DISABLE__SHIFT 0xc
-#define TCA_BURST_CTRL__RLC_DISABLE__SHIFT 0xd
-#define TCA_BURST_CTRL__PA_DISABLE__SHIFT 0xe
-#define TCA_BURST_CTRL__MAX_BURST_MASK 0x00000007L
-#define TCA_BURST_CTRL__RB_DISABLE_MASK 0x00000008L
-#define TCA_BURST_CTRL__TCP_DISABLE_MASK 0x00000010L
-#define TCA_BURST_CTRL__SQC_DISABLE_MASK 0x00000020L
-#define TCA_BURST_CTRL__CPF_DISABLE_MASK 0x00000040L
-#define TCA_BURST_CTRL__CPG_DISABLE_MASK 0x00000080L
-#define TCA_BURST_CTRL__IA_DISABLE_MASK 0x00000100L
-#define TCA_BURST_CTRL__WD_DISABLE_MASK 0x00000200L
-#define TCA_BURST_CTRL__SQG_DISABLE_MASK 0x00000400L
-#define TCA_BURST_CTRL__UTCL2_DISABLE_MASK 0x00000800L
-#define TCA_BURST_CTRL__TPI_DISABLE_MASK 0x00001000L
-#define TCA_BURST_CTRL__RLC_DISABLE_MASK 0x00002000L
-#define TCA_BURST_CTRL__PA_DISABLE_MASK 0x00004000L
-//TCA_DSM_CNTL
-#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT 0x0
-#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT 0x2
-#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT 0x3
-#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT 0x5
-#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL_MASK 0x00000003L
-#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L
-#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL_MASK 0x00000018L
-#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L
-//TCA_DSM_CNTL2
-#define TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY__SHIFT 0x2
-#define TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT 0x3
-#define TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY__SHIFT 0x5
-#define TCA_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
-#define TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT_MASK 0x00000018L
-#define TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY_MASK 0x00000020L
-#define TCA_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
-//TCA_EDC_CNT
-#define TCA_EDC_CNT__HOLE_FIFO_SED_COUNT__SHIFT 0x0
-#define TCA_EDC_CNT__REQ_FIFO_SED_COUNT__SHIFT 0x2
-#define TCA_EDC_CNT__HOLE_FIFO_SED_COUNT_MASK 0x00000003L
-#define TCA_EDC_CNT__REQ_FIFO_SED_COUNT_MASK 0x0000000CL
-
-
-// addressBlock: gc_shdec
-//SPI_SHADER_PGM_RSRC3_PS
-#define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT 0x10
-#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT 0x16
-#define SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE__SHIFT 0x1a
-#define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0x0000FFFFL
-#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK 0x003F0000L
-#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L
-#define SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE_MASK 0x3C000000L
-//SPI_SHADER_PGM_LO_PS
-#define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xFFFFFFFFL
-//SPI_SHADER_PGM_HI_PS
-#define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0xFFL
-//SPI_SHADER_PGM_RSRC1_PS
-#define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa
-#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0xc
-#define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14
-#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x15
-#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x17
-#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x18
-#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL__SHIFT 0x1d
-#define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x0000003FL
-#define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x000003C0L
-#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0x00000C00L
-#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0x000FF000L
-#define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x00100000L
-#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x00200000L
-#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x00800000L
-#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x01000000L
-#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL_MASK 0x20000000L
-//SPI_SHADER_PGM_RSRC2_PS
-#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x1
-#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x7
-#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x8
-#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x10
-#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID__SHIFT 0x19
-#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION__SHIFT 0x1a
-#define SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0__SHIFT 0x1b
-#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB__SHIFT 0x1c
-#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x00000001L
-#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x0000003EL
-#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x00000040L
-#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x00000080L
-#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0x0000FF00L
-#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x01FF0000L
-#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID_MASK 0x02000000L
-#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION_MASK 0x04000000L
-#define SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0_MASK 0x08000000L
-#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB_MASK 0x10000000L
-//SPI_SHADER_USER_DATA_PS_0
-#define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_1
-#define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_2
-#define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_3
-#define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_4
-#define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_5
-#define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_6
-#define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_7
-#define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_8
-#define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_9
-#define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_10
-#define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_11
-#define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_12
-#define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_13
-#define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_14
-#define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_15
-#define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_16
-#define SPI_SHADER_USER_DATA_PS_16__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_16__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_17
-#define SPI_SHADER_USER_DATA_PS_17__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_17__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_18
-#define SPI_SHADER_USER_DATA_PS_18__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_18__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_19
-#define SPI_SHADER_USER_DATA_PS_19__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_19__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_20
-#define SPI_SHADER_USER_DATA_PS_20__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_20__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_21
-#define SPI_SHADER_USER_DATA_PS_21__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_21__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_22
-#define SPI_SHADER_USER_DATA_PS_22__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_22__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_23
-#define SPI_SHADER_USER_DATA_PS_23__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_23__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_24
-#define SPI_SHADER_USER_DATA_PS_24__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_24__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_25
-#define SPI_SHADER_USER_DATA_PS_25__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_25__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_26
-#define SPI_SHADER_USER_DATA_PS_26__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_26__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_27
-#define SPI_SHADER_USER_DATA_PS_27__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_27__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_28
-#define SPI_SHADER_USER_DATA_PS_28__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_28__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_29
-#define SPI_SHADER_USER_DATA_PS_29__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_29__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_30
-#define SPI_SHADER_USER_DATA_PS_30__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_30__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_PS_31
-#define SPI_SHADER_USER_DATA_PS_31__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_31__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_PGM_RSRC3_VS
-#define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT 0x10
-#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT 0x16
-#define SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE__SHIFT 0x1a
-#define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK 0x0000FFFFL
-#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK 0x003F0000L
-#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L
-#define SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE_MASK 0x3C000000L
-//SPI_SHADER_LATE_ALLOC_VS
-#define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT 0x0
-#define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK 0x0000003FL
-//SPI_SHADER_PGM_LO_VS
-#define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xFFFFFFFFL
-//SPI_SHADER_PGM_HI_VS
-#define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0xFFL
-//SPI_SHADER_PGM_RSRC1_VS
-#define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0xa
-#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0xc
-#define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x14
-#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x15
-#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x17
-#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x18
-#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x1a
-#define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL__SHIFT 0x1f
-#define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x0000003FL
-#define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x000003C0L
-#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0x00000C00L
-#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0x000FF000L
-#define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x00100000L
-#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x00200000L
-#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x00800000L
-#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x03000000L
-#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x04000000L
-#define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL_MASK 0x80000000L
-//SPI_SHADER_PGM_RSRC2_VS
-#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x1
-#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x7
-#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x8
-#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x9
-#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0xa
-#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0xb
-#define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0xc
-#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0xd
-#define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN__SHIFT 0x16
-#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN__SHIFT 0x18
-#define SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0__SHIFT 0x1b
-#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB__SHIFT 0x1c
-#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x00000001L
-#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x0000003EL
-#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x00000040L
-#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x00000080L
-#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x00000100L
-#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x00000200L
-#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x00000400L
-#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x00000800L
-#define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x00001000L
-#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x003FE000L
-#define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN_MASK 0x00400000L
-#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN_MASK 0x01000000L
-#define SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0_MASK 0x08000000L
-#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB_MASK 0x10000000L
-//SPI_SHADER_USER_DATA_VS_0
-#define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_1
-#define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_2
-#define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_3
-#define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_4
-#define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_5
-#define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_6
-#define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_7
-#define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_8
-#define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_9
-#define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_10
-#define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_11
-#define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_12
-#define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_13
-#define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_14
-#define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_15
-#define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_16
-#define SPI_SHADER_USER_DATA_VS_16__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_16__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_17
-#define SPI_SHADER_USER_DATA_VS_17__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_17__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_18
-#define SPI_SHADER_USER_DATA_VS_18__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_18__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_19
-#define SPI_SHADER_USER_DATA_VS_19__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_19__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_20
-#define SPI_SHADER_USER_DATA_VS_20__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_20__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_21
-#define SPI_SHADER_USER_DATA_VS_21__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_21__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_22
-#define SPI_SHADER_USER_DATA_VS_22__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_22__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_23
-#define SPI_SHADER_USER_DATA_VS_23__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_23__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_24
-#define SPI_SHADER_USER_DATA_VS_24__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_24__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_25
-#define SPI_SHADER_USER_DATA_VS_25__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_25__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_26
-#define SPI_SHADER_USER_DATA_VS_26__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_26__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_27
-#define SPI_SHADER_USER_DATA_VS_27__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_27__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_28
-#define SPI_SHADER_USER_DATA_VS_28__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_28__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_29
-#define SPI_SHADER_USER_DATA_VS_29__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_29__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_30
-#define SPI_SHADER_USER_DATA_VS_30__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_30__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_VS_31
-#define SPI_SHADER_USER_DATA_VS_31__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_31__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_PGM_RSRC2_GS_VS
-#define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR__SHIFT 0x1
-#define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN__SHIFT 0x7
-#define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT__SHIFT 0x10
-#define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN__SHIFT 0x12
-#define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE__SHIFT 0x13
-#define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0__SHIFT 0x1b
-#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB__SHIFT 0x1c
-#define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN_MASK 0x00000001L
-#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MASK 0x0000003EL
-#define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT_MASK 0x00000040L
-#define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN_MASK 0x0000FF80L
-#define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT_MASK 0x00030000L
-#define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN_MASK 0x00040000L
-#define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE_MASK 0x07F80000L
-#define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0_MASK 0x08000000L
-#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB_MASK 0x10000000L
-//SPI_SHADER_PGM_RSRC4_GS
-#define SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS__SHIFT 0x7
-#define SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH_MASK 0x0000007FL
-#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS_MASK 0x00003F80L
-//SPI_SHADER_USER_DATA_ADDR_LO_GS
-#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ADDR_HI_GS
-#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE_MASK 0xFFFFFFFFL
-//SPI_SHADER_PGM_LO_ES
-#define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xFFFFFFFFL
-//SPI_SHADER_PGM_HI_ES
-#define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0xFFL
-//SPI_SHADER_PGM_RSRC3_GS
-#define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT 0x10
-#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT 0x16
-#define SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE__SHIFT 0x1a
-#define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0x0000FFFFL
-#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK 0x003F0000L
-#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L
-#define SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE_MASK 0x3C000000L
-//SPI_SHADER_PGM_LO_GS
-#define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL
-//SPI_SHADER_PGM_HI_GS
-#define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0xFFL
-//SPI_SHADER_PGM_RSRC1_GS
-#define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa
-#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0xc
-#define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14
-#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x15
-#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x17
-#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x18
-#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT__SHIFT 0x1d
-#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL__SHIFT 0x1f
-#define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x0000003FL
-#define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x000003C0L
-#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0x00000C00L
-#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0x000FF000L
-#define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x00100000L
-#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x00200000L
-#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x00800000L
-#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x01000000L
-#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT_MASK 0x60000000L
-#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL_MASK 0x80000000L
-//SPI_SHADER_PGM_RSRC2_GS
-#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x1
-#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x7
-#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT__SHIFT 0x10
-#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN__SHIFT 0x12
-#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE__SHIFT 0x13
-#define SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0__SHIFT 0x1b
-#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB__SHIFT 0x1c
-#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x00000001L
-#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x0000003EL
-#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x00000040L
-#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0x0000FF80L
-#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT_MASK 0x00030000L
-#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN_MASK 0x00040000L
-#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE_MASK 0x07F80000L
-#define SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0_MASK 0x08000000L
-#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB_MASK 0x10000000L
-//SPI_SHADER_USER_DATA_ES_0
-#define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_1
-#define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_2
-#define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_3
-#define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_4
-#define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_5
-#define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_6
-#define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_7
-#define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_8
-#define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_9
-#define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_10
-#define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_11
-#define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_12
-#define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_13
-#define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_14
-#define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_15
-#define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_16
-#define SPI_SHADER_USER_DATA_ES_16__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_16__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_17
-#define SPI_SHADER_USER_DATA_ES_17__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_17__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_18
-#define SPI_SHADER_USER_DATA_ES_18__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_18__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_19
-#define SPI_SHADER_USER_DATA_ES_19__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_19__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_20
-#define SPI_SHADER_USER_DATA_ES_20__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_20__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_21
-#define SPI_SHADER_USER_DATA_ES_21__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_21__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_22
-#define SPI_SHADER_USER_DATA_ES_22__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_22__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_23
-#define SPI_SHADER_USER_DATA_ES_23__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_23__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_24
-#define SPI_SHADER_USER_DATA_ES_24__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_24__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_25
-#define SPI_SHADER_USER_DATA_ES_25__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_25__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_26
-#define SPI_SHADER_USER_DATA_ES_26__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_26__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_27
-#define SPI_SHADER_USER_DATA_ES_27__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_27__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_28
-#define SPI_SHADER_USER_DATA_ES_28__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_28__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_29
-#define SPI_SHADER_USER_DATA_ES_29__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_29__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_30
-#define SPI_SHADER_USER_DATA_ES_30__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_30__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ES_31
-#define SPI_SHADER_USER_DATA_ES_31__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_31__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_PGM_RSRC4_HS
-#define SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH_MASK 0x0000007FL
-//SPI_SHADER_USER_DATA_ADDR_LO_HS
-#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_ADDR_HI_HS
-#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE_MASK 0xFFFFFFFFL
-//SPI_SHADER_PGM_LO_LS
-#define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xFFFFFFFFL
-//SPI_SHADER_PGM_HI_LS
-#define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0xFFL
-//SPI_SHADER_PGM_RSRC3_HS
-#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE__SHIFT 0xa
-#define SPI_SHADER_PGM_RSRC3_HS__CU_EN__SHIFT 0x10
-#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK 0x0000003FL
-#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK 0x000003C0L
-#define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE_MASK 0x00003C00L
-#define SPI_SHADER_PGM_RSRC3_HS__CU_EN_MASK 0xFFFF0000L
-//SPI_SHADER_PGM_LO_HS
-#define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL
-//SPI_SHADER_PGM_HI_HS
-#define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0xFFL
-//SPI_SHADER_PGM_RSRC1_HS
-#define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa
-#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0xc
-#define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14
-#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x15
-#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x17
-#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT__SHIFT 0x1c
-#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL__SHIFT 0x1e
-#define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x0000003FL
-#define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x000003C0L
-#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0x00000C00L
-#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0x000FF000L
-#define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x00100000L
-#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x00200000L
-#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x00800000L
-#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT_MASK 0x30000000L
-#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL_MASK 0x40000000L
-//SPI_SHADER_PGM_RSRC2_HS
-#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x1
-#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x7
-#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE__SHIFT 0x10
-#define SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0__SHIFT 0x1b
-#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB__SHIFT 0x1c
-#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x00000001L
-#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x0000003EL
-#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x00000040L
-#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x0000FF80L
-#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE_MASK 0x01FF0000L
-#define SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0_MASK 0x08000000L
-#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB_MASK 0x10000000L
-//SPI_SHADER_USER_DATA_LS_0
-#define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_1
-#define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_2
-#define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_3
-#define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_4
-#define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_5
-#define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_6
-#define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_7
-#define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_8
-#define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_9
-#define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_10
-#define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_11
-#define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_12
-#define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_13
-#define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_14
-#define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_15
-#define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_16
-#define SPI_SHADER_USER_DATA_LS_16__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_16__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_17
-#define SPI_SHADER_USER_DATA_LS_17__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_17__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_18
-#define SPI_SHADER_USER_DATA_LS_18__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_18__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_19
-#define SPI_SHADER_USER_DATA_LS_19__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_19__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_20
-#define SPI_SHADER_USER_DATA_LS_20__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_20__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_21
-#define SPI_SHADER_USER_DATA_LS_21__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_21__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_22
-#define SPI_SHADER_USER_DATA_LS_22__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_22__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_23
-#define SPI_SHADER_USER_DATA_LS_23__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_23__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_24
-#define SPI_SHADER_USER_DATA_LS_24__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_24__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_25
-#define SPI_SHADER_USER_DATA_LS_25__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_25__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_26
-#define SPI_SHADER_USER_DATA_LS_26__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_26__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_27
-#define SPI_SHADER_USER_DATA_LS_27__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_27__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_28
-#define SPI_SHADER_USER_DATA_LS_28__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_28__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_29
-#define SPI_SHADER_USER_DATA_LS_29__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_29__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_30
-#define SPI_SHADER_USER_DATA_LS_30__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_30__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_LS_31
-#define SPI_SHADER_USER_DATA_LS_31__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_31__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_0
-#define SPI_SHADER_USER_DATA_COMMON_0__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_0__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_1
-#define SPI_SHADER_USER_DATA_COMMON_1__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_1__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_2
-#define SPI_SHADER_USER_DATA_COMMON_2__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_2__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_3
-#define SPI_SHADER_USER_DATA_COMMON_3__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_3__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_4
-#define SPI_SHADER_USER_DATA_COMMON_4__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_4__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_5
-#define SPI_SHADER_USER_DATA_COMMON_5__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_5__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_6
-#define SPI_SHADER_USER_DATA_COMMON_6__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_6__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_7
-#define SPI_SHADER_USER_DATA_COMMON_7__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_7__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_8
-#define SPI_SHADER_USER_DATA_COMMON_8__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_8__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_9
-#define SPI_SHADER_USER_DATA_COMMON_9__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_9__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_10
-#define SPI_SHADER_USER_DATA_COMMON_10__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_10__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_11
-#define SPI_SHADER_USER_DATA_COMMON_11__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_11__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_12
-#define SPI_SHADER_USER_DATA_COMMON_12__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_12__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_13
-#define SPI_SHADER_USER_DATA_COMMON_13__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_13__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_14
-#define SPI_SHADER_USER_DATA_COMMON_14__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_14__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_15
-#define SPI_SHADER_USER_DATA_COMMON_15__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_15__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_16
-#define SPI_SHADER_USER_DATA_COMMON_16__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_16__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_17
-#define SPI_SHADER_USER_DATA_COMMON_17__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_17__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_18
-#define SPI_SHADER_USER_DATA_COMMON_18__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_18__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_19
-#define SPI_SHADER_USER_DATA_COMMON_19__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_19__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_20
-#define SPI_SHADER_USER_DATA_COMMON_20__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_20__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_21
-#define SPI_SHADER_USER_DATA_COMMON_21__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_21__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_22
-#define SPI_SHADER_USER_DATA_COMMON_22__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_22__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_23
-#define SPI_SHADER_USER_DATA_COMMON_23__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_23__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_24
-#define SPI_SHADER_USER_DATA_COMMON_24__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_24__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_25
-#define SPI_SHADER_USER_DATA_COMMON_25__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_25__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_26
-#define SPI_SHADER_USER_DATA_COMMON_26__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_26__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_27
-#define SPI_SHADER_USER_DATA_COMMON_27__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_27__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_28
-#define SPI_SHADER_USER_DATA_COMMON_28__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_28__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_29
-#define SPI_SHADER_USER_DATA_COMMON_29__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_29__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_30
-#define SPI_SHADER_USER_DATA_COMMON_30__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_30__DATA_MASK 0xFFFFFFFFL
-//SPI_SHADER_USER_DATA_COMMON_31
-#define SPI_SHADER_USER_DATA_COMMON_31__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_COMMON_31__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_DISPATCH_INITIATOR
-#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0
-#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1
-#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2
-#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3
-#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4
-#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5
-#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6
-#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa
-#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb
-#define COMPUTE_DISPATCH_INITIATOR__RESERVED__SHIFT 0xc
-#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe
-#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x00000001L
-#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x00000002L
-#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x00000004L
-#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x00000008L
-#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x00000010L
-#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x00000020L
-#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x00000040L
-#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x00000400L
-#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x00000800L
-#define COMPUTE_DISPATCH_INITIATOR__RESERVED_MASK 0x00001000L
-#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x00004000L
-//COMPUTE_DIM_X
-#define COMPUTE_DIM_X__SIZE__SHIFT 0x0
-#define COMPUTE_DIM_X__SIZE_MASK 0xFFFFFFFFL
-//COMPUTE_DIM_Y
-#define COMPUTE_DIM_Y__SIZE__SHIFT 0x0
-#define COMPUTE_DIM_Y__SIZE_MASK 0xFFFFFFFFL
-//COMPUTE_DIM_Z
-#define COMPUTE_DIM_Z__SIZE__SHIFT 0x0
-#define COMPUTE_DIM_Z__SIZE_MASK 0xFFFFFFFFL
-//COMPUTE_START_X
-#define COMPUTE_START_X__START__SHIFT 0x0
-#define COMPUTE_START_X__START_MASK 0xFFFFFFFFL
-//COMPUTE_START_Y
-#define COMPUTE_START_Y__START__SHIFT 0x0
-#define COMPUTE_START_Y__START_MASK 0xFFFFFFFFL
-//COMPUTE_START_Z
-#define COMPUTE_START_Z__START__SHIFT 0x0
-#define COMPUTE_START_Z__START_MASK 0xFFFFFFFFL
-//COMPUTE_NUM_THREAD_X
-#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0
-#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10
-#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0x0000FFFFL
-#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L
-//COMPUTE_NUM_THREAD_Y
-#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0
-#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10
-#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0x0000FFFFL
-#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L
-//COMPUTE_NUM_THREAD_Z
-#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0
-#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10
-#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0x0000FFFFL
-#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L
-//COMPUTE_PIPELINESTAT_ENABLE
-#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0
-#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x00000001L
-//COMPUTE_PERFCOUNT_ENABLE
-#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0
-#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x00000001L
-//COMPUTE_PGM_LO
-#define COMPUTE_PGM_LO__DATA__SHIFT 0x0
-#define COMPUTE_PGM_LO__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_PGM_HI
-#define COMPUTE_PGM_HI__DATA__SHIFT 0x0
-#define COMPUTE_PGM_HI__DATA_MASK 0x000000FFL
-//COMPUTE_DISPATCH_PKT_ADDR_LO
-#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA__SHIFT 0x0
-#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_DISPATCH_PKT_ADDR_HI
-#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA__SHIFT 0x0
-#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA_MASK 0x000000FFL
-//COMPUTE_DISPATCH_SCRATCH_BASE_LO
-#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA__SHIFT 0x0
-#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_DISPATCH_SCRATCH_BASE_HI
-#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA__SHIFT 0x0
-#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA_MASK 0x000000FFL
-//COMPUTE_PGM_RSRC1
-#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0
-#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6
-#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa
-#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc
-#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14
-#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15
-#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17
-#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18
-#define COMPUTE_PGM_RSRC1__FP16_OVFL__SHIFT 0x1a
-#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x0000003FL
-#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x000003C0L
-#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0x00000C00L
-#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0x000FF000L
-#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x00100000L
-#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x00200000L
-#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x00800000L
-#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x01000000L
-#define COMPUTE_PGM_RSRC1__FP16_OVFL_MASK 0x04000000L
-//COMPUTE_PGM_RSRC2
-#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0
-#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1
-#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6
-#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7
-#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8
-#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9
-#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa
-#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb
-#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd
-#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf
-#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18
-#define COMPUTE_PGM_RSRC2__SKIP_USGPR0__SHIFT 0x1f
-#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x00000001L
-#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x0000003EL
-#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x00000040L
-#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x00000080L
-#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x00000100L
-#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x00000200L
-#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x00000400L
-#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x00001800L
-#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x00006000L
-#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0x00FF8000L
-#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7F000000L
-#define COMPUTE_PGM_RSRC2__SKIP_USGPR0_MASK 0x80000000L
-//COMPUTE_VMID
-#define COMPUTE_VMID__DATA__SHIFT 0x0
-#define COMPUTE_VMID__DATA_MASK 0x0000000FL
-//COMPUTE_RESOURCE_LIMITS
-#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0
-#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc
-#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10
-#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16
-#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17
-#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18
-#define COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE__SHIFT 0x1b
-#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x000003FFL
-#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0x0000F000L
-#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x003F0000L
-#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x00400000L
-#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x00800000L
-#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x07000000L
-#define COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE_MASK 0x78000000L
-//COMPUTE_STATIC_THREAD_MGMT_SE0
-#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x0
-#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x10
-#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0x0000FFFFL
-#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xFFFF0000L
-//COMPUTE_STATIC_THREAD_MGMT_SE1
-#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x0
-#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x10
-#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0x0000FFFFL
-#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xFFFF0000L
-//COMPUTE_TMPRING_SIZE
-#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0
-#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc
-#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0x00000FFFL
-#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x01FFF000L
-//COMPUTE_STATIC_THREAD_MGMT_SE2
-#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT 0x0
-#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT 0x10
-#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK 0x0000FFFFL
-#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK 0xFFFF0000L
-//COMPUTE_STATIC_THREAD_MGMT_SE3
-#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT 0x0
-#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT 0x10
-#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK 0x0000FFFFL
-#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK 0xFFFF0000L
-//COMPUTE_RESTART_X
-#define COMPUTE_RESTART_X__RESTART__SHIFT 0x0
-#define COMPUTE_RESTART_X__RESTART_MASK 0xFFFFFFFFL
-//COMPUTE_RESTART_Y
-#define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0
-#define COMPUTE_RESTART_Y__RESTART_MASK 0xFFFFFFFFL
-//COMPUTE_RESTART_Z
-#define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0
-#define COMPUTE_RESTART_Z__RESTART_MASK 0xFFFFFFFFL
-//COMPUTE_THREAD_TRACE_ENABLE
-#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0
-#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x00000001L
-//COMPUTE_MISC_RESERVED
-#define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0
-#define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT 0x2
-#define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT 0x3
-#define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4
-#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT 0x5
-#define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x00000003L
-#define COMPUTE_MISC_RESERVED__RESERVED2_MASK 0x00000004L
-#define COMPUTE_MISC_RESERVED__RESERVED3_MASK 0x00000008L
-#define COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x00000010L
-#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK 0x0001FFE0L
-//COMPUTE_DISPATCH_ID
-#define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT 0x0
-#define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK 0xFFFFFFFFL
-//COMPUTE_THREADGROUP_ID
-#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT 0x0
-#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK 0xFFFFFFFFL
-//COMPUTE_RELAUNCH
-#define COMPUTE_RELAUNCH__PAYLOAD__SHIFT 0x0
-#define COMPUTE_RELAUNCH__IS_EVENT__SHIFT 0x1e
-#define COMPUTE_RELAUNCH__IS_STATE__SHIFT 0x1f
-#define COMPUTE_RELAUNCH__PAYLOAD_MASK 0x3FFFFFFFL
-#define COMPUTE_RELAUNCH__IS_EVENT_MASK 0x40000000L
-#define COMPUTE_RELAUNCH__IS_STATE_MASK 0x80000000L
-//COMPUTE_WAVE_RESTORE_ADDR_LO
-#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT 0x0
-#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK 0xFFFFFFFFL
-//COMPUTE_WAVE_RESTORE_ADDR_HI
-#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT 0x0
-#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK 0xFFFFL
-//COMPUTE_USER_DATA_0
-#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_0__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_USER_DATA_1
-#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_1__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_USER_DATA_2
-#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_2__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_USER_DATA_3
-#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_3__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_USER_DATA_4
-#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_4__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_USER_DATA_5
-#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_5__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_USER_DATA_6
-#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_6__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_USER_DATA_7
-#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_7__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_USER_DATA_8
-#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_8__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_USER_DATA_9
-#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_9__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_USER_DATA_10
-#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_10__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_USER_DATA_11
-#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_11__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_USER_DATA_12
-#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_12__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_USER_DATA_13
-#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_13__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_USER_DATA_14
-#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_14__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_USER_DATA_15
-#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_15__DATA_MASK 0xFFFFFFFFL
-//COMPUTE_NOWHERE
-#define COMPUTE_NOWHERE__DATA__SHIFT 0x0
-#define COMPUTE_NOWHERE__DATA_MASK 0xFFFFFFFFL
-
-
-// addressBlock: gc_cppdec
-//CP_DFY_CNTL
-#define CP_DFY_CNTL__POLICY__SHIFT 0x0
-#define CP_DFY_CNTL__MTYPE__SHIFT 0x2
-#define CP_DFY_CNTL__TPI_SDP_SEL__SHIFT 0x1a
-#define CP_DFY_CNTL__LFSR_RESET__SHIFT 0x1c
-#define CP_DFY_CNTL__MODE__SHIFT 0x1d
-#define CP_DFY_CNTL__ENABLE__SHIFT 0x1f
-#define CP_DFY_CNTL__POLICY_MASK 0x00000001L
-#define CP_DFY_CNTL__MTYPE_MASK 0x0000000CL
-#define CP_DFY_CNTL__TPI_SDP_SEL_MASK 0x04000000L
-#define CP_DFY_CNTL__LFSR_RESET_MASK 0x10000000L
-#define CP_DFY_CNTL__MODE_MASK 0x60000000L
-#define CP_DFY_CNTL__ENABLE_MASK 0x80000000L
-//CP_DFY_STAT
-#define CP_DFY_STAT__BURST_COUNT__SHIFT 0x0
-#define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x10
-#define CP_DFY_STAT__BUSY__SHIFT 0x1f
-#define CP_DFY_STAT__BURST_COUNT_MASK 0x0000FFFFL
-#define CP_DFY_STAT__TAGS_PENDING_MASK 0x07FF0000L
-#define CP_DFY_STAT__BUSY_MASK 0x80000000L
-//CP_DFY_ADDR_HI
-#define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x0
-#define CP_DFY_ADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL
-//CP_DFY_ADDR_LO
-#define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x5
-#define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xFFFFFFE0L
-//CP_DFY_DATA_0
-#define CP_DFY_DATA_0__DATA__SHIFT 0x0
-#define CP_DFY_DATA_0__DATA_MASK 0xFFFFFFFFL
-//CP_DFY_DATA_1
-#define CP_DFY_DATA_1__DATA__SHIFT 0x0
-#define CP_DFY_DATA_1__DATA_MASK 0xFFFFFFFFL
-//CP_DFY_DATA_2
-#define CP_DFY_DATA_2__DATA__SHIFT 0x0
-#define CP_DFY_DATA_2__DATA_MASK 0xFFFFFFFFL
-//CP_DFY_DATA_3
-#define CP_DFY_DATA_3__DATA__SHIFT 0x0
-#define CP_DFY_DATA_3__DATA_MASK 0xFFFFFFFFL
-//CP_DFY_DATA_4
-#define CP_DFY_DATA_4__DATA__SHIFT 0x0
-#define CP_DFY_DATA_4__DATA_MASK 0xFFFFFFFFL
-//CP_DFY_DATA_5
-#define CP_DFY_DATA_5__DATA__SHIFT 0x0
-#define CP_DFY_DATA_5__DATA_MASK 0xFFFFFFFFL
-//CP_DFY_DATA_6
-#define CP_DFY_DATA_6__DATA__SHIFT 0x0
-#define CP_DFY_DATA_6__DATA_MASK 0xFFFFFFFFL
-//CP_DFY_DATA_7
-#define CP_DFY_DATA_7__DATA__SHIFT 0x0
-#define CP_DFY_DATA_7__DATA_MASK 0xFFFFFFFFL
-//CP_DFY_DATA_8
-#define CP_DFY_DATA_8__DATA__SHIFT 0x0
-#define CP_DFY_DATA_8__DATA_MASK 0xFFFFFFFFL
-//CP_DFY_DATA_9
-#define CP_DFY_DATA_9__DATA__SHIFT 0x0
-#define CP_DFY_DATA_9__DATA_MASK 0xFFFFFFFFL
-//CP_DFY_DATA_10
-#define CP_DFY_DATA_10__DATA__SHIFT 0x0
-#define CP_DFY_DATA_10__DATA_MASK 0xFFFFFFFFL
-//CP_DFY_DATA_11
-#define CP_DFY_DATA_11__DATA__SHIFT 0x0
-#define CP_DFY_DATA_11__DATA_MASK 0xFFFFFFFFL
-//CP_DFY_DATA_12
-#define CP_DFY_DATA_12__DATA__SHIFT 0x0
-#define CP_DFY_DATA_12__DATA_MASK 0xFFFFFFFFL
-//CP_DFY_DATA_13
-#define CP_DFY_DATA_13__DATA__SHIFT 0x0
-#define CP_DFY_DATA_13__DATA_MASK 0xFFFFFFFFL
-//CP_DFY_DATA_14
-#define CP_DFY_DATA_14__DATA__SHIFT 0x0
-#define CP_DFY_DATA_14__DATA_MASK 0xFFFFFFFFL
-//CP_DFY_DATA_15
-#define CP_DFY_DATA_15__DATA__SHIFT 0x0
-#define CP_DFY_DATA_15__DATA_MASK 0xFFFFFFFFL
-//CP_DFY_CMD
-#define CP_DFY_CMD__OFFSET__SHIFT 0x0
-#define CP_DFY_CMD__SIZE__SHIFT 0x10
-#define CP_DFY_CMD__OFFSET_MASK 0x000001FFL
-#define CP_DFY_CMD__SIZE_MASK 0xFFFF0000L
-//CP_EOPQ_WAIT_TIME
-#define CP_EOPQ_WAIT_TIME__WAIT_TIME__SHIFT 0x0
-#define CP_EOPQ_WAIT_TIME__SCALE_COUNT__SHIFT 0xa
-#define CP_EOPQ_WAIT_TIME__WAIT_TIME_MASK 0x000003FFL
-#define CP_EOPQ_WAIT_TIME__SCALE_COUNT_MASK 0x0003FC00L
-//CP_CPC_MGCG_SYNC_CNTL
-#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0
-#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8
-#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0x000000FFL
-#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0x0000FF00L
-//CPC_INT_INFO
-#define CPC_INT_INFO__ADDR_HI__SHIFT 0x0
-#define CPC_INT_INFO__TYPE__SHIFT 0x10
-#define CPC_INT_INFO__VMID__SHIFT 0x14
-#define CPC_INT_INFO__QUEUE_ID__SHIFT 0x1c
-#define CPC_INT_INFO__ADDR_HI_MASK 0x0000FFFFL
-#define CPC_INT_INFO__TYPE_MASK 0x00010000L
-#define CPC_INT_INFO__VMID_MASK 0x00F00000L
-#define CPC_INT_INFO__QUEUE_ID_MASK 0x70000000L
-//CP_VIRT_STATUS
-#define CP_VIRT_STATUS__VIRT_STATUS__SHIFT 0x0
-#define CP_VIRT_STATUS__VIRT_STATUS_MASK 0xFFFFFFFFL
-//CPC_INT_ADDR
-#define CPC_INT_ADDR__ADDR__SHIFT 0x0
-#define CPC_INT_ADDR__ADDR_MASK 0xFFFFFFFFL
-//CPC_INT_PASID
-#define CPC_INT_PASID__PASID__SHIFT 0x0
-#define CPC_INT_PASID__PASID_MASK 0x0000FFFFL
-//CP_GFX_ERROR
-#define CP_GFX_ERROR__EDC_ERROR_ID__SHIFT 0x0
-#define CP_GFX_ERROR__SUA_ERROR__SHIFT 0x4
-#define CP_GFX_ERROR__RSVD1_ERROR__SHIFT 0x5
-#define CP_GFX_ERROR__RSVD2_ERROR__SHIFT 0x6
-#define CP_GFX_ERROR__SEM_UTCL1_ERROR__SHIFT 0x7
-#define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR__SHIFT 0x8
-#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR__SHIFT 0x9
-#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR__SHIFT 0xa
-#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR__SHIFT 0xb
-#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR__SHIFT 0xc
-#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR__SHIFT 0xd
-#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR__SHIFT 0xe
-#define CP_GFX_ERROR__APPEND_UTCL1_ERROR__SHIFT 0xf
-#define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR__SHIFT 0x10
-#define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR__SHIFT 0x11
-#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0x12
-#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x13
-#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR__SHIFT 0x14
-#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR__SHIFT 0x15
-#define CP_GFX_ERROR__CE_TC_UTCL1_ERROR__SHIFT 0x16
-#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR__SHIFT 0x17
-#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR__SHIFT 0x18
-#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR__SHIFT 0x19
-#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR__SHIFT 0x1a
-#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR__SHIFT 0x1b
-#define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR__SHIFT 0x1c
-#define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR__SHIFT 0x1d
-#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR__SHIFT 0x1e
-#define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR__SHIFT 0x1f
-#define CP_GFX_ERROR__EDC_ERROR_ID_MASK 0x0000000FL
-#define CP_GFX_ERROR__SUA_ERROR_MASK 0x00000010L
-#define CP_GFX_ERROR__RSVD1_ERROR_MASK 0x00000020L
-#define CP_GFX_ERROR__RSVD2_ERROR_MASK 0x00000040L
-#define CP_GFX_ERROR__SEM_UTCL1_ERROR_MASK 0x00000080L
-#define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR_MASK 0x00000100L
-#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR_MASK 0x00000200L
-#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR_MASK 0x00000400L
-#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR_MASK 0x00000800L
-#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR_MASK 0x00001000L
-#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR_MASK 0x00002000L
-#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR_MASK 0x00004000L
-#define CP_GFX_ERROR__APPEND_UTCL1_ERROR_MASK 0x00008000L
-#define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR_MASK 0x00010000L
-#define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR_MASK 0x00020000L
-#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00040000L
-#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00080000L
-#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR_MASK 0x00100000L
-#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR_MASK 0x00200000L
-#define CP_GFX_ERROR__CE_TC_UTCL1_ERROR_MASK 0x00400000L
-#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR_MASK 0x00800000L
-#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR_MASK 0x01000000L
-#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR_MASK 0x02000000L
-#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR_MASK 0x04000000L
-#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR_MASK 0x08000000L
-#define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR_MASK 0x10000000L
-#define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR_MASK 0x20000000L
-#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR_MASK 0x40000000L
-#define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR_MASK 0x80000000L
-//CPG_UTCL1_CNTL
-#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
-#define CPG_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17
-#define CPG_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
-#define CPG_UTCL1_CNTL__BYPASS__SHIFT 0x19
-#define CPG_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
-#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
-#define CPG_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
-#define CPG_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
-#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e
-#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
-#define CPG_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L
-#define CPG_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
-#define CPG_UTCL1_CNTL__BYPASS_MASK 0x02000000L
-#define CPG_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
-#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
-#define CPG_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
-#define CPG_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
-#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L
-//CPC_UTCL1_CNTL
-#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
-#define CPC_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
-#define CPC_UTCL1_CNTL__BYPASS__SHIFT 0x19
-#define CPC_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
-#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
-#define CPC_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
-#define CPC_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
-#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e
-#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
-#define CPC_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
-#define CPC_UTCL1_CNTL__BYPASS_MASK 0x02000000L
-#define CPC_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
-#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
-#define CPC_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
-#define CPC_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
-#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L
-//CPF_UTCL1_CNTL
-#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
-#define CPF_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17
-#define CPF_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
-#define CPF_UTCL1_CNTL__BYPASS__SHIFT 0x19
-#define CPF_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
-#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
-#define CPF_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
-#define CPF_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
-#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e
-#define CPF_UTCL1_CNTL__FORCE_NO_EXE__SHIFT 0x1f
-#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
-#define CPF_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L
-#define CPF_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
-#define CPF_UTCL1_CNTL__BYPASS_MASK 0x02000000L
-#define CPF_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
-#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
-#define CPF_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
-#define CPF_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
-#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L
-#define CPF_UTCL1_CNTL__FORCE_NO_EXE_MASK 0x80000000L
-//CP_AQL_SMM_STATUS
-#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM__SHIFT 0x0
-#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM_MASK 0xFFFFFFFFL
-//CP_RB0_BASE
-#define CP_RB0_BASE__RB_BASE__SHIFT 0x0
-#define CP_RB0_BASE__RB_BASE_MASK 0xFFFFFFFFL
-//CP_RB_BASE
-#define CP_RB_BASE__RB_BASE__SHIFT 0x0
-#define CP_RB_BASE__RB_BASE_MASK 0xFFFFFFFFL
-//CP_RB0_CNTL
-#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0
-#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8
-#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x11
-#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14
-#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
-#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18
-#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b
-#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
-#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x0000003FL
-#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x00003F00L
-#define CP_RB0_CNTL__BUF_SWAP_MASK 0x00060000L
-#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x00300000L
-#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L
-#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x01000000L
-#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x08000000L
-#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
-//CP_RB_CNTL
-#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0
-#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8
-#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14
-#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
-#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18
-#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b
-#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
-#define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003FL
-#define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003F00L
-#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x00300000L
-#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L
-#define CP_RB_CNTL__CACHE_POLICY_MASK 0x01000000L
-#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L
-#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
-//CP_RB_RPTR_WR
-#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0
-#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000FFFFFL
-//CP_RB0_RPTR_ADDR
-#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
-#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL
-//CP_RB_RPTR_ADDR
-#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
-#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL
-//CP_RB0_RPTR_ADDR_HI
-#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
-#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL
-//CP_RB_RPTR_ADDR_HI
-#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
-#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL
-//CP_RB0_BUFSZ_MASK
-#define CP_RB0_BUFSZ_MASK__DATA__SHIFT 0x0
-#define CP_RB0_BUFSZ_MASK__DATA_MASK 0x000FFFFFL
-//CP_RB_BUFSZ_MASK
-#define CP_RB_BUFSZ_MASK__DATA__SHIFT 0x0
-#define CP_RB_BUFSZ_MASK__DATA_MASK 0x000FFFFFL
-//CP_RB_WPTR_POLL_ADDR_LO
-#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2
-#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xFFFFFFFCL
-//CP_RB_WPTR_POLL_ADDR_HI
-#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0
-#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0x0000FFFFL
-//GC_PRIV_MODE
-//CP_INT_CNTL
-#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
-#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CP_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
-#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT 0x12
-#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
-#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
-#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT 0x15
-#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
-#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L
-#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
-#define CP_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
-#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
-#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK 0x00040000L
-#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
-#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
-#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK 0x00200000L
-#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
-#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
-#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
-#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
-#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
-#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
-#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
-#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
-//CP_INT_STATUS
-#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
-#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
-#define CP_INT_STATUS__GPF_INT_STAT__SHIFT 0x10
-#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
-#define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT 0x12
-#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13
-#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14
-#define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT 0x15
-#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16
-#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17
-#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18
-#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a
-#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
-#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d
-#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e
-#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f
-#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L
-#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
-#define CP_INT_STATUS__GPF_INT_STAT_MASK 0x00010000L
-#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
-#define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK 0x00040000L
-#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x00080000L
-#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
-#define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x00200000L
-#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x00400000L
-#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x00800000L
-#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
-#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x04000000L
-#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
-#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000L
-#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000L
-#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000L
-//CP_DEVICE_ID
-#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0
-#define CP_DEVICE_ID__DEVICE_ID_MASK 0x000000FFL
-//CP_ME0_PIPE_PRIORITY_CNTS
-#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
-#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
-#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
-#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
-#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL
-#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L
-#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L
-#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L
-//CP_RING_PRIORITY_CNTS
-#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
-#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
-#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
-#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
-#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL
-#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L
-#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L
-#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L
-//CP_ME0_PIPE0_PRIORITY
-#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L
-//CP_RING0_PRIORITY
-#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_RING0_PRIORITY__PRIORITY_MASK 0x00000003L
-//CP_ME0_PIPE1_PRIORITY
-#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L
-//CP_RING1_PRIORITY
-#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_RING1_PRIORITY__PRIORITY_MASK 0x00000003L
-//CP_ME0_PIPE2_PRIORITY
-#define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L
-//CP_RING2_PRIORITY
-#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_RING2_PRIORITY__PRIORITY_MASK 0x00000003L
-//CP_FATAL_ERROR
-#define CP_FATAL_ERROR__CPF_FATAL_ERROR__SHIFT 0x0
-#define CP_FATAL_ERROR__CPG_FATAL_ERROR__SHIFT 0x1
-#define CP_FATAL_ERROR__GFX_HALT_PROC__SHIFT 0x2
-#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR__SHIFT 0x3
-#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN__SHIFT 0x4
-#define CP_FATAL_ERROR__CPF_FATAL_ERROR_MASK 0x00000001L
-#define CP_FATAL_ERROR__CPG_FATAL_ERROR_MASK 0x00000002L
-#define CP_FATAL_ERROR__GFX_HALT_PROC_MASK 0x00000004L
-#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR_MASK 0x00000008L
-#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN_MASK 0x00000010L
-//CP_RB_VMID
-#define CP_RB_VMID__RB0_VMID__SHIFT 0x0
-#define CP_RB_VMID__RB1_VMID__SHIFT 0x8
-#define CP_RB_VMID__RB2_VMID__SHIFT 0x10
-#define CP_RB_VMID__RB0_VMID_MASK 0x0000000FL
-#define CP_RB_VMID__RB1_VMID_MASK 0x00000F00L
-#define CP_RB_VMID__RB2_VMID_MASK 0x000F0000L
-//CP_ME0_PIPE0_VMID
-#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0
-#define CP_ME0_PIPE0_VMID__VMID_MASK 0x0000000FL
-//CP_ME0_PIPE1_VMID
-#define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0
-#define CP_ME0_PIPE1_VMID__VMID_MASK 0x0000000FL
-//CP_RB0_WPTR
-#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0
-#define CP_RB0_WPTR__RB_WPTR_MASK 0xFFFFFFFFL
-//CP_RB_WPTR
-#define CP_RB_WPTR__RB_WPTR__SHIFT 0x0
-#define CP_RB_WPTR__RB_WPTR_MASK 0xFFFFFFFFL
-//CP_RB0_WPTR_HI
-#define CP_RB0_WPTR_HI__RB_WPTR__SHIFT 0x0
-#define CP_RB0_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL
-//CP_RB_WPTR_HI
-#define CP_RB_WPTR_HI__RB_WPTR__SHIFT 0x0
-#define CP_RB_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL
-//CP_RB1_WPTR
-#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0
-#define CP_RB1_WPTR__RB_WPTR_MASK 0xFFFFFFFFL
-//CP_RB1_WPTR_HI
-#define CP_RB1_WPTR_HI__RB_WPTR__SHIFT 0x0
-#define CP_RB1_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL
-//CP_RB2_WPTR
-#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0
-#define CP_RB2_WPTR__RB_WPTR_MASK 0x000FFFFFL
-//CP_RB_DOORBELL_CONTROL
-#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1
-#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
-#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
-#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
-#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L
-#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
-#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L
-#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L
-//CP_RB_DOORBELL_RANGE_LOWER
-#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2
-#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x0FFFFFFCL
-//CP_RB_DOORBELL_RANGE_UPPER
-#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2
-#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL
-//CP_MEC_DOORBELL_RANGE_LOWER
-#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2
-#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x0FFFFFFCL
-//CP_MEC_DOORBELL_RANGE_UPPER
-#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2
-#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL
-//CPG_UTCL1_ERROR
-#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0
-#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L
-//CPC_UTCL1_ERROR
-#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0
-#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L
-//CP_RB1_BASE
-#define CP_RB1_BASE__RB_BASE__SHIFT 0x0
-#define CP_RB1_BASE__RB_BASE_MASK 0xFFFFFFFFL
-//CP_RB1_CNTL
-#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0
-#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8
-#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14
-#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
-#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18
-#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b
-#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
-#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x0000003FL
-#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x00003F00L
-#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x00300000L
-#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L
-#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x01000000L
-#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x08000000L
-#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
-//CP_RB1_RPTR_ADDR
-#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
-#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL
-//CP_RB1_RPTR_ADDR_HI
-#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
-#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL
-//CP_RB2_BASE
-#define CP_RB2_BASE__RB_BASE__SHIFT 0x0
-#define CP_RB2_BASE__RB_BASE_MASK 0xFFFFFFFFL
-//CP_RB2_CNTL
-#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0
-#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8
-#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14
-#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
-#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18
-#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b
-#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
-#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x0000003FL
-#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x00003F00L
-#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x00300000L
-#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L
-#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x01000000L
-#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x08000000L
-#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
-//CP_RB2_RPTR_ADDR
-#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
-#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL
-//CP_RB2_RPTR_ADDR_HI
-#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
-#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL
-//CP_RB0_ACTIVE
-#define CP_RB0_ACTIVE__ACTIVE__SHIFT 0x0
-#define CP_RB0_ACTIVE__ACTIVE_MASK 0x00000001L
-//CP_RB_ACTIVE
-#define CP_RB_ACTIVE__ACTIVE__SHIFT 0x0
-#define CP_RB_ACTIVE__ACTIVE_MASK 0x00000001L
-//CP_INT_CNTL_RING0
-#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
-#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CP_INT_CNTL_RING0__GPF_INT_ENABLE__SHIFT 0x10
-#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT 0x12
-#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
-#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
-#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT 0x15
-#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
-#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L
-#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
-#define CP_INT_CNTL_RING0__GPF_INT_ENABLE_MASK 0x00010000L
-#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
-#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK 0x00040000L
-#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
-#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
-#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK 0x00200000L
-#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
-#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x00800000L
-#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
-#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
-#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
-#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000L
-#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000L
-#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000L
-//CP_INT_CNTL_RING1
-#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
-#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CP_INT_CNTL_RING1__GPF_INT_ENABLE__SHIFT 0x10
-#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT 0x12
-#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
-#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
-#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT 0x15
-#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
-#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L
-#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
-#define CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK 0x00010000L
-#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
-#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK 0x00040000L
-#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
-#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
-#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK 0x00200000L
-#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
-#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x00800000L
-#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
-#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
-#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
-#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000L
-#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000L
-#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000L
-//CP_INT_CNTL_RING2
-#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
-#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CP_INT_CNTL_RING2__GPF_INT_ENABLE__SHIFT 0x10
-#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT 0x12
-#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
-#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
-#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT 0x15
-#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
-#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L
-#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
-#define CP_INT_CNTL_RING2__GPF_INT_ENABLE_MASK 0x00010000L
-#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
-#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK 0x00040000L
-#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
-#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
-#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK 0x00200000L
-#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
-#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x00800000L
-#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
-#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
-#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
-#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000L
-#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000L
-#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000L
-//CP_INT_STATUS_RING0
-#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
-#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
-#define CP_INT_STATUS_RING0__GPF_INT_STAT__SHIFT 0x10
-#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
-#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT 0x12
-#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT 0x13
-#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14
-#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT 0x15
-#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16
-#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17
-#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18
-#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a
-#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
-#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d
-#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e
-#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f
-#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L
-#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
-#define CP_INT_STATUS_RING0__GPF_INT_STAT_MASK 0x00010000L
-#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
-#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK 0x00040000L
-#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK 0x00080000L
-#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
-#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK 0x00200000L
-#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x00400000L
-#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x00800000L
-#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
-#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x04000000L
-#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
-#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000L
-#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000L
-#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000L
-//CP_INT_STATUS_RING1
-#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
-#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
-#define CP_INT_STATUS_RING1__GPF_INT_STAT__SHIFT 0x10
-#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
-#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT 0x12
-#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13
-#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14
-#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT 0x15
-#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16
-#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17
-#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18
-#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a
-#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
-#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d
-#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e
-#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f
-#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L
-#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
-#define CP_INT_STATUS_RING1__GPF_INT_STAT_MASK 0x00010000L
-#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
-#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK 0x00040000L
-#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x00080000L
-#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
-#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK 0x00200000L
-#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x00400000L
-#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x00800000L
-#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
-#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x04000000L
-#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
-#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000L
-#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000L
-#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000L
-//CP_INT_STATUS_RING2
-#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
-#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
-#define CP_INT_STATUS_RING2__GPF_INT_STAT__SHIFT 0x10
-#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
-#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT 0x12
-#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13
-#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14
-#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT 0x15
-#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16
-#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17
-#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18
-#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a
-#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
-#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d
-#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e
-#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f
-#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L
-#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
-#define CP_INT_STATUS_RING2__GPF_INT_STAT_MASK 0x00010000L
-#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
-#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK 0x00040000L
-#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x00080000L
-#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
-#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK 0x00200000L
-#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x00400000L
-#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x00800000L
-#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
-#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x04000000L
-#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
-#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000L
-#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000L
-#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000L
-#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
-#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L
-#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
-#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L
-#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
-#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L
-//CP_PWR_CNTL
-#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT 0x0
-#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT 0x1
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT 0xb
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT 0x11
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT 0x12
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13
-#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x00000001L
-#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x00000002L
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK 0x00000100L
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK 0x00000200L
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x00000400L
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK 0x00000800L
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x00010000L
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK 0x00020000L
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x00040000L
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x00080000L
-//CP_MEM_SLP_CNTL
-#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0
-#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1
-#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
-#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT 0x7
-#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8
-#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10
-#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
-#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x00000001L
-#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x00000002L
-#define CP_MEM_SLP_CNTL__RESERVED_MASK 0x0000007CL
-#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L
-#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0x0000FF00L
-#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0x00FF0000L
-#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xFF000000L
-//CP_ECC_FIRSTOCCURRENCE
-#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0
-#define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT 0x4
-#define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT 0x8
-#define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa
-#define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT 0xc
-#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10
-#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x00000003L
-#define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK 0x000000F0L
-#define CP_ECC_FIRSTOCCURRENCE__ME_MASK 0x00000300L
-#define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK 0x00000C00L
-#define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK 0x00007000L
-#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0x000F0000L
-//CP_ECC_FIRSTOCCURRENCE_RING0
-#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT 0x0
-#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK 0xFFFFFFFFL
-//CP_ECC_FIRSTOCCURRENCE_RING1
-#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT 0x0
-#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK 0xFFFFFFFFL
-//CP_ECC_FIRSTOCCURRENCE_RING2
-#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT 0x0
-#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK 0xFFFFFFFFL
-//GB_EDC_MODE
-#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0xf
-#define GB_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10
-#define GB_EDC_MODE__GATE_FUE__SHIFT 0x11
-#define GB_EDC_MODE__DED_MODE__SHIFT 0x14
-#define GB_EDC_MODE__PROP_FED__SHIFT 0x1d
-#define GB_EDC_MODE__BYPASS__SHIFT 0x1f
-#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x00008000L
-#define GB_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L
-#define GB_EDC_MODE__GATE_FUE_MASK 0x00020000L
-#define GB_EDC_MODE__DED_MODE_MASK 0x00300000L
-#define GB_EDC_MODE__PROP_FED_MASK 0x20000000L
-#define GB_EDC_MODE__BYPASS_MASK 0x80000000L
-//CP_PQ_WPTR_POLL_CNTL
-#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0
-#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT__SHIFT 0x1d
-#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e
-#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f
-#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0x000000FFL
-#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT_MASK 0x20000000L
-#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000L
-#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000L
-//CP_PQ_WPTR_POLL_CNTL1
-#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0
-#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xFFFFFFFFL
-//CP_ME1_PIPE0_INT_CNTL
-#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
-#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
-#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
-#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
-#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
-#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
-#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
-#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
-#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
-#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
-#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
-#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
-#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
-#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
-#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
-#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
-#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
-//CP_ME1_PIPE1_INT_CNTL
-#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
-#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
-#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
-#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
-#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
-#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
-#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
-#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
-#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
-#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
-#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
-#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
-#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
-#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
-#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
-#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
-#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
-//CP_ME1_PIPE2_INT_CNTL
-#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
-#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
-#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
-#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
-#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
-#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
-#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
-#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
-#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
-#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
-#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
-#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
-#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
-#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
-#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
-#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
-#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
-//CP_ME1_PIPE3_INT_CNTL
-#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
-#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
-#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
-#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
-#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
-#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
-#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
-#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
-#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
-#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
-#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
-#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
-#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
-#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
-#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
-#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
-#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
-//CP_ME2_PIPE0_INT_CNTL
-#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
-#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
-#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
-#define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
-#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
-#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
-#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
-#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
-#define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
-#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
-#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
-#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
-#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
-#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
-#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
-#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
-#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
-//CP_ME2_PIPE1_INT_CNTL
-#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
-#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
-#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
-#define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
-#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
-#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
-#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
-#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
-#define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
-#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
-#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
-#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
-#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
-#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
-#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
-#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
-#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
-//CP_ME2_PIPE2_INT_CNTL
-#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
-#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
-#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
-#define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
-#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
-#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
-#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
-#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
-#define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
-#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
-#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
-#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
-#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
-#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
-#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
-#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
-#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
-//CP_ME2_PIPE3_INT_CNTL
-#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
-#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
-#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
-#define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
-#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
-#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
-#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
-#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
-#define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
-#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
-#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
-#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
-#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
-#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
-#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
-#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
-#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
-//CP_ME1_PIPE0_INT_STATUS
-#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
-#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
-#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
-#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
-#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
-#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
-#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
-#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
-#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
-#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
-#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
-#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
-#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
-#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
-#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
-#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
-#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
-#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
-#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
-#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
-#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
-#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
-#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
-#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
-#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
-#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
-//CP_ME1_PIPE1_INT_STATUS
-#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
-#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
-#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
-#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
-#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
-#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
-#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
-#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
-#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
-#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
-#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
-#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
-#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
-#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
-#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
-#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
-#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
-#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
-#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
-#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
-#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
-#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
-#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
-#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
-#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
-#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
-//CP_ME1_PIPE2_INT_STATUS
-#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
-#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
-#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
-#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
-#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
-#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
-#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
-#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
-#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
-#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
-#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
-#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
-#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
-#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
-#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
-#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
-#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
-#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
-#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
-#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
-#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
-#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
-#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
-#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
-#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
-#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
-//CP_ME1_PIPE3_INT_STATUS
-#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
-#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
-#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
-#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
-#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
-#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
-#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
-#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
-#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
-#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
-#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
-#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
-#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
-#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
-#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
-#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
-#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
-#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
-#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
-#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
-#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
-#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
-#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
-#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
-#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
-#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
-//CP_ME2_PIPE0_INT_STATUS
-#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
-#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
-#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
-#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
-#define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
-#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
-#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
-#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
-#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
-#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
-#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
-#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
-#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
-#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
-#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
-#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
-#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
-#define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
-#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
-#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
-#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
-#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
-#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
-#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
-#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
-#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
-//CP_ME2_PIPE1_INT_STATUS
-#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
-#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
-#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
-#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
-#define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
-#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
-#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
-#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
-#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
-#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
-#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
-#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
-#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
-#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
-#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
-#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
-#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
-#define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
-#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
-#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
-#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
-#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
-#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
-#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
-#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
-#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
-//CP_ME2_PIPE2_INT_STATUS
-#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
-#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
-#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
-#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
-#define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
-#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
-#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
-#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
-#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
-#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
-#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
-#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
-#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
-#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
-#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
-#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
-#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
-#define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
-#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
-#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
-#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
-#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
-#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
-#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
-#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
-#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
-//CP_ME2_PIPE3_INT_STATUS
-#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
-#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
-#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
-#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
-#define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
-#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
-#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
-#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
-#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
-#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
-#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
-#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
-#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
-#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
-#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
-#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
-#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
-#define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
-#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
-#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
-#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
-#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
-#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
-#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
-#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
-#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
-#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
-#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L
-#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
-#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L
-//CC_GC_EDC_CONFIG
-#define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1
-#define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x00000002L
-//CP_ME1_PIPE_PRIORITY_CNTS
-#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
-#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
-#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
-#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
-#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL
-#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L
-#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L
-#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L
-//CP_ME1_PIPE0_PRIORITY
-#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L
-//CP_ME1_PIPE1_PRIORITY
-#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L
-//CP_ME1_PIPE2_PRIORITY
-#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L
-//CP_ME1_PIPE3_PRIORITY
-#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L
-//CP_ME2_PIPE_PRIORITY_CNTS
-#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
-#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
-#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
-#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
-#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL
-#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L
-#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L
-#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L
-//CP_ME2_PIPE0_PRIORITY
-#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L
-//CP_ME2_PIPE1_PRIORITY
-#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L
-//CP_ME2_PIPE2_PRIORITY
-#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L
-//CP_ME2_PIPE3_PRIORITY
-#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L
-//CP_CE_PRGRM_CNTR_START
-#define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0
-#define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x000007FFL
-//CP_PFP_PRGRM_CNTR_START
-#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0
-#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0x00001FFFL
-//CP_ME_PRGRM_CNTR_START
-#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0
-#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0x00000FFFL
-//CP_MEC1_PRGRM_CNTR_START
-#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0
-#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0x0000FFFFL
-//CP_MEC2_PRGRM_CNTR_START
-#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0
-#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0x0000FFFFL
-//CP_CE_INTR_ROUTINE_START
-#define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0
-#define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x000007FFL
-//CP_PFP_INTR_ROUTINE_START
-#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0
-#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0x00001FFFL
-//CP_ME_INTR_ROUTINE_START
-#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0
-#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0x00000FFFL
-//CP_MEC1_INTR_ROUTINE_START
-#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0
-#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0x0000FFFFL
-//CP_MEC2_INTR_ROUTINE_START
-#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0
-#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0x0000FFFFL
-//CP_CONTEXT_CNTL
-#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x0
-#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4
-#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x10
-#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14
-#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x00000007L
-#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x00000070L
-#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x00070000L
-#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x00700000L
-//CP_MAX_CONTEXT
-#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0
-#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x00000007L
-//CP_IQ_WAIT_TIME1
-#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0
-#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8
-#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10
-#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18
-#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0x000000FFL
-#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0x0000FF00L
-#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0x00FF0000L
-#define CP_IQ_WAIT_TIME1__GWS_MASK 0xFF000000L
-//CP_IQ_WAIT_TIME2
-#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0
-#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8
-#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10
-#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18
-#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0x000000FFL
-#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0x0000FF00L
-#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0x00FF0000L
-#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xFF000000L
-//CP_RB0_BASE_HI
-#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0
-#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0x000000FFL
-//CP_RB1_BASE_HI
-#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0
-#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0x000000FFL
-//CP_VMID_RESET
-#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0
-#define CP_VMID_RESET__RESET_REQUEST_MASK 0x0000FFFFL
-//CPC_INT_CNTL
-#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
-#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
-#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
-#define CPC_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
-#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
-#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
-#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
-#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
-#define CPC_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
-#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
-#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
-#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
-#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
-#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
-#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
-#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
-#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
-//CPC_INT_STATUS
-#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
-#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
-#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
-#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
-#define CPC_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
-#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
-#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
-#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
-#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
-#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
-#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
-#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
-#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
-#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
-#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
-#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
-#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
-#define CPC_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
-#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
-#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
-#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
-#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
-#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
-#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
-#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
-#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
-//CP_VMID_PREEMPT
-#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0
-#define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT 0x10
-#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0x0000FFFFL
-#define CP_VMID_PREEMPT__VIRT_COMMAND_MASK 0x000F0000L
-//CPC_INT_CNTX_ID
-#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0
-#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL
-//CP_PQ_STATUS
-#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0
-#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1
-#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x00000001L
-#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x00000002L
-//CP_CPC_IC_BASE_LO
-#define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc
-#define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L
-//CP_CPC_IC_BASE_HI
-#define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0
-#define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL
-//CP_CPC_IC_BASE_CNTL
-#define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0
-#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18
-#define CP_CPC_IC_BASE_CNTL__VMID_MASK 0x0000000FL
-#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK 0x01000000L
-//CP_CPC_IC_OP_CNTL
-#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0
-#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4
-#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5
-#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L
-#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L
-#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L
-//CP_MEC1_F32_INT_DIS
-#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0
-#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1
-#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2
-#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3
-#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4
-#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5
-#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6
-#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7
-#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8
-#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9
-#define CP_MEC1_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa
-#define CP_MEC1_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb
-#define CP_MEC1_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc
-#define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT 0xd
-#define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe
-#define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT 0xf
-#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x00000001L
-#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L
-#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L
-#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x00000008L
-#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x00000010L
-#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x00000020L
-#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L
-#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L
-#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x00000100L
-#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L
-#define CP_MEC1_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L
-#define CP_MEC1_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L
-#define CP_MEC1_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L
-#define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK 0x00002000L
-#define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L
-#define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK 0x00008000L
-//CP_MEC2_F32_INT_DIS
-#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0
-#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1
-#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2
-#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3
-#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4
-#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5
-#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6
-#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7
-#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8
-#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9
-#define CP_MEC2_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa
-#define CP_MEC2_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb
-#define CP_MEC2_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc
-#define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT 0xd
-#define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe
-#define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT 0xf
-#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x00000001L
-#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L
-#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L
-#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x00000008L
-#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x00000010L
-#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x00000020L
-#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L
-#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L
-#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x00000100L
-#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L
-#define CP_MEC2_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L
-#define CP_MEC2_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L
-#define CP_MEC2_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L
-#define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK 0x00002000L
-#define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L
-#define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK 0x00008000L
-//CP_VMID_STATUS
-#define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT 0x0
-#define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10
-#define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0x0000FFFFL
-#define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xFFFF0000L
-
-
-// addressBlock: gc_cppdec2
-//CP_RB_DOORBELL_CONTROL_SCH_0
-#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET__SHIFT 0x2
-#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN__SHIFT 0x1e
-#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT__SHIFT 0x1f
-#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
-#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN_MASK 0x40000000L
-#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT_MASK 0x80000000L
-//CP_RB_DOORBELL_CONTROL_SCH_1
-#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET__SHIFT 0x2
-#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN__SHIFT 0x1e
-#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT__SHIFT 0x1f
-#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
-#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN_MASK 0x40000000L
-#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT_MASK 0x80000000L
-//CP_RB_DOORBELL_CONTROL_SCH_2
-#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET__SHIFT 0x2
-#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN__SHIFT 0x1e
-#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT__SHIFT 0x1f
-#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
-#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN_MASK 0x40000000L
-#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT_MASK 0x80000000L
-//CP_RB_DOORBELL_CONTROL_SCH_3
-#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET__SHIFT 0x2
-#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN__SHIFT 0x1e
-#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT__SHIFT 0x1f
-#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
-#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN_MASK 0x40000000L
-#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT_MASK 0x80000000L
-//CP_RB_DOORBELL_CONTROL_SCH_4
-#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET__SHIFT 0x2
-#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN__SHIFT 0x1e
-#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT__SHIFT 0x1f
-#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
-#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN_MASK 0x40000000L
-#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT_MASK 0x80000000L
-//CP_RB_DOORBELL_CONTROL_SCH_5
-#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET__SHIFT 0x2
-#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN__SHIFT 0x1e
-#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT__SHIFT 0x1f
-#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
-#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN_MASK 0x40000000L
-#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT_MASK 0x80000000L
-//CP_RB_DOORBELL_CONTROL_SCH_6
-#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET__SHIFT 0x2
-#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN__SHIFT 0x1e
-#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT__SHIFT 0x1f
-#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
-#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN_MASK 0x40000000L
-#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT_MASK 0x80000000L
-//CP_RB_DOORBELL_CONTROL_SCH_7
-#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET__SHIFT 0x2
-#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN__SHIFT 0x1e
-#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT__SHIFT 0x1f
-#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
-#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN_MASK 0x40000000L
-#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT_MASK 0x80000000L
-//CP_RB_DOORBELL_CLEAR
-#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE__SHIFT 0x0
-#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR__SHIFT 0x8
-#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR__SHIFT 0x9
-#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR__SHIFT 0xa
-#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR__SHIFT 0xb
-#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR__SHIFT 0xc
-#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR__SHIFT 0xd
-#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE_MASK 0x00000007L
-#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR_MASK 0x00000100L
-#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR_MASK 0x00000200L
-#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR_MASK 0x00000400L
-#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR_MASK 0x00000800L
-#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR_MASK 0x00001000L
-#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR_MASK 0x00002000L
-//CP_GFX_MQD_CONTROL
-#define CP_GFX_MQD_CONTROL__VMID__SHIFT 0x0
-#define CP_GFX_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17
-#define CP_GFX_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18
-#define CP_GFX_MQD_CONTROL__VMID_MASK 0x0000000FL
-#define CP_GFX_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L
-#define CP_GFX_MQD_CONTROL__CACHE_POLICY_MASK 0x01000000L
-//CP_GFX_MQD_BASE_ADDR
-#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2
-#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL
-//CP_GFX_MQD_BASE_ADDR_HI
-#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
-#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL
-//CP_RB_STATUS
-#define CP_RB_STATUS__DOORBELL_UPDATED__SHIFT 0x0
-#define CP_RB_STATUS__DOORBELL_ENABLE__SHIFT 0x1
-#define CP_RB_STATUS__DOORBELL_UPDATED_MASK 0x00000001L
-#define CP_RB_STATUS__DOORBELL_ENABLE_MASK 0x00000002L
-//CPG_UTCL1_STATUS
-#define CPG_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
-#define CPG_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
-#define CPG_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
-#define CPG_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
-#define CPG_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
-#define CPG_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
-#define CPG_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
-#define CPG_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
-#define CPG_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
-#define CPG_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
-#define CPG_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
-#define CPG_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
-//CPC_UTCL1_STATUS
-#define CPC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
-#define CPC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
-#define CPC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
-#define CPC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
-#define CPC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
-#define CPC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
-#define CPC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
-#define CPC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
-#define CPC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
-#define CPC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
-#define CPC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
-#define CPC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
-//CPF_UTCL1_STATUS
-#define CPF_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
-#define CPF_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
-#define CPF_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
-#define CPF_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
-#define CPF_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
-#define CPF_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
-#define CPF_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
-#define CPF_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
-#define CPF_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
-#define CPF_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
-#define CPF_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
-#define CPF_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
-//CP_SD_CNTL
-#define CP_SD_CNTL__CPF_EN__SHIFT 0x0
-#define CP_SD_CNTL__CPG_EN__SHIFT 0x1
-#define CP_SD_CNTL__CPC_EN__SHIFT 0x2
-#define CP_SD_CNTL__RLC_EN__SHIFT 0x3
-#define CP_SD_CNTL__SPI_EN__SHIFT 0x4
-#define CP_SD_CNTL__WD_EN__SHIFT 0x5
-#define CP_SD_CNTL__IA_EN__SHIFT 0x6
-#define CP_SD_CNTL__PA_EN__SHIFT 0x7
-#define CP_SD_CNTL__RMI_EN__SHIFT 0x8
-#define CP_SD_CNTL__EA_EN__SHIFT 0x9
-#define CP_SD_CNTL__CPF_EN_MASK 0x00000001L
-#define CP_SD_CNTL__CPG_EN_MASK 0x00000002L
-#define CP_SD_CNTL__CPC_EN_MASK 0x00000004L
-#define CP_SD_CNTL__RLC_EN_MASK 0x00000008L
-#define CP_SD_CNTL__SPI_EN_MASK 0x00000010L
-#define CP_SD_CNTL__WD_EN_MASK 0x00000020L
-#define CP_SD_CNTL__IA_EN_MASK 0x00000040L
-#define CP_SD_CNTL__PA_EN_MASK 0x00000080L
-#define CP_SD_CNTL__RMI_EN_MASK 0x00000100L
-#define CP_SD_CNTL__EA_EN_MASK 0x00000200L
-//CP_SOFT_RESET_CNTL
-#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET__SHIFT 0x0
-#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET__SHIFT 0x1
-#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET__SHIFT 0x2
-#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET__SHIFT 0x3
-#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET__SHIFT 0x4
-#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET__SHIFT 0x5
-#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET__SHIFT 0x6
-#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET_MASK 0x00000001L
-#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET_MASK 0x00000002L
-#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET_MASK 0x00000004L
-#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET_MASK 0x00000008L
-#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET_MASK 0x00000010L
-#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET_MASK 0x00000020L
-#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET_MASK 0x00000040L
-//CP_CPC_GFX_CNTL
-#define CP_CPC_GFX_CNTL__QUEUEID__SHIFT 0x0
-#define CP_CPC_GFX_CNTL__PIPEID__SHIFT 0x3
-#define CP_CPC_GFX_CNTL__MEID__SHIFT 0x5
-#define CP_CPC_GFX_CNTL__VALID__SHIFT 0x7
-#define CP_CPC_GFX_CNTL__QUEUEID_MASK 0x00000007L
-#define CP_CPC_GFX_CNTL__PIPEID_MASK 0x00000018L
-#define CP_CPC_GFX_CNTL__MEID_MASK 0x00000060L
-#define CP_CPC_GFX_CNTL__VALID_MASK 0x00000080L
-
-
-// addressBlock: gc_spipdec
-//SPI_ARB_PRIORITY
-#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0
-#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3
-#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6
-#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9
-#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc
-#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe
-#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10
-#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12
-#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x00000007L
-#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x00000038L
-#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x000001C0L
-#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0x00000E00L
-#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x00003000L
-#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0x0000C000L
-#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x00030000L
-#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0x000C0000L
-//SPI_ARB_CYCLES_0
-#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0
-#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10
-#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0x0000FFFFL
-#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xFFFF0000L
-//SPI_ARB_CYCLES_1
-#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0
-#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10
-#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0x0000FFFFL
-#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xFFFF0000L
-//SPI_WCL_PIPE_PERCENT_GFX
-#define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0
-#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE__SHIFT 0x7
-#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT 0xc
-#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE__SHIFT 0x11
-#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT 0x16
-#define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x0000007FL
-#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE_MASK 0x00000F80L
-#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK 0x0001F000L
-#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE_MASK 0x003E0000L
-#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK 0x07C00000L
-//SPI_WCL_PIPE_PERCENT_HP3D
-#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0
-#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT 0xc
-#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT 0x16
-#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x0000007FL
-#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK 0x0001F000L
-#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK 0x07C00000L
-//SPI_WCL_PIPE_PERCENT_CS0
-#define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0
-#define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x7FL
-//SPI_WCL_PIPE_PERCENT_CS1
-#define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0
-#define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x7FL
-//SPI_WCL_PIPE_PERCENT_CS2
-#define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0
-#define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x7FL
-//SPI_WCL_PIPE_PERCENT_CS3
-#define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0
-#define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x7FL
-//SPI_WCL_PIPE_PERCENT_CS4
-#define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0
-#define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x7FL
-//SPI_WCL_PIPE_PERCENT_CS5
-#define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0
-#define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x7FL
-//SPI_WCL_PIPE_PERCENT_CS6
-#define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0
-#define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x7FL
-//SPI_WCL_PIPE_PERCENT_CS7
-#define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0
-#define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x7FL
-//SPI_COMPUTE_QUEUE_RESET
-#define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0
-#define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x01L
-//SPI_RESOURCE_RESERVE_CU_0
-#define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0x0000000FL
-#define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0x000000F0L
-#define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0x00000F00L
-#define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x00007000L
-#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x00078000L
-//SPI_RESOURCE_RESERVE_CU_1
-#define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0x0000000FL
-#define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0x000000F0L
-#define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0x00000F00L
-#define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x00007000L
-#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x00078000L
-//SPI_RESOURCE_RESERVE_CU_2
-#define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0x0000000FL
-#define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0x000000F0L
-#define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0x00000F00L
-#define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x00007000L
-#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x00078000L
-//SPI_RESOURCE_RESERVE_CU_3
-#define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0x0000000FL
-#define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0x000000F0L
-#define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0x00000F00L
-#define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x00007000L
-#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x00078000L
-//SPI_RESOURCE_RESERVE_CU_4
-#define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0x0000000FL
-#define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0x000000F0L
-#define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0x00000F00L
-#define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x00007000L
-#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x00078000L
-//SPI_RESOURCE_RESERVE_CU_5
-#define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0x0000000FL
-#define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0x000000F0L
-#define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0x00000F00L
-#define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x00007000L
-#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x00078000L
-//SPI_RESOURCE_RESERVE_CU_6
-#define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0x0000000FL
-#define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0x000000F0L
-#define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0x00000F00L
-#define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x00007000L
-#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x00078000L
-//SPI_RESOURCE_RESERVE_CU_7
-#define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0x0000000FL
-#define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0x000000F0L
-#define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0x00000F00L
-#define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x00007000L
-#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x00078000L
-//SPI_RESOURCE_RESERVE_CU_8
-#define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0x0000000FL
-#define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0x000000F0L
-#define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0x00000F00L
-#define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x00007000L
-#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x00078000L
-//SPI_RESOURCE_RESERVE_CU_9
-#define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0x0000000FL
-#define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0x000000F0L
-#define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0x00000F00L
-#define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x00007000L
-#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x00078000L
-//SPI_RESOURCE_RESERVE_EN_CU_0
-#define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x00000001L
-#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0x0000FFFEL
-#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0x00FF0000L
-#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK 0x01000000L
-//SPI_RESOURCE_RESERVE_EN_CU_1
-#define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x00000001L
-#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0x0000FFFEL
-#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0x00FF0000L
-#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK 0x01000000L
-//SPI_RESOURCE_RESERVE_EN_CU_2
-#define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x00000001L
-#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0x0000FFFEL
-#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0x00FF0000L
-#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK 0x01000000L
-//SPI_RESOURCE_RESERVE_EN_CU_3
-#define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x00000001L
-#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0x0000FFFEL
-#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0x00FF0000L
-#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK 0x01000000L
-//SPI_RESOURCE_RESERVE_EN_CU_4
-#define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x00000001L
-#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0x0000FFFEL
-#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0x00FF0000L
-#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK 0x01000000L
-//SPI_RESOURCE_RESERVE_EN_CU_5
-#define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x00000001L
-#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0x0000FFFEL
-#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0x00FF0000L
-#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK 0x01000000L
-//SPI_RESOURCE_RESERVE_EN_CU_6
-#define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x00000001L
-#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0x0000FFFEL
-#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0x00FF0000L
-#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK 0x01000000L
-//SPI_RESOURCE_RESERVE_EN_CU_7
-#define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x00000001L
-#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0x0000FFFEL
-#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0x00FF0000L
-#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK 0x01000000L
-//SPI_RESOURCE_RESERVE_EN_CU_8
-#define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x00000001L
-#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0x0000FFFEL
-#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0x00FF0000L
-#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK 0x01000000L
-//SPI_RESOURCE_RESERVE_EN_CU_9
-#define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x00000001L
-#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0x0000FFFEL
-#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0x00FF0000L
-#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK 0x01000000L
-//SPI_RESOURCE_RESERVE_CU_10
-#define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0x0000000FL
-#define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0x000000F0L
-#define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0x00000F00L
-#define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x00007000L
-#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x00078000L
-//SPI_RESOURCE_RESERVE_CU_11
-#define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0x0000000FL
-#define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0x000000F0L
-#define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0x00000F00L
-#define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x00007000L
-#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x00078000L
-//SPI_RESOURCE_RESERVE_EN_CU_10
-#define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x00000001L
-#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0x0000FFFEL
-#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0x00FF0000L
-#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK 0x01000000L
-//SPI_RESOURCE_RESERVE_EN_CU_11
-#define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x00000001L
-#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0x0000FFFEL
-#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0x00FF0000L
-#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK 0x01000000L
-//SPI_RESOURCE_RESERVE_CU_12
-#define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK 0x0000000FL
-#define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK 0x000000F0L
-#define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK 0x00000F00L
-#define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK 0x00007000L
-#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK 0x00078000L
-//SPI_RESOURCE_RESERVE_CU_13
-#define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK 0x0000000FL
-#define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK 0x000000F0L
-#define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK 0x00000F00L
-#define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK 0x00007000L
-#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK 0x00078000L
-//SPI_RESOURCE_RESERVE_CU_14
-#define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK 0x0000000FL
-#define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK 0x000000F0L
-#define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK 0x00000F00L
-#define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK 0x00007000L
-#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK 0x00078000L
-//SPI_RESOURCE_RESERVE_CU_15
-#define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK 0x0000000FL
-#define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK 0x000000F0L
-#define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK 0x00000F00L
-#define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK 0x00007000L
-#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK 0x00078000L
-//SPI_RESOURCE_RESERVE_EN_CU_12
-#define SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK 0x00000001L
-#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK 0x0000FFFEL
-#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK 0x00FF0000L
-#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY_MASK 0x01000000L
-//SPI_RESOURCE_RESERVE_EN_CU_13
-#define SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK 0x00000001L
-#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK 0x0000FFFEL
-#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK 0x00FF0000L
-#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY_MASK 0x01000000L
-//SPI_RESOURCE_RESERVE_EN_CU_14
-#define SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK 0x00000001L
-#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK 0x0000FFFEL
-#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK 0x00FF0000L
-#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY_MASK 0x01000000L
-//SPI_RESOURCE_RESERVE_EN_CU_15
-#define SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK 0x00000001L
-#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK 0x0000FFFEL
-#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK 0x00FF0000L
-#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY_MASK 0x01000000L
-//SPI_COMPUTE_WF_CTX_SAVE
-#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT 0x0
-#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT 0x1
-#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT 0x2
-#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT 0x1e
-#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT 0x1f
-#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK 0x00000001L
-#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK 0x00000002L
-#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK 0x00000004L
-#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK 0x40000000L
-#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK 0x80000000L
-//SPI_ARB_CNTL_0
-#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT__SHIFT 0x0
-#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT__SHIFT 0x4
-#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT__SHIFT 0x8
-#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT_MASK 0x0000000FL
-#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT_MASK 0x000000F0L
-#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT_MASK 0x00000F00L
-
-
-// addressBlock: gc_cpphqddec
-//CP_HQD_GFX_CONTROL
-#define CP_HQD_GFX_CONTROL__MESSAGE__SHIFT 0x0
-#define CP_HQD_GFX_CONTROL__MISC__SHIFT 0x4
-#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT 0xf
-#define CP_HQD_GFX_CONTROL__MESSAGE_MASK 0x0000000FL
-#define CP_HQD_GFX_CONTROL__MISC_MASK 0x00007FF0L
-#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN_MASK 0x00008000L
-//CP_HQD_GFX_STATUS
-#define CP_HQD_GFX_STATUS__STATUS__SHIFT 0x0
-#define CP_HQD_GFX_STATUS__STATUS_MASK 0x0000FFFFL
-//CP_HPD_ROQ_OFFSETS
-#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0
-#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8
-#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10
-#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x00000007L
-#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x00003F00L
-#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x003F0000L
-//CP_HPD_STATUS0
-#define CP_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0
-#define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5
-#define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8
-#define CP_HPD_STATUS0__FETCHING_MQD__SHIFT 0x10
-#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB__SHIFT 0x11
-#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ__SHIFT 0x12
-#define CP_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT 0x14
-#define CP_HPD_STATUS0__FORCE_QUEUE__SHIFT 0x1f
-#define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x0000001FL
-#define CP_HPD_STATUS0__MAPPED_QUEUE_MASK 0x000000E0L
-#define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0x0000FF00L
-#define CP_HPD_STATUS0__FETCHING_MQD_MASK 0x00010000L
-#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB_MASK 0x00020000L
-#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ_MASK 0x00040000L
-#define CP_HPD_STATUS0__FORCE_QUEUE_STATE_MASK 0x01F00000L
-#define CP_HPD_STATUS0__FORCE_QUEUE_MASK 0x80000000L
-//CP_HPD_UTCL1_CNTL
-#define CP_HPD_UTCL1_CNTL__SELECT__SHIFT 0x0
-#define CP_HPD_UTCL1_CNTL__SELECT_MASK 0x0000000FL
-//CP_HPD_UTCL1_ERROR
-#define CP_HPD_UTCL1_ERROR__ADDR_HI__SHIFT 0x0
-#define CP_HPD_UTCL1_ERROR__TYPE__SHIFT 0x10
-#define CP_HPD_UTCL1_ERROR__VMID__SHIFT 0x14
-#define CP_HPD_UTCL1_ERROR__ADDR_HI_MASK 0x0000FFFFL
-#define CP_HPD_UTCL1_ERROR__TYPE_MASK 0x00010000L
-#define CP_HPD_UTCL1_ERROR__VMID_MASK 0x00F00000L
-//CP_HPD_UTCL1_ERROR_ADDR
-#define CP_HPD_UTCL1_ERROR_ADDR__ADDR__SHIFT 0xc
-#define CP_HPD_UTCL1_ERROR_ADDR__ADDR_MASK 0xFFFFF000L
-//CP_MQD_BASE_ADDR
-#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2
-#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL
-//CP_MQD_BASE_ADDR_HI
-#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
-#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL
-//CP_HQD_ACTIVE
-#define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0
-#define CP_HQD_ACTIVE__BUSY_GATE__SHIFT 0x1
-#define CP_HQD_ACTIVE__ACTIVE_MASK 0x00000001L
-#define CP_HQD_ACTIVE__BUSY_GATE_MASK 0x00000002L
-//CP_HQD_VMID
-#define CP_HQD_VMID__VMID__SHIFT 0x0
-#define CP_HQD_VMID__IB_VMID__SHIFT 0x8
-#define CP_HQD_VMID__VQID__SHIFT 0x10
-#define CP_HQD_VMID__VMID_MASK 0x0000000FL
-#define CP_HQD_VMID__IB_VMID_MASK 0x00000F00L
-#define CP_HQD_VMID__VQID_MASK 0x03FF0000L
-//CP_HQD_PERSISTENT_STATE
-#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0
-#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8
-#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN__SHIFT 0x15
-#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT 0x16
-#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN__SHIFT 0x17
-#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN__SHIFT 0x18
-#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN__SHIFT 0x19
-#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN__SHIFT 0x1a
-#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN__SHIFT 0x1b
-#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT 0x1c
-#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x1d
-#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT 0x1e
-#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f
-#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x00000001L
-#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x0003FF00L
-#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN_MASK 0x00200000L
-#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN_MASK 0x00400000L
-#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN_MASK 0x00800000L
-#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN_MASK 0x01000000L
-#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN_MASK 0x02000000L
-#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN_MASK 0x04000000L
-#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN_MASK 0x08000000L
-#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK 0x10000000L
-#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK 0x20000000L
-#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK 0x40000000L
-#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000L
-//CP_HQD_PIPE_PRIORITY
-#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0
-#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x00000003L
-//CP_HQD_QUEUE_PRIORITY
-#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0
-#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0x0000000FL
-//CP_HQD_QUANTUM
-#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0
-#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4
-#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8
-#define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f
-#define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x00000001L
-#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x00000010L
-#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x00003F00L
-#define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000L
-//CP_HQD_PQ_BASE
-#define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0
-#define CP_HQD_PQ_BASE__ADDR_MASK 0xFFFFFFFFL
-//CP_HQD_PQ_BASE_HI
-#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0
-#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0x000000FFL
-//CP_HQD_PQ_RPTR
-#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0
-#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xFFFFFFFFL
-//CP_HQD_PQ_RPTR_REPORT_ADDR
-#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2
-#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xFFFFFFFCL
-//CP_HQD_PQ_RPTR_REPORT_ADDR_HI
-#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0
-#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0x0000FFFFL
-//CP_HQD_PQ_WPTR_POLL_ADDR
-#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x3
-#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xFFFFFFF8L
-//CP_HQD_PQ_WPTR_POLL_ADDR_HI
-#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0
-#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0x0000FFFFL
-//CP_HQD_PQ_DOORBELL_CONTROL
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK 0x00000001L
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000L
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000L
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L
-//CP_HQD_PQ_CONTROL
-#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0
-#define CP_HQD_PQ_CONTROL__WPTR_CARRY__SHIFT 0x6
-#define CP_HQD_PQ_CONTROL__RPTR_CARRY__SHIFT 0x7
-#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8
-#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT 0xe
-#define CP_HQD_PQ_CONTROL__PQ_EMPTY__SHIFT 0xf
-#define CP_HQD_PQ_CONTROL__WPP_CLAMP_EN__SHIFT 0x10
-#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x11
-#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14
-#define CP_HQD_PQ_CONTROL__EXE_DISABLE__SHIFT 0x17
-#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18
-#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x19
-#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b
-#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c
-#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d
-#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e
-#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f
-#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x0000003FL
-#define CP_HQD_PQ_CONTROL__WPTR_CARRY_MASK 0x00000040L
-#define CP_HQD_PQ_CONTROL__RPTR_CARRY_MASK 0x00000080L
-#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x00003F00L
-#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN_MASK 0x00004000L
-#define CP_HQD_PQ_CONTROL__PQ_EMPTY_MASK 0x00008000L
-#define CP_HQD_PQ_CONTROL__WPP_CLAMP_EN_MASK 0x00010000L
-#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x00060000L
-#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x00300000L
-#define CP_HQD_PQ_CONTROL__EXE_DISABLE_MASK 0x00800000L
-#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x01000000L
-#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x06000000L
-#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x08000000L
-#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000L
-#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK 0x20000000L
-#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000L
-#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000L
-//CP_HQD_IB_BASE_ADDR
-#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2
-#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xFFFFFFFCL
-//CP_HQD_IB_BASE_ADDR_HI
-#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0
-#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0x0000FFFFL
-//CP_HQD_IB_RPTR
-#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0
-#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0x000FFFFFL
-//CP_HQD_IB_CONTROL
-#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0
-#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14
-#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT 0x17
-#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18
-#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f
-#define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0x000FFFFFL
-#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x00300000L
-#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE_MASK 0x00800000L
-#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x01000000L
-#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000L
-//CP_HQD_IQ_TIMER
-#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0
-#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8
-#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb
-#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc
-#define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe
-#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10
-#define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16
-#define CP_HQD_IQ_TIMER__EXE_DISABLE__SHIFT 0x17
-#define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18
-#define CP_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT 0x19
-#define CP_HQD_IQ_TIMER__REARM_TIMER__SHIFT 0x1c
-#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d
-#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e
-#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f
-#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0x000000FFL
-#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x00000700L
-#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x00000800L
-#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x00003000L
-#define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0x0000C000L
-#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x003F0000L
-#define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x00400000L
-#define CP_HQD_IQ_TIMER__EXE_DISABLE_MASK 0x00800000L
-#define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x01000000L
-#define CP_HQD_IQ_TIMER__QUEUE_TYPE_MASK 0x02000000L
-#define CP_HQD_IQ_TIMER__REARM_TIMER_MASK 0x10000000L
-#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000L
-#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000L
-#define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000L
-//CP_HQD_IQ_RPTR
-#define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0
-#define CP_HQD_IQ_RPTR__OFFSET_MASK 0x0000003FL
-//CP_HQD_DEQUEUE_REQUEST
-#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0
-#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4
-#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8
-#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9
-#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa
-#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x00000007L
-#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x00000010L
-#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x00000100L
-#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x00000200L
-#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x00000400L
-//CP_HQD_DMA_OFFLOAD
-#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0
-#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L
-//CP_HQD_OFFLOAD
-#define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0
-#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1
-#define CP_HQD_OFFLOAD__AQL_OFFLOAD__SHIFT 0x2
-#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN__SHIFT 0x3
-#define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4
-#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5
-#define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L
-#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x00000002L
-#define CP_HQD_OFFLOAD__AQL_OFFLOAD_MASK 0x00000004L
-#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN_MASK 0x00000008L
-#define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK 0x00000010L
-#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x00000020L
-//CP_HQD_SEMA_CMD
-#define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0
-#define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1
-#define CP_HQD_SEMA_CMD__RETRY_MASK 0x00000001L
-#define CP_HQD_SEMA_CMD__RESULT_MASK 0x00000006L
-//CP_HQD_MSG_TYPE
-#define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0
-#define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT 0x4
-#define CP_HQD_MSG_TYPE__ACTION_MASK 0x00000007L
-#define CP_HQD_MSG_TYPE__SAVE_STATE_MASK 0x00000070L
-//CP_HQD_ATOMIC0_PREOP_LO
-#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0
-#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL
-//CP_HQD_ATOMIC0_PREOP_HI
-#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0
-#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL
-//CP_HQD_ATOMIC1_PREOP_LO
-#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0
-#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL
-//CP_HQD_ATOMIC1_PREOP_HI
-#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0
-#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL
-//CP_HQD_HQ_SCHEDULER0
-#define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT 0x0
-#define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK 0xFFFFFFFFL
-//CP_HQD_HQ_STATUS0
-#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0
-#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT 0x2
-#define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT 0x4
-#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT 0x7
-#define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x8
-#define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT 0x9
-#define CP_HQD_HQ_STATUS0__RSVR_29_10__SHIFT 0xa
-#define CP_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT 0x1e
-#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN__SHIFT 0x1f
-#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x00000003L
-#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK 0x0000000CL
-#define CP_HQD_HQ_STATUS0__RSV_6_4_MASK 0x00000070L
-#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK 0x00000080L
-#define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK 0x00000100L
-#define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK 0x00000200L
-#define CP_HQD_HQ_STATUS0__RSVR_29_10_MASK 0x3FFFFC00L
-#define CP_HQD_HQ_STATUS0__QUEUE_IDLE_MASK 0x40000000L
-#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN_MASK 0x80000000L
-//CP_HQD_HQ_CONTROL0
-#define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT 0x0
-#define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xFFFFFFFFL
-//CP_HQD_HQ_SCHEDULER1
-#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0
-#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xFFFFFFFFL
-//CP_MQD_CONTROL
-#define CP_MQD_CONTROL__VMID__SHIFT 0x0
-#define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8
-#define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc
-#define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd
-#define CP_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17
-#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18
-#define CP_MQD_CONTROL__VMID_MASK 0x0000000FL
-#define CP_MQD_CONTROL__PRIV_STATE_MASK 0x00000100L
-#define CP_MQD_CONTROL__PROCESSING_MQD_MASK 0x00001000L
-#define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x00002000L
-#define CP_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L
-#define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x01000000L
-//CP_HQD_HQ_STATUS1
-#define CP_HQD_HQ_STATUS1__STATUS__SHIFT 0x0
-#define CP_HQD_HQ_STATUS1__STATUS_MASK 0xFFFFFFFFL
-//CP_HQD_HQ_CONTROL1
-#define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT 0x0
-#define CP_HQD_HQ_CONTROL1__CONTROL_MASK 0xFFFFFFFFL
-//CP_HQD_EOP_BASE_ADDR
-#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0
-#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
-//CP_HQD_EOP_BASE_ADDR_HI
-#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
-#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x000000FFL
-//CP_HQD_EOP_CONTROL
-#define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0
-#define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8
-#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc
-#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd
-#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe
-#define CP_HQD_EOP_CONTROL__HALT_FETCHER__SHIFT 0x15
-#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN__SHIFT 0x16
-#define CP_HQD_EOP_CONTROL__EXE_DISABLE__SHIFT 0x17
-#define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18
-#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT 0x1d
-#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f
-#define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x0000003FL
-#define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK 0x00000100L
-#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x00001000L
-#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x00002000L
-#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x00004000L
-#define CP_HQD_EOP_CONTROL__HALT_FETCHER_MASK 0x00200000L
-#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN_MASK 0x00400000L
-#define CP_HQD_EOP_CONTROL__EXE_DISABLE_MASK 0x00800000L
-#define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK 0x01000000L
-#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK 0x60000000L
-#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000L
-//CP_HQD_EOP_RPTR
-#define CP_HQD_EOP_RPTR__RPTR__SHIFT 0x0
-#define CP_HQD_EOP_RPTR__RESET_FETCHER__SHIFT 0x1c
-#define CP_HQD_EOP_RPTR__DEQUEUE_PEND__SHIFT 0x1d
-#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT 0x1e
-#define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT 0x1f
-#define CP_HQD_EOP_RPTR__RPTR_MASK 0x00001FFFL
-#define CP_HQD_EOP_RPTR__RESET_FETCHER_MASK 0x10000000L
-#define CP_HQD_EOP_RPTR__DEQUEUE_PEND_MASK 0x20000000L
-#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000L
-#define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK 0x80000000L
-//CP_HQD_EOP_WPTR
-#define CP_HQD_EOP_WPTR__WPTR__SHIFT 0x0
-#define CP_HQD_EOP_WPTR__EOP_EMPTY__SHIFT 0xf
-#define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT 0x10
-#define CP_HQD_EOP_WPTR__WPTR_MASK 0x00001FFFL
-#define CP_HQD_EOP_WPTR__EOP_EMPTY_MASK 0x00008000L
-#define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK 0x1FFF0000L
-//CP_HQD_EOP_EVENTS
-#define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT 0x0
-#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT 0x10
-#define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK 0x00000FFFL
-#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK 0x00010000L
-//CP_HQD_CTX_SAVE_BASE_ADDR_LO
-#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc
-#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xFFFFF000L
-//CP_HQD_CTX_SAVE_BASE_ADDR_HI
-#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
-#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
-//CP_HQD_CTX_SAVE_CONTROL
-#define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3
-#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT 0x17
-#define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK 0x00000008L
-#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE_MASK 0x00800000L
-//CP_HQD_CNTL_STACK_OFFSET
-#define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2
-#define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK 0x00007FFCL
-//CP_HQD_CNTL_STACK_SIZE
-#define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT 0xc
-#define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK 0x00007000L
-//CP_HQD_WG_STATE_OFFSET
-#define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT 0x2
-#define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x01FFFFFCL
-//CP_HQD_CTX_SAVE_SIZE
-#define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT 0xc
-#define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK 0x01FFF000L
-//CP_HQD_GDS_RESOURCE_STATE
-#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT 0x0
-#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT 0x1
-#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT 0x4
-#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT 0xc
-#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK 0x00000001L
-#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK 0x00000002L
-#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK 0x000003F0L
-#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK 0x0003F000L
-//CP_HQD_ERROR
-#define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT 0x0
-#define CP_HQD_ERROR__SUA_ERROR__SHIFT 0x4
-#define CP_HQD_ERROR__AQL_ERROR__SHIFT 0x5
-#define CP_HQD_ERROR__PQ_UTCL1_ERROR__SHIFT 0x8
-#define CP_HQD_ERROR__IB_UTCL1_ERROR__SHIFT 0x9
-#define CP_HQD_ERROR__EOP_UTCL1_ERROR__SHIFT 0xa
-#define CP_HQD_ERROR__IQ_UTCL1_ERROR__SHIFT 0xb
-#define CP_HQD_ERROR__RRPT_UTCL1_ERROR__SHIFT 0xc
-#define CP_HQD_ERROR__WPP_UTCL1_ERROR__SHIFT 0xd
-#define CP_HQD_ERROR__SEM_UTCL1_ERROR__SHIFT 0xe
-#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0xf
-#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x10
-#define CP_HQD_ERROR__SR_UTCL1_ERROR__SHIFT 0x11
-#define CP_HQD_ERROR__QU_UTCL1_ERROR__SHIFT 0x12
-#define CP_HQD_ERROR__TC_UTCL1_ERROR__SHIFT 0x13
-#define CP_HQD_ERROR__EDC_ERROR_ID_MASK 0x0000000FL
-#define CP_HQD_ERROR__SUA_ERROR_MASK 0x00000010L
-#define CP_HQD_ERROR__AQL_ERROR_MASK 0x00000020L
-#define CP_HQD_ERROR__PQ_UTCL1_ERROR_MASK 0x00000100L
-#define CP_HQD_ERROR__IB_UTCL1_ERROR_MASK 0x00000200L
-#define CP_HQD_ERROR__EOP_UTCL1_ERROR_MASK 0x00000400L
-#define CP_HQD_ERROR__IQ_UTCL1_ERROR_MASK 0x00000800L
-#define CP_HQD_ERROR__RRPT_UTCL1_ERROR_MASK 0x00001000L
-#define CP_HQD_ERROR__WPP_UTCL1_ERROR_MASK 0x00002000L
-#define CP_HQD_ERROR__SEM_UTCL1_ERROR_MASK 0x00004000L
-#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00008000L
-#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00010000L
-#define CP_HQD_ERROR__SR_UTCL1_ERROR_MASK 0x00020000L
-#define CP_HQD_ERROR__QU_UTCL1_ERROR_MASK 0x00040000L
-#define CP_HQD_ERROR__TC_UTCL1_ERROR_MASK 0x00080000L
-//CP_HQD_EOP_WPTR_MEM
-#define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x0
-#define CP_HQD_EOP_WPTR_MEM__WPTR_MASK 0x00001FFFL
-//CP_HQD_AQL_CONTROL
-#define CP_HQD_AQL_CONTROL__CONTROL0__SHIFT 0x0
-#define CP_HQD_AQL_CONTROL__CONTROL0_EN__SHIFT 0xf
-#define CP_HQD_AQL_CONTROL__CONTROL1__SHIFT 0x10
-#define CP_HQD_AQL_CONTROL__CONTROL1_EN__SHIFT 0x1f
-#define CP_HQD_AQL_CONTROL__CONTROL0_MASK 0x00007FFFL
-#define CP_HQD_AQL_CONTROL__CONTROL0_EN_MASK 0x00008000L
-#define CP_HQD_AQL_CONTROL__CONTROL1_MASK 0x7FFF0000L
-#define CP_HQD_AQL_CONTROL__CONTROL1_EN_MASK 0x80000000L
-//CP_HQD_PQ_WPTR_LO
-#define CP_HQD_PQ_WPTR_LO__OFFSET__SHIFT 0x0
-#define CP_HQD_PQ_WPTR_LO__OFFSET_MASK 0xFFFFFFFFL
-//CP_HQD_PQ_WPTR_HI
-#define CP_HQD_PQ_WPTR_HI__DATA__SHIFT 0x0
-#define CP_HQD_PQ_WPTR_HI__DATA_MASK 0xFFFFFFFFL
-
-
-// addressBlock: gc_didtdec
-//DIDT_IND_INDEX
-#define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT 0x0
-#define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK 0xFFFFFFFFL
-//DIDT_IND_DATA
-#define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT 0x0
-#define DIDT_IND_DATA__DIDT_IND_DATA_MASK 0xFFFFFFFFL
-
-
-// addressBlock: gc_gccacdec
-//GC_CAC_CTRL_1
-#define GC_CAC_CTRL_1__CAC_WINDOW__SHIFT 0x0
-#define GC_CAC_CTRL_1__TDP_WINDOW__SHIFT 0x18
-#define GC_CAC_CTRL_1__CAC_WINDOW_MASK 0x00FFFFFFL
-#define GC_CAC_CTRL_1__TDP_WINDOW_MASK 0xFF000000L
-//GC_CAC_CTRL_2
-#define GC_CAC_CTRL_2__CAC_ENABLE__SHIFT 0x0
-#define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE__SHIFT 0x1
-#define GC_CAC_CTRL_2__UNUSED_0__SHIFT 0x2
-#define GC_CAC_CTRL_2__CAC_ENABLE_MASK 0x00000001L
-#define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE_MASK 0x00000002L
-#define GC_CAC_CTRL_2__UNUSED_0_MASK 0xFFFFFFFCL
-//GC_CAC_CGTT_CLK_CTRL
-#define GC_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
-#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
-#define GC_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
-#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
-//GC_CAC_AGGR_LOWER
-#define GC_CAC_AGGR_LOWER__AGGR_31_0__SHIFT 0x0
-#define GC_CAC_AGGR_LOWER__AGGR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_AGGR_UPPER
-#define GC_CAC_AGGR_UPPER__AGGR_63_32__SHIFT 0x0
-#define GC_CAC_AGGR_UPPER__AGGR_63_32_MASK 0xFFFFFFFFL
-//GC_CAC_PG_AGGR_LOWER
-#define GC_CAC_PG_AGGR_LOWER__LKG_AGGR_31_0__SHIFT 0x0
-#define GC_CAC_PG_AGGR_LOWER__LKG_AGGR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_PG_AGGR_UPPER
-#define GC_CAC_PG_AGGR_UPPER__LKG_AGGR_63_32__SHIFT 0x0
-#define GC_CAC_PG_AGGR_UPPER__LKG_AGGR_63_32_MASK 0xFFFFFFFFL
-//GC_CAC_SOFT_CTRL
-#define GC_CAC_SOFT_CTRL__SOFT_SNAP__SHIFT 0x0
-#define GC_CAC_SOFT_CTRL__UNUSED__SHIFT 0x1
-#define GC_CAC_SOFT_CTRL__SOFT_SNAP_MASK 0x00000001L
-#define GC_CAC_SOFT_CTRL__UNUSED_MASK 0xFFFFFFFEL
-//GC_DIDT_CTRL0
-#define GC_DIDT_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
-#define GC_DIDT_CTRL0__PHASE_OFFSET__SHIFT 0x1
-#define GC_DIDT_CTRL0__DIDT_SW_RST__SHIFT 0x3
-#define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
-#define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x5
-#define GC_DIDT_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
-#define GC_DIDT_CTRL0__PHASE_OFFSET_MASK 0x00000006L
-#define GC_DIDT_CTRL0__DIDT_SW_RST_MASK 0x00000008L
-#define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
-#define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001E0L
-//GC_DIDT_CTRL1
-#define GC_DIDT_CTRL1__MIN_POWER__SHIFT 0x0
-#define GC_DIDT_CTRL1__MAX_POWER__SHIFT 0x10
-#define GC_DIDT_CTRL1__MIN_POWER_MASK 0x0000FFFFL
-#define GC_DIDT_CTRL1__MAX_POWER_MASK 0xFFFF0000L
-//GC_DIDT_CTRL2
-#define GC_DIDT_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
-#define GC_DIDT_CTRL2__UNUSED_0__SHIFT 0xe
-#define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
-#define GC_DIDT_CTRL2__UNUSED_1__SHIFT 0x1a
-#define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
-#define GC_DIDT_CTRL2__UNUSED_2__SHIFT 0x1f
-#define GC_DIDT_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
-#define GC_DIDT_CTRL2__UNUSED_0_MASK 0x0000C000L
-#define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
-#define GC_DIDT_CTRL2__UNUSED_1_MASK 0x04000000L
-#define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
-#define GC_DIDT_CTRL2__UNUSED_2_MASK 0x80000000L
-//GC_DIDT_WEIGHT
-#define GC_DIDT_WEIGHT__SQ_WEIGHT__SHIFT 0x0
-#define GC_DIDT_WEIGHT__DB_WEIGHT__SHIFT 0x8
-#define GC_DIDT_WEIGHT__TD_WEIGHT__SHIFT 0x10
-#define GC_DIDT_WEIGHT__TCP_WEIGHT__SHIFT 0x18
-#define GC_DIDT_WEIGHT__SQ_WEIGHT_MASK 0x000000FFL
-#define GC_DIDT_WEIGHT__DB_WEIGHT_MASK 0x0000FF00L
-#define GC_DIDT_WEIGHT__TD_WEIGHT_MASK 0x00FF0000L
-#define GC_DIDT_WEIGHT__TCP_WEIGHT_MASK 0xFF000000L
-//GC_EDC_CTRL
-#define GC_EDC_CTRL__EDC_EN__SHIFT 0x0
-#define GC_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
-#define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
-#define GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
-#define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
-#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x9
-#define GC_EDC_CTRL__UNUSED_0__SHIFT 0xa
-#define GC_EDC_CTRL__EDC_EN_MASK 0x00000001L
-#define GC_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
-#define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
-#define GC_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
-#define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
-#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00000200L
-#define GC_EDC_CTRL__UNUSED_0_MASK 0xFFFFFC00L
-//GC_EDC_THRESHOLD
-#define GC_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
-#define GC_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
-//GC_EDC_STATUS
-#define GC_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x0
-#define GC_EDC_STATUS__EDC_ROLLING_DROOP_DELTA__SHIFT 0x3
-#define GC_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x00000007L
-#define GC_EDC_STATUS__EDC_ROLLING_DROOP_DELTA_MASK 0x03FFFFF8L
-//GC_EDC_OVERFLOW
-#define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0
-#define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1
-#define GC_EDC_OVERFLOW__EDC_DROOP_LEVEL_OVERFLOW__SHIFT 0x11
-#define GC_EDC_OVERFLOW__PSM_COUNTER__SHIFT 0x12
-#define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L
-#define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL
-#define GC_EDC_OVERFLOW__EDC_DROOP_LEVEL_OVERFLOW_MASK 0x00020000L
-#define GC_EDC_OVERFLOW__PSM_COUNTER_MASK 0xFFFC0000L
-//GC_EDC_ROLLING_POWER_DELTA
-#define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0
-#define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL
-//GC_DIDT_DROOP_CTRL
-#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN__SHIFT 0x0
-#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD__SHIFT 0x1
-#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX__SHIFT 0xf
-#define GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL__SHIFT 0x13
-#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW__SHIFT 0x1f
-#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN_MASK 0x00000001L
-#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD_MASK 0x00007FFEL
-#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX_MASK 0x00078000L
-#define GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL_MASK 0x00080000L
-#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW_MASK 0x80000000L
-//GC_EDC_DROOP_CTRL
-#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN__SHIFT 0x0
-#define GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD__SHIFT 0x1
-#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX__SHIFT 0xf
-#define GC_EDC_DROOP_CTRL__AVG_PSM_SEL__SHIFT 0x14
-#define GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL__SHIFT 0x15
-#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN_MASK 0x00000001L
-#define GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD_MASK 0x00007FFEL
-#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX_MASK 0x000F8000L
-#define GC_EDC_DROOP_CTRL__AVG_PSM_SEL_MASK 0x00100000L
-#define GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL_MASK 0x00200000L
-//GC_CAC_IND_INDEX
-#define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR__SHIFT 0x0
-#define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR_MASK 0xFFFFFFFFL
-//GC_CAC_IND_DATA
-#define GC_CAC_IND_DATA__GC_CAC_IND_DATA__SHIFT 0x0
-#define GC_CAC_IND_DATA__GC_CAC_IND_DATA_MASK 0xFFFFFFFFL
-//SE_CAC_CGTT_CLK_CTRL
-#define SE_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
-#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
-#define SE_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
-#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
-//SE_CAC_IND_INDEX
-#define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR__SHIFT 0x0
-#define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR_MASK 0xFFFFFFFFL
-//SE_CAC_IND_DATA
-#define SE_CAC_IND_DATA__SE_CAC_IND_DATA__SHIFT 0x0
-#define SE_CAC_IND_DATA__SE_CAC_IND_DATA_MASK 0xFFFFFFFFL
-
-
-// addressBlock: gc_tcpdec
-//TCP_WATCH0_ADDR_H
-#define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x0
-#define TCP_WATCH0_ADDR_H__ADDR_MASK 0x0000FFFFL
-//TCP_WATCH0_ADDR_L
-#define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x6
-#define TCP_WATCH0_ADDR_L__ADDR_MASK 0xFFFFFFC0L
-//TCP_WATCH0_CNTL
-#define TCP_WATCH0_CNTL__MASK__SHIFT 0x0
-#define TCP_WATCH0_CNTL__VMID__SHIFT 0x18
-#define TCP_WATCH0_CNTL__ATC__SHIFT 0x1c
-#define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d
-#define TCP_WATCH0_CNTL__VALID__SHIFT 0x1f
-#define TCP_WATCH0_CNTL__MASK_MASK 0x00FFFFFFL
-#define TCP_WATCH0_CNTL__VMID_MASK 0x0F000000L
-#define TCP_WATCH0_CNTL__ATC_MASK 0x10000000L
-#define TCP_WATCH0_CNTL__MODE_MASK 0x60000000L
-#define TCP_WATCH0_CNTL__VALID_MASK 0x80000000L
-//TCP_WATCH1_ADDR_H
-#define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x0
-#define TCP_WATCH1_ADDR_H__ADDR_MASK 0x0000FFFFL
-//TCP_WATCH1_ADDR_L
-#define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x6
-#define TCP_WATCH1_ADDR_L__ADDR_MASK 0xFFFFFFC0L
-//TCP_WATCH1_CNTL
-#define TCP_WATCH1_CNTL__MASK__SHIFT 0x0
-#define TCP_WATCH1_CNTL__VMID__SHIFT 0x18
-#define TCP_WATCH1_CNTL__ATC__SHIFT 0x1c
-#define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d
-#define TCP_WATCH1_CNTL__VALID__SHIFT 0x1f
-#define TCP_WATCH1_CNTL__MASK_MASK 0x00FFFFFFL
-#define TCP_WATCH1_CNTL__VMID_MASK 0x0F000000L
-#define TCP_WATCH1_CNTL__ATC_MASK 0x10000000L
-#define TCP_WATCH1_CNTL__MODE_MASK 0x60000000L
-#define TCP_WATCH1_CNTL__VALID_MASK 0x80000000L
-//TCP_WATCH2_ADDR_H
-#define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x0
-#define TCP_WATCH2_ADDR_H__ADDR_MASK 0x0000FFFFL
-//TCP_WATCH2_ADDR_L
-#define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x6
-#define TCP_WATCH2_ADDR_L__ADDR_MASK 0xFFFFFFC0L
-//TCP_WATCH2_CNTL
-#define TCP_WATCH2_CNTL__MASK__SHIFT 0x0
-#define TCP_WATCH2_CNTL__VMID__SHIFT 0x18
-#define TCP_WATCH2_CNTL__ATC__SHIFT 0x1c
-#define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d
-#define TCP_WATCH2_CNTL__VALID__SHIFT 0x1f
-#define TCP_WATCH2_CNTL__MASK_MASK 0x00FFFFFFL
-#define TCP_WATCH2_CNTL__VMID_MASK 0x0F000000L
-#define TCP_WATCH2_CNTL__ATC_MASK 0x10000000L
-#define TCP_WATCH2_CNTL__MODE_MASK 0x60000000L
-#define TCP_WATCH2_CNTL__VALID_MASK 0x80000000L
-//TCP_WATCH3_ADDR_H
-#define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x0
-#define TCP_WATCH3_ADDR_H__ADDR_MASK 0x0000FFFFL
-//TCP_WATCH3_ADDR_L
-#define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x6
-#define TCP_WATCH3_ADDR_L__ADDR_MASK 0xFFFFFFC0L
-//TCP_WATCH3_CNTL
-#define TCP_WATCH3_CNTL__MASK__SHIFT 0x0
-#define TCP_WATCH3_CNTL__VMID__SHIFT 0x18
-#define TCP_WATCH3_CNTL__ATC__SHIFT 0x1c
-#define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d
-#define TCP_WATCH3_CNTL__VALID__SHIFT 0x1f
-#define TCP_WATCH3_CNTL__MASK_MASK 0x00FFFFFFL
-#define TCP_WATCH3_CNTL__VMID_MASK 0x0F000000L
-#define TCP_WATCH3_CNTL__ATC_MASK 0x10000000L
-#define TCP_WATCH3_CNTL__MODE_MASK 0x60000000L
-#define TCP_WATCH3_CNTL__VALID_MASK 0x80000000L
-//TCP_GATCL1_CNTL
-#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID__SHIFT 0x19
-#define TCP_GATCL1_CNTL__FORCE_MISS__SHIFT 0x1a
-#define TCP_GATCL1_CNTL__FORCE_IN_ORDER__SHIFT 0x1b
-#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
-#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
-#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID_MASK 0x02000000L
-#define TCP_GATCL1_CNTL__FORCE_MISS_MASK 0x04000000L
-#define TCP_GATCL1_CNTL__FORCE_IN_ORDER_MASK 0x08000000L
-#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
-#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
-//TCP_ATC_EDC_GATCL1_CNT
-#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC__SHIFT 0x0
-#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC_MASK 0x000000FFL
-//TCP_GATCL1_DSM_CNTL
-#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0__SHIFT 0x0
-#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1__SHIFT 0x1
-#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A__SHIFT 0x2
-#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0_MASK 0x00000001L
-#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1_MASK 0x00000002L
-#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A_MASK 0x00000004L
-//TCP_CNTL2
-#define TCP_CNTL2__LS_DISABLE_CLOCKS__SHIFT 0x0
-#define TCP_CNTL2__LS_DISABLE_CLOCKS_MASK 0x000000FFL
-//TCP_UTCL1_CNTL1
-#define TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
-#define TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1
-#define TCP_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
-#define TCP_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
-#define TCP_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
-#define TCP_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
-#define TCP_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13
-#define TCP_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17
-#define TCP_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18
-#define TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
-#define TCP_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
-#define TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
-#define TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
-#define TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
-#define TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L
-#define TCP_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
-#define TCP_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
-#define TCP_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
-#define TCP_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
-#define TCP_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L
-#define TCP_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L
-#define TCP_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L
-#define TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
-#define TCP_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
-#define TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
-#define TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
-//TCP_UTCL1_CNTL2
-#define TCP_UTCL1_CNTL2__SPARE__SHIFT 0x0
-#define TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
-#define TCP_UTCL1_CNTL2__ANY_LINE_VALID__SHIFT 0xa
-#define TCP_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
-#define TCP_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
-#define TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
-#define TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
-#define TCP_UTCL1_CNTL2__SPARE_MASK 0x000000FFL
-#define TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
-#define TCP_UTCL1_CNTL2__ANY_LINE_VALID_MASK 0x00000400L
-#define TCP_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
-#define TCP_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
-#define TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
-#define TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
-//TCP_UTCL1_STATUS
-#define TCP_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
-#define TCP_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
-#define TCP_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
-#define TCP_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
-#define TCP_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
-#define TCP_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
-//TCP_PERFCOUNTER_FILTER
-#define TCP_PERFCOUNTER_FILTER__BUFFER__SHIFT 0x0
-#define TCP_PERFCOUNTER_FILTER__FLAT__SHIFT 0x1
-#define TCP_PERFCOUNTER_FILTER__DIM__SHIFT 0x2
-#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT__SHIFT 0x5
-#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT__SHIFT 0xb
-#define TCP_PERFCOUNTER_FILTER__SW_MODE__SHIFT 0xf
-#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES__SHIFT 0x14
-#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE__SHIFT 0x16
-#define TCP_PERFCOUNTER_FILTER__GLC__SHIFT 0x19
-#define TCP_PERFCOUNTER_FILTER__SLC__SHIFT 0x1a
-#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE__SHIFT 0x1b
-#define TCP_PERFCOUNTER_FILTER__ADDR_MODE__SHIFT 0x1c
-#define TCP_PERFCOUNTER_FILTER__BUFFER_MASK 0x00000001L
-#define TCP_PERFCOUNTER_FILTER__FLAT_MASK 0x00000002L
-#define TCP_PERFCOUNTER_FILTER__DIM_MASK 0x0000001CL
-#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT_MASK 0x000007E0L
-#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT_MASK 0x00007800L
-#define TCP_PERFCOUNTER_FILTER__SW_MODE_MASK 0x000F8000L
-#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES_MASK 0x00300000L
-#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE_MASK 0x01C00000L
-#define TCP_PERFCOUNTER_FILTER__GLC_MASK 0x02000000L
-#define TCP_PERFCOUNTER_FILTER__SLC_MASK 0x04000000L
-#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE_MASK 0x08000000L
-#define TCP_PERFCOUNTER_FILTER__ADDR_MODE_MASK 0x70000000L
-//TCP_PERFCOUNTER_FILTER_EN
-#define TCP_PERFCOUNTER_FILTER_EN__BUFFER__SHIFT 0x0
-#define TCP_PERFCOUNTER_FILTER_EN__FLAT__SHIFT 0x1
-#define TCP_PERFCOUNTER_FILTER_EN__DIM__SHIFT 0x2
-#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT__SHIFT 0x3
-#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT__SHIFT 0x4
-#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE__SHIFT 0x5
-#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES__SHIFT 0x6
-#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE__SHIFT 0x7
-#define TCP_PERFCOUNTER_FILTER_EN__GLC__SHIFT 0x8
-#define TCP_PERFCOUNTER_FILTER_EN__SLC__SHIFT 0x9
-#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE__SHIFT 0xa
-#define TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE__SHIFT 0xb
-#define TCP_PERFCOUNTER_FILTER_EN__BUFFER_MASK 0x00000001L
-#define TCP_PERFCOUNTER_FILTER_EN__FLAT_MASK 0x00000002L
-#define TCP_PERFCOUNTER_FILTER_EN__DIM_MASK 0x00000004L
-#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT_MASK 0x00000008L
-#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT_MASK 0x00000010L
-#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE_MASK 0x00000020L
-#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES_MASK 0x00000040L
-#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE_MASK 0x00000080L
-#define TCP_PERFCOUNTER_FILTER_EN__GLC_MASK 0x00000100L
-#define TCP_PERFCOUNTER_FILTER_EN__SLC_MASK 0x00000200L
-#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE_MASK 0x00000400L
-#define TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE_MASK 0x00000800L
-
-
-// addressBlock: gc_gdspdec
-//GDS_VMID0_BASE
-#define GDS_VMID0_BASE__BASE__SHIFT 0x0
-#define GDS_VMID0_BASE__BASE_MASK 0x0000FFFFL
-//GDS_VMID0_SIZE
-#define GDS_VMID0_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID0_SIZE__SIZE_MASK 0x0001FFFFL
-//GDS_VMID1_BASE
-#define GDS_VMID1_BASE__BASE__SHIFT 0x0
-#define GDS_VMID1_BASE__BASE_MASK 0x0000FFFFL
-//GDS_VMID1_SIZE
-#define GDS_VMID1_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID1_SIZE__SIZE_MASK 0x0001FFFFL
-//GDS_VMID2_BASE
-#define GDS_VMID2_BASE__BASE__SHIFT 0x0
-#define GDS_VMID2_BASE__BASE_MASK 0x0000FFFFL
-//GDS_VMID2_SIZE
-#define GDS_VMID2_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID2_SIZE__SIZE_MASK 0x0001FFFFL
-//GDS_VMID3_BASE
-#define GDS_VMID3_BASE__BASE__SHIFT 0x0
-#define GDS_VMID3_BASE__BASE_MASK 0x0000FFFFL
-//GDS_VMID3_SIZE
-#define GDS_VMID3_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID3_SIZE__SIZE_MASK 0x0001FFFFL
-//GDS_VMID4_BASE
-#define GDS_VMID4_BASE__BASE__SHIFT 0x0
-#define GDS_VMID4_BASE__BASE_MASK 0x0000FFFFL
-//GDS_VMID4_SIZE
-#define GDS_VMID4_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID4_SIZE__SIZE_MASK 0x0001FFFFL
-//GDS_VMID5_BASE
-#define GDS_VMID5_BASE__BASE__SHIFT 0x0
-#define GDS_VMID5_BASE__BASE_MASK 0x0000FFFFL
-//GDS_VMID5_SIZE
-#define GDS_VMID5_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID5_SIZE__SIZE_MASK 0x0001FFFFL
-//GDS_VMID6_BASE
-#define GDS_VMID6_BASE__BASE__SHIFT 0x0
-#define GDS_VMID6_BASE__BASE_MASK 0x0000FFFFL
-//GDS_VMID6_SIZE
-#define GDS_VMID6_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID6_SIZE__SIZE_MASK 0x0001FFFFL
-//GDS_VMID7_BASE
-#define GDS_VMID7_BASE__BASE__SHIFT 0x0
-#define GDS_VMID7_BASE__BASE_MASK 0x0000FFFFL
-//GDS_VMID7_SIZE
-#define GDS_VMID7_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID7_SIZE__SIZE_MASK 0x0001FFFFL
-//GDS_VMID8_BASE
-#define GDS_VMID8_BASE__BASE__SHIFT 0x0
-#define GDS_VMID8_BASE__BASE_MASK 0x0000FFFFL
-//GDS_VMID8_SIZE
-#define GDS_VMID8_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID8_SIZE__SIZE_MASK 0x0001FFFFL
-//GDS_VMID9_BASE
-#define GDS_VMID9_BASE__BASE__SHIFT 0x0
-#define GDS_VMID9_BASE__BASE_MASK 0x0000FFFFL
-//GDS_VMID9_SIZE
-#define GDS_VMID9_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID9_SIZE__SIZE_MASK 0x0001FFFFL
-//GDS_VMID10_BASE
-#define GDS_VMID10_BASE__BASE__SHIFT 0x0
-#define GDS_VMID10_BASE__BASE_MASK 0x0000FFFFL
-//GDS_VMID10_SIZE
-#define GDS_VMID10_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID10_SIZE__SIZE_MASK 0x0001FFFFL
-//GDS_VMID11_BASE
-#define GDS_VMID11_BASE__BASE__SHIFT 0x0
-#define GDS_VMID11_BASE__BASE_MASK 0x0000FFFFL
-//GDS_VMID11_SIZE
-#define GDS_VMID11_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID11_SIZE__SIZE_MASK 0x0001FFFFL
-//GDS_VMID12_BASE
-#define GDS_VMID12_BASE__BASE__SHIFT 0x0
-#define GDS_VMID12_BASE__BASE_MASK 0x0000FFFFL
-//GDS_VMID12_SIZE
-#define GDS_VMID12_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID12_SIZE__SIZE_MASK 0x0001FFFFL
-//GDS_VMID13_BASE
-#define GDS_VMID13_BASE__BASE__SHIFT 0x0
-#define GDS_VMID13_BASE__BASE_MASK 0x0000FFFFL
-//GDS_VMID13_SIZE
-#define GDS_VMID13_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID13_SIZE__SIZE_MASK 0x0001FFFFL
-//GDS_VMID14_BASE
-#define GDS_VMID14_BASE__BASE__SHIFT 0x0
-#define GDS_VMID14_BASE__BASE_MASK 0x0000FFFFL
-//GDS_VMID14_SIZE
-#define GDS_VMID14_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID14_SIZE__SIZE_MASK 0x0001FFFFL
-//GDS_VMID15_BASE
-#define GDS_VMID15_BASE__BASE__SHIFT 0x0
-#define GDS_VMID15_BASE__BASE_MASK 0x0000FFFFL
-//GDS_VMID15_SIZE
-#define GDS_VMID15_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID15_SIZE__SIZE_MASK 0x0001FFFFL
-//GDS_GWS_VMID0
-#define GDS_GWS_VMID0__BASE__SHIFT 0x0
-#define GDS_GWS_VMID0__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID0__BASE_MASK 0x0000003FL
-#define GDS_GWS_VMID0__SIZE_MASK 0x007F0000L
-//GDS_GWS_VMID1
-#define GDS_GWS_VMID1__BASE__SHIFT 0x0
-#define GDS_GWS_VMID1__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID1__BASE_MASK 0x0000003FL
-#define GDS_GWS_VMID1__SIZE_MASK 0x007F0000L
-//GDS_GWS_VMID2
-#define GDS_GWS_VMID2__BASE__SHIFT 0x0
-#define GDS_GWS_VMID2__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID2__BASE_MASK 0x0000003FL
-#define GDS_GWS_VMID2__SIZE_MASK 0x007F0000L
-//GDS_GWS_VMID3
-#define GDS_GWS_VMID3__BASE__SHIFT 0x0
-#define GDS_GWS_VMID3__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID3__BASE_MASK 0x0000003FL
-#define GDS_GWS_VMID3__SIZE_MASK 0x007F0000L
-//GDS_GWS_VMID4
-#define GDS_GWS_VMID4__BASE__SHIFT 0x0
-#define GDS_GWS_VMID4__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID4__BASE_MASK 0x0000003FL
-#define GDS_GWS_VMID4__SIZE_MASK 0x007F0000L
-//GDS_GWS_VMID5
-#define GDS_GWS_VMID5__BASE__SHIFT 0x0
-#define GDS_GWS_VMID5__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID5__BASE_MASK 0x0000003FL
-#define GDS_GWS_VMID5__SIZE_MASK 0x007F0000L
-//GDS_GWS_VMID6
-#define GDS_GWS_VMID6__BASE__SHIFT 0x0
-#define GDS_GWS_VMID6__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID6__BASE_MASK 0x0000003FL
-#define GDS_GWS_VMID6__SIZE_MASK 0x007F0000L
-//GDS_GWS_VMID7
-#define GDS_GWS_VMID7__BASE__SHIFT 0x0
-#define GDS_GWS_VMID7__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID7__BASE_MASK 0x0000003FL
-#define GDS_GWS_VMID7__SIZE_MASK 0x007F0000L
-//GDS_GWS_VMID8
-#define GDS_GWS_VMID8__BASE__SHIFT 0x0
-#define GDS_GWS_VMID8__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID8__BASE_MASK 0x0000003FL
-#define GDS_GWS_VMID8__SIZE_MASK 0x007F0000L
-//GDS_GWS_VMID9
-#define GDS_GWS_VMID9__BASE__SHIFT 0x0
-#define GDS_GWS_VMID9__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID9__BASE_MASK 0x0000003FL
-#define GDS_GWS_VMID9__SIZE_MASK 0x007F0000L
-//GDS_GWS_VMID10
-#define GDS_GWS_VMID10__BASE__SHIFT 0x0
-#define GDS_GWS_VMID10__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID10__BASE_MASK 0x0000003FL
-#define GDS_GWS_VMID10__SIZE_MASK 0x007F0000L
-//GDS_GWS_VMID11
-#define GDS_GWS_VMID11__BASE__SHIFT 0x0
-#define GDS_GWS_VMID11__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID11__BASE_MASK 0x0000003FL
-#define GDS_GWS_VMID11__SIZE_MASK 0x007F0000L
-//GDS_GWS_VMID12
-#define GDS_GWS_VMID12__BASE__SHIFT 0x0
-#define GDS_GWS_VMID12__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID12__BASE_MASK 0x0000003FL
-#define GDS_GWS_VMID12__SIZE_MASK 0x007F0000L
-//GDS_GWS_VMID13
-#define GDS_GWS_VMID13__BASE__SHIFT 0x0
-#define GDS_GWS_VMID13__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID13__BASE_MASK 0x0000003FL
-#define GDS_GWS_VMID13__SIZE_MASK 0x007F0000L
-//GDS_GWS_VMID14
-#define GDS_GWS_VMID14__BASE__SHIFT 0x0
-#define GDS_GWS_VMID14__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID14__BASE_MASK 0x0000003FL
-#define GDS_GWS_VMID14__SIZE_MASK 0x007F0000L
-//GDS_GWS_VMID15
-#define GDS_GWS_VMID15__BASE__SHIFT 0x0
-#define GDS_GWS_VMID15__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID15__BASE_MASK 0x0000003FL
-#define GDS_GWS_VMID15__SIZE_MASK 0x007F0000L
-//GDS_OA_VMID0
-#define GDS_OA_VMID0__MASK__SHIFT 0x0
-#define GDS_OA_VMID0__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID0__MASK_MASK 0x0000FFFFL
-#define GDS_OA_VMID0__UNUSED_MASK 0xFFFF0000L
-//GDS_OA_VMID1
-#define GDS_OA_VMID1__MASK__SHIFT 0x0
-#define GDS_OA_VMID1__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID1__MASK_MASK 0x0000FFFFL
-#define GDS_OA_VMID1__UNUSED_MASK 0xFFFF0000L
-//GDS_OA_VMID2
-#define GDS_OA_VMID2__MASK__SHIFT 0x0
-#define GDS_OA_VMID2__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID2__MASK_MASK 0x0000FFFFL
-#define GDS_OA_VMID2__UNUSED_MASK 0xFFFF0000L
-//GDS_OA_VMID3
-#define GDS_OA_VMID3__MASK__SHIFT 0x0
-#define GDS_OA_VMID3__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID3__MASK_MASK 0x0000FFFFL
-#define GDS_OA_VMID3__UNUSED_MASK 0xFFFF0000L
-//GDS_OA_VMID4
-#define GDS_OA_VMID4__MASK__SHIFT 0x0
-#define GDS_OA_VMID4__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID4__MASK_MASK 0x0000FFFFL
-#define GDS_OA_VMID4__UNUSED_MASK 0xFFFF0000L
-//GDS_OA_VMID5
-#define GDS_OA_VMID5__MASK__SHIFT 0x0
-#define GDS_OA_VMID5__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID5__MASK_MASK 0x0000FFFFL
-#define GDS_OA_VMID5__UNUSED_MASK 0xFFFF0000L
-//GDS_OA_VMID6
-#define GDS_OA_VMID6__MASK__SHIFT 0x0
-#define GDS_OA_VMID6__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID6__MASK_MASK 0x0000FFFFL
-#define GDS_OA_VMID6__UNUSED_MASK 0xFFFF0000L
-//GDS_OA_VMID7
-#define GDS_OA_VMID7__MASK__SHIFT 0x0
-#define GDS_OA_VMID7__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID7__MASK_MASK 0x0000FFFFL
-#define GDS_OA_VMID7__UNUSED_MASK 0xFFFF0000L
-//GDS_OA_VMID8
-#define GDS_OA_VMID8__MASK__SHIFT 0x0
-#define GDS_OA_VMID8__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID8__MASK_MASK 0x0000FFFFL
-#define GDS_OA_VMID8__UNUSED_MASK 0xFFFF0000L
-//GDS_OA_VMID9
-#define GDS_OA_VMID9__MASK__SHIFT 0x0
-#define GDS_OA_VMID9__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID9__MASK_MASK 0x0000FFFFL
-#define GDS_OA_VMID9__UNUSED_MASK 0xFFFF0000L
-//GDS_OA_VMID10
-#define GDS_OA_VMID10__MASK__SHIFT 0x0
-#define GDS_OA_VMID10__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID10__MASK_MASK 0x0000FFFFL
-#define GDS_OA_VMID10__UNUSED_MASK 0xFFFF0000L
-//GDS_OA_VMID11
-#define GDS_OA_VMID11__MASK__SHIFT 0x0
-#define GDS_OA_VMID11__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID11__MASK_MASK 0x0000FFFFL
-#define GDS_OA_VMID11__UNUSED_MASK 0xFFFF0000L
-//GDS_OA_VMID12
-#define GDS_OA_VMID12__MASK__SHIFT 0x0
-#define GDS_OA_VMID12__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID12__MASK_MASK 0x0000FFFFL
-#define GDS_OA_VMID12__UNUSED_MASK 0xFFFF0000L
-//GDS_OA_VMID13
-#define GDS_OA_VMID13__MASK__SHIFT 0x0
-#define GDS_OA_VMID13__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID13__MASK_MASK 0x0000FFFFL
-#define GDS_OA_VMID13__UNUSED_MASK 0xFFFF0000L
-//GDS_OA_VMID14
-#define GDS_OA_VMID14__MASK__SHIFT 0x0
-#define GDS_OA_VMID14__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID14__MASK_MASK 0x0000FFFFL
-#define GDS_OA_VMID14__UNUSED_MASK 0xFFFF0000L
-//GDS_OA_VMID15
-#define GDS_OA_VMID15__MASK__SHIFT 0x0
-#define GDS_OA_VMID15__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID15__MASK_MASK 0x0000FFFFL
-#define GDS_OA_VMID15__UNUSED_MASK 0xFFFF0000L
-//GDS_GWS_RESET0
-#define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT 0x0
-#define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT 0x1
-#define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT 0x2
-#define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT 0x3
-#define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT 0x4
-#define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT 0x5
-#define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT 0x6
-#define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT 0x7
-#define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT 0x8
-#define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT 0x9
-#define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa
-#define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT 0xb
-#define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT 0xc
-#define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT 0xd
-#define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT 0xe
-#define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT 0xf
-#define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT 0x10
-#define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT 0x11
-#define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT 0x12
-#define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT 0x13
-#define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT 0x14
-#define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT 0x15
-#define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT 0x16
-#define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT 0x17
-#define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT 0x18
-#define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT 0x19
-#define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT 0x1a
-#define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT 0x1b
-#define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT 0x1c
-#define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d
-#define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT 0x1e
-#define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT 0x1f
-#define GDS_GWS_RESET0__RESOURCE0_RESET_MASK 0x00000001L
-#define GDS_GWS_RESET0__RESOURCE1_RESET_MASK 0x00000002L
-#define GDS_GWS_RESET0__RESOURCE2_RESET_MASK 0x00000004L
-#define GDS_GWS_RESET0__RESOURCE3_RESET_MASK 0x00000008L
-#define GDS_GWS_RESET0__RESOURCE4_RESET_MASK 0x00000010L
-#define GDS_GWS_RESET0__RESOURCE5_RESET_MASK 0x00000020L
-#define GDS_GWS_RESET0__RESOURCE6_RESET_MASK 0x00000040L
-#define GDS_GWS_RESET0__RESOURCE7_RESET_MASK 0x00000080L
-#define GDS_GWS_RESET0__RESOURCE8_RESET_MASK 0x00000100L
-#define GDS_GWS_RESET0__RESOURCE9_RESET_MASK 0x00000200L
-#define GDS_GWS_RESET0__RESOURCE10_RESET_MASK 0x00000400L
-#define GDS_GWS_RESET0__RESOURCE11_RESET_MASK 0x00000800L
-#define GDS_GWS_RESET0__RESOURCE12_RESET_MASK 0x00001000L
-#define GDS_GWS_RESET0__RESOURCE13_RESET_MASK 0x00002000L
-#define GDS_GWS_RESET0__RESOURCE14_RESET_MASK 0x00004000L
-#define GDS_GWS_RESET0__RESOURCE15_RESET_MASK 0x00008000L
-#define GDS_GWS_RESET0__RESOURCE16_RESET_MASK 0x00010000L
-#define GDS_GWS_RESET0__RESOURCE17_RESET_MASK 0x00020000L
-#define GDS_GWS_RESET0__RESOURCE18_RESET_MASK 0x00040000L
-#define GDS_GWS_RESET0__RESOURCE19_RESET_MASK 0x00080000L
-#define GDS_GWS_RESET0__RESOURCE20_RESET_MASK 0x00100000L
-#define GDS_GWS_RESET0__RESOURCE21_RESET_MASK 0x00200000L
-#define GDS_GWS_RESET0__RESOURCE22_RESET_MASK 0x00400000L
-#define GDS_GWS_RESET0__RESOURCE23_RESET_MASK 0x00800000L
-#define GDS_GWS_RESET0__RESOURCE24_RESET_MASK 0x01000000L
-#define GDS_GWS_RESET0__RESOURCE25_RESET_MASK 0x02000000L
-#define GDS_GWS_RESET0__RESOURCE26_RESET_MASK 0x04000000L
-#define GDS_GWS_RESET0__RESOURCE27_RESET_MASK 0x08000000L
-#define GDS_GWS_RESET0__RESOURCE28_RESET_MASK 0x10000000L
-#define GDS_GWS_RESET0__RESOURCE29_RESET_MASK 0x20000000L
-#define GDS_GWS_RESET0__RESOURCE30_RESET_MASK 0x40000000L
-#define GDS_GWS_RESET0__RESOURCE31_RESET_MASK 0x80000000L
-//GDS_GWS_RESET1
-#define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT 0x0
-#define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT 0x1
-#define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT 0x2
-#define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT 0x3
-#define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT 0x4
-#define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT 0x5
-#define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT 0x6
-#define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT 0x7
-#define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT 0x8
-#define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT 0x9
-#define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa
-#define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT 0xb
-#define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT 0xc
-#define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT 0xd
-#define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT 0xe
-#define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT 0xf
-#define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT 0x10
-#define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT 0x11
-#define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT 0x12
-#define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT 0x13
-#define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT 0x14
-#define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT 0x15
-#define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT 0x16
-#define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT 0x17
-#define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT 0x18
-#define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT 0x19
-#define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT 0x1a
-#define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT 0x1b
-#define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT 0x1c
-#define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d
-#define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT 0x1e
-#define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT 0x1f
-#define GDS_GWS_RESET1__RESOURCE32_RESET_MASK 0x00000001L
-#define GDS_GWS_RESET1__RESOURCE33_RESET_MASK 0x00000002L
-#define GDS_GWS_RESET1__RESOURCE34_RESET_MASK 0x00000004L
-#define GDS_GWS_RESET1__RESOURCE35_RESET_MASK 0x00000008L
-#define GDS_GWS_RESET1__RESOURCE36_RESET_MASK 0x00000010L
-#define GDS_GWS_RESET1__RESOURCE37_RESET_MASK 0x00000020L
-#define GDS_GWS_RESET1__RESOURCE38_RESET_MASK 0x00000040L
-#define GDS_GWS_RESET1__RESOURCE39_RESET_MASK 0x00000080L
-#define GDS_GWS_RESET1__RESOURCE40_RESET_MASK 0x00000100L
-#define GDS_GWS_RESET1__RESOURCE41_RESET_MASK 0x00000200L
-#define GDS_GWS_RESET1__RESOURCE42_RESET_MASK 0x00000400L
-#define GDS_GWS_RESET1__RESOURCE43_RESET_MASK 0x00000800L
-#define GDS_GWS_RESET1__RESOURCE44_RESET_MASK 0x00001000L
-#define GDS_GWS_RESET1__RESOURCE45_RESET_MASK 0x00002000L
-#define GDS_GWS_RESET1__RESOURCE46_RESET_MASK 0x00004000L
-#define GDS_GWS_RESET1__RESOURCE47_RESET_MASK 0x00008000L
-#define GDS_GWS_RESET1__RESOURCE48_RESET_MASK 0x00010000L
-#define GDS_GWS_RESET1__RESOURCE49_RESET_MASK 0x00020000L
-#define GDS_GWS_RESET1__RESOURCE50_RESET_MASK 0x00040000L
-#define GDS_GWS_RESET1__RESOURCE51_RESET_MASK 0x00080000L
-#define GDS_GWS_RESET1__RESOURCE52_RESET_MASK 0x00100000L
-#define GDS_GWS_RESET1__RESOURCE53_RESET_MASK 0x00200000L
-#define GDS_GWS_RESET1__RESOURCE54_RESET_MASK 0x00400000L
-#define GDS_GWS_RESET1__RESOURCE55_RESET_MASK 0x00800000L
-#define GDS_GWS_RESET1__RESOURCE56_RESET_MASK 0x01000000L
-#define GDS_GWS_RESET1__RESOURCE57_RESET_MASK 0x02000000L
-#define GDS_GWS_RESET1__RESOURCE58_RESET_MASK 0x04000000L
-#define GDS_GWS_RESET1__RESOURCE59_RESET_MASK 0x08000000L
-#define GDS_GWS_RESET1__RESOURCE60_RESET_MASK 0x10000000L
-#define GDS_GWS_RESET1__RESOURCE61_RESET_MASK 0x20000000L
-#define GDS_GWS_RESET1__RESOURCE62_RESET_MASK 0x40000000L
-#define GDS_GWS_RESET1__RESOURCE63_RESET_MASK 0x80000000L
-//GDS_GWS_RESOURCE_RESET
-#define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x0
-#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x8
-#define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x00000001L
-#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0x0000FF00L
-//GDS_COMPUTE_MAX_WAVE_ID
-#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
-#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
-//GDS_OA_RESET_MASK
-#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT 0x0
-#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT 0x1
-#define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT 0x2
-#define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET__SHIFT 0x3
-#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT 0x4
-#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT 0x5
-#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT 0x6
-#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT 0x7
-#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT 0x8
-#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT 0x9
-#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa
-#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT 0xb
-#define GDS_OA_RESET_MASK__UNUSED1__SHIFT 0xc
-#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK 0x00000001L
-#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK 0x00000002L
-#define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK 0x00000004L
-#define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET_MASK 0x00000008L
-#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK 0x00000010L
-#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK 0x00000020L
-#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK 0x00000040L
-#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK 0x00000080L
-#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK 0x00000100L
-#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK 0x00000200L
-#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK 0x00000400L
-#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK 0x00000800L
-#define GDS_OA_RESET_MASK__UNUSED1_MASK 0xFFFFF000L
-//GDS_OA_RESET
-#define GDS_OA_RESET__RESET__SHIFT 0x0
-#define GDS_OA_RESET__PIPE_ID__SHIFT 0x8
-#define GDS_OA_RESET__RESET_MASK 0x00000001L
-#define GDS_OA_RESET__PIPE_ID_MASK 0x0000FF00L
-//GDS_ENHANCE
-#define GDS_ENHANCE__MISC__SHIFT 0x0
-#define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x10
-#define GDS_ENHANCE__CGPG_RESTORE__SHIFT 0x11
-#define GDS_ENHANCE__RD_BUF_TAG_MISS__SHIFT 0x12
-#define GDS_ENHANCE__GDSA_PC_CGTS_DIS__SHIFT 0x13
-#define GDS_ENHANCE__GDSO_PC_CGTS_DIS__SHIFT 0x14
-#define GDS_ENHANCE__WD_GDS_CSB_OVERRIDE__SHIFT 0x15
-#define GDS_ENHANCE__UNUSED__SHIFT 0x16
-#define GDS_ENHANCE__MISC_MASK 0x0000FFFFL
-#define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x00010000L
-#define GDS_ENHANCE__CGPG_RESTORE_MASK 0x00020000L
-#define GDS_ENHANCE__RD_BUF_TAG_MISS_MASK 0x00040000L
-#define GDS_ENHANCE__GDSA_PC_CGTS_DIS_MASK 0x00080000L
-#define GDS_ENHANCE__GDSO_PC_CGTS_DIS_MASK 0x00100000L
-#define GDS_ENHANCE__WD_GDS_CSB_OVERRIDE_MASK 0x00200000L
-#define GDS_ENHANCE__UNUSED_MASK 0xFFC00000L
-//GDS_OA_CGPG_RESTORE
-#define GDS_OA_CGPG_RESTORE__VMID__SHIFT 0x0
-#define GDS_OA_CGPG_RESTORE__MEID__SHIFT 0x8
-#define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT 0xc
-#define GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT 0x10
-#define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT 0x14
-#define GDS_OA_CGPG_RESTORE__VMID_MASK 0x000000FFL
-#define GDS_OA_CGPG_RESTORE__MEID_MASK 0x00000F00L
-#define GDS_OA_CGPG_RESTORE__PIPEID_MASK 0x0000F000L
-#define GDS_OA_CGPG_RESTORE__QUEUEID_MASK 0x000F0000L
-#define GDS_OA_CGPG_RESTORE__UNUSED_MASK 0xFFF00000L
-//GDS_CS_CTXSW_STATUS
-#define GDS_CS_CTXSW_STATUS__R__SHIFT 0x0
-#define GDS_CS_CTXSW_STATUS__W__SHIFT 0x1
-#define GDS_CS_CTXSW_STATUS__UNUSED__SHIFT 0x2
-#define GDS_CS_CTXSW_STATUS__R_MASK 0x00000001L
-#define GDS_CS_CTXSW_STATUS__W_MASK 0x00000002L
-#define GDS_CS_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL
-//GDS_CS_CTXSW_CNT0
-#define GDS_CS_CTXSW_CNT0__UPDN__SHIFT 0x0
-#define GDS_CS_CTXSW_CNT0__PTR__SHIFT 0x10
-#define GDS_CS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
-#define GDS_CS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
-//GDS_CS_CTXSW_CNT1
-#define GDS_CS_CTXSW_CNT1__UPDN__SHIFT 0x0
-#define GDS_CS_CTXSW_CNT1__PTR__SHIFT 0x10
-#define GDS_CS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
-#define GDS_CS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
-//GDS_CS_CTXSW_CNT2
-#define GDS_CS_CTXSW_CNT2__UPDN__SHIFT 0x0
-#define GDS_CS_CTXSW_CNT2__PTR__SHIFT 0x10
-#define GDS_CS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
-#define GDS_CS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
-//GDS_CS_CTXSW_CNT3
-#define GDS_CS_CTXSW_CNT3__UPDN__SHIFT 0x0
-#define GDS_CS_CTXSW_CNT3__PTR__SHIFT 0x10
-#define GDS_CS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
-#define GDS_CS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
-//GDS_GFX_CTXSW_STATUS
-#define GDS_GFX_CTXSW_STATUS__R__SHIFT 0x0
-#define GDS_GFX_CTXSW_STATUS__W__SHIFT 0x1
-#define GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT 0x2
-#define GDS_GFX_CTXSW_STATUS__R_MASK 0x00000001L
-#define GDS_GFX_CTXSW_STATUS__W_MASK 0x00000002L
-#define GDS_GFX_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL
-//GDS_VS_CTXSW_CNT0
-#define GDS_VS_CTXSW_CNT0__UPDN__SHIFT 0x0
-#define GDS_VS_CTXSW_CNT0__PTR__SHIFT 0x10
-#define GDS_VS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
-#define GDS_VS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
-//GDS_VS_CTXSW_CNT1
-#define GDS_VS_CTXSW_CNT1__UPDN__SHIFT 0x0
-#define GDS_VS_CTXSW_CNT1__PTR__SHIFT 0x10
-#define GDS_VS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
-#define GDS_VS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
-//GDS_VS_CTXSW_CNT2
-#define GDS_VS_CTXSW_CNT2__UPDN__SHIFT 0x0
-#define GDS_VS_CTXSW_CNT2__PTR__SHIFT 0x10
-#define GDS_VS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
-#define GDS_VS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
-//GDS_VS_CTXSW_CNT3
-#define GDS_VS_CTXSW_CNT3__UPDN__SHIFT 0x0
-#define GDS_VS_CTXSW_CNT3__PTR__SHIFT 0x10
-#define GDS_VS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
-#define GDS_VS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
-//GDS_PS0_CTXSW_CNT0
-#define GDS_PS0_CTXSW_CNT0__UPDN__SHIFT 0x0
-#define GDS_PS0_CTXSW_CNT0__PTR__SHIFT 0x10
-#define GDS_PS0_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
-#define GDS_PS0_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
-//GDS_PS0_CTXSW_CNT1
-#define GDS_PS0_CTXSW_CNT1__UPDN__SHIFT 0x0
-#define GDS_PS0_CTXSW_CNT1__PTR__SHIFT 0x10
-#define GDS_PS0_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
-#define GDS_PS0_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
-//GDS_PS0_CTXSW_CNT2
-#define GDS_PS0_CTXSW_CNT2__UPDN__SHIFT 0x0
-#define GDS_PS0_CTXSW_CNT2__PTR__SHIFT 0x10
-#define GDS_PS0_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
-#define GDS_PS0_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
-//GDS_PS0_CTXSW_CNT3
-#define GDS_PS0_CTXSW_CNT3__UPDN__SHIFT 0x0
-#define GDS_PS0_CTXSW_CNT3__PTR__SHIFT 0x10
-#define GDS_PS0_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
-#define GDS_PS0_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
-//GDS_PS1_CTXSW_CNT0
-#define GDS_PS1_CTXSW_CNT0__UPDN__SHIFT 0x0
-#define GDS_PS1_CTXSW_CNT0__PTR__SHIFT 0x10
-#define GDS_PS1_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
-#define GDS_PS1_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
-//GDS_PS1_CTXSW_CNT1
-#define GDS_PS1_CTXSW_CNT1__UPDN__SHIFT 0x0
-#define GDS_PS1_CTXSW_CNT1__PTR__SHIFT 0x10
-#define GDS_PS1_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
-#define GDS_PS1_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
-//GDS_PS1_CTXSW_CNT2
-#define GDS_PS1_CTXSW_CNT2__UPDN__SHIFT 0x0
-#define GDS_PS1_CTXSW_CNT2__PTR__SHIFT 0x10
-#define GDS_PS1_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
-#define GDS_PS1_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
-//GDS_PS1_CTXSW_CNT3
-#define GDS_PS1_CTXSW_CNT3__UPDN__SHIFT 0x0
-#define GDS_PS1_CTXSW_CNT3__PTR__SHIFT 0x10
-#define GDS_PS1_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
-#define GDS_PS1_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
-//GDS_PS2_CTXSW_CNT0
-#define GDS_PS2_CTXSW_CNT0__UPDN__SHIFT 0x0
-#define GDS_PS2_CTXSW_CNT0__PTR__SHIFT 0x10
-#define GDS_PS2_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
-#define GDS_PS2_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
-//GDS_PS2_CTXSW_CNT1
-#define GDS_PS2_CTXSW_CNT1__UPDN__SHIFT 0x0
-#define GDS_PS2_CTXSW_CNT1__PTR__SHIFT 0x10
-#define GDS_PS2_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
-#define GDS_PS2_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
-//GDS_PS2_CTXSW_CNT2
-#define GDS_PS2_CTXSW_CNT2__UPDN__SHIFT 0x0
-#define GDS_PS2_CTXSW_CNT2__PTR__SHIFT 0x10
-#define GDS_PS2_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
-#define GDS_PS2_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
-//GDS_PS2_CTXSW_CNT3
-#define GDS_PS2_CTXSW_CNT3__UPDN__SHIFT 0x0
-#define GDS_PS2_CTXSW_CNT3__PTR__SHIFT 0x10
-#define GDS_PS2_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
-#define GDS_PS2_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
-//GDS_PS3_CTXSW_CNT0
-#define GDS_PS3_CTXSW_CNT0__UPDN__SHIFT 0x0
-#define GDS_PS3_CTXSW_CNT0__PTR__SHIFT 0x10
-#define GDS_PS3_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
-#define GDS_PS3_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
-//GDS_PS3_CTXSW_CNT1
-#define GDS_PS3_CTXSW_CNT1__UPDN__SHIFT 0x0
-#define GDS_PS3_CTXSW_CNT1__PTR__SHIFT 0x10
-#define GDS_PS3_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
-#define GDS_PS3_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
-//GDS_PS3_CTXSW_CNT2
-#define GDS_PS3_CTXSW_CNT2__UPDN__SHIFT 0x0
-#define GDS_PS3_CTXSW_CNT2__PTR__SHIFT 0x10
-#define GDS_PS3_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
-#define GDS_PS3_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
-//GDS_PS3_CTXSW_CNT3
-#define GDS_PS3_CTXSW_CNT3__UPDN__SHIFT 0x0
-#define GDS_PS3_CTXSW_CNT3__PTR__SHIFT 0x10
-#define GDS_PS3_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
-#define GDS_PS3_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
-//GDS_PS4_CTXSW_CNT0
-#define GDS_PS4_CTXSW_CNT0__UPDN__SHIFT 0x0
-#define GDS_PS4_CTXSW_CNT0__PTR__SHIFT 0x10
-#define GDS_PS4_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
-#define GDS_PS4_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
-//GDS_PS4_CTXSW_CNT1
-#define GDS_PS4_CTXSW_CNT1__UPDN__SHIFT 0x0
-#define GDS_PS4_CTXSW_CNT1__PTR__SHIFT 0x10
-#define GDS_PS4_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
-#define GDS_PS4_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
-//GDS_PS4_CTXSW_CNT2
-#define GDS_PS4_CTXSW_CNT2__UPDN__SHIFT 0x0
-#define GDS_PS4_CTXSW_CNT2__PTR__SHIFT 0x10
-#define GDS_PS4_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
-#define GDS_PS4_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
-//GDS_PS4_CTXSW_CNT3
-#define GDS_PS4_CTXSW_CNT3__UPDN__SHIFT 0x0
-#define GDS_PS4_CTXSW_CNT3__PTR__SHIFT 0x10
-#define GDS_PS4_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
-#define GDS_PS4_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
-//GDS_PS5_CTXSW_CNT0
-#define GDS_PS5_CTXSW_CNT0__UPDN__SHIFT 0x0
-#define GDS_PS5_CTXSW_CNT0__PTR__SHIFT 0x10
-#define GDS_PS5_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
-#define GDS_PS5_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
-//GDS_PS5_CTXSW_CNT1
-#define GDS_PS5_CTXSW_CNT1__UPDN__SHIFT 0x0
-#define GDS_PS5_CTXSW_CNT1__PTR__SHIFT 0x10
-#define GDS_PS5_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
-#define GDS_PS5_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
-//GDS_PS5_CTXSW_CNT2
-#define GDS_PS5_CTXSW_CNT2__UPDN__SHIFT 0x0
-#define GDS_PS5_CTXSW_CNT2__PTR__SHIFT 0x10
-#define GDS_PS5_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
-#define GDS_PS5_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
-//GDS_PS5_CTXSW_CNT3
-#define GDS_PS5_CTXSW_CNT3__UPDN__SHIFT 0x0
-#define GDS_PS5_CTXSW_CNT3__PTR__SHIFT 0x10
-#define GDS_PS5_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
-#define GDS_PS5_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
-//GDS_PS6_CTXSW_CNT0
-#define GDS_PS6_CTXSW_CNT0__UPDN__SHIFT 0x0
-#define GDS_PS6_CTXSW_CNT0__PTR__SHIFT 0x10
-#define GDS_PS6_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
-#define GDS_PS6_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
-//GDS_PS6_CTXSW_CNT1
-#define GDS_PS6_CTXSW_CNT1__UPDN__SHIFT 0x0
-#define GDS_PS6_CTXSW_CNT1__PTR__SHIFT 0x10
-#define GDS_PS6_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
-#define GDS_PS6_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
-//GDS_PS6_CTXSW_CNT2
-#define GDS_PS6_CTXSW_CNT2__UPDN__SHIFT 0x0
-#define GDS_PS6_CTXSW_CNT2__PTR__SHIFT 0x10
-#define GDS_PS6_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
-#define GDS_PS6_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
-//GDS_PS6_CTXSW_CNT3
-#define GDS_PS6_CTXSW_CNT3__UPDN__SHIFT 0x0
-#define GDS_PS6_CTXSW_CNT3__PTR__SHIFT 0x10
-#define GDS_PS6_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
-#define GDS_PS6_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
-//GDS_PS7_CTXSW_CNT0
-#define GDS_PS7_CTXSW_CNT0__UPDN__SHIFT 0x0
-#define GDS_PS7_CTXSW_CNT0__PTR__SHIFT 0x10
-#define GDS_PS7_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
-#define GDS_PS7_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
-//GDS_PS7_CTXSW_CNT1
-#define GDS_PS7_CTXSW_CNT1__UPDN__SHIFT 0x0
-#define GDS_PS7_CTXSW_CNT1__PTR__SHIFT 0x10
-#define GDS_PS7_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
-#define GDS_PS7_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
-//GDS_PS7_CTXSW_CNT2
-#define GDS_PS7_CTXSW_CNT2__UPDN__SHIFT 0x0
-#define GDS_PS7_CTXSW_CNT2__PTR__SHIFT 0x10
-#define GDS_PS7_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
-#define GDS_PS7_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
-//GDS_PS7_CTXSW_CNT3
-#define GDS_PS7_CTXSW_CNT3__UPDN__SHIFT 0x0
-#define GDS_PS7_CTXSW_CNT3__PTR__SHIFT 0x10
-#define GDS_PS7_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
-#define GDS_PS7_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
-//GDS_GS_CTXSW_CNT0
-#define GDS_GS_CTXSW_CNT0__UPDN__SHIFT 0x0
-#define GDS_GS_CTXSW_CNT0__PTR__SHIFT 0x10
-#define GDS_GS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
-#define GDS_GS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
-//GDS_GS_CTXSW_CNT1
-#define GDS_GS_CTXSW_CNT1__UPDN__SHIFT 0x0
-#define GDS_GS_CTXSW_CNT1__PTR__SHIFT 0x10
-#define GDS_GS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
-#define GDS_GS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
-//GDS_GS_CTXSW_CNT2
-#define GDS_GS_CTXSW_CNT2__UPDN__SHIFT 0x0
-#define GDS_GS_CTXSW_CNT2__PTR__SHIFT 0x10
-#define GDS_GS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
-#define GDS_GS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
-//GDS_GS_CTXSW_CNT3
-#define GDS_GS_CTXSW_CNT3__UPDN__SHIFT 0x0
-#define GDS_GS_CTXSW_CNT3__PTR__SHIFT 0x10
-#define GDS_GS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
-#define GDS_GS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
-
-
-// addressBlock: gc_rasdec
-//RAS_SIGNATURE_CONTROL
-#define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT 0x0
-#define RAS_SIGNATURE_CONTROL__ENABLE_MASK 0x00000001L
-//RAS_SIGNATURE_MASK
-#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT 0x0
-#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK 0xFFFFFFFFL
-//RAS_SX_SIGNATURE0
-#define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT 0x0
-#define RAS_SX_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_SX_SIGNATURE1
-#define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT 0x0
-#define RAS_SX_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_SX_SIGNATURE2
-#define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT 0x0
-#define RAS_SX_SIGNATURE2__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_SX_SIGNATURE3
-#define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT 0x0
-#define RAS_SX_SIGNATURE3__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_DB_SIGNATURE0
-#define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT 0x0
-#define RAS_DB_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_PA_SIGNATURE0
-#define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT 0x0
-#define RAS_PA_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_VGT_SIGNATURE0
-#define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT 0x0
-#define RAS_VGT_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_SQ_SIGNATURE0
-#define RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT 0x0
-#define RAS_SQ_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_SC_SIGNATURE0
-#define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT 0x0
-#define RAS_SC_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_SC_SIGNATURE1
-#define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT 0x0
-#define RAS_SC_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_SC_SIGNATURE2
-#define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT 0x0
-#define RAS_SC_SIGNATURE2__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_SC_SIGNATURE3
-#define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT 0x0
-#define RAS_SC_SIGNATURE3__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_SC_SIGNATURE4
-#define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT 0x0
-#define RAS_SC_SIGNATURE4__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_SC_SIGNATURE5
-#define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT 0x0
-#define RAS_SC_SIGNATURE5__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_SC_SIGNATURE6
-#define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT 0x0
-#define RAS_SC_SIGNATURE6__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_SC_SIGNATURE7
-#define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT 0x0
-#define RAS_SC_SIGNATURE7__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_IA_SIGNATURE0
-#define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT 0x0
-#define RAS_IA_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_IA_SIGNATURE1
-#define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT 0x0
-#define RAS_IA_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_SPI_SIGNATURE0
-#define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT 0x0
-#define RAS_SPI_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_SPI_SIGNATURE1
-#define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT 0x0
-#define RAS_SPI_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_TA_SIGNATURE0
-#define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT 0x0
-#define RAS_TA_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_TD_SIGNATURE0
-#define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT 0x0
-#define RAS_TD_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_CB_SIGNATURE0
-#define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT 0x0
-#define RAS_CB_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_BCI_SIGNATURE0
-#define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT 0x0
-#define RAS_BCI_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_BCI_SIGNATURE1
-#define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT 0x0
-#define RAS_BCI_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL
-//RAS_TA_SIGNATURE1
-#define RAS_TA_SIGNATURE1__SIGNATURE__SHIFT 0x0
-#define RAS_TA_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL
-
-
-// addressBlock: gc_gfxdec0
-//DB_RENDER_CONTROL
-#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0
-#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1
-#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2
-#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3
-#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4
-#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5
-#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6
-#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7
-#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8
-#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT 0xc
-#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x00000001L
-#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x00000002L
-#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x00000004L
-#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x00000008L
-#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x00000010L
-#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x00000020L
-#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x00000040L
-#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x00000080L
-#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0x00000F00L
-#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK 0x00001000L
-//DB_COUNT_CONTROL
-#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0
-#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1
-#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4
-#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8
-#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc
-#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10
-#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14
-#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18
-#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c
-#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x00000001L
-#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x00000002L
-#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x00000070L
-#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0x00000F00L
-#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0x0000F000L
-#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0x000F0000L
-#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0x00F00000L
-#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x0F000000L
-#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xF0000000L
-//DB_DEPTH_VIEW
-#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0
-#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd
-#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18
-#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19
-#define DB_DEPTH_VIEW__MIPID__SHIFT 0x1a
-#define DB_DEPTH_VIEW__SLICE_START_MASK 0x000007FFL
-#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0x00FFE000L
-#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x01000000L
-#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x02000000L
-#define DB_DEPTH_VIEW__MIPID_MASK 0x3C000000L
-//DB_RENDER_OVERRIDE
-#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0
-#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2
-#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4
-#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6
-#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7
-#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8
-#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9
-#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa
-#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb
-#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc
-#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd
-#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf
-#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10
-#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11
-#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12
-#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13
-#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15
-#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a
-#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b
-#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c
-#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d
-#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e
-#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f
-#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x00000003L
-#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0x0000000CL
-#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x00000030L
-#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x00000040L
-#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x00000080L
-#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x00000100L
-#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x00000200L
-#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x00000400L
-#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x00000800L
-#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x00001000L
-#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x00006000L
-#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x00008000L
-#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x00010000L
-#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x00020000L
-#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x00040000L
-#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x00180000L
-#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x03E00000L
-#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x04000000L
-#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x08000000L
-#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000L
-#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000L
-#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000L
-#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000L
-//DB_RENDER_OVERRIDE2
-#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0
-#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2
-#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5
-#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6
-#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7
-#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8
-#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9
-#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa
-#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb
-#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc
-#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf
-#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12
-#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15
-#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16
-#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17
-#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL__SHIFT 0x19
-#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x00000003L
-#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x0000001CL
-#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x00000020L
-#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x00000040L
-#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x00000080L
-#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x00000100L
-#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x00000200L
-#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x00000400L
-#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x00000800L
-#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x00007000L
-#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x00038000L
-#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x001C0000L
-#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x00200000L
-#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x00400000L
-#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x00800000L
-#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL_MASK 0x02000000L
-//DB_HTILE_DATA_BASE
-#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0
-#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//DB_HTILE_DATA_BASE_HI
-#define DB_HTILE_DATA_BASE_HI__BASE_HI__SHIFT 0x0
-#define DB_HTILE_DATA_BASE_HI__BASE_HI_MASK 0x000000FFL
-//DB_DEPTH_SIZE
-#define DB_DEPTH_SIZE__X_MAX__SHIFT 0x0
-#define DB_DEPTH_SIZE__Y_MAX__SHIFT 0x10
-#define DB_DEPTH_SIZE__X_MAX_MASK 0x00003FFFL
-#define DB_DEPTH_SIZE__Y_MAX_MASK 0x3FFF0000L
-//DB_DEPTH_BOUNDS_MIN
-#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0
-#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xFFFFFFFFL
-//DB_DEPTH_BOUNDS_MAX
-#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0
-#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xFFFFFFFFL
-//DB_STENCIL_CLEAR
-#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0
-#define DB_STENCIL_CLEAR__CLEAR_MASK 0x000000FFL
-//DB_DEPTH_CLEAR
-#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0
-#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xFFFFFFFFL
-//PA_SC_SCREEN_SCISSOR_TL
-#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0
-#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10
-#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0x0000FFFFL
-#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xFFFF0000L
-//PA_SC_SCREEN_SCISSOR_BR
-#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0
-#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10
-#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0x0000FFFFL
-#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xFFFF0000L
-//DB_Z_INFO
-#define DB_Z_INFO__FORMAT__SHIFT 0x0
-#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2
-#define DB_Z_INFO__SW_MODE__SHIFT 0x4
-#define DB_Z_INFO__PARTIALLY_RESIDENT__SHIFT 0xc
-#define DB_Z_INFO__FAULT_BEHAVIOR__SHIFT 0xd
-#define DB_Z_INFO__ITERATE_FLUSH__SHIFT 0xf
-#define DB_Z_INFO__MAXMIP__SHIFT 0x10
-#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT 0x17
-#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
-#define DB_Z_INFO__READ_SIZE__SHIFT 0x1c
-#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d
-#define DB_Z_INFO__CLEAR_DISALLOWED__SHIFT 0x1e
-#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f
-#define DB_Z_INFO__FORMAT_MASK 0x00000003L
-#define DB_Z_INFO__NUM_SAMPLES_MASK 0x0000000CL
-#define DB_Z_INFO__SW_MODE_MASK 0x000001F0L
-#define DB_Z_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L
-#define DB_Z_INFO__FAULT_BEHAVIOR_MASK 0x00006000L
-#define DB_Z_INFO__ITERATE_FLUSH_MASK 0x00008000L
-#define DB_Z_INFO__MAXMIP_MASK 0x000F0000L
-#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK 0x07800000L
-#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L
-#define DB_Z_INFO__READ_SIZE_MASK 0x10000000L
-#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000L
-#define DB_Z_INFO__CLEAR_DISALLOWED_MASK 0x40000000L
-#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000L
-//DB_STENCIL_INFO
-#define DB_STENCIL_INFO__FORMAT__SHIFT 0x0
-#define DB_STENCIL_INFO__SW_MODE__SHIFT 0x4
-#define DB_STENCIL_INFO__PARTIALLY_RESIDENT__SHIFT 0xc
-#define DB_STENCIL_INFO__FAULT_BEHAVIOR__SHIFT 0xd
-#define DB_STENCIL_INFO__ITERATE_FLUSH__SHIFT 0xf
-#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
-#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d
-#define DB_STENCIL_INFO__CLEAR_DISALLOWED__SHIFT 0x1e
-#define DB_STENCIL_INFO__FORMAT_MASK 0x00000001L
-#define DB_STENCIL_INFO__SW_MODE_MASK 0x000001F0L
-#define DB_STENCIL_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L
-#define DB_STENCIL_INFO__FAULT_BEHAVIOR_MASK 0x00006000L
-#define DB_STENCIL_INFO__ITERATE_FLUSH_MASK 0x00008000L
-#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L
-#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000L
-#define DB_STENCIL_INFO__CLEAR_DISALLOWED_MASK 0x40000000L
-//DB_Z_READ_BASE
-#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0
-#define DB_Z_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//DB_Z_READ_BASE_HI
-#define DB_Z_READ_BASE_HI__BASE_HI__SHIFT 0x0
-#define DB_Z_READ_BASE_HI__BASE_HI_MASK 0x000000FFL
-//DB_STENCIL_READ_BASE
-#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0
-#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//DB_STENCIL_READ_BASE_HI
-#define DB_STENCIL_READ_BASE_HI__BASE_HI__SHIFT 0x0
-#define DB_STENCIL_READ_BASE_HI__BASE_HI_MASK 0x000000FFL
-//DB_Z_WRITE_BASE
-#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0
-#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//DB_Z_WRITE_BASE_HI
-#define DB_Z_WRITE_BASE_HI__BASE_HI__SHIFT 0x0
-#define DB_Z_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL
-//DB_STENCIL_WRITE_BASE
-#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0
-#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//DB_STENCIL_WRITE_BASE_HI
-#define DB_STENCIL_WRITE_BASE_HI__BASE_HI__SHIFT 0x0
-#define DB_STENCIL_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL
-//DB_DFSM_CONTROL
-#define DB_DFSM_CONTROL__PUNCHOUT_MODE__SHIFT 0x0
-#define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP__SHIFT 0x2
-#define DB_DFSM_CONTROL__DISALLOW_OVERFLOW__SHIFT 0x3
-#define DB_DFSM_CONTROL__PUNCHOUT_MODE_MASK 0x00000003L
-#define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP_MASK 0x00000004L
-#define DB_DFSM_CONTROL__DISALLOW_OVERFLOW_MASK 0x00000008L
-//DB_Z_INFO2
-#define DB_Z_INFO2__EPITCH__SHIFT 0x0
-#define DB_Z_INFO2__EPITCH_MASK 0x0000FFFFL
-//DB_STENCIL_INFO2
-#define DB_STENCIL_INFO2__EPITCH__SHIFT 0x0
-#define DB_STENCIL_INFO2__EPITCH_MASK 0x0000FFFFL
-//TA_BC_BASE_ADDR
-#define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x0
-#define TA_BC_BASE_ADDR__ADDRESS_MASK 0xFFFFFFFFL
-//TA_BC_BASE_ADDR_HI
-#define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0
-#define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL
-//COHER_DEST_BASE_HI_0
-#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0
-#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0x000000FFL
-//COHER_DEST_BASE_HI_1
-#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0
-#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0x000000FFL
-//COHER_DEST_BASE_HI_2
-#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0
-#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0x000000FFL
-//COHER_DEST_BASE_HI_3
-#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0
-#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0x000000FFL
-//COHER_DEST_BASE_2
-#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0
-#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xFFFFFFFFL
-//COHER_DEST_BASE_3
-#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0
-#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xFFFFFFFFL
-//PA_SC_WINDOW_OFFSET
-#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0
-#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10
-#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0x0000FFFFL
-#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xFFFF0000L
-//PA_SC_WINDOW_SCISSOR_TL
-#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0
-#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10
-#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L
-#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
-//PA_SC_WINDOW_SCISSOR_BR
-#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0
-#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10
-#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_CLIPRECT_RULE
-#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0
-#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0x0000FFFFL
-//PA_SC_CLIPRECT_0_TL
-#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0
-#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10
-#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7FFF0000L
-//PA_SC_CLIPRECT_0_BR
-#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0
-#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10
-#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_CLIPRECT_1_TL
-#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0
-#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10
-#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7FFF0000L
-//PA_SC_CLIPRECT_1_BR
-#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0
-#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10
-#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_CLIPRECT_2_TL
-#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0
-#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10
-#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7FFF0000L
-//PA_SC_CLIPRECT_2_BR
-#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0
-#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10
-#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_CLIPRECT_3_TL
-#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0
-#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10
-#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7FFF0000L
-//PA_SC_CLIPRECT_3_BR
-#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0
-#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10
-#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_EDGERULE
-#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0
-#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4
-#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8
-#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc
-#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12
-#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18
-#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c
-#define PA_SC_EDGERULE__ER_TRI_MASK 0x0000000FL
-#define PA_SC_EDGERULE__ER_POINT_MASK 0x000000F0L
-#define PA_SC_EDGERULE__ER_RECT_MASK 0x00000F00L
-#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x0003F000L
-#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0x00FC0000L
-#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0x0F000000L
-#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xF0000000L
-//PA_SU_HARDWARE_SCREEN_OFFSET
-#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0
-#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10
-#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x000001FFL
-#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x01FF0000L
-//CB_TARGET_MASK
-#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0
-#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4
-#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8
-#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc
-#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10
-#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14
-#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18
-#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c
-#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0x0000000FL
-#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0x000000F0L
-#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0x00000F00L
-#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0x0000F000L
-#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0x000F0000L
-#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0x00F00000L
-#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0x0F000000L
-#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xF0000000L
-//CB_SHADER_MASK
-#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0
-#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4
-#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8
-#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc
-#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10
-#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14
-#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18
-#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c
-#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0x0000000FL
-#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0x000000F0L
-#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0x00000F00L
-#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0x0000F000L
-#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0x000F0000L
-#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0x00F00000L
-#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0x0F000000L
-#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xF0000000L
-//PA_SC_GENERIC_SCISSOR_TL
-#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0
-#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10
-#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L
-#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
-//PA_SC_GENERIC_SCISSOR_BR
-#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0
-#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10
-#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L
-//COHER_DEST_BASE_0
-#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0
-#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xFFFFFFFFL
-//COHER_DEST_BASE_1
-#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0
-#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_SCISSOR_0_TL
-#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7FFF0000L
-#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
-//PA_SC_VPORT_SCISSOR_0_BR
-#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_VPORT_SCISSOR_1_TL
-#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7FFF0000L
-#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
-//PA_SC_VPORT_SCISSOR_1_BR
-#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_VPORT_SCISSOR_2_TL
-#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7FFF0000L
-#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
-//PA_SC_VPORT_SCISSOR_2_BR
-#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_VPORT_SCISSOR_3_TL
-#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7FFF0000L
-#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
-//PA_SC_VPORT_SCISSOR_3_BR
-#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_VPORT_SCISSOR_4_TL
-#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7FFF0000L
-#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
-//PA_SC_VPORT_SCISSOR_4_BR
-#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_VPORT_SCISSOR_5_TL
-#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7FFF0000L
-#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
-//PA_SC_VPORT_SCISSOR_5_BR
-#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_VPORT_SCISSOR_6_TL
-#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7FFF0000L
-#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
-//PA_SC_VPORT_SCISSOR_6_BR
-#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_VPORT_SCISSOR_7_TL
-#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7FFF0000L
-#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
-//PA_SC_VPORT_SCISSOR_7_BR
-#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_VPORT_SCISSOR_8_TL
-#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7FFF0000L
-#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
-//PA_SC_VPORT_SCISSOR_8_BR
-#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_VPORT_SCISSOR_9_TL
-#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7FFF0000L
-#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
-//PA_SC_VPORT_SCISSOR_9_BR
-#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_VPORT_SCISSOR_10_TL
-#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7FFF0000L
-#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
-//PA_SC_VPORT_SCISSOR_10_BR
-#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_VPORT_SCISSOR_11_TL
-#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7FFF0000L
-#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
-//PA_SC_VPORT_SCISSOR_11_BR
-#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_VPORT_SCISSOR_12_TL
-#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7FFF0000L
-#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
-//PA_SC_VPORT_SCISSOR_12_BR
-#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_VPORT_SCISSOR_13_TL
-#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7FFF0000L
-#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
-//PA_SC_VPORT_SCISSOR_13_BR
-#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_VPORT_SCISSOR_14_TL
-#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7FFF0000L
-#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
-//PA_SC_VPORT_SCISSOR_14_BR
-#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_VPORT_SCISSOR_15_TL
-#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7FFF0000L
-#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
-//PA_SC_VPORT_SCISSOR_15_BR
-#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x00007FFFL
-#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7FFF0000L
-//PA_SC_VPORT_ZMIN_0
-#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMAX_0
-#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMIN_1
-#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMAX_1
-#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMIN_2
-#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMAX_2
-#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMIN_3
-#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMAX_3
-#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMIN_4
-#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMAX_4
-#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMIN_5
-#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMAX_5
-#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMIN_6
-#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMAX_6
-#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMIN_7
-#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMAX_7
-#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMIN_8
-#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMAX_8
-#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMIN_9
-#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMAX_9
-#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMIN_10
-#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMAX_10
-#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMIN_11
-#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMAX_11
-#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMIN_12
-#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMAX_12
-#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMIN_13
-#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMAX_13
-#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMIN_14
-#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMAX_14
-#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMIN_15
-#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xFFFFFFFFL
-//PA_SC_VPORT_ZMAX_15
-#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xFFFFFFFFL
-//PA_SC_RASTER_CONFIG
-#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0
-#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2
-#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4
-#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6
-#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7
-#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8
-#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa
-#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc
-#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe
-#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10
-#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12
-#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14
-#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18
-#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a
-#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1d
-#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x00000003L
-#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0x0000000CL
-#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x00000030L
-#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x00000040L
-#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x00000080L
-#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x00000300L
-#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0x00000C00L
-#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x00003000L
-#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0x0000C000L
-#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x00030000L
-#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0x000C0000L
-#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x00300000L
-#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x03000000L
-#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0x1C000000L
-#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0xE0000000L
-//PA_SC_RASTER_CONFIG_1
-#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0
-#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2
-#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x5
-#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x00000003L
-#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0x0000001CL
-#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x000000E0L
-//PA_SC_SCREEN_EXTENT_CONTROL
-#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0
-#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2
-#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x00000003L
-#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0x0000000CL
-//PA_SC_TILE_STEERING_OVERRIDE
-#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT 0x0
-#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE__SHIFT 0x1
-#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE__SHIFT 0x5
-#define PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING__SHIFT 0x8
-#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK 0x00000001L
-#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE_MASK 0x00000006L
-#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE_MASK 0x00000060L
-#define PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING_MASK 0x00000100L
-//CP_PERFMON_CNTX_CNTL
-#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f
-#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000L
-//CP_PIPEID
-#define CP_PIPEID__PIPE_ID__SHIFT 0x0
-#define CP_PIPEID__PIPE_ID_MASK 0x00000003L
-//CP_RINGID
-#define CP_RINGID__RINGID__SHIFT 0x0
-#define CP_RINGID__RINGID_MASK 0x00000003L
-//CP_VMID
-#define CP_VMID__VMID__SHIFT 0x0
-#define CP_VMID__VMID_MASK 0x0000000FL
-//PA_SC_RIGHT_VERT_GRID
-#define PA_SC_RIGHT_VERT_GRID__LEFT_QTR__SHIFT 0x0
-#define PA_SC_RIGHT_VERT_GRID__LEFT_HALF__SHIFT 0x8
-#define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF__SHIFT 0x10
-#define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR__SHIFT 0x18
-#define PA_SC_RIGHT_VERT_GRID__LEFT_QTR_MASK 0x000000FFL
-#define PA_SC_RIGHT_VERT_GRID__LEFT_HALF_MASK 0x0000FF00L
-#define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF_MASK 0x00FF0000L
-#define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR_MASK 0xFF000000L
-//PA_SC_LEFT_VERT_GRID
-#define PA_SC_LEFT_VERT_GRID__LEFT_QTR__SHIFT 0x0
-#define PA_SC_LEFT_VERT_GRID__LEFT_HALF__SHIFT 0x8
-#define PA_SC_LEFT_VERT_GRID__RIGHT_HALF__SHIFT 0x10
-#define PA_SC_LEFT_VERT_GRID__RIGHT_QTR__SHIFT 0x18
-#define PA_SC_LEFT_VERT_GRID__LEFT_QTR_MASK 0x000000FFL
-#define PA_SC_LEFT_VERT_GRID__LEFT_HALF_MASK 0x0000FF00L
-#define PA_SC_LEFT_VERT_GRID__RIGHT_HALF_MASK 0x00FF0000L
-#define PA_SC_LEFT_VERT_GRID__RIGHT_QTR_MASK 0xFF000000L
-//PA_SC_HORIZ_GRID
-#define PA_SC_HORIZ_GRID__TOP_QTR__SHIFT 0x0
-#define PA_SC_HORIZ_GRID__TOP_HALF__SHIFT 0x8
-#define PA_SC_HORIZ_GRID__BOT_HALF__SHIFT 0x10
-#define PA_SC_HORIZ_GRID__BOT_QTR__SHIFT 0x18
-#define PA_SC_HORIZ_GRID__TOP_QTR_MASK 0x000000FFL
-#define PA_SC_HORIZ_GRID__TOP_HALF_MASK 0x0000FF00L
-#define PA_SC_HORIZ_GRID__BOT_HALF_MASK 0x00FF0000L
-#define PA_SC_HORIZ_GRID__BOT_QTR_MASK 0xFF000000L
-//VGT_MULTI_PRIM_IB_RESET_INDX
-#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0
-#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xFFFFFFFFL
-//CB_BLEND_RED
-#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
-#define CB_BLEND_RED__BLEND_RED_MASK 0xFFFFFFFFL
-//CB_BLEND_GREEN
-#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
-#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xFFFFFFFFL
-//CB_BLEND_BLUE
-#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
-#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xFFFFFFFFL
-//CB_BLEND_ALPHA
-#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
-#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xFFFFFFFFL
-//CB_DCC_CONTROL
-#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
-#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE__SHIFT 0x1
-#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT 0x2
-#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
-#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE_MASK 0x00000002L
-#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK 0x0000007CL
-//DB_STENCIL_CONTROL
-#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0
-#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4
-#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8
-#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc
-#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10
-#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14
-#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0x0000000FL
-#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0x000000F0L
-#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0x00000F00L
-#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0x0000F000L
-#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0x000F0000L
-#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0x00F00000L
-//DB_STENCILREFMASK
-#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0
-#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8
-#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10
-#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18
-#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0x000000FFL
-#define DB_STENCILREFMASK__STENCILMASK_MASK 0x0000FF00L
-#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0x00FF0000L
-#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xFF000000L
-//DB_STENCILREFMASK_BF
-#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0
-#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8
-#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10
-#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18
-#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0x000000FFL
-#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0x0000FF00L
-#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0x00FF0000L
-#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xFF000000L
-//PA_CL_VPORT_XSCALE
-#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XOFFSET
-#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YSCALE
-#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YOFFSET
-#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZSCALE
-#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZOFFSET
-#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XSCALE_1
-#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XOFFSET_1
-#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YSCALE_1
-#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YOFFSET_1
-#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZSCALE_1
-#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZOFFSET_1
-#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XSCALE_2
-#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XOFFSET_2
-#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YSCALE_2
-#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YOFFSET_2
-#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZSCALE_2
-#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZOFFSET_2
-#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XSCALE_3
-#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XOFFSET_3
-#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YSCALE_3
-#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YOFFSET_3
-#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZSCALE_3
-#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZOFFSET_3
-#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XSCALE_4
-#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XOFFSET_4
-#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YSCALE_4
-#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YOFFSET_4
-#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZSCALE_4
-#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZOFFSET_4
-#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XSCALE_5
-#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XOFFSET_5
-#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YSCALE_5
-#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YOFFSET_5
-#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZSCALE_5
-#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZOFFSET_5
-#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XSCALE_6
-#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XOFFSET_6
-#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YSCALE_6
-#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YOFFSET_6
-#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZSCALE_6
-#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZOFFSET_6
-#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XSCALE_7
-#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XOFFSET_7
-#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YSCALE_7
-#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YOFFSET_7
-#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZSCALE_7
-#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZOFFSET_7
-#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XSCALE_8
-#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XOFFSET_8
-#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YSCALE_8
-#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YOFFSET_8
-#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZSCALE_8
-#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZOFFSET_8
-#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XSCALE_9
-#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XOFFSET_9
-#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YSCALE_9
-#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YOFFSET_9
-#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZSCALE_9
-#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZOFFSET_9
-#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XSCALE_10
-#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XOFFSET_10
-#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YSCALE_10
-#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YOFFSET_10
-#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZSCALE_10
-#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZOFFSET_10
-#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XSCALE_11
-#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XOFFSET_11
-#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YSCALE_11
-#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YOFFSET_11
-#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZSCALE_11
-#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZOFFSET_11
-#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XSCALE_12
-#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XOFFSET_12
-#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YSCALE_12
-#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YOFFSET_12
-#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZSCALE_12
-#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZOFFSET_12
-#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XSCALE_13
-#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XOFFSET_13
-#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YSCALE_13
-#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YOFFSET_13
-#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZSCALE_13
-#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZOFFSET_13
-#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XSCALE_14
-#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XOFFSET_14
-#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YSCALE_14
-#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YOFFSET_14
-#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZSCALE_14
-#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZOFFSET_14
-#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XSCALE_15
-#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_XOFFSET_15
-#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YSCALE_15
-#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_YOFFSET_15
-#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZSCALE_15
-#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xFFFFFFFFL
-//PA_CL_VPORT_ZOFFSET_15
-#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
-//PA_CL_UCP_0_X
-#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_0_Y
-#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_0_Z
-#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_0_W
-#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_1_X
-#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_1_Y
-#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_1_Z
-#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_1_W
-#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_2_X
-#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_2_Y
-#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_2_Z
-#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_2_W
-#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_3_X
-#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_3_Y
-#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_3_Z
-#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_3_W
-#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_4_X
-#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_4_Y
-#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_4_Z
-#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_4_W
-#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_5_X
-#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_5_Y
-#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_5_Z
-#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_UCP_5_W
-#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xFFFFFFFFL
-//SPI_PS_INPUT_CNTL_0
-#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_1
-#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_2
-#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_3
-#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_4
-#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_5
-#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_6
-#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_7
-#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_8
-#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_9
-#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_10
-#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_11
-#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_12
-#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_13
-#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_14
-#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_15
-#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_16
-#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_17
-#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_18
-#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_19
-#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x0001E000L
-#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x00020000L
-#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
-#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_20
-#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_21
-#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_22
-#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_23
-#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_24
-#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_25
-#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_26
-#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_27
-#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_28
-#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_29
-#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_30
-#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK 0x02000000L
-//SPI_PS_INPUT_CNTL_31
-#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x0000003FL
-#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x00000300L
-#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x00000400L
-#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x00040000L
-#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK 0x00080000L
-#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK 0x00100000L
-#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK 0x00600000L
-#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK 0x01000000L
-#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK 0x02000000L
-//SPI_VS_OUT_CONFIG
-#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1
-#define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x6
-#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x0000003EL
-#define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x00000040L
-//SPI_PS_INPUT_ENA
-#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0
-#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1
-#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2
-#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3
-#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4
-#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5
-#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6
-#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7
-#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8
-#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9
-#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa
-#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb
-#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc
-#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd
-#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe
-#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf
-#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x00000001L
-#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x00000002L
-#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x00000004L
-#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x00000008L
-#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x00000010L
-#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x00000020L
-#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x00000040L
-#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L
-#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x00000100L
-#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x00000200L
-#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x00000400L
-#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x00000800L
-#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x00001000L
-#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x00002000L
-#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x00004000L
-#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x00008000L
-//SPI_PS_INPUT_ADDR
-#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0
-#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1
-#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2
-#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3
-#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4
-#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5
-#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6
-#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7
-#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8
-#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9
-#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa
-#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb
-#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc
-#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd
-#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe
-#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf
-#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x00000001L
-#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x00000002L
-#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x00000004L
-#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x00000008L
-#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x00000010L
-#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x00000020L
-#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x00000040L
-#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L
-#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x00000100L
-#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x00000200L
-#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x00000400L
-#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x00000800L
-#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x00001000L
-#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x00002000L
-#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x00004000L
-#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x00008000L
-//SPI_INTERP_CONTROL_0
-#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0
-#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1
-#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2
-#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5
-#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8
-#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb
-#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe
-#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x00000001L
-#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x00000002L
-#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x0000001CL
-#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0x000000E0L
-#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x00000700L
-#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x00003800L
-#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x00004000L
-//SPI_PS_IN_CONTROL
-#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0
-#define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x6
-#define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN__SHIFT 0x7
-#define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC__SHIFT 0x8
-#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe
-#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x0000003FL
-#define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x00000040L
-#define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN_MASK 0x00000080L
-#define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC_MASK 0x00000100L
-#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x00004000L
-//SPI_BARYC_CNTL
-#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0
-#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4
-#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8
-#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc
-#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10
-#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14
-#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18
-#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x00000001L
-#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x00000010L
-#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x00000100L
-#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x00001000L
-#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x00030000L
-#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x00100000L
-#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x01000000L
-//SPI_TMPRING_SIZE
-#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0
-#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc
-#define SPI_TMPRING_SIZE__WAVES_MASK 0x00000FFFL
-#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x01FFF000L
-//SPI_SHADER_POS_FORMAT
-#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0
-#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4
-#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8
-#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc
-#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0x0000000FL
-#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0x000000F0L
-#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0x00000F00L
-#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0x0000F000L
-//SPI_SHADER_Z_FORMAT
-#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0
-#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0x0000000FL
-//SPI_SHADER_COL_FORMAT
-#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0
-#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4
-#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8
-#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc
-#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10
-#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14
-#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18
-#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c
-#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0x0000000FL
-#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0x000000F0L
-#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0x00000F00L
-#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0x0000F000L
-#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0x000F0000L
-#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0x00F00000L
-#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0x0F000000L
-#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xF0000000L
-//SX_PS_DOWNCONVERT
-#define SX_PS_DOWNCONVERT__MRT0__SHIFT 0x0
-#define SX_PS_DOWNCONVERT__MRT1__SHIFT 0x4
-#define SX_PS_DOWNCONVERT__MRT2__SHIFT 0x8
-#define SX_PS_DOWNCONVERT__MRT3__SHIFT 0xc
-#define SX_PS_DOWNCONVERT__MRT4__SHIFT 0x10
-#define SX_PS_DOWNCONVERT__MRT5__SHIFT 0x14
-#define SX_PS_DOWNCONVERT__MRT6__SHIFT 0x18
-#define SX_PS_DOWNCONVERT__MRT7__SHIFT 0x1c
-#define SX_PS_DOWNCONVERT__MRT0_MASK 0x0000000FL
-#define SX_PS_DOWNCONVERT__MRT1_MASK 0x000000F0L
-#define SX_PS_DOWNCONVERT__MRT2_MASK 0x00000F00L
-#define SX_PS_DOWNCONVERT__MRT3_MASK 0x0000F000L
-#define SX_PS_DOWNCONVERT__MRT4_MASK 0x000F0000L
-#define SX_PS_DOWNCONVERT__MRT5_MASK 0x00F00000L
-#define SX_PS_DOWNCONVERT__MRT6_MASK 0x0F000000L
-#define SX_PS_DOWNCONVERT__MRT7_MASK 0xF0000000L
-//SX_BLEND_OPT_EPSILON
-#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON__SHIFT 0x0
-#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON__SHIFT 0x4
-#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON__SHIFT 0x8
-#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON__SHIFT 0xc
-#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON__SHIFT 0x10
-#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON__SHIFT 0x14
-#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON__SHIFT 0x18
-#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON__SHIFT 0x1c
-#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON_MASK 0x0000000FL
-#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON_MASK 0x000000F0L
-#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON_MASK 0x00000F00L
-#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON_MASK 0x0000F000L
-#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON_MASK 0x000F0000L
-#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON_MASK 0x00F00000L
-#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON_MASK 0x0F000000L
-#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON_MASK 0xF0000000L
-//SX_BLEND_OPT_CONTROL
-#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE__SHIFT 0x0
-#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE__SHIFT 0x1
-#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE__SHIFT 0x4
-#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE__SHIFT 0x5
-#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE__SHIFT 0x8
-#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE__SHIFT 0x9
-#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE__SHIFT 0xc
-#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE__SHIFT 0xd
-#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE__SHIFT 0x10
-#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE__SHIFT 0x11
-#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE__SHIFT 0x14
-#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE__SHIFT 0x15
-#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE__SHIFT 0x18
-#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE__SHIFT 0x19
-#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE__SHIFT 0x1c
-#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE__SHIFT 0x1d
-#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE__SHIFT 0x1f
-#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE_MASK 0x00000001L
-#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE_MASK 0x00000002L
-#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE_MASK 0x00000010L
-#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE_MASK 0x00000020L
-#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE_MASK 0x00000100L
-#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE_MASK 0x00000200L
-#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE_MASK 0x00001000L
-#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE_MASK 0x00002000L
-#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE_MASK 0x00010000L
-#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE_MASK 0x00020000L
-#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE_MASK 0x00100000L
-#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE_MASK 0x00200000L
-#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE_MASK 0x01000000L
-#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE_MASK 0x02000000L
-#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE_MASK 0x10000000L
-#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE_MASK 0x20000000L
-#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE_MASK 0x80000000L
-//SX_MRT0_BLEND_OPT
-#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
-#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
-#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
-#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
-#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
-#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
-#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
-#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
-#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
-#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
-#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
-#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
-//SX_MRT1_BLEND_OPT
-#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
-#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
-#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
-#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
-#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
-#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
-#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
-#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
-#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
-#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
-#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
-#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
-//SX_MRT2_BLEND_OPT
-#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
-#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
-#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
-#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
-#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
-#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
-#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
-#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
-#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
-#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
-#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
-#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
-//SX_MRT3_BLEND_OPT
-#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
-#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
-#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
-#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
-#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
-#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
-#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
-#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
-#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
-#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
-#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
-#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
-//SX_MRT4_BLEND_OPT
-#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
-#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
-#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
-#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
-#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
-#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
-#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
-#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
-#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
-#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
-#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
-#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
-//SX_MRT5_BLEND_OPT
-#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
-#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
-#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
-#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
-#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
-#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
-#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
-#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
-#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
-#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
-#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
-#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
-//SX_MRT6_BLEND_OPT
-#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
-#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
-#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
-#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
-#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
-#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
-#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
-#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
-#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
-#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
-#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
-#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
-//SX_MRT7_BLEND_OPT
-#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
-#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
-#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
-#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
-#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
-#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
-#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
-#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
-#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
-#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
-#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
-#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
-//CB_BLEND0_CONTROL
-#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
-#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
-#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
-#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
-#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
-#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
-#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
-#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e
-#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f
-#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
-#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
-#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
-#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
-#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
-#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
-#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
-#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000L
-#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000L
-//CB_BLEND1_CONTROL
-#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
-#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
-#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
-#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
-#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
-#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
-#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
-#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e
-#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f
-#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
-#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
-#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
-#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
-#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
-#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
-#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
-#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000L
-#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000L
-//CB_BLEND2_CONTROL
-#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
-#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
-#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
-#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
-#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
-#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
-#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
-#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e
-#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f
-#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
-#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
-#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
-#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
-#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
-#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
-#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
-#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000L
-#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000L
-//CB_BLEND3_CONTROL
-#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
-#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
-#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
-#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
-#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
-#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
-#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
-#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e
-#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f
-#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
-#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
-#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
-#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
-#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
-#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
-#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
-#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000L
-#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000L
-//CB_BLEND4_CONTROL
-#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
-#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
-#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
-#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
-#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
-#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
-#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
-#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e
-#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f
-#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
-#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
-#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
-#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
-#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
-#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
-#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
-#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000L
-#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000L
-//CB_BLEND5_CONTROL
-#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
-#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
-#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
-#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
-#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
-#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
-#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
-#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e
-#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f
-#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
-#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
-#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
-#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
-#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
-#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
-#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
-#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000L
-#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000L
-//CB_BLEND6_CONTROL
-#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
-#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
-#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
-#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
-#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
-#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
-#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
-#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e
-#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f
-#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
-#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
-#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
-#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
-#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
-#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
-#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
-#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000L
-#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000L
-//CB_BLEND7_CONTROL
-#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
-#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
-#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
-#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
-#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
-#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
-#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
-#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e
-#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f
-#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
-#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
-#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
-#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
-#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
-#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
-#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
-#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000L
-#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000L
-//CB_MRT0_EPITCH
-#define CB_MRT0_EPITCH__EPITCH__SHIFT 0x0
-#define CB_MRT0_EPITCH__EPITCH_MASK 0x0000FFFFL
-//CB_MRT1_EPITCH
-#define CB_MRT1_EPITCH__EPITCH__SHIFT 0x0
-#define CB_MRT1_EPITCH__EPITCH_MASK 0x0000FFFFL
-//CB_MRT2_EPITCH
-#define CB_MRT2_EPITCH__EPITCH__SHIFT 0x0
-#define CB_MRT2_EPITCH__EPITCH_MASK 0x0000FFFFL
-//CB_MRT3_EPITCH
-#define CB_MRT3_EPITCH__EPITCH__SHIFT 0x0
-#define CB_MRT3_EPITCH__EPITCH_MASK 0x0000FFFFL
-//CB_MRT4_EPITCH
-#define CB_MRT4_EPITCH__EPITCH__SHIFT 0x0
-#define CB_MRT4_EPITCH__EPITCH_MASK 0x0000FFFFL
-//CB_MRT5_EPITCH
-#define CB_MRT5_EPITCH__EPITCH__SHIFT 0x0
-#define CB_MRT5_EPITCH__EPITCH_MASK 0x0000FFFFL
-//CB_MRT6_EPITCH
-#define CB_MRT6_EPITCH__EPITCH__SHIFT 0x0
-#define CB_MRT6_EPITCH__EPITCH_MASK 0x0000FFFFL
-//CB_MRT7_EPITCH
-#define CB_MRT7_EPITCH__EPITCH__SHIFT 0x0
-#define CB_MRT7_EPITCH__EPITCH_MASK 0x0000FFFFL
-//CS_COPY_STATE
-#define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
-#define CS_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L
-//GFX_COPY_STATE
-#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
-#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L
-//PA_CL_POINT_X_RAD
-#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_POINT_Y_RAD
-#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_POINT_SIZE
-#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_POINT_CULL_RAD
-#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL
-//VGT_DMA_BASE_HI
-#define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x0
-#define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0x0000FFFFL
-//VGT_DMA_BASE
-#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x0
-#define VGT_DMA_BASE__BASE_ADDR_MASK 0xFFFFFFFFL
-//VGT_DRAW_INITIATOR
-#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x0
-#define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x2
-#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x4
-#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x5
-#define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x6
-#define VGT_DRAW_INITIATOR__UNROLLED_INST__SHIFT 0x7
-#define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC__SHIFT 0x8
-#define VGT_DRAW_INITIATOR__REG_RT_INDEX__SHIFT 0x1d
-#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x00000003L
-#define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0x0000000CL
-#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x00000010L
-#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x00000020L
-#define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x00000040L
-#define VGT_DRAW_INITIATOR__UNROLLED_INST_MASK 0x00000080L
-#define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC_MASK 0x00000100L
-#define VGT_DRAW_INITIATOR__REG_RT_INDEX_MASK 0xE0000000L
-//VGT_IMMED_DATA
-#define VGT_IMMED_DATA__DATA__SHIFT 0x0
-#define VGT_IMMED_DATA__DATA_MASK 0xFFFFFFFFL
-//VGT_EVENT_ADDRESS_REG
-#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x0
-#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0x0FFFFFFFL
-//DB_DEPTH_CONTROL
-#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0
-#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1
-#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2
-#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3
-#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4
-#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7
-#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8
-#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14
-#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e
-#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f
-#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x00000001L
-#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x00000002L
-#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x00000004L
-#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x00000008L
-#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x00000070L
-#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x00000080L
-#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x00000700L
-#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x00700000L
-#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000L
-#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000L
-//DB_EQAA
-#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0
-#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4
-#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8
-#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc
-#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10
-#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11
-#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12
-#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13
-#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14
-#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15
-#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18
-#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b
-#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x00000007L
-#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x00000070L
-#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x00000700L
-#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x00007000L
-#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x00010000L
-#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x00020000L
-#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x00040000L
-#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x00080000L
-#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x00100000L
-#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x00200000L
-#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x07000000L
-#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x08000000L
-//CB_COLOR_CONTROL
-#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD__SHIFT 0x0
-#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
-#define CB_COLOR_CONTROL__MODE__SHIFT 0x4
-#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10
-#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD_MASK 0x00000001L
-#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x00000008L
-#define CB_COLOR_CONTROL__MODE_MASK 0x00000070L
-#define CB_COLOR_CONTROL__ROP3_MASK 0x00FF0000L
-//DB_SHADER_CONTROL
-#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0
-#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1
-#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2
-#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4
-#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6
-#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7
-#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8
-#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9
-#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa
-#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb
-#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc
-#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd
-#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT 0xf
-#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER__SHIFT 0x10
-#define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED__SHIFT 0x11
-#define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES__SHIFT 0x14
-#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x00000001L
-#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x00000002L
-#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x00000004L
-#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x00000030L
-#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x00000040L
-#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x00000080L
-#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x00000100L
-#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x00000200L
-#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x00000400L
-#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x00000800L
-#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x00001000L
-#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x00006000L
-#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK 0x00008000L
-#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER_MASK 0x00010000L
-#define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED_MASK 0x00020000L
-#define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES_MASK 0x00700000L
-//PA_CL_CLIP_CNTL
-#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0
-#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1
-#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2
-#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3
-#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4
-#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5
-#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd
-#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe
-#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10
-#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11
-#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12
-#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13
-#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14
-#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15
-#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16
-#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18
-#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19
-#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a
-#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b
-#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x00000001L
-#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x00000002L
-#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x00000004L
-#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x00000008L
-#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x00000010L
-#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x00000020L
-#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x00002000L
-#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0x0000C000L
-#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x00010000L
-#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x00020000L
-#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000L
-#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x00080000L
-#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x00100000L
-#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x00200000L
-#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x00400000L
-#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x01000000L
-#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x02000000L
-#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x04000000L
-#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x08000000L
-//PA_SU_SC_MODE_CNTL
-#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0
-#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1
-#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2
-#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3
-#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5
-#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8
-#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb
-#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc
-#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd
-#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10
-#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13
-#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14
-#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15
-#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF__SHIFT 0x16
-#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION__SHIFT 0x17
-#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x00000001L
-#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x00000002L
-#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x00000004L
-#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x00000018L
-#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0x000000E0L
-#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x00000700L
-#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800L
-#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x00001000L
-#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x00002000L
-#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000L
-#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x00080000L
-#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x00100000L
-#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x00200000L
-#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF_MASK 0x00400000L
-#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION_MASK 0x00800000L
-//PA_CL_VTE_CNTL
-#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0
-#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1
-#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2
-#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3
-#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4
-#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5
-#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8
-#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9
-#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa
-#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb
-#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x00000001L
-#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x00000002L
-#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L
-#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x00000008L
-#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x00000010L
-#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x00000020L
-#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100L
-#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200L
-#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x00000400L
-#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x00000800L
-//PA_CL_VS_OUT_CNTL
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf
-#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10
-#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11
-#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12
-#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13
-#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14
-#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15
-#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16
-#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17
-#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18
-#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x19
-#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT 0x1a
-#define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID__SHIFT 0x1b
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x00000001L
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x00000002L
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x00000004L
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x00000008L
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x00000010L
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x00000020L
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x00000040L
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x00000080L
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x00000100L
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x00000200L
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x00000400L
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x00000800L
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x00001000L
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x00002000L
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x00004000L
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x00008000L
-#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x00010000L
-#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x00020000L
-#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x00040000L
-#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x00080000L
-#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x00100000L
-#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x00200000L
-#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x00400000L
-#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x00800000L
-#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x01000000L
-#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x02000000L
-#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK 0x04000000L
-#define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID_MASK 0x08000000L
-//PA_CL_NANINF_CNTL
-#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0
-#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1
-#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2
-#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3
-#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4
-#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5
-#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6
-#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7
-#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8
-#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9
-#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa
-#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb
-#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc
-#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd
-#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe
-#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14
-#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x00000001L
-#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x00000002L
-#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x00000004L
-#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x00000008L
-#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x00000010L
-#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x00000020L
-#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x00000040L
-#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x00000080L
-#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x00000100L
-#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x00000200L
-#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x00000400L
-#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x00000800L
-#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x00001000L
-#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x00002000L
-#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x00004000L
-#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x00100000L
-//PA_SU_LINE_STIPPLE_CNTL
-#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0
-#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2
-#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3
-#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x4
-#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x00000003L
-#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x00000004L
-#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x00000008L
-#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x00000010L
-//PA_SU_LINE_STIPPLE_SCALE
-#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0
-#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xFFFFFFFFL
-//PA_SU_PRIM_FILTER_CNTL
-#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0
-#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1
-#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2
-#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3
-#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4
-#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5
-#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6
-#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7
-#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8
-#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e
-#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f
-#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000001L
-#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000002L
-#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000004L
-#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000008L
-#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x00000010L
-#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x00000020L
-#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x00000040L
-#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x00000080L
-#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0x0000FF00L
-#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000L
-#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000L
-//PA_SU_SMALL_PRIM_FILTER_CNTL
-#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE__SHIFT 0x0
-#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x1
-#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x2
-#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x3
-#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x4
-#define PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE__SHIFT 0x5
-#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK 0x00000001L
-#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000002L
-#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000004L
-#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000008L
-#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000010L
-#define PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE_MASK 0x00000020L
-//PA_CL_OBJPRIM_ID_CNTL
-#define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL__SHIFT 0x0
-#define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID__SHIFT 0x1
-#define PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID__SHIFT 0x2
-#define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL_MASK 0x00000001L
-#define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID_MASK 0x00000002L
-#define PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID_MASK 0x00000004L
-//PA_CL_NGG_CNTL
-#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF__SHIFT 0x0
-#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA__SHIFT 0x1
-#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF_MASK 0x00000001L
-#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA_MASK 0x00000002L
-//PA_SU_OVER_RASTERIZATION_CNTL
-#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES__SHIFT 0x0
-#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES__SHIFT 0x1
-#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS__SHIFT 0x2
-#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES__SHIFT 0x3
-#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW__SHIFT 0x4
-#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES_MASK 0x00000001L
-#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES_MASK 0x00000002L
-#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS_MASK 0x00000004L
-#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES_MASK 0x00000008L
-#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW_MASK 0x00000010L
-//PA_SU_POINT_SIZE
-#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0
-#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10
-#define PA_SU_POINT_SIZE__HEIGHT_MASK 0x0000FFFFL
-#define PA_SU_POINT_SIZE__WIDTH_MASK 0xFFFF0000L
-//PA_SU_POINT_MINMAX
-#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0
-#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10
-#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0x0000FFFFL
-#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xFFFF0000L
-//PA_SU_LINE_CNTL
-#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0
-#define PA_SU_LINE_CNTL__WIDTH_MASK 0x0000FFFFL
-//PA_SC_LINE_STIPPLE
-#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0
-#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10
-#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c
-#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d
-#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0x0000FFFFL
-#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0x00FF0000L
-#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000L
-#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000L
-//VGT_OUTPUT_PATH_CNTL
-#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x0
-#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x00000007L
-//VGT_HOS_CNTL
-#define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x0
-#define VGT_HOS_CNTL__TESS_MODE_MASK 0x00000003L
-//VGT_HOS_MAX_TESS_LEVEL
-#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x0
-#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xFFFFFFFFL
-//VGT_HOS_MIN_TESS_LEVEL
-#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x0
-#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xFFFFFFFFL
-//VGT_HOS_REUSE_DEPTH
-#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x0
-#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0x000000FFL
-//VGT_GROUP_PRIM_TYPE
-#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x0
-#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0xe
-#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0xf
-#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x10
-#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x0000001FL
-#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x00004000L
-#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x00008000L
-#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x00070000L
-//VGT_GROUP_FIRST_DECR
-#define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x0
-#define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0x0000000FL
-//VGT_GROUP_DECR
-#define VGT_GROUP_DECR__DECR__SHIFT 0x0
-#define VGT_GROUP_DECR__DECR_MASK 0x0000000FL
-//VGT_GROUP_VECT_0_CNTL
-#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x0
-#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x1
-#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x2
-#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x3
-#define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x8
-#define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x10
-#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x00000001L
-#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x00000002L
-#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x00000004L
-#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x00000008L
-#define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0x0000FF00L
-#define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0x00FF0000L
-//VGT_GROUP_VECT_1_CNTL
-#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x0
-#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x1
-#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x2
-#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x3
-#define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x8
-#define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x10
-#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x00000001L
-#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x00000002L
-#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x00000004L
-#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x00000008L
-#define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0x0000FF00L
-#define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0x00FF0000L
-//VGT_GROUP_VECT_0_FMT_CNTL
-#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x0
-#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x4
-#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x8
-#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0xc
-#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x10
-#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x14
-#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x18
-#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x1c
-#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0x0000000FL
-#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0x000000F0L
-#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0x00000F00L
-#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0x0000F000L
-#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0x000F0000L
-#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0x00F00000L
-#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0x0F000000L
-#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xF0000000L
-//VGT_GROUP_VECT_1_FMT_CNTL
-#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x0
-#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x4
-#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x8
-#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0xc
-#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x10
-#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x14
-#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x18
-#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x1c
-#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0x0000000FL
-#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0x000000F0L
-#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0x00000F00L
-#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0x0000F000L
-#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0x000F0000L
-#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0x00F00000L
-#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0x0F000000L
-#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xF0000000L
-//VGT_GS_MODE
-#define VGT_GS_MODE__MODE__SHIFT 0x0
-#define VGT_GS_MODE__RESERVED_0__SHIFT 0x3
-#define VGT_GS_MODE__CUT_MODE__SHIFT 0x4
-#define VGT_GS_MODE__RESERVED_1__SHIFT 0x6
-#define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0xb
-#define VGT_GS_MODE__RESERVED_2__SHIFT 0xc
-#define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0xd
-#define VGT_GS_MODE__RESERVED_3__SHIFT 0xe
-#define VGT_GS_MODE__RESERVED_4__SHIFT 0xf
-#define VGT_GS_MODE__RESERVED_5__SHIFT 0x10
-#define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x11
-#define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x12
-#define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x13
-#define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x14
-#define VGT_GS_MODE__ONCHIP__SHIFT 0x15
-#define VGT_GS_MODE__MODE_MASK 0x00000007L
-#define VGT_GS_MODE__RESERVED_0_MASK 0x00000008L
-#define VGT_GS_MODE__CUT_MODE_MASK 0x00000030L
-#define VGT_GS_MODE__RESERVED_1_MASK 0x000007C0L
-#define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x00000800L
-#define VGT_GS_MODE__RESERVED_2_MASK 0x00001000L
-#define VGT_GS_MODE__ES_PASSTHRU_MASK 0x00002000L
-#define VGT_GS_MODE__RESERVED_3_MASK 0x00004000L
-#define VGT_GS_MODE__RESERVED_4_MASK 0x00008000L
-#define VGT_GS_MODE__RESERVED_5_MASK 0x00010000L
-#define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x00020000L
-#define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x00040000L
-#define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x00080000L
-#define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x00100000L
-#define VGT_GS_MODE__ONCHIP_MASK 0x00600000L
-//VGT_GS_ONCHIP_CNTL
-#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT 0x0
-#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT 0xb
-#define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP__SHIFT 0x16
-#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK 0x000007FFL
-#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK 0x003FF800L
-#define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP_MASK 0xFFC00000L
-//PA_SC_MODE_CNTL_0
-#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0
-#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1
-#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2
-#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3
-#define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD__SHIFT 0x4
-#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE__SHIFT 0x5
-#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB__SHIFT 0x6
-#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x00000001L
-#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x00000002L
-#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x00000004L
-#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x00000008L
-#define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD_MASK 0x00000010L
-#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE_MASK 0x00000020L
-#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB_MASK 0x00000040L
-//PA_SC_MODE_CNTL_1
-#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0
-#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1
-#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2
-#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3
-#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4
-#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7
-#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8
-#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9
-#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa
-#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb
-#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc
-#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd
-#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe
-#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf
-#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10
-#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11
-#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12
-#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13
-#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14
-#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18
-#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19
-#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a
-#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b
-#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c
-#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x00000001L
-#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x00000002L
-#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x00000004L
-#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x00000008L
-#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x00000070L
-#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x00000080L
-#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x00000100L
-#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x00000200L
-#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x00000400L
-#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x00000800L
-#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x00001000L
-#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x00002000L
-#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x00004000L
-#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x00008000L
-#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x00010000L
-#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x00020000L
-#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x00040000L
-#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x00080000L
-#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0x00F00000L
-#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x01000000L
-#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x02000000L
-#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x04000000L
-#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x08000000L
-#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000L
-//VGT_ENHANCE
-#define VGT_ENHANCE__MISC__SHIFT 0x0
-#define VGT_ENHANCE__MISC_MASK 0xFFFFFFFFL
-//VGT_GS_PER_ES
-#define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x0
-#define VGT_GS_PER_ES__GS_PER_ES_MASK 0x000007FFL
-//VGT_ES_PER_GS
-#define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x0
-#define VGT_ES_PER_GS__ES_PER_GS_MASK 0x000007FFL
-//VGT_GS_PER_VS
-#define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x0
-#define VGT_GS_PER_VS__GS_PER_VS_MASK 0x0000000FL
-//VGT_GSVS_RING_OFFSET_1
-#define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x0
-#define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x00007FFFL
-//VGT_GSVS_RING_OFFSET_2
-#define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x0
-#define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x00007FFFL
-//VGT_GSVS_RING_OFFSET_3
-#define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x0
-#define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x00007FFFL
-//VGT_GS_OUT_PRIM_TYPE
-#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x0
-#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x8
-#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x10
-#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x16
-#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x1f
-#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x0000003FL
-#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x00003F00L
-#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x003F0000L
-#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0x0FC00000L
-#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000L
-//IA_ENHANCE
-#define IA_ENHANCE__MISC__SHIFT 0x0
-#define IA_ENHANCE__MISC_MASK 0xFFFFFFFFL
-//VGT_DMA_SIZE
-#define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x0
-#define VGT_DMA_SIZE__NUM_INDICES_MASK 0xFFFFFFFFL
-//VGT_DMA_MAX_SIZE
-#define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x0
-#define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xFFFFFFFFL
-//VGT_DMA_INDEX_TYPE
-#define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
-#define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x2
-#define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x4
-#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x6
-#define VGT_DMA_INDEX_TYPE__PRIMGEN_EN__SHIFT 0x8
-#define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x9
-#define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa
-#define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L
-#define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0x0000000CL
-#define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x00000030L
-#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0x00000040L
-#define VGT_DMA_INDEX_TYPE__PRIMGEN_EN_MASK 0x00000100L
-#define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x00000200L
-#define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x00000400L
-//WD_ENHANCE
-#define WD_ENHANCE__MISC__SHIFT 0x0
-#define WD_ENHANCE__MISC_MASK 0xFFFFFFFFL
-//VGT_PRIMITIVEID_EN
-#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x0
-#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x1
-#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE__SHIFT 0x2
-#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x00000001L
-#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x00000002L
-#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE_MASK 0x00000004L
-//VGT_DMA_NUM_INSTANCES
-#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0
-#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL
-//VGT_PRIMITIVEID_RESET
-#define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x0
-#define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xFFFFFFFFL
-//VGT_EVENT_INITIATOR
-#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0
-#define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa
-#define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b
-#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL
-#define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L
-#define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L
-//VGT_GS_MAX_PRIMS_PER_SUBGROUP
-#define VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP__SHIFT 0x0
-#define VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP_MASK 0x0000FFFFL
-//VGT_DRAW_PAYLOAD_CNTL
-#define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN__SHIFT 0x0
-#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX__SHIFT 0x1
-#define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID__SHIFT 0x2
-#define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN__SHIFT 0x3
-#define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN_MASK 0x00000001L
-#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK 0x00000002L
-#define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID_MASK 0x00000004L
-#define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN_MASK 0x00000008L
-//VGT_INSTANCE_STEP_RATE_0
-#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0
-#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xFFFFFFFFL
-//VGT_INSTANCE_STEP_RATE_1
-#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x0
-#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xFFFFFFFFL
-//VGT_ESGS_RING_ITEMSIZE
-#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0
-#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL
-//VGT_GSVS_RING_ITEMSIZE
-#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0
-#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL
-//VGT_REUSE_OFF
-#define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x0
-#define VGT_REUSE_OFF__REUSE_OFF_MASK 0x00000001L
-//VGT_VTX_CNT_EN
-#define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x0
-#define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x00000001L
-//DB_HTILE_SURFACE
-#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1
-#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x2
-#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x3
-#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x4
-#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0xa
-#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10
-#define DB_HTILE_SURFACE__PIPE_ALIGNED__SHIFT 0x12
-#define DB_HTILE_SURFACE__RB_ALIGNED__SHIFT 0x13
-#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x00000002L
-#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x00000004L
-#define DB_HTILE_SURFACE__PRELOAD_MASK 0x00000008L
-#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x000003F0L
-#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0x0000FC00L
-#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x00010000L
-#define DB_HTILE_SURFACE__PIPE_ALIGNED_MASK 0x00040000L
-#define DB_HTILE_SURFACE__RB_ALIGNED_MASK 0x00080000L
-//DB_SRESULTS_COMPARE_STATE0
-#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0
-#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4
-#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc
-#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18
-#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x00000007L
-#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0x00000FF0L
-#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0x000FF000L
-#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x01000000L
-//DB_SRESULTS_COMPARE_STATE1
-#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0
-#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4
-#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc
-#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18
-#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x00000007L
-#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0x00000FF0L
-#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0x000FF000L
-#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x01000000L
-//DB_PRELOAD_CONTROL
-#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0
-#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8
-#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10
-#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18
-#define DB_PRELOAD_CONTROL__START_X_MASK 0x000000FFL
-#define DB_PRELOAD_CONTROL__START_Y_MASK 0x0000FF00L
-#define DB_PRELOAD_CONTROL__MAX_X_MASK 0x00FF0000L
-#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xFF000000L
-//VGT_STRMOUT_BUFFER_SIZE_0
-#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xFFFFFFFFL
-//VGT_STRMOUT_VTX_STRIDE_0
-#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x0
-#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x000003FFL
-//VGT_STRMOUT_BUFFER_OFFSET_0
-#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xFFFFFFFFL
-//VGT_STRMOUT_BUFFER_SIZE_1
-#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xFFFFFFFFL
-//VGT_STRMOUT_VTX_STRIDE_1
-#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x0
-#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x000003FFL
-//VGT_STRMOUT_BUFFER_OFFSET_1
-#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xFFFFFFFFL
-//VGT_STRMOUT_BUFFER_SIZE_2
-#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xFFFFFFFFL
-//VGT_STRMOUT_VTX_STRIDE_2
-#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x0
-#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x000003FFL
-//VGT_STRMOUT_BUFFER_OFFSET_2
-#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xFFFFFFFFL
-//VGT_STRMOUT_BUFFER_SIZE_3
-#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xFFFFFFFFL
-//VGT_STRMOUT_VTX_STRIDE_3
-#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x0
-#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x000003FFL
-//VGT_STRMOUT_BUFFER_OFFSET_3
-#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xFFFFFFFFL
-//VGT_STRMOUT_DRAW_OPAQUE_OFFSET
-#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x0
-#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xFFFFFFFFL
-//VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
-#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x0
-#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xFFFFFFFFL
-//VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
-#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x0
-#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x000001FFL
-//VGT_GS_MAX_VERT_OUT
-#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x0
-#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x000007FFL
-//VGT_TESS_DISTRIBUTION
-#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT 0x0
-#define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT 0x8
-#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT 0x10
-#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT 0x18
-#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT__SHIFT 0x1d
-#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK 0x000000FFL
-#define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK 0x0000FF00L
-#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0x00FF0000L
-#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK 0x1F000000L
-#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT_MASK 0xE0000000L
-//VGT_SHADER_STAGES_EN
-#define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x0
-#define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x2
-#define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x3
-#define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x5
-#define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x6
-#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT 0x9
-#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT 0xa
-#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT 0xb
-#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT 0xc
-#define VGT_SHADER_STAGES_EN__PRIMGEN_EN__SHIFT 0xd
-#define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE__SHIFT 0xe
-#define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE__SHIFT 0xf
-#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH__SHIFT 0x13
-#define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x00000003L
-#define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x00000004L
-#define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x00000018L
-#define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x00000020L
-#define VGT_SHADER_STAGES_EN__VS_EN_MASK 0x000000C0L
-#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK 0x00000200L
-#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK 0x00000400L
-#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK 0x00000800L
-#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK 0x00001000L
-#define VGT_SHADER_STAGES_EN__PRIMGEN_EN_MASK 0x00002000L
-#define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE_MASK 0x00004000L
-#define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE_MASK 0x00078000L
-#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH_MASK 0x00080000L
-//VGT_LS_HS_CONFIG
-#define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x0
-#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8
-#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0xe
-#define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0x000000FFL
-#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L
-#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0x000FC000L
-//VGT_GS_VERT_ITEMSIZE
-#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x0
-#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL
-//VGT_GS_VERT_ITEMSIZE_1
-#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x0
-#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x00007FFFL
-//VGT_GS_VERT_ITEMSIZE_2
-#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x0
-#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x00007FFFL
-//VGT_GS_VERT_ITEMSIZE_3
-#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x0
-#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x00007FFFL
-//VGT_TF_PARAM
-#define VGT_TF_PARAM__TYPE__SHIFT 0x0
-#define VGT_TF_PARAM__PARTITIONING__SHIFT 0x2
-#define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x5
-#define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT 0x8
-#define VGT_TF_PARAM__DEPRECATED__SHIFT 0x9
-#define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0xe
-#define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0xf
-#define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT 0x11
-#define VGT_TF_PARAM__TYPE_MASK 0x00000003L
-#define VGT_TF_PARAM__PARTITIONING_MASK 0x0000001CL
-#define VGT_TF_PARAM__TOPOLOGY_MASK 0x000000E0L
-#define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK 0x00000100L
-#define VGT_TF_PARAM__DEPRECATED_MASK 0x00000200L
-#define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x00004000L
-#define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x00008000L
-#define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK 0x00060000L
-//DB_ALPHA_TO_MASK
-#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0
-#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8
-#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa
-#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc
-#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe
-#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10
-#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x00000001L
-#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x00000300L
-#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0x00000C00L
-#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x00003000L
-#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0x0000C000L
-#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x00010000L
-//VGT_DISPATCH_DRAW_INDEX
-#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT 0x0
-#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK 0xFFFFFFFFL
-//PA_SU_POLY_OFFSET_DB_FMT_CNTL
-#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0
-#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8
-#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0x000000FFL
-#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x00000100L
-//PA_SU_POLY_OFFSET_CLAMP
-#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0
-#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xFFFFFFFFL
-//PA_SU_POLY_OFFSET_FRONT_SCALE
-#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0
-#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xFFFFFFFFL
-//PA_SU_POLY_OFFSET_FRONT_OFFSET
-#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0
-#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xFFFFFFFFL
-//PA_SU_POLY_OFFSET_BACK_SCALE
-#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0
-#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xFFFFFFFFL
-//PA_SU_POLY_OFFSET_BACK_OFFSET
-#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0
-#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xFFFFFFFFL
-//VGT_GS_INSTANCE_CNT
-#define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x0
-#define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x2
-#define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x00000001L
-#define VGT_GS_INSTANCE_CNT__CNT_MASK 0x000001FCL
-//VGT_STRMOUT_CONFIG
-#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x0
-#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x1
-#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x2
-#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x3
-#define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x4
-#define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT__SHIFT 0x7
-#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x8
-#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x1f
-#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x00000001L
-#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x00000002L
-#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x00000004L
-#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x00000008L
-#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x00000070L
-#define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT_MASK 0x00000080L
-#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0x00000F00L
-#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000L
-//VGT_STRMOUT_BUFFER_CONFIG
-#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x4
-#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x8
-#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0xc
-#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0x0000000FL
-#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0x000000F0L
-#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0x00000F00L
-#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0x0000F000L
-//VGT_DMA_EVENT_INITIATOR
-#define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0
-#define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa
-#define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b
-#define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL
-#define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L
-#define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L
-//PA_SC_CENTROID_PRIORITY_0
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0x0000000FL
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0x000000F0L
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0x00000F00L
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0x0000F000L
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0x000F0000L
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0x00F00000L
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0x0F000000L
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xF0000000L
-//PA_SC_CENTROID_PRIORITY_1
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0x0000000FL
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0x000000F0L
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0x00000F00L
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0x0000F000L
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0x000F0000L
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0x00F00000L
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0x0F000000L
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xF0000000L
-//PA_SC_LINE_CNTL
-#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9
-#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa
-#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb
-#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc
-#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x00000200L
-#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x00000400L
-#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x00000800L
-#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x00001000L
-//PA_SC_AA_CONFIG
-#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0
-#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4
-#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd
-#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14
-#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18
-#define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT__SHIFT 0x1a
-#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x00000007L
-#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x00000010L
-#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x0001E000L
-#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x00700000L
-#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x03000000L
-#define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT_MASK 0x0C000000L
-//PA_SU_VTX_CNTL
-#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0
-#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1
-#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3
-#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x00000001L
-#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x00000006L
-#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x00000038L
-//PA_CL_GB_VERT_CLIP_ADJ
-#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_GB_VERT_DISC_ADJ
-#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_GB_HORZ_CLIP_ADJ
-#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_CL_GB_HORZ_DISC_ADJ
-#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL
-//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0x0000000FL
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0x000000F0L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0x00000F00L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0x0000F000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0x000F0000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0x00F00000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0x0F000000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xF0000000L
-//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0x0000000FL
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0x000000F0L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0x00000F00L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0x0000F000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0x000F0000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0x00F00000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0x0F000000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xF0000000L
-//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0x0000000FL
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0x000000F0L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0x00000F00L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0x0000F000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0x000F0000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0x00F00000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0x0F000000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xF0000000L
-//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0x0000000FL
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0x000000F0L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0x00000F00L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0x0000F000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0x000F0000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0x00F00000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0x0F000000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xF0000000L
-//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0x0000000FL
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0x000000F0L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0x00000F00L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0x0000F000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0x000F0000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0x00F00000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0x0F000000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xF0000000L
-//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0x0000000FL
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0x000000F0L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0x00000F00L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0x0000F000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0x000F0000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0x00F00000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0x0F000000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xF0000000L
-//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0x0000000FL
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0x000000F0L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0x00000F00L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0x0000F000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0x000F0000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0x00F00000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0x0F000000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xF0000000L
-//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0x0000000FL
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0x000000F0L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0x00000F00L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0x0000F000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0x000F0000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0x00F00000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0x0F000000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xF0000000L
-//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0x0000000FL
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0x000000F0L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0x00000F00L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0x0000F000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0x000F0000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0x00F00000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0x0F000000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xF0000000L
-//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0x0000000FL
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0x000000F0L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0x00000F00L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0x0000F000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0x000F0000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0x00F00000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0x0F000000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xF0000000L
-//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0x0000000FL
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0x000000F0L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0x00000F00L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0x0000F000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0x000F0000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0x00F00000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0x0F000000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xF0000000L
-//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0x0000000FL
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0x000000F0L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0x00000F00L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0x0000F000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0x000F0000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0x00F00000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0x0F000000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xF0000000L
-//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0x0000000FL
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0x000000F0L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0x00000F00L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0x0000F000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0x000F0000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0x00F00000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0x0F000000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xF0000000L
-//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0x0000000FL
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0x000000F0L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0x00000F00L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0x0000F000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0x000F0000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0x00F00000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0x0F000000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xF0000000L
-//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0x0000000FL
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0x000000F0L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0x00000F00L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0x0000F000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0x000F0000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0x00F00000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0x0F000000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xF0000000L
-//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0x0000000FL
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0x000000F0L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0x00000F00L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0x0000F000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0x000F0000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0x00F00000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0x0F000000L
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xF0000000L
-//PA_SC_AA_MASK_X0Y0_X1Y0
-#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0
-#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10
-#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0x0000FFFFL
-#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xFFFF0000L
-//PA_SC_AA_MASK_X0Y1_X1Y1
-#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0
-#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10
-#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0x0000FFFFL
-#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xFFFF0000L
-//PA_SC_SHADER_CONTROL
-#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT 0x0
-#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID__SHIFT 0x2
-#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION__SHIFT 0x3
-#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK 0x00000003L
-#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID_MASK 0x00000004L
-#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION_MASK 0x00000008L
-//PA_SC_BINNER_CNTL_0
-#define PA_SC_BINNER_CNTL_0__BINNING_MODE__SHIFT 0x0
-#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X__SHIFT 0x2
-#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y__SHIFT 0x3
-#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND__SHIFT 0x4
-#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND__SHIFT 0x7
-#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN__SHIFT 0xa
-#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN__SHIFT 0xd
-#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM__SHIFT 0x12
-#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT 0x13
-#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION__SHIFT 0x1b
-#define PA_SC_BINNER_CNTL_0__BINNING_MODE_MASK 0x00000003L
-#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_MASK 0x00000004L
-#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_MASK 0x00000008L
-#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND_MASK 0x00000070L
-#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND_MASK 0x00000380L
-#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN_MASK 0x00001C00L
-#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN_MASK 0x0003E000L
-#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM_MASK 0x00040000L
-#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH_MASK 0x07F80000L
-#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION_MASK 0x08000000L
-//PA_SC_BINNER_CNTL_1
-#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT__SHIFT 0x0
-#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH__SHIFT 0x10
-#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT_MASK 0x0000FFFFL
-#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH_MASK 0xFFFF0000L
-//PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE__SHIFT 0x0
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT__SHIFT 0x1
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE__SHIFT 0x5
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT__SHIFT 0x6
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE__SHIFT 0xa
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT__SHIFT 0xb
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET__SHIFT 0xc
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL__SHIFT 0xd
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL__SHIFT 0xe
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE__SHIFT 0xf
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE__SHIFT 0x10
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x12
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x13
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE__SHIFT 0x14
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE__SHIFT 0x15
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE__SHIFT 0x16
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE__SHIFT 0x17
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE__SHIFT 0x18
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE_MASK 0x00000001L
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT_MASK 0x0000001EL
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE_MASK 0x00000020L
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT_MASK 0x000003C0L
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE_MASK 0x00000400L
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT_MASK 0x00000800L
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET_MASK 0x00001000L
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL_MASK 0x00002000L
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL_MASK 0x00004000L
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE_MASK 0x00008000L
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE_MASK 0x00030000L
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00040000L
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00080000L
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE_MASK 0x00100000L
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE_MASK 0x00200000L
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE_MASK 0x00400000L
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE_MASK 0x00800000L
-#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE_MASK 0x01000000L
-//PA_SC_NGG_MODE_CNTL
-#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE__SHIFT 0x0
-#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE_MASK 0x000007FFL
-//VGT_VERTEX_REUSE_BLOCK_CNTL
-#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x0
-#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0x000000FFL
-//VGT_OUT_DEALLOC_CNTL
-#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x0
-#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x0000007FL
-//CB_COLOR0_BASE
-#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR0_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR0_BASE_EXT
-#define CB_COLOR0_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR0_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR0_ATTRIB2
-#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
-#define CB_COLOR0_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
-#define CB_COLOR0_ATTRIB2__MAX_MIP__SHIFT 0x1c
-#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
-#define CB_COLOR0_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
-#define CB_COLOR0_ATTRIB2__MAX_MIP_MASK 0xF0000000L
-//CB_COLOR0_VIEW
-#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0
-#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd
-#define CB_COLOR0_VIEW__MIP_LEVEL__SHIFT 0x18
-#define CB_COLOR0_VIEW__SLICE_START_MASK 0x000007FFL
-#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0x00FFE000L
-#define CB_COLOR0_VIEW__MIP_LEVEL_MASK 0x0F000000L
-//CB_COLOR0_INFO
-#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0
-#define CB_COLOR0_INFO__FORMAT__SHIFT 0x2
-#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8
-#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb
-#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd
-#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe
-#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf
-#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10
-#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11
-#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12
-#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
-#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
-#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
-#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
-#define CB_COLOR0_INFO__DCC_ENABLE__SHIFT 0x1c
-#define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
-#define CB_COLOR0_INFO__ENDIAN_MASK 0x00000003L
-#define CB_COLOR0_INFO__FORMAT_MASK 0x0000007CL
-#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x00000700L
-#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x00001800L
-#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x00002000L
-#define CB_COLOR0_INFO__COMPRESSION_MASK 0x00004000L
-#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x00008000L
-#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x00010000L
-#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x00020000L
-#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x00040000L
-#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
-#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
-#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
-#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
-#define CB_COLOR0_INFO__DCC_ENABLE_MASK 0x10000000L
-#define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
-//CB_COLOR0_ATTRIB
-#define CB_COLOR0_ATTRIB__MIP0_DEPTH__SHIFT 0x0
-#define CB_COLOR0_ATTRIB__META_LINEAR__SHIFT 0xb
-#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc
-#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
-#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
-#define CB_COLOR0_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
-#define CB_COLOR0_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
-#define CB_COLOR0_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
-#define CB_COLOR0_ATTRIB__RB_ALIGNED__SHIFT 0x1e
-#define CB_COLOR0_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
-#define CB_COLOR0_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
-#define CB_COLOR0_ATTRIB__META_LINEAR_MASK 0x00000800L
-#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
-#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
-#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
-#define CB_COLOR0_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
-#define CB_COLOR0_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
-#define CB_COLOR0_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
-#define CB_COLOR0_ATTRIB__RB_ALIGNED_MASK 0x40000000L
-#define CB_COLOR0_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
-//CB_COLOR0_DCC_CONTROL
-#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
-#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
-#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
-#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
-#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
-#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
-#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
-#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
-#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
-#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
-#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
-#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
-#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
-#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
-#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
-#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
-#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
-#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
-//CB_COLOR0_CMASK
-#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR0_CMASK__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR0_CMASK_BASE_EXT
-#define CB_COLOR0_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR0_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR0_FMASK
-#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR0_FMASK__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR0_FMASK_BASE_EXT
-#define CB_COLOR0_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR0_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR0_CLEAR_WORD0
-#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
-#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
-//CB_COLOR0_CLEAR_WORD1
-#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
-#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
-//CB_COLOR0_DCC_BASE
-#define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR0_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR0_DCC_BASE_EXT
-#define CB_COLOR0_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR0_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR1_BASE
-#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR1_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR1_BASE_EXT
-#define CB_COLOR1_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR1_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR1_ATTRIB2
-#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
-#define CB_COLOR1_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
-#define CB_COLOR1_ATTRIB2__MAX_MIP__SHIFT 0x1c
-#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
-#define CB_COLOR1_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
-#define CB_COLOR1_ATTRIB2__MAX_MIP_MASK 0xF0000000L
-//CB_COLOR1_VIEW
-#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0
-#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd
-#define CB_COLOR1_VIEW__MIP_LEVEL__SHIFT 0x18
-#define CB_COLOR1_VIEW__SLICE_START_MASK 0x000007FFL
-#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0x00FFE000L
-#define CB_COLOR1_VIEW__MIP_LEVEL_MASK 0x0F000000L
-//CB_COLOR1_INFO
-#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0
-#define CB_COLOR1_INFO__FORMAT__SHIFT 0x2
-#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8
-#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb
-#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd
-#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe
-#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf
-#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10
-#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11
-#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12
-#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
-#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
-#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
-#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
-#define CB_COLOR1_INFO__DCC_ENABLE__SHIFT 0x1c
-#define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
-#define CB_COLOR1_INFO__ENDIAN_MASK 0x00000003L
-#define CB_COLOR1_INFO__FORMAT_MASK 0x0000007CL
-#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x00000700L
-#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x00001800L
-#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x00002000L
-#define CB_COLOR1_INFO__COMPRESSION_MASK 0x00004000L
-#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x00008000L
-#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x00010000L
-#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x00020000L
-#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x00040000L
-#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
-#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
-#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
-#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
-#define CB_COLOR1_INFO__DCC_ENABLE_MASK 0x10000000L
-#define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
-//CB_COLOR1_ATTRIB
-#define CB_COLOR1_ATTRIB__MIP0_DEPTH__SHIFT 0x0
-#define CB_COLOR1_ATTRIB__META_LINEAR__SHIFT 0xb
-#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc
-#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
-#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
-#define CB_COLOR1_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
-#define CB_COLOR1_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
-#define CB_COLOR1_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
-#define CB_COLOR1_ATTRIB__RB_ALIGNED__SHIFT 0x1e
-#define CB_COLOR1_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
-#define CB_COLOR1_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
-#define CB_COLOR1_ATTRIB__META_LINEAR_MASK 0x00000800L
-#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
-#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
-#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
-#define CB_COLOR1_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
-#define CB_COLOR1_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
-#define CB_COLOR1_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
-#define CB_COLOR1_ATTRIB__RB_ALIGNED_MASK 0x40000000L
-#define CB_COLOR1_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
-//CB_COLOR1_DCC_CONTROL
-#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
-#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
-#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
-#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
-#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
-#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
-#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
-#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
-#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
-#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
-#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
-#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
-#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
-#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
-#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
-#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
-#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
-#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
-//CB_COLOR1_CMASK
-#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR1_CMASK__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR1_CMASK_BASE_EXT
-#define CB_COLOR1_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR1_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR1_FMASK
-#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR1_FMASK__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR1_FMASK_BASE_EXT
-#define CB_COLOR1_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR1_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR1_CLEAR_WORD0
-#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
-#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
-//CB_COLOR1_CLEAR_WORD1
-#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
-#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
-//CB_COLOR1_DCC_BASE
-#define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR1_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR1_DCC_BASE_EXT
-#define CB_COLOR1_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR1_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR2_BASE
-#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR2_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR2_BASE_EXT
-#define CB_COLOR2_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR2_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR2_ATTRIB2
-#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
-#define CB_COLOR2_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
-#define CB_COLOR2_ATTRIB2__MAX_MIP__SHIFT 0x1c
-#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
-#define CB_COLOR2_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
-#define CB_COLOR2_ATTRIB2__MAX_MIP_MASK 0xF0000000L
-//CB_COLOR2_VIEW
-#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0
-#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd
-#define CB_COLOR2_VIEW__MIP_LEVEL__SHIFT 0x18
-#define CB_COLOR2_VIEW__SLICE_START_MASK 0x000007FFL
-#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0x00FFE000L
-#define CB_COLOR2_VIEW__MIP_LEVEL_MASK 0x0F000000L
-//CB_COLOR2_INFO
-#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0
-#define CB_COLOR2_INFO__FORMAT__SHIFT 0x2
-#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8
-#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb
-#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd
-#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe
-#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf
-#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10
-#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11
-#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12
-#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
-#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
-#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
-#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
-#define CB_COLOR2_INFO__DCC_ENABLE__SHIFT 0x1c
-#define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
-#define CB_COLOR2_INFO__ENDIAN_MASK 0x00000003L
-#define CB_COLOR2_INFO__FORMAT_MASK 0x0000007CL
-#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x00000700L
-#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x00001800L
-#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x00002000L
-#define CB_COLOR2_INFO__COMPRESSION_MASK 0x00004000L
-#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x00008000L
-#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x00010000L
-#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x00020000L
-#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x00040000L
-#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
-#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
-#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
-#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
-#define CB_COLOR2_INFO__DCC_ENABLE_MASK 0x10000000L
-#define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
-//CB_COLOR2_ATTRIB
-#define CB_COLOR2_ATTRIB__MIP0_DEPTH__SHIFT 0x0
-#define CB_COLOR2_ATTRIB__META_LINEAR__SHIFT 0xb
-#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc
-#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
-#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
-#define CB_COLOR2_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
-#define CB_COLOR2_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
-#define CB_COLOR2_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
-#define CB_COLOR2_ATTRIB__RB_ALIGNED__SHIFT 0x1e
-#define CB_COLOR2_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
-#define CB_COLOR2_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
-#define CB_COLOR2_ATTRIB__META_LINEAR_MASK 0x00000800L
-#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
-#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
-#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
-#define CB_COLOR2_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
-#define CB_COLOR2_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
-#define CB_COLOR2_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
-#define CB_COLOR2_ATTRIB__RB_ALIGNED_MASK 0x40000000L
-#define CB_COLOR2_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
-//CB_COLOR2_DCC_CONTROL
-#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
-#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
-#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
-#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
-#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
-#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
-#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
-#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
-#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
-#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
-#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
-#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
-#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
-#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
-#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
-#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
-#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
-#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
-//CB_COLOR2_CMASK
-#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR2_CMASK__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR2_CMASK_BASE_EXT
-#define CB_COLOR2_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR2_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR2_FMASK
-#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR2_FMASK__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR2_FMASK_BASE_EXT
-#define CB_COLOR2_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR2_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR2_CLEAR_WORD0
-#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
-#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
-//CB_COLOR2_CLEAR_WORD1
-#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
-#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
-//CB_COLOR2_DCC_BASE
-#define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR2_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR2_DCC_BASE_EXT
-#define CB_COLOR2_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR2_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR3_BASE
-#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR3_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR3_BASE_EXT
-#define CB_COLOR3_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR3_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR3_ATTRIB2
-#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
-#define CB_COLOR3_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
-#define CB_COLOR3_ATTRIB2__MAX_MIP__SHIFT 0x1c
-#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
-#define CB_COLOR3_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
-#define CB_COLOR3_ATTRIB2__MAX_MIP_MASK 0xF0000000L
-//CB_COLOR3_VIEW
-#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0
-#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd
-#define CB_COLOR3_VIEW__MIP_LEVEL__SHIFT 0x18
-#define CB_COLOR3_VIEW__SLICE_START_MASK 0x000007FFL
-#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0x00FFE000L
-#define CB_COLOR3_VIEW__MIP_LEVEL_MASK 0x0F000000L
-//CB_COLOR3_INFO
-#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0
-#define CB_COLOR3_INFO__FORMAT__SHIFT 0x2
-#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8
-#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb
-#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd
-#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe
-#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf
-#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10
-#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11
-#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12
-#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
-#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
-#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
-#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
-#define CB_COLOR3_INFO__DCC_ENABLE__SHIFT 0x1c
-#define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
-#define CB_COLOR3_INFO__ENDIAN_MASK 0x00000003L
-#define CB_COLOR3_INFO__FORMAT_MASK 0x0000007CL
-#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x00000700L
-#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x00001800L
-#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x00002000L
-#define CB_COLOR3_INFO__COMPRESSION_MASK 0x00004000L
-#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x00008000L
-#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x00010000L
-#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x00020000L
-#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x00040000L
-#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
-#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
-#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
-#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
-#define CB_COLOR3_INFO__DCC_ENABLE_MASK 0x10000000L
-#define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
-//CB_COLOR3_ATTRIB
-#define CB_COLOR3_ATTRIB__MIP0_DEPTH__SHIFT 0x0
-#define CB_COLOR3_ATTRIB__META_LINEAR__SHIFT 0xb
-#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc
-#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
-#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
-#define CB_COLOR3_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
-#define CB_COLOR3_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
-#define CB_COLOR3_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
-#define CB_COLOR3_ATTRIB__RB_ALIGNED__SHIFT 0x1e
-#define CB_COLOR3_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
-#define CB_COLOR3_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
-#define CB_COLOR3_ATTRIB__META_LINEAR_MASK 0x00000800L
-#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
-#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
-#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
-#define CB_COLOR3_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
-#define CB_COLOR3_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
-#define CB_COLOR3_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
-#define CB_COLOR3_ATTRIB__RB_ALIGNED_MASK 0x40000000L
-#define CB_COLOR3_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
-//CB_COLOR3_DCC_CONTROL
-#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
-#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
-#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
-#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
-#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
-#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
-#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
-#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
-#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
-#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
-#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
-#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
-#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
-#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
-#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
-#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
-#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
-#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
-//CB_COLOR3_CMASK
-#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR3_CMASK__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR3_CMASK_BASE_EXT
-#define CB_COLOR3_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR3_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR3_FMASK
-#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR3_FMASK__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR3_FMASK_BASE_EXT
-#define CB_COLOR3_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR3_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR3_CLEAR_WORD0
-#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
-#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
-//CB_COLOR3_CLEAR_WORD1
-#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
-#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
-//CB_COLOR3_DCC_BASE
-#define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR3_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR3_DCC_BASE_EXT
-#define CB_COLOR3_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR3_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR4_BASE
-#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR4_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR4_BASE_EXT
-#define CB_COLOR4_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR4_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR4_ATTRIB2
-#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
-#define CB_COLOR4_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
-#define CB_COLOR4_ATTRIB2__MAX_MIP__SHIFT 0x1c
-#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
-#define CB_COLOR4_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
-#define CB_COLOR4_ATTRIB2__MAX_MIP_MASK 0xF0000000L
-//CB_COLOR4_VIEW
-#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0
-#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd
-#define CB_COLOR4_VIEW__MIP_LEVEL__SHIFT 0x18
-#define CB_COLOR4_VIEW__SLICE_START_MASK 0x000007FFL
-#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0x00FFE000L
-#define CB_COLOR4_VIEW__MIP_LEVEL_MASK 0x0F000000L
-//CB_COLOR4_INFO
-#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0
-#define CB_COLOR4_INFO__FORMAT__SHIFT 0x2
-#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8
-#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb
-#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd
-#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe
-#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf
-#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10
-#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11
-#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12
-#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
-#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
-#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
-#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
-#define CB_COLOR4_INFO__DCC_ENABLE__SHIFT 0x1c
-#define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
-#define CB_COLOR4_INFO__ENDIAN_MASK 0x00000003L
-#define CB_COLOR4_INFO__FORMAT_MASK 0x0000007CL
-#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x00000700L
-#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x00001800L
-#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x00002000L
-#define CB_COLOR4_INFO__COMPRESSION_MASK 0x00004000L
-#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x00008000L
-#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x00010000L
-#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x00020000L
-#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x00040000L
-#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
-#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
-#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
-#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
-#define CB_COLOR4_INFO__DCC_ENABLE_MASK 0x10000000L
-#define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
-//CB_COLOR4_ATTRIB
-#define CB_COLOR4_ATTRIB__MIP0_DEPTH__SHIFT 0x0
-#define CB_COLOR4_ATTRIB__META_LINEAR__SHIFT 0xb
-#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc
-#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
-#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
-#define CB_COLOR4_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
-#define CB_COLOR4_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
-#define CB_COLOR4_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
-#define CB_COLOR4_ATTRIB__RB_ALIGNED__SHIFT 0x1e
-#define CB_COLOR4_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
-#define CB_COLOR4_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
-#define CB_COLOR4_ATTRIB__META_LINEAR_MASK 0x00000800L
-#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
-#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
-#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
-#define CB_COLOR4_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
-#define CB_COLOR4_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
-#define CB_COLOR4_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
-#define CB_COLOR4_ATTRIB__RB_ALIGNED_MASK 0x40000000L
-#define CB_COLOR4_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
-//CB_COLOR4_DCC_CONTROL
-#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
-#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
-#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
-#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
-#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
-#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
-#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
-#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
-#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
-#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
-#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
-#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
-#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
-#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
-#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
-#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
-#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
-#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
-//CB_COLOR4_CMASK
-#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR4_CMASK__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR4_CMASK_BASE_EXT
-#define CB_COLOR4_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR4_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR4_FMASK
-#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR4_FMASK__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR4_FMASK_BASE_EXT
-#define CB_COLOR4_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR4_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR4_CLEAR_WORD0
-#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
-#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
-//CB_COLOR4_CLEAR_WORD1
-#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
-#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
-//CB_COLOR4_DCC_BASE
-#define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR4_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR4_DCC_BASE_EXT
-#define CB_COLOR4_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR4_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR5_BASE
-#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR5_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR5_BASE_EXT
-#define CB_COLOR5_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR5_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR5_ATTRIB2
-#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
-#define CB_COLOR5_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
-#define CB_COLOR5_ATTRIB2__MAX_MIP__SHIFT 0x1c
-#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
-#define CB_COLOR5_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
-#define CB_COLOR5_ATTRIB2__MAX_MIP_MASK 0xF0000000L
-//CB_COLOR5_VIEW
-#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0
-#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd
-#define CB_COLOR5_VIEW__MIP_LEVEL__SHIFT 0x18
-#define CB_COLOR5_VIEW__SLICE_START_MASK 0x000007FFL
-#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0x00FFE000L
-#define CB_COLOR5_VIEW__MIP_LEVEL_MASK 0x0F000000L
-//CB_COLOR5_INFO
-#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0
-#define CB_COLOR5_INFO__FORMAT__SHIFT 0x2
-#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8
-#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb
-#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd
-#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe
-#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf
-#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10
-#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11
-#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12
-#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
-#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
-#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
-#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
-#define CB_COLOR5_INFO__DCC_ENABLE__SHIFT 0x1c
-#define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
-#define CB_COLOR5_INFO__ENDIAN_MASK 0x00000003L
-#define CB_COLOR5_INFO__FORMAT_MASK 0x0000007CL
-#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x00000700L
-#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x00001800L
-#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x00002000L
-#define CB_COLOR5_INFO__COMPRESSION_MASK 0x00004000L
-#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x00008000L
-#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x00010000L
-#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x00020000L
-#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x00040000L
-#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
-#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
-#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
-#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
-#define CB_COLOR5_INFO__DCC_ENABLE_MASK 0x10000000L
-#define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
-//CB_COLOR5_ATTRIB
-#define CB_COLOR5_ATTRIB__MIP0_DEPTH__SHIFT 0x0
-#define CB_COLOR5_ATTRIB__META_LINEAR__SHIFT 0xb
-#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc
-#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
-#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
-#define CB_COLOR5_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
-#define CB_COLOR5_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
-#define CB_COLOR5_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
-#define CB_COLOR5_ATTRIB__RB_ALIGNED__SHIFT 0x1e
-#define CB_COLOR5_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
-#define CB_COLOR5_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
-#define CB_COLOR5_ATTRIB__META_LINEAR_MASK 0x00000800L
-#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
-#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
-#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
-#define CB_COLOR5_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
-#define CB_COLOR5_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
-#define CB_COLOR5_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
-#define CB_COLOR5_ATTRIB__RB_ALIGNED_MASK 0x40000000L
-#define CB_COLOR5_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
-//CB_COLOR5_DCC_CONTROL
-#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
-#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
-#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
-#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
-#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
-#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
-#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
-#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
-#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
-#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
-#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
-#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
-#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
-#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
-#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
-#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
-#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
-#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
-//CB_COLOR5_CMASK
-#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR5_CMASK__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR5_CMASK_BASE_EXT
-#define CB_COLOR5_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR5_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR5_FMASK
-#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR5_FMASK__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR5_FMASK_BASE_EXT
-#define CB_COLOR5_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR5_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR5_CLEAR_WORD0
-#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
-#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
-//CB_COLOR5_CLEAR_WORD1
-#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
-#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
-//CB_COLOR5_DCC_BASE
-#define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR5_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR5_DCC_BASE_EXT
-#define CB_COLOR5_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR5_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR6_BASE
-#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR6_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR6_BASE_EXT
-#define CB_COLOR6_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR6_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR6_ATTRIB2
-#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
-#define CB_COLOR6_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
-#define CB_COLOR6_ATTRIB2__MAX_MIP__SHIFT 0x1c
-#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
-#define CB_COLOR6_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
-#define CB_COLOR6_ATTRIB2__MAX_MIP_MASK 0xF0000000L
-//CB_COLOR6_VIEW
-#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0
-#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd
-#define CB_COLOR6_VIEW__MIP_LEVEL__SHIFT 0x18
-#define CB_COLOR6_VIEW__SLICE_START_MASK 0x000007FFL
-#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0x00FFE000L
-#define CB_COLOR6_VIEW__MIP_LEVEL_MASK 0x0F000000L
-//CB_COLOR6_INFO
-#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0
-#define CB_COLOR6_INFO__FORMAT__SHIFT 0x2
-#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8
-#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb
-#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd
-#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe
-#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf
-#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10
-#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11
-#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12
-#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
-#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
-#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
-#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
-#define CB_COLOR6_INFO__DCC_ENABLE__SHIFT 0x1c
-#define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
-#define CB_COLOR6_INFO__ENDIAN_MASK 0x00000003L
-#define CB_COLOR6_INFO__FORMAT_MASK 0x0000007CL
-#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x00000700L
-#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x00001800L
-#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x00002000L
-#define CB_COLOR6_INFO__COMPRESSION_MASK 0x00004000L
-#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x00008000L
-#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x00010000L
-#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x00020000L
-#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x00040000L
-#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
-#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
-#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
-#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
-#define CB_COLOR6_INFO__DCC_ENABLE_MASK 0x10000000L
-#define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
-//CB_COLOR6_ATTRIB
-#define CB_COLOR6_ATTRIB__MIP0_DEPTH__SHIFT 0x0
-#define CB_COLOR6_ATTRIB__META_LINEAR__SHIFT 0xb
-#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc
-#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
-#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
-#define CB_COLOR6_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
-#define CB_COLOR6_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
-#define CB_COLOR6_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
-#define CB_COLOR6_ATTRIB__RB_ALIGNED__SHIFT 0x1e
-#define CB_COLOR6_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
-#define CB_COLOR6_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
-#define CB_COLOR6_ATTRIB__META_LINEAR_MASK 0x00000800L
-#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
-#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
-#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
-#define CB_COLOR6_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
-#define CB_COLOR6_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
-#define CB_COLOR6_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
-#define CB_COLOR6_ATTRIB__RB_ALIGNED_MASK 0x40000000L
-#define CB_COLOR6_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
-//CB_COLOR6_DCC_CONTROL
-#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
-#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
-#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
-#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
-#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
-#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
-#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
-#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
-#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
-#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
-#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
-#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
-#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
-#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
-#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
-#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
-#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
-#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
-//CB_COLOR6_CMASK
-#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR6_CMASK__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR6_CMASK_BASE_EXT
-#define CB_COLOR6_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR6_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR6_FMASK
-#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR6_FMASK__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR6_FMASK_BASE_EXT
-#define CB_COLOR6_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR6_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR6_CLEAR_WORD0
-#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
-#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
-//CB_COLOR6_CLEAR_WORD1
-#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
-#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
-//CB_COLOR6_DCC_BASE
-#define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR6_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR6_DCC_BASE_EXT
-#define CB_COLOR6_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR6_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR7_BASE
-#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR7_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR7_BASE_EXT
-#define CB_COLOR7_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR7_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR7_ATTRIB2
-#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
-#define CB_COLOR7_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
-#define CB_COLOR7_ATTRIB2__MAX_MIP__SHIFT 0x1c
-#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
-#define CB_COLOR7_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
-#define CB_COLOR7_ATTRIB2__MAX_MIP_MASK 0xF0000000L
-//CB_COLOR7_VIEW
-#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0
-#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd
-#define CB_COLOR7_VIEW__MIP_LEVEL__SHIFT 0x18
-#define CB_COLOR7_VIEW__SLICE_START_MASK 0x000007FFL
-#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0x00FFE000L
-#define CB_COLOR7_VIEW__MIP_LEVEL_MASK 0x0F000000L
-//CB_COLOR7_INFO
-#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0
-#define CB_COLOR7_INFO__FORMAT__SHIFT 0x2
-#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8
-#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb
-#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd
-#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe
-#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf
-#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10
-#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11
-#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12
-#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
-#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
-#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
-#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
-#define CB_COLOR7_INFO__DCC_ENABLE__SHIFT 0x1c
-#define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
-#define CB_COLOR7_INFO__ENDIAN_MASK 0x00000003L
-#define CB_COLOR7_INFO__FORMAT_MASK 0x0000007CL
-#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x00000700L
-#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x00001800L
-#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x00002000L
-#define CB_COLOR7_INFO__COMPRESSION_MASK 0x00004000L
-#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x00008000L
-#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x00010000L
-#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x00020000L
-#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x00040000L
-#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
-#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
-#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
-#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
-#define CB_COLOR7_INFO__DCC_ENABLE_MASK 0x10000000L
-#define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
-//CB_COLOR7_ATTRIB
-#define CB_COLOR7_ATTRIB__MIP0_DEPTH__SHIFT 0x0
-#define CB_COLOR7_ATTRIB__META_LINEAR__SHIFT 0xb
-#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc
-#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
-#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
-#define CB_COLOR7_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
-#define CB_COLOR7_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
-#define CB_COLOR7_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
-#define CB_COLOR7_ATTRIB__RB_ALIGNED__SHIFT 0x1e
-#define CB_COLOR7_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
-#define CB_COLOR7_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
-#define CB_COLOR7_ATTRIB__META_LINEAR_MASK 0x00000800L
-#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
-#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
-#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
-#define CB_COLOR7_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
-#define CB_COLOR7_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
-#define CB_COLOR7_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
-#define CB_COLOR7_ATTRIB__RB_ALIGNED_MASK 0x40000000L
-#define CB_COLOR7_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
-//CB_COLOR7_DCC_CONTROL
-#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
-#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
-#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
-#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
-#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
-#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
-#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
-#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
-#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
-#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
-#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
-#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
-#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
-#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
-#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
-#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
-#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
-#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
-//CB_COLOR7_CMASK
-#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR7_CMASK__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR7_CMASK_BASE_EXT
-#define CB_COLOR7_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR7_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR7_FMASK
-#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR7_FMASK__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR7_FMASK_BASE_EXT
-#define CB_COLOR7_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR7_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
-//CB_COLOR7_CLEAR_WORD0
-#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
-#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
-//CB_COLOR7_CLEAR_WORD1
-#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
-#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
-//CB_COLOR7_DCC_BASE
-#define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR7_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
-//CB_COLOR7_DCC_BASE_EXT
-#define CB_COLOR7_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
-#define CB_COLOR7_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
-
-
-// addressBlock: gc_gfxudec
-//CP_EOP_DONE_ADDR_LO
-#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2
-#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL
-//CP_EOP_DONE_ADDR_HI
-#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0
-#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
-//CP_EOP_DONE_DATA_LO
-#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0
-#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xFFFFFFFFL
-//CP_EOP_DONE_DATA_HI
-#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0
-#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xFFFFFFFFL
-//CP_EOP_LAST_FENCE_LO
-#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0
-#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xFFFFFFFFL
-//CP_EOP_LAST_FENCE_HI
-#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0
-#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xFFFFFFFFL
-//CP_STREAM_OUT_ADDR_LO
-#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2
-#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xFFFFFFFCL
-//CP_STREAM_OUT_ADDR_HI
-#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0
-#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0x0000FFFFL
-//CP_NUM_PRIM_WRITTEN_COUNT0_LO
-#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0
-#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xFFFFFFFFL
-//CP_NUM_PRIM_WRITTEN_COUNT0_HI
-#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0
-#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xFFFFFFFFL
-//CP_NUM_PRIM_NEEDED_COUNT0_LO
-#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0
-#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xFFFFFFFFL
-//CP_NUM_PRIM_NEEDED_COUNT0_HI
-#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0
-#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xFFFFFFFFL
-//CP_NUM_PRIM_WRITTEN_COUNT1_LO
-#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0
-#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xFFFFFFFFL
-//CP_NUM_PRIM_WRITTEN_COUNT1_HI
-#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0
-#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xFFFFFFFFL
-//CP_NUM_PRIM_NEEDED_COUNT1_LO
-#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0
-#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xFFFFFFFFL
-//CP_NUM_PRIM_NEEDED_COUNT1_HI
-#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0
-#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xFFFFFFFFL
-//CP_NUM_PRIM_WRITTEN_COUNT2_LO
-#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0
-#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xFFFFFFFFL
-//CP_NUM_PRIM_WRITTEN_COUNT2_HI
-#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0
-#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xFFFFFFFFL
-//CP_NUM_PRIM_NEEDED_COUNT2_LO
-#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0
-#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xFFFFFFFFL
-//CP_NUM_PRIM_NEEDED_COUNT2_HI
-#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0
-#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xFFFFFFFFL
-//CP_NUM_PRIM_WRITTEN_COUNT3_LO
-#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0
-#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xFFFFFFFFL
-//CP_NUM_PRIM_WRITTEN_COUNT3_HI
-#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0
-#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xFFFFFFFFL
-//CP_NUM_PRIM_NEEDED_COUNT3_LO
-#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0
-#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xFFFFFFFFL
-//CP_NUM_PRIM_NEEDED_COUNT3_HI
-#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0
-#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xFFFFFFFFL
-//CP_PIPE_STATS_ADDR_LO
-#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2
-#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xFFFFFFFCL
-//CP_PIPE_STATS_ADDR_HI
-#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0
-#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0x0000FFFFL
-//CP_VGT_IAVERT_COUNT_LO
-#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0
-#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xFFFFFFFFL
-//CP_VGT_IAVERT_COUNT_HI
-#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0
-#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xFFFFFFFFL
-//CP_VGT_IAPRIM_COUNT_LO
-#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0
-#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xFFFFFFFFL
-//CP_VGT_IAPRIM_COUNT_HI
-#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0
-#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xFFFFFFFFL
-//CP_VGT_GSPRIM_COUNT_LO
-#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0
-#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xFFFFFFFFL
-//CP_VGT_GSPRIM_COUNT_HI
-#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0
-#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xFFFFFFFFL
-//CP_VGT_VSINVOC_COUNT_LO
-#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0
-#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xFFFFFFFFL
-//CP_VGT_VSINVOC_COUNT_HI
-#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0
-#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xFFFFFFFFL
-//CP_VGT_GSINVOC_COUNT_LO
-#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0
-#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xFFFFFFFFL
-//CP_VGT_GSINVOC_COUNT_HI
-#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0
-#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xFFFFFFFFL
-//CP_VGT_HSINVOC_COUNT_LO
-#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0
-#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xFFFFFFFFL
-//CP_VGT_HSINVOC_COUNT_HI
-#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0
-#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xFFFFFFFFL
-//CP_VGT_DSINVOC_COUNT_LO
-#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0
-#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xFFFFFFFFL
-//CP_VGT_DSINVOC_COUNT_HI
-#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0
-#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xFFFFFFFFL
-//CP_PA_CINVOC_COUNT_LO
-#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0
-#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xFFFFFFFFL
-//CP_PA_CINVOC_COUNT_HI
-#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0
-#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xFFFFFFFFL
-//CP_PA_CPRIM_COUNT_LO
-#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0
-#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xFFFFFFFFL
-//CP_PA_CPRIM_COUNT_HI
-#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0
-#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xFFFFFFFFL
-//CP_SC_PSINVOC_COUNT0_LO
-#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0
-#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xFFFFFFFFL
-//CP_SC_PSINVOC_COUNT0_HI
-#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0
-#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xFFFFFFFFL
-//CP_SC_PSINVOC_COUNT1_LO
-#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0
-#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xFFFFFFFFL
-//CP_SC_PSINVOC_COUNT1_HI
-#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0
-#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xFFFFFFFFL
-//CP_VGT_CSINVOC_COUNT_LO
-#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0
-#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xFFFFFFFFL
-//CP_VGT_CSINVOC_COUNT_HI
-#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0
-#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xFFFFFFFFL
-//CP_PIPE_STATS_CONTROL
-#define CP_PIPE_STATS_CONTROL__CACHE_POLICY__SHIFT 0x19
-#define CP_PIPE_STATS_CONTROL__CACHE_POLICY_MASK 0x02000000L
-//CP_STREAM_OUT_CONTROL
-#define CP_STREAM_OUT_CONTROL__CACHE_POLICY__SHIFT 0x19
-#define CP_STREAM_OUT_CONTROL__CACHE_POLICY_MASK 0x02000000L
-//CP_STRMOUT_CNTL
-#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0
-#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x00000001L
-//SCRATCH_REG0
-#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
-#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL
-//SCRATCH_REG1
-#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
-#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL
-//SCRATCH_REG2
-#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
-#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL
-//SCRATCH_REG3
-#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
-#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL
-//SCRATCH_REG4
-#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
-#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL
-//SCRATCH_REG5
-#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
-#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL
-//SCRATCH_REG6
-#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
-#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL
-//SCRATCH_REG7
-#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
-#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL
-//CP_APPEND_DATA_HI
-#define CP_APPEND_DATA_HI__DATA__SHIFT 0x0
-#define CP_APPEND_DATA_HI__DATA_MASK 0xFFFFFFFFL
-//CP_APPEND_LAST_CS_FENCE_HI
-#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE__SHIFT 0x0
-#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL
-//CP_APPEND_LAST_PS_FENCE_HI
-#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE__SHIFT 0x0
-#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL
-//SCRATCH_UMSK
-#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0
-#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10
-#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0x000000FFL
-#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x00030000L
-//SCRATCH_ADDR
-#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0
-#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xFFFFFFFFL
-//CP_PFP_ATOMIC_PREOP_LO
-#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
-#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL
-//CP_PFP_ATOMIC_PREOP_HI
-#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
-#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL
-//CP_PFP_GDS_ATOMIC0_PREOP_LO
-#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
-#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL
-//CP_PFP_GDS_ATOMIC0_PREOP_HI
-#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
-#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL
-//CP_PFP_GDS_ATOMIC1_PREOP_LO
-#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
-#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL
-//CP_PFP_GDS_ATOMIC1_PREOP_HI
-#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
-#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL
-//CP_APPEND_ADDR_LO
-#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2
-#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xFFFFFFFCL
-//CP_APPEND_ADDR_HI
-#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0
-#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10
-#define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT 0x19
-#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d
-#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0x0000FFFFL
-#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x00010000L
-#define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK 0x02000000L
-#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xE0000000L
-//CP_APPEND_DATA_LO
-#define CP_APPEND_DATA_LO__DATA__SHIFT 0x0
-#define CP_APPEND_DATA_LO__DATA_MASK 0xFFFFFFFFL
-//CP_APPEND_LAST_CS_FENCE_LO
-#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE__SHIFT 0x0
-#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL
-//CP_APPEND_LAST_PS_FENCE_LO
-#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE__SHIFT 0x0
-#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL
-//CP_ATOMIC_PREOP_LO
-#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
-#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL
-//CP_ME_ATOMIC_PREOP_LO
-#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
-#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL
-//CP_ATOMIC_PREOP_HI
-#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
-#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL
-//CP_ME_ATOMIC_PREOP_HI
-#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
-#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL
-//CP_GDS_ATOMIC0_PREOP_LO
-#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
-#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL
-//CP_ME_GDS_ATOMIC0_PREOP_LO
-#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
-#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL
-//CP_GDS_ATOMIC0_PREOP_HI
-#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
-#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL
-//CP_ME_GDS_ATOMIC0_PREOP_HI
-#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
-#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL
-//CP_GDS_ATOMIC1_PREOP_LO
-#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
-#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL
-//CP_ME_GDS_ATOMIC1_PREOP_LO
-#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
-#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL
-//CP_GDS_ATOMIC1_PREOP_HI
-#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
-#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL
-//CP_ME_GDS_ATOMIC1_PREOP_HI
-#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
-#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL
-//CP_ME_MC_WADDR_LO
-#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2
-#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xFFFFFFFCL
-//CP_ME_MC_WADDR_HI
-#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0
-#define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT 0x16
-#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0x0000FFFFL
-#define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK 0x00400000L
-//CP_ME_MC_WDATA_LO
-#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0
-#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xFFFFFFFFL
-//CP_ME_MC_WDATA_HI
-#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0
-#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xFFFFFFFFL
-//CP_ME_MC_RADDR_LO
-#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2
-#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xFFFFFFFCL
-//CP_ME_MC_RADDR_HI
-#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0
-#define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x16
-#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0x0000FFFFL
-#define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK 0x00400000L
-//CP_SEM_WAIT_TIMER
-#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0
-#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xFFFFFFFFL
-//CP_SIG_SEM_ADDR_LO
-#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
-#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
-#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L
-#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L
-//CP_SIG_SEM_ADDR_HI
-#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
-#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
-#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
-#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
-#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
-#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL
-#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L
-#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L
-#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L
-#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L
-//CP_WAIT_REG_MEM_TIMEOUT
-#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0
-#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xFFFFFFFFL
-//CP_WAIT_SEM_ADDR_LO
-#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
-#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
-#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L
-#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L
-//CP_WAIT_SEM_ADDR_HI
-#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
-#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
-#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
-#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
-#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
-#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL
-#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L
-#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L
-#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L
-#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L
-//CP_DMA_PFP_CONTROL
-#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR__SHIFT 0xa
-#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
-#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14
-#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
-#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d
-#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L
-#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x00002000L
-#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x00300000L
-#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x02000000L
-#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000L
-//CP_DMA_ME_CONTROL
-#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR__SHIFT 0xa
-#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
-#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14
-#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
-#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d
-#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L
-#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x00002000L
-#define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x00300000L
-#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x02000000L
-#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000L
-//CP_COHER_BASE_HI
-#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0
-#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL
-//CP_COHER_START_DELAY
-#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0
-#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x0000003FL
-//CP_COHER_CNTL
-#define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT 0x3
-#define CP_COHER_CNTL__TC_WC_ACTION_ENA__SHIFT 0x4
-#define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA__SHIFT 0x5
-#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf
-#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12
-#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16
-#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17
-#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19
-#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a
-#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b
-#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c
-#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d
-#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT 0x1e
-#define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK 0x00000008L
-#define CP_COHER_CNTL__TC_WC_ACTION_ENA_MASK 0x00000010L
-#define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA_MASK 0x00000020L
-#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x00008000L
-#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x00040000L
-#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x00400000L
-#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x00800000L
-#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x02000000L
-#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x04000000L
-#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x08000000L
-#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000L
-#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000L
-#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK 0x40000000L
-//CP_COHER_SIZE
-#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0
-#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL
-//CP_COHER_BASE
-#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0
-#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL
-//CP_COHER_STATUS
-#define CP_COHER_STATUS__MEID__SHIFT 0x18
-#define CP_COHER_STATUS__STATUS__SHIFT 0x1f
-#define CP_COHER_STATUS__MEID_MASK 0x03000000L
-#define CP_COHER_STATUS__STATUS_MASK 0x80000000L
-//CP_DMA_ME_SRC_ADDR
-#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0
-#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL
-//CP_DMA_ME_SRC_ADDR_HI
-#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
-#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL
-//CP_DMA_ME_DST_ADDR
-#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0
-#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL
-//CP_DMA_ME_DST_ADDR_HI
-#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
-#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL
-//CP_DMA_ME_COMMAND
-#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0
-#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a
-#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b
-#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c
-#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d
-#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e
-#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x1f
-#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL
-#define CP_DMA_ME_COMMAND__SAS_MASK 0x04000000L
-#define CP_DMA_ME_COMMAND__DAS_MASK 0x08000000L
-#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000L
-#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000L
-#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000L
-#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x80000000L
-//CP_DMA_PFP_SRC_ADDR
-#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0
-#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL
-//CP_DMA_PFP_SRC_ADDR_HI
-#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
-#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL
-//CP_DMA_PFP_DST_ADDR
-#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0
-#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL
-//CP_DMA_PFP_DST_ADDR_HI
-#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
-#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL
-//CP_DMA_PFP_COMMAND
-#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0
-#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a
-#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b
-#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c
-#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d
-#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e
-#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x1f
-#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL
-#define CP_DMA_PFP_COMMAND__SAS_MASK 0x04000000L
-#define CP_DMA_PFP_COMMAND__DAS_MASK 0x08000000L
-#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000L
-#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000L
-#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000L
-#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x80000000L
-//CP_DMA_CNTL
-#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL__SHIFT 0x0
-#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4
-#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10
-#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c
-#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d
-#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e
-#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL_MASK 0x00000001L
-#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x00000030L
-#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0x000F0000L
-#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000L
-#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000L
-#define CP_DMA_CNTL__PIO_COUNT_MASK 0xC0000000L
-//CP_DMA_READ_TAGS
-#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0
-#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c
-#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x03FFFFFFL
-#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000L
-//CP_COHER_SIZE_HI
-#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0
-#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL
-//CP_PFP_IB_CONTROL
-#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0
-#define CP_PFP_IB_CONTROL__IB_EN_MASK 0x000000FFL
-//CP_PFP_LOAD_CONTROL
-#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0
-#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1
-#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10
-#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18
-#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x00000001L
-#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x00000002L
-#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x00010000L
-#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x01000000L
-//CP_SCRATCH_INDEX
-#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
-#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000000FFL
-//CP_SCRATCH_DATA
-#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
-#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL
-//CP_RB_OFFSET
-#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0
-#define CP_RB_OFFSET__RB_OFFSET_MASK 0x000FFFFFL
-//CP_IB1_OFFSET
-#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
-#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0x000FFFFFL
-//CP_IB2_OFFSET
-#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
-#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL
-//CP_IB1_PREAMBLE_BEGIN
-#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0
-#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0x000FFFFFL
-//CP_IB1_PREAMBLE_END
-#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0
-#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0x000FFFFFL
-//CP_IB2_PREAMBLE_BEGIN
-#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0
-#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0x000FFFFFL
-//CP_IB2_PREAMBLE_END
-#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0
-#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0x000FFFFFL
-//CP_CE_IB1_OFFSET
-#define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
-#define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0x000FFFFFL
-//CP_CE_IB2_OFFSET
-#define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
-#define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL
-//CP_CE_COUNTER
-#define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0
-#define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL
-//CP_CE_RB_OFFSET
-#define CP_CE_RB_OFFSET__RB_OFFSET__SHIFT 0x0
-#define CP_CE_RB_OFFSET__RB_OFFSET_MASK 0x000FFFFFL
-//CP_CE_INIT_CMD_BUFSZ
-#define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ__SHIFT 0x0
-#define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ_MASK 0x00000FFFL
-//CP_CE_IB1_CMD_BUFSZ
-#define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0
-#define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL
-//CP_CE_IB2_CMD_BUFSZ
-#define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0
-#define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL
-//CP_IB1_CMD_BUFSZ
-#define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0
-#define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL
-//CP_IB2_CMD_BUFSZ
-#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0
-#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL
-//CP_ST_CMD_BUFSZ
-#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ__SHIFT 0x0
-#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ_MASK 0x000FFFFFL
-//CP_CE_INIT_BASE_LO
-#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5
-#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xFFFFFFE0L
-//CP_CE_INIT_BASE_HI
-#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0
-#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0x0000FFFFL
-//CP_CE_INIT_BUFSZ
-#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0
-#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0x00000FFFL
-//CP_CE_IB1_BASE_LO
-#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
-#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL
-//CP_CE_IB1_BASE_HI
-#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
-#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL
-//CP_CE_IB1_BUFSZ
-#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
-#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL
-//CP_CE_IB2_BASE_LO
-#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
-#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL
-//CP_CE_IB2_BASE_HI
-#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
-#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL
-//CP_CE_IB2_BUFSZ
-#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
-#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL
-//CP_IB1_BASE_LO
-#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
-#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL
-//CP_IB1_BASE_HI
-#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
-#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL
-//CP_IB1_BUFSZ
-#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
-#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL
-//CP_IB2_BASE_LO
-#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
-#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL
-//CP_IB2_BASE_HI
-#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
-#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL
-//CP_IB2_BUFSZ
-#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
-#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL
-//CP_ST_BASE_LO
-#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2
-#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xFFFFFFFCL
-//CP_ST_BASE_HI
-#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0
-#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0x0000FFFFL
-//CP_ST_BUFSZ
-#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0
-#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000FFFFFL
-//CP_EOP_DONE_EVENT_CNTL
-#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x0
-#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0xc
-#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY__SHIFT 0x19
-#define CP_EOP_DONE_EVENT_CNTL__EXECUTE__SHIFT 0x1c
-#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x0000007FL
-#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x0003F000L
-#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY_MASK 0x02000000L
-#define CP_EOP_DONE_EVENT_CNTL__EXECUTE_MASK 0x10000000L
-//CP_EOP_DONE_DATA_CNTL
-#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10
-#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18
-#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d
-#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x00030000L
-#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x07000000L
-#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xE0000000L
-//CP_EOP_DONE_CNTX_ID
-#define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT 0x0
-#define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL
-//CP_PFP_COMPLETION_STATUS
-#define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT 0x0
-#define CP_PFP_COMPLETION_STATUS__STATUS_MASK 0x00000003L
-//CP_CE_COMPLETION_STATUS
-#define CP_CE_COMPLETION_STATUS__STATUS__SHIFT 0x0
-#define CP_CE_COMPLETION_STATUS__STATUS_MASK 0x00000003L
-//CP_PRED_NOT_VISIBLE
-#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT 0x0
-#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK 0x00000001L
-//CP_PFP_METADATA_BASE_ADDR
-#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0
-#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
-//CP_PFP_METADATA_BASE_ADDR_HI
-#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
-#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
-//CP_CE_METADATA_BASE_ADDR
-#define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0
-#define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
-//CP_CE_METADATA_BASE_ADDR_HI
-#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
-#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
-//CP_DRAW_INDX_INDR_ADDR
-#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT 0x0
-#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
-//CP_DRAW_INDX_INDR_ADDR_HI
-#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0
-#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
-//CP_DISPATCH_INDR_ADDR
-#define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT 0x0
-#define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
-//CP_DISPATCH_INDR_ADDR_HI
-#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0
-#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
-//CP_INDEX_BASE_ADDR
-#define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT 0x0
-#define CP_INDEX_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
-//CP_INDEX_BASE_ADDR_HI
-#define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
-#define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
-//CP_INDEX_TYPE
-#define CP_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
-#define CP_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L
-//CP_GDS_BKUP_ADDR
-#define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT 0x0
-#define CP_GDS_BKUP_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
-//CP_GDS_BKUP_ADDR_HI
-#define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT 0x0
-#define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
-//CP_SAMPLE_STATUS
-#define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT 0x0
-#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT 0x1
-#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT 0x2
-#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT 0x3
-#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT 0x4
-#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT 0x5
-#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT 0x6
-#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT 0x7
-#define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK 0x00000001L
-#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK 0x00000002L
-#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK 0x00000004L
-#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK 0x00000008L
-#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK 0x00000010L
-#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK 0x00000020L
-#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK 0x00000040L
-#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK 0x00000080L
-//CP_ME_COHER_CNTL
-#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0
-#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1
-#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6
-#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7
-#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8
-#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9
-#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa
-#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb
-#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc
-#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd
-#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe
-#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13
-#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15
-#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x00000001L
-#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x00000002L
-#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x00000040L
-#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x00000080L
-#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x00000100L
-#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x00000200L
-#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x00000400L
-#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x00000800L
-#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x00001000L
-#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x00002000L
-#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x00004000L
-#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x00080000L
-#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x00200000L
-//CP_ME_COHER_SIZE
-#define CP_ME_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0
-#define CP_ME_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL
-//CP_ME_COHER_SIZE_HI
-#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0
-#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL
-//CP_ME_COHER_BASE
-#define CP_ME_COHER_BASE__COHER_BASE_256B__SHIFT 0x0
-#define CP_ME_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL
-//CP_ME_COHER_BASE_HI
-#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0
-#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL
-//CP_ME_COHER_STATUS
-#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0
-#define CP_ME_COHER_STATUS__STATUS__SHIFT 0x1f
-#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0x000000FFL
-#define CP_ME_COHER_STATUS__STATUS_MASK 0x80000000L
-//RLC_GPM_PERF_COUNT_0
-#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0
-#define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4
-#define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT 0x8
-#define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT 0xc
-#define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10
-#define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12
-#define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14
-#define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15
-#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0x0000000FL
-#define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0x000000F0L
-#define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK 0x00000F00L
-#define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK 0x0000F000L
-#define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x00030000L
-#define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0x000C0000L
-#define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x00100000L
-#define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xFFE00000L
-//RLC_GPM_PERF_COUNT_1
-#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0
-#define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4
-#define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT 0x8
-#define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT 0xc
-#define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10
-#define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12
-#define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14
-#define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15
-#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0x0000000FL
-#define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0x000000F0L
-#define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK 0x00000F00L
-#define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK 0x0000F000L
-#define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x00030000L
-#define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0x000C0000L
-#define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x00100000L
-#define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xFFE00000L
-//GRBM_GFX_INDEX
-#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0
-#define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x8
-#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10
-#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d
-#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e
-#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f
-#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0x000000FFL
-#define GRBM_GFX_INDEX__SH_INDEX_MASK 0x0000FF00L
-#define GRBM_GFX_INDEX__SE_INDEX_MASK 0x00FF0000L
-#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000L
-#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L
-#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000L
-//VGT_GSVS_RING_SIZE
-#define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x0
-#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xFFFFFFFFL
-//VGT_PRIMITIVE_TYPE
-#define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0
-#define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL
-//VGT_INDEX_TYPE
-#define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
-#define VGT_INDEX_TYPE__PRIMGEN_EN__SHIFT 0x8
-#define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L
-#define VGT_INDEX_TYPE__PRIMGEN_EN_MASK 0x00000100L
-//VGT_STRMOUT_BUFFER_FILLED_SIZE_0
-#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xFFFFFFFFL
-//VGT_STRMOUT_BUFFER_FILLED_SIZE_1
-#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xFFFFFFFFL
-//VGT_STRMOUT_BUFFER_FILLED_SIZE_2
-#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xFFFFFFFFL
-//VGT_STRMOUT_BUFFER_FILLED_SIZE_3
-#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xFFFFFFFFL
-//VGT_MAX_VTX_INDX
-#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0
-#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xFFFFFFFFL
-//VGT_MIN_VTX_INDX
-#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0
-#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xFFFFFFFFL
-//VGT_INDX_OFFSET
-#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0
-#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xFFFFFFFFL
-//VGT_MULTI_PRIM_IB_RESET_EN
-#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0
-#define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT 0x1
-#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x00000001L
-#define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK 0x00000002L
-//VGT_NUM_INDICES
-#define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x0
-#define VGT_NUM_INDICES__NUM_INDICES_MASK 0xFFFFFFFFL
-//VGT_NUM_INSTANCES
-#define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0
-#define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL
-//VGT_TF_RING_SIZE
-#define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0
-#define VGT_TF_RING_SIZE__SIZE_MASK 0x0000FFFFL
-//VGT_HS_OFFCHIP_PARAM
-#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0
-#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x9
-#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x000001FFL
-#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x00000600L
-//VGT_TF_MEMORY_BASE
-#define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0
-#define VGT_TF_MEMORY_BASE__BASE_MASK 0xFFFFFFFFL
-//VGT_TF_MEMORY_BASE_HI
-#define VGT_TF_MEMORY_BASE_HI__BASE_HI__SHIFT 0x0
-#define VGT_TF_MEMORY_BASE_HI__BASE_HI_MASK 0x000000FFL
-//WD_POS_BUF_BASE
-#define WD_POS_BUF_BASE__BASE__SHIFT 0x0
-#define WD_POS_BUF_BASE__BASE_MASK 0xFFFFFFFFL
-//WD_POS_BUF_BASE_HI
-#define WD_POS_BUF_BASE_HI__BASE_HI__SHIFT 0x0
-#define WD_POS_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL
-//WD_CNTL_SB_BUF_BASE
-#define WD_CNTL_SB_BUF_BASE__BASE__SHIFT 0x0
-#define WD_CNTL_SB_BUF_BASE__BASE_MASK 0xFFFFFFFFL
-//WD_CNTL_SB_BUF_BASE_HI
-#define WD_CNTL_SB_BUF_BASE_HI__BASE_HI__SHIFT 0x0
-#define WD_CNTL_SB_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL
-//WD_INDEX_BUF_BASE
-#define WD_INDEX_BUF_BASE__BASE__SHIFT 0x0
-#define WD_INDEX_BUF_BASE__BASE_MASK 0xFFFFFFFFL
-//WD_INDEX_BUF_BASE_HI
-#define WD_INDEX_BUF_BASE_HI__BASE_HI__SHIFT 0x0
-#define WD_INDEX_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL
-//IA_MULTI_VGT_PARAM
-#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x0
-#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x10
-#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x11
-#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x12
-#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x13
-#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x14
-#define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC__SHIFT 0x15
-#define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV__SHIFT 0x16
-#define IA_MULTI_VGT_PARAM__HW_USE_ONLY__SHIFT 0x17
-#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0x0000FFFFL
-#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x00010000L
-#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x00020000L
-#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x00040000L
-#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x00080000L
-#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x00100000L
-#define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC_MASK 0x00200000L
-#define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV_MASK 0x00400000L
-#define IA_MULTI_VGT_PARAM__HW_USE_ONLY_MASK 0x00800000L
-//VGT_INSTANCE_BASE_ID
-#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT 0x0
-#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK 0xFFFFFFFFL
-//PA_SU_LINE_STIPPLE_VALUE
-#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0
-#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0x00FFFFFFL
-//PA_SC_LINE_STIPPLE_STATE
-#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0
-#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8
-#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0x0000000FL
-#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0x0000FF00L
-//PA_SC_SCREEN_EXTENT_MIN_0
-#define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0
-#define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10
-#define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0x0000FFFFL
-#define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xFFFF0000L
-//PA_SC_SCREEN_EXTENT_MAX_0
-#define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0
-#define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10
-#define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0x0000FFFFL
-#define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xFFFF0000L
-//PA_SC_SCREEN_EXTENT_MIN_1
-#define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0
-#define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10
-#define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0x0000FFFFL
-#define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xFFFF0000L
-//PA_SC_SCREEN_EXTENT_MAX_1
-#define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0
-#define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10
-#define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0x0000FFFFL
-#define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xFFFF0000L
-//PA_SC_P3D_TRAP_SCREEN_HV_EN
-#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
-#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
-#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L
-#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L
-//PA_SC_P3D_TRAP_SCREEN_H
-#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
-#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL
-//PA_SC_P3D_TRAP_SCREEN_V
-#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
-#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL
-//PA_SC_P3D_TRAP_SCREEN_OCCURRENCE
-#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
-#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL
-//PA_SC_P3D_TRAP_SCREEN_COUNT
-#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
-#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL
-//PA_SC_HP3D_TRAP_SCREEN_HV_EN
-#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
-#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
-#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L
-#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L
-//PA_SC_HP3D_TRAP_SCREEN_H
-#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
-#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL
-//PA_SC_HP3D_TRAP_SCREEN_V
-#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
-#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL
-//PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE
-#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
-#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL
-//PA_SC_HP3D_TRAP_SCREEN_COUNT
-#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
-#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL
-//PA_SC_TRAP_SCREEN_HV_EN
-#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
-#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
-#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L
-#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L
-//PA_SC_TRAP_SCREEN_H
-#define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
-#define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL
-//PA_SC_TRAP_SCREEN_V
-#define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
-#define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL
-//PA_SC_TRAP_SCREEN_OCCURRENCE
-#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
-#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL
-//PA_SC_TRAP_SCREEN_COUNT
-#define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
-#define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL
-//SQ_THREAD_TRACE_BASE
-#define SQ_THREAD_TRACE_BASE__ADDR__SHIFT 0x0
-#define SQ_THREAD_TRACE_BASE__ADDR_MASK 0xFFFFFFFFL
-//SQ_THREAD_TRACE_SIZE
-#define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT 0x0
-#define SQ_THREAD_TRACE_SIZE__SIZE_MASK 0x003FFFFFL
-//SQ_THREAD_TRACE_MASK
-#define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT 0x0
-#define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT 0x5
-#define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT 0x7
-#define SQ_THREAD_TRACE_MASK__SIMD_EN__SHIFT 0x8
-#define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT 0xc
-#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT 0xe
-#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT 0xf
-#define SQ_THREAD_TRACE_MASK__CU_SEL_MASK 0x0000001FL
-#define SQ_THREAD_TRACE_MASK__SH_SEL_MASK 0x00000020L
-#define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK 0x00000080L
-#define SQ_THREAD_TRACE_MASK__SIMD_EN_MASK 0x00000F00L
-#define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK 0x00003000L
-#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK 0x00004000L
-#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK 0x00008000L
-//SQ_THREAD_TRACE_TOKEN_MASK
-#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT 0x0
-#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT 0x10
-#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT 0x18
-#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK 0x0000FFFFL
-#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK 0x00FF0000L
-#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK 0x01000000L
-//SQ_THREAD_TRACE_PERF_MASK
-#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT 0x0
-#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT 0x10
-#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK 0x0000FFFFL
-#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK 0xFFFF0000L
-//SQ_THREAD_TRACE_CTRL
-#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT 0x1f
-#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK 0x80000000L
-//SQ_THREAD_TRACE_MODE
-#define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT 0x0
-#define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT 0x3
-#define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT 0x6
-#define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT 0x9
-#define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT 0xc
-#define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT 0xf
-#define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT 0x12
-#define SQ_THREAD_TRACE_MODE__MODE__SHIFT 0x15
-#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT 0x17
-#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT 0x19
-#define SQ_THREAD_TRACE_MODE__TC_PERF_EN__SHIFT 0x1a
-#define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT 0x1b
-#define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x1d
-#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT 0x1e
-#define SQ_THREAD_TRACE_MODE__WRAP__SHIFT 0x1f
-#define SQ_THREAD_TRACE_MODE__MASK_PS_MASK 0x00000007L
-#define SQ_THREAD_TRACE_MODE__MASK_VS_MASK 0x00000038L
-#define SQ_THREAD_TRACE_MODE__MASK_GS_MASK 0x000001C0L
-#define SQ_THREAD_TRACE_MODE__MASK_ES_MASK 0x00000E00L
-#define SQ_THREAD_TRACE_MODE__MASK_HS_MASK 0x00007000L
-#define SQ_THREAD_TRACE_MODE__MASK_LS_MASK 0x00038000L
-#define SQ_THREAD_TRACE_MODE__MASK_CS_MASK 0x001C0000L
-#define SQ_THREAD_TRACE_MODE__MODE_MASK 0x00600000L
-#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK 0x01800000L
-#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK 0x02000000L
-#define SQ_THREAD_TRACE_MODE__TC_PERF_EN_MASK 0x04000000L
-#define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK 0x18000000L
-#define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK 0x20000000L
-#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK 0x40000000L
-#define SQ_THREAD_TRACE_MODE__WRAP_MASK 0x80000000L
-//SQ_THREAD_TRACE_BASE2
-#define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT 0x0
-#define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK 0x0000000FL
-//SQ_THREAD_TRACE_TOKEN_MASK2
-#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT 0x0
-#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK 0xFFFFFFFFL
-//SQ_THREAD_TRACE_WPTR
-#define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT 0x0
-#define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT 0x1e
-#define SQ_THREAD_TRACE_WPTR__WPTR_MASK 0x3FFFFFFFL
-#define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK 0xC0000000L
-//SQ_THREAD_TRACE_STATUS
-#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0
-#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0x10
-#define SQ_THREAD_TRACE_STATUS__UTC_ERROR__SHIFT 0x1c
-#define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x1d
-#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x1e
-#define SQ_THREAD_TRACE_STATUS__FULL__SHIFT 0x1f
-#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x000003FFL
-#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x03FF0000L
-#define SQ_THREAD_TRACE_STATUS__UTC_ERROR_MASK 0x10000000L
-#define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK 0x20000000L
-#define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x40000000L
-#define SQ_THREAD_TRACE_STATUS__FULL_MASK 0x80000000L
-//SQ_THREAD_TRACE_HIWATER
-#define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT 0x0
-#define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK 0x00000007L
-//SQ_THREAD_TRACE_CNTR
-#define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT 0x0
-#define SQ_THREAD_TRACE_CNTR__CNTR_MASK 0xFFFFFFFFL
-//SQ_THREAD_TRACE_USERDATA_0
-#define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x0
-#define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xFFFFFFFFL
-//SQ_THREAD_TRACE_USERDATA_1
-#define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x0
-#define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xFFFFFFFFL
-//SQ_THREAD_TRACE_USERDATA_2
-#define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x0
-#define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xFFFFFFFFL
-//SQ_THREAD_TRACE_USERDATA_3
-#define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x0
-#define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xFFFFFFFFL
-//SQC_CACHES
-#define SQC_CACHES__TARGET_INST__SHIFT 0x0
-#define SQC_CACHES__TARGET_DATA__SHIFT 0x1
-#define SQC_CACHES__INVALIDATE__SHIFT 0x2
-#define SQC_CACHES__WRITEBACK__SHIFT 0x3
-#define SQC_CACHES__VOL__SHIFT 0x4
-#define SQC_CACHES__COMPLETE__SHIFT 0x10
-#define SQC_CACHES__TARGET_INST_MASK 0x00000001L
-#define SQC_CACHES__TARGET_DATA_MASK 0x00000002L
-#define SQC_CACHES__INVALIDATE_MASK 0x00000004L
-#define SQC_CACHES__WRITEBACK_MASK 0x00000008L
-#define SQC_CACHES__VOL_MASK 0x00000010L
-#define SQC_CACHES__COMPLETE_MASK 0x00010000L
-//SQC_WRITEBACK
-#define SQC_WRITEBACK__DWB__SHIFT 0x0
-#define SQC_WRITEBACK__DIRTY__SHIFT 0x1
-#define SQC_WRITEBACK__DWB_MASK 0x00000001L
-#define SQC_WRITEBACK__DIRTY_MASK 0x00000002L
-//TA_CS_BC_BASE_ADDR
-#define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x0
-#define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xFFFFFFFFL
-//TA_CS_BC_BASE_ADDR_HI
-#define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0
-#define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL
-//DB_OCCLUSION_COUNT0_LOW
-#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0
-#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
-//DB_OCCLUSION_COUNT0_HI
-#define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0
-#define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7FFFFFFFL
-//DB_OCCLUSION_COUNT1_LOW
-#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0
-#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
-//DB_OCCLUSION_COUNT1_HI
-#define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0
-#define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7FFFFFFFL
-//DB_OCCLUSION_COUNT2_LOW
-#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0
-#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
-//DB_OCCLUSION_COUNT2_HI
-#define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0
-#define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7FFFFFFFL
-//DB_OCCLUSION_COUNT3_LOW
-#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0
-#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
-//DB_OCCLUSION_COUNT3_HI
-#define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0
-#define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7FFFFFFFL
-//DB_ZPASS_COUNT_LOW
-#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x0
-#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
-//DB_ZPASS_COUNT_HI
-#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x0
-#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7FFFFFFFL
-//GDS_RD_ADDR
-#define GDS_RD_ADDR__READ_ADDR__SHIFT 0x0
-#define GDS_RD_ADDR__READ_ADDR_MASK 0xFFFFFFFFL
-//GDS_RD_DATA
-#define GDS_RD_DATA__READ_DATA__SHIFT 0x0
-#define GDS_RD_DATA__READ_DATA_MASK 0xFFFFFFFFL
-//GDS_RD_BURST_ADDR
-#define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x0
-#define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xFFFFFFFFL
-//GDS_RD_BURST_COUNT
-#define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x0
-#define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xFFFFFFFFL
-//GDS_RD_BURST_DATA
-#define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x0
-#define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xFFFFFFFFL
-//GDS_WR_ADDR
-#define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x0
-#define GDS_WR_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL
-//GDS_WR_DATA
-#define GDS_WR_DATA__WRITE_DATA__SHIFT 0x0
-#define GDS_WR_DATA__WRITE_DATA_MASK 0xFFFFFFFFL
-//GDS_WR_BURST_ADDR
-#define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x0
-#define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL
-//GDS_WR_BURST_DATA
-#define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x0
-#define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xFFFFFFFFL
-//GDS_WRITE_COMPLETE
-#define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x0
-#define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xFFFFFFFFL
-//GDS_ATOM_CNTL
-#define GDS_ATOM_CNTL__AINC__SHIFT 0x0
-#define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x6
-#define GDS_ATOM_CNTL__DMODE__SHIFT 0x8
-#define GDS_ATOM_CNTL__UNUSED2__SHIFT 0xa
-#define GDS_ATOM_CNTL__AINC_MASK 0x0000003FL
-#define GDS_ATOM_CNTL__UNUSED1_MASK 0x000000C0L
-#define GDS_ATOM_CNTL__DMODE_MASK 0x00000300L
-#define GDS_ATOM_CNTL__UNUSED2_MASK 0xFFFFFC00L
-//GDS_ATOM_COMPLETE
-#define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x0
-#define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x1
-#define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x00000001L
-#define GDS_ATOM_COMPLETE__UNUSED_MASK 0xFFFFFFFEL
-//GDS_ATOM_BASE
-#define GDS_ATOM_BASE__BASE__SHIFT 0x0
-#define GDS_ATOM_BASE__UNUSED__SHIFT 0x10
-#define GDS_ATOM_BASE__BASE_MASK 0x0000FFFFL
-#define GDS_ATOM_BASE__UNUSED_MASK 0xFFFF0000L
-//GDS_ATOM_SIZE
-#define GDS_ATOM_SIZE__SIZE__SHIFT 0x0
-#define GDS_ATOM_SIZE__UNUSED__SHIFT 0x10
-#define GDS_ATOM_SIZE__SIZE_MASK 0x0000FFFFL
-#define GDS_ATOM_SIZE__UNUSED_MASK 0xFFFF0000L
-//GDS_ATOM_OFFSET0
-#define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x0
-#define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x8
-#define GDS_ATOM_OFFSET0__OFFSET0_MASK 0x000000FFL
-#define GDS_ATOM_OFFSET0__UNUSED_MASK 0xFFFFFF00L
-//GDS_ATOM_OFFSET1
-#define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x0
-#define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x8
-#define GDS_ATOM_OFFSET1__OFFSET1_MASK 0x000000FFL
-#define GDS_ATOM_OFFSET1__UNUSED_MASK 0xFFFFFF00L
-//GDS_ATOM_DST
-#define GDS_ATOM_DST__DST__SHIFT 0x0
-#define GDS_ATOM_DST__DST_MASK 0xFFFFFFFFL
-//GDS_ATOM_OP
-#define GDS_ATOM_OP__OP__SHIFT 0x0
-#define GDS_ATOM_OP__UNUSED__SHIFT 0x8
-#define GDS_ATOM_OP__OP_MASK 0x000000FFL
-#define GDS_ATOM_OP__UNUSED_MASK 0xFFFFFF00L
-//GDS_ATOM_SRC0
-#define GDS_ATOM_SRC0__DATA__SHIFT 0x0
-#define GDS_ATOM_SRC0__DATA_MASK 0xFFFFFFFFL
-//GDS_ATOM_SRC0_U
-#define GDS_ATOM_SRC0_U__DATA__SHIFT 0x0
-#define GDS_ATOM_SRC0_U__DATA_MASK 0xFFFFFFFFL
-//GDS_ATOM_SRC1
-#define GDS_ATOM_SRC1__DATA__SHIFT 0x0
-#define GDS_ATOM_SRC1__DATA_MASK 0xFFFFFFFFL
-//GDS_ATOM_SRC1_U
-#define GDS_ATOM_SRC1_U__DATA__SHIFT 0x0
-#define GDS_ATOM_SRC1_U__DATA_MASK 0xFFFFFFFFL
-//GDS_ATOM_READ0
-#define GDS_ATOM_READ0__DATA__SHIFT 0x0
-#define GDS_ATOM_READ0__DATA_MASK 0xFFFFFFFFL
-//GDS_ATOM_READ0_U
-#define GDS_ATOM_READ0_U__DATA__SHIFT 0x0
-#define GDS_ATOM_READ0_U__DATA_MASK 0xFFFFFFFFL
-//GDS_ATOM_READ1
-#define GDS_ATOM_READ1__DATA__SHIFT 0x0
-#define GDS_ATOM_READ1__DATA_MASK 0xFFFFFFFFL
-//GDS_ATOM_READ1_U
-#define GDS_ATOM_READ1_U__DATA__SHIFT 0x0
-#define GDS_ATOM_READ1_U__DATA_MASK 0xFFFFFFFFL
-//GDS_GWS_RESOURCE_CNTL
-#define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x0
-#define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x6
-#define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x0000003FL
-#define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xFFFFFFC0L
-//GDS_GWS_RESOURCE
-#define GDS_GWS_RESOURCE__FLAG__SHIFT 0x0
-#define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x1
-#define GDS_GWS_RESOURCE__TYPE__SHIFT 0xd
-#define GDS_GWS_RESOURCE__DED__SHIFT 0xe
-#define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0xf
-#define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x10
-#define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x1c
-#define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x1d
-#define GDS_GWS_RESOURCE__HALTED__SHIFT 0x1e
-#define GDS_GWS_RESOURCE__UNUSED1__SHIFT 0x1f
-#define GDS_GWS_RESOURCE__FLAG_MASK 0x00000001L
-#define GDS_GWS_RESOURCE__COUNTER_MASK 0x00001FFEL
-#define GDS_GWS_RESOURCE__TYPE_MASK 0x00002000L
-#define GDS_GWS_RESOURCE__DED_MASK 0x00004000L
-#define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x00008000L
-#define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0x0FFF0000L
-#define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x10000000L
-#define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x20000000L
-#define GDS_GWS_RESOURCE__HALTED_MASK 0x40000000L
-#define GDS_GWS_RESOURCE__UNUSED1_MASK 0x80000000L
-//GDS_GWS_RESOURCE_CNT
-#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x0
-#define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x10
-#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0x0000FFFFL
-#define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xFFFF0000L
-//GDS_OA_CNTL
-#define GDS_OA_CNTL__INDEX__SHIFT 0x0
-#define GDS_OA_CNTL__UNUSED__SHIFT 0x4
-#define GDS_OA_CNTL__INDEX_MASK 0x0000000FL
-#define GDS_OA_CNTL__UNUSED_MASK 0xFFFFFFF0L
-//GDS_OA_COUNTER
-#define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT 0x0
-#define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK 0xFFFFFFFFL
-//GDS_OA_ADDRESS
-#define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT 0x0
-#define GDS_OA_ADDRESS__CRAWLER__SHIFT 0x10
-#define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT 0x14
-#define GDS_OA_ADDRESS__UNUSED__SHIFT 0x16
-#define GDS_OA_ADDRESS__NO_ALLOC__SHIFT 0x1e
-#define GDS_OA_ADDRESS__ENABLE__SHIFT 0x1f
-#define GDS_OA_ADDRESS__DS_ADDRESS_MASK 0x0000FFFFL
-#define GDS_OA_ADDRESS__CRAWLER_MASK 0x000F0000L
-#define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK 0x00300000L
-#define GDS_OA_ADDRESS__UNUSED_MASK 0x3FC00000L
-#define GDS_OA_ADDRESS__NO_ALLOC_MASK 0x40000000L
-#define GDS_OA_ADDRESS__ENABLE_MASK 0x80000000L
-//GDS_OA_INCDEC
-#define GDS_OA_INCDEC__VALUE__SHIFT 0x0
-#define GDS_OA_INCDEC__INCDEC__SHIFT 0x1f
-#define GDS_OA_INCDEC__VALUE_MASK 0x7FFFFFFFL
-#define GDS_OA_INCDEC__INCDEC_MASK 0x80000000L
-//GDS_OA_RING_SIZE
-#define GDS_OA_RING_SIZE__RING_SIZE__SHIFT 0x0
-#define GDS_OA_RING_SIZE__RING_SIZE_MASK 0xFFFFFFFFL
-//SPI_CONFIG_CNTL
-#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0
-#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15
-#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18
-#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19
-#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x1a
-#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x1b
-#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA__SHIFT 0x1c
-#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA__SHIFT 0x1d
-#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL__SHIFT 0x1e
-#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x001FFFFFL
-#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0x00E00000L
-#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x01000000L
-#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x02000000L
-#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x04000000L
-#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x08000000L
-#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA_MASK 0x10000000L
-#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA_MASK 0x20000000L
-#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL_MASK 0xC0000000L
-//SPI_CONFIG_CNTL_1
-#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0
-#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4
-#define SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE__SHIFT 0x5
-#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x6
-#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7
-#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x8
-#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x9
-#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa
-#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE__SHIFT 0xe
-#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE__SHIFT 0xf
-#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT 0x10
-#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0x0000000FL
-#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x00000010L
-#define SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE_MASK 0x00000020L
-#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x00000040L
-#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x00000080L
-#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x00000100L
-#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x00000200L
-#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x00003C00L
-#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE_MASK 0x00004000L
-#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE_MASK 0x00008000L
-#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK 0xFFFF0000L
-//SPI_CONFIG_CNTL_2
-#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT 0x0
-#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT 0x4
-#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK 0x0000000FL
-#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK 0x000000F0L
-
-
-// addressBlock: gc_perfddec
-//CPG_PERFCOUNTER1_LO
-#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//CPG_PERFCOUNTER1_HI
-#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//CPG_PERFCOUNTER0_LO
-#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//CPG_PERFCOUNTER0_HI
-#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//CPC_PERFCOUNTER1_LO
-#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//CPC_PERFCOUNTER1_HI
-#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//CPC_PERFCOUNTER0_LO
-#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//CPC_PERFCOUNTER0_HI
-#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//CPF_PERFCOUNTER1_LO
-#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//CPF_PERFCOUNTER1_HI
-#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//CPF_PERFCOUNTER0_LO
-#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//CPF_PERFCOUNTER0_HI
-#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//CPF_LATENCY_STATS_DATA
-#define CPF_LATENCY_STATS_DATA__DATA__SHIFT 0x0
-#define CPF_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL
-//CPG_LATENCY_STATS_DATA
-#define CPG_LATENCY_STATS_DATA__DATA__SHIFT 0x0
-#define CPG_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL
-//CPC_LATENCY_STATS_DATA
-#define CPC_LATENCY_STATS_DATA__DATA__SHIFT 0x0
-#define CPC_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL
-//GRBM_PERFCOUNTER0_LO
-#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//GRBM_PERFCOUNTER0_HI
-#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//GRBM_PERFCOUNTER1_LO
-#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//GRBM_PERFCOUNTER1_HI
-#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//GRBM_SE0_PERFCOUNTER_LO
-#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//GRBM_SE0_PERFCOUNTER_HI
-#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//GRBM_SE1_PERFCOUNTER_LO
-#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//GRBM_SE1_PERFCOUNTER_HI
-#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//GRBM_SE2_PERFCOUNTER_LO
-#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//GRBM_SE2_PERFCOUNTER_HI
-#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//GRBM_SE3_PERFCOUNTER_LO
-#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//GRBM_SE3_PERFCOUNTER_HI
-#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//WD_PERFCOUNTER0_LO
-#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//WD_PERFCOUNTER0_HI
-#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//WD_PERFCOUNTER1_LO
-#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//WD_PERFCOUNTER1_HI
-#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//WD_PERFCOUNTER2_LO
-#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//WD_PERFCOUNTER2_HI
-#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//WD_PERFCOUNTER3_LO
-#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//WD_PERFCOUNTER3_HI
-#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//IA_PERFCOUNTER0_LO
-#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//IA_PERFCOUNTER0_HI
-#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//IA_PERFCOUNTER1_LO
-#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//IA_PERFCOUNTER1_HI
-#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//IA_PERFCOUNTER2_LO
-#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//IA_PERFCOUNTER2_HI
-#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//IA_PERFCOUNTER3_LO
-#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//IA_PERFCOUNTER3_HI
-#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//VGT_PERFCOUNTER0_LO
-#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//VGT_PERFCOUNTER0_HI
-#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//VGT_PERFCOUNTER1_LO
-#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//VGT_PERFCOUNTER1_HI
-#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//VGT_PERFCOUNTER2_LO
-#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//VGT_PERFCOUNTER2_HI
-#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//VGT_PERFCOUNTER3_LO
-#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//VGT_PERFCOUNTER3_HI
-#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//PA_SU_PERFCOUNTER0_LO
-#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//PA_SU_PERFCOUNTER0_HI
-#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL
-//PA_SU_PERFCOUNTER1_LO
-#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//PA_SU_PERFCOUNTER1_HI
-#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL
-//PA_SU_PERFCOUNTER2_LO
-#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//PA_SU_PERFCOUNTER2_HI
-#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL
-//PA_SU_PERFCOUNTER3_LO
-#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//PA_SU_PERFCOUNTER3_HI
-#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL
-//PA_SC_PERFCOUNTER0_LO
-#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//PA_SC_PERFCOUNTER0_HI
-#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//PA_SC_PERFCOUNTER1_LO
-#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//PA_SC_PERFCOUNTER1_HI
-#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//PA_SC_PERFCOUNTER2_LO
-#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//PA_SC_PERFCOUNTER2_HI
-#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//PA_SC_PERFCOUNTER3_LO
-#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//PA_SC_PERFCOUNTER3_HI
-#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//PA_SC_PERFCOUNTER4_LO
-#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//PA_SC_PERFCOUNTER4_HI
-#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//PA_SC_PERFCOUNTER5_LO
-#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//PA_SC_PERFCOUNTER5_HI
-#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//PA_SC_PERFCOUNTER6_LO
-#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//PA_SC_PERFCOUNTER6_HI
-#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//PA_SC_PERFCOUNTER7_LO
-#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//PA_SC_PERFCOUNTER7_HI
-#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SPI_PERFCOUNTER0_HI
-#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SPI_PERFCOUNTER0_LO
-#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SPI_PERFCOUNTER1_HI
-#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SPI_PERFCOUNTER1_LO
-#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SPI_PERFCOUNTER2_HI
-#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SPI_PERFCOUNTER2_LO
-#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SPI_PERFCOUNTER3_HI
-#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SPI_PERFCOUNTER3_LO
-#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SPI_PERFCOUNTER4_HI
-#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SPI_PERFCOUNTER4_LO
-#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SPI_PERFCOUNTER5_HI
-#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SPI_PERFCOUNTER5_LO
-#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER0_LO
-#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER0_HI
-#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER1_LO
-#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER1_HI
-#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER2_LO
-#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER2_HI
-#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER3_LO
-#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER3_HI
-#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER4_LO
-#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER4_HI
-#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER5_LO
-#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER5_HI
-#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER6_LO
-#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER6_HI
-#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER7_LO
-#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER7_HI
-#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER8_LO
-#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER8_HI
-#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER9_LO
-#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER9_HI
-#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER10_LO
-#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER10_HI
-#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER11_LO
-#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER11_HI
-#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER12_LO
-#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER12_HI
-#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER13_LO
-#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER13_HI
-#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER14_LO
-#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER14_HI
-#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER15_LO
-#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SQ_PERFCOUNTER15_HI
-#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SX_PERFCOUNTER0_LO
-#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SX_PERFCOUNTER0_HI
-#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SX_PERFCOUNTER1_LO
-#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SX_PERFCOUNTER1_HI
-#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SX_PERFCOUNTER2_LO
-#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SX_PERFCOUNTER2_HI
-#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//SX_PERFCOUNTER3_LO
-#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//SX_PERFCOUNTER3_HI
-#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//GDS_PERFCOUNTER0_LO
-#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//GDS_PERFCOUNTER0_HI
-#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//GDS_PERFCOUNTER1_LO
-#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//GDS_PERFCOUNTER1_HI
-#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//GDS_PERFCOUNTER2_LO
-#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//GDS_PERFCOUNTER2_HI
-#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//GDS_PERFCOUNTER3_LO
-#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//GDS_PERFCOUNTER3_HI
-#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//TA_PERFCOUNTER0_LO
-#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//TA_PERFCOUNTER0_HI
-#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//TA_PERFCOUNTER1_LO
-#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//TA_PERFCOUNTER1_HI
-#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//TD_PERFCOUNTER0_LO
-#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//TD_PERFCOUNTER0_HI
-#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//TD_PERFCOUNTER1_LO
-#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//TD_PERFCOUNTER1_HI
-#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//TCP_PERFCOUNTER0_LO
-#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//TCP_PERFCOUNTER0_HI
-#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//TCP_PERFCOUNTER1_LO
-#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//TCP_PERFCOUNTER1_HI
-#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//TCP_PERFCOUNTER2_LO
-#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//TCP_PERFCOUNTER2_HI
-#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//TCP_PERFCOUNTER3_LO
-#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//TCP_PERFCOUNTER3_HI
-#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//TCC_PERFCOUNTER0_LO
-#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//TCC_PERFCOUNTER0_HI
-#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//TCC_PERFCOUNTER1_LO
-#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//TCC_PERFCOUNTER1_HI
-#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//TCC_PERFCOUNTER2_LO
-#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//TCC_PERFCOUNTER2_HI
-#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//TCC_PERFCOUNTER3_LO
-#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//TCC_PERFCOUNTER3_HI
-#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//TCA_PERFCOUNTER0_LO
-#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//TCA_PERFCOUNTER0_HI
-#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//TCA_PERFCOUNTER1_LO
-#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//TCA_PERFCOUNTER1_HI
-#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//TCA_PERFCOUNTER2_LO
-#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//TCA_PERFCOUNTER2_HI
-#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//TCA_PERFCOUNTER3_LO
-#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//TCA_PERFCOUNTER3_HI
-#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//CB_PERFCOUNTER0_LO
-#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//CB_PERFCOUNTER0_HI
-#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//CB_PERFCOUNTER1_LO
-#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//CB_PERFCOUNTER1_HI
-#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//CB_PERFCOUNTER2_LO
-#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//CB_PERFCOUNTER2_HI
-#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//CB_PERFCOUNTER3_LO
-#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//CB_PERFCOUNTER3_HI
-#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//DB_PERFCOUNTER0_LO
-#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//DB_PERFCOUNTER0_HI
-#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//DB_PERFCOUNTER1_LO
-#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//DB_PERFCOUNTER1_HI
-#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//DB_PERFCOUNTER2_LO
-#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//DB_PERFCOUNTER2_HI
-#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//DB_PERFCOUNTER3_LO
-#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//DB_PERFCOUNTER3_HI
-#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//RLC_PERFCOUNTER0_LO
-#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//RLC_PERFCOUNTER0_HI
-#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//RLC_PERFCOUNTER1_LO
-#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//RLC_PERFCOUNTER1_HI
-#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//RMI_PERFCOUNTER0_LO
-#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//RMI_PERFCOUNTER0_HI
-#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//RMI_PERFCOUNTER1_LO
-#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//RMI_PERFCOUNTER1_HI
-#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//RMI_PERFCOUNTER2_LO
-#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//RMI_PERFCOUNTER2_HI
-#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-//RMI_PERFCOUNTER3_LO
-#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
-//RMI_PERFCOUNTER3_HI
-#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
-
-
-// addressBlock: gc_utcl2_atcl2pfcntrdec
-//ATC_L2_PERFCOUNTER_LO
-#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
-#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
-//ATC_L2_PERFCOUNTER_HI
-#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
-#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
-#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
-#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
-
-
-// addressBlock: gc_utcl2_vml2prdec
-//MC_VM_L2_PERFCOUNTER_LO
-#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
-#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
-//MC_VM_L2_PERFCOUNTER_HI
-#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
-#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
-#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
-#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
-
-
-// addressBlock: gc_perfsdec
-//CPG_PERFCOUNTER1_SELECT
-#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0
-#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa
-#define CPG_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
-#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18
-#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c
-#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL
-#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L
-#define CPG_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L
-#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L
-#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L
-//CPG_PERFCOUNTER0_SELECT1
-#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0
-#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa
-#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18
-#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c
-#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL
-#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L
-#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L
-#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L
-//CPG_PERFCOUNTER0_SELECT
-#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0
-#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa
-#define CPG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
-#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18
-#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c
-#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL
-#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L
-#define CPG_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L
-#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L
-#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L
-//CPC_PERFCOUNTER1_SELECT
-#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0
-#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa
-#define CPC_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
-#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18
-#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c
-#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL
-#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L
-#define CPC_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L
-#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L
-#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L
-//CPC_PERFCOUNTER0_SELECT1
-#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0
-#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa
-#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18
-#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c
-#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL
-#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L
-#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L
-#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L
-//CPF_PERFCOUNTER1_SELECT
-#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0
-#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa
-#define CPF_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
-#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18
-#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c
-#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL
-#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L
-#define CPF_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L
-#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L
-#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L
-//CPF_PERFCOUNTER0_SELECT1
-#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0
-#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa
-#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18
-#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c
-#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL
-#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L
-#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L
-#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L
-//CPF_PERFCOUNTER0_SELECT
-#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0
-#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa
-#define CPF_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
-#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18
-#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c
-#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL
-#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L
-#define CPF_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L
-#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L
-#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L
-//CP_PERFMON_CNTL
-#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
-#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4
-#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8
-#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
-#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000FL
-#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0x000000F0L
-#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L
-#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L
-//CPC_PERFCOUNTER0_SELECT
-#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0
-#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa
-#define CPC_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
-#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18
-#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c
-#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL
-#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L
-#define CPC_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L
-#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L
-#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L
-//CPF_TC_PERF_COUNTER_WINDOW_SELECT
-#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0
-#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e
-#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f
-#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x00000007L
-#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L
-#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L
-//CPG_TC_PERF_COUNTER_WINDOW_SELECT
-#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0
-#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e
-#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f
-#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x0000001FL
-#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L
-#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L
-//CPF_LATENCY_STATS_SELECT
-#define CPF_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0
-#define CPF_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e
-#define CPF_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f
-#define CPF_LATENCY_STATS_SELECT__INDEX_MASK 0x0000000FL
-#define CPF_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L
-#define CPF_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L
-//CPG_LATENCY_STATS_SELECT
-#define CPG_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0
-#define CPG_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e
-#define CPG_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f
-#define CPG_LATENCY_STATS_SELECT__INDEX_MASK 0x0000001FL
-#define CPG_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L
-#define CPG_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L
-//CPC_LATENCY_STATS_SELECT
-#define CPC_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0
-#define CPC_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e
-#define CPC_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f
-#define CPC_LATENCY_STATS_SELECT__INDEX_MASK 0x00000007L
-#define CPC_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L
-#define CPC_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L
-//CP_DRAW_OBJECT
-#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0
-#define CP_DRAW_OBJECT__OBJECT_MASK 0xFFFFFFFFL
-//CP_DRAW_OBJECT_COUNTER
-#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0
-#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0x0000FFFFL
-//CP_DRAW_WINDOW_MASK_HI
-#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0
-#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xFFFFFFFFL
-//CP_DRAW_WINDOW_HI
-#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0
-#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xFFFFFFFFL
-//CP_DRAW_WINDOW_LO
-#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0
-#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10
-#define CP_DRAW_WINDOW_LO__MIN_MASK 0x0000FFFFL
-#define CP_DRAW_WINDOW_LO__MAX_MASK 0xFFFF0000L
-//CP_DRAW_WINDOW_CNTL
-#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0
-#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1
-#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2
-#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8
-#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x00000001L
-#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x00000002L
-#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x00000004L
-#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x00000100L
-//GRBM_PERFCOUNTER0_SELECT
-#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
-#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
-#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc
-#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
-#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
-#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
-#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
-#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
-#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13
-#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
-#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
-#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16
-#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17
-#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18
-#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
-#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
-#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
-#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
-#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d
-#define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e
-#define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f
-#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003FL
-#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
-#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
-#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
-#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
-#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L
-#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
-#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
-#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
-#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
-#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
-#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
-#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
-#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L
-#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L
-#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L
-#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L
-#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L
-#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L
-#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L
-#define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L
-#define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L
-//GRBM_PERFCOUNTER1_SELECT
-#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
-#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
-#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc
-#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
-#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
-#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
-#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
-#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
-#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13
-#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
-#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
-#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16
-#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17
-#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18
-#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
-#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
-#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
-#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
-#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d
-#define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e
-#define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f
-#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003FL
-#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
-#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
-#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
-#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
-#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L
-#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
-#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
-#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
-#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
-#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
-#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
-#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
-#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L
-#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L
-#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L
-#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L
-#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L
-#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L
-#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L
-#define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L
-#define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L
-//GRBM_SE0_PERFCOUNTER_SELECT
-#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
-#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
-#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
-#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
-#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
-#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
-#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
-#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
-#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
-#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
-#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
-#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
-#define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16
-#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL
-#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
-#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
-#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
-#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
-#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L
-#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
-#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
-#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
-#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
-#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
-#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
-#define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
-//GRBM_SE1_PERFCOUNTER_SELECT
-#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
-#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
-#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
-#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
-#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
-#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
-#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
-#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
-#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
-#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
-#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
-#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
-#define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16
-#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL
-#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
-#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
-#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
-#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
-#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L
-#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
-#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
-#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
-#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
-#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
-#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
-#define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
-//GRBM_SE2_PERFCOUNTER_SELECT
-#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
-#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
-#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
-#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
-#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
-#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
-#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
-#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
-#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
-#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
-#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
-#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
-#define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16
-#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL
-#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
-#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
-#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
-#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
-#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L
-#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
-#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
-#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
-#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
-#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
-#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
-#define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
-//GRBM_SE3_PERFCOUNTER_SELECT
-#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
-#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
-#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
-#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
-#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
-#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
-#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
-#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
-#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
-#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
-#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
-#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
-#define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16
-#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL
-#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
-#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
-#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
-#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
-#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L
-#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
-#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
-#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
-#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
-#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
-#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
-#define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
-//WD_PERFCOUNTER0_SELECT
-#define WD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define WD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define WD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL
-#define WD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
-//WD_PERFCOUNTER1_SELECT
-#define WD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define WD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define WD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL
-#define WD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
-//WD_PERFCOUNTER2_SELECT
-#define WD_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define WD_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
-#define WD_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL
-#define WD_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
-//WD_PERFCOUNTER3_SELECT
-#define WD_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define WD_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
-#define WD_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL
-#define WD_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
-//IA_PERFCOUNTER0_SELECT
-#define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
-#define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
-#define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
-//IA_PERFCOUNTER1_SELECT
-#define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL
-#define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
-//IA_PERFCOUNTER2_SELECT
-#define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
-#define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL
-#define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
-//IA_PERFCOUNTER3_SELECT
-#define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
-#define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL
-#define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
-//IA_PERFCOUNTER0_SELECT1
-#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
-#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//VGT_PERFCOUNTER0_SELECT
-#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
-#define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
-#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
-//VGT_PERFCOUNTER1_SELECT
-#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
-#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
-#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
-#define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
-#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
-//VGT_PERFCOUNTER2_SELECT
-#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
-#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL
-#define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
-//VGT_PERFCOUNTER3_SELECT
-#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
-#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL
-#define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
-//VGT_PERFCOUNTER0_SELECT1
-#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
-#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//VGT_PERFCOUNTER1_SELECT1
-#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
-#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
-#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
-#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//VGT_PERFCOUNTER_SEID_MASK
-#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT 0x0
-#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK 0x000000FFL
-//PA_SU_PERFCOUNTER0_SELECT
-#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
-#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
-//PA_SU_PERFCOUNTER0_SELECT1
-#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-//PA_SU_PERFCOUNTER1_SELECT
-#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
-#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
-#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
-#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
-//PA_SU_PERFCOUNTER1_SELECT1
-#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
-#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
-#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-//PA_SU_PERFCOUNTER2_SELECT
-#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
-#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
-#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
-//PA_SU_PERFCOUNTER3_SELECT
-#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
-#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
-#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
-//PA_SC_PERFCOUNTER0_SELECT
-#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
-#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
-//PA_SC_PERFCOUNTER0_SELECT1
-#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-//PA_SC_PERFCOUNTER1_SELECT
-#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
-//PA_SC_PERFCOUNTER2_SELECT
-#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
-//PA_SC_PERFCOUNTER3_SELECT
-#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
-//PA_SC_PERFCOUNTER4_SELECT
-#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
-#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL
-//PA_SC_PERFCOUNTER5_SELECT
-#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
-#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL
-//PA_SC_PERFCOUNTER6_SELECT
-#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0
-#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000003FFL
-//PA_SC_PERFCOUNTER7_SELECT
-#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0
-#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000003FFL
-//SPI_PERFCOUNTER0_SELECT
-#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
-#define SPI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
-#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define SPI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
-//SPI_PERFCOUNTER1_SELECT
-#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
-#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
-#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
-#define SPI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
-#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define SPI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
-//SPI_PERFCOUNTER2_SELECT
-#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
-#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
-#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
-#define SPI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
-#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
-#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define SPI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
-//SPI_PERFCOUNTER3_SELECT
-#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
-#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
-#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18
-#define SPI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
-#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
-#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define SPI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
-//SPI_PERFCOUNTER0_SELECT1
-#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
-#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//SPI_PERFCOUNTER1_SELECT1
-#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
-#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
-#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
-#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//SPI_PERFCOUNTER2_SELECT1
-#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0
-#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
-#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18
-#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//SPI_PERFCOUNTER3_SELECT1
-#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0
-#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa
-#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18
-#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//SPI_PERFCOUNTER4_SELECT
-#define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
-#define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000000FFL
-//SPI_PERFCOUNTER5_SELECT
-#define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
-#define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000000FFL
-//SPI_PERFCOUNTER_BINS
-#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0
-#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4
-#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8
-#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc
-#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10
-#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14
-#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18
-#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c
-#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0x0000000FL
-#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0x000000F0L
-#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0x00000F00L
-#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0x0000F000L
-#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0x000F0000L
-#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0x00F00000L
-#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0x0F000000L
-#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xF0000000L
-//SQ_PERFCOUNTER0_SELECT
-#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL
-#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
-#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
-#define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L
-#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK 0x0F000000L
-#define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
-//SQ_PERFCOUNTER1_SELECT
-#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL
-#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
-#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
-#define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L
-#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK 0x0F000000L
-#define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
-//SQ_PERFCOUNTER2_SELECT
-#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL
-#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
-#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
-#define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0x00F00000L
-#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK 0x0F000000L
-#define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
-//SQ_PERFCOUNTER3_SELECT
-#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL
-#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
-#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
-#define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0x00F00000L
-#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK 0x0F000000L
-#define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
-//SQ_PERFCOUNTER4_SELECT
-#define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000001FFL
-#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
-#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
-#define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0x00F00000L
-#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK 0x0F000000L
-#define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xF0000000L
-//SQ_PERFCOUNTER5_SELECT
-#define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000001FFL
-#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
-#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
-#define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0x00F00000L
-#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK 0x0F000000L
-#define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xF0000000L
-//SQ_PERFCOUNTER6_SELECT
-#define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000001FFL
-#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
-#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
-#define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0x00F00000L
-#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK 0x0F000000L
-#define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xF0000000L
-//SQ_PERFCOUNTER7_SELECT
-#define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000001FFL
-#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
-#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
-#define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0x00F00000L
-#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK 0x0F000000L
-#define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xF0000000L
-//SQ_PERFCOUNTER8_SELECT
-#define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0x000001FFL
-#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
-#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
-#define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0x00F00000L
-#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK 0x0F000000L
-#define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xF0000000L
-//SQ_PERFCOUNTER9_SELECT
-#define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0x000001FFL
-#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
-#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
-#define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0x00F00000L
-#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK 0x0F000000L
-#define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xF0000000L
-//SQ_PERFCOUNTER10_SELECT
-#define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0x000001FFL
-#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
-#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
-#define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0x00F00000L
-#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK 0x0F000000L
-#define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xF0000000L
-//SQ_PERFCOUNTER11_SELECT
-#define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0x000001FFL
-#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
-#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
-#define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0x00F00000L
-#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK 0x0F000000L
-#define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xF0000000L
-//SQ_PERFCOUNTER12_SELECT
-#define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0x000001FFL
-#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
-#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
-#define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0x00F00000L
-#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK 0x0F000000L
-#define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xF0000000L
-//SQ_PERFCOUNTER13_SELECT
-#define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0x000001FFL
-#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
-#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
-#define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0x00F00000L
-#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK 0x0F000000L
-#define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xF0000000L
-//SQ_PERFCOUNTER14_SELECT
-#define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0x000001FFL
-#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
-#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
-#define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0x00F00000L
-#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK 0x0F000000L
-#define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xF0000000L
-//SQ_PERFCOUNTER15_SELECT
-#define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0x000001FFL
-#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
-#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
-#define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0x00F00000L
-#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK 0x0F000000L
-#define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xF0000000L
-//SQ_PERFCOUNTER_CTRL
-#define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0
-#define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x1
-#define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2
-#define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x3
-#define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4
-#define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x5
-#define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6
-#define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x8
-#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0xd
-#define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x00000001L
-#define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x00000002L
-#define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x00000004L
-#define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x00000008L
-#define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x00000010L
-#define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x00000020L
-#define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x00000040L
-#define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x00001F00L
-#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x00002000L
-//SQ_PERFCOUNTER_MASK
-#define SQ_PERFCOUNTER_MASK__SH0_MASK__SHIFT 0x0
-#define SQ_PERFCOUNTER_MASK__SH1_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER_MASK__SH0_MASK_MASK 0x0000FFFFL
-#define SQ_PERFCOUNTER_MASK__SH1_MASK_MASK 0xFFFF0000L
-//SQ_PERFCOUNTER_CTRL2
-#define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0
-#define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x00000001L
-//SX_PERFCOUNTER0_SELECT
-#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
-#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
-#define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL
-#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L
-#define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
-//SX_PERFCOUNTER1_SELECT
-#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
-#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
-#define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
-#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL
-#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L
-#define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
-//SX_PERFCOUNTER2_SELECT
-#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
-#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
-#define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
-#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL
-#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L
-#define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
-//SX_PERFCOUNTER3_SELECT
-#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
-#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
-#define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
-#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL
-#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L
-#define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
-//SX_PERFCOUNTER0_SELECT1
-#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
-#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
-#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003FFL
-#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000FFC00L
-//SX_PERFCOUNTER1_SELECT1
-#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
-#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
-#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003FFL
-#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000FFC00L
-//GDS_PERFCOUNTER0_SELECT
-#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
-#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
-#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL
-#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L
-#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
-//GDS_PERFCOUNTER1_SELECT
-#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
-#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
-#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
-#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL
-#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L
-#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
-//GDS_PERFCOUNTER2_SELECT
-#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
-#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
-#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
-#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL
-#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L
-#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
-//GDS_PERFCOUNTER3_SELECT
-#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
-#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
-#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
-#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL
-#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L
-#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
-//GDS_PERFCOUNTER0_SELECT1
-#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
-#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
-#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003FFL
-#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000FFC00L
-//TA_PERFCOUNTER0_SELECT
-#define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
-#define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL
-#define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003FC00L
-#define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
-//TA_PERFCOUNTER0_SELECT1
-#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
-#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000FFL
-#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003FC00L
-#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//TA_PERFCOUNTER1_SELECT
-#define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define TA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
-#define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
-#define TA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
-#define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL
-#define TA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x0003FC00L
-#define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define TA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
-//TD_PERFCOUNTER0_SELECT
-#define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
-#define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL
-#define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003FC00L
-#define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
-//TD_PERFCOUNTER0_SELECT1
-#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
-#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000FFL
-#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003FC00L
-#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//TD_PERFCOUNTER1_SELECT
-#define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define TD_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
-#define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
-#define TD_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
-#define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL
-#define TD_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x0003FC00L
-#define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define TD_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
-//TCP_PERFCOUNTER0_SELECT
-#define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
-#define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
-#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
-//TCP_PERFCOUNTER0_SELECT1
-#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
-#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//TCP_PERFCOUNTER1_SELECT
-#define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
-#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
-#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
-#define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
-#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
-//TCP_PERFCOUNTER1_SELECT1
-#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
-#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
-#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
-#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//TCP_PERFCOUNTER2_SELECT
-#define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
-#define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
-#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
-#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
-//TCP_PERFCOUNTER3_SELECT
-#define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
-#define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
-#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
-#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
-//TCC_PERFCOUNTER0_SELECT
-#define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
-#define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
-#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
-//TCC_PERFCOUNTER0_SELECT1
-#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
-#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
-#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L
-#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L
-//TCC_PERFCOUNTER1_SELECT
-#define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
-#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
-#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
-#define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
-#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
-//TCC_PERFCOUNTER1_SELECT1
-#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
-#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
-#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18
-#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c
-#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L
-#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L
-//TCC_PERFCOUNTER2_SELECT
-#define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
-#define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
-#define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
-#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
-//TCC_PERFCOUNTER3_SELECT
-#define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
-#define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
-#define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
-#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
-//TCA_PERFCOUNTER0_SELECT
-#define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
-#define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
-#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
-//TCA_PERFCOUNTER0_SELECT1
-#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
-#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
-#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L
-#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L
-//TCA_PERFCOUNTER1_SELECT
-#define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
-#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
-#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
-#define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
-#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
-//TCA_PERFCOUNTER1_SELECT1
-#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
-#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
-#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18
-#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c
-#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L
-#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L
-//TCA_PERFCOUNTER2_SELECT
-#define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
-#define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
-#define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
-#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
-//TCA_PERFCOUNTER3_SELECT
-#define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
-#define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
-#define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
-#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
-//CB_PERFCOUNTER_FILTER
-#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0
-#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1
-#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4
-#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5
-#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa
-#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb
-#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc
-#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd
-#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11
-#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12
-#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15
-#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16
-#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x00000001L
-#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0x0000000EL
-#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x00000010L
-#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x000003E0L
-#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x00000400L
-#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x00000800L
-#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x00001000L
-#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0x0000E000L
-#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x00020000L
-#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x001C0000L
-#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x00200000L
-#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0x00C00000L
-//CB_PERFCOUNTER0_SELECT
-#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
-#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL
-#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L
-#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
-//CB_PERFCOUNTER0_SELECT1
-#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
-#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL
-#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L
-#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//CB_PERFCOUNTER1_SELECT
-#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL
-#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
-//CB_PERFCOUNTER2_SELECT
-#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
-#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL
-#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
-//CB_PERFCOUNTER3_SELECT
-#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
-#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL
-#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
-//DB_PERFCOUNTER0_SELECT
-#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
-#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
-#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
-//DB_PERFCOUNTER0_SELECT1
-#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
-#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//DB_PERFCOUNTER1_SELECT
-#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
-#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
-#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
-#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
-#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
-//DB_PERFCOUNTER1_SELECT1
-#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
-#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
-#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
-#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
-#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
-#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//DB_PERFCOUNTER2_SELECT
-#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
-#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
-#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
-#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
-#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
-#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
-//DB_PERFCOUNTER3_SELECT
-#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
-#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
-#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18
-#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
-#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
-#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L
-#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
-//RLC_SPM_PERFMON_CNTL
-#define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x2
-#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc
-#define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xe
-#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10
-#define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0x00000FFCL
-#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x00003000L
-#define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0x0000C000L
-#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xFFFF0000L
-//RLC_SPM_PERFMON_RING_BASE_LO
-#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0
-#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xFFFFFFFFL
-//RLC_SPM_PERFMON_RING_BASE_HI
-#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0
-#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10
-#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0x0000FFFFL
-#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xFFFF0000L
-//RLC_SPM_PERFMON_RING_SIZE
-#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0
-#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xFFFFFFFFL
-//RLC_SPM_PERFMON_SEGMENT_SIZE
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT 0x8
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0xb
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x10
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x15
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x1a
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT 0x1f
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0x000000FFL
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK 0x00000700L
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0x0000F800L
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x001F0000L
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x03E00000L
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7C000000L
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK 0x80000000L
-//RLC_SPM_SE_MUXSEL_ADDR
-#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0
-#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xFFFFFFFFL
-//RLC_SPM_SE_MUXSEL_DATA
-#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0
-#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xFFFFFFFFL
-//RLC_SPM_CPG_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_SPM_CPC_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_SPM_CPF_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_SPM_CB_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_SPM_DB_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_SPM_PA_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_SPM_GDS_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_SPM_IA_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_SPM_SC_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_SPM_TCC_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_SPM_TCA_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_SPM_TCP_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_SPM_TA_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_SPM_TD_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_SPM_VGT_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_SPM_SPI_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_SPM_SQG_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_SPM_SX_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_SPM_GLOBAL_MUXSEL_ADDR
-#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0
-#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xFFFFFFFFL
-//RLC_SPM_GLOBAL_MUXSEL_DATA
-#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0
-#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xFFFFFFFFL
-//RLC_SPM_RING_RDPTR
-#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0
-#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xFFFFFFFFL
-//RLC_SPM_SEGMENT_THRESHOLD
-#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0
-#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0xFFFFFFFFL
-//RLC_SPM_RMI_PERFMON_SAMPLE_DELAY
-#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
-#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
-//RLC_PERFMON_CLK_CNTL
-#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE__SHIFT 0x0
-#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK 0x00000001L
-//RLC_PERFMON_CNTL
-#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
-#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
-#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000007L
-#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L
-//RLC_PERFCOUNTER0_SELECT
-#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
-#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x00FFL
-//RLC_PERFCOUNTER1_SELECT
-#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
-#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x00FFL
-//RLC_GPU_IOV_PERF_CNT_CNTL
-#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE__SHIFT 0x0
-#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT__SHIFT 0x1
-#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET__SHIFT 0x2
-#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED__SHIFT 0x3
-#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE_MASK 0x00000001L
-#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT_MASK 0x00000002L
-#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET_MASK 0x00000004L
-#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED_MASK 0xFFFFFFF8L
-//RLC_GPU_IOV_PERF_CNT_WR_ADDR
-#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID__SHIFT 0x0
-#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID__SHIFT 0x4
-#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED__SHIFT 0x6
-#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID_MASK 0x0000000FL
-#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID_MASK 0x00000030L
-#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED_MASK 0xFFFFFFC0L
-//RLC_GPU_IOV_PERF_CNT_WR_DATA
-#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA__SHIFT 0x0
-#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA_MASK 0x0000000FL
-//RLC_GPU_IOV_PERF_CNT_RD_ADDR
-#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID__SHIFT 0x0
-#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID__SHIFT 0x4
-#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED__SHIFT 0x6
-#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID_MASK 0x0000000FL
-#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID_MASK 0x00000030L
-#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED_MASK 0xFFFFFFC0L
-//RLC_GPU_IOV_PERF_CNT_RD_DATA
-#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA__SHIFT 0x0
-#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA_MASK 0x0000000FL
-//RMI_PERFCOUNTER0_SELECT
-#define RMI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
-#define RMI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define RMI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL
-#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L
-#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define RMI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
-//RMI_PERFCOUNTER0_SELECT1
-#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
-#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL
-#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L
-#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//RMI_PERFCOUNTER1_SELECT
-#define RMI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define RMI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define RMI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL
-#define RMI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
-//RMI_PERFCOUNTER2_SELECT
-#define RMI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
-#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
-#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
-#define RMI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
-#define RMI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL
-#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x0007FC00L
-#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
-#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L
-#define RMI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
-//RMI_PERFCOUNTER2_SELECT1
-#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0
-#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
-#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18
-#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000001FFL
-#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x0007FC00L
-#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L
-#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L
-//RMI_PERFCOUNTER3_SELECT
-#define RMI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define RMI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
-#define RMI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL
-#define RMI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
-//RMI_PERF_COUNTER_CNTL
-#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL__SHIFT 0x0
-#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL__SHIFT 0x2
-#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL__SHIFT 0x4
-#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0__SHIFT 0x6
-#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1__SHIFT 0x8
-#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID__SHIFT 0xa
-#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID__SHIFT 0xe
-#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD__SHIFT 0x13
-#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET__SHIFT 0x19
-#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL__SHIFT 0x1a
-#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL_MASK 0x00000003L
-#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL_MASK 0x0000000CL
-#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL_MASK 0x00000030L
-#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0_MASK 0x000000C0L
-#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1_MASK 0x00000300L
-#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID_MASK 0x00003C00L
-#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID_MASK 0x0007C000L
-#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD_MASK 0x01F80000L
-#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET_MASK 0x02000000L
-#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL_MASK 0x04000000L
-
-
-// addressBlock: gc_utcl2_atcl2pfcntldec
-//ATC_L2_PERFCOUNTER0_CFG
-#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
-#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
-#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
-#define ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
-#define ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
-#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
-#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
-#define ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
-#define ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
-//ATC_L2_PERFCOUNTER1_CFG
-#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
-#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
-#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
-#define ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
-#define ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
-#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
-#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
-#define ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
-#define ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
-//ATC_L2_PERFCOUNTER_RSLT_CNTL
-#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
-#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
-#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
-#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
-#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
-#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
-#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
-#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
-#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
-#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
-#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
-#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
-
-
-// addressBlock: gc_utcl2_vml2pldec
-//MC_VM_L2_PERFCOUNTER0_CFG
-#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
-#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
-#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
-#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
-#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
-#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
-#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
-#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
-#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
-//MC_VM_L2_PERFCOUNTER1_CFG
-#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
-#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
-#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
-#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
-#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
-#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
-#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
-#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
-#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
-//MC_VM_L2_PERFCOUNTER2_CFG
-#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
-#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
-#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
-#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
-#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
-#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
-#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
-#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
-#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
-//MC_VM_L2_PERFCOUNTER3_CFG
-#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
-#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
-#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
-#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
-#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
-#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL
-#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L
-#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L
-#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L
-//MC_VM_L2_PERFCOUNTER4_CFG
-#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0
-#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8
-#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18
-#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c
-#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d
-#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL
-#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L
-#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L
-#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L
-//MC_VM_L2_PERFCOUNTER5_CFG
-#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0
-#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8
-#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18
-#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c
-#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d
-#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL
-#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L
-#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L
-#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L
-//MC_VM_L2_PERFCOUNTER6_CFG
-#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0
-#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8
-#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18
-#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c
-#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d
-#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL
-#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L
-#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L
-#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L
-//MC_VM_L2_PERFCOUNTER7_CFG
-#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0
-#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8
-#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18
-#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c
-#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d
-#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL
-#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L
-#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L
-#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L
-//MC_VM_L2_PERFCOUNTER_RSLT_CNTL
-#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
-#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
-#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
-#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
-#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
-#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
-#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
-#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
-#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
-#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
-#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
-#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
-
-
-// addressBlock: gc_rlcpdec
-//RLC_CNTL
-#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0
-#define RLC_CNTL__FORCE_RETRY__SHIFT 0x1
-#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2
-#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3
-#define RLC_CNTL__RESERVED__SHIFT 0x4
-#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x00000001L
-#define RLC_CNTL__FORCE_RETRY_MASK 0x00000002L
-#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x00000004L
-#define RLC_CNTL__RLC_STEP_F32_MASK 0x00000008L
-#define RLC_CNTL__RESERVED_MASK 0xFFFFFFF0L
-//RLC_STAT
-#define RLC_STAT__RLC_BUSY__SHIFT 0x0
-#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x1
-#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x2
-#define RLC_STAT__RLC_SRM_BUSY__SHIFT 0x3
-#define RLC_STAT__MC_BUSY__SHIFT 0x4
-#define RLC_STAT__RLC_THREAD_0_BUSY__SHIFT 0x5
-#define RLC_STAT__RLC_THREAD_1_BUSY__SHIFT 0x6
-#define RLC_STAT__RLC_THREAD_2_BUSY__SHIFT 0x7
-#define RLC_STAT__RESERVED__SHIFT 0x8
-#define RLC_STAT__RLC_BUSY_MASK 0x00000001L
-#define RLC_STAT__RLC_GPM_BUSY_MASK 0x00000002L
-#define RLC_STAT__RLC_SPM_BUSY_MASK 0x00000004L
-#define RLC_STAT__RLC_SRM_BUSY_MASK 0x00000008L
-#define RLC_STAT__MC_BUSY_MASK 0x00000010L
-#define RLC_STAT__RLC_THREAD_0_BUSY_MASK 0x00000020L
-#define RLC_STAT__RLC_THREAD_1_BUSY_MASK 0x00000040L
-#define RLC_STAT__RLC_THREAD_2_BUSY_MASK 0x00000080L
-#define RLC_STAT__RESERVED_MASK 0xFFFFFF00L
-//RLC_SAFE_MODE
-#define RLC_SAFE_MODE__CMD__SHIFT 0x0
-#define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1
-#define RLC_SAFE_MODE__RESERVED1__SHIFT 0x5
-#define RLC_SAFE_MODE__RESPONSE__SHIFT 0x8
-#define RLC_SAFE_MODE__RESERVED__SHIFT 0xc
-#define RLC_SAFE_MODE__CMD_MASK 0x00000001L
-#define RLC_SAFE_MODE__MESSAGE_MASK 0x0000001EL
-#define RLC_SAFE_MODE__RESERVED1_MASK 0x000000E0L
-#define RLC_SAFE_MODE__RESPONSE_MASK 0x00000F00L
-#define RLC_SAFE_MODE__RESERVED_MASK 0xFFFFF000L
-//RLC_MEM_SLP_CNTL
-#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0
-#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1
-#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
-#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT 0x7
-#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8
-#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10
-#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
-#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x00000001L
-#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L
-#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x0000007CL
-#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L
-#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0x0000FF00L
-#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0x00FF0000L
-#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xFF000000L
-//SMU_RLC_RESPONSE
-#define SMU_RLC_RESPONSE__RESP__SHIFT 0x0
-#define SMU_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL
-//RLC_RLCV_SAFE_MODE
-#define RLC_RLCV_SAFE_MODE__CMD__SHIFT 0x0
-#define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT 0x1
-#define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT 0x5
-#define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT 0x8
-#define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT 0xc
-#define RLC_RLCV_SAFE_MODE__CMD_MASK 0x00000001L
-#define RLC_RLCV_SAFE_MODE__MESSAGE_MASK 0x0000001EL
-#define RLC_RLCV_SAFE_MODE__RESERVED1_MASK 0x000000E0L
-#define RLC_RLCV_SAFE_MODE__RESPONSE_MASK 0x00000F00L
-#define RLC_RLCV_SAFE_MODE__RESERVED_MASK 0xFFFFF000L
-//RLC_SMU_SAFE_MODE
-#define RLC_SMU_SAFE_MODE__CMD__SHIFT 0x0
-#define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT 0x1
-#define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT 0x5
-#define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT 0x8
-#define RLC_SMU_SAFE_MODE__RESERVED__SHIFT 0xc
-#define RLC_SMU_SAFE_MODE__CMD_MASK 0x00000001L
-#define RLC_SMU_SAFE_MODE__MESSAGE_MASK 0x0000001EL
-#define RLC_SMU_SAFE_MODE__RESERVED1_MASK 0x000000E0L
-#define RLC_SMU_SAFE_MODE__RESPONSE_MASK 0x00000F00L
-#define RLC_SMU_SAFE_MODE__RESERVED_MASK 0xFFFFF000L
-//RLC_RLCV_COMMAND
-#define RLC_RLCV_COMMAND__CMD__SHIFT 0x0
-#define RLC_RLCV_COMMAND__RESERVED__SHIFT 0x4
-#define RLC_RLCV_COMMAND__CMD_MASK 0x0000000FL
-#define RLC_RLCV_COMMAND__RESERVED_MASK 0xFFFFFFF0L
-//RLC_REFCLOCK_TIMESTAMP_LSB
-#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB__SHIFT 0x0
-#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB_MASK 0xFFFFFFFFL
-//RLC_REFCLOCK_TIMESTAMP_MSB
-#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB__SHIFT 0x0
-#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB_MASK 0xFFFFFFFFL
-//RLC_GPM_TIMER_INT_0
-#define RLC_GPM_TIMER_INT_0__TIMER__SHIFT 0x0
-#define RLC_GPM_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL
-//RLC_GPM_TIMER_INT_1
-#define RLC_GPM_TIMER_INT_1__TIMER__SHIFT 0x0
-#define RLC_GPM_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL
-//RLC_GPM_TIMER_INT_2
-#define RLC_GPM_TIMER_INT_2__TIMER__SHIFT 0x0
-#define RLC_GPM_TIMER_INT_2__TIMER_MASK 0xFFFFFFFFL
-//RLC_GPM_TIMER_CTRL
-#define RLC_GPM_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0
-#define RLC_GPM_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1
-#define RLC_GPM_TIMER_CTRL__TIMER_2_EN__SHIFT 0x2
-#define RLC_GPM_TIMER_CTRL__TIMER_3_EN__SHIFT 0x3
-#define RLC_GPM_TIMER_CTRL__RESERVED__SHIFT 0x4
-#define RLC_GPM_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L
-#define RLC_GPM_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L
-#define RLC_GPM_TIMER_CTRL__TIMER_2_EN_MASK 0x00000004L
-#define RLC_GPM_TIMER_CTRL__TIMER_3_EN_MASK 0x00000008L
-#define RLC_GPM_TIMER_CTRL__RESERVED_MASK 0xFFFFFFF0L
-//RLC_LB_CNTR_MAX
-#define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x0
-#define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xFFFFFFFFL
-//RLC_GPM_TIMER_STAT
-#define RLC_GPM_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0
-#define RLC_GPM_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1
-#define RLC_GPM_TIMER_STAT__TIMER_2_STAT__SHIFT 0x2
-#define RLC_GPM_TIMER_STAT__TIMER_3_STAT__SHIFT 0x3
-#define RLC_GPM_TIMER_STAT__RESERVED__SHIFT 0x4
-#define RLC_GPM_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L
-#define RLC_GPM_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L
-#define RLC_GPM_TIMER_STAT__TIMER_2_STAT_MASK 0x00000004L
-#define RLC_GPM_TIMER_STAT__TIMER_3_STAT_MASK 0x00000008L
-#define RLC_GPM_TIMER_STAT__RESERVED_MASK 0xFFFFFFF0L
-//RLC_GPM_TIMER_INT_3
-#define RLC_GPM_TIMER_INT_3__TIMER__SHIFT 0x0
-#define RLC_GPM_TIMER_INT_3__TIMER_MASK 0xFFFFFFFFL
-//RLC_SERDES_WR_NONCU_MASTER_MASK_1
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1__SHIFT 0x0
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1__SHIFT 0x10
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1__SHIFT 0x11
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK__SHIFT 0x12
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1__SHIFT 0x13
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK__SHIFT 0x14
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK__SHIFT 0x15
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK__SHIFT 0x16
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK__SHIFT 0x17
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK__SHIFT 0x18
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED__SHIFT 0x19
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1_MASK 0x0000FFFFL
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1_MASK 0x00010000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1_MASK 0x00020000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK_MASK 0x00040000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1_MASK 0x00080000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK_MASK 0x00100000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK_MASK 0x00200000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK_MASK 0x00400000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK_MASK 0x00800000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK_MASK 0x01000000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_MASK 0xFE000000L
-//RLC_SERDES_NONCU_MASTER_BUSY_1
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1__SHIFT 0x0
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1__SHIFT 0x10
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1__SHIFT 0x11
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1__SHIFT 0x12
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1__SHIFT 0x13
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY__SHIFT 0x14
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY__SHIFT 0x15
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY__SHIFT 0x16
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY__SHIFT 0x17
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY__SHIFT 0x18
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED__SHIFT 0x19
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1_MASK 0x0000FFFFL
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1_MASK 0x00010000L
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1_MASK 0x00020000L
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1_MASK 0x00040000L
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1_MASK 0x00080000L
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY_MASK 0x00100000L
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY_MASK 0x00200000L
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY_MASK 0x00400000L
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY_MASK 0x00800000L
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY_MASK 0x01000000L
-#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_MASK 0xFE000000L
-//RLC_INT_STAT
-#define RLC_INT_STAT__LAST_CP_RLC_INT_ID__SHIFT 0x0
-#define RLC_INT_STAT__CP_RLC_INT_PENDING__SHIFT 0x8
-#define RLC_INT_STAT__RESERVED__SHIFT 0x9
-#define RLC_INT_STAT__LAST_CP_RLC_INT_ID_MASK 0x000000FFL
-#define RLC_INT_STAT__CP_RLC_INT_PENDING_MASK 0x00000100L
-#define RLC_INT_STAT__RESERVED_MASK 0xFFFFFE00L
-//RLC_LB_CNTL
-#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x0
-#define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x1
-#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x2
-#define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x3
-#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x4
-#define RLC_LB_CNTL__RESERVED__SHIFT 0xc
-#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x00000001L
-#define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x00000002L
-#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x00000004L
-#define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x00000008L
-#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0x00000FF0L
-#define RLC_LB_CNTL__RESERVED_MASK 0xFFFFF000L
-//RLC_MGCG_CTRL
-#define RLC_MGCG_CTRL__MGCG_EN__SHIFT 0x0
-#define RLC_MGCG_CTRL__SILICON_EN__SHIFT 0x1
-#define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT 0x2
-#define RLC_MGCG_CTRL__ON_DELAY__SHIFT 0x3
-#define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT 0x7
-#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL__SHIFT 0xf
-#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL__SHIFT 0x10
-#define RLC_MGCG_CTRL__SPARE__SHIFT 0x11
-#define RLC_MGCG_CTRL__MGCG_EN_MASK 0x00000001L
-#define RLC_MGCG_CTRL__SILICON_EN_MASK 0x00000002L
-#define RLC_MGCG_CTRL__SIMULATION_EN_MASK 0x00000004L
-#define RLC_MGCG_CTRL__ON_DELAY_MASK 0x00000078L
-#define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK 0x00007F80L
-#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL_MASK 0x00008000L
-#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL_MASK 0x00010000L
-#define RLC_MGCG_CTRL__SPARE_MASK 0xFFFE0000L
-//RLC_LB_CNTR_INIT
-#define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x0
-#define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xFFFFFFFFL
-//RLC_LOAD_BALANCE_CNTR
-#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0
-#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xFFFFFFFFL
-//RLC_JUMP_TABLE_RESTORE
-#define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0
-#define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xFFFFFFFFL
-//RLC_PG_DELAY_2
-#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0
-#define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8
-#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT 0x10
-#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0x000000FFL
-#define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0x0000FF00L
-#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK 0xFFFF0000L
-//RLC_GPU_CLOCK_COUNT_LSB
-#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0
-#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL
-//RLC_GPU_CLOCK_COUNT_MSB
-#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0
-#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL
-//RLC_CAPTURE_GPU_CLOCK_COUNT
-#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0
-#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1
-#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x00000001L
-#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xFFFFFFFEL
-//RLC_UCODE_CNTL
-#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0
-#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xFFFFFFFFL
-//RLC_GPM_THREAD_RESET
-#define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT 0x0
-#define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT 0x1
-#define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT 0x2
-#define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT 0x3
-#define RLC_GPM_THREAD_RESET__RESERVED__SHIFT 0x4
-#define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK 0x00000001L
-#define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK 0x00000002L
-#define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK 0x00000004L
-#define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK 0x00000008L
-#define RLC_GPM_THREAD_RESET__RESERVED_MASK 0xFFFFFFF0L
-//RLC_GPM_CP_DMA_COMPLETE_T0
-#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA__SHIFT 0x0
-#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED__SHIFT 0x1
-#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA_MASK 0x00000001L
-#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED_MASK 0xFFFFFFFEL
-//RLC_GPM_CP_DMA_COMPLETE_T1
-#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA__SHIFT 0x0
-#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED__SHIFT 0x1
-#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA_MASK 0x00000001L
-#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED_MASK 0xFFFFFFFEL
-//RLC_FIREWALL_VIOLATION
-#define RLC_FIREWALL_VIOLATION__ADDR__SHIFT 0x0
-#define RLC_FIREWALL_VIOLATION__ADDR_MASK 0xFFFFFFFFL
-//RLC_GPM_STAT
-#define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0
-#define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1
-#define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2
-#define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3
-#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4
-#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5
-#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6
-#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7
-#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8
-#define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9
-#define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa
-#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb
-#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc
-#define RLC_GPM_STAT__STATIC_CU_POWERING_UP__SHIFT 0xd
-#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN__SHIFT 0xe
-#define RLC_GPM_STAT__DYN_CU_POWERING_UP__SHIFT 0xf
-#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN__SHIFT 0x10
-#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11
-#define RLC_GPM_STAT__CMP_power_status__SHIFT 0x12
-#define RLC_GPM_STAT__GFX_LS_STATUS_3D__SHIFT 0x13
-#define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D__SHIFT 0x14
-#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT 0x15
-#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT 0x16
-#define RLC_GPM_STAT__RESERVED__SHIFT 0x17
-#define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18
-#define RLC_GPM_STAT__RLC_BUSY_MASK 0x00000001L
-#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L
-#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L
-#define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x00000008L
-#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x00000010L
-#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x00000020L
-#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x00000040L
-#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x00000080L
-#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x00000100L
-#define RLC_GPM_STAT__SAVING_REGISTERS_MASK 0x00000200L
-#define RLC_GPM_STAT__RESTORING_REGISTERS_MASK 0x00000400L
-#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x00000800L
-#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x00001000L
-#define RLC_GPM_STAT__STATIC_CU_POWERING_UP_MASK 0x00002000L
-#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN_MASK 0x00004000L
-#define RLC_GPM_STAT__DYN_CU_POWERING_UP_MASK 0x00008000L
-#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN_MASK 0x00010000L
-#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x00020000L
-#define RLC_GPM_STAT__CMP_power_status_MASK 0x00040000L
-#define RLC_GPM_STAT__GFX_LS_STATUS_3D_MASK 0x00080000L
-#define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D_MASK 0x00100000L
-#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK 0x00200000L
-#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE_MASK 0x00400000L
-#define RLC_GPM_STAT__RESERVED_MASK 0x00800000L
-#define RLC_GPM_STAT__PG_ERROR_STATUS_MASK 0xFF000000L
-//RLC_GPU_CLOCK_32_RES_SEL
-#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0
-#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6
-#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x0000003FL
-#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xFFFFFFC0L
-//RLC_GPU_CLOCK_32
-#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0
-#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xFFFFFFFFL
-//RLC_PG_CNTL
-#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0
-#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1
-#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x2
-#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x3
-#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT 0x4
-#define RLC_PG_CNTL__RESERVED__SHIFT 0x5
-#define RLC_PG_CNTL__PG_OVERRIDE__SHIFT 0xe
-#define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT 0xf
-#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10
-#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x11
-#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x12
-#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE__SHIFT 0x13
-#define RLC_PG_CNTL__RESERVED1__SHIFT 0x14
-#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L
-#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L
-#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x00000004L
-#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x00000008L
-#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK 0x00000010L
-#define RLC_PG_CNTL__RESERVED_MASK 0x00003FE0L
-#define RLC_PG_CNTL__PG_OVERRIDE_MASK 0x00004000L
-#define RLC_PG_CNTL__CP_PG_DISABLE_MASK 0x00008000L
-#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x00010000L
-#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x00020000L
-#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x00040000L
-#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE_MASK 0x00080000L
-#define RLC_PG_CNTL__RESERVED1_MASK 0x00F00000L
-//RLC_GPM_THREAD_PRIORITY
-#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0
-#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8
-#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10
-#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18
-#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0x000000FFL
-#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0x0000FF00L
-#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0x00FF0000L
-#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xFF000000L
-//RLC_GPM_THREAD_ENABLE
-#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0
-#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1
-#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2
-#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3
-#define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4
-#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x00000001L
-#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x00000002L
-#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x00000004L
-#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x00000008L
-#define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xFFFFFFF0L
-//RLC_CGTT_MGCG_OVERRIDE
-#define RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE__SHIFT 0x0
-#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE__SHIFT 0x1
-#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE__SHIFT 0x2
-#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE__SHIFT 0x3
-#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE__SHIFT 0x4
-#define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE__SHIFT 0x5
-#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE__SHIFT 0x6
-#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE__SHIFT 0x7
-#define RLC_CGTT_MGCG_OVERRIDE__RESERVED__SHIFT 0x8
-#define RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK 0x00000001L
-#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK 0x00000002L
-#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK 0x00000004L
-#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK 0x00000008L
-#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK 0x00000010L
-#define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK 0x00000020L
-#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK 0x00000040L
-#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK 0x00000080L
-#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_MASK 0xFFFFFF00L
-//RLC_CGCG_CGLS_CTRL
-#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0
-#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1
-#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2
-#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8
-#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b
-#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c
-#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d
-#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT 0x1f
-#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L
-#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x00000002L
-#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000FCL
-#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07FFFF00L
-#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x08000000L
-#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L
-#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000L
-#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK 0x80000000L
-//RLC_CGCG_RAMP_CTRL
-#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0
-#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4
-#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8
-#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc
-#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10
-#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c
-#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0x0000000FL
-#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0x000000F0L
-#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0x00000F00L
-#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0x0000F000L
-#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0x0FFF0000L
-#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xF0000000L
-//RLC_DYN_PG_STATUS
-#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0
-#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xFFFFFFFFL
-//RLC_DYN_PG_REQUEST
-#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x0
-#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xFFFFFFFFL
-//RLC_PG_DELAY
-#define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0
-#define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8
-#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10
-#define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18
-#define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0x000000FFL
-#define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0x0000FF00L
-#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0x00FF0000L
-#define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xFF000000L
-//RLC_CU_STATUS
-#define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x0
-#define RLC_CU_STATUS__WORK_PENDING_MASK 0xFFFFFFFFL
-//RLC_LB_INIT_CU_MASK
-#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x0
-#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xFFFFFFFFL
-//RLC_LB_ALWAYS_ACTIVE_CU_MASK
-#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x0
-#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xFFFFFFFFL
-//RLC_LB_PARAMS
-#define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x0
-#define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x1
-#define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x8
-#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x10
-#define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x00000001L
-#define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0x000000FEL
-#define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0x0000FF00L
-#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xFFFF0000L
-//RLC_THREAD1_DELAY
-#define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x0
-#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x8
-#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x10
-#define RLC_THREAD1_DELAY__SPARE__SHIFT 0x18
-#define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0x000000FFL
-#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0x0000FF00L
-#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0x00FF0000L
-#define RLC_THREAD1_DELAY__SPARE_MASK 0xFF000000L
-//RLC_PG_ALWAYS_ON_CU_MASK
-#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x0
-#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xFFFFFFFFL
-//RLC_MAX_PG_CU
-#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x0
-#define RLC_MAX_PG_CU__SPARE__SHIFT 0x8
-#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0x000000FFL
-#define RLC_MAX_PG_CU__SPARE_MASK 0xFFFFFF00L
-//RLC_AUTO_PG_CTRL
-#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0
-#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1
-#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2
-#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3
-#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13
-#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L
-#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x00000002L
-#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L
-#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x0007FFF8L
-#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xFFF80000L
-//RLC_SMU_GRBM_REG_SAVE_CTRL
-#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x0
-#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x1
-#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x00000001L
-#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xFFFFFFFEL
-//RLC_SERDES_RD_MASTER_INDEX
-#define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x0
-#define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x4
-#define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x6
-#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x9
-#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0xc
-#define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0xd
-#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0x11
-#define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x13
-#define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0x0000000FL
-#define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x00000030L
-#define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x000001C0L
-#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x00000E00L
-#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x00001000L
-#define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x0001E000L
-#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0x00060000L
-#define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xFFF80000L
-//RLC_SERDES_RD_DATA_0
-#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0
-#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xFFFFFFFFL
-//RLC_SERDES_RD_DATA_1
-#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0
-#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xFFFFFFFFL
-//RLC_SERDES_RD_DATA_2
-#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0
-#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xFFFFFFFFL
-//RLC_SERDES_WR_CU_MASTER_MASK
-#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT 0x0
-#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK 0xFFFFFFFFL
-//RLC_SERDES_WR_NONCU_MASTER_MASK
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT 0x0
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT 0x10
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK__SHIFT 0x11
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT 0x12
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT 0x13
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT 0x14
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT 0x15
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT 0x16
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT 0x17
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK__SHIFT 0x18
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK__SHIFT 0x19
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT 0x1a
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK 0x0000FFFFL
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK 0x00010000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK_MASK 0x00020000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK 0x00040000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK 0x00080000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK 0x00100000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK 0x00200000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK 0x00400000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK 0x00800000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK_MASK 0x01000000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK_MASK 0x02000000L
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK 0xFC000000L
-//RLC_SERDES_WR_CTRL
-#define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x0
-#define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x8
-#define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x9
-#define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0xa
-#define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0xb
-#define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0xc
-#define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0xd
-#define RLC_SERDES_WR_CTRL__RDDATA_RESET__SHIFT 0xe
-#define RLC_SERDES_WR_CTRL__SHORT_FORMAT__SHIFT 0xf
-#define RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT 0x10
-#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE__SHIFT 0x1a
-#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR__SHIFT 0x1b
-#define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x1c
-#define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0x000000FFL
-#define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x00000100L
-#define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x00000200L
-#define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x00000400L
-#define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x00000800L
-#define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x00001000L
-#define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x00002000L
-#define RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK 0x00004000L
-#define RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK 0x00008000L
-#define RLC_SERDES_WR_CTRL__BPM_DATA_MASK 0x03FF0000L
-#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK 0x04000000L
-#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK 0x08000000L
-#define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xF0000000L
-//RLC_SERDES_WR_DATA
-#define RLC_SERDES_WR_DATA__DATA__SHIFT 0x0
-#define RLC_SERDES_WR_DATA__DATA_MASK 0xFFFFFFFFL
-//RLC_SERDES_CU_MASTER_BUSY
-#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT 0x0
-#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK 0xFFFFFFFFL
-//RLC_SERDES_NONCU_MASTER_BUSY
-#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT 0x0
-#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT 0x10
-#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY__SHIFT 0x11
-#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT 0x12
-#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT 0x13
-#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT 0x14
-#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT 0x15
-#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT 0x16
-#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT 0x17
-#define RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY__SHIFT 0x18
-#define RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY__SHIFT 0x19
-#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT 0x1a
-#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK 0x0000FFFFL
-#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK 0x00010000L
-#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY_MASK 0x00020000L
-#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK 0x00040000L
-#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK 0x00080000L
-#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK 0x00100000L
-#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK 0x00200000L
-#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK 0x00400000L
-#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK 0x00800000L
-#define RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY_MASK 0x01000000L
-#define RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY_MASK 0x02000000L
-#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK 0xFC000000L
-//RLC_GPM_GENERAL_0
-#define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_0__DATA_MASK 0xFFFFFFFFL
-//RLC_GPM_GENERAL_1
-#define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_1__DATA_MASK 0xFFFFFFFFL
-//RLC_GPM_GENERAL_2
-#define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_2__DATA_MASK 0xFFFFFFFFL
-//RLC_GPM_GENERAL_3
-#define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_3__DATA_MASK 0xFFFFFFFFL
-//RLC_GPM_GENERAL_4
-#define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_4__DATA_MASK 0xFFFFFFFFL
-//RLC_GPM_GENERAL_5
-#define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_5__DATA_MASK 0xFFFFFFFFL
-//RLC_GPM_GENERAL_6
-#define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_6__DATA_MASK 0xFFFFFFFFL
-//RLC_GPM_GENERAL_7
-#define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_7__DATA_MASK 0xFFFFFFFFL
-//RLC_GPM_SCRATCH_ADDR
-#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0
-#define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x9
-#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x000001FFL
-#define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xFFFFFE00L
-//RLC_GPM_SCRATCH_DATA
-#define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0
-#define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL
-//RLC_STATIC_PG_STATUS
-#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0
-#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xFFFFFFFFL
-//RLC_SPM_MC_CNTL
-#define RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT 0x0
-#define RLC_SPM_MC_CNTL__RLC_SPM_POLICY__SHIFT 0x4
-#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR__SHIFT 0x5
-#define RLC_SPM_MC_CNTL__RLC_SPM_FED__SHIFT 0x6
-#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER__SHIFT 0x7
-#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE__SHIFT 0x8
-#define RLC_SPM_MC_CNTL__RESERVED__SHIFT 0xa
-#define RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK 0x0000000FL
-#define RLC_SPM_MC_CNTL__RLC_SPM_POLICY_MASK 0x00000010L
-#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR_MASK 0x00000020L
-#define RLC_SPM_MC_CNTL__RLC_SPM_FED_MASK 0x00000040L
-#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER_MASK 0x00000080L
-#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_MASK 0x00000300L
-#define RLC_SPM_MC_CNTL__RESERVED_MASK 0xFFFFFC00L
-//RLC_SPM_INT_CNTL
-#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0
-#define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1
-#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x00000001L
-#define RLC_SPM_INT_CNTL__RESERVED_MASK 0xFFFFFFFEL
-//RLC_SPM_INT_STATUS
-#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0
-#define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1
-#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x00000001L
-#define RLC_SPM_INT_STATUS__RESERVED_MASK 0xFFFFFFFEL
-//RLC_SMU_MESSAGE
-#define RLC_SMU_MESSAGE__CMD__SHIFT 0x0
-#define RLC_SMU_MESSAGE__CMD_MASK 0xFFFFFFFFL
-//RLC_GPM_LOG_SIZE
-#define RLC_GPM_LOG_SIZE__SIZE__SHIFT 0x0
-#define RLC_GPM_LOG_SIZE__SIZE_MASK 0xFFFFFFFFL
-//RLC_PG_DELAY_3
-#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT 0x0
-#define RLC_PG_DELAY_3__RESERVED__SHIFT 0x8
-#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK 0x000000FFL
-#define RLC_PG_DELAY_3__RESERVED_MASK 0xFFFFFF00L
-//RLC_GPR_REG1
-#define RLC_GPR_REG1__DATA__SHIFT 0x0
-#define RLC_GPR_REG1__DATA_MASK 0xFFFFFFFFL
-//RLC_GPR_REG2
-#define RLC_GPR_REG2__DATA__SHIFT 0x0
-#define RLC_GPR_REG2__DATA_MASK 0xFFFFFFFFL
-//RLC_GPM_LOG_CONT
-#define RLC_GPM_LOG_CONT__CONT__SHIFT 0x0
-#define RLC_GPM_LOG_CONT__CONT_MASK 0xFFFFFFFFL
-//RLC_GPM_INT_DISABLE_TH0
-#define RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT 0x0
-#define RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK 0xFFFFFFFFL
-//RLC_GPM_INT_DISABLE_TH1
-#define RLC_GPM_INT_DISABLE_TH1__DISABLE__SHIFT 0x0
-#define RLC_GPM_INT_DISABLE_TH1__DISABLE_MASK 0xFFFFFFFFL
-//RLC_GPM_INT_FORCE_TH0
-#define RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT 0x0
-#define RLC_GPM_INT_FORCE_TH0__FORCE_MASK 0xFFFFFFFFL
-//RLC_GPM_INT_FORCE_TH1
-#define RLC_GPM_INT_FORCE_TH1__FORCE__SHIFT 0x0
-#define RLC_GPM_INT_FORCE_TH1__FORCE_MASK 0xFFFFFFFFL
-//RLC_SRM_CNTL
-#define RLC_SRM_CNTL__SRM_ENABLE__SHIFT 0x0
-#define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT 0x1
-#define RLC_SRM_CNTL__RESERVED__SHIFT 0x2
-#define RLC_SRM_CNTL__SRM_ENABLE_MASK 0x00000001L
-#define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK 0x00000002L
-#define RLC_SRM_CNTL__RESERVED_MASK 0xFFFFFFFCL
-//RLC_SRM_ARAM_ADDR
-#define RLC_SRM_ARAM_ADDR__ADDR__SHIFT 0x0
-#define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT 0xc
-#define RLC_SRM_ARAM_ADDR__ADDR_MASK 0x00000FFFL
-#define RLC_SRM_ARAM_ADDR__RESERVED_MASK 0xFFFFF000L
-//RLC_SRM_ARAM_DATA
-#define RLC_SRM_ARAM_DATA__DATA__SHIFT 0x0
-#define RLC_SRM_ARAM_DATA__DATA_MASK 0xFFFFFFFFL
-//RLC_SRM_DRAM_ADDR
-#define RLC_SRM_DRAM_ADDR__ADDR__SHIFT 0x0
-#define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT 0xc
-#define RLC_SRM_DRAM_ADDR__ADDR_MASK 0x00000FFFL
-#define RLC_SRM_DRAM_ADDR__RESERVED_MASK 0xFFFFF000L
-//RLC_SRM_DRAM_DATA
-#define RLC_SRM_DRAM_DATA__DATA__SHIFT 0x0
-#define RLC_SRM_DRAM_DATA__DATA_MASK 0xFFFFFFFFL
-//RLC_SRM_GPM_COMMAND
-#define RLC_SRM_GPM_COMMAND__OP__SHIFT 0x0
-#define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT 0x1
-#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT 0x2
-#define RLC_SRM_GPM_COMMAND__SIZE__SHIFT 0x5
-#define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT 0x11
-#define RLC_SRM_GPM_COMMAND__RESERVED1__SHIFT 0x1d
-#define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT 0x1f
-#define RLC_SRM_GPM_COMMAND__OP_MASK 0x00000001L
-#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK 0x00000002L
-#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK 0x0000001CL
-#define RLC_SRM_GPM_COMMAND__SIZE_MASK 0x0001FFE0L
-#define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK 0x1FFE0000L
-#define RLC_SRM_GPM_COMMAND__RESERVED1_MASK 0x60000000L
-#define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK 0x80000000L
-//RLC_SRM_GPM_COMMAND_STATUS
-#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0
-#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1
-#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT 0x2
-#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L
-#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L
-#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFFCL
-//RLC_SRM_RLCV_COMMAND
-#define RLC_SRM_RLCV_COMMAND__OP__SHIFT 0x0
-#define RLC_SRM_RLCV_COMMAND__RESERVED__SHIFT 0x1
-#define RLC_SRM_RLCV_COMMAND__SIZE__SHIFT 0x4
-#define RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT 0x10
-#define RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT 0x1c
-#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT 0x1f
-#define RLC_SRM_RLCV_COMMAND__OP_MASK 0x00000001L
-#define RLC_SRM_RLCV_COMMAND__RESERVED_MASK 0x0000000EL
-#define RLC_SRM_RLCV_COMMAND__SIZE_MASK 0x0000FFF0L
-#define RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK 0x0FFF0000L
-#define RLC_SRM_RLCV_COMMAND__RESERVED1_MASK 0x70000000L
-#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK 0x80000000L
-//RLC_SRM_RLCV_COMMAND_STATUS
-#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0
-#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1
-#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT 0x2
-#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L
-#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L
-#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFFCL
-//RLC_SRM_INDEX_CNTL_ADDR_0
-#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT 0x10
-#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK 0x0000FFFFL
-#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK 0xFFFF0000L
-//RLC_SRM_INDEX_CNTL_ADDR_1
-#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT 0x10
-#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK 0x0000FFFFL
-#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK 0xFFFF0000L
-//RLC_SRM_INDEX_CNTL_ADDR_2
-#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT 0x10
-#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK 0x0000FFFFL
-#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK 0xFFFF0000L
-//RLC_SRM_INDEX_CNTL_ADDR_3
-#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT 0x10
-#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK 0x0000FFFFL
-#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK 0xFFFF0000L
-//RLC_SRM_INDEX_CNTL_ADDR_4
-#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT 0x10
-#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK 0x0000FFFFL
-#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK 0xFFFF0000L
-//RLC_SRM_INDEX_CNTL_ADDR_5
-#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT 0x10
-#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK 0x0000FFFFL
-#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK 0xFFFF0000L
-//RLC_SRM_INDEX_CNTL_ADDR_6
-#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT 0x10
-#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK 0x0000FFFFL
-#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK 0xFFFF0000L
-//RLC_SRM_INDEX_CNTL_ADDR_7
-#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT 0x10
-#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK 0x0000FFFFL
-#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK 0xFFFF0000L
-//RLC_SRM_INDEX_CNTL_DATA_0
-#define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK 0xFFFFFFFFL
-//RLC_SRM_INDEX_CNTL_DATA_1
-#define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK 0xFFFFFFFFL
-//RLC_SRM_INDEX_CNTL_DATA_2
-#define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK 0xFFFFFFFFL
-//RLC_SRM_INDEX_CNTL_DATA_3
-#define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK 0xFFFFFFFFL
-//RLC_SRM_INDEX_CNTL_DATA_4
-#define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK 0xFFFFFFFFL
-//RLC_SRM_INDEX_CNTL_DATA_5
-#define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK 0xFFFFFFFFL
-//RLC_SRM_INDEX_CNTL_DATA_6
-#define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK 0xFFFFFFFFL
-//RLC_SRM_INDEX_CNTL_DATA_7
-#define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK 0xFFFFFFFFL
-//RLC_SRM_STAT
-#define RLC_SRM_STAT__SRM_BUSY__SHIFT 0x0
-#define RLC_SRM_STAT__SRM_BUSY_DELAY__SHIFT 0x1
-#define RLC_SRM_STAT__RESERVED__SHIFT 0x2
-#define RLC_SRM_STAT__SRM_BUSY_MASK 0x00000001L
-#define RLC_SRM_STAT__SRM_BUSY_DELAY_MASK 0x00000002L
-#define RLC_SRM_STAT__RESERVED_MASK 0xFFFFFFFCL
-//RLC_SRM_GPM_ABORT
-#define RLC_SRM_GPM_ABORT__ABORT__SHIFT 0x0
-#define RLC_SRM_GPM_ABORT__RESERVED__SHIFT 0x1
-#define RLC_SRM_GPM_ABORT__ABORT_MASK 0x00000001L
-#define RLC_SRM_GPM_ABORT__RESERVED_MASK 0xFFFFFFFEL
-//RLC_CSIB_ADDR_LO
-#define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT 0x0
-#define RLC_CSIB_ADDR_LO__ADDRESS_MASK 0xFFFFFFFFL
-//RLC_CSIB_ADDR_HI
-#define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT 0x0
-#define RLC_CSIB_ADDR_HI__ADDRESS_MASK 0x0000FFFFL
-//RLC_CSIB_LENGTH
-#define RLC_CSIB_LENGTH__LENGTH__SHIFT 0x0
-#define RLC_CSIB_LENGTH__LENGTH_MASK 0xFFFFFFFFL
-//RLC_SMU_COMMAND
-#define RLC_SMU_COMMAND__CMD__SHIFT 0x0
-#define RLC_SMU_COMMAND__CMD_MASK 0xFFFFFFFFL
-//RLC_CP_SCHEDULERS
-#define RLC_CP_SCHEDULERS__scheduler0__SHIFT 0x0
-#define RLC_CP_SCHEDULERS__scheduler1__SHIFT 0x8
-#define RLC_CP_SCHEDULERS__scheduler2__SHIFT 0x10
-#define RLC_CP_SCHEDULERS__scheduler3__SHIFT 0x18
-#define RLC_CP_SCHEDULERS__scheduler0_MASK 0x000000FFL
-#define RLC_CP_SCHEDULERS__scheduler1_MASK 0x0000FF00L
-#define RLC_CP_SCHEDULERS__scheduler2_MASK 0x00FF0000L
-#define RLC_CP_SCHEDULERS__scheduler3_MASK 0xFF000000L
-//RLC_SMU_ARGUMENT_1
-#define RLC_SMU_ARGUMENT_1__ARG__SHIFT 0x0
-#define RLC_SMU_ARGUMENT_1__ARG_MASK 0xFFFFFFFFL
-//RLC_SMU_ARGUMENT_2
-#define RLC_SMU_ARGUMENT_2__ARG__SHIFT 0x0
-#define RLC_SMU_ARGUMENT_2__ARG_MASK 0xFFFFFFFFL
-//RLC_GPM_GENERAL_8
-#define RLC_GPM_GENERAL_8__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_8__DATA_MASK 0xFFFFFFFFL
-//RLC_GPM_GENERAL_9
-#define RLC_GPM_GENERAL_9__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_9__DATA_MASK 0xFFFFFFFFL
-//RLC_GPM_GENERAL_10
-#define RLC_GPM_GENERAL_10__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_10__DATA_MASK 0xFFFFFFFFL
-//RLC_GPM_GENERAL_11
-#define RLC_GPM_GENERAL_11__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_11__DATA_MASK 0xFFFFFFFFL
-//RLC_GPM_GENERAL_12
-#define RLC_GPM_GENERAL_12__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_12__DATA_MASK 0xFFFFFFFFL
-//RLC_GPM_UTCL1_CNTL_0
-#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT__SHIFT 0x0
-#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE__SHIFT 0x18
-#define RLC_GPM_UTCL1_CNTL_0__BYPASS__SHIFT 0x19
-#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE__SHIFT 0x1a
-#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE__SHIFT 0x1b
-#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP__SHIFT 0x1c
-#define RLC_GPM_UTCL1_CNTL_0__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
-#define RLC_GPM_UTCL1_CNTL_0__RESERVED__SHIFT 0x1e
-#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
-#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE_MASK 0x01000000L
-#define RLC_GPM_UTCL1_CNTL_0__BYPASS_MASK 0x02000000L
-#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE_MASK 0x04000000L
-#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE_MASK 0x08000000L
-#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP_MASK 0x10000000L
-#define RLC_GPM_UTCL1_CNTL_0__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
-#define RLC_GPM_UTCL1_CNTL_0__RESERVED_MASK 0xC0000000L
-//RLC_GPM_UTCL1_CNTL_1
-#define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT__SHIFT 0x0
-#define RLC_GPM_UTCL1_CNTL_1__DROP_MODE__SHIFT 0x18
-#define RLC_GPM_UTCL1_CNTL_1__BYPASS__SHIFT 0x19
-#define RLC_GPM_UTCL1_CNTL_1__INVALIDATE__SHIFT 0x1a
-#define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE__SHIFT 0x1b
-#define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP__SHIFT 0x1c
-#define RLC_GPM_UTCL1_CNTL_1__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
-#define RLC_GPM_UTCL1_CNTL_1__RESERVED__SHIFT 0x1e
-#define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
-#define RLC_GPM_UTCL1_CNTL_1__DROP_MODE_MASK 0x01000000L
-#define RLC_GPM_UTCL1_CNTL_1__BYPASS_MASK 0x02000000L
-#define RLC_GPM_UTCL1_CNTL_1__INVALIDATE_MASK 0x04000000L
-#define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE_MASK 0x08000000L
-#define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP_MASK 0x10000000L
-#define RLC_GPM_UTCL1_CNTL_1__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
-#define RLC_GPM_UTCL1_CNTL_1__RESERVED_MASK 0xC0000000L
-//RLC_GPM_UTCL1_CNTL_2
-#define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT__SHIFT 0x0
-#define RLC_GPM_UTCL1_CNTL_2__DROP_MODE__SHIFT 0x18
-#define RLC_GPM_UTCL1_CNTL_2__BYPASS__SHIFT 0x19
-#define RLC_GPM_UTCL1_CNTL_2__INVALIDATE__SHIFT 0x1a
-#define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE__SHIFT 0x1b
-#define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP__SHIFT 0x1c
-#define RLC_GPM_UTCL1_CNTL_2__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
-#define RLC_GPM_UTCL1_CNTL_2__RESERVED__SHIFT 0x1e
-#define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
-#define RLC_GPM_UTCL1_CNTL_2__DROP_MODE_MASK 0x01000000L
-#define RLC_GPM_UTCL1_CNTL_2__BYPASS_MASK 0x02000000L
-#define RLC_GPM_UTCL1_CNTL_2__INVALIDATE_MASK 0x04000000L
-#define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE_MASK 0x08000000L
-#define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP_MASK 0x10000000L
-#define RLC_GPM_UTCL1_CNTL_2__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
-#define RLC_GPM_UTCL1_CNTL_2__RESERVED_MASK 0xC0000000L
-//RLC_SPM_UTCL1_CNTL
-#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
-#define RLC_SPM_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
-#define RLC_SPM_UTCL1_CNTL__BYPASS__SHIFT 0x19
-#define RLC_SPM_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
-#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
-#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
-#define RLC_SPM_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
-#define RLC_SPM_UTCL1_CNTL__RESERVED__SHIFT 0x1e
-#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
-#define RLC_SPM_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
-#define RLC_SPM_UTCL1_CNTL__BYPASS_MASK 0x02000000L
-#define RLC_SPM_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
-#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
-#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
-#define RLC_SPM_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
-#define RLC_SPM_UTCL1_CNTL__RESERVED_MASK 0xC0000000L
-//RLC_UTCL1_STATUS_2
-#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY__SHIFT 0x0
-#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY__SHIFT 0x1
-#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY__SHIFT 0x2
-#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY__SHIFT 0x3
-#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY__SHIFT 0x4
-#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans__SHIFT 0x5
-#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans__SHIFT 0x6
-#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans__SHIFT 0x7
-#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans__SHIFT 0x8
-#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans__SHIFT 0x9
-#define RLC_UTCL1_STATUS_2__RESERVED__SHIFT 0xa
-#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY_MASK 0x00000001L
-#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY_MASK 0x00000002L
-#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY_MASK 0x00000004L
-#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY_MASK 0x00000008L
-#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY_MASK 0x00000010L
-#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans_MASK 0x00000020L
-#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans_MASK 0x00000040L
-#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans_MASK 0x00000080L
-#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans_MASK 0x00000100L
-#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans_MASK 0x00000200L
-#define RLC_UTCL1_STATUS_2__RESERVED_MASK 0xFFFFFC00L
-//RLC_LB_THR_CONFIG_2
-#define RLC_LB_THR_CONFIG_2__DATA__SHIFT 0x0
-#define RLC_LB_THR_CONFIG_2__DATA_MASK 0xFFFFFFFFL
-//RLC_LB_THR_CONFIG_3
-#define RLC_LB_THR_CONFIG_3__DATA__SHIFT 0x0
-#define RLC_LB_THR_CONFIG_3__DATA_MASK 0xFFFFFFFFL
-//RLC_LB_THR_CONFIG_4
-#define RLC_LB_THR_CONFIG_4__DATA__SHIFT 0x0
-#define RLC_LB_THR_CONFIG_4__DATA_MASK 0xFFFFFFFFL
-//RLC_SPM_UTCL1_ERROR_1
-#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError__SHIFT 0x0
-#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2
-#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6
-#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError_MASK 0x00000003L
-#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL
-#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L
-//RLC_SPM_UTCL1_ERROR_2
-#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0
-#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL
-//RLC_GPM_UTCL1_TH0_ERROR_1
-#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError__SHIFT 0x0
-#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2
-#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6
-#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError_MASK 0x00000003L
-#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL
-#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L
-//RLC_LB_THR_CONFIG_1
-#define RLC_LB_THR_CONFIG_1__DATA__SHIFT 0x0
-#define RLC_LB_THR_CONFIG_1__DATA_MASK 0xFFFFFFFFL
-//RLC_GPM_UTCL1_TH0_ERROR_2
-#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0
-#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL
-//RLC_GPM_UTCL1_TH1_ERROR_1
-#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError__SHIFT 0x0
-#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2
-#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6
-#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError_MASK 0x00000003L
-#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL
-#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L
-//RLC_GPM_UTCL1_TH1_ERROR_2
-#define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0
-#define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL
-//RLC_GPM_UTCL1_TH2_ERROR_1
-#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError__SHIFT 0x0
-#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2
-#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6
-#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError_MASK 0x00000003L
-#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL
-#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L
-//RLC_GPM_UTCL1_TH2_ERROR_2
-#define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0
-#define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL
-//RLC_CGCG_CGLS_CTRL_3D
-#define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN__SHIFT 0x0
-#define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN__SHIFT 0x1
-#define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2
-#define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8
-#define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER__SHIFT 0x1b
-#define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL__SHIFT 0x1c
-#define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE__SHIFT 0x1d
-#define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN__SHIFT 0x1f
-#define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK 0x00000001L
-#define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK 0x00000002L
-#define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000FCL
-#define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07FFFF00L
-#define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER_MASK 0x08000000L
-#define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL_MASK 0x10000000L
-#define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE_MASK 0x60000000L
-#define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN_MASK 0x80000000L
-//RLC_CGCG_RAMP_CTRL_3D
-#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT__SHIFT 0x0
-#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT__SHIFT 0x4
-#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT__SHIFT 0x8
-#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT__SHIFT 0xc
-#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT__SHIFT 0x10
-#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT__SHIFT 0x1c
-#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT_MASK 0x0000000FL
-#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT_MASK 0x000000F0L
-#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT_MASK 0x00000F00L
-#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT_MASK 0x0000F000L
-#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT_MASK 0x0FFF0000L
-#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT_MASK 0xF0000000L
-//RLC_SEMAPHORE_0
-#define RLC_SEMAPHORE_0__CLIENT_ID__SHIFT 0x0
-#define RLC_SEMAPHORE_0__RESERVED__SHIFT 0x5
-#define RLC_SEMAPHORE_0__CLIENT_ID_MASK 0x0000001FL
-#define RLC_SEMAPHORE_0__RESERVED_MASK 0xFFFFFFE0L
-//RLC_SEMAPHORE_1
-#define RLC_SEMAPHORE_1__CLIENT_ID__SHIFT 0x0
-#define RLC_SEMAPHORE_1__RESERVED__SHIFT 0x5
-#define RLC_SEMAPHORE_1__CLIENT_ID_MASK 0x0000001FL
-#define RLC_SEMAPHORE_1__RESERVED_MASK 0xFFFFFFE0L
-//RLC_CP_EOF_INT
-#define RLC_CP_EOF_INT__INTERRUPT__SHIFT 0x0
-#define RLC_CP_EOF_INT__RESERVED__SHIFT 0x1
-#define RLC_CP_EOF_INT__INTERRUPT_MASK 0x00000001L
-#define RLC_CP_EOF_INT__RESERVED_MASK 0xFFFFFFFEL
-//RLC_CP_EOF_INT_CNT
-#define RLC_CP_EOF_INT_CNT__CNT__SHIFT 0x0
-#define RLC_CP_EOF_INT_CNT__CNT_MASK 0xFFFFFFFFL
-//RLC_SPARE_INT
-#define RLC_SPARE_INT__INTERRUPT__SHIFT 0x0
-#define RLC_SPARE_INT__RESERVED__SHIFT 0x1
-#define RLC_SPARE_INT__INTERRUPT_MASK 0x00000001L
-#define RLC_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL
-//RLC_PREWALKER_UTCL1_CNTL
-#define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
-#define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
-#define RLC_PREWALKER_UTCL1_CNTL__BYPASS__SHIFT 0x19
-#define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
-#define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
-#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
-#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
-#define RLC_PREWALKER_UTCL1_CNTL__RESERVED__SHIFT 0x1e
-#define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
-#define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
-#define RLC_PREWALKER_UTCL1_CNTL__BYPASS_MASK 0x02000000L
-#define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
-#define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
-#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
-#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
-#define RLC_PREWALKER_UTCL1_CNTL__RESERVED_MASK 0xC0000000L
-//RLC_PREWALKER_UTCL1_TRIG
-#define RLC_PREWALKER_UTCL1_TRIG__VALID__SHIFT 0x0
-#define RLC_PREWALKER_UTCL1_TRIG__VMID__SHIFT 0x1
-#define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE__SHIFT 0x5
-#define RLC_PREWALKER_UTCL1_TRIG__READ_PERM__SHIFT 0x6
-#define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM__SHIFT 0x7
-#define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM__SHIFT 0x8
-#define RLC_PREWALKER_UTCL1_TRIG__RESERVED__SHIFT 0x9
-#define RLC_PREWALKER_UTCL1_TRIG__READY__SHIFT 0x1f
-#define RLC_PREWALKER_UTCL1_TRIG__VALID_MASK 0x00000001L
-#define RLC_PREWALKER_UTCL1_TRIG__VMID_MASK 0x0000001EL
-#define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE_MASK 0x00000020L
-#define RLC_PREWALKER_UTCL1_TRIG__READ_PERM_MASK 0x00000040L
-#define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM_MASK 0x00000080L
-#define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM_MASK 0x00000100L
-#define RLC_PREWALKER_UTCL1_TRIG__RESERVED_MASK 0x7FFFFE00L
-#define RLC_PREWALKER_UTCL1_TRIG__READY_MASK 0x80000000L
-//RLC_PREWALKER_UTCL1_ADDR_LSB
-#define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB__SHIFT 0x0
-#define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB_MASK 0xFFFFFFFFL
-//RLC_PREWALKER_UTCL1_ADDR_MSB
-#define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB__SHIFT 0x0
-#define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB_MASK 0x0000FFFFL
-//RLC_PREWALKER_UTCL1_SIZE_LSB
-#define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB__SHIFT 0x0
-#define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB_MASK 0xFFFFFFFFL
-//RLC_PREWALKER_UTCL1_SIZE_MSB
-#define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB__SHIFT 0x0
-#define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB_MASK 0x00000003L
-//RLC_DSM_TRIG
-//RLC_UTCL1_STATUS
-#define RLC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
-#define RLC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
-#define RLC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
-#define RLC_UTCL1_STATUS__RESERVED__SHIFT 0x3
-#define RLC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
-#define RLC_UTCL1_STATUS__RESERVED_1__SHIFT 0xe
-#define RLC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
-#define RLC_UTCL1_STATUS__RESERVED_2__SHIFT 0x16
-#define RLC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
-#define RLC_UTCL1_STATUS__RESERVED_3__SHIFT 0x1e
-#define RLC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
-#define RLC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
-#define RLC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
-#define RLC_UTCL1_STATUS__RESERVED_MASK 0x000000F8L
-#define RLC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
-#define RLC_UTCL1_STATUS__RESERVED_1_MASK 0x0000C000L
-#define RLC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
-#define RLC_UTCL1_STATUS__RESERVED_2_MASK 0x00C00000L
-#define RLC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
-#define RLC_UTCL1_STATUS__RESERVED_3_MASK 0xC0000000L
-//RLC_R2I_CNTL_0
-#define RLC_R2I_CNTL_0__Data__SHIFT 0x0
-#define RLC_R2I_CNTL_0__Data_MASK 0xFFFFFFFFL
-//RLC_R2I_CNTL_1
-#define RLC_R2I_CNTL_1__Data__SHIFT 0x0
-#define RLC_R2I_CNTL_1__Data_MASK 0xFFFFFFFFL
-//RLC_R2I_CNTL_2
-#define RLC_R2I_CNTL_2__Data__SHIFT 0x0
-#define RLC_R2I_CNTL_2__Data_MASK 0xFFFFFFFFL
-//RLC_R2I_CNTL_3
-#define RLC_R2I_CNTL_3__Data__SHIFT 0x0
-#define RLC_R2I_CNTL_3__Data_MASK 0xFFFFFFFFL
-//RLC_UTCL2_CNTL
-#define RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x0
-#define RLC_UTCL2_CNTL__RESERVED__SHIFT 0x1
-#define RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE_MASK 0x00000001L
-#define RLC_UTCL2_CNTL__RESERVED_MASK 0xFFFFFFFEL
-//RLC_LBPW_CU_STAT
-#define RLC_LBPW_CU_STAT__MAX_CU__SHIFT 0x0
-#define RLC_LBPW_CU_STAT__ON_CU__SHIFT 0x10
-#define RLC_LBPW_CU_STAT__MAX_CU_MASK 0x0000FFFFL
-#define RLC_LBPW_CU_STAT__ON_CU_MASK 0xFFFF0000L
-//RLC_DS_CNTL
-#define RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK__SHIFT 0x0
-#define RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK__SHIFT 0x1
-#define RLC_DS_CNTL__RESRVED__SHIFT 0x2
-#define RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK__SHIFT 0x10
-#define RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK__SHIFT 0x11
-#define RLC_DS_CNTL__RESRVED_1__SHIFT 0x12
-#define RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK_MASK 0x00000001L
-#define RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK_MASK 0x00000002L
-#define RLC_DS_CNTL__RESRVED_MASK 0x0000FFFCL
-#define RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK_MASK 0x00010000L
-#define RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK_MASK 0x00020000L
-#define RLC_DS_CNTL__RESRVED_1_MASK 0xFFFC0000L
-//RLC_RLCV_SPARE_INT
-#define RLC_RLCV_SPARE_INT__INTERRUPT__SHIFT 0x0
-#define RLC_RLCV_SPARE_INT__RESERVED__SHIFT 0x1
-#define RLC_RLCV_SPARE_INT__INTERRUPT_MASK 0x00000001L
-#define RLC_RLCV_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL
-
-
-// addressBlock: gc_pwrdec
-//CGTS_SM_CTRL_REG
-#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0
-#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4
-#define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0xc
-#define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x10
-#define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x11
-#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14
-#define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x15
-#define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16
-#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x17
-#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x18
-#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0x0000000FL
-#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0x00000FF0L
-#define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x00001000L
-#define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x00010000L
-#define CGTS_SM_CTRL_REG__SM_MODE_MASK 0x000E0000L
-#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x00100000L
-#define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x00200000L
-#define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x00400000L
-#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x00800000L
-#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xFF000000L
-//CGTS_RD_CTRL_REG
-#define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x0
-#define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x8
-#define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x0000001FL
-#define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x00001F00L
-//CGTS_RD_REG
-#define CGTS_RD_REG__READ_DATA__SHIFT 0x0
-#define CGTS_RD_REG__READ_DATA_MASK 0x00003FFFL
-//CGTS_TCC_DISABLE
-#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10
-#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L
-//CGTS_USER_TCC_DISABLE
-#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10
-#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L
-//CGTS_CU0_SP0_CTRL_REG
-#define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU0_SP0_CTRL_REG__SP00_MASK 0x0000007FL
-#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU0_SP0_CTRL_REG__SP01_MASK 0x007F0000L
-#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU0_LDS_SQ_CTRL_REG
-#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
-#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
-#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU0_TA_SQC_CTRL_REG
-#define CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
-#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
-#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
-#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
-#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU0_SP1_CTRL_REG
-#define CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU0_SP1_CTRL_REG__SP10_MASK 0x0000007FL
-#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU0_SP1_CTRL_REG__SP11_MASK 0x007F0000L
-#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU0_TD_TCP_CTRL_REG
-#define CGTS_CU0_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
-#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
-#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU0_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
-#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
-#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU1_SP0_CTRL_REG
-#define CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU1_SP0_CTRL_REG__SP00_MASK 0x0000007FL
-#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU1_SP0_CTRL_REG__SP01_MASK 0x007F0000L
-#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU1_LDS_SQ_CTRL_REG
-#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
-#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
-#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU1_TA_SQC_CTRL_REG
-#define CGTS_CU1_TA_SQC_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU1_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
-#define CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-//CGTS_CU1_SP1_CTRL_REG
-#define CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU1_SP1_CTRL_REG__SP10_MASK 0x0000007FL
-#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU1_SP1_CTRL_REG__SP11_MASK 0x007F0000L
-#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU1_TD_TCP_CTRL_REG
-#define CGTS_CU1_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
-#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
-#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU1_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
-#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
-#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU2_SP0_CTRL_REG
-#define CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU2_SP0_CTRL_REG__SP00_MASK 0x0000007FL
-#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU2_SP0_CTRL_REG__SP01_MASK 0x007F0000L
-#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU2_LDS_SQ_CTRL_REG
-#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
-#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
-#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU2_TA_SQC_CTRL_REG
-#define CGTS_CU2_TA_SQC_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU2_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
-#define CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-//CGTS_CU2_SP1_CTRL_REG
-#define CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU2_SP1_CTRL_REG__SP10_MASK 0x0000007FL
-#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU2_SP1_CTRL_REG__SP11_MASK 0x007F0000L
-#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU2_TD_TCP_CTRL_REG
-#define CGTS_CU2_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
-#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
-#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU2_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
-#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
-#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU3_SP0_CTRL_REG
-#define CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU3_SP0_CTRL_REG__SP00_MASK 0x0000007FL
-#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU3_SP0_CTRL_REG__SP01_MASK 0x007F0000L
-#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU3_LDS_SQ_CTRL_REG
-#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
-#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
-#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU3_TA_SQC_CTRL_REG
-#define CGTS_CU3_TA_SQC_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU3_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
-#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
-#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU3_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
-#define CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
-#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU3_SP1_CTRL_REG
-#define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU3_SP1_CTRL_REG__SP10_MASK 0x0000007FL
-#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU3_SP1_CTRL_REG__SP11_MASK 0x007F0000L
-#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU3_TD_TCP_CTRL_REG
-#define CGTS_CU3_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
-#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
-#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU3_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
-#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
-#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU4_SP0_CTRL_REG
-#define CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU4_SP0_CTRL_REG__SP00_MASK 0x0000007FL
-#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU4_SP0_CTRL_REG__SP01_MASK 0x007F0000L
-#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU4_LDS_SQ_CTRL_REG
-#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
-#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
-#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU4_TA_SQC_CTRL_REG
-#define CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
-#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-//CGTS_CU4_SP1_CTRL_REG
-#define CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU4_SP1_CTRL_REG__SP10_MASK 0x0000007FL
-#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU4_SP1_CTRL_REG__SP11_MASK 0x007F0000L
-#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU4_TD_TCP_CTRL_REG
-#define CGTS_CU4_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
-#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
-#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU4_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
-#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
-#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU5_SP0_CTRL_REG
-#define CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU5_SP0_CTRL_REG__SP00_MASK 0x0000007FL
-#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x007F0000L
-#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU5_LDS_SQ_CTRL_REG
-#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
-#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
-#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU5_TA_SQC_CTRL_REG
-#define CGTS_CU5_TA_SQC_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU5_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
-#define CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-//CGTS_CU5_SP1_CTRL_REG
-#define CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU5_SP1_CTRL_REG__SP10_MASK 0x0000007FL
-#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU5_SP1_CTRL_REG__SP11_MASK 0x007F0000L
-#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU5_TD_TCP_CTRL_REG
-#define CGTS_CU5_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
-#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
-#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU5_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
-#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
-#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU6_SP0_CTRL_REG
-#define CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU6_SP0_CTRL_REG__SP00_MASK 0x0000007FL
-#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU6_SP0_CTRL_REG__SP01_MASK 0x007F0000L
-#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU6_LDS_SQ_CTRL_REG
-#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
-#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
-#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU6_TA_SQC_CTRL_REG
-#define CGTS_CU6_TA_SQC_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU6_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
-#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
-#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU6_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
-#define CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
-#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU6_SP1_CTRL_REG
-#define CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU6_SP1_CTRL_REG__SP10_MASK 0x0000007FL
-#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU6_SP1_CTRL_REG__SP11_MASK 0x007F0000L
-#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU6_TD_TCP_CTRL_REG
-#define CGTS_CU6_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
-#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
-#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU6_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
-#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
-#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU7_SP0_CTRL_REG
-#define CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU7_SP0_CTRL_REG__SP00_MASK 0x0000007FL
-#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU7_SP0_CTRL_REG__SP01_MASK 0x007F0000L
-#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU7_LDS_SQ_CTRL_REG
-#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
-#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
-#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU7_TA_SQC_CTRL_REG
-#define CGTS_CU7_TA_SQC_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU7_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
-#define CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-//CGTS_CU7_SP1_CTRL_REG
-#define CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU7_SP1_CTRL_REG__SP10_MASK 0x0000007FL
-#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU7_SP1_CTRL_REG__SP11_MASK 0x007F0000L
-#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU7_TD_TCP_CTRL_REG
-#define CGTS_CU7_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
-#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
-#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU7_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
-#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
-#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU8_SP0_CTRL_REG
-#define CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU8_SP0_CTRL_REG__SP00_MASK 0x0000007FL
-#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU8_SP0_CTRL_REG__SP01_MASK 0x007F0000L
-#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU8_LDS_SQ_CTRL_REG
-#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
-#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
-#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU8_TA_SQC_CTRL_REG
-#define CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
-#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-//CGTS_CU8_SP1_CTRL_REG
-#define CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU8_SP1_CTRL_REG__SP10_MASK 0x0000007FL
-#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU8_SP1_CTRL_REG__SP11_MASK 0x007F0000L
-#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU8_TD_TCP_CTRL_REG
-#define CGTS_CU8_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
-#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
-#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU8_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
-#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
-#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU9_SP0_CTRL_REG
-#define CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU9_SP0_CTRL_REG__SP00_MASK 0x0000007FL
-#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU9_SP0_CTRL_REG__SP01_MASK 0x007F0000L
-#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU9_LDS_SQ_CTRL_REG
-#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
-#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
-#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU9_TA_SQC_CTRL_REG
-#define CGTS_CU9_TA_SQC_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU9_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
-#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
-#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU9_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
-#define CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
-#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU9_SP1_CTRL_REG
-#define CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU9_SP1_CTRL_REG__SP10_MASK 0x0000007FL
-#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU9_SP1_CTRL_REG__SP11_MASK 0x007F0000L
-#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU9_TD_TCP_CTRL_REG
-#define CGTS_CU9_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
-#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
-#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU9_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
-#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
-#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU10_SP0_CTRL_REG
-#define CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU10_SP0_CTRL_REG__SP00_MASK 0x0000007FL
-#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU10_SP0_CTRL_REG__SP01_MASK 0x007F0000L
-#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU10_LDS_SQ_CTRL_REG
-#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
-#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
-#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU10_TA_SQC_CTRL_REG
-#define CGTS_CU10_TA_SQC_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU10_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
-#define CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-//CGTS_CU10_SP1_CTRL_REG
-#define CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU10_SP1_CTRL_REG__SP10_MASK 0x0000007FL
-#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU10_SP1_CTRL_REG__SP11_MASK 0x007F0000L
-#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU10_TD_TCP_CTRL_REG
-#define CGTS_CU10_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
-#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
-#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU10_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
-#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
-#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU11_SP0_CTRL_REG
-#define CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU11_SP0_CTRL_REG__SP00_MASK 0x0000007FL
-#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU11_SP0_CTRL_REG__SP01_MASK 0x007F0000L
-#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU11_LDS_SQ_CTRL_REG
-#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
-#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
-#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU11_TA_SQC_CTRL_REG
-#define CGTS_CU11_TA_SQC_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU11_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
-#define CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-//CGTS_CU11_SP1_CTRL_REG
-#define CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU11_SP1_CTRL_REG__SP10_MASK 0x0000007FL
-#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU11_SP1_CTRL_REG__SP11_MASK 0x007F0000L
-#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU11_TD_TCP_CTRL_REG
-#define CGTS_CU11_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
-#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
-#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU11_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
-#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
-#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU12_SP0_CTRL_REG
-#define CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU12_SP0_CTRL_REG__SP00_MASK 0x0000007FL
-#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU12_SP0_CTRL_REG__SP01_MASK 0x007F0000L
-#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU12_LDS_SQ_CTRL_REG
-#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
-#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
-#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU12_TA_SQC_CTRL_REG
-#define CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
-#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
-#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
-#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
-#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU12_SP1_CTRL_REG
-#define CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU12_SP1_CTRL_REG__SP10_MASK 0x0000007FL
-#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU12_SP1_CTRL_REG__SP11_MASK 0x007F0000L
-#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU12_TD_TCP_CTRL_REG
-#define CGTS_CU12_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
-#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
-#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU12_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
-#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
-#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU13_SP0_CTRL_REG
-#define CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU13_SP0_CTRL_REG__SP00_MASK 0x0000007FL
-#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU13_SP0_CTRL_REG__SP01_MASK 0x007F0000L
-#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU13_LDS_SQ_CTRL_REG
-#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
-#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
-#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU13_TA_SQC_CTRL_REG
-#define CGTS_CU13_TA_SQC_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU13_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
-#define CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-//CGTS_CU13_SP1_CTRL_REG
-#define CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU13_SP1_CTRL_REG__SP10_MASK 0x0000007FL
-#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU13_SP1_CTRL_REG__SP11_MASK 0x007F0000L
-#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU13_TD_TCP_CTRL_REG
-#define CGTS_CU13_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
-#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
-#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU13_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
-#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
-#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU14_SP0_CTRL_REG
-#define CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU14_SP0_CTRL_REG__SP00_MASK 0x0000007FL
-#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU14_SP0_CTRL_REG__SP01_MASK 0x007F0000L
-#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU14_LDS_SQ_CTRL_REG
-#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
-#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
-#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU14_TA_SQC_CTRL_REG
-#define CGTS_CU14_TA_SQC_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU14_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
-#define CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-//CGTS_CU14_SP1_CTRL_REG
-#define CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU14_SP1_CTRL_REG__SP10_MASK 0x0000007FL
-#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU14_SP1_CTRL_REG__SP11_MASK 0x007F0000L
-#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU14_TD_TCP_CTRL_REG
-#define CGTS_CU14_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
-#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
-#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU14_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
-#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
-#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU15_SP0_CTRL_REG
-#define CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU15_SP0_CTRL_REG__SP00_MASK 0x0000007FL
-#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU15_SP0_CTRL_REG__SP01_MASK 0x007F0000L
-#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU15_LDS_SQ_CTRL_REG
-#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
-#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
-#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU15_TA_SQC_CTRL_REG
-#define CGTS_CU15_TA_SQC_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU15_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
-#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
-#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU15_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
-#define CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
-#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU15_SP1_CTRL_REG
-#define CGTS_CU15_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU15_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU15_SP1_CTRL_REG__SP10_MASK 0x0000007FL
-#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU15_SP1_CTRL_REG__SP11_MASK 0x007F0000L
-#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU15_TD_TCP_CTRL_REG
-#define CGTS_CU15_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
-#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
-#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU15_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
-#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
-#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
-#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
-#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
-#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
-//CGTS_CU0_TCPI_CTRL_REG
-#define CGTS_CU0_TCPI_CTRL_REG__TCPI__SHIFT 0x0
-#define CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
-#define CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU0_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
-#define CGTS_CU0_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
-#define CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU0_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
-//CGTS_CU1_TCPI_CTRL_REG
-#define CGTS_CU1_TCPI_CTRL_REG__TCPI__SHIFT 0x0
-#define CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
-#define CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU1_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
-#define CGTS_CU1_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
-#define CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU1_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
-//CGTS_CU2_TCPI_CTRL_REG
-#define CGTS_CU2_TCPI_CTRL_REG__TCPI__SHIFT 0x0
-#define CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
-#define CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU2_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
-#define CGTS_CU2_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
-#define CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU2_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
-//CGTS_CU3_TCPI_CTRL_REG
-#define CGTS_CU3_TCPI_CTRL_REG__TCPI__SHIFT 0x0
-#define CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
-#define CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU3_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
-#define CGTS_CU3_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
-#define CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU3_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
-//CGTS_CU4_TCPI_CTRL_REG
-#define CGTS_CU4_TCPI_CTRL_REG__TCPI__SHIFT 0x0
-#define CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
-#define CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU4_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
-#define CGTS_CU4_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
-#define CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU4_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
-//CGTS_CU5_TCPI_CTRL_REG
-#define CGTS_CU5_TCPI_CTRL_REG__TCPI__SHIFT 0x0
-#define CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
-#define CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU5_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
-#define CGTS_CU5_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
-#define CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU5_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
-//CGTS_CU6_TCPI_CTRL_REG
-#define CGTS_CU6_TCPI_CTRL_REG__TCPI__SHIFT 0x0
-#define CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
-#define CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU6_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
-#define CGTS_CU6_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
-#define CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU6_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
-//CGTS_CU7_TCPI_CTRL_REG
-#define CGTS_CU7_TCPI_CTRL_REG__TCPI__SHIFT 0x0
-#define CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
-#define CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU7_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
-#define CGTS_CU7_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
-#define CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU7_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
-//CGTS_CU8_TCPI_CTRL_REG
-#define CGTS_CU8_TCPI_CTRL_REG__TCPI__SHIFT 0x0
-#define CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
-#define CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU8_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
-#define CGTS_CU8_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
-#define CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU8_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
-//CGTS_CU9_TCPI_CTRL_REG
-#define CGTS_CU9_TCPI_CTRL_REG__TCPI__SHIFT 0x0
-#define CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
-#define CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU9_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
-#define CGTS_CU9_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
-#define CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU9_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
-//CGTS_CU10_TCPI_CTRL_REG
-#define CGTS_CU10_TCPI_CTRL_REG__TCPI__SHIFT 0x0
-#define CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
-#define CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU10_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
-#define CGTS_CU10_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
-#define CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU10_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
-//CGTS_CU11_TCPI_CTRL_REG
-#define CGTS_CU11_TCPI_CTRL_REG__TCPI__SHIFT 0x0
-#define CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
-#define CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU11_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
-#define CGTS_CU11_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
-#define CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU11_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
-//CGTS_CU12_TCPI_CTRL_REG
-#define CGTS_CU12_TCPI_CTRL_REG__TCPI__SHIFT 0x0
-#define CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
-#define CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU12_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
-#define CGTS_CU12_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
-#define CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU12_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
-//CGTS_CU13_TCPI_CTRL_REG
-#define CGTS_CU13_TCPI_CTRL_REG__TCPI__SHIFT 0x0
-#define CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
-#define CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU13_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
-#define CGTS_CU13_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
-#define CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU13_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
-//CGTS_CU14_TCPI_CTRL_REG
-#define CGTS_CU14_TCPI_CTRL_REG__TCPI__SHIFT 0x0
-#define CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
-#define CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU14_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
-#define CGTS_CU14_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
-#define CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU14_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
-//CGTS_CU15_TCPI_CTRL_REG
-#define CGTS_CU15_TCPI_CTRL_REG__TCPI__SHIFT 0x0
-#define CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
-#define CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU15_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
-#define CGTS_CU15_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
-#define CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
-#define CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
-#define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
-#define CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
-#define CGTS_CU15_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
-//CGTT_SPI_CLK_CTRL
-#define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12
-#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18
-#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x1a
-#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b
-#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c
-#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d
-#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e
-#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
-#define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00FC0000L
-#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L
-#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x04000000L
-#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L
-#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L
-#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L
-#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L
-#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
-//CGTT_PC_CLK_CTRL
-#define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12
-#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18
-#define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE__SHIFT 0x19
-#define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE__SHIFT 0x1a
-#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b
-#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c
-#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d
-#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e
-#define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
-#define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00FC0000L
-#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L
-#define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE_MASK 0x02000000L
-#define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE_MASK 0x04000000L
-#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L
-#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L
-#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L
-#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L
-#define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
-//CGTT_BCI_CLK_CTRL
-#define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0xc
-#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x18
-#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x19
-#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x1a
-#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b
-#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c
-#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d
-#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e
-#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
-#define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0x0000F000L
-#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x01000000L
-#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x02000000L
-#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x04000000L
-#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L
-#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L
-#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L
-#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L
-#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
-//CGTT_VGT_CLK_CTRL
-#define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0xf
-#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9__SHIFT 0x18
-#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8__SHIFT 0x19
-#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x1a
-#define CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT 0x1b
-#define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x1c
-#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x1d
-#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
-#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
-#define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L
-#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9_MASK 0x01000000L
-#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8_MASK 0x02000000L
-#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x04000000L
-#define CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE_MASK 0x08000000L
-#define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000L
-#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK 0x20000000L
-#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L
-#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
-//CGTT_IA_CLK_CTRL
-#define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x19
-#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
-#define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
-#define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
-#define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x02000000L
-#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
-#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
-#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
-#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L
-#define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
-//CGTT_WD_CLK_CTRL
-#define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT 0xf
-#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8__SHIFT 0x19
-#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x1a
-#define CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT 0x1b
-#define CGTT_WD_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x1c
-#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d
-#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x1e
-#define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
-#define CGTT_WD_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L
-#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8_MASK 0x02000000L
-#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x04000000L
-#define CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE_MASK 0x08000000L
-#define CGTT_WD_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000L
-#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000L
-#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000L
-#define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
-//CGTT_PA_CLK_CTRL
-#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d
-#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e
-#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x1f
-#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
-#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
-#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
-#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
-#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
-#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000L
-#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000L
-#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000L
-//CGTT_SC_CLK_CTRL0
-#define CGTT_SC_CLK_CTRL0__ON_DELAY__SHIFT 0x0
-#define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE__SHIFT 0x10
-#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x11
-#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x12
-#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x13
-#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x14
-#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x15
-#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x16
-#define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE__SHIFT 0x17
-#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE__SHIFT 0x18
-#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x19
-#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1a
-#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1b
-#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1c
-#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1d
-#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1e
-#define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT 0x1f
-#define CGTT_SC_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL
-#define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE_MASK 0x00010000L
-#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00020000L
-#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00040000L
-#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00080000L
-#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00100000L
-#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00200000L
-#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00400000L
-#define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE_MASK 0x00800000L
-#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE_MASK 0x01000000L
-#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x02000000L
-#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x04000000L
-#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x08000000L
-#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x10000000L
-#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x20000000L
-#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x40000000L
-#define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE_MASK 0x80000000L
-//CGTT_SC_CLK_CTRL1
-#define CGTT_SC_CLK_CTRL1__ON_DELAY__SHIFT 0x0
-#define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE__SHIFT 0x11
-#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE__SHIFT 0x12
-#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE__SHIFT 0x13
-#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE__SHIFT 0x14
-#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE__SHIFT 0x15
-#define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE__SHIFT 0x16
-#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE__SHIFT 0x19
-#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE__SHIFT 0x1a
-#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE__SHIFT 0x1b
-#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE__SHIFT 0x1c
-#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE__SHIFT 0x1d
-#define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE__SHIFT 0x1e
-#define CGTT_SC_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL
-#define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE_MASK 0x00020000L
-#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE_MASK 0x00040000L
-#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE_MASK 0x00080000L
-#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE_MASK 0x00100000L
-#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE_MASK 0x00200000L
-#define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE_MASK 0x00400000L
-#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE_MASK 0x02000000L
-#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE_MASK 0x04000000L
-#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE_MASK 0x08000000L
-#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE_MASK 0x10000000L
-#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE_MASK 0x20000000L
-#define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE_MASK 0x40000000L
-//CGTT_SQ_CLK_CTRL
-#define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d
-#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
-#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
-#define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000L
-#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L
-#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
-//CGTT_SQG_CLK_CTRL
-#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT 0x1c
-#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d
-#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
-#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
-#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK 0x10000000L
-#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000L
-#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L
-#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
-//SQ_ALU_CLK_CTRL
-#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
-#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
-#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL
-#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L
-//SQ_TEX_CLK_CTRL
-#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
-#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
-#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL
-#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L
-//SQ_LDS_CLK_CTRL
-#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
-#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
-#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL
-#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L
-//SQ_POWER_THROTTLE
-#define SQ_POWER_THROTTLE__MIN_POWER__SHIFT 0x0
-#define SQ_POWER_THROTTLE__MAX_POWER__SHIFT 0x10
-#define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT 0x1e
-#define SQ_POWER_THROTTLE__MIN_POWER_MASK 0x00003FFFL
-#define SQ_POWER_THROTTLE__MAX_POWER_MASK 0x3FFF0000L
-#define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK 0xC0000000L
-//SQ_POWER_THROTTLE2
-#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT 0x0
-#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
-#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
-#define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT 0x1f
-#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK 0x00003FFFL
-#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
-#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
-#define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK 0x80000000L
-//CGTT_SX_CLK_CTRL0
-#define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x0
-#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0xc
-#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
-#define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL
-#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0x0000F000L
-#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L
-//CGTT_SX_CLK_CTRL1
-#define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x0
-#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0xc
-#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x1f
-#define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL
-#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0x0000F000L
-#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x02000000L
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x04000000L
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x08000000L
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000L
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000L
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000L
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000L
-//CGTT_SX_CLK_CTRL2
-#define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x0
-#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0xd
-#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x1f
-#define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0x0000000FL
-#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0x0000E000L
-#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x02000000L
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x04000000L
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x08000000L
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000L
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000L
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000L
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000L
-//CGTT_SX_CLK_CTRL3
-#define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x0
-#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0xd
-#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x1f
-#define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0x0000000FL
-#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0x0000E000L
-#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x02000000L
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x04000000L
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x08000000L
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000L
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000L
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000L
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000L
-//CGTT_SX_CLK_CTRL4
-#define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x0
-#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0xc
-#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x19
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x1a
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x1d
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x1e
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x1f
-#define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0x0000000FL
-#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0x0000F000L
-#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x02000000L
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x04000000L
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x08000000L
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000L
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000L
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000L
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000L
-//TD_CGTT_CTRL
-#define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x0
-#define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
-#define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
-#define TD_CGTT_CTRL__ON_DELAY_MASK 0x0000000FL
-#define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
-#define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
-#define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
-#define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
-#define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
-#define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
-#define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
-#define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
-//TA_CGTT_CTRL
-#define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x0
-#define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
-#define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
-#define TA_CGTT_CTRL__ON_DELAY_MASK 0x0000000FL
-#define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
-#define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
-#define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
-#define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
-#define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
-#define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
-#define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
-#define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
-//CGTT_TCPI_CLK_CTRL
-#define CGTT_TCPI_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_TCPI_CLK_CTRL__SPARE__SHIFT 0xc
-#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
-#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
-#define CGTT_TCPI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_TCPI_CLK_CTRL__SPARE_MASK 0x0000F000L
-#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
-#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
-#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
-#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
-#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
-#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
-#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
-#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
-//CGTT_TCI_CLK_CTRL
-#define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
-#define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
-//CGTT_GDS_CLK_CTRL
-#define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
-#define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
-//DB_CGTT_CLK_CTRL_0
-#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x0
-#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x4
-#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0xc
-#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x18
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x19
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x1a
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x1b
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x1c
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1e
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x1f
-#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0x0000000FL
-#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0x0000F000L
-#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x01000000L
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x02000000L
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x04000000L
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x08000000L
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000L
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000L
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000L
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000L
-//CB_CGTT_SCLK_CTRL
-#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
-#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
-//TCC_CGTT_SCLK_CTRL
-#define TCC_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
-#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
-#define TCC_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
-//TCA_CGTT_SCLK_CTRL
-#define TCA_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
-#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
-#define TCA_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
-//CGTT_CP_CLK_CTRL
-#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
-#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
-#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
-#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
-#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
-#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L
-#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
-#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
-//CGTT_CPF_CLK_CTRL
-#define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
-#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
-#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
-#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
-#define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
-#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L
-#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
-#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
-//CGTT_CPC_CLK_CTRL
-#define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
-#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
-#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
-#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
-#define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
-#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L
-#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
-#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
-//RLC_PWR_CTRL
-#define RLC_PWR_CTRL__MON_CGPG_RTN_EN__SHIFT 0x0
-#define RLC_PWR_CTRL__RESERVED__SHIFT 0x1
-#define RLC_PWR_CTRL__DLDO_STATUS__SHIFT 0x8
-#define RLC_PWR_CTRL__MON_CGPG_RTN_EN_MASK 0x00000001L
-#define RLC_PWR_CTRL__RESERVED_MASK 0x000000FEL
-#define RLC_PWR_CTRL__DLDO_STATUS_MASK 0x00000100L
-//CGTT_RLC_CLK_CTRL
-#define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
-#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
-#define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
-#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
-//RLC_GFX_RM_CNTL
-#define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID__SHIFT 0x0
-#define RLC_GFX_RM_CNTL__RESERVED__SHIFT 0x1
-#define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID_MASK 0x00000001L
-#define RLC_GFX_RM_CNTL__RESERVED_MASK 0xFFFFFFFEL
-//RMI_CGTT_SCLK_CTRL
-#define RMI_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
-#define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
-#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
-#define RMI_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
-#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
-#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
-#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
-#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
-#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
-#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
-//CGTT_TCPF_CLK_CTRL
-#define CGTT_TCPF_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_TCPF_CLK_CTRL__SPARE__SHIFT 0xc
-#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
-#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
-#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
-#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
-#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
-#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
-#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
-#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
-#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
-#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
-#define CGTT_TCPF_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define CGTT_TCPF_CLK_CTRL__SPARE_MASK 0x0000F000L
-#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
-#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
-#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
-#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
-#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
-#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
-#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
-#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
-#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
-#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
-#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
-#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
-#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
-#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
-#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
-#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
-
-
-// addressBlock: gc_ea_pwrdec
-//GCEA_CGTT_CLK_CTRL
-#define GCEA_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
-#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e
-#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f
-#define GCEA_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
-#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L
-#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L
-
-
-// addressBlock: gc_utcl2_vmsharedhvdec
-//MC_VM_FB_SIZE_OFFSET_VF0
-#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF1
-#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF2
-#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF3
-#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF4
-#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF5
-#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF6
-#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF7
-#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF8
-#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF9
-#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF10
-#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF11
-#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF12
-#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF13
-#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF14
-#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF15
-#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L
-//VM_IOMMU_MMIO_CNTRL_1
-#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT 0x8
-#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK 0x00000100L
-//MC_VM_MARC_BASE_LO_0
-#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc
-#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L
-//MC_VM_MARC_BASE_LO_1
-#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc
-#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L
-//MC_VM_MARC_BASE_LO_2
-#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc
-#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L
-//MC_VM_MARC_BASE_LO_3
-#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc
-#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L
-//MC_VM_MARC_BASE_HI_0
-#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0
-#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL
-//MC_VM_MARC_BASE_HI_1
-#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0
-#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL
-//MC_VM_MARC_BASE_HI_2
-#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0
-#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL
-//MC_VM_MARC_BASE_HI_3
-#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0
-#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL
-//MC_VM_MARC_RELOC_LO_0
-#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0
-#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1
-#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc
-#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L
-#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L
-#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L
-//MC_VM_MARC_RELOC_LO_1
-#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0
-#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1
-#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc
-#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L
-#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L
-#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L
-//MC_VM_MARC_RELOC_LO_2
-#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0
-#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1
-#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc
-#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L
-#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L
-#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L
-//MC_VM_MARC_RELOC_LO_3
-#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0
-#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1
-#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc
-#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L
-#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L
-#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L
-//MC_VM_MARC_RELOC_HI_0
-#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0
-#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL
-//MC_VM_MARC_RELOC_HI_1
-#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0
-#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL
-//MC_VM_MARC_RELOC_HI_2
-#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0
-#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL
-//MC_VM_MARC_RELOC_HI_3
-#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0
-#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL
-//MC_VM_MARC_LEN_LO_0
-#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc
-#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L
-//MC_VM_MARC_LEN_LO_1
-#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc
-#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L
-//MC_VM_MARC_LEN_LO_2
-#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc
-#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L
-//MC_VM_MARC_LEN_LO_3
-#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc
-#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L
-//MC_VM_MARC_LEN_HI_0
-#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0
-#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL
-//MC_VM_MARC_LEN_HI_1
-#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0
-#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL
-//MC_VM_MARC_LEN_HI_2
-#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0
-#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL
-//MC_VM_MARC_LEN_HI_3
-#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0
-#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL
-//VM_IOMMU_CONTROL_REGISTER
-#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0
-#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L
-//VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER
-#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd
-#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L
-//VM_PCIE_ATS_CNTL
-#define VM_PCIE_ATS_CNTL__STU__SHIFT 0x10
-#define VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L
-#define VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_0
-#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_1
-#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_2
-#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_3
-#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_4
-#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_5
-#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_6
-#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_7
-#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_8
-#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_9
-#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_10
-#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_11
-#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_12
-#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_13
-#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_14
-#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_15
-#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L
-//UTCL2_CGTT_CLK_CTRL
-#define UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT 0xc
-#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
-#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10
-#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18
-#define UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK 0x00007000L
-#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
-#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
-#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
-
-
-// addressBlock: gc_hypdec
-//CP_HYP_PFP_UCODE_ADDR
-#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
-#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL
-//CP_PFP_UCODE_ADDR
-#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
-#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL
-//CP_HYP_PFP_UCODE_DATA
-#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0
-#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
-//CP_PFP_UCODE_DATA
-#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0
-#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
-//CP_HYP_ME_UCODE_ADDR
-#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
-#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR_MASK 0x00001FFFL
-//CP_ME_RAM_RADDR
-#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0
-#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x00001FFFL
-//CP_ME_RAM_WADDR
-#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0
-#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x00001FFFL
-//CP_HYP_ME_UCODE_DATA
-#define CP_HYP_ME_UCODE_DATA__UCODE_DATA__SHIFT 0x0
-#define CP_HYP_ME_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
-//CP_ME_RAM_DATA
-#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0
-#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xFFFFFFFFL
-//CP_CE_UCODE_ADDR
-#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
-#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL
-//CP_HYP_CE_UCODE_ADDR
-#define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
-#define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL
-//CP_CE_UCODE_DATA
-#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0
-#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
-//CP_HYP_CE_UCODE_DATA
-#define CP_HYP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0
-#define CP_HYP_CE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
-//CP_HYP_MEC1_UCODE_ADDR
-#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
-#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL
-//CP_MEC_ME1_UCODE_ADDR
-#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
-#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL
-//CP_HYP_MEC1_UCODE_DATA
-#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA__SHIFT 0x0
-#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
-//CP_MEC_ME1_UCODE_DATA
-#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0
-#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
-//CP_HYP_MEC2_UCODE_ADDR
-#define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
-#define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL
-//CP_MEC_ME2_UCODE_ADDR
-#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
-#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL
-//CP_HYP_MEC2_UCODE_DATA
-#define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA__SHIFT 0x0
-#define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
-//CP_MEC_ME2_UCODE_DATA
-#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0
-#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
-//RLC_GPM_UCODE_ADDR
-#define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
-#define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xe
-#define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL
-#define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xFFFFC000L
-//RLC_GPM_UCODE_DATA
-#define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0
-#define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
-//GRBM_GFX_INDEX_SR_SELECT
-#define GRBM_GFX_INDEX_SR_SELECT__INDEX__SHIFT 0x0
-#define GRBM_GFX_INDEX_SR_SELECT__INDEX_MASK 0x00000007L
-//GRBM_GFX_INDEX_SR_DATA
-#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX__SHIFT 0x0
-#define GRBM_GFX_INDEX_SR_DATA__SH_INDEX__SHIFT 0x8
-#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX__SHIFT 0x10
-#define GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES__SHIFT 0x1d
-#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e
-#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES__SHIFT 0x1f
-#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX_MASK 0x000000FFL
-#define GRBM_GFX_INDEX_SR_DATA__SH_INDEX_MASK 0x0000FF00L
-#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX_MASK 0x00FF0000L
-#define GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES_MASK 0x20000000L
-#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L
-#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES_MASK 0x80000000L
-//GRBM_GFX_CNTL_SR_SELECT
-#define GRBM_GFX_CNTL_SR_SELECT__INDEX__SHIFT 0x0
-#define GRBM_GFX_CNTL_SR_SELECT__INDEX_MASK 0x00000007L
-//GRBM_GFX_CNTL_SR_DATA
-#define GRBM_GFX_CNTL_SR_DATA__PIPEID__SHIFT 0x0
-#define GRBM_GFX_CNTL_SR_DATA__MEID__SHIFT 0x2
-#define GRBM_GFX_CNTL_SR_DATA__VMID__SHIFT 0x4
-#define GRBM_GFX_CNTL_SR_DATA__QUEUEID__SHIFT 0x8
-#define GRBM_GFX_CNTL_SR_DATA__PIPEID_MASK 0x00000003L
-#define GRBM_GFX_CNTL_SR_DATA__MEID_MASK 0x0000000CL
-#define GRBM_GFX_CNTL_SR_DATA__VMID_MASK 0x000000F0L
-#define GRBM_GFX_CNTL_SR_DATA__QUEUEID_MASK 0x00000700L
-//GRBM_CAM_INDEX
-#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0
-#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x00000007L
-//GRBM_HYP_CAM_INDEX
-#define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT 0x0
-#define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK 0x00000007L
-//GRBM_CAM_DATA
-#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0
-#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
-#define GRBM_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL
-#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L
-//GRBM_HYP_CAM_DATA
-#define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT 0x0
-#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
-#define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL
-#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L
-//RLC_GPU_IOV_VF_ENABLE
-#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT 0x0
-#define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT 0x1
-#define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT 0x10
-#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK 0x00000001L
-#define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK 0x0000FFFEL
-#define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK 0xFFFF0000L
-//RLC_GFX_RM_CNTL_ADJ
-#define RLC_GFX_RM_CNTL_ADJ__RLC_GFX_RM_VALID__SHIFT 0x0
-#define RLC_GFX_RM_CNTL_ADJ__RESERVED__SHIFT 0x1
-#define RLC_GFX_RM_CNTL_ADJ__RLC_GFX_RM_VALID_MASK 0x00000001L
-#define RLC_GFX_RM_CNTL_ADJ__RESERVED_MASK 0xFFFFFFFEL
-//RLC_GPU_IOV_CFG_REG6
-#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT 0x0
-#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT 0x7
-#define RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT 0x8
-#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT 0xa
-#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK 0x0000007FL
-#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK 0x00000080L
-#define RLC_GPU_IOV_CFG_REG6__RESERVED_MASK 0x00000300L
-#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK 0xFFFFFC00L
-//RLC_GPU_IOV_CFG_REG8
-#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT 0x0
-#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK 0xFFFFFFFFL
-//RLC_RLCV_TIMER_INT_0
-#define RLC_RLCV_TIMER_INT_0__TIMER__SHIFT 0x0
-#define RLC_RLCV_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL
-//RLC_RLCV_TIMER_CTRL
-#define RLC_RLCV_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0
-#define RLC_RLCV_TIMER_CTRL__RESERVED__SHIFT 0x1
-#define RLC_RLCV_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L
-#define RLC_RLCV_TIMER_CTRL__RESERVED_MASK 0xFFFFFFFEL
-//RLC_RLCV_TIMER_STAT
-#define RLC_RLCV_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0
-#define RLC_RLCV_TIMER_STAT__RESERVED__SHIFT 0x1
-#define RLC_RLCV_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L
-#define RLC_RLCV_TIMER_STAT__RESERVED_MASK 0xFFFFFFFEL
-//RLC_GPU_IOV_VF_DOORBELL_STATUS
-#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS__SHIFT 0x0
-#define RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED__SHIFT 0x10
-#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS__SHIFT 0x1f
-#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_MASK 0x0000FFFFL
-#define RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED_MASK 0x7FFF0000L
-#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS_MASK 0x80000000L
-//RLC_GPU_IOV_VF_DOORBELL_STATUS_SET
-#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET__SHIFT 0x0
-#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED__SHIFT 0x10
-#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET__SHIFT 0x1f
-#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET_MASK 0x0000FFFFL
-#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED_MASK 0x7FFF0000L
-#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET_MASK 0x80000000L
-//RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR
-#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR__SHIFT 0x0
-#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED__SHIFT 0x10
-#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR__SHIFT 0x1f
-#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR_MASK 0x0000FFFFL
-#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED_MASK 0x7FFF0000L
-#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR_MASK 0x80000000L
-//RLC_GPU_IOV_VF_MASK
-#define RLC_GPU_IOV_VF_MASK__VF_MASK__SHIFT 0x0
-#define RLC_GPU_IOV_VF_MASK__RESERVED__SHIFT 0x10
-#define RLC_GPU_IOV_VF_MASK__VF_MASK_MASK 0x0000FFFFL
-#define RLC_GPU_IOV_VF_MASK__RESERVED_MASK 0xFFFF0000L
-//RLC_HYP_SEMAPHORE_2
-#define RLC_HYP_SEMAPHORE_2__CLIENT_ID__SHIFT 0x0
-#define RLC_HYP_SEMAPHORE_2__RESERVED__SHIFT 0x5
-#define RLC_HYP_SEMAPHORE_2__CLIENT_ID_MASK 0x0000001FL
-#define RLC_HYP_SEMAPHORE_2__RESERVED_MASK 0xFFFFFFE0L
-//RLC_HYP_SEMAPHORE_3
-#define RLC_HYP_SEMAPHORE_3__CLIENT_ID__SHIFT 0x0
-#define RLC_HYP_SEMAPHORE_3__RESERVED__SHIFT 0x5
-#define RLC_HYP_SEMAPHORE_3__CLIENT_ID_MASK 0x0000001FL
-#define RLC_HYP_SEMAPHORE_3__RESERVED_MASK 0xFFFFFFE0L
-//RLC_CLK_CNTL
-#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL__SHIFT 0x0
-#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL__SHIFT 0x1
-#define RLC_CLK_CNTL__RESERVED__SHIFT 0x2
-#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL_MASK 0x00000001L
-#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK 0x00000002L
-#define RLC_CLK_CNTL__RESERVED_MASK 0xFFFFFFFCL
-//RLC_GPU_IOV_SCH_BLOCK
-#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID__SHIFT 0x0
-#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver__SHIFT 0x4
-#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size__SHIFT 0x8
-#define RLC_GPU_IOV_SCH_BLOCK__RESERVED__SHIFT 0x10
-#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID_MASK 0x0000000FL
-#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver_MASK 0x000000F0L
-#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size_MASK 0x00007F00L
-#define RLC_GPU_IOV_SCH_BLOCK__RESERVED_MASK 0x7FFF0000L
-//RLC_GPU_IOV_CFG_REG1
-#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT 0x0
-#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT 0x4
-#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT 0x5
-#define RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT 0x6
-#define RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT 0x8
-#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT 0x10
-#define RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT 0x18
-#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK 0x0000000FL
-#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK 0x00000010L
-#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L
-#define RLC_GPU_IOV_CFG_REG1__RESERVED_MASK 0x000000C0L
-#define RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK 0x0000FF00L
-#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK 0x00FF0000L
-#define RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK 0xFF000000L
-//RLC_GPU_IOV_CFG_REG2
-#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT 0x0
-#define RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT 0x4
-#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK 0x0000000FL
-#define RLC_GPU_IOV_CFG_REG2__RESERVED_MASK 0xFFFFFFF0L
-//RLC_GPU_IOV_VM_BUSY_STATUS
-#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
-#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL
-//RLC_GPU_IOV_SCH_0
-#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS__SHIFT 0x0
-#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS_MASK 0xFFFFFFFFL
-//RLC_GPU_IOV_ACTIVE_FCN_ID
-#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0
-#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4
-#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f
-#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0x0000000FL
-#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L
-#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L
-//RLC_GPU_IOV_SCH_3
-#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def__SHIFT 0x0
-#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def_MASK 0xFFFFFFFFL
-//RLC_GPU_IOV_SCH_1
-#define RLC_GPU_IOV_SCH_1__DATA__SHIFT 0x0
-#define RLC_GPU_IOV_SCH_1__DATA_MASK 0xFFFFFFFFL
-//RLC_GPU_IOV_SCH_2
-#define RLC_GPU_IOV_SCH_2__DATA__SHIFT 0x0
-#define RLC_GPU_IOV_SCH_2__DATA_MASK 0xFFFFFFFFL
-//RLC_GPU_IOV_UCODE_ADDR
-#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
-#define RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT 0xc
-#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL
-#define RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK 0xFFFFF000L
-//RLC_GPU_IOV_UCODE_DATA
-#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT 0x0
-#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
-//RLC_GPU_IOV_SCRATCH_ADDR
-#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT 0x0
-#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED__SHIFT 0x9
-#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK 0x000001FFL
-#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED_MASK 0xFFFFFE00L
-//RLC_GPU_IOV_SCRATCH_DATA
-#define RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT 0x0
-#define RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL
-//RLC_GPU_IOV_F32_CNTL
-#define RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT 0x0
-#define RLC_GPU_IOV_F32_CNTL__RESERVED__SHIFT 0x1
-#define RLC_GPU_IOV_F32_CNTL__ENABLE_MASK 0x00000001L
-#define RLC_GPU_IOV_F32_CNTL__RESERVED_MASK 0xFFFFFFFEL
-//RLC_GPU_IOV_F32_RESET
-#define RLC_GPU_IOV_F32_RESET__RESET__SHIFT 0x0
-#define RLC_GPU_IOV_F32_RESET__RESERVED__SHIFT 0x1
-#define RLC_GPU_IOV_F32_RESET__RESET_MASK 0x00000001L
-#define RLC_GPU_IOV_F32_RESET__RESERVED_MASK 0xFFFFFFFEL
-//RLC_GPU_IOV_SDMA0_STATUS
-#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED__SHIFT 0x0
-#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED__SHIFT 0x1
-#define RLC_GPU_IOV_SDMA0_STATUS__SAVED__SHIFT 0x8
-#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1__SHIFT 0x9
-#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT 0xc
-#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2__SHIFT 0xd
-#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED_MASK 0x00000001L
-#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_MASK 0x000000FEL
-#define RLC_GPU_IOV_SDMA0_STATUS__SAVED_MASK 0x00000100L
-#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1_MASK 0x00000E00L
-#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED_MASK 0x00001000L
-#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2_MASK 0xFFFFE000L
-//RLC_GPU_IOV_SDMA1_STATUS
-#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED__SHIFT 0x0
-#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED__SHIFT 0x1
-#define RLC_GPU_IOV_SDMA1_STATUS__SAVED__SHIFT 0x8
-#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1__SHIFT 0x9
-#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED__SHIFT 0xc
-#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2__SHIFT 0xd
-#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED_MASK 0x00000001L
-#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_MASK 0x000000FEL
-#define RLC_GPU_IOV_SDMA1_STATUS__SAVED_MASK 0x00000100L
-#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1_MASK 0x00000E00L
-#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED_MASK 0x00001000L
-#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2_MASK 0xFFFFE000L
-//RLC_GPU_IOV_SMU_RESPONSE
-#define RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT 0x0
-#define RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK 0xFFFFFFFFL
-//RLC_GPU_IOV_VIRT_RESET_REQ
-#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0
-#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED__SHIFT 0x10
-#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT 0x1f
-#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK 0x0000FFFFL
-#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED_MASK 0x7FFF0000L
-#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK 0x80000000L
-//RLC_GPU_IOV_RLC_RESPONSE
-#define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT 0x0
-#define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL
-//RLC_GPU_IOV_INT_DISABLE
-#define RLC_GPU_IOV_INT_DISABLE__DISABLE__SHIFT 0x0
-#define RLC_GPU_IOV_INT_DISABLE__DISABLE_MASK 0xFFFFFFFFL
-//RLC_GPU_IOV_INT_FORCE
-#define RLC_GPU_IOV_INT_FORCE__FORCE__SHIFT 0x0
-#define RLC_GPU_IOV_INT_FORCE__FORCE_MASK 0xFFFFFFFFL
-//RLC_GPU_IOV_SDMA0_BUSY_STATUS
-#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
-#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL
-//RLC_GPU_IOV_SDMA1_BUSY_STATUS
-#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
-#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL
-
-
-// addressBlock: gccacind
-//GC_CAC_CNTL
-#define GC_CAC_CNTL__CAC_ENABLE__SHIFT 0x0
-#define GC_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x1
-#define GC_CAC_CNTL__CAC_BLOCK_ID__SHIFT 0x11
-#define GC_CAC_CNTL__CAC_SIGNAL_ID__SHIFT 0x17
-#define GC_CAC_CNTL__UNUSED_0__SHIFT 0x1f
-#define GC_CAC_CNTL__CAC_ENABLE_MASK 0x00000001L
-#define GC_CAC_CNTL__CAC_THRESHOLD_MASK 0x0001FFFEL
-#define GC_CAC_CNTL__CAC_BLOCK_ID_MASK 0x007E0000L
-#define GC_CAC_CNTL__CAC_SIGNAL_ID_MASK 0x7F800000L
-#define GC_CAC_CNTL__UNUSED_0_MASK 0x80000000L
-//GC_CAC_OVR_SEL
-#define GC_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT 0x0
-#define GC_CAC_OVR_SEL__CAC_OVR_SEL_MASK 0xFFFFFFFFL
-//GC_CAC_OVR_VAL
-#define GC_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT 0x0
-#define GC_CAC_OVR_VAL__CAC_OVR_VAL_MASK 0xFFFFFFFFL
-//GC_CAC_WEIGHT_BCI_0
-#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_CB_0
-#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_CB_1
-#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2__SHIFT 0x0
-#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3__SHIFT 0x10
-#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_CP_0
-#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_CP_1
-#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2__SHIFT 0x0
-#define GC_CAC_WEIGHT_CP_1__UNUSED_0__SHIFT 0x10
-#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_CP_1__UNUSED_0_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_DB_0
-#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_DB_1
-#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2__SHIFT 0x0
-#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3__SHIFT 0x10
-#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_GDS_0
-#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_GDS_1
-#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2__SHIFT 0x0
-#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3__SHIFT 0x10
-#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_IA_0
-#define GC_CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_IA_0__UNUSED_0__SHIFT 0x10
-#define GC_CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_IA_0__UNUSED_0_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_LDS_0
-#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_LDS_1
-#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2__SHIFT 0x0
-#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3__SHIFT 0x10
-#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_PA_0
-#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_PC_0
-#define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_PC_0__UNUSED_0__SHIFT 0x10
-#define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_PC_0__UNUSED_0_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_SC_0
-#define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_SC_0__UNUSED_0__SHIFT 0x10
-#define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_SC_0__UNUSED_0_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_SPI_0
-#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_SPI_1
-#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2__SHIFT 0x0
-#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3__SHIFT 0x10
-#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_SPI_2
-#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4__SHIFT 0x0
-#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5__SHIFT 0x10
-#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_SQ_0
-#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_SQ_1
-#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2__SHIFT 0x0
-#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3__SHIFT 0x10
-#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_SQ_2
-#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4__SHIFT 0x0
-#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5__SHIFT 0x10
-#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_SQ_3
-#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6__SHIFT 0x0
-#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7__SHIFT 0x10
-#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_SQ_4
-#define GC_CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8__SHIFT 0x0
-#define GC_CAC_WEIGHT_SQ_4__UNUSED_0__SHIFT 0x10
-#define GC_CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_SQ_4__UNUSED_0_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_SX_0
-#define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_SX_0__UNUSED_0__SHIFT 0x10
-#define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_SX_0__UNUSED_0_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_SXRB_0
-#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_TA_0
-#define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_TA_0__UNUSED_0__SHIFT 0x10
-#define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_TA_0__UNUSED_0_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_TCC_0
-#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_TCC_1
-#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2__SHIFT 0x0
-#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3__SHIFT 0x10
-#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_TCC_2
-#define GC_CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4__SHIFT 0x0
-#define GC_CAC_WEIGHT_TCC_2__UNUSED_0__SHIFT 0x10
-#define GC_CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_TCC_2__UNUSED_0_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_TCP_0
-#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_TCP_1
-#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2__SHIFT 0x0
-#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3__SHIFT 0x10
-#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_TCP_2
-#define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4__SHIFT 0x0
-#define GC_CAC_WEIGHT_TCP_2__UNUSED_0__SHIFT 0x10
-#define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_TCP_2__UNUSED_0_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_TD_0
-#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_TD_1
-#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2__SHIFT 0x0
-#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3__SHIFT 0x10
-#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_TD_2
-#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4__SHIFT 0x0
-#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5__SHIFT 0x10
-#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_VGT_0
-#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_VGT_1
-#define GC_CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2__SHIFT 0x0
-#define GC_CAC_WEIGHT_VGT_1__UNUSED_0__SHIFT 0x10
-#define GC_CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_VGT_1__UNUSED_0_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_WD_0
-#define GC_CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_WD_0__UNUSED_0__SHIFT 0x10
-#define GC_CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_WD_0__UNUSED_0_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_CU_0
-#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_CU_1
-#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2__SHIFT 0x0
-#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3__SHIFT 0x10
-#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_CU_2
-#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG4__SHIFT 0x0
-#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG5__SHIFT 0x10
-#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG4_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG5_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_CU_3
-#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG6__SHIFT 0x0
-#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG7__SHIFT 0x10
-#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG6_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG7_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_CU_4
-#define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG8__SHIFT 0x0
-#define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG9__SHIFT 0x10
-#define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG8_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG9_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_CU_5
-#define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG10__SHIFT 0x0
-#define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG11__SHIFT 0x10
-#define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG10_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG11_MASK 0xFFFF0000L
-//GC_CAC_ACC_BCI0
-#define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_CB0
-#define GC_CAC_ACC_CB0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_CB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_CB1
-#define GC_CAC_ACC_CB1__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_CB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_CB2
-#define GC_CAC_ACC_CB2__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_CB2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_CB3
-#define GC_CAC_ACC_CB3__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_CB3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_CP0
-#define GC_CAC_ACC_CP0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_CP0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_CP1
-#define GC_CAC_ACC_CP1__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_CP1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_CP2
-#define GC_CAC_ACC_CP2__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_CP2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_DB0
-#define GC_CAC_ACC_DB0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_DB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_DB1
-#define GC_CAC_ACC_DB1__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_DB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_DB2
-#define GC_CAC_ACC_DB2__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_DB2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_DB3
-#define GC_CAC_ACC_DB3__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_DB3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_GDS0
-#define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_GDS1
-#define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_GDS2
-#define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_GDS3
-#define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_IA0
-#define GC_CAC_ACC_IA0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_IA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_LDS0
-#define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_LDS1
-#define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_LDS2
-#define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_LDS3
-#define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_PA0
-#define GC_CAC_ACC_PA0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_PA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_PA1
-#define GC_CAC_ACC_PA1__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_PA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_PC0
-#define GC_CAC_ACC_PC0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_PC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_SC0
-#define GC_CAC_ACC_SC0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_SPI0
-#define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_SPI1
-#define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_SPI2
-#define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_SPI3
-#define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_SPI4
-#define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_SPI5
-#define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_WEIGHT_PG_0
-#define GC_CAC_WEIGHT_PG_0__WEIGHT_PG_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_PG_0__unused__SHIFT 0x10
-#define GC_CAC_WEIGHT_PG_0__WEIGHT_PG_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_PG_0__unused_MASK 0xFFFF0000L
-//GC_CAC_ACC_PG0
-#define GC_CAC_ACC_PG0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_PG0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_OVRD_PG
-#define GC_CAC_OVRD_PG__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_PG__OVRRD_VALUE__SHIFT 0x10
-#define GC_CAC_OVRD_PG__OVRRD_SELECT_MASK 0x0000FFFFL
-#define GC_CAC_OVRD_PG__OVRRD_VALUE_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_UTCL2_ATCL2_0
-#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1_MASK 0xFFFF0000L
-//GC_CAC_ACC_EA0
-#define GC_CAC_ACC_EA0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_EA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_EA1
-#define GC_CAC_ACC_EA1__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_EA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_EA2
-#define GC_CAC_ACC_EA2__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_EA2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_EA3
-#define GC_CAC_ACC_EA3__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_EA3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_ATCL20
-#define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_OVRD_EA
-#define GC_CAC_OVRD_EA__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_EA__OVRRD_VALUE__SHIFT 0x6
-#define GC_CAC_OVRD_EA__OVRRD_SELECT_MASK 0x0000003FL
-#define GC_CAC_OVRD_EA__OVRRD_VALUE_MASK 0x00000FC0L
-//GC_CAC_OVRD_UTCL2_ATCL2
-#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE__SHIFT 0x5
-#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT_MASK 0x0000001FL
-#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE_MASK 0x000003E0L
-//GC_CAC_WEIGHT_EA_0
-#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_EA_1
-#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2__SHIFT 0x0
-#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3__SHIFT 0x10
-#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_RMI_0
-#define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_RMI_0__UNUSED__SHIFT 0x10
-#define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_RMI_0__UNUSED_MASK 0xFFFF0000L
-//GC_CAC_ACC_RMI0
-#define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_OVRD_RMI
-#define GC_CAC_OVRD_RMI__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_RMI__OVRRD_VALUE__SHIFT 0x1
-#define GC_CAC_OVRD_RMI__OVRRD_SELECT_MASK 0x00000001L
-#define GC_CAC_OVRD_RMI__OVRRD_VALUE_MASK 0x00000002L
-//GC_CAC_WEIGHT_UTCL2_ATCL2_1
-#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2__SHIFT 0x0
-#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3__SHIFT 0x10
-#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3_MASK 0xFFFF0000L
-//GC_CAC_ACC_UTCL2_ATCL21
-#define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_ATCL22
-#define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_ATCL23
-#define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_EA4
-#define GC_CAC_ACC_EA4__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_EA4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_EA5
-#define GC_CAC_ACC_EA5__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_EA5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_WEIGHT_EA_2
-#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4__SHIFT 0x0
-#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5__SHIFT 0x10
-#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5_MASK 0xFFFF0000L
-//GC_CAC_ACC_SQ0_LOWER
-#define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_SQ0_UPPER
-#define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
-#define GC_CAC_ACC_SQ0_UPPER__UNUSED_0__SHIFT 0x8
-#define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
-#define GC_CAC_ACC_SQ0_UPPER__UNUSED_0_MASK 0xFFFFFF00L
-//GC_CAC_ACC_SQ1_LOWER
-#define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_SQ1_UPPER
-#define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
-#define GC_CAC_ACC_SQ1_UPPER__UNUSED_0__SHIFT 0x8
-#define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
-#define GC_CAC_ACC_SQ1_UPPER__UNUSED_0_MASK 0xFFFFFF00L
-//GC_CAC_ACC_SQ2_LOWER
-#define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_SQ2_UPPER
-#define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
-#define GC_CAC_ACC_SQ2_UPPER__UNUSED_0__SHIFT 0x8
-#define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
-#define GC_CAC_ACC_SQ2_UPPER__UNUSED_0_MASK 0xFFFFFF00L
-//GC_CAC_ACC_SQ3_LOWER
-#define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_SQ3_UPPER
-#define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
-#define GC_CAC_ACC_SQ3_UPPER__UNUSED_0__SHIFT 0x8
-#define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
-#define GC_CAC_ACC_SQ3_UPPER__UNUSED_0_MASK 0xFFFFFF00L
-//GC_CAC_ACC_SQ4_LOWER
-#define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_SQ4_UPPER
-#define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
-#define GC_CAC_ACC_SQ4_UPPER__UNUSED_0__SHIFT 0x8
-#define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
-#define GC_CAC_ACC_SQ4_UPPER__UNUSED_0_MASK 0xFFFFFF00L
-//GC_CAC_ACC_SQ5_LOWER
-#define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_SQ5_UPPER
-#define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
-#define GC_CAC_ACC_SQ5_UPPER__UNUSED_0__SHIFT 0x8
-#define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
-#define GC_CAC_ACC_SQ5_UPPER__UNUSED_0_MASK 0xFFFFFF00L
-//GC_CAC_ACC_SQ6_LOWER
-#define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_SQ6_UPPER
-#define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
-#define GC_CAC_ACC_SQ6_UPPER__UNUSED_0__SHIFT 0x8
-#define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
-#define GC_CAC_ACC_SQ6_UPPER__UNUSED_0_MASK 0xFFFFFF00L
-//GC_CAC_ACC_SQ7_LOWER
-#define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_SQ7_UPPER
-#define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
-#define GC_CAC_ACC_SQ7_UPPER__UNUSED_0__SHIFT 0x8
-#define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
-#define GC_CAC_ACC_SQ7_UPPER__UNUSED_0_MASK 0xFFFFFF00L
-//GC_CAC_ACC_SQ8_LOWER
-#define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_SQ8_UPPER
-#define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
-#define GC_CAC_ACC_SQ8_UPPER__UNUSED_0__SHIFT 0x8
-#define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
-#define GC_CAC_ACC_SQ8_UPPER__UNUSED_0_MASK 0xFFFFFF00L
-//GC_CAC_ACC_SX0
-#define GC_CAC_ACC_SX0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SX0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_SXRB0
-#define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_SXRB1
-#define GC_CAC_ACC_SXRB1__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_SXRB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_TA0
-#define GC_CAC_ACC_TA0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_TA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_TCC0
-#define GC_CAC_ACC_TCC0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_TCC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_TCC1
-#define GC_CAC_ACC_TCC1__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_TCC1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_TCC2
-#define GC_CAC_ACC_TCC2__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_TCC2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_TCC3
-#define GC_CAC_ACC_TCC3__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_TCC3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_TCC4
-#define GC_CAC_ACC_TCC4__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_TCC4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_TCP0
-#define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_TCP1
-#define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_TCP2
-#define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_TCP3
-#define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_TCP4
-#define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_TD0
-#define GC_CAC_ACC_TD0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_TD0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_TD1
-#define GC_CAC_ACC_TD1__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_TD1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_TD2
-#define GC_CAC_ACC_TD2__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_TD2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_TD3
-#define GC_CAC_ACC_TD3__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_TD3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_TD4
-#define GC_CAC_ACC_TD4__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_TD4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_TD5
-#define GC_CAC_ACC_TD5__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_TD5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_VGT0
-#define GC_CAC_ACC_VGT0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_VGT0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_VGT1
-#define GC_CAC_ACC_VGT1__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_VGT1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_VGT2
-#define GC_CAC_ACC_VGT2__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_VGT2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_WD0
-#define GC_CAC_ACC_WD0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_WD0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_CU0
-#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_CU1
-#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_CU2
-#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_CU3
-#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_CU4
-#define GC_CAC_ACC_CU4__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_CU4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_CU5
-#define GC_CAC_ACC_CU5__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_CU5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_CU6
-#define GC_CAC_ACC_CU6__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_CU6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_CU7
-#define GC_CAC_ACC_CU7__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_CU7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_CU8
-#define GC_CAC_ACC_CU8__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_CU8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_CU9
-#define GC_CAC_ACC_CU9__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_CU9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_CU10
-#define GC_CAC_ACC_CU10__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_CU10__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_OVRD_BCI
-#define GC_CAC_OVRD_BCI__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_BCI__OVRRD_VALUE__SHIFT 0x2
-#define GC_CAC_OVRD_BCI__OVRRD_SELECT_MASK 0x00000003L
-#define GC_CAC_OVRD_BCI__OVRRD_VALUE_MASK 0x0000000CL
-//GC_CAC_OVRD_CB
-#define GC_CAC_OVRD_CB__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_CB__OVRRD_VALUE__SHIFT 0x4
-#define GC_CAC_OVRD_CB__OVRRD_SELECT_MASK 0x0000000FL
-#define GC_CAC_OVRD_CB__OVRRD_VALUE_MASK 0x000000F0L
-//GC_CAC_OVRD_CP
-#define GC_CAC_OVRD_CP__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_CP__OVRRD_VALUE__SHIFT 0x3
-#define GC_CAC_OVRD_CP__OVRRD_SELECT_MASK 0x00000007L
-#define GC_CAC_OVRD_CP__OVRRD_VALUE_MASK 0x00000038L
-//GC_CAC_OVRD_DB
-#define GC_CAC_OVRD_DB__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_DB__OVRRD_VALUE__SHIFT 0x4
-#define GC_CAC_OVRD_DB__OVRRD_SELECT_MASK 0x0000000FL
-#define GC_CAC_OVRD_DB__OVRRD_VALUE_MASK 0x000000F0L
-//GC_CAC_OVRD_GDS
-#define GC_CAC_OVRD_GDS__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_GDS__OVRRD_VALUE__SHIFT 0x4
-#define GC_CAC_OVRD_GDS__OVRRD_SELECT_MASK 0x0000000FL
-#define GC_CAC_OVRD_GDS__OVRRD_VALUE_MASK 0x000000F0L
-//GC_CAC_OVRD_IA
-#define GC_CAC_OVRD_IA__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_IA__OVRRD_VALUE__SHIFT 0x1
-#define GC_CAC_OVRD_IA__OVRRD_SELECT_MASK 0x00000001L
-#define GC_CAC_OVRD_IA__OVRRD_VALUE_MASK 0x00000002L
-//GC_CAC_OVRD_LDS
-#define GC_CAC_OVRD_LDS__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_LDS__OVRRD_VALUE__SHIFT 0x4
-#define GC_CAC_OVRD_LDS__OVRRD_SELECT_MASK 0x0000000FL
-#define GC_CAC_OVRD_LDS__OVRRD_VALUE_MASK 0x000000F0L
-//GC_CAC_OVRD_PA
-#define GC_CAC_OVRD_PA__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_PA__OVRRD_VALUE__SHIFT 0x2
-#define GC_CAC_OVRD_PA__OVRRD_SELECT_MASK 0x00000003L
-#define GC_CAC_OVRD_PA__OVRRD_VALUE_MASK 0x0000000CL
-//GC_CAC_OVRD_PC
-#define GC_CAC_OVRD_PC__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_PC__OVRRD_VALUE__SHIFT 0x1
-#define GC_CAC_OVRD_PC__OVRRD_SELECT_MASK 0x00000001L
-#define GC_CAC_OVRD_PC__OVRRD_VALUE_MASK 0x00000002L
-//GC_CAC_OVRD_SC
-#define GC_CAC_OVRD_SC__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_SC__OVRRD_VALUE__SHIFT 0x1
-#define GC_CAC_OVRD_SC__OVRRD_SELECT_MASK 0x00000001L
-#define GC_CAC_OVRD_SC__OVRRD_VALUE_MASK 0x00000002L
-//GC_CAC_OVRD_SPI
-#define GC_CAC_OVRD_SPI__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_SPI__OVRRD_VALUE__SHIFT 0x6
-#define GC_CAC_OVRD_SPI__OVRRD_SELECT_MASK 0x0000003FL
-#define GC_CAC_OVRD_SPI__OVRRD_VALUE_MASK 0x00000FC0L
-//GC_CAC_OVRD_CU
-#define GC_CAC_OVRD_CU__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT 0x1
-#define GC_CAC_OVRD_CU__OVRRD_SELECT_MASK 0x00000001L
-#define GC_CAC_OVRD_CU__OVRRD_VALUE_MASK 0x00000002L
-//GC_CAC_OVRD_SQ
-#define GC_CAC_OVRD_SQ__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_SQ__OVRRD_VALUE__SHIFT 0x9
-#define GC_CAC_OVRD_SQ__OVRRD_SELECT_MASK 0x000001FFL
-#define GC_CAC_OVRD_SQ__OVRRD_VALUE_MASK 0x0003FE00L
-//GC_CAC_OVRD_SX
-#define GC_CAC_OVRD_SX__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_SX__OVRRD_VALUE__SHIFT 0x1
-#define GC_CAC_OVRD_SX__OVRRD_SELECT_MASK 0x00000001L
-#define GC_CAC_OVRD_SX__OVRRD_VALUE_MASK 0x00000002L
-//GC_CAC_OVRD_SXRB
-#define GC_CAC_OVRD_SXRB__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_SXRB__OVRRD_VALUE__SHIFT 0x1
-#define GC_CAC_OVRD_SXRB__OVRRD_SELECT_MASK 0x00000001L
-#define GC_CAC_OVRD_SXRB__OVRRD_VALUE_MASK 0x00000002L
-//GC_CAC_OVRD_TA
-#define GC_CAC_OVRD_TA__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_TA__OVRRD_VALUE__SHIFT 0x1
-#define GC_CAC_OVRD_TA__OVRRD_SELECT_MASK 0x00000001L
-#define GC_CAC_OVRD_TA__OVRRD_VALUE_MASK 0x00000002L
-//GC_CAC_OVRD_TCC
-#define GC_CAC_OVRD_TCC__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_TCC__OVRRD_VALUE__SHIFT 0x5
-#define GC_CAC_OVRD_TCC__OVRRD_SELECT_MASK 0x0000001FL
-#define GC_CAC_OVRD_TCC__OVRRD_VALUE_MASK 0x000003E0L
-//GC_CAC_OVRD_TCP
-#define GC_CAC_OVRD_TCP__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_TCP__OVRRD_VALUE__SHIFT 0x5
-#define GC_CAC_OVRD_TCP__OVRRD_SELECT_MASK 0x0000001FL
-#define GC_CAC_OVRD_TCP__OVRRD_VALUE_MASK 0x000003E0L
-//GC_CAC_OVRD_TD
-#define GC_CAC_OVRD_TD__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_TD__OVRRD_VALUE__SHIFT 0x6
-#define GC_CAC_OVRD_TD__OVRRD_SELECT_MASK 0x0000003FL
-#define GC_CAC_OVRD_TD__OVRRD_VALUE_MASK 0x00000FC0L
-//GC_CAC_OVRD_VGT
-#define GC_CAC_OVRD_VGT__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_VGT__OVRRD_VALUE__SHIFT 0x3
-#define GC_CAC_OVRD_VGT__OVRRD_SELECT_MASK 0x00000007L
-#define GC_CAC_OVRD_VGT__OVRRD_VALUE_MASK 0x00000038L
-//GC_CAC_OVRD_WD
-#define GC_CAC_OVRD_WD__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_WD__OVRRD_VALUE__SHIFT 0x1
-#define GC_CAC_OVRD_WD__OVRRD_SELECT_MASK 0x00000001L
-#define GC_CAC_OVRD_WD__OVRRD_VALUE_MASK 0x00000002L
-//GC_CAC_ACC_BCI1
-#define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_WEIGHT_UTCL2_ATCL2_2
-#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4__SHIFT 0x0
-#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG5__SHIFT 0x10
-#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG5_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_UTCL2_ROUTER_0
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_UTCL2_ROUTER_1
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2__SHIFT 0x0
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3__SHIFT 0x10
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_UTCL2_ROUTER_2
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4__SHIFT 0x0
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5__SHIFT 0x10
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_UTCL2_ROUTER_3
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6__SHIFT 0x0
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7__SHIFT 0x10
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_UTCL2_ROUTER_4
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8__SHIFT 0x0
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9__SHIFT 0x10
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_UTCL2_VML2_0
-#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_UTCL2_VML2_1
-#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2__SHIFT 0x0
-#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3__SHIFT 0x10
-#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_UTCL2_VML2_2
-#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4__SHIFT 0x0
-#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG5__SHIFT 0x10
-#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG5_MASK 0xFFFF0000L
-//GC_CAC_ACC_UTCL2_ATCL24
-#define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_ROUTER0
-#define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_ROUTER1
-#define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_ROUTER2
-#define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_ROUTER3
-#define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_ROUTER4
-#define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_ROUTER5
-#define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_ROUTER6
-#define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_ROUTER7
-#define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_ROUTER8
-#define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_ROUTER9
-#define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_VML20
-#define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_VML21
-#define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_VML22
-#define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_VML23
-#define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_VML24
-#define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_OVRD_UTCL2_ROUTER
-#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE__SHIFT 0xa
-#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT_MASK 0x000003FFL
-#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE_MASK 0x000FFC00L
-//GC_CAC_OVRD_UTCL2_VML2
-#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE__SHIFT 0x5
-#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT_MASK 0x0000001FL
-#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE_MASK 0x000003E0L
-//GC_CAC_WEIGHT_UTCL2_WALKER_0
-#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0__SHIFT 0x0
-#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1__SHIFT 0x10
-#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_UTCL2_WALKER_1
-#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2__SHIFT 0x0
-#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3__SHIFT 0x10
-#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3_MASK 0xFFFF0000L
-//GC_CAC_WEIGHT_UTCL2_WALKER_2
-#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4__SHIFT 0x0
-#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG5__SHIFT 0x10
-#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4_MASK 0x0000FFFFL
-#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG5_MASK 0xFFFF0000L
-//GC_CAC_ACC_UTCL2_WALKER0
-#define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_WALKER1
-#define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_WALKER2
-#define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_WALKER3
-#define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_ACC_UTCL2_WALKER4
-#define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0__SHIFT 0x0
-#define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
-//GC_CAC_OVRD_UTCL2_WALKER
-#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT__SHIFT 0x0
-#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE__SHIFT 0x5
-#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT_MASK 0x0000001FL
-#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE_MASK 0x000003E0L
-
-
-// addressBlock: secacind
-//SE_CAC_CNTL
-#define SE_CAC_CNTL__CAC_ENABLE__SHIFT 0x0
-#define SE_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x1
-#define SE_CAC_CNTL__CAC_BLOCK_ID__SHIFT 0x11
-#define SE_CAC_CNTL__CAC_SIGNAL_ID__SHIFT 0x17
-#define SE_CAC_CNTL__UNUSED_0__SHIFT 0x1f
-#define SE_CAC_CNTL__CAC_ENABLE_MASK 0x00000001L
-#define SE_CAC_CNTL__CAC_THRESHOLD_MASK 0x0001FFFEL
-#define SE_CAC_CNTL__CAC_BLOCK_ID_MASK 0x007E0000L
-#define SE_CAC_CNTL__CAC_SIGNAL_ID_MASK 0x7F800000L
-#define SE_CAC_CNTL__UNUSED_0_MASK 0x80000000L
-//SE_CAC_OVR_SEL
-#define SE_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT 0x0
-#define SE_CAC_OVR_SEL__CAC_OVR_SEL_MASK 0xFFFFFFFFL
-//SE_CAC_OVR_VAL
-#define SE_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT 0x0
-#define SE_CAC_OVR_VAL__CAC_OVR_VAL_MASK 0xFFFFFFFFL
-
-
-// addressBlock: sqind
-//SQ_DEBUG_STS_GLOBAL
-#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0x000000ffL
-#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x00000000
-#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0x0000ff00L
-#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x00000008
-#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK 0xff000000L
-#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT 0x00000018
-#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK 0x00ff0000L
-#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT 0x00000010
-#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK 0x0000000fL
-#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT 0x00000000
-#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK 0x000000f0L
-#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT 0x00000004
-#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x00000001L
-#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x00000000
-#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x00000002L
-#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x00000001
-#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK 0x0000fff0L
-#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT 0x00000004
-#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK 0x0fff0000L
-#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT 0x00000010
-//SQ_DEBUG_STS_LOCAL
-#define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L
-#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x00000000
-#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x000003f0L
-#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x00000004
-//SQ_WAVE_MODE
-#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0
-#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4
-#define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x8
-#define SQ_WAVE_MODE__IEEE__SHIFT 0x9
-#define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa
-#define SQ_WAVE_MODE__EXCP_EN__SHIFT 0xc
-#define SQ_WAVE_MODE__FP16_OVFL__SHIFT 0x17
-#define SQ_WAVE_MODE__POPS_PACKER0__SHIFT 0x18
-#define SQ_WAVE_MODE__POPS_PACKER1__SHIFT 0x19
-#define SQ_WAVE_MODE__DISABLE_PERF__SHIFT 0x1a
-#define SQ_WAVE_MODE__GPR_IDX_EN__SHIFT 0x1b
-#define SQ_WAVE_MODE__VSKIP__SHIFT 0x1c
-#define SQ_WAVE_MODE__CSP__SHIFT 0x1d
-#define SQ_WAVE_MODE__FP_ROUND_MASK 0x0000000FL
-#define SQ_WAVE_MODE__FP_DENORM_MASK 0x000000F0L
-#define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x00000100L
-#define SQ_WAVE_MODE__IEEE_MASK 0x00000200L
-#define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x00000400L
-#define SQ_WAVE_MODE__EXCP_EN_MASK 0x001FF000L
-#define SQ_WAVE_MODE__FP16_OVFL_MASK 0x00800000L
-#define SQ_WAVE_MODE__POPS_PACKER0_MASK 0x01000000L
-#define SQ_WAVE_MODE__POPS_PACKER1_MASK 0x02000000L
-#define SQ_WAVE_MODE__DISABLE_PERF_MASK 0x04000000L
-#define SQ_WAVE_MODE__GPR_IDX_EN_MASK 0x08000000L
-#define SQ_WAVE_MODE__VSKIP_MASK 0x10000000L
-#define SQ_WAVE_MODE__CSP_MASK 0xE0000000L
-//SQ_WAVE_STATUS
-#define SQ_WAVE_STATUS__SCC__SHIFT 0x0
-#define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x1
-#define SQ_WAVE_STATUS__USER_PRIO__SHIFT 0x3
-#define SQ_WAVE_STATUS__PRIV__SHIFT 0x5
-#define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x6
-#define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x7
-#define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x8
-#define SQ_WAVE_STATUS__EXECZ__SHIFT 0x9
-#define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa
-#define SQ_WAVE_STATUS__IN_TG__SHIFT 0xb
-#define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0xc
-#define SQ_WAVE_STATUS__HALT__SHIFT 0xd
-#define SQ_WAVE_STATUS__TRAP__SHIFT 0xe
-#define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT 0xf
-#define SQ_WAVE_STATUS__VALID__SHIFT 0x10
-#define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x11
-#define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x12
-#define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x13
-#define SQ_WAVE_STATUS__ALLOW_REPLAY__SHIFT 0x16
-#define SQ_WAVE_STATUS__FATAL_HALT__SHIFT 0x17
-#define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x1b
-#define SQ_WAVE_STATUS__SCC_MASK 0x00000001L
-#define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x00000006L
-#define SQ_WAVE_STATUS__USER_PRIO_MASK 0x00000018L
-#define SQ_WAVE_STATUS__PRIV_MASK 0x00000020L
-#define SQ_WAVE_STATUS__TRAP_EN_MASK 0x00000040L
-#define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x00000080L
-#define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x00000100L
-#define SQ_WAVE_STATUS__EXECZ_MASK 0x00000200L
-#define SQ_WAVE_STATUS__VCCZ_MASK 0x00000400L
-#define SQ_WAVE_STATUS__IN_TG_MASK 0x00000800L
-#define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x00001000L
-#define SQ_WAVE_STATUS__HALT_MASK 0x00002000L
-#define SQ_WAVE_STATUS__TRAP_MASK 0x00004000L
-#define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK 0x00008000L
-#define SQ_WAVE_STATUS__VALID_MASK 0x00010000L
-#define SQ_WAVE_STATUS__ECC_ERR_MASK 0x00020000L
-#define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x00040000L
-#define SQ_WAVE_STATUS__PERF_EN_MASK 0x00080000L
-#define SQ_WAVE_STATUS__ALLOW_REPLAY_MASK 0x00400000L
-#define SQ_WAVE_STATUS__FATAL_HALT_MASK 0x00800000L
-#define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x08000000L
-//SQ_WAVE_TRAPSTS
-#define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x0
-#define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT 0xa
-#define SQ_WAVE_TRAPSTS__ILLEGAL_INST__SHIFT 0xb
-#define SQ_WAVE_TRAPSTS__EXCP_HI__SHIFT 0xc
-#define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x10
-#define SQ_WAVE_TRAPSTS__XNACK_ERROR__SHIFT 0x1c
-#define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x1d
-#define SQ_WAVE_TRAPSTS__EXCP_MASK 0x000001FFL
-#define SQ_WAVE_TRAPSTS__SAVECTX_MASK 0x00000400L
-#define SQ_WAVE_TRAPSTS__ILLEGAL_INST_MASK 0x00000800L
-#define SQ_WAVE_TRAPSTS__EXCP_HI_MASK 0x00007000L
-#define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x003F0000L
-#define SQ_WAVE_TRAPSTS__XNACK_ERROR_MASK 0x10000000L
-#define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xE0000000L
-//SQ_WAVE_HW_ID
-#define SQ_WAVE_HW_ID__WAVE_ID__SHIFT 0x0
-#define SQ_WAVE_HW_ID__SIMD_ID__SHIFT 0x4
-#define SQ_WAVE_HW_ID__PIPE_ID__SHIFT 0x6
-#define SQ_WAVE_HW_ID__CU_ID__SHIFT 0x8
-#define SQ_WAVE_HW_ID__SH_ID__SHIFT 0xc
-#define SQ_WAVE_HW_ID__SE_ID__SHIFT 0xd
-#define SQ_WAVE_HW_ID__TG_ID__SHIFT 0x10
-#define SQ_WAVE_HW_ID__VM_ID__SHIFT 0x14
-#define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT 0x18
-#define SQ_WAVE_HW_ID__STATE_ID__SHIFT 0x1b
-#define SQ_WAVE_HW_ID__ME_ID__SHIFT 0x1e
-#define SQ_WAVE_HW_ID__WAVE_ID_MASK 0x0000000FL
-#define SQ_WAVE_HW_ID__SIMD_ID_MASK 0x00000030L
-#define SQ_WAVE_HW_ID__PIPE_ID_MASK 0x000000C0L
-#define SQ_WAVE_HW_ID__CU_ID_MASK 0x00000F00L
-#define SQ_WAVE_HW_ID__SH_ID_MASK 0x00001000L
-#define SQ_WAVE_HW_ID__SE_ID_MASK 0x00006000L
-#define SQ_WAVE_HW_ID__TG_ID_MASK 0x000F0000L
-#define SQ_WAVE_HW_ID__VM_ID_MASK 0x00F00000L
-#define SQ_WAVE_HW_ID__QUEUE_ID_MASK 0x07000000L
-#define SQ_WAVE_HW_ID__STATE_ID_MASK 0x38000000L
-#define SQ_WAVE_HW_ID__ME_ID_MASK 0xC0000000L
-//SQ_WAVE_GPR_ALLOC
-#define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x0
-#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x8
-#define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x10
-#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x18
-#define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x0000003FL
-#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x00003F00L
-#define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x003F0000L
-#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0x0F000000L
-//SQ_WAVE_LDS_ALLOC
-#define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x0
-#define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0xc
-#define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0x000000FFL
-#define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x001FF000L
-//SQ_WAVE_IB_STS
-#define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x0
-#define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x4
-#define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x8
-#define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0xc
-#define SQ_WAVE_IB_STS__FIRST_REPLAY__SHIFT 0xf
-#define SQ_WAVE_IB_STS__RCNT__SHIFT 0x10
-#define SQ_WAVE_IB_STS__VM_CNT_HI__SHIFT 0x16
-#define SQ_WAVE_IB_STS__VM_CNT_MASK 0x0000000FL
-#define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x00000070L
-#define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0x00000F00L
-#define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x00007000L
-#define SQ_WAVE_IB_STS__FIRST_REPLAY_MASK 0x00008000L
-#define SQ_WAVE_IB_STS__RCNT_MASK 0x001F0000L
-#define SQ_WAVE_IB_STS__VM_CNT_HI_MASK 0x00C00000L
-//SQ_WAVE_PC_LO
-#define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x0
-#define SQ_WAVE_PC_LO__PC_LO_MASK 0xFFFFFFFFL
-//SQ_WAVE_PC_HI
-#define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x0
-#define SQ_WAVE_PC_HI__PC_HI_MASK 0x0000FFFFL
-//SQ_WAVE_INST_DW0
-#define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x0
-#define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xFFFFFFFFL
-//SQ_WAVE_INST_DW1
-#define SQ_WAVE_INST_DW1__INST_DW1__SHIFT 0x0
-#define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xFFFFFFFFL
-//SQ_WAVE_IB_DBG0
-#define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x0
-#define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT 0x3
-#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT 0x4
-#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT 0x5
-#define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT 0x8
-#define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0xa
-#define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT 0x10
-#define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT 0x18
-#define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT 0x1a
-#define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT 0x1b
-#define SQ_WAVE_IB_DBG0__KILL__SHIFT 0x1d
-#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT 0x1e
-#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI__SHIFT 0x1f
-#define SQ_WAVE_IB_DBG0__IBUF_ST_MASK 0x00000007L
-#define SQ_WAVE_IB_DBG0__PC_INVALID_MASK 0x00000008L
-#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK 0x00000010L
-#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK 0x000000E0L
-#define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK 0x00000300L
-#define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK 0x00000C00L
-#define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK 0x000F0000L
-#define SQ_WAVE_IB_DBG0__ECC_ST_MASK 0x03000000L
-#define SQ_WAVE_IB_DBG0__IS_HYB_MASK 0x04000000L
-#define SQ_WAVE_IB_DBG0__HYB_CNT_MASK 0x18000000L
-#define SQ_WAVE_IB_DBG0__KILL_MASK 0x20000000L
-#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK 0x40000000L
-#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI_MASK 0x80000000L
-//SQ_WAVE_IB_DBG1
-#define SQ_WAVE_IB_DBG1__IXNACK__SHIFT 0x0
-#define SQ_WAVE_IB_DBG1__XNACK__SHIFT 0x1
-#define SQ_WAVE_IB_DBG1__TA_NEED_RESET__SHIFT 0x2
-#define SQ_WAVE_IB_DBG1__XCNT__SHIFT 0x4
-#define SQ_WAVE_IB_DBG1__QCNT__SHIFT 0xb
-#define SQ_WAVE_IB_DBG1__RCNT__SHIFT 0x12
-#define SQ_WAVE_IB_DBG1__MISC_CNT__SHIFT 0x19
-#define SQ_WAVE_IB_DBG1__IXNACK_MASK 0x00000001L
-#define SQ_WAVE_IB_DBG1__XNACK_MASK 0x00000002L
-#define SQ_WAVE_IB_DBG1__TA_NEED_RESET_MASK 0x00000004L
-#define SQ_WAVE_IB_DBG1__XCNT_MASK 0x000001F0L
-#define SQ_WAVE_IB_DBG1__QCNT_MASK 0x0000F800L
-#define SQ_WAVE_IB_DBG1__RCNT_MASK 0x007C0000L
-#define SQ_WAVE_IB_DBG1__MISC_CNT_MASK 0xFE000000L
-//SQ_WAVE_FLUSH_IB
-#define SQ_WAVE_FLUSH_IB__UNUSED__SHIFT 0x0
-#define SQ_WAVE_FLUSH_IB__UNUSED_MASK 0xFFFFFFFFL
-//SQ_WAVE_TTMP0
-#define SQ_WAVE_TTMP0__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP0__DATA_MASK 0xFFFFFFFFL
-//SQ_WAVE_TTMP1
-#define SQ_WAVE_TTMP1__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP1__DATA_MASK 0xFFFFFFFFL
-//SQ_WAVE_TTMP2
-#define SQ_WAVE_TTMP2__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP2__DATA_MASK 0xFFFFFFFFL
-//SQ_WAVE_TTMP3
-#define SQ_WAVE_TTMP3__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP3__DATA_MASK 0xFFFFFFFFL
-//SQ_WAVE_TTMP4
-#define SQ_WAVE_TTMP4__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP4__DATA_MASK 0xFFFFFFFFL
-//SQ_WAVE_TTMP5
-#define SQ_WAVE_TTMP5__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP5__DATA_MASK 0xFFFFFFFFL
-//SQ_WAVE_TTMP6
-#define SQ_WAVE_TTMP6__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP6__DATA_MASK 0xFFFFFFFFL
-//SQ_WAVE_TTMP7
-#define SQ_WAVE_TTMP7__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP7__DATA_MASK 0xFFFFFFFFL
-//SQ_WAVE_TTMP8
-#define SQ_WAVE_TTMP8__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP8__DATA_MASK 0xFFFFFFFFL
-//SQ_WAVE_TTMP9
-#define SQ_WAVE_TTMP9__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP9__DATA_MASK 0xFFFFFFFFL
-//SQ_WAVE_TTMP10
-#define SQ_WAVE_TTMP10__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP10__DATA_MASK 0xFFFFFFFFL
-//SQ_WAVE_TTMP11
-#define SQ_WAVE_TTMP11__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP11__DATA_MASK 0xFFFFFFFFL
-//SQ_WAVE_TTMP12
-#define SQ_WAVE_TTMP12__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP12__DATA_MASK 0xFFFFFFFFL
-//SQ_WAVE_TTMP13
-#define SQ_WAVE_TTMP13__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP13__DATA_MASK 0xFFFFFFFFL
-//SQ_WAVE_TTMP14
-#define SQ_WAVE_TTMP14__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP14__DATA_MASK 0xFFFFFFFFL
-//SQ_WAVE_TTMP15
-#define SQ_WAVE_TTMP15__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP15__DATA_MASK 0xFFFFFFFFL
-//SQ_WAVE_M0
-#define SQ_WAVE_M0__M0__SHIFT 0x0
-#define SQ_WAVE_M0__M0_MASK 0xFFFFFFFFL
-//SQ_WAVE_EXEC_LO
-#define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x0
-#define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xFFFFFFFFL
-//SQ_WAVE_EXEC_HI
-#define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x0
-#define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xFFFFFFFFL
-//SQ_INTERRUPT_WORD_AUTO_CTXID
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE__SHIFT 0x0
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT__SHIFT 0x1
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL__SHIFT 0x2
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP__SHIFT 0x3
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP__SHIFT 0x4
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW__SHIFT 0x5
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW__SHIFT 0x6
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW__SHIFT 0x7
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR__SHIFT 0x8
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID__SHIFT 0x18
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING__SHIFT 0x1a
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_MASK 0x0000001L
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT_MASK 0x0000002L
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL_MASK 0x0000004L
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP_MASK 0x0000008L
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP_MASK 0x0000010L
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW_MASK 0x0000020L
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW_MASK 0x0000040L
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW_MASK 0x0000080L
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR_MASK 0x0000100L
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID_MASK 0x3000000L
-#define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING_MASK 0xC000000L
-//SQ_INTERRUPT_WORD_AUTO_HI
-#define SQ_INTERRUPT_WORD_AUTO_HI__SE_ID__SHIFT 0x8
-#define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING__SHIFT 0xa
-#define SQ_INTERRUPT_WORD_AUTO_HI__SE_ID_MASK 0x300L
-#define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING_MASK 0xC00L
-//SQ_INTERRUPT_WORD_AUTO_LO
-#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE__SHIFT 0x0
-#define SQ_INTERRUPT_WORD_AUTO_LO__WLT__SHIFT 0x1
-#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL__SHIFT 0x2
-#define SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP__SHIFT 0x3
-#define SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP__SHIFT 0x4
-#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW__SHIFT 0x5
-#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW__SHIFT 0x6
-#define SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW__SHIFT 0x7
-#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR__SHIFT 0x8
-#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_MASK 0x001L
-#define SQ_INTERRUPT_WORD_AUTO_LO__WLT_MASK 0x002L
-#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL_MASK 0x004L
-#define SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP_MASK 0x008L
-#define SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP_MASK 0x010L
-#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW_MASK 0x020L
-#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW_MASK 0x040L
-#define SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW_MASK 0x080L
-#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR_MASK 0x100L
-//SQ_INTERRUPT_WORD_CMN_CTXID
-#define SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID__SHIFT 0x18
-#define SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING__SHIFT 0x1a
-#define SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID_MASK 0x3000000L
-#define SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING_MASK 0xC000000L
-//SQ_INTERRUPT_WORD_CMN_HI
-#define SQ_INTERRUPT_WORD_CMN_HI__SE_ID__SHIFT 0x8
-#define SQ_INTERRUPT_WORD_CMN_HI__ENCODING__SHIFT 0xa
-#define SQ_INTERRUPT_WORD_CMN_HI__SE_ID_MASK 0x300L
-#define SQ_INTERRUPT_WORD_CMN_HI__ENCODING_MASK 0xC00L
-//SQ_INTERRUPT_WORD_WAVE_CTXID
-#define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA__SHIFT 0x0
-#define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID__SHIFT 0xc
-#define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV__SHIFT 0xd
-#define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID__SHIFT 0xe
-#define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID__SHIFT 0x12
-#define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID__SHIFT 0x14
-#define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID__SHIFT 0x18
-#define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING__SHIFT 0x1a
-#define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA_MASK 0x0000FFFL
-#define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID_MASK 0x0001000L
-#define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV_MASK 0x0002000L
-#define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID_MASK 0x003C000L
-#define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID_MASK 0x00C0000L
-#define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID_MASK 0x0F00000L
-#define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID_MASK 0x3000000L
-#define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING_MASK 0xC000000L
-//SQ_INTERRUPT_WORD_WAVE_HI
-#define SQ_INTERRUPT_WORD_WAVE_HI__CU_ID__SHIFT 0x0
-#define SQ_INTERRUPT_WORD_WAVE_HI__VM_ID__SHIFT 0x4
-#define SQ_INTERRUPT_WORD_WAVE_HI__SE_ID__SHIFT 0x8
-#define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING__SHIFT 0xa
-#define SQ_INTERRUPT_WORD_WAVE_HI__CU_ID_MASK 0x00FL
-#define SQ_INTERRUPT_WORD_WAVE_HI__VM_ID_MASK 0x0F0L
-#define SQ_INTERRUPT_WORD_WAVE_HI__SE_ID_MASK 0x300L
-#define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING_MASK 0xC00L
-//SQ_INTERRUPT_WORD_WAVE_LO
-#define SQ_INTERRUPT_WORD_WAVE_LO__DATA__SHIFT 0x0
-#define SQ_INTERRUPT_WORD_WAVE_LO__SH_ID__SHIFT 0x18
-#define SQ_INTERRUPT_WORD_WAVE_LO__PRIV__SHIFT 0x19
-#define SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID__SHIFT 0x1a
-#define SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID__SHIFT 0x1e
-#define SQ_INTERRUPT_WORD_WAVE_LO__DATA_MASK 0x00FFFFFFL
-#define SQ_INTERRUPT_WORD_WAVE_LO__SH_ID_MASK 0x01000000L
-#define SQ_INTERRUPT_WORD_WAVE_LO__PRIV_MASK 0x02000000L
-#define SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID_MASK 0x3C000000L
-#define SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID_MASK 0xC0000000L
-
-
-
-
-
-
-
-
-// addressBlock: didtind
-//DIDT_SQ_CTRL0
-#define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
-#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x1
-#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x3
-#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
-#define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5
-#define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6
-#define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7
-#define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8
-#define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18
-#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19
-#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a
-#define DIDT_SQ_CTRL0__UNUSED_0__SHIFT 0x1b
-#define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
-#define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0x00000006L
-#define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L
-#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
-#define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L
-#define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L
-#define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L
-#define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L
-#define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L
-#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L
-#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L
-#define DIDT_SQ_CTRL0__UNUSED_0_MASK 0xF8000000L
-//DIDT_SQ_CTRL1
-#define DIDT_SQ_CTRL1__MIN_POWER__SHIFT 0x0
-#define DIDT_SQ_CTRL1__MAX_POWER__SHIFT 0x10
-#define DIDT_SQ_CTRL1__MIN_POWER_MASK 0x0000FFFFL
-#define DIDT_SQ_CTRL1__MAX_POWER_MASK 0xFFFF0000L
-//DIDT_SQ_CTRL2
-#define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
-#define DIDT_SQ_CTRL2__UNUSED_0__SHIFT 0xe
-#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
-#define DIDT_SQ_CTRL2__UNUSED_1__SHIFT 0x1a
-#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
-#define DIDT_SQ_CTRL2__UNUSED_2__SHIFT 0x1f
-#define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
-#define DIDT_SQ_CTRL2__UNUSED_0_MASK 0x0000C000L
-#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
-#define DIDT_SQ_CTRL2__UNUSED_1_MASK 0x04000000L
-#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
-#define DIDT_SQ_CTRL2__UNUSED_2_MASK 0x80000000L
-//DIDT_SQ_STALL_CTRL
-#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0
-#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6
-#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc
-#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12
-#define DIDT_SQ_STALL_CTRL__UNUSED_0__SHIFT 0x18
-#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL
-#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L
-#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L
-#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L
-#define DIDT_SQ_STALL_CTRL__UNUSED_0_MASK 0xFF000000L
-//DIDT_SQ_TUNING_CTRL
-#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0
-#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
-#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL
-#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L
-//DIDT_SQ_STALL_AUTO_RELEASE_CTRL
-#define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0
-#define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL
-//DIDT_SQ_CTRL3
-#define DIDT_SQ_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0
-#define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1
-#define DIDT_SQ_CTRL3__THROTTLE_POLICY__SHIFT 0x2
-#define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
-#define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9
-#define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
-#define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16
-#define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17
-#define DIDT_SQ_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18
-#define DIDT_SQ_CTRL3__DIDT_STALL_SEL__SHIFT 0x19
-#define DIDT_SQ_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b
-#define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c
-#define DIDT_SQ_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L
-#define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L
-#define DIDT_SQ_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL
-#define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
-#define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L
-#define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L
-#define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L
-#define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L
-#define DIDT_SQ_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L
-#define DIDT_SQ_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L
-#define DIDT_SQ_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L
-#define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L
-//DIDT_SQ_STALL_PATTERN_1_2
-#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0
-#define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
-#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10
-#define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
-#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL
-#define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
-#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L
-#define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
-//DIDT_SQ_STALL_PATTERN_3_4
-#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0
-#define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
-#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10
-#define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
-#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL
-#define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
-#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L
-#define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
-//DIDT_SQ_STALL_PATTERN_5_6
-#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0
-#define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
-#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10
-#define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
-#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL
-#define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
-#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L
-#define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
-//DIDT_SQ_STALL_PATTERN_7
-#define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0
-#define DIDT_SQ_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
-#define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL
-#define DIDT_SQ_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
-//DIDT_SQ_WEIGHT0_3
-#define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT 0x0
-#define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT 0x8
-#define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT 0x10
-#define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT 0x18
-#define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL
-#define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L
-#define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L
-#define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L
-//DIDT_SQ_WEIGHT4_7
-#define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT 0x0
-#define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT 0x8
-#define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT 0x10
-#define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT 0x18
-#define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL
-#define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L
-#define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L
-#define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L
-//DIDT_SQ_WEIGHT8_11
-#define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT 0x0
-#define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT 0x8
-#define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT 0x10
-#define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT 0x18
-#define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL
-#define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L
-#define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L
-#define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L
-//DIDT_SQ_EDC_CTRL
-#define DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT 0x0
-#define DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
-#define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
-#define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
-#define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
-#define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9
-#define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11
-#define DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT 0x12
-#define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13
-#define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15
-#define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16
-#define DIDT_SQ_EDC_CTRL__UNUSED_0__SHIFT 0x17
-#define DIDT_SQ_EDC_CTRL__EDC_EN_MASK 0x00000001L
-#define DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
-#define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
-#define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
-#define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
-#define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L
-#define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L
-#define DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L
-#define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L
-#define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L
-#define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L
-#define DIDT_SQ_EDC_CTRL__UNUSED_0_MASK 0xFF800000L
-//DIDT_SQ_EDC_THRESHOLD
-#define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
-#define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
-//DIDT_SQ_EDC_STALL_PATTERN_1_2
-#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0
-#define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
-#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10
-#define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
-#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL
-#define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
-#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L
-#define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
-//DIDT_SQ_EDC_STALL_PATTERN_3_4
-#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0
-#define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
-#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10
-#define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
-#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL
-#define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
-#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L
-#define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
-//DIDT_SQ_EDC_STALL_PATTERN_5_6
-#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0
-#define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
-#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10
-#define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
-#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL
-#define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
-#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L
-#define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
-//DIDT_SQ_EDC_STALL_PATTERN_7
-#define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0
-#define DIDT_SQ_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
-#define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL
-#define DIDT_SQ_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
-//DIDT_SQ_EDC_STATUS
-#define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0
-#define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1
-#define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L
-#define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL
-//DIDT_SQ_EDC_STALL_DELAY_1
-#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0__SHIFT 0x0
-#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1__SHIFT 0x6
-#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2__SHIFT 0xc
-#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3__SHIFT 0x12
-#define DIDT_SQ_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x18
-#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0_MASK 0x0000003FL
-#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1_MASK 0x00000FC0L
-#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2_MASK 0x0003F000L
-#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3_MASK 0x00FC0000L
-#define DIDT_SQ_EDC_STALL_DELAY_1__UNUSED_MASK 0xFF000000L
-//DIDT_SQ_EDC_STALL_DELAY_2
-#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4__SHIFT 0x0
-#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5__SHIFT 0x6
-#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6__SHIFT 0xc
-#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7__SHIFT 0x12
-#define DIDT_SQ_EDC_STALL_DELAY_2__UNUSED__SHIFT 0x18
-#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4_MASK 0x0000003FL
-#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5_MASK 0x00000FC0L
-#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6_MASK 0x0003F000L
-#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7_MASK 0x00FC0000L
-#define DIDT_SQ_EDC_STALL_DELAY_2__UNUSED_MASK 0xFF000000L
-//DIDT_SQ_EDC_STALL_DELAY_3
-#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8__SHIFT 0x0
-#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9__SHIFT 0x6
-#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10__SHIFT 0xc
-#define DIDT_SQ_EDC_STALL_DELAY_3__UNUSED__SHIFT 0x12
-#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8_MASK 0x0000003FL
-#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9_MASK 0x00000FC0L
-#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10_MASK 0x0003F000L
-#define DIDT_SQ_EDC_STALL_DELAY_3__UNUSED_MASK 0xFFFC0000L
-//DIDT_SQ_EDC_OVERFLOW
-#define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0
-#define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1
-#define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L
-#define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL
-//DIDT_SQ_EDC_ROLLING_POWER_DELTA
-#define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0
-#define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL
-//DIDT_DB_CTRL0
-#define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
-#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x1
-#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x3
-#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
-#define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5
-#define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6
-#define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7
-#define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8
-#define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18
-#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19
-#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a
-#define DIDT_DB_CTRL0__UNUSED_0__SHIFT 0x1b
-#define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
-#define DIDT_DB_CTRL0__PHASE_OFFSET_MASK 0x00000006L
-#define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L
-#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
-#define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L
-#define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L
-#define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L
-#define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L
-#define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L
-#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L
-#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L
-#define DIDT_DB_CTRL0__UNUSED_0_MASK 0xF8000000L
-//DIDT_DB_CTRL1
-#define DIDT_DB_CTRL1__MIN_POWER__SHIFT 0x0
-#define DIDT_DB_CTRL1__MAX_POWER__SHIFT 0x10
-#define DIDT_DB_CTRL1__MIN_POWER_MASK 0x0000FFFFL
-#define DIDT_DB_CTRL1__MAX_POWER_MASK 0xFFFF0000L
-//DIDT_DB_CTRL2
-#define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
-#define DIDT_DB_CTRL2__UNUSED_0__SHIFT 0xe
-#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
-#define DIDT_DB_CTRL2__UNUSED_1__SHIFT 0x1a
-#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
-#define DIDT_DB_CTRL2__UNUSED_2__SHIFT 0x1f
-#define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
-#define DIDT_DB_CTRL2__UNUSED_0_MASK 0x0000C000L
-#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
-#define DIDT_DB_CTRL2__UNUSED_1_MASK 0x04000000L
-#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
-#define DIDT_DB_CTRL2__UNUSED_2_MASK 0x80000000L
-//DIDT_DB_STALL_CTRL
-#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0
-#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6
-#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc
-#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12
-#define DIDT_DB_STALL_CTRL__UNUSED_0__SHIFT 0x18
-#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL
-#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L
-#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L
-#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L
-#define DIDT_DB_STALL_CTRL__UNUSED_0_MASK 0xFF000000L
-//DIDT_DB_TUNING_CTRL
-#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0
-#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
-#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL
-#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L
-//DIDT_DB_STALL_AUTO_RELEASE_CTRL
-#define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0
-#define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL
-//DIDT_DB_CTRL3
-#define DIDT_DB_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0
-#define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1
-#define DIDT_DB_CTRL3__THROTTLE_POLICY__SHIFT 0x2
-#define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
-#define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9
-#define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
-#define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16
-#define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17
-#define DIDT_DB_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18
-#define DIDT_DB_CTRL3__DIDT_STALL_SEL__SHIFT 0x19
-#define DIDT_DB_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b
-#define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c
-#define DIDT_DB_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L
-#define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L
-#define DIDT_DB_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL
-#define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
-#define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L
-#define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L
-#define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L
-#define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L
-#define DIDT_DB_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L
-#define DIDT_DB_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L
-#define DIDT_DB_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L
-#define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L
-//DIDT_DB_STALL_PATTERN_1_2
-#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0
-#define DIDT_DB_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
-#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10
-#define DIDT_DB_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
-#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL
-#define DIDT_DB_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
-#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L
-#define DIDT_DB_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
-//DIDT_DB_STALL_PATTERN_3_4
-#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0
-#define DIDT_DB_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
-#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10
-#define DIDT_DB_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
-#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL
-#define DIDT_DB_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
-#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L
-#define DIDT_DB_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
-//DIDT_DB_STALL_PATTERN_5_6
-#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0
-#define DIDT_DB_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
-#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10
-#define DIDT_DB_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
-#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL
-#define DIDT_DB_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
-#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L
-#define DIDT_DB_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
-//DIDT_DB_STALL_PATTERN_7
-#define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0
-#define DIDT_DB_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
-#define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL
-#define DIDT_DB_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
-//DIDT_DB_WEIGHT0_3
-#define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT 0x0
-#define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT 0x8
-#define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT 0x10
-#define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT 0x18
-#define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL
-#define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L
-#define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L
-#define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L
-//DIDT_DB_WEIGHT4_7
-#define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT 0x0
-#define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT 0x8
-#define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT 0x10
-#define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT 0x18
-#define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL
-#define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L
-#define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L
-#define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L
-//DIDT_DB_WEIGHT8_11
-#define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT 0x0
-#define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT 0x8
-#define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT 0x10
-#define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT 0x18
-#define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL
-#define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L
-#define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L
-#define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L
-//DIDT_DB_EDC_CTRL
-#define DIDT_DB_EDC_CTRL__EDC_EN__SHIFT 0x0
-#define DIDT_DB_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
-#define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
-#define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
-#define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
-#define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9
-#define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11
-#define DIDT_DB_EDC_CTRL__GC_EDC_EN__SHIFT 0x12
-#define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13
-#define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15
-#define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16
-#define DIDT_DB_EDC_CTRL__UNUSED_0__SHIFT 0x17
-#define DIDT_DB_EDC_CTRL__EDC_EN_MASK 0x00000001L
-#define DIDT_DB_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
-#define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
-#define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
-#define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
-#define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L
-#define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L
-#define DIDT_DB_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L
-#define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L
-#define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L
-#define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L
-#define DIDT_DB_EDC_CTRL__UNUSED_0_MASK 0xFF800000L
-//DIDT_DB_EDC_THRESHOLD
-#define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
-#define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
-//DIDT_DB_EDC_STALL_PATTERN_1_2
-#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0
-#define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
-#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10
-#define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
-#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL
-#define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
-#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L
-#define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
-//DIDT_DB_EDC_STALL_PATTERN_3_4
-#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0
-#define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
-#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10
-#define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
-#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL
-#define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
-#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L
-#define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
-//DIDT_DB_EDC_STALL_PATTERN_5_6
-#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0
-#define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
-#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10
-#define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
-#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL
-#define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
-#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L
-#define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
-//DIDT_DB_EDC_STALL_PATTERN_7
-#define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0
-#define DIDT_DB_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
-#define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL
-#define DIDT_DB_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
-//DIDT_DB_EDC_STATUS
-#define DIDT_DB_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0
-#define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1
-#define DIDT_DB_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L
-#define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL
-//DIDT_DB_EDC_STALL_DELAY_1
-#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0__SHIFT 0x0
-#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1__SHIFT 0x3
-#define DIDT_DB_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x6
-#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0_MASK 0x00000007L
-#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1_MASK 0x00000038L
-#define DIDT_DB_EDC_STALL_DELAY_1__UNUSED_MASK 0xFFFFFFC0L
-//DIDT_DB_EDC_OVERFLOW
-#define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0
-#define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1
-#define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L
-#define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL
-//DIDT_DB_EDC_ROLLING_POWER_DELTA
-#define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0
-#define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL
-//DIDT_TD_CTRL0
-#define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
-#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x1
-#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x3
-#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
-#define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5
-#define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6
-#define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7
-#define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8
-#define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18
-#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19
-#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a
-#define DIDT_TD_CTRL0__UNUSED_0__SHIFT 0x1b
-#define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
-#define DIDT_TD_CTRL0__PHASE_OFFSET_MASK 0x00000006L
-#define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L
-#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
-#define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L
-#define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L
-#define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L
-#define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L
-#define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L
-#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L
-#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L
-#define DIDT_TD_CTRL0__UNUSED_0_MASK 0xF8000000L
-//DIDT_TD_CTRL1
-#define DIDT_TD_CTRL1__MIN_POWER__SHIFT 0x0
-#define DIDT_TD_CTRL1__MAX_POWER__SHIFT 0x10
-#define DIDT_TD_CTRL1__MIN_POWER_MASK 0x0000FFFFL
-#define DIDT_TD_CTRL1__MAX_POWER_MASK 0xFFFF0000L
-//DIDT_TD_CTRL2
-#define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
-#define DIDT_TD_CTRL2__UNUSED_0__SHIFT 0xe
-#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
-#define DIDT_TD_CTRL2__UNUSED_1__SHIFT 0x1a
-#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
-#define DIDT_TD_CTRL2__UNUSED_2__SHIFT 0x1f
-#define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
-#define DIDT_TD_CTRL2__UNUSED_0_MASK 0x0000C000L
-#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
-#define DIDT_TD_CTRL2__UNUSED_1_MASK 0x04000000L
-#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
-#define DIDT_TD_CTRL2__UNUSED_2_MASK 0x80000000L
-//DIDT_TD_STALL_CTRL
-#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0
-#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6
-#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc
-#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12
-#define DIDT_TD_STALL_CTRL__UNUSED_0__SHIFT 0x18
-#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL
-#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L
-#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L
-#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L
-#define DIDT_TD_STALL_CTRL__UNUSED_0_MASK 0xFF000000L
-//DIDT_TD_TUNING_CTRL
-#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0
-#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
-#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL
-#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L
-//DIDT_TD_STALL_AUTO_RELEASE_CTRL
-#define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0
-#define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL
-//DIDT_TD_CTRL3
-#define DIDT_TD_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0
-#define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1
-#define DIDT_TD_CTRL3__THROTTLE_POLICY__SHIFT 0x2
-#define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
-#define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9
-#define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
-#define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16
-#define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17
-#define DIDT_TD_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18
-#define DIDT_TD_CTRL3__DIDT_STALL_SEL__SHIFT 0x19
-#define DIDT_TD_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b
-#define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c
-#define DIDT_TD_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L
-#define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L
-#define DIDT_TD_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL
-#define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
-#define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L
-#define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L
-#define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L
-#define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L
-#define DIDT_TD_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L
-#define DIDT_TD_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L
-#define DIDT_TD_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L
-#define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L
-//DIDT_TD_STALL_PATTERN_1_2
-#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0
-#define DIDT_TD_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
-#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10
-#define DIDT_TD_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
-#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL
-#define DIDT_TD_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
-#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L
-#define DIDT_TD_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
-//DIDT_TD_STALL_PATTERN_3_4
-#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0
-#define DIDT_TD_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
-#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10
-#define DIDT_TD_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
-#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL
-#define DIDT_TD_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
-#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L
-#define DIDT_TD_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
-//DIDT_TD_STALL_PATTERN_5_6
-#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0
-#define DIDT_TD_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
-#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10
-#define DIDT_TD_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
-#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL
-#define DIDT_TD_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
-#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L
-#define DIDT_TD_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
-//DIDT_TD_STALL_PATTERN_7
-#define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0
-#define DIDT_TD_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
-#define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL
-#define DIDT_TD_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
-//DIDT_TD_WEIGHT0_3
-#define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT 0x0
-#define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT 0x8
-#define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT 0x10
-#define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT 0x18
-#define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL
-#define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L
-#define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L
-#define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L
-//DIDT_TD_WEIGHT4_7
-#define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT 0x0
-#define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT 0x8
-#define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT 0x10
-#define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT 0x18
-#define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL
-#define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L
-#define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L
-#define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L
-//DIDT_TD_WEIGHT8_11
-#define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT 0x0
-#define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT 0x8
-#define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT 0x10
-#define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT 0x18
-#define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL
-#define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L
-#define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L
-#define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L
-//DIDT_TD_EDC_CTRL
-#define DIDT_TD_EDC_CTRL__EDC_EN__SHIFT 0x0
-#define DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
-#define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
-#define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
-#define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
-#define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9
-#define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11
-#define DIDT_TD_EDC_CTRL__GC_EDC_EN__SHIFT 0x12
-#define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13
-#define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15
-#define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16
-#define DIDT_TD_EDC_CTRL__UNUSED_0__SHIFT 0x17
-#define DIDT_TD_EDC_CTRL__EDC_EN_MASK 0x00000001L
-#define DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
-#define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
-#define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
-#define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
-#define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L
-#define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L
-#define DIDT_TD_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L
-#define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L
-#define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L
-#define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L
-#define DIDT_TD_EDC_CTRL__UNUSED_0_MASK 0xFF800000L
-//DIDT_TD_EDC_THRESHOLD
-#define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
-#define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
-//DIDT_TD_EDC_STALL_PATTERN_1_2
-#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0
-#define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
-#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10
-#define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
-#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL
-#define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
-#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L
-#define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
-//DIDT_TD_EDC_STALL_PATTERN_3_4
-#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0
-#define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
-#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10
-#define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
-#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL
-#define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
-#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L
-#define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
-//DIDT_TD_EDC_STALL_PATTERN_5_6
-#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0
-#define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
-#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10
-#define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
-#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL
-#define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
-#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L
-#define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
-//DIDT_TD_EDC_STALL_PATTERN_7
-#define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0
-#define DIDT_TD_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
-#define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL
-#define DIDT_TD_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
-//DIDT_TD_EDC_STATUS
-#define DIDT_TD_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0
-#define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1
-#define DIDT_TD_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L
-#define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL
-//DIDT_TD_EDC_STALL_DELAY_1
-#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0__SHIFT 0x0
-#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1__SHIFT 0x6
-#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2__SHIFT 0xc
-#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3__SHIFT 0x12
-#define DIDT_TD_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x18
-#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0_MASK 0x0000003FL
-#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1_MASK 0x00000FC0L
-#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2_MASK 0x0003F000L
-#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3_MASK 0x00FC0000L
-#define DIDT_TD_EDC_STALL_DELAY_1__UNUSED_MASK 0xFF000000L
-//DIDT_TD_EDC_STALL_DELAY_2
-#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4__SHIFT 0x0
-#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5__SHIFT 0x6
-#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6__SHIFT 0xc
-#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7__SHIFT 0x12
-#define DIDT_TD_EDC_STALL_DELAY_2__UNUSED__SHIFT 0x18
-#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4_MASK 0x0000003FL
-#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5_MASK 0x00000FC0L
-#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6_MASK 0x0003F000L
-#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7_MASK 0x00FC0000L
-#define DIDT_TD_EDC_STALL_DELAY_2__UNUSED_MASK 0xFF000000L
-//DIDT_TD_EDC_STALL_DELAY_3
-#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8__SHIFT 0x0
-#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9__SHIFT 0x6
-#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD10__SHIFT 0xc
-#define DIDT_TD_EDC_STALL_DELAY_3__UNUSED__SHIFT 0x12
-#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8_MASK 0x0000003FL
-#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9_MASK 0x00000FC0L
-#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD10_MASK 0x0003F000L
-#define DIDT_TD_EDC_STALL_DELAY_3__UNUSED_MASK 0xFFFC0000L
-//DIDT_TD_EDC_OVERFLOW
-#define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0
-#define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1
-#define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L
-#define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL
-//DIDT_TD_EDC_ROLLING_POWER_DELTA
-#define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0
-#define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL
-//DIDT_TCP_CTRL0
-#define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
-#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x1
-#define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT 0x3
-#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
-#define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5
-#define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6
-#define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7
-#define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8
-#define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18
-#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19
-#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a
-#define DIDT_TCP_CTRL0__UNUSED_0__SHIFT 0x1b
-#define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
-#define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK 0x00000006L
-#define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L
-#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
-#define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L
-#define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L
-#define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L
-#define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L
-#define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L
-#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L
-#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L
-#define DIDT_TCP_CTRL0__UNUSED_0_MASK 0xF8000000L
-//DIDT_TCP_CTRL1
-#define DIDT_TCP_CTRL1__MIN_POWER__SHIFT 0x0
-#define DIDT_TCP_CTRL1__MAX_POWER__SHIFT 0x10
-#define DIDT_TCP_CTRL1__MIN_POWER_MASK 0x0000FFFFL
-#define DIDT_TCP_CTRL1__MAX_POWER_MASK 0xFFFF0000L
-//DIDT_TCP_CTRL2
-#define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
-#define DIDT_TCP_CTRL2__UNUSED_0__SHIFT 0xe
-#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
-#define DIDT_TCP_CTRL2__UNUSED_1__SHIFT 0x1a
-#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
-#define DIDT_TCP_CTRL2__UNUSED_2__SHIFT 0x1f
-#define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
-#define DIDT_TCP_CTRL2__UNUSED_0_MASK 0x0000C000L
-#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
-#define DIDT_TCP_CTRL2__UNUSED_1_MASK 0x04000000L
-#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
-#define DIDT_TCP_CTRL2__UNUSED_2_MASK 0x80000000L
-//DIDT_TCP_STALL_CTRL
-#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0
-#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6
-#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc
-#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12
-#define DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT 0x18
-#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL
-#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L
-#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L
-#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L
-#define DIDT_TCP_STALL_CTRL__UNUSED_0_MASK 0xFF000000L
-//DIDT_TCP_TUNING_CTRL
-#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0
-#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
-#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL
-#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L
-//DIDT_TCP_STALL_AUTO_RELEASE_CTRL
-#define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0
-#define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL
-//DIDT_TCP_CTRL3
-#define DIDT_TCP_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0
-#define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1
-#define DIDT_TCP_CTRL3__THROTTLE_POLICY__SHIFT 0x2
-#define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
-#define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9
-#define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
-#define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16
-#define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17
-#define DIDT_TCP_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18
-#define DIDT_TCP_CTRL3__DIDT_STALL_SEL__SHIFT 0x19
-#define DIDT_TCP_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b
-#define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c
-#define DIDT_TCP_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L
-#define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L
-#define DIDT_TCP_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL
-#define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
-#define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L
-#define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L
-#define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L
-#define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L
-#define DIDT_TCP_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L
-#define DIDT_TCP_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L
-#define DIDT_TCP_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L
-#define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L
-//DIDT_TCP_STALL_PATTERN_1_2
-#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0
-#define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
-#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10
-#define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
-#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL
-#define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
-#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L
-#define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
-//DIDT_TCP_STALL_PATTERN_3_4
-#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0
-#define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
-#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10
-#define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
-#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL
-#define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
-#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L
-#define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
-//DIDT_TCP_STALL_PATTERN_5_6
-#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0
-#define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
-#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10
-#define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
-#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL
-#define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
-#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L
-#define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
-//DIDT_TCP_STALL_PATTERN_7
-#define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0
-#define DIDT_TCP_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
-#define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL
-#define DIDT_TCP_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
-//DIDT_TCP_WEIGHT0_3
-#define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT 0x0
-#define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT 0x8
-#define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT 0x10
-#define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT 0x18
-#define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL
-#define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L
-#define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L
-#define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L
-//DIDT_TCP_WEIGHT4_7
-#define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT 0x0
-#define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT 0x8
-#define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT 0x10
-#define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT 0x18
-#define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL
-#define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L
-#define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L
-#define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L
-//DIDT_TCP_WEIGHT8_11
-#define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT 0x0
-#define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT 0x8
-#define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT 0x10
-#define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT 0x18
-#define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL
-#define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L
-#define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L
-#define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L
-//DIDT_TCP_EDC_CTRL
-#define DIDT_TCP_EDC_CTRL__EDC_EN__SHIFT 0x0
-#define DIDT_TCP_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
-#define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
-#define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
-#define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
-#define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9
-#define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11
-#define DIDT_TCP_EDC_CTRL__GC_EDC_EN__SHIFT 0x12
-#define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13
-#define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15
-#define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16
-#define DIDT_TCP_EDC_CTRL__UNUSED_0__SHIFT 0x17
-#define DIDT_TCP_EDC_CTRL__EDC_EN_MASK 0x00000001L
-#define DIDT_TCP_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
-#define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
-#define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
-#define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
-#define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L
-#define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L
-#define DIDT_TCP_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L
-#define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L
-#define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L
-#define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L
-#define DIDT_TCP_EDC_CTRL__UNUSED_0_MASK 0xFF800000L
-//DIDT_TCP_EDC_THRESHOLD
-#define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
-#define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
-//DIDT_TCP_EDC_STALL_PATTERN_1_2
-#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0
-#define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
-#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10
-#define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
-#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL
-#define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
-#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L
-#define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
-//DIDT_TCP_EDC_STALL_PATTERN_3_4
-#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0
-#define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
-#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10
-#define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
-#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL
-#define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
-#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L
-#define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
-//DIDT_TCP_EDC_STALL_PATTERN_5_6
-#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0
-#define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
-#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10
-#define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
-#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL
-#define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
-#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L
-#define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
-//DIDT_TCP_EDC_STALL_PATTERN_7
-#define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0
-#define DIDT_TCP_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
-#define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL
-#define DIDT_TCP_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
-//DIDT_TCP_EDC_STATUS
-#define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0
-#define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1
-#define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L
-#define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL
-//DIDT_TCP_EDC_STALL_DELAY_1
-#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0__SHIFT 0x0
-#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1__SHIFT 0x6
-#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2__SHIFT 0xc
-#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3__SHIFT 0x12
-#define DIDT_TCP_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x18
-#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0_MASK 0x0000003FL
-#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1_MASK 0x00000FC0L
-#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2_MASK 0x0003F000L
-#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3_MASK 0x00FC0000L
-#define DIDT_TCP_EDC_STALL_DELAY_1__UNUSED_MASK 0xFF000000L
-//DIDT_TCP_EDC_STALL_DELAY_2
-#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4__SHIFT 0x0
-#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5__SHIFT 0x6
-#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6__SHIFT 0xc
-#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7__SHIFT 0x12
-#define DIDT_TCP_EDC_STALL_DELAY_2__UNUSED__SHIFT 0x18
-#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4_MASK 0x0000003FL
-#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5_MASK 0x00000FC0L
-#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6_MASK 0x0003F000L
-#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7_MASK 0x00FC0000L
-#define DIDT_TCP_EDC_STALL_DELAY_2__UNUSED_MASK 0xFF000000L
-//DIDT_TCP_EDC_STALL_DELAY_3
-#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8__SHIFT 0x0
-#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9__SHIFT 0x6
-#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP10__SHIFT 0xc
-#define DIDT_TCP_EDC_STALL_DELAY_3__UNUSED__SHIFT 0x12
-#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8_MASK 0x0000003FL
-#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9_MASK 0x00000FC0L
-#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP10_MASK 0x0003F000L
-#define DIDT_TCP_EDC_STALL_DELAY_3__UNUSED_MASK 0xFFFC0000L
-//DIDT_TCP_EDC_OVERFLOW
-#define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0
-#define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1
-#define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L
-#define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL
-//DIDT_TCP_EDC_ROLLING_POWER_DELTA
-#define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0
-#define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL
-//DIDT_DBR_CTRL0
-#define DIDT_DBR_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
-#define DIDT_DBR_CTRL0__PHASE_OFFSET__SHIFT 0x1
-#define DIDT_DBR_CTRL0__DIDT_CTRL_RST__SHIFT 0x3
-#define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
-#define DIDT_DBR_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5
-#define DIDT_DBR_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6
-#define DIDT_DBR_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7
-#define DIDT_DBR_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8
-#define DIDT_DBR_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18
-#define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19
-#define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a
-#define DIDT_DBR_CTRL0__UNUSED_0__SHIFT 0x1b
-#define DIDT_DBR_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
-#define DIDT_DBR_CTRL0__PHASE_OFFSET_MASK 0x00000006L
-#define DIDT_DBR_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L
-#define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
-#define DIDT_DBR_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L
-#define DIDT_DBR_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L
-#define DIDT_DBR_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L
-#define DIDT_DBR_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L
-#define DIDT_DBR_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L
-#define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L
-#define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L
-#define DIDT_DBR_CTRL0__UNUSED_0_MASK 0xF8000000L
-//DIDT_DBR_CTRL1
-#define DIDT_DBR_CTRL1__MIN_POWER__SHIFT 0x0
-#define DIDT_DBR_CTRL1__MAX_POWER__SHIFT 0x10
-#define DIDT_DBR_CTRL1__MIN_POWER_MASK 0x0000FFFFL
-#define DIDT_DBR_CTRL1__MAX_POWER_MASK 0xFFFF0000L
-//DIDT_DBR_CTRL2
-#define DIDT_DBR_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
-#define DIDT_DBR_CTRL2__UNUSED_0__SHIFT 0xe
-#define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
-#define DIDT_DBR_CTRL2__UNUSED_1__SHIFT 0x1a
-#define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
-#define DIDT_DBR_CTRL2__UNUSED_2__SHIFT 0x1f
-#define DIDT_DBR_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
-#define DIDT_DBR_CTRL2__UNUSED_0_MASK 0x0000C000L
-#define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
-#define DIDT_DBR_CTRL2__UNUSED_1_MASK 0x04000000L
-#define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
-#define DIDT_DBR_CTRL2__UNUSED_2_MASK 0x80000000L
-//DIDT_DBR_STALL_CTRL
-#define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0
-#define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6
-#define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc
-#define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12
-#define DIDT_DBR_STALL_CTRL__UNUSED_0__SHIFT 0x18
-#define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL
-#define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L
-#define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L
-#define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L
-#define DIDT_DBR_STALL_CTRL__UNUSED_0_MASK 0xFF000000L
-//DIDT_DBR_TUNING_CTRL
-#define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0
-#define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
-#define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL
-#define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L
-//DIDT_DBR_STALL_AUTO_RELEASE_CTRL
-#define DIDT_DBR_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0
-#define DIDT_DBR_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL
-//DIDT_DBR_CTRL3
-#define DIDT_DBR_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0
-#define DIDT_DBR_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1
-#define DIDT_DBR_CTRL3__THROTTLE_POLICY__SHIFT 0x2
-#define DIDT_DBR_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
-#define DIDT_DBR_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9
-#define DIDT_DBR_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
-#define DIDT_DBR_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16
-#define DIDT_DBR_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17
-#define DIDT_DBR_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18
-#define DIDT_DBR_CTRL3__DIDT_STALL_SEL__SHIFT 0x19
-#define DIDT_DBR_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b
-#define DIDT_DBR_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c
-#define DIDT_DBR_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L
-#define DIDT_DBR_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L
-#define DIDT_DBR_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL
-#define DIDT_DBR_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
-#define DIDT_DBR_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L
-#define DIDT_DBR_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L
-#define DIDT_DBR_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L
-#define DIDT_DBR_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L
-#define DIDT_DBR_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L
-#define DIDT_DBR_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L
-#define DIDT_DBR_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L
-#define DIDT_DBR_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L
-//DIDT_DBR_STALL_PATTERN_1_2
-#define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0
-#define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
-#define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10
-#define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
-#define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL
-#define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
-#define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L
-#define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
-//DIDT_DBR_STALL_PATTERN_3_4
-#define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0
-#define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
-#define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10
-#define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
-#define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL
-#define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
-#define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L
-#define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
-//DIDT_DBR_STALL_PATTERN_5_6
-#define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0
-#define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
-#define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10
-#define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
-#define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL
-#define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
-#define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L
-#define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
-//DIDT_DBR_STALL_PATTERN_7
-#define DIDT_DBR_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0
-#define DIDT_DBR_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
-#define DIDT_DBR_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL
-#define DIDT_DBR_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
-//DIDT_DBR_WEIGHT0_3
-#define DIDT_DBR_WEIGHT0_3__WEIGHT0__SHIFT 0x0
-#define DIDT_DBR_WEIGHT0_3__WEIGHT1__SHIFT 0x8
-#define DIDT_DBR_WEIGHT0_3__WEIGHT2__SHIFT 0x10
-#define DIDT_DBR_WEIGHT0_3__WEIGHT3__SHIFT 0x18
-#define DIDT_DBR_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL
-#define DIDT_DBR_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L
-#define DIDT_DBR_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L
-#define DIDT_DBR_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L
-//DIDT_DBR_WEIGHT4_7
-#define DIDT_DBR_WEIGHT4_7__WEIGHT4__SHIFT 0x0
-#define DIDT_DBR_WEIGHT4_7__WEIGHT5__SHIFT 0x8
-#define DIDT_DBR_WEIGHT4_7__WEIGHT6__SHIFT 0x10
-#define DIDT_DBR_WEIGHT4_7__WEIGHT7__SHIFT 0x18
-#define DIDT_DBR_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL
-#define DIDT_DBR_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L
-#define DIDT_DBR_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L
-#define DIDT_DBR_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L
-//DIDT_DBR_WEIGHT8_11
-#define DIDT_DBR_WEIGHT8_11__WEIGHT8__SHIFT 0x0
-#define DIDT_DBR_WEIGHT8_11__WEIGHT9__SHIFT 0x8
-#define DIDT_DBR_WEIGHT8_11__WEIGHT10__SHIFT 0x10
-#define DIDT_DBR_WEIGHT8_11__WEIGHT11__SHIFT 0x18
-#define DIDT_DBR_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL
-#define DIDT_DBR_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L
-#define DIDT_DBR_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L
-#define DIDT_DBR_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L
-//DIDT_DBR_EDC_CTRL
-#define DIDT_DBR_EDC_CTRL__EDC_EN__SHIFT 0x0
-#define DIDT_DBR_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
-#define DIDT_DBR_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
-#define DIDT_DBR_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
-#define DIDT_DBR_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
-#define DIDT_DBR_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9
-#define DIDT_DBR_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11
-#define DIDT_DBR_EDC_CTRL__GC_EDC_EN__SHIFT 0x12
-#define DIDT_DBR_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13
-#define DIDT_DBR_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15
-#define DIDT_DBR_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16
-#define DIDT_DBR_EDC_CTRL__UNUSED_0__SHIFT 0x17
-#define DIDT_DBR_EDC_CTRL__EDC_EN_MASK 0x00000001L
-#define DIDT_DBR_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
-#define DIDT_DBR_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
-#define DIDT_DBR_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
-#define DIDT_DBR_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
-#define DIDT_DBR_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L
-#define DIDT_DBR_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L
-#define DIDT_DBR_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L
-#define DIDT_DBR_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L
-#define DIDT_DBR_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L
-#define DIDT_DBR_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L
-#define DIDT_DBR_EDC_CTRL__UNUSED_0_MASK 0xFF800000L
-//DIDT_DBR_EDC_THRESHOLD
-#define DIDT_DBR_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
-#define DIDT_DBR_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
-//DIDT_DBR_EDC_STALL_PATTERN_1_2
-#define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0
-#define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf
-#define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10
-#define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f
-#define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL
-#define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L
-#define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L
-#define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L
-//DIDT_DBR_EDC_STALL_PATTERN_3_4
-#define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0
-#define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf
-#define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10
-#define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f
-#define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL
-#define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L
-#define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L
-#define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L
-//DIDT_DBR_EDC_STALL_PATTERN_5_6
-#define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0
-#define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf
-#define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10
-#define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f
-#define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL
-#define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L
-#define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L
-#define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L
-//DIDT_DBR_EDC_STALL_PATTERN_7
-#define DIDT_DBR_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0
-#define DIDT_DBR_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf
-#define DIDT_DBR_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL
-#define DIDT_DBR_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L
-//DIDT_DBR_EDC_STATUS
-#define DIDT_DBR_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0
-#define DIDT_DBR_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1
-#define DIDT_DBR_EDC_STATUS__UNUSED_0__SHIFT 0x4
-#define DIDT_DBR_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L
-#define DIDT_DBR_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL
-#define DIDT_DBR_EDC_STATUS__UNUSED_0_MASK 0xFFFFFFF0L
-//DIDT_DBR_EDC_STALL_DELAY_1
-#define DIDT_DBR_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DBR0__SHIFT 0x0
-#define DIDT_DBR_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x1
-#define DIDT_DBR_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DBR0_MASK 0x00000001L
-#define DIDT_DBR_EDC_STALL_DELAY_1__UNUSED_MASK 0xFFFFFFFEL
-//DIDT_DBR_EDC_OVERFLOW
-#define DIDT_DBR_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0
-#define DIDT_DBR_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1
-#define DIDT_DBR_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L
-#define DIDT_DBR_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL
-//DIDT_DBR_EDC_ROLLING_POWER_DELTA
-#define DIDT_DBR_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0
-#define DIDT_DBR_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL
-//DIDT_SQ_STALL_EVENT_COUNTER
-#define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0
-#define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL
-//DIDT_DB_STALL_EVENT_COUNTER
-#define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0
-#define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL
-//DIDT_TD_STALL_EVENT_COUNTER
-#define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0
-#define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL
-//DIDT_TCP_STALL_EVENT_COUNTER
-#define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0
-#define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL
-//DIDT_DBR_STALL_EVENT_COUNTER
-#define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0
-#define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL
-
-
-
-
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h
deleted file mode 100644
index 2d672b3d2..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h
+++ /dev/null
@@ -1,2791 +0,0 @@
-/*
- * GFX_8_1 Register documentation
- *
- * Copyright (C) 2014 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef GFX_8_1_D_H
-#define GFX_8_1_D_H
-
-#define mmCB_BLEND_RED 0xa105
-#define mmCB_BLEND_GREEN 0xa106
-#define mmCB_BLEND_BLUE 0xa107
-#define mmCB_BLEND_ALPHA 0xa108
-#define mmCB_DCC_CONTROL 0xa109
-#define mmCB_COLOR_CONTROL 0xa202
-#define mmCB_BLEND0_CONTROL 0xa1e0
-#define mmCB_BLEND1_CONTROL 0xa1e1
-#define mmCB_BLEND2_CONTROL 0xa1e2
-#define mmCB_BLEND3_CONTROL 0xa1e3
-#define mmCB_BLEND4_CONTROL 0xa1e4
-#define mmCB_BLEND5_CONTROL 0xa1e5
-#define mmCB_BLEND6_CONTROL 0xa1e6
-#define mmCB_BLEND7_CONTROL 0xa1e7
-#define mmCB_COLOR0_BASE 0xa318
-#define mmCB_COLOR1_BASE 0xa327
-#define mmCB_COLOR2_BASE 0xa336
-#define mmCB_COLOR3_BASE 0xa345
-#define mmCB_COLOR4_BASE 0xa354
-#define mmCB_COLOR5_BASE 0xa363
-#define mmCB_COLOR6_BASE 0xa372
-#define mmCB_COLOR7_BASE 0xa381
-#define mmCB_COLOR0_PITCH 0xa319
-#define mmCB_COLOR1_PITCH 0xa328
-#define mmCB_COLOR2_PITCH 0xa337
-#define mmCB_COLOR3_PITCH 0xa346
-#define mmCB_COLOR4_PITCH 0xa355
-#define mmCB_COLOR5_PITCH 0xa364
-#define mmCB_COLOR6_PITCH 0xa373
-#define mmCB_COLOR7_PITCH 0xa382
-#define mmCB_COLOR0_SLICE 0xa31a
-#define mmCB_COLOR1_SLICE 0xa329
-#define mmCB_COLOR2_SLICE 0xa338
-#define mmCB_COLOR3_SLICE 0xa347
-#define mmCB_COLOR4_SLICE 0xa356
-#define mmCB_COLOR5_SLICE 0xa365
-#define mmCB_COLOR6_SLICE 0xa374
-#define mmCB_COLOR7_SLICE 0xa383
-#define mmCB_COLOR0_VIEW 0xa31b
-#define mmCB_COLOR1_VIEW 0xa32a
-#define mmCB_COLOR2_VIEW 0xa339
-#define mmCB_COLOR3_VIEW 0xa348
-#define mmCB_COLOR4_VIEW 0xa357
-#define mmCB_COLOR5_VIEW 0xa366
-#define mmCB_COLOR6_VIEW 0xa375
-#define mmCB_COLOR7_VIEW 0xa384
-#define mmCB_COLOR0_INFO 0xa31c
-#define mmCB_COLOR1_INFO 0xa32b
-#define mmCB_COLOR2_INFO 0xa33a
-#define mmCB_COLOR3_INFO 0xa349
-#define mmCB_COLOR4_INFO 0xa358
-#define mmCB_COLOR5_INFO 0xa367
-#define mmCB_COLOR6_INFO 0xa376
-#define mmCB_COLOR7_INFO 0xa385
-#define mmCB_COLOR0_ATTRIB 0xa31d
-#define mmCB_COLOR1_ATTRIB 0xa32c
-#define mmCB_COLOR2_ATTRIB 0xa33b
-#define mmCB_COLOR3_ATTRIB 0xa34a
-#define mmCB_COLOR4_ATTRIB 0xa359
-#define mmCB_COLOR5_ATTRIB 0xa368
-#define mmCB_COLOR6_ATTRIB 0xa377
-#define mmCB_COLOR7_ATTRIB 0xa386
-#define mmCB_COLOR0_DCC_CONTROL 0xa31e
-#define mmCB_COLOR1_DCC_CONTROL 0xa32d
-#define mmCB_COLOR2_DCC_CONTROL 0xa33c
-#define mmCB_COLOR3_DCC_CONTROL 0xa34b
-#define mmCB_COLOR4_DCC_CONTROL 0xa35a
-#define mmCB_COLOR5_DCC_CONTROL 0xa369
-#define mmCB_COLOR6_DCC_CONTROL 0xa378
-#define mmCB_COLOR7_DCC_CONTROL 0xa387
-#define mmCB_COLOR0_CMASK 0xa31f
-#define mmCB_COLOR1_CMASK 0xa32e
-#define mmCB_COLOR2_CMASK 0xa33d
-#define mmCB_COLOR3_CMASK 0xa34c
-#define mmCB_COLOR4_CMASK 0xa35b
-#define mmCB_COLOR5_CMASK 0xa36a
-#define mmCB_COLOR6_CMASK 0xa379
-#define mmCB_COLOR7_CMASK 0xa388
-#define mmCB_COLOR0_CMASK_SLICE 0xa320
-#define mmCB_COLOR1_CMASK_SLICE 0xa32f
-#define mmCB_COLOR2_CMASK_SLICE 0xa33e
-#define mmCB_COLOR3_CMASK_SLICE 0xa34d
-#define mmCB_COLOR4_CMASK_SLICE 0xa35c
-#define mmCB_COLOR5_CMASK_SLICE 0xa36b
-#define mmCB_COLOR6_CMASK_SLICE 0xa37a
-#define mmCB_COLOR7_CMASK_SLICE 0xa389
-#define mmCB_COLOR0_FMASK 0xa321
-#define mmCB_COLOR1_FMASK 0xa330
-#define mmCB_COLOR2_FMASK 0xa33f
-#define mmCB_COLOR3_FMASK 0xa34e
-#define mmCB_COLOR4_FMASK 0xa35d
-#define mmCB_COLOR5_FMASK 0xa36c
-#define mmCB_COLOR6_FMASK 0xa37b
-#define mmCB_COLOR7_FMASK 0xa38a
-#define mmCB_COLOR0_FMASK_SLICE 0xa322
-#define mmCB_COLOR1_FMASK_SLICE 0xa331
-#define mmCB_COLOR2_FMASK_SLICE 0xa340
-#define mmCB_COLOR3_FMASK_SLICE 0xa34f
-#define mmCB_COLOR4_FMASK_SLICE 0xa35e
-#define mmCB_COLOR5_FMASK_SLICE 0xa36d
-#define mmCB_COLOR6_FMASK_SLICE 0xa37c
-#define mmCB_COLOR7_FMASK_SLICE 0xa38b
-#define mmCB_COLOR0_CLEAR_WORD0 0xa323
-#define mmCB_COLOR1_CLEAR_WORD0 0xa332
-#define mmCB_COLOR2_CLEAR_WORD0 0xa341
-#define mmCB_COLOR3_CLEAR_WORD0 0xa350
-#define mmCB_COLOR4_CLEAR_WORD0 0xa35f
-#define mmCB_COLOR5_CLEAR_WORD0 0xa36e
-#define mmCB_COLOR6_CLEAR_WORD0 0xa37d
-#define mmCB_COLOR7_CLEAR_WORD0 0xa38c
-#define mmCB_COLOR0_CLEAR_WORD1 0xa324
-#define mmCB_COLOR1_CLEAR_WORD1 0xa333
-#define mmCB_COLOR2_CLEAR_WORD1 0xa342
-#define mmCB_COLOR3_CLEAR_WORD1 0xa351
-#define mmCB_COLOR4_CLEAR_WORD1 0xa360
-#define mmCB_COLOR5_CLEAR_WORD1 0xa36f
-#define mmCB_COLOR6_CLEAR_WORD1 0xa37e
-#define mmCB_COLOR7_CLEAR_WORD1 0xa38d
-#define mmCB_COLOR0_DCC_BASE 0xa325
-#define mmCB_COLOR1_DCC_BASE 0xa334
-#define mmCB_COLOR2_DCC_BASE 0xa343
-#define mmCB_COLOR3_DCC_BASE 0xa352
-#define mmCB_COLOR4_DCC_BASE 0xa361
-#define mmCB_COLOR5_DCC_BASE 0xa370
-#define mmCB_COLOR6_DCC_BASE 0xa37f
-#define mmCB_COLOR7_DCC_BASE 0xa38e
-#define mmCB_TARGET_MASK 0xa08e
-#define mmCB_SHADER_MASK 0xa08f
-#define mmCB_HW_CONTROL 0x2684
-#define mmCB_HW_CONTROL_1 0x2685
-#define mmCB_HW_CONTROL_2 0x2686
-#define mmCB_HW_CONTROL_3 0x2683
-#define mmCB_DCC_CONFIG 0x2687
-#define mmCB_PERFCOUNTER_FILTER 0xdc00
-#define mmCB_PERFCOUNTER0_SELECT 0xdc01
-#define mmCB_PERFCOUNTER0_SELECT1 0xdc02
-#define mmCB_PERFCOUNTER1_SELECT 0xdc03
-#define mmCB_PERFCOUNTER2_SELECT 0xdc04
-#define mmCB_PERFCOUNTER3_SELECT 0xdc05
-#define mmCB_PERFCOUNTER0_LO 0xd406
-#define mmCB_PERFCOUNTER1_LO 0xd408
-#define mmCB_PERFCOUNTER2_LO 0xd40a
-#define mmCB_PERFCOUNTER3_LO 0xd40c
-#define mmCB_PERFCOUNTER0_HI 0xd407
-#define mmCB_PERFCOUNTER1_HI 0xd409
-#define mmCB_PERFCOUNTER2_HI 0xd40b
-#define mmCB_PERFCOUNTER3_HI 0xd40d
-#define mmCB_CGTT_SCLK_CTRL 0xf0a8
-#define mmCB_DEBUG_BUS_1 0x2699
-#define mmCB_DEBUG_BUS_2 0x269a
-#define mmCB_DEBUG_BUS_3 0x269b
-#define mmCB_DEBUG_BUS_4 0x269c
-#define mmCB_DEBUG_BUS_5 0x269d
-#define mmCB_DEBUG_BUS_6 0x269e
-#define mmCB_DEBUG_BUS_7 0x269f
-#define mmCB_DEBUG_BUS_8 0x26a0
-#define mmCB_DEBUG_BUS_9 0x26a1
-#define mmCB_DEBUG_BUS_10 0x26a2
-#define mmCB_DEBUG_BUS_11 0x26a3
-#define mmCB_DEBUG_BUS_12 0x26a4
-#define mmCB_DEBUG_BUS_13 0x26a5
-#define mmCB_DEBUG_BUS_14 0x26a6
-#define mmCB_DEBUG_BUS_15 0x26a7
-#define mmCB_DEBUG_BUS_16 0x26a8
-#define mmCB_DEBUG_BUS_17 0x26a9
-#define mmCB_DEBUG_BUS_18 0x26aa
-#define mmCB_DEBUG_BUS_19 0x26ab
-#define mmCB_DEBUG_BUS_20 0x26ac
-#define mmCB_DEBUG_BUS_21 0x26ad
-#define mmCB_DEBUG_BUS_22 0x26ae
-#define mmCP_DFY_CNTL 0x3020
-#define mmCP_DFY_STAT 0x3021
-#define mmCP_DFY_ADDR_HI 0x3022
-#define mmCP_DFY_ADDR_LO 0x3023
-#define mmCP_DFY_DATA_0 0x3024
-#define mmCP_DFY_DATA_1 0x3025
-#define mmCP_DFY_DATA_2 0x3026
-#define mmCP_DFY_DATA_3 0x3027
-#define mmCP_DFY_DATA_4 0x3028
-#define mmCP_DFY_DATA_5 0x3029
-#define mmCP_DFY_DATA_6 0x302a
-#define mmCP_DFY_DATA_7 0x302b
-#define mmCP_DFY_DATA_8 0x302c
-#define mmCP_DFY_DATA_9 0x302d
-#define mmCP_DFY_DATA_10 0x302e
-#define mmCP_DFY_DATA_11 0x302f
-#define mmCP_DFY_DATA_12 0x3030
-#define mmCP_DFY_DATA_13 0x3031
-#define mmCP_DFY_DATA_14 0x3032
-#define mmCP_DFY_DATA_15 0x3033
-#define mmCP_DFY_CMD 0x3034
-#define mmCP_CPC_MGCG_SYNC_CNTL 0x3036
-#define mmCP_ATCL1_CNTL 0x303c
-#define mmCP_RB0_BASE 0x3040
-#define mmCP_RB0_BASE_HI 0x30b1
-#define mmCP_RB_BASE 0x3040
-#define mmCP_RB1_BASE 0x3060
-#define mmCP_RB1_BASE_HI 0x30b2
-#define mmCP_RB2_BASE 0x3065
-#define mmCP_RB0_CNTL 0x3041
-#define mmCP_RB_CNTL 0x3041
-#define mmCP_RB1_CNTL 0x3061
-#define mmCP_RB2_CNTL 0x3066
-#define mmCP_RB_RPTR_WR 0x3042
-#define mmCP_RB0_RPTR_ADDR 0x3043
-#define mmCP_RB_RPTR_ADDR 0x3043
-#define mmCP_RB1_RPTR_ADDR 0x3062
-#define mmCP_RB2_RPTR_ADDR 0x3067
-#define mmCP_RB0_RPTR_ADDR_HI 0x3044
-#define mmCP_RB_RPTR_ADDR_HI 0x3044
-#define mmCP_RB1_RPTR_ADDR_HI 0x3063
-#define mmCP_RB2_RPTR_ADDR_HI 0x3068
-#define mmCP_RB0_WPTR 0x3045
-#define mmCP_RB_WPTR 0x3045
-#define mmCP_RB1_WPTR 0x3064
-#define mmCP_RB2_WPTR 0x3069
-#define mmCP_RB_WPTR_POLL_ADDR_LO 0x3046
-#define mmCP_RB_WPTR_POLL_ADDR_HI 0x3047
-#define mmGC_PRIV_MODE 0x3048
-#define mmCP_INT_CNTL 0x3049
-#define mmCP_INT_CNTL_RING0 0x306a
-#define mmCP_INT_CNTL_RING1 0x306b
-#define mmCP_INT_CNTL_RING2 0x306c
-#define mmCP_INT_STATUS 0x304a
-#define mmCP_INT_STATUS_RING0 0x306d
-#define mmCP_INT_STATUS_RING1 0x306e
-#define mmCP_INT_STATUS_RING2 0x306f
-#define mmCP_DEVICE_ID 0x304b
-#define mmCP_RING_PRIORITY_CNTS 0x304c
-#define mmCP_ME0_PIPE_PRIORITY_CNTS 0x304c
-#define mmCP_RING0_PRIORITY 0x304d
-#define mmCP_ME0_PIPE0_PRIORITY 0x304d
-#define mmCP_RING1_PRIORITY 0x304e
-#define mmCP_ME0_PIPE1_PRIORITY 0x304e
-#define mmCP_RING2_PRIORITY 0x304f
-#define mmCP_ME0_PIPE2_PRIORITY 0x304f
-#define mmCP_ENDIAN_SWAP 0x3050
-#define mmCP_RB_VMID 0x3051
-#define mmCP_ME0_PIPE0_VMID 0x3052
-#define mmCP_ME0_PIPE1_VMID 0x3053
-#define mmCP_RB_DOORBELL_CONTROL 0x3059
-#define mmCP_RB_DOORBELL_RANGE_LOWER 0x305a
-#define mmCP_RB_DOORBELL_RANGE_UPPER 0x305b
-#define mmCP_MEC_DOORBELL_RANGE_LOWER 0x305c
-#define mmCP_MEC_DOORBELL_RANGE_UPPER 0x305d
-#define mmCP_PFP_UCODE_ADDR 0xf814
-#define mmCP_PFP_UCODE_DATA 0xf815
-#define mmCP_ME_RAM_RADDR 0xf816
-#define mmCP_ME_RAM_WADDR 0xf816
-#define mmCP_ME_RAM_DATA 0xf817
-#define mmCGTT_CPC_CLK_CTRL 0xf0b2
-#define mmCGTT_CPF_CLK_CTRL 0xf0b1
-#define mmCGTT_CP_CLK_CTRL 0xf0b0
-#define mmCP_CE_UCODE_ADDR 0xf818
-#define mmCP_CE_UCODE_DATA 0xf819
-#define mmCP_MEC_ME1_UCODE_ADDR 0xf81a
-#define mmCP_MEC_ME1_UCODE_DATA 0xf81b
-#define mmCP_MEC_ME2_UCODE_ADDR 0xf81c
-#define mmCP_MEC_ME2_UCODE_DATA 0xf81d
-#define mmCP_MEC1_F32_INT_DIS 0x30bd
-#define mmCP_MEC2_F32_INT_DIS 0x30be
-#define mmCP_PWR_CNTL 0x3078
-#define mmCP_MEM_SLP_CNTL 0x3079
-#define mmCP_ECC_FIRSTOCCURRENCE 0x307a
-#define mmCP_ECC_FIRSTOCCURRENCE_RING0 0x307b
-#define mmCP_ECC_FIRSTOCCURRENCE_RING1 0x307c
-#define mmCP_ECC_FIRSTOCCURRENCE_RING2 0x307d
-#define mmCP_CPF_DEBUG 0x3080
-#define mmCP_PQ_WPTR_POLL_CNTL 0x3083
-#define mmCP_PQ_WPTR_POLL_CNTL1 0x3084
-#define mmCPC_INT_CNTL 0x30b4
-#define mmCP_ME1_PIPE0_INT_CNTL 0x3085
-#define mmCP_ME1_PIPE1_INT_CNTL 0x3086
-#define mmCP_ME1_PIPE2_INT_CNTL 0x3087
-#define mmCP_ME1_PIPE3_INT_CNTL 0x3088
-#define mmCP_ME2_PIPE0_INT_CNTL 0x3089
-#define mmCP_ME2_PIPE1_INT_CNTL 0x308a
-#define mmCP_ME2_PIPE2_INT_CNTL 0x308b
-#define mmCP_ME2_PIPE3_INT_CNTL 0x308c
-#define mmCPC_INT_STATUS 0x30b5
-#define mmCP_ME1_PIPE0_INT_STATUS 0x308d
-#define mmCP_ME1_PIPE1_INT_STATUS 0x308e
-#define mmCP_ME1_PIPE2_INT_STATUS 0x308f
-#define mmCP_ME1_PIPE3_INT_STATUS 0x3090
-#define mmCP_ME2_PIPE0_INT_STATUS 0x3091
-#define mmCP_ME2_PIPE1_INT_STATUS 0x3092
-#define mmCP_ME2_PIPE2_INT_STATUS 0x3093
-#define mmCP_ME2_PIPE3_INT_STATUS 0x3094
-#define mmCP_ME1_INT_STAT_DEBUG 0x3095
-#define mmCP_ME2_INT_STAT_DEBUG 0x3096
-#define mmCP_ME1_PIPE_PRIORITY_CNTS 0x3099
-#define mmCP_ME1_PIPE0_PRIORITY 0x309a
-#define mmCP_ME1_PIPE1_PRIORITY 0x309b
-#define mmCP_ME1_PIPE2_PRIORITY 0x309c
-#define mmCP_ME1_PIPE3_PRIORITY 0x309d
-#define mmCP_ME2_PIPE_PRIORITY_CNTS 0x309e
-#define mmCP_ME2_PIPE0_PRIORITY 0x309f
-#define mmCP_ME2_PIPE1_PRIORITY 0x30a0
-#define mmCP_ME2_PIPE2_PRIORITY 0x30a1
-#define mmCP_ME2_PIPE3_PRIORITY 0x30a2
-#define mmCP_CE_PRGRM_CNTR_START 0x30a3
-#define mmCP_PFP_PRGRM_CNTR_START 0x30a4
-#define mmCP_ME_PRGRM_CNTR_START 0x30a5
-#define mmCP_MEC1_PRGRM_CNTR_START 0x30a6
-#define mmCP_MEC2_PRGRM_CNTR_START 0x30a7
-#define mmCP_CE_INTR_ROUTINE_START 0x30a8
-#define mmCP_PFP_INTR_ROUTINE_START 0x30a9
-#define mmCP_ME_INTR_ROUTINE_START 0x30aa
-#define mmCP_MEC1_INTR_ROUTINE_START 0x30ab
-#define mmCP_MEC2_INTR_ROUTINE_START 0x30ac
-#define mmCP_CONTEXT_CNTL 0x30ad
-#define mmCP_MAX_CONTEXT 0x30ae
-#define mmCP_IQ_WAIT_TIME1 0x30af
-#define mmCP_IQ_WAIT_TIME2 0x30b0
-#define mmCP_VMID_RESET 0x30b3
-#define mmCP_VMID_PREEMPT 0x30b6
-#define mmCP_VMID_STATUS 0x30bf
-#define mmCPC_INT_CNTX_ID 0x30b7
-#define mmCP_PQ_STATUS 0x30b8
-#define mmCP_CPC_IC_BASE_LO 0x30b9
-#define mmCP_CPC_IC_BASE_HI 0x30ba
-#define mmCP_CPC_IC_BASE_CNTL 0x30bb
-#define mmCP_CPC_IC_OP_CNTL 0x30bc
-#define mmCP_CPC_STATUS 0x2084
-#define mmCP_CPC_BUSY_STAT 0x2085
-#define mmCP_CPC_STALLED_STAT1 0x2086
-#define mmCP_CPF_STATUS 0x2087
-#define mmCP_CPF_BUSY_STAT 0x2088
-#define mmCP_CPF_STALLED_STAT1 0x2089
-#define mmCP_CPC_GRBM_FREE_COUNT 0x208b
-#define mmCP_MEC_CNTL 0x208d
-#define mmCP_MEC_ME1_HEADER_DUMP 0x208e
-#define mmCP_MEC_ME2_HEADER_DUMP 0x208f
-#define mmCP_CPC_SCRATCH_INDEX 0x2090
-#define mmCP_CPC_SCRATCH_DATA 0x2091
-#define mmCPG_PERFCOUNTER1_SELECT 0xd800
-#define mmCPG_PERFCOUNTER1_LO 0xd000
-#define mmCPG_PERFCOUNTER1_HI 0xd001
-#define mmCPG_PERFCOUNTER0_SELECT1 0xd801
-#define mmCPG_PERFCOUNTER0_SELECT 0xd802
-#define mmCPG_PERFCOUNTER0_LO 0xd002
-#define mmCPG_PERFCOUNTER0_HI 0xd003
-#define mmCPC_PERFCOUNTER1_SELECT 0xd803
-#define mmCPC_PERFCOUNTER1_LO 0xd004
-#define mmCPC_PERFCOUNTER1_HI 0xd005
-#define mmCPC_PERFCOUNTER0_SELECT1 0xd804
-#define mmCPC_PERFCOUNTER0_SELECT 0xd809
-#define mmCPC_PERFCOUNTER0_LO 0xd006
-#define mmCPC_PERFCOUNTER0_HI 0xd007
-#define mmCPF_PERFCOUNTER1_SELECT 0xd805
-#define mmCPF_PERFCOUNTER1_LO 0xd008
-#define mmCPF_PERFCOUNTER1_HI 0xd009
-#define mmCPF_PERFCOUNTER0_SELECT1 0xd806
-#define mmCPF_PERFCOUNTER0_SELECT 0xd807
-#define mmCPF_PERFCOUNTER0_LO 0xd00a
-#define mmCPF_PERFCOUNTER0_HI 0xd00b
-#define mmCP_CPC_HALT_HYST_COUNT 0x20a7
-#define mmCP_DRAW_OBJECT 0xd810
-#define mmCP_DRAW_OBJECT_COUNTER 0xd811
-#define mmCP_DRAW_WINDOW_MASK_HI 0xd812
-#define mmCP_DRAW_WINDOW_HI 0xd813
-#define mmCP_DRAW_WINDOW_LO 0xd814
-#define mmCP_DRAW_WINDOW_CNTL 0xd815
-#define mmCP_PRT_LOD_STATS_CNTL0 0x20ad
-#define mmCP_PRT_LOD_STATS_CNTL1 0x20ae
-#define mmCP_PRT_LOD_STATS_CNTL2 0x20af
-#define mmCP_CE_COMPARE_COUNT 0x20c0
-#define mmCP_CE_DE_COUNT 0x20c1
-#define mmCP_DE_CE_COUNT 0x20c2
-#define mmCP_DE_LAST_INVAL_COUNT 0x20c3
-#define mmCP_DE_DE_COUNT 0x20c4
-#define mmCP_EOP_DONE_EVENT_CNTL 0xc0d5
-#define mmCP_EOP_DONE_DATA_CNTL 0xc0d6
-#define mmCP_EOP_DONE_CNTX_ID 0xc0d7
-#define mmCP_EOP_DONE_ADDR_LO 0xc000
-#define mmCP_EOP_DONE_ADDR_HI 0xc001
-#define mmCP_EOP_DONE_DATA_LO 0xc002
-#define mmCP_EOP_DONE_DATA_HI 0xc003
-#define mmCP_EOP_LAST_FENCE_LO 0xc004
-#define mmCP_EOP_LAST_FENCE_HI 0xc005
-#define mmCP_STREAM_OUT_ADDR_LO 0xc006
-#define mmCP_STREAM_OUT_ADDR_HI 0xc007
-#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO 0xc008
-#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI 0xc009
-#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO 0xc00a
-#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI 0xc00b
-#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO 0xc00c
-#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI 0xc00d
-#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO 0xc00e
-#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI 0xc00f
-#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO 0xc010
-#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI 0xc011
-#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO 0xc012
-#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI 0xc013
-#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO 0xc014
-#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI 0xc015
-#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO 0xc016
-#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI 0xc017
-#define mmCP_PIPE_STATS_ADDR_LO 0xc018
-#define mmCP_PIPE_STATS_ADDR_HI 0xc019
-#define mmCP_VGT_IAVERT_COUNT_LO 0xc01a
-#define mmCP_VGT_IAVERT_COUNT_HI 0xc01b
-#define mmCP_VGT_IAPRIM_COUNT_LO 0xc01c
-#define mmCP_VGT_IAPRIM_COUNT_HI 0xc01d
-#define mmCP_VGT_GSPRIM_COUNT_LO 0xc01e
-#define mmCP_VGT_GSPRIM_COUNT_HI 0xc01f
-#define mmCP_VGT_VSINVOC_COUNT_LO 0xc020
-#define mmCP_VGT_VSINVOC_COUNT_HI 0xc021
-#define mmCP_VGT_GSINVOC_COUNT_LO 0xc022
-#define mmCP_VGT_GSINVOC_COUNT_HI 0xc023
-#define mmCP_VGT_HSINVOC_COUNT_LO 0xc024
-#define mmCP_VGT_HSINVOC_COUNT_HI 0xc025
-#define mmCP_VGT_DSINVOC_COUNT_LO 0xc026
-#define mmCP_VGT_DSINVOC_COUNT_HI 0xc027
-#define mmCP_PA_CINVOC_COUNT_LO 0xc028
-#define mmCP_PA_CINVOC_COUNT_HI 0xc029
-#define mmCP_PA_CPRIM_COUNT_LO 0xc02a
-#define mmCP_PA_CPRIM_COUNT_HI 0xc02b
-#define mmCP_SC_PSINVOC_COUNT0_LO 0xc02c
-#define mmCP_SC_PSINVOC_COUNT0_HI 0xc02d
-#define mmCP_SC_PSINVOC_COUNT1_LO 0xc02e
-#define mmCP_SC_PSINVOC_COUNT1_HI 0xc02f
-#define mmCP_VGT_CSINVOC_COUNT_LO 0xc030
-#define mmCP_VGT_CSINVOC_COUNT_HI 0xc031
-#define mmCP_PIPE_STATS_CONTROL 0xc03d
-#define mmCP_STREAM_OUT_CONTROL 0xc03e
-#define mmCP_STRMOUT_CNTL 0xc03f
-#define mmSCRATCH_REG0 0xc040
-#define mmSCRATCH_REG1 0xc041
-#define mmSCRATCH_REG2 0xc042
-#define mmSCRATCH_REG3 0xc043
-#define mmSCRATCH_REG4 0xc044
-#define mmSCRATCH_REG5 0xc045
-#define mmSCRATCH_REG6 0xc046
-#define mmSCRATCH_REG7 0xc047
-#define mmSCRATCH_UMSK 0xc050
-#define mmSCRATCH_ADDR 0xc051
-#define mmCP_PFP_ATOMIC_PREOP_LO 0xc052
-#define mmCP_PFP_ATOMIC_PREOP_HI 0xc053
-#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO 0xc054
-#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI 0xc055
-#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO 0xc056
-#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI 0xc057
-#define mmCP_APPEND_ADDR_LO 0xc058
-#define mmCP_APPEND_ADDR_HI 0xc059
-#define mmCP_APPEND_DATA 0xc05a
-#define mmCP_APPEND_LAST_CS_FENCE 0xc05b
-#define mmCP_APPEND_LAST_PS_FENCE 0xc05c
-#define mmCP_ATOMIC_PREOP_LO 0xc05d
-#define mmCP_ME_ATOMIC_PREOP_LO 0xc05d
-#define mmCP_ATOMIC_PREOP_HI 0xc05e
-#define mmCP_ME_ATOMIC_PREOP_HI 0xc05e
-#define mmCP_GDS_ATOMIC0_PREOP_LO 0xc05f
-#define mmCP_ME_GDS_ATOMIC0_PREOP_LO 0xc05f
-#define mmCP_GDS_ATOMIC0_PREOP_HI 0xc060
-#define mmCP_ME_GDS_ATOMIC0_PREOP_HI 0xc060
-#define mmCP_GDS_ATOMIC1_PREOP_LO 0xc061
-#define mmCP_ME_GDS_ATOMIC1_PREOP_LO 0xc061
-#define mmCP_GDS_ATOMIC1_PREOP_HI 0xc062
-#define mmCP_ME_GDS_ATOMIC1_PREOP_HI 0xc062
-#define mmCP_ME_MC_WADDR_LO 0xc069
-#define mmCP_ME_MC_WADDR_HI 0xc06a
-#define mmCP_ME_MC_WDATA_LO 0xc06b
-#define mmCP_ME_MC_WDATA_HI 0xc06c
-#define mmCP_ME_MC_RADDR_LO 0xc06d
-#define mmCP_ME_MC_RADDR_HI 0xc06e
-#define mmCP_SEM_WAIT_TIMER 0xc06f
-#define mmCP_SIG_SEM_ADDR_LO 0xc070
-#define mmCP_SIG_SEM_ADDR_HI 0xc071
-#define mmCP_WAIT_SEM_ADDR_LO 0xc075
-#define mmCP_WAIT_SEM_ADDR_HI 0xc076
-#define mmCP_WAIT_REG_MEM_TIMEOUT 0xc074
-#define mmCP_COHER_START_DELAY 0xc07b
-#define mmCP_COHER_CNTL 0xc07c
-#define mmCP_COHER_SIZE 0xc07d
-#define mmCP_COHER_SIZE_HI 0xc08c
-#define mmCP_COHER_BASE 0xc07e
-#define mmCP_COHER_BASE_HI 0xc079
-#define mmCP_COHER_STATUS 0xc07f
-#define mmCOHER_DEST_BASE_0 0xa092
-#define mmCOHER_DEST_BASE_1 0xa093
-#define mmCOHER_DEST_BASE_2 0xa07e
-#define mmCOHER_DEST_BASE_3 0xa07f
-#define mmCOHER_DEST_BASE_HI_0 0xa07a
-#define mmCOHER_DEST_BASE_HI_1 0xa07b
-#define mmCOHER_DEST_BASE_HI_2 0xa07c
-#define mmCOHER_DEST_BASE_HI_3 0xa07d
-#define mmCP_DMA_ME_SRC_ADDR 0xc080
-#define mmCP_DMA_ME_SRC_ADDR_HI 0xc081
-#define mmCP_DMA_ME_DST_ADDR 0xc082
-#define mmCP_DMA_ME_DST_ADDR_HI 0xc083
-#define mmCP_DMA_ME_CONTROL 0xc078
-#define mmCP_DMA_ME_COMMAND 0xc084
-#define mmCP_DMA_PFP_SRC_ADDR 0xc085
-#define mmCP_DMA_PFP_SRC_ADDR_HI 0xc086
-#define mmCP_DMA_PFP_DST_ADDR 0xc087
-#define mmCP_DMA_PFP_DST_ADDR_HI 0xc088
-#define mmCP_DMA_PFP_CONTROL 0xc077
-#define mmCP_DMA_PFP_COMMAND 0xc089
-#define mmCP_DMA_CNTL 0xc08a
-#define mmCP_DMA_READ_TAGS 0xc08b
-#define mmCP_PFP_IB_CONTROL 0xc08d
-#define mmCP_PFP_LOAD_CONTROL 0xc08e
-#define mmCP_SCRATCH_INDEX 0xc08f
-#define mmCP_SCRATCH_DATA 0xc090
-#define mmCP_RB_OFFSET 0xc091
-#define mmCP_IB1_OFFSET 0xc092
-#define mmCP_IB2_OFFSET 0xc093
-#define mmCP_IB1_PREAMBLE_BEGIN 0xc094
-#define mmCP_IB1_PREAMBLE_END 0xc095
-#define mmCP_IB2_PREAMBLE_BEGIN 0xc096
-#define mmCP_IB2_PREAMBLE_END 0xc097
-#define mmCP_CE_IB1_OFFSET 0xc098
-#define mmCP_CE_IB2_OFFSET 0xc099
-#define mmCP_CE_COUNTER 0xc09a
-#define mmCP_CE_RB_OFFSET 0xc09b
-#define mmCP_PFP_COMPLETION_STATUS 0xc0ec
-#define mmCP_CE_COMPLETION_STATUS 0xc0ed
-#define mmCP_PRED_NOT_VISIBLE 0xc0ee
-#define mmCP_PFP_METADATA_BASE_ADDR 0xc0f0
-#define mmCP_PFP_METADATA_BASE_ADDR_HI 0xc0f1
-#define mmCP_CE_METADATA_BASE_ADDR 0xc0f2
-#define mmCP_CE_METADATA_BASE_ADDR_HI 0xc0f3
-#define mmCP_DRAW_INDX_INDR_ADDR 0xc0f4
-#define mmCP_DRAW_INDX_INDR_ADDR_HI 0xc0f5
-#define mmCP_DISPATCH_INDR_ADDR 0xc0f6
-#define mmCP_DISPATCH_INDR_ADDR_HI 0xc0f7
-#define mmCP_INDEX_BASE_ADDR 0xc0f8
-#define mmCP_INDEX_BASE_ADDR_HI 0xc0f9
-#define mmCP_INDEX_TYPE 0xc0fa
-#define mmCP_GDS_BKUP_ADDR 0xc0fb
-#define mmCP_GDS_BKUP_ADDR_HI 0xc0fc
-#define mmCP_SAMPLE_STATUS 0xc0fd
-#define mmCP_STALLED_STAT1 0x219d
-#define mmCP_STALLED_STAT2 0x219e
-#define mmCP_STALLED_STAT3 0x219c
-#define mmCP_BUSY_STAT 0x219f
-#define mmCP_STAT 0x21a0
-#define mmCP_ME_HEADER_DUMP 0x21a1
-#define mmCP_PFP_HEADER_DUMP 0x21a2
-#define mmCP_GRBM_FREE_COUNT 0x21a3
-#define mmCP_CE_HEADER_DUMP 0x21a4
-#define mmCP_CSF_STAT 0x21b4
-#define mmCP_CSF_CNTL 0x21b5
-#define mmCP_ME_CNTL 0x21b6
-#define mmCP_CNTX_STAT 0x21b8
-#define mmCP_ME_PREEMPTION 0x21b9
-#define mmCP_RB0_RPTR 0x21c0
-#define mmCP_RB_RPTR 0x21c0
-#define mmCP_RB1_RPTR 0x21bf
-#define mmCP_RB2_RPTR 0x21be
-#define mmCP_RB_WPTR_DELAY 0x21c1
-#define mmCP_RB_WPTR_POLL_CNTL 0x21c2
-#define mmCP_CE_INIT_BASE_LO 0xc0c3
-#define mmCP_CE_INIT_BASE_HI 0xc0c4
-#define mmCP_CE_INIT_BUFSZ 0xc0c5
-#define mmCP_CE_IB1_BASE_LO 0xc0c6
-#define mmCP_CE_IB1_BASE_HI 0xc0c7
-#define mmCP_CE_IB1_BUFSZ 0xc0c8
-#define mmCP_CE_IB2_BASE_LO 0xc0c9
-#define mmCP_CE_IB2_BASE_HI 0xc0ca
-#define mmCP_CE_IB2_BUFSZ 0xc0cb
-#define mmCP_IB1_BASE_LO 0xc0cc
-#define mmCP_IB1_BASE_HI 0xc0cd
-#define mmCP_IB1_BUFSZ 0xc0ce
-#define mmCP_IB2_BASE_LO 0xc0cf
-#define mmCP_IB2_BASE_HI 0xc0d0
-#define mmCP_IB2_BUFSZ 0xc0d1
-#define mmCP_ST_BASE_LO 0xc0d2
-#define mmCP_ST_BASE_HI 0xc0d3
-#define mmCP_ST_BUFSZ 0xc0d4
-#define mmCP_ROQ_THRESHOLDS 0x21bc
-#define mmCP_MEQ_STQ_THRESHOLD 0x21bd
-#define mmCP_ROQ1_THRESHOLDS 0x21d5
-#define mmCP_ROQ2_THRESHOLDS 0x21d6
-#define mmCP_STQ_THRESHOLDS 0x21d7
-#define mmCP_QUEUE_THRESHOLDS 0x21d8
-#define mmCP_MEQ_THRESHOLDS 0x21d9
-#define mmCP_ROQ_AVAIL 0x21da
-#define mmCP_STQ_AVAIL 0x21db
-#define mmCP_ROQ2_AVAIL 0x21dc
-#define mmCP_MEQ_AVAIL 0x21dd
-#define mmCP_CMD_INDEX 0x21de
-#define mmCP_CMD_DATA 0x21df
-#define mmCP_ROQ_RB_STAT 0x21e0
-#define mmCP_ROQ_IB1_STAT 0x21e1
-#define mmCP_ROQ_IB2_STAT 0x21e2
-#define mmCP_STQ_STAT 0x21e3
-#define mmCP_STQ_WR_STAT 0x21e4
-#define mmCP_MEQ_STAT 0x21e5
-#define mmCP_CEQ1_AVAIL 0x21e6
-#define mmCP_CEQ2_AVAIL 0x21e7
-#define mmCP_CE_ROQ_RB_STAT 0x21e8
-#define mmCP_CE_ROQ_IB1_STAT 0x21e9
-#define mmCP_CE_ROQ_IB2_STAT 0x21ea
-#define mmCP_INT_STAT_DEBUG 0x21f7
-#define mmCP_PERFMON_CNTL 0xd808
-#define mmCP_PERFMON_CNTX_CNTL 0xa0d8
-#define mmCP_RINGID 0xa0d9
-#define mmCP_PIPEID 0xa0d9
-#define mmCP_VMID 0xa0da
-#define mmCP_HPD_ROQ_OFFSETS 0x3240
-#define mmCP_HPD_STATUS0 0x3241
-#define mmCP_MQD_BASE_ADDR 0x3245
-#define mmCP_MQD_BASE_ADDR_HI 0x3246
-#define mmCP_HQD_ACTIVE 0x3247
-#define mmCP_HQD_VMID 0x3248
-#define mmCP_HQD_PERSISTENT_STATE 0x3249
-#define mmCP_HQD_PIPE_PRIORITY 0x324a
-#define mmCP_HQD_QUEUE_PRIORITY 0x324b
-#define mmCP_HQD_QUANTUM 0x324c
-#define mmCP_HQD_PQ_BASE 0x324d
-#define mmCP_HQD_PQ_BASE_HI 0x324e
-#define mmCP_HQD_PQ_RPTR 0x324f
-#define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x3250
-#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x3251
-#define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x3252
-#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x3253
-#define mmCP_HQD_PQ_DOORBELL_CONTROL 0x3254
-#define mmCP_HQD_PQ_WPTR 0x3255
-#define mmCP_HQD_PQ_CONTROL 0x3256
-#define mmCP_HQD_IB_BASE_ADDR 0x3257
-#define mmCP_HQD_IB_BASE_ADDR_HI 0x3258
-#define mmCP_HQD_IB_RPTR 0x3259
-#define mmCP_HQD_IB_CONTROL 0x325a
-#define mmCP_HQD_IQ_TIMER 0x325b
-#define mmCP_HQD_IQ_RPTR 0x325c
-#define mmCP_HQD_DEQUEUE_REQUEST 0x325d
-#define mmCP_HQD_DMA_OFFLOAD 0x325e
-#define mmCP_HQD_OFFLOAD 0x325e
-#define mmCP_HQD_SEMA_CMD 0x325f
-#define mmCP_HQD_MSG_TYPE 0x3260
-#define mmCP_HQD_ATOMIC0_PREOP_LO 0x3261
-#define mmCP_HQD_ATOMIC0_PREOP_HI 0x3262
-#define mmCP_HQD_ATOMIC1_PREOP_LO 0x3263
-#define mmCP_HQD_ATOMIC1_PREOP_HI 0x3264
-#define mmCP_HQD_HQ_SCHEDULER0 0x3265
-#define mmCP_HQD_HQ_STATUS0 0x3265
-#define mmCP_HQD_HQ_SCHEDULER1 0x3266
-#define mmCP_HQD_HQ_CONTROL0 0x3266
-#define mmCP_MQD_CONTROL 0x3267
-#define mmCP_HQD_HQ_STATUS1 0x3268
-#define mmCP_HQD_HQ_CONTROL1 0x3269
-#define mmCP_HQD_EOP_BASE_ADDR 0x326a
-#define mmCP_HQD_EOP_BASE_ADDR_HI 0x326b
-#define mmCP_HQD_EOP_CONTROL 0x326c
-#define mmCP_HQD_EOP_RPTR 0x326d
-#define mmCP_HQD_EOP_WPTR 0x326e
-#define mmCP_HQD_EOP_EVENTS 0x326f
-#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO 0x3270
-#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI 0x3271
-#define mmCP_HQD_CTX_SAVE_CONTROL 0x3272
-#define mmCP_HQD_CNTL_STACK_OFFSET 0x3273
-#define mmCP_HQD_CNTL_STACK_SIZE 0x3274
-#define mmCP_HQD_WG_STATE_OFFSET 0x3275
-#define mmCP_HQD_CTX_SAVE_SIZE 0x3276
-#define mmCP_HQD_GDS_RESOURCE_STATE 0x3277
-#define mmCP_HQD_ERROR 0x3278
-#define mmCP_HQD_EOP_WPTR_MEM 0x3279
-#define mmCP_HQD_EOP_DONES 0x327a
-#define mmDB_Z_READ_BASE 0xa012
-#define mmDB_STENCIL_READ_BASE 0xa013
-#define mmDB_Z_WRITE_BASE 0xa014
-#define mmDB_STENCIL_WRITE_BASE 0xa015
-#define mmDB_DEPTH_INFO 0xa00f
-#define mmDB_Z_INFO 0xa010
-#define mmDB_STENCIL_INFO 0xa011
-#define mmDB_DEPTH_SIZE 0xa016
-#define mmDB_DEPTH_SLICE 0xa017
-#define mmDB_DEPTH_VIEW 0xa002
-#define mmDB_RENDER_CONTROL 0xa000
-#define mmDB_COUNT_CONTROL 0xa001
-#define mmDB_RENDER_OVERRIDE 0xa003
-#define mmDB_RENDER_OVERRIDE2 0xa004
-#define mmDB_EQAA 0xa201
-#define mmDB_SHADER_CONTROL 0xa203
-#define mmDB_DEPTH_BOUNDS_MIN 0xa008
-#define mmDB_DEPTH_BOUNDS_MAX 0xa009
-#define mmDB_STENCIL_CLEAR 0xa00a
-#define mmDB_DEPTH_CLEAR 0xa00b
-#define mmDB_HTILE_DATA_BASE 0xa005
-#define mmDB_HTILE_SURFACE 0xa2af
-#define mmDB_PRELOAD_CONTROL 0xa2b2
-#define mmDB_STENCILREFMASK 0xa10c
-#define mmDB_STENCILREFMASK_BF 0xa10d
-#define mmDB_SRESULTS_COMPARE_STATE0 0xa2b0
-#define mmDB_SRESULTS_COMPARE_STATE1 0xa2b1
-#define mmDB_DEPTH_CONTROL 0xa200
-#define mmDB_STENCIL_CONTROL 0xa10b
-#define mmDB_ALPHA_TO_MASK 0xa2dc
-#define mmDB_PERFCOUNTER0_SELECT 0xdc40
-#define mmDB_PERFCOUNTER1_SELECT 0xdc42
-#define mmDB_PERFCOUNTER2_SELECT 0xdc44
-#define mmDB_PERFCOUNTER3_SELECT 0xdc46
-#define mmDB_PERFCOUNTER0_SELECT1 0xdc41
-#define mmDB_PERFCOUNTER1_SELECT1 0xdc43
-#define mmDB_PERFCOUNTER0_LO 0xd440
-#define mmDB_PERFCOUNTER1_LO 0xd442
-#define mmDB_PERFCOUNTER2_LO 0xd444
-#define mmDB_PERFCOUNTER3_LO 0xd446
-#define mmDB_PERFCOUNTER0_HI 0xd441
-#define mmDB_PERFCOUNTER1_HI 0xd443
-#define mmDB_PERFCOUNTER2_HI 0xd445
-#define mmDB_PERFCOUNTER3_HI 0xd447
-#define mmDB_DEBUG 0x260c
-#define mmDB_DEBUG2 0x260d
-#define mmDB_DEBUG3 0x260e
-#define mmDB_DEBUG4 0x260f
-#define mmDB_CREDIT_LIMIT 0x2614
-#define mmDB_WATERMARKS 0x2615
-#define mmDB_SUBTILE_CONTROL 0x2616
-#define mmDB_FREE_CACHELINES 0x2617
-#define mmDB_FIFO_DEPTH1 0x2618
-#define mmDB_FIFO_DEPTH2 0x2619
-#define mmDB_CGTT_CLK_CTRL_0 0xf0a4
-#define mmDB_ZPASS_COUNT_LOW 0xc3fe
-#define mmDB_ZPASS_COUNT_HI 0xc3ff
-#define mmDB_RING_CONTROL 0x261b
-#define mmDB_READ_DEBUG_0 0x2620
-#define mmDB_READ_DEBUG_1 0x2621
-#define mmDB_READ_DEBUG_2 0x2622
-#define mmDB_READ_DEBUG_3 0x2623
-#define mmDB_READ_DEBUG_4 0x2624
-#define mmDB_READ_DEBUG_5 0x2625
-#define mmDB_READ_DEBUG_6 0x2626
-#define mmDB_READ_DEBUG_7 0x2627
-#define mmDB_READ_DEBUG_8 0x2628
-#define mmDB_READ_DEBUG_9 0x2629
-#define mmDB_READ_DEBUG_A 0x262a
-#define mmDB_READ_DEBUG_B 0x262b
-#define mmDB_READ_DEBUG_C 0x262c
-#define mmDB_READ_DEBUG_D 0x262d
-#define mmDB_READ_DEBUG_E 0x262e
-#define mmDB_READ_DEBUG_F 0x262f
-#define mmDB_OCCLUSION_COUNT0_LOW 0xc3c0
-#define mmDB_OCCLUSION_COUNT0_HI 0xc3c1
-#define mmDB_OCCLUSION_COUNT1_LOW 0xc3c2
-#define mmDB_OCCLUSION_COUNT1_HI 0xc3c3
-#define mmDB_OCCLUSION_COUNT2_LOW 0xc3c4
-#define mmDB_OCCLUSION_COUNT2_HI 0xc3c5
-#define mmDB_OCCLUSION_COUNT3_LOW 0xc3c6
-#define mmDB_OCCLUSION_COUNT3_HI 0xc3c7
-#define mmCC_RB_REDUNDANCY 0x263c
-#define mmCC_RB_BACKEND_DISABLE 0x263d
-#define mmGC_USER_RB_REDUNDANCY 0x26de
-#define mmGC_USER_RB_BACKEND_DISABLE 0x26df
-#define mmGB_ADDR_CONFIG 0x263e
-#define mmGB_BACKEND_MAP 0x263f
-#define mmGB_GPU_ID 0x2640
-#define mmCC_RB_DAISY_CHAIN 0x2641
-#define mmGB_TILE_MODE0 0x2644
-#define mmGB_TILE_MODE1 0x2645
-#define mmGB_TILE_MODE2 0x2646
-#define mmGB_TILE_MODE3 0x2647
-#define mmGB_TILE_MODE4 0x2648
-#define mmGB_TILE_MODE5 0x2649
-#define mmGB_TILE_MODE6 0x264a
-#define mmGB_TILE_MODE7 0x264b
-#define mmGB_TILE_MODE8 0x264c
-#define mmGB_TILE_MODE9 0x264d
-#define mmGB_TILE_MODE10 0x264e
-#define mmGB_TILE_MODE11 0x264f
-#define mmGB_TILE_MODE12 0x2650
-#define mmGB_TILE_MODE13 0x2651
-#define mmGB_TILE_MODE14 0x2652
-#define mmGB_TILE_MODE15 0x2653
-#define mmGB_TILE_MODE16 0x2654
-#define mmGB_TILE_MODE17 0x2655
-#define mmGB_TILE_MODE18 0x2656
-#define mmGB_TILE_MODE19 0x2657
-#define mmGB_TILE_MODE20 0x2658
-#define mmGB_TILE_MODE21 0x2659
-#define mmGB_TILE_MODE22 0x265a
-#define mmGB_TILE_MODE23 0x265b
-#define mmGB_TILE_MODE24 0x265c
-#define mmGB_TILE_MODE25 0x265d
-#define mmGB_TILE_MODE26 0x265e
-#define mmGB_TILE_MODE27 0x265f
-#define mmGB_TILE_MODE28 0x2660
-#define mmGB_TILE_MODE29 0x2661
-#define mmGB_TILE_MODE30 0x2662
-#define mmGB_TILE_MODE31 0x2663
-#define mmGB_MACROTILE_MODE0 0x2664
-#define mmGB_MACROTILE_MODE1 0x2665
-#define mmGB_MACROTILE_MODE2 0x2666
-#define mmGB_MACROTILE_MODE3 0x2667
-#define mmGB_MACROTILE_MODE4 0x2668
-#define mmGB_MACROTILE_MODE5 0x2669
-#define mmGB_MACROTILE_MODE6 0x266a
-#define mmGB_MACROTILE_MODE7 0x266b
-#define mmGB_MACROTILE_MODE8 0x266c
-#define mmGB_MACROTILE_MODE9 0x266d
-#define mmGB_MACROTILE_MODE10 0x266e
-#define mmGB_MACROTILE_MODE11 0x266f
-#define mmGB_MACROTILE_MODE12 0x2670
-#define mmGB_MACROTILE_MODE13 0x2671
-#define mmGB_MACROTILE_MODE14 0x2672
-#define mmGB_MACROTILE_MODE15 0x2673
-#define mmGB_EDC_MODE 0x307e
-#define mmCC_GC_EDC_CONFIG 0x3098
-#define mmRAS_SIGNATURE_CONTROL 0x3380
-#define mmRAS_SIGNATURE_MASK 0x3381
-#define mmRAS_SX_SIGNATURE0 0x3382
-#define mmRAS_SX_SIGNATURE1 0x3383
-#define mmRAS_SX_SIGNATURE2 0x3384
-#define mmRAS_SX_SIGNATURE3 0x3385
-#define mmRAS_DB_SIGNATURE0 0x338b
-#define mmRAS_PA_SIGNATURE0 0x338c
-#define mmRAS_VGT_SIGNATURE0 0x338d
-#define mmRAS_SC_SIGNATURE0 0x338f
-#define mmRAS_SC_SIGNATURE1 0x3390
-#define mmRAS_SC_SIGNATURE2 0x3391
-#define mmRAS_SC_SIGNATURE3 0x3392
-#define mmRAS_SC_SIGNATURE4 0x3393
-#define mmRAS_SC_SIGNATURE5 0x3394
-#define mmRAS_SC_SIGNATURE6 0x3395
-#define mmRAS_SC_SIGNATURE7 0x3396
-#define mmRAS_IA_SIGNATURE0 0x3397
-#define mmRAS_IA_SIGNATURE1 0x3398
-#define mmRAS_SPI_SIGNATURE0 0x3399
-#define mmRAS_SPI_SIGNATURE1 0x339a
-#define mmRAS_TA_SIGNATURE0 0x339b
-#define mmRAS_TD_SIGNATURE0 0x339c
-#define mmRAS_CB_SIGNATURE0 0x339d
-#define mmRAS_BCI_SIGNATURE0 0x339e
-#define mmRAS_BCI_SIGNATURE1 0x339f
-#define mmRAS_TA_SIGNATURE1 0x33a0
-#define mmGRBM_HYP_CAM_INDEX 0xf83e
-#define mmGRBM_CAM_INDEX 0xf83e
-#define mmGRBM_HYP_CAM_DATA 0xf83f
-#define mmGRBM_CAM_DATA 0xf83f
-#define mmGRBM_CNTL 0x2000
-#define mmGRBM_SKEW_CNTL 0x2001
-#define mmGRBM_PWR_CNTL 0x2003
-#define mmGRBM_STATUS 0x2004
-#define mmGRBM_STATUS2 0x2002
-#define mmGRBM_STATUS_SE0 0x2005
-#define mmGRBM_STATUS_SE1 0x2006
-#define mmGRBM_STATUS_SE2 0x200e
-#define mmGRBM_STATUS_SE3 0x200f
-#define mmGRBM_SOFT_RESET 0x2008
-#define mmGRBM_DEBUG_CNTL 0x2009
-#define mmGRBM_DEBUG_DATA 0x200a
-#define mmGRBM_CGTT_CLK_CNTL 0x200b
-#define mmGRBM_GFX_INDEX 0xc200
-#define mmGRBM_GFX_CLKEN_CNTL 0x200c
-#define mmGRBM_WAIT_IDLE_CLOCKS 0x200d
-#define mmGRBM_DEBUG 0x2014
-#define mmGRBM_DEBUG_SNAPSHOT 0x2015
-#define mmGRBM_READ_ERROR 0x2016
-#define mmGRBM_READ_ERROR2 0x2017
-#define mmGRBM_INT_CNTL 0x2018
-#define mmGRBM_TRAP_OP 0x2019
-#define mmGRBM_TRAP_ADDR 0x201a
-#define mmGRBM_TRAP_ADDR_MSK 0x201b
-#define mmGRBM_TRAP_WD 0x201c
-#define mmGRBM_TRAP_WD_MSK 0x201d
-#define mmGRBM_DSM_BYPASS 0x201e
-#define mmGRBM_WRITE_ERROR 0x201f
-#define mmGRBM_PERFCOUNTER0_SELECT 0xd840
-#define mmGRBM_PERFCOUNTER1_SELECT 0xd841
-#define mmGRBM_SE0_PERFCOUNTER_SELECT 0xd842
-#define mmGRBM_SE1_PERFCOUNTER_SELECT 0xd843
-#define mmGRBM_SE2_PERFCOUNTER_SELECT 0xd844
-#define mmGRBM_SE3_PERFCOUNTER_SELECT 0xd845
-#define mmGRBM_PERFCOUNTER0_LO 0xd040
-#define mmGRBM_PERFCOUNTER0_HI 0xd041
-#define mmGRBM_PERFCOUNTER1_LO 0xd043
-#define mmGRBM_PERFCOUNTER1_HI 0xd044
-#define mmGRBM_SE0_PERFCOUNTER_LO 0xd045
-#define mmGRBM_SE0_PERFCOUNTER_HI 0xd046
-#define mmGRBM_SE1_PERFCOUNTER_LO 0xd047
-#define mmGRBM_SE1_PERFCOUNTER_HI 0xd048
-#define mmGRBM_SE2_PERFCOUNTER_LO 0xd049
-#define mmGRBM_SE2_PERFCOUNTER_HI 0xd04a
-#define mmGRBM_SE3_PERFCOUNTER_LO 0xd04b
-#define mmGRBM_SE3_PERFCOUNTER_HI 0xd04c
-#define mmGRBM_SCRATCH_REG0 0x2040
-#define mmGRBM_SCRATCH_REG1 0x2041
-#define mmGRBM_SCRATCH_REG2 0x2042
-#define mmGRBM_SCRATCH_REG3 0x2043
-#define mmGRBM_SCRATCH_REG4 0x2044
-#define mmGRBM_SCRATCH_REG5 0x2045
-#define mmGRBM_SCRATCH_REG6 0x2046
-#define mmGRBM_SCRATCH_REG7 0x2047
-#define mmDEBUG_INDEX 0x203c
-#define mmDEBUG_DATA 0x203d
-#define mmGRBM_NOWHERE 0x203f
-#define mmPA_CL_VPORT_XSCALE 0xa10f
-#define mmPA_CL_VPORT_XOFFSET 0xa110
-#define mmPA_CL_VPORT_YSCALE 0xa111
-#define mmPA_CL_VPORT_YOFFSET 0xa112
-#define mmPA_CL_VPORT_ZSCALE 0xa113
-#define mmPA_CL_VPORT_ZOFFSET 0xa114
-#define mmPA_CL_VPORT_XSCALE_1 0xa115
-#define mmPA_CL_VPORT_XSCALE_2 0xa11b
-#define mmPA_CL_VPORT_XSCALE_3 0xa121
-#define mmPA_CL_VPORT_XSCALE_4 0xa127
-#define mmPA_CL_VPORT_XSCALE_5 0xa12d
-#define mmPA_CL_VPORT_XSCALE_6 0xa133
-#define mmPA_CL_VPORT_XSCALE_7 0xa139
-#define mmPA_CL_VPORT_XSCALE_8 0xa13f
-#define mmPA_CL_VPORT_XSCALE_9 0xa145
-#define mmPA_CL_VPORT_XSCALE_10 0xa14b
-#define mmPA_CL_VPORT_XSCALE_11 0xa151
-#define mmPA_CL_VPORT_XSCALE_12 0xa157
-#define mmPA_CL_VPORT_XSCALE_13 0xa15d
-#define mmPA_CL_VPORT_XSCALE_14 0xa163
-#define mmPA_CL_VPORT_XSCALE_15 0xa169
-#define mmPA_CL_VPORT_XOFFSET_1 0xa116
-#define mmPA_CL_VPORT_XOFFSET_2 0xa11c
-#define mmPA_CL_VPORT_XOFFSET_3 0xa122
-#define mmPA_CL_VPORT_XOFFSET_4 0xa128
-#define mmPA_CL_VPORT_XOFFSET_5 0xa12e
-#define mmPA_CL_VPORT_XOFFSET_6 0xa134
-#define mmPA_CL_VPORT_XOFFSET_7 0xa13a
-#define mmPA_CL_VPORT_XOFFSET_8 0xa140
-#define mmPA_CL_VPORT_XOFFSET_9 0xa146
-#define mmPA_CL_VPORT_XOFFSET_10 0xa14c
-#define mmPA_CL_VPORT_XOFFSET_11 0xa152
-#define mmPA_CL_VPORT_XOFFSET_12 0xa158
-#define mmPA_CL_VPORT_XOFFSET_13 0xa15e
-#define mmPA_CL_VPORT_XOFFSET_14 0xa164
-#define mmPA_CL_VPORT_XOFFSET_15 0xa16a
-#define mmPA_CL_VPORT_YSCALE_1 0xa117
-#define mmPA_CL_VPORT_YSCALE_2 0xa11d
-#define mmPA_CL_VPORT_YSCALE_3 0xa123
-#define mmPA_CL_VPORT_YSCALE_4 0xa129
-#define mmPA_CL_VPORT_YSCALE_5 0xa12f
-#define mmPA_CL_VPORT_YSCALE_6 0xa135
-#define mmPA_CL_VPORT_YSCALE_7 0xa13b
-#define mmPA_CL_VPORT_YSCALE_8 0xa141
-#define mmPA_CL_VPORT_YSCALE_9 0xa147
-#define mmPA_CL_VPORT_YSCALE_10 0xa14d
-#define mmPA_CL_VPORT_YSCALE_11 0xa153
-#define mmPA_CL_VPORT_YSCALE_12 0xa159
-#define mmPA_CL_VPORT_YSCALE_13 0xa15f
-#define mmPA_CL_VPORT_YSCALE_14 0xa165
-#define mmPA_CL_VPORT_YSCALE_15 0xa16b
-#define mmPA_CL_VPORT_YOFFSET_1 0xa118
-#define mmPA_CL_VPORT_YOFFSET_2 0xa11e
-#define mmPA_CL_VPORT_YOFFSET_3 0xa124
-#define mmPA_CL_VPORT_YOFFSET_4 0xa12a
-#define mmPA_CL_VPORT_YOFFSET_5 0xa130
-#define mmPA_CL_VPORT_YOFFSET_6 0xa136
-#define mmPA_CL_VPORT_YOFFSET_7 0xa13c
-#define mmPA_CL_VPORT_YOFFSET_8 0xa142
-#define mmPA_CL_VPORT_YOFFSET_9 0xa148
-#define mmPA_CL_VPORT_YOFFSET_10 0xa14e
-#define mmPA_CL_VPORT_YOFFSET_11 0xa154
-#define mmPA_CL_VPORT_YOFFSET_12 0xa15a
-#define mmPA_CL_VPORT_YOFFSET_13 0xa160
-#define mmPA_CL_VPORT_YOFFSET_14 0xa166
-#define mmPA_CL_VPORT_YOFFSET_15 0xa16c
-#define mmPA_CL_VPORT_ZSCALE_1 0xa119
-#define mmPA_CL_VPORT_ZSCALE_2 0xa11f
-#define mmPA_CL_VPORT_ZSCALE_3 0xa125
-#define mmPA_CL_VPORT_ZSCALE_4 0xa12b
-#define mmPA_CL_VPORT_ZSCALE_5 0xa131
-#define mmPA_CL_VPORT_ZSCALE_6 0xa137
-#define mmPA_CL_VPORT_ZSCALE_7 0xa13d
-#define mmPA_CL_VPORT_ZSCALE_8 0xa143
-#define mmPA_CL_VPORT_ZSCALE_9 0xa149
-#define mmPA_CL_VPORT_ZSCALE_10 0xa14f
-#define mmPA_CL_VPORT_ZSCALE_11 0xa155
-#define mmPA_CL_VPORT_ZSCALE_12 0xa15b
-#define mmPA_CL_VPORT_ZSCALE_13 0xa161
-#define mmPA_CL_VPORT_ZSCALE_14 0xa167
-#define mmPA_CL_VPORT_ZSCALE_15 0xa16d
-#define mmPA_CL_VPORT_ZOFFSET_1 0xa11a
-#define mmPA_CL_VPORT_ZOFFSET_2 0xa120
-#define mmPA_CL_VPORT_ZOFFSET_3 0xa126
-#define mmPA_CL_VPORT_ZOFFSET_4 0xa12c
-#define mmPA_CL_VPORT_ZOFFSET_5 0xa132
-#define mmPA_CL_VPORT_ZOFFSET_6 0xa138
-#define mmPA_CL_VPORT_ZOFFSET_7 0xa13e
-#define mmPA_CL_VPORT_ZOFFSET_8 0xa144
-#define mmPA_CL_VPORT_ZOFFSET_9 0xa14a
-#define mmPA_CL_VPORT_ZOFFSET_10 0xa150
-#define mmPA_CL_VPORT_ZOFFSET_11 0xa156
-#define mmPA_CL_VPORT_ZOFFSET_12 0xa15c
-#define mmPA_CL_VPORT_ZOFFSET_13 0xa162
-#define mmPA_CL_VPORT_ZOFFSET_14 0xa168
-#define mmPA_CL_VPORT_ZOFFSET_15 0xa16e
-#define mmPA_CL_VTE_CNTL 0xa206
-#define mmPA_CL_VS_OUT_CNTL 0xa207
-#define mmPA_CL_NANINF_CNTL 0xa208
-#define mmPA_CL_CLIP_CNTL 0xa204
-#define mmPA_CL_GB_VERT_CLIP_ADJ 0xa2fa
-#define mmPA_CL_GB_VERT_DISC_ADJ 0xa2fb
-#define mmPA_CL_GB_HORZ_CLIP_ADJ 0xa2fc
-#define mmPA_CL_GB_HORZ_DISC_ADJ 0xa2fd
-#define mmPA_CL_UCP_0_X 0xa16f
-#define mmPA_CL_UCP_0_Y 0xa170
-#define mmPA_CL_UCP_0_Z 0xa171
-#define mmPA_CL_UCP_0_W 0xa172
-#define mmPA_CL_UCP_1_X 0xa173
-#define mmPA_CL_UCP_1_Y 0xa174
-#define mmPA_CL_UCP_1_Z 0xa175
-#define mmPA_CL_UCP_1_W 0xa176
-#define mmPA_CL_UCP_2_X 0xa177
-#define mmPA_CL_UCP_2_Y 0xa178
-#define mmPA_CL_UCP_2_Z 0xa179
-#define mmPA_CL_UCP_2_W 0xa17a
-#define mmPA_CL_UCP_3_X 0xa17b
-#define mmPA_CL_UCP_3_Y 0xa17c
-#define mmPA_CL_UCP_3_Z 0xa17d
-#define mmPA_CL_UCP_3_W 0xa17e
-#define mmPA_CL_UCP_4_X 0xa17f
-#define mmPA_CL_UCP_4_Y 0xa180
-#define mmPA_CL_UCP_4_Z 0xa181
-#define mmPA_CL_UCP_4_W 0xa182
-#define mmPA_CL_UCP_5_X 0xa183
-#define mmPA_CL_UCP_5_Y 0xa184
-#define mmPA_CL_UCP_5_Z 0xa185
-#define mmPA_CL_UCP_5_W 0xa186
-#define mmPA_CL_POINT_X_RAD 0xa1f5
-#define mmPA_CL_POINT_Y_RAD 0xa1f6
-#define mmPA_CL_POINT_SIZE 0xa1f7
-#define mmPA_CL_POINT_CULL_RAD 0xa1f8
-#define mmPA_CL_ENHANCE 0x2285
-#define mmPA_CL_RESET_DEBUG 0x2286
-#define mmPA_SU_VTX_CNTL 0xa2f9
-#define mmPA_SU_POINT_SIZE 0xa280
-#define mmPA_SU_POINT_MINMAX 0xa281
-#define mmPA_SU_LINE_CNTL 0xa282
-#define mmPA_SU_LINE_STIPPLE_CNTL 0xa209
-#define mmPA_SU_LINE_STIPPLE_SCALE 0xa20a
-#define mmPA_SU_PRIM_FILTER_CNTL 0xa20b
-#define mmPA_SU_SC_MODE_CNTL 0xa205
-#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL 0xa2de
-#define mmPA_SU_POLY_OFFSET_CLAMP 0xa2df
-#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0xa2e0
-#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0xa2e1
-#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0xa2e2
-#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0xa2e3
-#define mmPA_SU_HARDWARE_SCREEN_OFFSET 0xa08d
-#define mmPA_SU_LINE_STIPPLE_VALUE 0xc280
-#define mmPA_SU_PERFCOUNTER0_SELECT 0xd900
-#define mmPA_SU_PERFCOUNTER0_SELECT1 0xd901
-#define mmPA_SU_PERFCOUNTER1_SELECT 0xd902
-#define mmPA_SU_PERFCOUNTER1_SELECT1 0xd903
-#define mmPA_SU_PERFCOUNTER2_SELECT 0xd904
-#define mmPA_SU_PERFCOUNTER3_SELECT 0xd905
-#define mmPA_SU_PERFCOUNTER0_LO 0xd100
-#define mmPA_SU_PERFCOUNTER0_HI 0xd101
-#define mmPA_SU_PERFCOUNTER1_LO 0xd102
-#define mmPA_SU_PERFCOUNTER1_HI 0xd103
-#define mmPA_SU_PERFCOUNTER2_LO 0xd104
-#define mmPA_SU_PERFCOUNTER2_HI 0xd105
-#define mmPA_SU_PERFCOUNTER3_LO 0xd106
-#define mmPA_SU_PERFCOUNTER3_HI 0xd107
-#define mmPA_SC_AA_CONFIG 0xa2f8
-#define mmPA_SC_AA_MASK_X0Y0_X1Y0 0xa30e
-#define mmPA_SC_AA_MASK_X0Y1_X1Y1 0xa30f
-#define mmPA_SC_SHADER_CONTROL 0xa310
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0xa2fe
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0xa2ff
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0xa300
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0xa301
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0xa302
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0xa303
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0xa304
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0xa305
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0xa306
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0xa307
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0xa308
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0xa309
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0xa30a
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0xa30b
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0xa30c
-#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0xa30d
-#define mmPA_SC_CENTROID_PRIORITY_0 0xa2f5
-#define mmPA_SC_CENTROID_PRIORITY_1 0xa2f6
-#define mmPA_SC_CLIPRECT_0_TL 0xa084
-#define mmPA_SC_CLIPRECT_0_BR 0xa085
-#define mmPA_SC_CLIPRECT_1_TL 0xa086
-#define mmPA_SC_CLIPRECT_1_BR 0xa087
-#define mmPA_SC_CLIPRECT_2_TL 0xa088
-#define mmPA_SC_CLIPRECT_2_BR 0xa089
-#define mmPA_SC_CLIPRECT_3_TL 0xa08a
-#define mmPA_SC_CLIPRECT_3_BR 0xa08b
-#define mmPA_SC_CLIPRECT_RULE 0xa083
-#define mmPA_SC_EDGERULE 0xa08c
-#define mmPA_SC_LINE_CNTL 0xa2f7
-#define mmPA_SC_LINE_STIPPLE 0xa283
-#define mmPA_SC_MODE_CNTL_0 0xa292
-#define mmPA_SC_MODE_CNTL_1 0xa293
-#define mmPA_SC_RASTER_CONFIG 0xa0d4
-#define mmPA_SC_RASTER_CONFIG_1 0xa0d5
-#define mmPA_SC_SCREEN_EXTENT_CONTROL 0xa0d6
-#define mmPA_SC_GENERIC_SCISSOR_TL 0xa090
-#define mmPA_SC_GENERIC_SCISSOR_BR 0xa091
-#define mmPA_SC_SCREEN_SCISSOR_TL 0xa00c
-#define mmPA_SC_SCREEN_SCISSOR_BR 0xa00d
-#define mmPA_SC_WINDOW_OFFSET 0xa080
-#define mmPA_SC_WINDOW_SCISSOR_TL 0xa081
-#define mmPA_SC_WINDOW_SCISSOR_BR 0xa082
-#define mmPA_SC_VPORT_SCISSOR_0_TL 0xa094
-#define mmPA_SC_VPORT_SCISSOR_1_TL 0xa096
-#define mmPA_SC_VPORT_SCISSOR_2_TL 0xa098
-#define mmPA_SC_VPORT_SCISSOR_3_TL 0xa09a
-#define mmPA_SC_VPORT_SCISSOR_4_TL 0xa09c
-#define mmPA_SC_VPORT_SCISSOR_5_TL 0xa09e
-#define mmPA_SC_VPORT_SCISSOR_6_TL 0xa0a0
-#define mmPA_SC_VPORT_SCISSOR_7_TL 0xa0a2
-#define mmPA_SC_VPORT_SCISSOR_8_TL 0xa0a4
-#define mmPA_SC_VPORT_SCISSOR_9_TL 0xa0a6
-#define mmPA_SC_VPORT_SCISSOR_10_TL 0xa0a8
-#define mmPA_SC_VPORT_SCISSOR_11_TL 0xa0aa
-#define mmPA_SC_VPORT_SCISSOR_12_TL 0xa0ac
-#define mmPA_SC_VPORT_SCISSOR_13_TL 0xa0ae
-#define mmPA_SC_VPORT_SCISSOR_14_TL 0xa0b0
-#define mmPA_SC_VPORT_SCISSOR_15_TL 0xa0b2
-#define mmPA_SC_VPORT_SCISSOR_0_BR 0xa095
-#define mmPA_SC_VPORT_SCISSOR_1_BR 0xa097
-#define mmPA_SC_VPORT_SCISSOR_2_BR 0xa099
-#define mmPA_SC_VPORT_SCISSOR_3_BR 0xa09b
-#define mmPA_SC_VPORT_SCISSOR_4_BR 0xa09d
-#define mmPA_SC_VPORT_SCISSOR_5_BR 0xa09f
-#define mmPA_SC_VPORT_SCISSOR_6_BR 0xa0a1
-#define mmPA_SC_VPORT_SCISSOR_7_BR 0xa0a3
-#define mmPA_SC_VPORT_SCISSOR_8_BR 0xa0a5
-#define mmPA_SC_VPORT_SCISSOR_9_BR 0xa0a7
-#define mmPA_SC_VPORT_SCISSOR_10_BR 0xa0a9
-#define mmPA_SC_VPORT_SCISSOR_11_BR 0xa0ab
-#define mmPA_SC_VPORT_SCISSOR_12_BR 0xa0ad
-#define mmPA_SC_VPORT_SCISSOR_13_BR 0xa0af
-#define mmPA_SC_VPORT_SCISSOR_14_BR 0xa0b1
-#define mmPA_SC_VPORT_SCISSOR_15_BR 0xa0b3
-#define mmPA_SC_VPORT_ZMIN_0 0xa0b4
-#define mmPA_SC_VPORT_ZMIN_1 0xa0b6
-#define mmPA_SC_VPORT_ZMIN_2 0xa0b8
-#define mmPA_SC_VPORT_ZMIN_3 0xa0ba
-#define mmPA_SC_VPORT_ZMIN_4 0xa0bc
-#define mmPA_SC_VPORT_ZMIN_5 0xa0be
-#define mmPA_SC_VPORT_ZMIN_6 0xa0c0
-#define mmPA_SC_VPORT_ZMIN_7 0xa0c2
-#define mmPA_SC_VPORT_ZMIN_8 0xa0c4
-#define mmPA_SC_VPORT_ZMIN_9 0xa0c6
-#define mmPA_SC_VPORT_ZMIN_10 0xa0c8
-#define mmPA_SC_VPORT_ZMIN_11 0xa0ca
-#define mmPA_SC_VPORT_ZMIN_12 0xa0cc
-#define mmPA_SC_VPORT_ZMIN_13 0xa0ce
-#define mmPA_SC_VPORT_ZMIN_14 0xa0d0
-#define mmPA_SC_VPORT_ZMIN_15 0xa0d2
-#define mmPA_SC_VPORT_ZMAX_0 0xa0b5
-#define mmPA_SC_VPORT_ZMAX_1 0xa0b7
-#define mmPA_SC_VPORT_ZMAX_2 0xa0b9
-#define mmPA_SC_VPORT_ZMAX_3 0xa0bb
-#define mmPA_SC_VPORT_ZMAX_4 0xa0bd
-#define mmPA_SC_VPORT_ZMAX_5 0xa0bf
-#define mmPA_SC_VPORT_ZMAX_6 0xa0c1
-#define mmPA_SC_VPORT_ZMAX_7 0xa0c3
-#define mmPA_SC_VPORT_ZMAX_8 0xa0c5
-#define mmPA_SC_VPORT_ZMAX_9 0xa0c7
-#define mmPA_SC_VPORT_ZMAX_10 0xa0c9
-#define mmPA_SC_VPORT_ZMAX_11 0xa0cb
-#define mmPA_SC_VPORT_ZMAX_12 0xa0cd
-#define mmPA_SC_VPORT_ZMAX_13 0xa0cf
-#define mmPA_SC_VPORT_ZMAX_14 0xa0d1
-#define mmPA_SC_VPORT_ZMAX_15 0xa0d3
-#define mmPA_SC_ENHANCE 0x22fc
-#define mmPA_SC_ENHANCE_1 0x22fd
-#define mmPA_SC_DSM_CNTL 0x22fe
-#define mmPA_SC_FIFO_SIZE 0x22f3
-#define mmPA_SC_IF_FIFO_SIZE 0x22f5
-#define mmPA_SC_FORCE_EOV_MAX_CNTS 0x22c9
-#define mmPA_SC_LINE_STIPPLE_STATE 0xc281
-#define mmPA_SC_SCREEN_EXTENT_MIN_0 0xc284
-#define mmPA_SC_SCREEN_EXTENT_MAX_0 0xc285
-#define mmPA_SC_SCREEN_EXTENT_MIN_1 0xc286
-#define mmPA_SC_SCREEN_EXTENT_MAX_1 0xc28b
-#define mmPA_SC_PERFCOUNTER0_SELECT 0xd940
-#define mmPA_SC_PERFCOUNTER0_SELECT1 0xd941
-#define mmPA_SC_PERFCOUNTER1_SELECT 0xd942
-#define mmPA_SC_PERFCOUNTER2_SELECT 0xd943
-#define mmPA_SC_PERFCOUNTER3_SELECT 0xd944
-#define mmPA_SC_PERFCOUNTER4_SELECT 0xd945
-#define mmPA_SC_PERFCOUNTER5_SELECT 0xd946
-#define mmPA_SC_PERFCOUNTER6_SELECT 0xd947
-#define mmPA_SC_PERFCOUNTER7_SELECT 0xd948
-#define mmPA_SC_PERFCOUNTER0_LO 0xd140
-#define mmPA_SC_PERFCOUNTER0_HI 0xd141
-#define mmPA_SC_PERFCOUNTER1_LO 0xd142
-#define mmPA_SC_PERFCOUNTER1_HI 0xd143
-#define mmPA_SC_PERFCOUNTER2_LO 0xd144
-#define mmPA_SC_PERFCOUNTER2_HI 0xd145
-#define mmPA_SC_PERFCOUNTER3_LO 0xd146
-#define mmPA_SC_PERFCOUNTER3_HI 0xd147
-#define mmPA_SC_PERFCOUNTER4_LO 0xd148
-#define mmPA_SC_PERFCOUNTER4_HI 0xd149
-#define mmPA_SC_PERFCOUNTER5_LO 0xd14a
-#define mmPA_SC_PERFCOUNTER5_HI 0xd14b
-#define mmPA_SC_PERFCOUNTER6_LO 0xd14c
-#define mmPA_SC_PERFCOUNTER6_HI 0xd14d
-#define mmPA_SC_PERFCOUNTER7_LO 0xd14e
-#define mmPA_SC_PERFCOUNTER7_HI 0xd14f
-#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN 0xc2a0
-#define mmPA_SC_P3D_TRAP_SCREEN_H 0xc2a1
-#define mmPA_SC_P3D_TRAP_SCREEN_V 0xc2a2
-#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0xc2a3
-#define mmPA_SC_P3D_TRAP_SCREEN_COUNT 0xc2a4
-#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN 0xc2a8
-#define mmPA_SC_HP3D_TRAP_SCREEN_H 0xc2a9
-#define mmPA_SC_HP3D_TRAP_SCREEN_V 0xc2aa
-#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0xc2ab
-#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT 0xc2ac
-#define mmPA_SC_TRAP_SCREEN_HV_EN 0xc2b0
-#define mmPA_SC_TRAP_SCREEN_H 0xc2b1
-#define mmPA_SC_TRAP_SCREEN_V 0xc2b2
-#define mmPA_SC_TRAP_SCREEN_OCCURRENCE 0xc2b3
-#define mmPA_SC_TRAP_SCREEN_COUNT 0xc2b4
-#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x22c0
-#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x22c1
-#define mmPA_SC_TRAP_SCREEN_HV_LOCK 0x22c2
-#define mmPA_CL_CNTL_STATUS 0x2284
-#define mmPA_SU_CNTL_STATUS 0x2294
-#define mmPA_SC_FIFO_DEPTH_CNTL 0x2295
-#define mmCGTT_PA_CLK_CTRL 0xf088
-#define mmCGTT_SC_CLK_CTRL 0xf089
-#define mmPA_SU_DEBUG_CNTL 0x2280
-#define mmPA_SU_DEBUG_DATA 0x2281
-#define mmPA_SC_DEBUG_CNTL 0x22f6
-#define mmPA_SC_DEBUG_DATA 0x22f7
-#define ixCLIPPER_DEBUG_REG00 0x0
-#define ixCLIPPER_DEBUG_REG01 0x1
-#define ixCLIPPER_DEBUG_REG02 0x2
-#define ixCLIPPER_DEBUG_REG03 0x3
-#define ixCLIPPER_DEBUG_REG04 0x4
-#define ixCLIPPER_DEBUG_REG05 0x5
-#define ixCLIPPER_DEBUG_REG06 0x6
-#define ixCLIPPER_DEBUG_REG07 0x7
-#define ixCLIPPER_DEBUG_REG08 0x8
-#define ixCLIPPER_DEBUG_REG09 0x9
-#define ixCLIPPER_DEBUG_REG10 0xa
-#define ixCLIPPER_DEBUG_REG11 0xb
-#define ixCLIPPER_DEBUG_REG12 0xc
-#define ixCLIPPER_DEBUG_REG13 0xd
-#define ixCLIPPER_DEBUG_REG14 0xe
-#define ixCLIPPER_DEBUG_REG15 0xf
-#define ixCLIPPER_DEBUG_REG16 0x10
-#define ixCLIPPER_DEBUG_REG17 0x11
-#define ixCLIPPER_DEBUG_REG18 0x12
-#define ixCLIPPER_DEBUG_REG19 0x13
-#define ixSXIFCCG_DEBUG_REG0 0x14
-#define ixSXIFCCG_DEBUG_REG1 0x15
-#define ixSXIFCCG_DEBUG_REG2 0x16
-#define ixSXIFCCG_DEBUG_REG3 0x17
-#define ixSETUP_DEBUG_REG0 0x18
-#define ixSETUP_DEBUG_REG1 0x19
-#define ixSETUP_DEBUG_REG2 0x1a
-#define ixSETUP_DEBUG_REG3 0x1b
-#define ixSETUP_DEBUG_REG4 0x1c
-#define ixSETUP_DEBUG_REG5 0x1d
-#define ixPA_SC_DEBUG_REG0 0x0
-#define ixPA_SC_DEBUG_REG1 0x1
-#define mmCOMPUTE_DISPATCH_INITIATOR 0x2e00
-#define mmCOMPUTE_DIM_X 0x2e01
-#define mmCOMPUTE_DIM_Y 0x2e02
-#define mmCOMPUTE_DIM_Z 0x2e03
-#define mmCOMPUTE_START_X 0x2e04
-#define mmCOMPUTE_START_Y 0x2e05
-#define mmCOMPUTE_START_Z 0x2e06
-#define mmCOMPUTE_NUM_THREAD_X 0x2e07
-#define mmCOMPUTE_NUM_THREAD_Y 0x2e08
-#define mmCOMPUTE_NUM_THREAD_Z 0x2e09
-#define mmCOMPUTE_PIPELINESTAT_ENABLE 0x2e0a
-#define mmCOMPUTE_PERFCOUNT_ENABLE 0x2e0b
-#define mmCOMPUTE_PGM_LO 0x2e0c
-#define mmCOMPUTE_PGM_HI 0x2e0d
-#define mmCOMPUTE_TBA_LO 0x2e0e
-#define mmCOMPUTE_TBA_HI 0x2e0f
-#define mmCOMPUTE_TMA_LO 0x2e10
-#define mmCOMPUTE_TMA_HI 0x2e11
-#define mmCOMPUTE_PGM_RSRC1 0x2e12
-#define mmCOMPUTE_PGM_RSRC2 0x2e13
-#define mmCOMPUTE_VMID 0x2e14
-#define mmCOMPUTE_RESOURCE_LIMITS 0x2e15
-#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0 0x2e16
-#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1 0x2e17
-#define mmCOMPUTE_TMPRING_SIZE 0x2e18
-#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2 0x2e19
-#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3 0x2e1a
-#define mmCOMPUTE_RESTART_X 0x2e1b
-#define mmCOMPUTE_RESTART_Y 0x2e1c
-#define mmCOMPUTE_RESTART_Z 0x2e1d
-#define mmCOMPUTE_THREAD_TRACE_ENABLE 0x2e1e
-#define mmCOMPUTE_MISC_RESERVED 0x2e1f
-#define mmCOMPUTE_DISPATCH_ID 0x2e20
-#define mmCOMPUTE_THREADGROUP_ID 0x2e21
-#define mmCOMPUTE_RELAUNCH 0x2e22
-#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO 0x2e23
-#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI 0x2e24
-#define mmCOMPUTE_WAVE_RESTORE_CONTROL 0x2e25
-#define mmCOMPUTE_USER_DATA_0 0x2e40
-#define mmCOMPUTE_USER_DATA_1 0x2e41
-#define mmCOMPUTE_USER_DATA_2 0x2e42
-#define mmCOMPUTE_USER_DATA_3 0x2e43
-#define mmCOMPUTE_USER_DATA_4 0x2e44
-#define mmCOMPUTE_USER_DATA_5 0x2e45
-#define mmCOMPUTE_USER_DATA_6 0x2e46
-#define mmCOMPUTE_USER_DATA_7 0x2e47
-#define mmCOMPUTE_USER_DATA_8 0x2e48
-#define mmCOMPUTE_USER_DATA_9 0x2e49
-#define mmCOMPUTE_USER_DATA_10 0x2e4a
-#define mmCOMPUTE_USER_DATA_11 0x2e4b
-#define mmCOMPUTE_USER_DATA_12 0x2e4c
-#define mmCOMPUTE_USER_DATA_13 0x2e4d
-#define mmCOMPUTE_USER_DATA_14 0x2e4e
-#define mmCOMPUTE_USER_DATA_15 0x2e4f
-#define mmCOMPUTE_NOWHERE 0x2e7f
-#define mmCSPRIV_CONNECT 0x0
-#define mmCSPRIV_THREAD_TRACE_TG0 0x1e
-#define mmCSPRIV_THREAD_TRACE_TG1 0x1e
-#define mmCSPRIV_THREAD_TRACE_TG2 0x1e
-#define mmCSPRIV_THREAD_TRACE_TG3 0x1e
-#define mmCSPRIV_THREAD_TRACE_EVENT 0x1f
-#define mmRLC_CNTL 0xec00
-#define mmRLC_DEBUG_SELECT 0xec01
-#define mmRLC_DEBUG 0xec02
-#define mmRLC_MC_CNTL 0xec03
-#define mmRLC_STAT 0xec04
-#define mmRLC_SAFE_MODE 0xec05
-#define mmRLC_MEM_SLP_CNTL 0xec06
-#define mmSMU_RLC_RESPONSE 0xec07
-#define mmRLC_RLCV_SAFE_MODE 0xec08
-#define mmRLC_SMU_SAFE_MODE 0xec09
-#define mmRLC_RLCV_COMMAND 0xec0a
-#define mmRLC_CLK_CNTL 0xec0b
-#define mmRLC_PERFMON_CLK_CNTL 0xdcbf
-#define mmRLC_PERFMON_CNTL 0xdcc0
-#define mmRLC_PERFCOUNTER0_SELECT 0xdcc1
-#define mmRLC_PERFCOUNTER1_SELECT 0xdcc2
-#define mmRLC_PERFCOUNTER0_LO 0xd480
-#define mmRLC_PERFCOUNTER1_LO 0xd482
-#define mmRLC_PERFCOUNTER0_HI 0xd481
-#define mmRLC_PERFCOUNTER1_HI 0xd483
-#define mmCGTT_RLC_CLK_CTRL 0xf0b8
-#define mmRLC_LB_CNTL 0xec19
-#define mmRLC_LB_CNTR_MAX 0xec12
-#define mmRLC_LB_CNTR_INIT 0xec1b
-#define mmRLC_LOAD_BALANCE_CNTR 0xec1c
-#define mmRLC_JUMP_TABLE_RESTORE 0xec1e
-#define mmRLC_PG_DELAY_2 0xec1f
-#define mmRLC_GPM_DEBUG_SELECT 0xec20
-#define mmRLC_GPM_DEBUG 0xec21
-#define mmRLC_GPM_DEBUG_INST_A 0xec22
-#define mmRLC_GPM_DEBUG_INST_B 0xec23
-#define mmRLC_GPM_DEBUG_INST_ADDR 0xec1d
-#define mmRLC_GPM_UCODE_ADDR 0xf83c
-#define mmRLC_GPM_UCODE_DATA 0xf83d
-#define mmGPU_BIST_CONTROL 0xf835
-#define mmRLC_ROM_CNTL 0xf836
-#define mmRLC_GPU_CLOCK_COUNT_LSB 0xec24
-#define mmRLC_GPU_CLOCK_COUNT_MSB 0xec25
-#define mmRLC_CAPTURE_GPU_CLOCK_COUNT 0xec26
-#define mmRLC_UCODE_CNTL 0xec27
-#define mmRLC_GPM_STAT 0xec40
-#define mmRLC_GPU_CLOCK_32_RES_SEL 0xec41
-#define mmRLC_GPU_CLOCK_32 0xec42
-#define mmRLC_PG_CNTL 0xec43
-#define mmRLC_GPM_THREAD_PRIORITY 0xec44
-#define mmRLC_GPM_THREAD_ENABLE 0xec45
-#define mmRLC_GPM_VMID_THREAD0 0xec46
-#define mmRLC_GPM_VMID_THREAD1 0xec47
-#define mmRLC_CGTT_MGCG_OVERRIDE 0xec48
-#define mmRLC_CGCG_CGLS_CTRL 0xec49
-#define mmRLC_CGCG_RAMP_CTRL 0xec4a
-#define mmRLC_DYN_PG_STATUS 0xec4b
-#define mmRLC_DYN_PG_REQUEST 0xec4c
-#define mmRLC_PG_DELAY 0xec4d
-#define mmRLC_CU_STATUS 0xec4e
-#define mmRLC_LB_INIT_CU_MASK 0xec4f
-#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK 0xec50
-#define mmRLC_LB_PARAMS 0xec51
-#define mmRLC_THREAD1_DELAY 0xec52
-#define mmRLC_PG_ALWAYS_ON_CU_MASK 0xec53
-#define mmRLC_MAX_PG_CU 0xec54
-#define mmRLC_AUTO_PG_CTRL 0xec55
-#define mmRLC_SMU_GRBM_REG_SAVE_CTRL 0xec56
-#define mmRLC_SERDES_RD_MASTER_INDEX 0xec59
-#define mmRLC_SERDES_RD_DATA_0 0xec5a
-#define mmRLC_SERDES_RD_DATA_1 0xec5b
-#define mmRLC_SERDES_RD_DATA_2 0xec5c
-#define mmRLC_SERDES_WR_CU_MASTER_MASK 0xec5d
-#define mmRLC_SERDES_WR_NONCU_MASTER_MASK 0xec5e
-#define mmRLC_SERDES_WR_CTRL 0xec5f
-#define mmRLC_SERDES_WR_DATA 0xec60
-#define mmRLC_SERDES_CU_MASTER_BUSY 0xec61
-#define mmRLC_SERDES_NONCU_MASTER_BUSY 0xec62
-#define mmRLC_GPM_GENERAL_0 0xec63
-#define mmRLC_GPM_GENERAL_1 0xec64
-#define mmRLC_GPM_GENERAL_2 0xec65
-#define mmRLC_GPM_GENERAL_3 0xec66
-#define mmRLC_GPM_GENERAL_4 0xec67
-#define mmRLC_GPM_GENERAL_5 0xec68
-#define mmRLC_GPM_GENERAL_6 0xec69
-#define mmRLC_GPM_GENERAL_7 0xec6a
-#define mmRLC_GPM_SCRATCH_ADDR 0xec6c
-#define mmRLC_GPM_SCRATCH_DATA 0xec6d
-#define mmRLC_STATIC_PG_STATUS 0xec6e
-#define mmRLC_GPM_PERF_COUNT_0 0xec6f
-#define mmRLC_GPM_PERF_COUNT_1 0xec70
-#define mmRLC_GPR_REG1 0xec79
-#define mmRLC_GPR_REG2 0xec7a
-#define mmRLC_MGCG_CTRL 0xec1a
-#define mmRLC_GPM_THREAD_RESET 0xec28
-#define mmRLC_SPM_VMID 0xec71
-#define mmRLC_SPM_INT_CNTL 0xec72
-#define mmRLC_SPM_INT_STATUS 0xec73
-#define mmRLC_SPM_DEBUG_SELECT 0xec74
-#define mmRLC_SPM_DEBUG 0xec75
-#define mmRLC_SMU_MESSAGE 0xec76
-#define mmRLC_GPM_LOG_SIZE 0xec77
-#define mmRLC_GPM_LOG_CONT 0xec7b
-#define mmRLC_PG_DELAY_3 0xec78
-#define mmRLC_GPM_INT_DISABLE_TH0 0xec7c
-#define mmRLC_GPM_INT_DISABLE_TH1 0xec7d
-#define mmRLC_GPM_INT_FORCE_TH0 0xec7e
-#define mmRLC_GPM_INT_FORCE_TH1 0xec7f
-#define mmRLC_SRM_CNTL 0xec80
-#define mmRLC_SRM_DEBUG_SELECT 0xec81
-#define mmRLC_SRM_DEBUG 0xec82
-#define mmRLC_SRM_ARAM_ADDR 0xec83
-#define mmRLC_SRM_ARAM_DATA 0xec84
-#define mmRLC_SRM_DRAM_ADDR 0xec85
-#define mmRLC_SRM_DRAM_DATA 0xec86
-#define mmRLC_SRM_GPM_COMMAND 0xec87
-#define mmRLC_SRM_GPM_COMMAND_STATUS 0xec88
-#define mmRLC_SRM_RLCV_COMMAND 0xec89
-#define mmRLC_SRM_RLCV_COMMAND_STATUS 0xec8a
-#define mmRLC_SRM_INDEX_CNTL_ADDR_0 0xec8b
-#define mmRLC_SRM_INDEX_CNTL_ADDR_1 0xec8c
-#define mmRLC_SRM_INDEX_CNTL_ADDR_2 0xec8d
-#define mmRLC_SRM_INDEX_CNTL_ADDR_3 0xec8e
-#define mmRLC_SRM_INDEX_CNTL_ADDR_4 0xec8f
-#define mmRLC_SRM_INDEX_CNTL_ADDR_5 0xec90
-#define mmRLC_SRM_INDEX_CNTL_ADDR_6 0xec91
-#define mmRLC_SRM_INDEX_CNTL_ADDR_7 0xec92
-#define mmRLC_SRM_INDEX_CNTL_DATA_0 0xec93
-#define mmRLC_SRM_INDEX_CNTL_DATA_1 0xec94
-#define mmRLC_SRM_INDEX_CNTL_DATA_2 0xec95
-#define mmRLC_SRM_INDEX_CNTL_DATA_3 0xec96
-#define mmRLC_SRM_INDEX_CNTL_DATA_4 0xec97
-#define mmRLC_SRM_INDEX_CNTL_DATA_5 0xec98
-#define mmRLC_SRM_INDEX_CNTL_DATA_6 0xec99
-#define mmRLC_SRM_INDEX_CNTL_DATA_7 0xec9a
-#define mmRLC_SRM_STAT 0xec9b
-#define mmRLC_SRM_GPM_ABORT 0xec9c
-#define mmRLC_CSIB_ADDR_LO 0xeca2
-#define mmRLC_CSIB_ADDR_HI 0xeca3
-#define mmRLC_CSIB_LENGTH 0xeca4
-#define mmRLC_CP_RESPONSE0 0xeca5
-#define mmRLC_CP_RESPONSE1 0xeca6
-#define mmRLC_CP_RESPONSE2 0xeca7
-#define mmRLC_CP_RESPONSE3 0xeca8
-#define mmRLC_SMU_COMMAND 0xeca9
-#define mmRLC_CP_SCHEDULERS 0xecaa
-#define mmRLC_SMU_ARGUMENT_1 0xecab
-#define mmRLC_SMU_ARGUMENT_2 0xecac
-#define mmRLC_GPM_GENERAL_8 0xecad
-#define mmRLC_GPM_GENERAL_9 0xecae
-#define mmRLC_GPM_GENERAL_10 0xecaf
-#define mmRLC_GPM_GENERAL_11 0xecb0
-#define mmRLC_GPM_GENERAL_12 0xecb1
-#define mmRLC_SPM_PERFMON_CNTL 0xdc80
-#define mmRLC_SPM_PERFMON_RING_BASE_LO 0xdc81
-#define mmRLC_SPM_PERFMON_RING_BASE_HI 0xdc82
-#define mmRLC_SPM_PERFMON_RING_SIZE 0xdc83
-#define mmRLC_SPM_PERFMON_SEGMENT_SIZE 0xdc84
-#define mmRLC_SPM_SE_MUXSEL_ADDR 0xdc85
-#define mmRLC_SPM_SE_MUXSEL_DATA 0xdc86
-#define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY 0xdc87
-#define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY 0xdc88
-#define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY 0xdc89
-#define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY 0xdc8a
-#define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY 0xdc8b
-#define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY 0xdc8c
-#define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY 0xdc8d
-#define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY 0xdc8e
-#define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY 0xdc90
-#define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY 0xdc91
-#define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY 0xdc92
-#define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY 0xdc93
-#define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY 0xdc94
-#define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY 0xdc95
-#define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY 0xdc96
-#define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY 0xdc97
-#define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY 0xdc98
-#define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY 0xdc9a
-#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR 0xdc9b
-#define mmRLC_SPM_GLOBAL_MUXSEL_DATA 0xdc9c
-#define mmRLC_SPM_RING_RDPTR 0xdc9d
-#define mmRLC_SPM_SEGMENT_THRESHOLD 0xdc9e
-#define mmRLC_GPU_IOV_VF_ENABLE 0xfb00
-#define mmRLC_GPU_IOV_RLC_RESPONSE 0xfb4d
-#define mmRLC_GPU_IOV_ACTIVE_FCN_ID 0xfb40
-#define mmSPI_PS_INPUT_CNTL_0 0xa191
-#define mmSPI_PS_INPUT_CNTL_1 0xa192
-#define mmSPI_PS_INPUT_CNTL_2 0xa193
-#define mmSPI_PS_INPUT_CNTL_3 0xa194
-#define mmSPI_PS_INPUT_CNTL_4 0xa195
-#define mmSPI_PS_INPUT_CNTL_5 0xa196
-#define mmSPI_PS_INPUT_CNTL_6 0xa197
-#define mmSPI_PS_INPUT_CNTL_7 0xa198
-#define mmSPI_PS_INPUT_CNTL_8 0xa199
-#define mmSPI_PS_INPUT_CNTL_9 0xa19a
-#define mmSPI_PS_INPUT_CNTL_10 0xa19b
-#define mmSPI_PS_INPUT_CNTL_11 0xa19c
-#define mmSPI_PS_INPUT_CNTL_12 0xa19d
-#define mmSPI_PS_INPUT_CNTL_13 0xa19e
-#define mmSPI_PS_INPUT_CNTL_14 0xa19f
-#define mmSPI_PS_INPUT_CNTL_15 0xa1a0
-#define mmSPI_PS_INPUT_CNTL_16 0xa1a1
-#define mmSPI_PS_INPUT_CNTL_17 0xa1a2
-#define mmSPI_PS_INPUT_CNTL_18 0xa1a3
-#define mmSPI_PS_INPUT_CNTL_19 0xa1a4
-#define mmSPI_PS_INPUT_CNTL_20 0xa1a5
-#define mmSPI_PS_INPUT_CNTL_21 0xa1a6
-#define mmSPI_PS_INPUT_CNTL_22 0xa1a7
-#define mmSPI_PS_INPUT_CNTL_23 0xa1a8
-#define mmSPI_PS_INPUT_CNTL_24 0xa1a9
-#define mmSPI_PS_INPUT_CNTL_25 0xa1aa
-#define mmSPI_PS_INPUT_CNTL_26 0xa1ab
-#define mmSPI_PS_INPUT_CNTL_27 0xa1ac
-#define mmSPI_PS_INPUT_CNTL_28 0xa1ad
-#define mmSPI_PS_INPUT_CNTL_29 0xa1ae
-#define mmSPI_PS_INPUT_CNTL_30 0xa1af
-#define mmSPI_PS_INPUT_CNTL_31 0xa1b0
-#define mmSPI_VS_OUT_CONFIG 0xa1b1
-#define mmSPI_PS_INPUT_ENA 0xa1b3
-#define mmSPI_PS_INPUT_ADDR 0xa1b4
-#define mmSPI_INTERP_CONTROL_0 0xa1b5
-#define mmSPI_PS_IN_CONTROL 0xa1b6
-#define mmSPI_BARYC_CNTL 0xa1b8
-#define mmSPI_TMPRING_SIZE 0xa1ba
-#define mmSPI_SHADER_POS_FORMAT 0xa1c3
-#define mmSPI_SHADER_Z_FORMAT 0xa1c4
-#define mmSPI_SHADER_COL_FORMAT 0xa1c5
-#define mmSPI_ARB_PRIORITY 0x31c0
-#define mmSPI_ARB_CYCLES_0 0x31c1
-#define mmSPI_ARB_CYCLES_1 0x31c2
-#define mmSPI_CDBG_SYS_GFX 0x31c3
-#define mmSPI_CDBG_SYS_HP3D 0x31c4
-#define mmSPI_CDBG_SYS_CS0 0x31c5
-#define mmSPI_CDBG_SYS_CS1 0x31c6
-#define mmSPI_WCL_PIPE_PERCENT_GFX 0x31c7
-#define mmSPI_WCL_PIPE_PERCENT_HP3D 0x31c8
-#define mmSPI_WCL_PIPE_PERCENT_CS0 0x31c9
-#define mmSPI_WCL_PIPE_PERCENT_CS1 0x31ca
-#define mmSPI_WCL_PIPE_PERCENT_CS2 0x31cb
-#define mmSPI_WCL_PIPE_PERCENT_CS3 0x31cc
-#define mmSPI_WCL_PIPE_PERCENT_CS4 0x31cd
-#define mmSPI_WCL_PIPE_PERCENT_CS5 0x31ce
-#define mmSPI_WCL_PIPE_PERCENT_CS6 0x31cf
-#define mmSPI_WCL_PIPE_PERCENT_CS7 0x31d0
-#define mmSPI_GDBG_WAVE_CNTL 0x31d1
-#define mmSPI_GDBG_TRAP_CONFIG 0x31d2
-#define mmSPI_GDBG_TRAP_MASK 0x31d3
-#define mmSPI_GDBG_TBA_LO 0x31d4
-#define mmSPI_GDBG_TBA_HI 0x31d5
-#define mmSPI_GDBG_TMA_LO 0x31d6
-#define mmSPI_GDBG_TMA_HI 0x31d7
-#define mmSPI_GDBG_TRAP_DATA0 0x31d8
-#define mmSPI_GDBG_TRAP_DATA1 0x31d9
-#define mmSPI_RESET_DEBUG 0x31da
-#define mmSPI_COMPUTE_QUEUE_RESET 0x31db
-#define mmSPI_RESOURCE_RESERVE_CU_0 0x31dc
-#define mmSPI_RESOURCE_RESERVE_CU_1 0x31dd
-#define mmSPI_RESOURCE_RESERVE_CU_2 0x31de
-#define mmSPI_RESOURCE_RESERVE_CU_3 0x31df
-#define mmSPI_RESOURCE_RESERVE_CU_4 0x31e0
-#define mmSPI_RESOURCE_RESERVE_CU_5 0x31e1
-#define mmSPI_RESOURCE_RESERVE_CU_6 0x31e2
-#define mmSPI_RESOURCE_RESERVE_CU_7 0x31e3
-#define mmSPI_RESOURCE_RESERVE_CU_8 0x31e4
-#define mmSPI_RESOURCE_RESERVE_CU_9 0x31e5
-#define mmSPI_RESOURCE_RESERVE_CU_10 0x31f0
-#define mmSPI_RESOURCE_RESERVE_CU_11 0x31f1
-#define mmSPI_RESOURCE_RESERVE_CU_12 0x31f4
-#define mmSPI_RESOURCE_RESERVE_CU_13 0x31f5
-#define mmSPI_RESOURCE_RESERVE_CU_14 0x31f6
-#define mmSPI_RESOURCE_RESERVE_CU_15 0x31f7
-#define mmSPI_RESOURCE_RESERVE_EN_CU_0 0x31e6
-#define mmSPI_RESOURCE_RESERVE_EN_CU_1 0x31e7
-#define mmSPI_RESOURCE_RESERVE_EN_CU_2 0x31e8
-#define mmSPI_RESOURCE_RESERVE_EN_CU_3 0x31e9
-#define mmSPI_RESOURCE_RESERVE_EN_CU_4 0x31ea
-#define mmSPI_RESOURCE_RESERVE_EN_CU_5 0x31eb
-#define mmSPI_RESOURCE_RESERVE_EN_CU_6 0x31ec
-#define mmSPI_RESOURCE_RESERVE_EN_CU_7 0x31ed
-#define mmSPI_RESOURCE_RESERVE_EN_CU_8 0x31ee
-#define mmSPI_RESOURCE_RESERVE_EN_CU_9 0x31ef
-#define mmSPI_RESOURCE_RESERVE_EN_CU_10 0x31f2
-#define mmSPI_RESOURCE_RESERVE_EN_CU_11 0x31f3
-#define mmSPI_RESOURCE_RESERVE_EN_CU_12 0x31f8
-#define mmSPI_RESOURCE_RESERVE_EN_CU_13 0x31f9
-#define mmSPI_RESOURCE_RESERVE_EN_CU_14 0x31fa
-#define mmSPI_RESOURCE_RESERVE_EN_CU_15 0x31fb
-#define mmSPI_COMPUTE_WF_CTX_SAVE 0x31fc
-#define mmSPI_PS_MAX_WAVE_ID 0x243a
-#define mmSPI_START_PHASE 0x243b
-#define mmSPI_GFX_CNTL 0x243c
-#define mmSPI_CONFIG_CNTL 0x2440
-#define mmSPI_DEBUG_CNTL 0x2441
-#define mmSPI_DEBUG_READ 0x2442
-#define mmSPI_DSM_CNTL 0x2443
-#define mmSPI_EDC_CNT 0x2444
-#define mmSPI_PERFCOUNTER0_SELECT 0xd980
-#define mmSPI_PERFCOUNTER1_SELECT 0xd981
-#define mmSPI_PERFCOUNTER2_SELECT 0xd982
-#define mmSPI_PERFCOUNTER3_SELECT 0xd983
-#define mmSPI_PERFCOUNTER0_SELECT1 0xd984
-#define mmSPI_PERFCOUNTER1_SELECT1 0xd985
-#define mmSPI_PERFCOUNTER2_SELECT1 0xd986
-#define mmSPI_PERFCOUNTER3_SELECT1 0xd987
-#define mmSPI_PERFCOUNTER4_SELECT 0xd988
-#define mmSPI_PERFCOUNTER5_SELECT 0xd989
-#define mmSPI_PERFCOUNTER_BINS 0xd98a
-#define mmSPI_PERFCOUNTER0_HI 0xd180
-#define mmSPI_PERFCOUNTER0_LO 0xd181
-#define mmSPI_PERFCOUNTER1_HI 0xd182
-#define mmSPI_PERFCOUNTER1_LO 0xd183
-#define mmSPI_PERFCOUNTER2_HI 0xd184
-#define mmSPI_PERFCOUNTER2_LO 0xd185
-#define mmSPI_PERFCOUNTER3_HI 0xd186
-#define mmSPI_PERFCOUNTER3_LO 0xd187
-#define mmSPI_PERFCOUNTER4_HI 0xd188
-#define mmSPI_PERFCOUNTER4_LO 0xd189
-#define mmSPI_PERFCOUNTER5_HI 0xd18a
-#define mmSPI_PERFCOUNTER5_LO 0xd18b
-#define mmSPI_CONFIG_CNTL_1 0x244f
-#define mmSPI_DEBUG_BUSY 0x2450
-#define mmSPI_CONFIG_CNTL_2 0x2451
-#define mmCGTS_SM_CTRL_REG 0xf000
-#define mmCGTS_RD_CTRL_REG 0xf001
-#define mmCGTS_RD_REG 0xf002
-#define mmCGTS_TCC_DISABLE 0xf003
-#define mmCGTS_USER_TCC_DISABLE 0xf004
-#define mmCGTS_CU0_SP0_CTRL_REG 0xf008
-#define mmCGTS_CU0_LDS_SQ_CTRL_REG 0xf009
-#define mmCGTS_CU0_TA_SQC_CTRL_REG 0xf00a
-#define mmCGTS_CU0_SP1_CTRL_REG 0xf00b
-#define mmCGTS_CU0_TD_TCP_CTRL_REG 0xf00c
-#define mmCGTS_CU1_SP0_CTRL_REG 0xf00d
-#define mmCGTS_CU1_LDS_SQ_CTRL_REG 0xf00e
-#define mmCGTS_CU1_TA_CTRL_REG 0xf00f
-#define mmCGTS_CU1_SP1_CTRL_REG 0xf010
-#define mmCGTS_CU1_TD_TCP_CTRL_REG 0xf011
-#define mmCGTS_CU2_SP0_CTRL_REG 0xf012
-#define mmCGTS_CU2_LDS_SQ_CTRL_REG 0xf013
-#define mmCGTS_CU2_TA_CTRL_REG 0xf014
-#define mmCGTS_CU2_SP1_CTRL_REG 0xf015
-#define mmCGTS_CU2_TD_TCP_CTRL_REG 0xf016
-#define mmCGTS_CU3_SP0_CTRL_REG 0xf017
-#define mmCGTS_CU3_LDS_SQ_CTRL_REG 0xf018
-#define mmCGTS_CU3_TA_CTRL_REG 0xf019
-#define mmCGTS_CU3_SP1_CTRL_REG 0xf01a
-#define mmCGTS_CU3_TD_TCP_CTRL_REG 0xf01b
-#define mmCGTS_CU4_SP0_CTRL_REG 0xf01c
-#define mmCGTS_CU4_LDS_SQ_CTRL_REG 0xf01d
-#define mmCGTS_CU4_TA_SQC_CTRL_REG 0xf01e
-#define mmCGTS_CU4_SP1_CTRL_REG 0xf01f
-#define mmCGTS_CU4_TD_TCP_CTRL_REG 0xf020
-#define mmCGTS_CU5_SP0_CTRL_REG 0xf021
-#define mmCGTS_CU5_LDS_SQ_CTRL_REG 0xf022
-#define mmCGTS_CU5_TA_CTRL_REG 0xf023
-#define mmCGTS_CU5_SP1_CTRL_REG 0xf024
-#define mmCGTS_CU5_TD_TCP_CTRL_REG 0xf025
-#define mmCGTS_CU6_SP0_CTRL_REG 0xf026
-#define mmCGTS_CU6_LDS_SQ_CTRL_REG 0xf027
-#define mmCGTS_CU6_TA_CTRL_REG 0xf028
-#define mmCGTS_CU6_SP1_CTRL_REG 0xf029
-#define mmCGTS_CU6_TD_TCP_CTRL_REG 0xf02a
-#define mmCGTS_CU7_SP0_CTRL_REG 0xf02b
-#define mmCGTS_CU7_LDS_SQ_CTRL_REG 0xf02c
-#define mmCGTS_CU7_TA_CTRL_REG 0xf02d
-#define mmCGTS_CU7_SP1_CTRL_REG 0xf02e
-#define mmCGTS_CU7_TD_TCP_CTRL_REG 0xf02f
-#define mmCGTS_CU8_SP0_CTRL_REG 0xf030
-#define mmCGTS_CU8_LDS_SQ_CTRL_REG 0xf031
-#define mmCGTS_CU8_TA_SQC_CTRL_REG 0xf032
-#define mmCGTS_CU8_SP1_CTRL_REG 0xf033
-#define mmCGTS_CU8_TD_TCP_CTRL_REG 0xf034
-#define mmCGTS_CU9_SP0_CTRL_REG 0xf035
-#define mmCGTS_CU9_LDS_SQ_CTRL_REG 0xf036
-#define mmCGTS_CU9_TA_CTRL_REG 0xf037
-#define mmCGTS_CU9_SP1_CTRL_REG 0xf038
-#define mmCGTS_CU9_TD_TCP_CTRL_REG 0xf039
-#define mmCGTS_CU10_SP0_CTRL_REG 0xf03a
-#define mmCGTS_CU10_LDS_SQ_CTRL_REG 0xf03b
-#define mmCGTS_CU10_TA_CTRL_REG 0xf03c
-#define mmCGTS_CU10_SP1_CTRL_REG 0xf03d
-#define mmCGTS_CU10_TD_TCP_CTRL_REG 0xf03e
-#define mmCGTS_CU11_SP0_CTRL_REG 0xf03f
-#define mmCGTS_CU11_LDS_SQ_CTRL_REG 0xf040
-#define mmCGTS_CU11_TA_CTRL_REG 0xf041
-#define mmCGTS_CU11_SP1_CTRL_REG 0xf042
-#define mmCGTS_CU11_TD_TCP_CTRL_REG 0xf043
-#define mmCGTS_CU12_SP0_CTRL_REG 0xf044
-#define mmCGTS_CU12_LDS_SQ_CTRL_REG 0xf045
-#define mmCGTS_CU12_TA_SQC_CTRL_REG 0xf046
-#define mmCGTS_CU12_SP1_CTRL_REG 0xf047
-#define mmCGTS_CU12_TD_TCP_CTRL_REG 0xf048
-#define mmCGTS_CU13_SP0_CTRL_REG 0xf049
-#define mmCGTS_CU13_LDS_SQ_CTRL_REG 0xf04a
-#define mmCGTS_CU13_TA_CTRL_REG 0xf04b
-#define mmCGTS_CU13_SP1_CTRL_REG 0xf04c
-#define mmCGTS_CU13_TD_TCP_CTRL_REG 0xf04d
-#define mmCGTS_CU14_SP0_CTRL_REG 0xf04e
-#define mmCGTS_CU14_LDS_SQ_CTRL_REG 0xf04f
-#define mmCGTS_CU14_TA_CTRL_REG 0xf050
-#define mmCGTS_CU14_SP1_CTRL_REG 0xf051
-#define mmCGTS_CU14_TD_TCP_CTRL_REG 0xf052
-#define mmCGTS_CU15_SP0_CTRL_REG 0xf053
-#define mmCGTS_CU15_LDS_SQ_CTRL_REG 0xf054
-#define mmCGTS_CU15_TA_CTRL_REG 0xf055
-#define mmCGTS_CU15_SP1_CTRL_REG 0xf056
-#define mmCGTS_CU15_TD_TCP_CTRL_REG 0xf057
-#define mmCGTT_SPI_CLK_CTRL 0xf080
-#define mmCGTT_PC_CLK_CTRL 0xf081
-#define mmCGTT_BCI_CLK_CTRL 0xf082
-#define mmSPI_WF_LIFETIME_CNTL 0x24aa
-#define mmSPI_WF_LIFETIME_LIMIT_0 0x24ab
-#define mmSPI_WF_LIFETIME_LIMIT_1 0x24ac
-#define mmSPI_WF_LIFETIME_LIMIT_2 0x24ad
-#define mmSPI_WF_LIFETIME_LIMIT_3 0x24ae
-#define mmSPI_WF_LIFETIME_LIMIT_4 0x24af
-#define mmSPI_WF_LIFETIME_LIMIT_5 0x24b0
-#define mmSPI_WF_LIFETIME_LIMIT_6 0x24b1
-#define mmSPI_WF_LIFETIME_LIMIT_7 0x24b2
-#define mmSPI_WF_LIFETIME_LIMIT_8 0x24b3
-#define mmSPI_WF_LIFETIME_LIMIT_9 0x24b4
-#define mmSPI_WF_LIFETIME_STATUS_0 0x24b5
-#define mmSPI_WF_LIFETIME_STATUS_1 0x24b6
-#define mmSPI_WF_LIFETIME_STATUS_2 0x24b7
-#define mmSPI_WF_LIFETIME_STATUS_3 0x24b8
-#define mmSPI_WF_LIFETIME_STATUS_4 0x24b9
-#define mmSPI_WF_LIFETIME_STATUS_5 0x24ba
-#define mmSPI_WF_LIFETIME_STATUS_6 0x24bb
-#define mmSPI_WF_LIFETIME_STATUS_7 0x24bc
-#define mmSPI_WF_LIFETIME_STATUS_8 0x24bd
-#define mmSPI_WF_LIFETIME_STATUS_9 0x24be
-#define mmSPI_WF_LIFETIME_STATUS_10 0x24bf
-#define mmSPI_WF_LIFETIME_STATUS_11 0x24c0
-#define mmSPI_WF_LIFETIME_STATUS_12 0x24c1
-#define mmSPI_WF_LIFETIME_STATUS_13 0x24c2
-#define mmSPI_WF_LIFETIME_STATUS_14 0x24c3
-#define mmSPI_WF_LIFETIME_STATUS_15 0x24c4
-#define mmSPI_WF_LIFETIME_STATUS_16 0x24c5
-#define mmSPI_WF_LIFETIME_STATUS_17 0x24c6
-#define mmSPI_WF_LIFETIME_STATUS_18 0x24c7
-#define mmSPI_WF_LIFETIME_STATUS_19 0x24c8
-#define mmSPI_WF_LIFETIME_STATUS_20 0x24c9
-#define mmSPI_WF_LIFETIME_DEBUG 0x24ca
-#define mmSPI_SLAVE_DEBUG_BUSY 0x24d3
-#define mmSPI_LB_CTR_CTRL 0x24d4
-#define mmSPI_LB_CU_MASK 0x24d5
-#define mmSPI_LB_DATA_REG 0x24d6
-#define mmSPI_PG_ENABLE_STATIC_CU_MASK 0x24d7
-#define mmSPI_GDS_CREDITS 0x24d8
-#define mmSPI_SX_EXPORT_BUFFER_SIZES 0x24d9
-#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES 0x24da
-#define mmSPI_CSQ_WF_ACTIVE_STATUS 0x24db
-#define mmSPI_CSQ_WF_ACTIVE_COUNT_0 0x24dc
-#define mmSPI_CSQ_WF_ACTIVE_COUNT_1 0x24dd
-#define mmSPI_CSQ_WF_ACTIVE_COUNT_2 0x24de
-#define mmSPI_CSQ_WF_ACTIVE_COUNT_3 0x24df
-#define mmSPI_CSQ_WF_ACTIVE_COUNT_4 0x24e0
-#define mmSPI_CSQ_WF_ACTIVE_COUNT_5 0x24e1
-#define mmSPI_CSQ_WF_ACTIVE_COUNT_6 0x24e2
-#define mmSPI_CSQ_WF_ACTIVE_COUNT_7 0x24e3
-#define mmBCI_DEBUG_READ 0x24eb
-#define mmSPI_P0_TRAP_SCREEN_PSBA_LO 0x24ec
-#define mmSPI_P0_TRAP_SCREEN_PSBA_HI 0x24ed
-#define mmSPI_P0_TRAP_SCREEN_PSMA_LO 0x24ee
-#define mmSPI_P0_TRAP_SCREEN_PSMA_HI 0x24ef
-#define mmSPI_P0_TRAP_SCREEN_GPR_MIN 0x24f0
-#define mmSPI_P1_TRAP_SCREEN_PSBA_LO 0x24f1
-#define mmSPI_P1_TRAP_SCREEN_PSBA_HI 0x24f2
-#define mmSPI_P1_TRAP_SCREEN_PSMA_LO 0x24f3
-#define mmSPI_P1_TRAP_SCREEN_PSMA_HI 0x24f4
-#define mmSPI_P1_TRAP_SCREEN_GPR_MIN 0x24f5
-#define mmSPI_SHADER_TBA_LO_PS 0x2c00
-#define mmSPI_SHADER_TBA_HI_PS 0x2c01
-#define mmSPI_SHADER_TMA_LO_PS 0x2c02
-#define mmSPI_SHADER_TMA_HI_PS 0x2c03
-#define mmSPI_SHADER_PGM_LO_PS 0x2c08
-#define mmSPI_SHADER_PGM_HI_PS 0x2c09
-#define mmSPI_SHADER_PGM_RSRC1_PS 0x2c0a
-#define mmSPI_SHADER_PGM_RSRC2_PS 0x2c0b
-#define mmSPI_SHADER_PGM_RSRC3_PS 0x2c07
-#define mmSPI_SHADER_USER_DATA_PS_0 0x2c0c
-#define mmSPI_SHADER_USER_DATA_PS_1 0x2c0d
-#define mmSPI_SHADER_USER_DATA_PS_2 0x2c0e
-#define mmSPI_SHADER_USER_DATA_PS_3 0x2c0f
-#define mmSPI_SHADER_USER_DATA_PS_4 0x2c10
-#define mmSPI_SHADER_USER_DATA_PS_5 0x2c11
-#define mmSPI_SHADER_USER_DATA_PS_6 0x2c12
-#define mmSPI_SHADER_USER_DATA_PS_7 0x2c13
-#define mmSPI_SHADER_USER_DATA_PS_8 0x2c14
-#define mmSPI_SHADER_USER_DATA_PS_9 0x2c15
-#define mmSPI_SHADER_USER_DATA_PS_10 0x2c16
-#define mmSPI_SHADER_USER_DATA_PS_11 0x2c17
-#define mmSPI_SHADER_USER_DATA_PS_12 0x2c18
-#define mmSPI_SHADER_USER_DATA_PS_13 0x2c19
-#define mmSPI_SHADER_USER_DATA_PS_14 0x2c1a
-#define mmSPI_SHADER_USER_DATA_PS_15 0x2c1b
-#define mmSPI_SHADER_TBA_LO_VS 0x2c40
-#define mmSPI_SHADER_TBA_HI_VS 0x2c41
-#define mmSPI_SHADER_TMA_LO_VS 0x2c42
-#define mmSPI_SHADER_TMA_HI_VS 0x2c43
-#define mmSPI_SHADER_PGM_LO_VS 0x2c48
-#define mmSPI_SHADER_PGM_HI_VS 0x2c49
-#define mmSPI_SHADER_PGM_RSRC1_VS 0x2c4a
-#define mmSPI_SHADER_PGM_RSRC2_VS 0x2c4b
-#define mmSPI_SHADER_PGM_RSRC3_VS 0x2c46
-#define mmSPI_SHADER_LATE_ALLOC_VS 0x2c47
-#define mmSPI_SHADER_USER_DATA_VS_0 0x2c4c
-#define mmSPI_SHADER_USER_DATA_VS_1 0x2c4d
-#define mmSPI_SHADER_USER_DATA_VS_2 0x2c4e
-#define mmSPI_SHADER_USER_DATA_VS_3 0x2c4f
-#define mmSPI_SHADER_USER_DATA_VS_4 0x2c50
-#define mmSPI_SHADER_USER_DATA_VS_5 0x2c51
-#define mmSPI_SHADER_USER_DATA_VS_6 0x2c52
-#define mmSPI_SHADER_USER_DATA_VS_7 0x2c53
-#define mmSPI_SHADER_USER_DATA_VS_8 0x2c54
-#define mmSPI_SHADER_USER_DATA_VS_9 0x2c55
-#define mmSPI_SHADER_USER_DATA_VS_10 0x2c56
-#define mmSPI_SHADER_USER_DATA_VS_11 0x2c57
-#define mmSPI_SHADER_USER_DATA_VS_12 0x2c58
-#define mmSPI_SHADER_USER_DATA_VS_13 0x2c59
-#define mmSPI_SHADER_USER_DATA_VS_14 0x2c5a
-#define mmSPI_SHADER_USER_DATA_VS_15 0x2c5b
-#define mmSPI_SHADER_PGM_RSRC2_ES_VS 0x2c7c
-#define mmSPI_SHADER_PGM_RSRC2_LS_VS 0x2c7d
-#define mmSPI_SHADER_TBA_LO_GS 0x2c80
-#define mmSPI_SHADER_TBA_HI_GS 0x2c81
-#define mmSPI_SHADER_TMA_LO_GS 0x2c82
-#define mmSPI_SHADER_TMA_HI_GS 0x2c83
-#define mmSPI_SHADER_PGM_LO_GS 0x2c88
-#define mmSPI_SHADER_PGM_HI_GS 0x2c89
-#define mmSPI_SHADER_PGM_RSRC1_GS 0x2c8a
-#define mmSPI_SHADER_PGM_RSRC2_GS 0x2c8b
-#define mmSPI_SHADER_PGM_RSRC3_GS 0x2c87
-#define mmSPI_SHADER_USER_DATA_GS_0 0x2c8c
-#define mmSPI_SHADER_USER_DATA_GS_1 0x2c8d
-#define mmSPI_SHADER_USER_DATA_GS_2 0x2c8e
-#define mmSPI_SHADER_USER_DATA_GS_3 0x2c8f
-#define mmSPI_SHADER_USER_DATA_GS_4 0x2c90
-#define mmSPI_SHADER_USER_DATA_GS_5 0x2c91
-#define mmSPI_SHADER_USER_DATA_GS_6 0x2c92
-#define mmSPI_SHADER_USER_DATA_GS_7 0x2c93
-#define mmSPI_SHADER_USER_DATA_GS_8 0x2c94
-#define mmSPI_SHADER_USER_DATA_GS_9 0x2c95
-#define mmSPI_SHADER_USER_DATA_GS_10 0x2c96
-#define mmSPI_SHADER_USER_DATA_GS_11 0x2c97
-#define mmSPI_SHADER_USER_DATA_GS_12 0x2c98
-#define mmSPI_SHADER_USER_DATA_GS_13 0x2c99
-#define mmSPI_SHADER_USER_DATA_GS_14 0x2c9a
-#define mmSPI_SHADER_USER_DATA_GS_15 0x2c9b
-#define mmSPI_SHADER_PGM_RSRC2_ES_GS 0x2cbc
-#define mmSPI_SHADER_TBA_LO_ES 0x2cc0
-#define mmSPI_SHADER_TBA_HI_ES 0x2cc1
-#define mmSPI_SHADER_TMA_LO_ES 0x2cc2
-#define mmSPI_SHADER_TMA_HI_ES 0x2cc3
-#define mmSPI_SHADER_PGM_LO_ES 0x2cc8
-#define mmSPI_SHADER_PGM_HI_ES 0x2cc9
-#define mmSPI_SHADER_PGM_RSRC1_ES 0x2cca
-#define mmSPI_SHADER_PGM_RSRC2_ES 0x2ccb
-#define mmSPI_SHADER_PGM_RSRC3_ES 0x2cc7
-#define mmSPI_SHADER_USER_DATA_ES_0 0x2ccc
-#define mmSPI_SHADER_USER_DATA_ES_1 0x2ccd
-#define mmSPI_SHADER_USER_DATA_ES_2 0x2cce
-#define mmSPI_SHADER_USER_DATA_ES_3 0x2ccf
-#define mmSPI_SHADER_USER_DATA_ES_4 0x2cd0
-#define mmSPI_SHADER_USER_DATA_ES_5 0x2cd1
-#define mmSPI_SHADER_USER_DATA_ES_6 0x2cd2
-#define mmSPI_SHADER_USER_DATA_ES_7 0x2cd3
-#define mmSPI_SHADER_USER_DATA_ES_8 0x2cd4
-#define mmSPI_SHADER_USER_DATA_ES_9 0x2cd5
-#define mmSPI_SHADER_USER_DATA_ES_10 0x2cd6
-#define mmSPI_SHADER_USER_DATA_ES_11 0x2cd7
-#define mmSPI_SHADER_USER_DATA_ES_12 0x2cd8
-#define mmSPI_SHADER_USER_DATA_ES_13 0x2cd9
-#define mmSPI_SHADER_USER_DATA_ES_14 0x2cda
-#define mmSPI_SHADER_USER_DATA_ES_15 0x2cdb
-#define mmSPI_SHADER_PGM_RSRC2_LS_ES 0x2cfd
-#define mmSPI_SHADER_TBA_LO_HS 0x2d00
-#define mmSPI_SHADER_TBA_HI_HS 0x2d01
-#define mmSPI_SHADER_TMA_LO_HS 0x2d02
-#define mmSPI_SHADER_TMA_HI_HS 0x2d03
-#define mmSPI_SHADER_PGM_LO_HS 0x2d08
-#define mmSPI_SHADER_PGM_HI_HS 0x2d09
-#define mmSPI_SHADER_PGM_RSRC1_HS 0x2d0a
-#define mmSPI_SHADER_PGM_RSRC2_HS 0x2d0b
-#define mmSPI_SHADER_PGM_RSRC3_HS 0x2d07
-#define mmSPI_SHADER_USER_DATA_HS_0 0x2d0c
-#define mmSPI_SHADER_USER_DATA_HS_1 0x2d0d
-#define mmSPI_SHADER_USER_DATA_HS_2 0x2d0e
-#define mmSPI_SHADER_USER_DATA_HS_3 0x2d0f
-#define mmSPI_SHADER_USER_DATA_HS_4 0x2d10
-#define mmSPI_SHADER_USER_DATA_HS_5 0x2d11
-#define mmSPI_SHADER_USER_DATA_HS_6 0x2d12
-#define mmSPI_SHADER_USER_DATA_HS_7 0x2d13
-#define mmSPI_SHADER_USER_DATA_HS_8 0x2d14
-#define mmSPI_SHADER_USER_DATA_HS_9 0x2d15
-#define mmSPI_SHADER_USER_DATA_HS_10 0x2d16
-#define mmSPI_SHADER_USER_DATA_HS_11 0x2d17
-#define mmSPI_SHADER_USER_DATA_HS_12 0x2d18
-#define mmSPI_SHADER_USER_DATA_HS_13 0x2d19
-#define mmSPI_SHADER_USER_DATA_HS_14 0x2d1a
-#define mmSPI_SHADER_USER_DATA_HS_15 0x2d1b
-#define mmSPI_SHADER_PGM_RSRC2_LS_HS 0x2d3d
-#define mmSPI_SHADER_TBA_LO_LS 0x2d40
-#define mmSPI_SHADER_TBA_HI_LS 0x2d41
-#define mmSPI_SHADER_TMA_LO_LS 0x2d42
-#define mmSPI_SHADER_TMA_HI_LS 0x2d43
-#define mmSPI_SHADER_PGM_LO_LS 0x2d48
-#define mmSPI_SHADER_PGM_HI_LS 0x2d49
-#define mmSPI_SHADER_PGM_RSRC1_LS 0x2d4a
-#define mmSPI_SHADER_PGM_RSRC2_LS 0x2d4b
-#define mmSPI_SHADER_PGM_RSRC3_LS 0x2d47
-#define mmSPI_SHADER_USER_DATA_LS_0 0x2d4c
-#define mmSPI_SHADER_USER_DATA_LS_1 0x2d4d
-#define mmSPI_SHADER_USER_DATA_LS_2 0x2d4e
-#define mmSPI_SHADER_USER_DATA_LS_3 0x2d4f
-#define mmSPI_SHADER_USER_DATA_LS_4 0x2d50
-#define mmSPI_SHADER_USER_DATA_LS_5 0x2d51
-#define mmSPI_SHADER_USER_DATA_LS_6 0x2d52
-#define mmSPI_SHADER_USER_DATA_LS_7 0x2d53
-#define mmSPI_SHADER_USER_DATA_LS_8 0x2d54
-#define mmSPI_SHADER_USER_DATA_LS_9 0x2d55
-#define mmSPI_SHADER_USER_DATA_LS_10 0x2d56
-#define mmSPI_SHADER_USER_DATA_LS_11 0x2d57
-#define mmSPI_SHADER_USER_DATA_LS_12 0x2d58
-#define mmSPI_SHADER_USER_DATA_LS_13 0x2d59
-#define mmSPI_SHADER_USER_DATA_LS_14 0x2d5a
-#define mmSPI_SHADER_USER_DATA_LS_15 0x2d5b
-#define mmSQ_CONFIG 0x2300
-#define mmSQC_CONFIG 0x2301
-#define mmSQC_CACHES 0xc348
-#define mmSQC_WRITEBACK 0xc349
-#define mmSQC_DSM_CNTL 0x230f
-#define mmSQ_RANDOM_WAVE_PRI 0x2303
-#define mmSQ_REG_CREDITS 0x2304
-#define mmSQ_FIFO_SIZES 0x2305
-#define mmSQ_DSM_CNTL 0x2306
-#define mmCC_GC_SHADER_RATE_CONFIG 0x2312
-#define mmGC_USER_SHADER_RATE_CONFIG 0x2313
-#define mmSQ_INTERRUPT_AUTO_MASK 0x2314
-#define mmSQ_INTERRUPT_MSG_CTRL 0x2315
-#define mmSQ_PERFCOUNTER_CTRL 0xd9e0
-#define mmSQ_PERFCOUNTER_MASK 0xd9e1
-#define mmSQ_PERFCOUNTER_CTRL2 0xd9e2
-#define mmCC_SQC_BANK_DISABLE 0x2307
-#define mmUSER_SQC_BANK_DISABLE 0x2308
-#define mmSQ_PERFCOUNTER0_LO 0xd1c0
-#define mmSQ_PERFCOUNTER1_LO 0xd1c2
-#define mmSQ_PERFCOUNTER2_LO 0xd1c4
-#define mmSQ_PERFCOUNTER3_LO 0xd1c6
-#define mmSQ_PERFCOUNTER4_LO 0xd1c8
-#define mmSQ_PERFCOUNTER5_LO 0xd1ca
-#define mmSQ_PERFCOUNTER6_LO 0xd1cc
-#define mmSQ_PERFCOUNTER7_LO 0xd1ce
-#define mmSQ_PERFCOUNTER8_LO 0xd1d0
-#define mmSQ_PERFCOUNTER9_LO 0xd1d2
-#define mmSQ_PERFCOUNTER10_LO 0xd1d4
-#define mmSQ_PERFCOUNTER11_LO 0xd1d6
-#define mmSQ_PERFCOUNTER12_LO 0xd1d8
-#define mmSQ_PERFCOUNTER13_LO 0xd1da
-#define mmSQ_PERFCOUNTER14_LO 0xd1dc
-#define mmSQ_PERFCOUNTER15_LO 0xd1de
-#define mmSQ_PERFCOUNTER0_HI 0xd1c1
-#define mmSQ_PERFCOUNTER1_HI 0xd1c3
-#define mmSQ_PERFCOUNTER2_HI 0xd1c5
-#define mmSQ_PERFCOUNTER3_HI 0xd1c7
-#define mmSQ_PERFCOUNTER4_HI 0xd1c9
-#define mmSQ_PERFCOUNTER5_HI 0xd1cb
-#define mmSQ_PERFCOUNTER6_HI 0xd1cd
-#define mmSQ_PERFCOUNTER7_HI 0xd1cf
-#define mmSQ_PERFCOUNTER8_HI 0xd1d1
-#define mmSQ_PERFCOUNTER9_HI 0xd1d3
-#define mmSQ_PERFCOUNTER10_HI 0xd1d5
-#define mmSQ_PERFCOUNTER11_HI 0xd1d7
-#define mmSQ_PERFCOUNTER12_HI 0xd1d9
-#define mmSQ_PERFCOUNTER13_HI 0xd1db
-#define mmSQ_PERFCOUNTER14_HI 0xd1dd
-#define mmSQ_PERFCOUNTER15_HI 0xd1df
-#define mmSQ_PERFCOUNTER0_SELECT 0xd9c0
-#define mmSQ_PERFCOUNTER1_SELECT 0xd9c1
-#define mmSQ_PERFCOUNTER2_SELECT 0xd9c2
-#define mmSQ_PERFCOUNTER3_SELECT 0xd9c3
-#define mmSQ_PERFCOUNTER4_SELECT 0xd9c4
-#define mmSQ_PERFCOUNTER5_SELECT 0xd9c5
-#define mmSQ_PERFCOUNTER6_SELECT 0xd9c6
-#define mmSQ_PERFCOUNTER7_SELECT 0xd9c7
-#define mmSQ_PERFCOUNTER8_SELECT 0xd9c8
-#define mmSQ_PERFCOUNTER9_SELECT 0xd9c9
-#define mmSQ_PERFCOUNTER10_SELECT 0xd9ca
-#define mmSQ_PERFCOUNTER11_SELECT 0xd9cb
-#define mmSQ_PERFCOUNTER12_SELECT 0xd9cc
-#define mmSQ_PERFCOUNTER13_SELECT 0xd9cd
-#define mmSQ_PERFCOUNTER14_SELECT 0xd9ce
-#define mmSQ_PERFCOUNTER15_SELECT 0xd9cf
-#define mmCGTT_SQ_CLK_CTRL 0xf08c
-#define mmCGTT_SQG_CLK_CTRL 0xf08d
-#define mmSQ_ALU_CLK_CTRL 0xf08e
-#define mmSQ_TEX_CLK_CTRL 0xf08f
-#define mmSQ_LDS_CLK_CTRL 0xf090
-#define mmSQ_POWER_THROTTLE 0xf091
-#define mmSQ_POWER_THROTTLE2 0xf092
-#define mmSQ_TIME_HI 0x237c
-#define mmSQ_TIME_LO 0x237d
-#define mmSQ_THREAD_TRACE_BASE 0xc330
-#define mmSQ_THREAD_TRACE_BASE2 0xc337
-#define mmSQ_THREAD_TRACE_SIZE 0xc331
-#define mmSQ_THREAD_TRACE_MASK 0xc332
-#define mmSQ_THREAD_TRACE_USERDATA_0 0xc340
-#define mmSQ_THREAD_TRACE_USERDATA_1 0xc341
-#define mmSQ_THREAD_TRACE_USERDATA_2 0xc342
-#define mmSQ_THREAD_TRACE_USERDATA_3 0xc343
-#define mmSQ_THREAD_TRACE_MODE 0xc336
-#define mmSQ_THREAD_TRACE_CTRL 0xc335
-#define mmSQ_THREAD_TRACE_TOKEN_MASK 0xc333
-#define mmSQ_THREAD_TRACE_TOKEN_MASK2 0xc338
-#define mmSQ_THREAD_TRACE_PERF_MASK 0xc334
-#define mmSQ_THREAD_TRACE_WPTR 0xc339
-#define mmSQ_THREAD_TRACE_STATUS 0xc33a
-#define mmSQ_THREAD_TRACE_CNTR 0x2390
-#define mmSQ_THREAD_TRACE_HIWATER 0xc33b
-#define mmSQ_LB_CTR_CTRL 0x2398
-#define mmSQ_LB_DATA_ALU_CYCLES 0x2399
-#define mmSQ_LB_DATA_TEX_CYCLES 0x239a
-#define mmSQ_LB_DATA_ALU_STALLS 0x239b
-#define mmSQ_LB_DATA_TEX_STALLS 0x239c
-#define mmSQC_EDC_CNT 0x23a0
-#define mmSQ_EDC_SEC_CNT 0x23a1
-#define mmSQ_EDC_DED_CNT 0x23a2
-#define mmSQ_EDC_INFO 0x23a3
-#define mmSQ_BUF_RSRC_WORD0 0x23c0
-#define mmSQ_BUF_RSRC_WORD1 0x23c1
-#define mmSQ_BUF_RSRC_WORD2 0x23c2
-#define mmSQ_BUF_RSRC_WORD3 0x23c3
-#define mmSQ_IMG_RSRC_WORD0 0x23c4
-#define mmSQ_IMG_RSRC_WORD1 0x23c5
-#define mmSQ_IMG_RSRC_WORD2 0x23c6
-#define mmSQ_IMG_RSRC_WORD3 0x23c7
-#define mmSQ_IMG_RSRC_WORD4 0x23c8
-#define mmSQ_IMG_RSRC_WORD5 0x23c9
-#define mmSQ_IMG_RSRC_WORD6 0x23ca
-#define mmSQ_IMG_RSRC_WORD7 0x23cb
-#define mmSQ_IMG_SAMP_WORD0 0x23cc
-#define mmSQ_IMG_SAMP_WORD1 0x23cd
-#define mmSQ_IMG_SAMP_WORD2 0x23ce
-#define mmSQ_IMG_SAMP_WORD3 0x23cf
-#define mmSQ_FLAT_SCRATCH_WORD0 0x23d0
-#define mmSQ_FLAT_SCRATCH_WORD1 0x23d1
-#define mmSQ_M0_GPR_IDX_WORD 0x23d2
-#define mmSQ_IND_INDEX 0x2378
-#define mmSQ_CMD 0x237b
-#define mmSQ_IND_DATA 0x2379
-#define mmSQ_REG_TIMESTAMP 0x2374
-#define mmSQ_CMD_TIMESTAMP 0x2375
-#define mmSQ_HV_VMID_CTRL 0xf840
-#define ixSQ_WAVE_INST_DW0 0x1a
-#define ixSQ_WAVE_INST_DW1 0x1b
-#define ixSQ_WAVE_PC_LO 0x18
-#define ixSQ_WAVE_PC_HI 0x19
-#define ixSQ_WAVE_IB_DBG0 0x1c
-#define ixSQ_WAVE_IB_DBG1 0x1d
-#define ixSQ_WAVE_EXEC_LO 0x27e
-#define ixSQ_WAVE_EXEC_HI 0x27f
-#define ixSQ_WAVE_STATUS 0x12
-#define ixSQ_WAVE_MODE 0x11
-#define ixSQ_WAVE_TRAPSTS 0x13
-#define ixSQ_WAVE_HW_ID 0x14
-#define ixSQ_WAVE_GPR_ALLOC 0x15
-#define ixSQ_WAVE_LDS_ALLOC 0x16
-#define ixSQ_WAVE_IB_STS 0x17
-#define ixSQ_WAVE_M0 0x27c
-#define ixSQ_WAVE_TBA_LO 0x26c
-#define ixSQ_WAVE_TBA_HI 0x26d
-#define ixSQ_WAVE_TMA_LO 0x26e
-#define ixSQ_WAVE_TMA_HI 0x26f
-#define ixSQ_WAVE_TTMP0 0x270
-#define ixSQ_WAVE_TTMP1 0x271
-#define ixSQ_WAVE_TTMP2 0x272
-#define ixSQ_WAVE_TTMP3 0x273
-#define ixSQ_WAVE_TTMP4 0x274
-#define ixSQ_WAVE_TTMP5 0x275
-#define ixSQ_WAVE_TTMP6 0x276
-#define ixSQ_WAVE_TTMP7 0x277
-#define ixSQ_WAVE_TTMP8 0x278
-#define ixSQ_WAVE_TTMP9 0x279
-#define ixSQ_WAVE_TTMP10 0x27a
-#define ixSQ_WAVE_TTMP11 0x27b
-#define mmSQ_DEBUG_STS_GLOBAL 0x2309
-#define mmSQ_DEBUG_STS_GLOBAL2 0x2310
-#define mmSQ_DEBUG_STS_GLOBAL3 0x2311
-#define ixSQ_DEBUG_STS_LOCAL 0x8
-#define ixSQ_DEBUG_CTRL_LOCAL 0x9
-#define mmSH_MEM_BASES 0x230a
-#define mmSH_MEM_APE1_BASE 0x230b
-#define mmSH_MEM_APE1_LIMIT 0x230c
-#define mmSH_MEM_CONFIG 0x230d
-#define mmSQ_THREAD_TRACE_WORD_CMN 0x23b0
-#define mmSQ_THREAD_TRACE_WORD_INST 0x23b0
-#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0x23b0
-#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 0x23b1
-#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0x23b0
-#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 0x23b1
-#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 0x23b0
-#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 0x23b1
-#define mmSQ_THREAD_TRACE_WORD_WAVE 0x23b0
-#define mmSQ_THREAD_TRACE_WORD_MISC 0x23b0
-#define mmSQ_THREAD_TRACE_WORD_WAVE_START 0x23b0
-#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2 0x23b0
-#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2 0x23b0
-#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 0x23b0
-#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 0x23b0
-#define mmSQ_THREAD_TRACE_WORD_EVENT 0x23b0
-#define mmSQ_THREAD_TRACE_WORD_ISSUE 0x23b0
-#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0x23b0
-#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2 0x23b1
-#define mmSQ_WREXEC_EXEC_LO 0x23b1
-#define mmSQ_WREXEC_EXEC_HI 0x23b1
-#define mmSQC_GATCL1_CNTL 0x23b2
-#define mmSQC_ATC_EDC_GATCL1_CNT 0x23b3
-#define ixSQ_INTERRUPT_WORD_CMN 0x20c0
-#define ixSQ_INTERRUPT_WORD_AUTO 0x20c0
-#define ixSQ_INTERRUPT_WORD_WAVE 0x20c0
-#define mmSQ_SOP2 0x237f
-#define mmSQ_VOP1 0x237f
-#define mmSQ_MTBUF_1 0x237f
-#define mmSQ_EXP_1 0x237f
-#define mmSQ_MUBUF_1 0x237f
-#define mmSQ_SMEM_1 0x237f
-#define mmSQ_INST 0x237f
-#define mmSQ_EXP_0 0x237f
-#define mmSQ_MUBUF_0 0x237f
-#define mmSQ_VOP_SDWA 0x237f
-#define mmSQ_VOP3_0 0x237f
-#define mmSQ_VOP2 0x237f
-#define mmSQ_MTBUF_0 0x237f
-#define mmSQ_SOPP 0x237f
-#define mmSQ_FLAT_0 0x237f
-#define mmSQ_VOP3_0_SDST_ENC 0x237f
-#define mmSQ_MIMG_1 0x237f
-#define mmSQ_SOP1 0x237f
-#define mmSQ_SOPC 0x237f
-#define mmSQ_FLAT_1 0x237f
-#define mmSQ_DS_1 0x237f
-#define mmSQ_VOP3_1 0x237f
-#define mmSQ_SMEM_0 0x237f
-#define mmSQ_MIMG_0 0x237f
-#define mmSQ_SOPK 0x237f
-#define mmSQ_DS_0 0x237f
-#define mmSQ_VOP_DPP 0x237f
-#define mmSQ_VOPC 0x237f
-#define mmSQ_VINTRP 0x237f
-#define mmCGTT_SX_CLK_CTRL0 0xf094
-#define mmCGTT_SX_CLK_CTRL1 0xf095
-#define mmCGTT_SX_CLK_CTRL2 0xf096
-#define mmCGTT_SX_CLK_CTRL3 0xf097
-#define mmCGTT_SX_CLK_CTRL4 0xf098
-#define mmSX_DEBUG_BUSY 0x2414
-#define mmSX_DEBUG_BUSY_2 0x2415
-#define mmSX_DEBUG_BUSY_3 0x2416
-#define mmSX_DEBUG_BUSY_4 0x2417
-#define mmSX_DEBUG_1 0x2418
-#define mmSX_PERFCOUNTER0_SELECT 0xda40
-#define mmSX_PERFCOUNTER1_SELECT 0xda41
-#define mmSX_PERFCOUNTER2_SELECT 0xda42
-#define mmSX_PERFCOUNTER3_SELECT 0xda43
-#define mmSX_PERFCOUNTER0_SELECT1 0xda44
-#define mmSX_PERFCOUNTER1_SELECT1 0xda45
-#define mmSX_PERFCOUNTER0_LO 0xd240
-#define mmSX_PERFCOUNTER0_HI 0xd241
-#define mmSX_PERFCOUNTER1_LO 0xd242
-#define mmSX_PERFCOUNTER1_HI 0xd243
-#define mmSX_PERFCOUNTER2_LO 0xd244
-#define mmSX_PERFCOUNTER2_HI 0xd245
-#define mmSX_PERFCOUNTER3_LO 0xd246
-#define mmSX_PERFCOUNTER3_HI 0xd247
-#define mmSX_PS_DOWNCONVERT 0xa1d5
-#define mmSX_BLEND_OPT_EPSILON 0xa1d6
-#define mmSX_BLEND_OPT_CONTROL 0xa1d7
-#define mmSX_MRT0_BLEND_OPT 0xa1d8
-#define mmSX_MRT1_BLEND_OPT 0xa1d9
-#define mmSX_MRT2_BLEND_OPT 0xa1da
-#define mmSX_MRT3_BLEND_OPT 0xa1db
-#define mmSX_MRT4_BLEND_OPT 0xa1dc
-#define mmSX_MRT5_BLEND_OPT 0xa1dd
-#define mmSX_MRT6_BLEND_OPT 0xa1de
-#define mmSX_MRT7_BLEND_OPT 0xa1df
-#define mmTCC_CTRL 0x2b80
-#define mmTCC_EDC_CNT 0x2b82
-#define mmTCC_REDUNDANCY 0x2b83
-#define mmTCC_EXE_DISABLE 0x2b84
-#define mmTCC_DSM_CNTL 0x2b85
-#define mmTCC_CGTT_SCLK_CTRL 0xf0ac
-#define mmTCA_CGTT_SCLK_CTRL 0xf0ad
-#define mmTCC_PERFCOUNTER0_SELECT 0xdb80
-#define mmTCC_PERFCOUNTER1_SELECT 0xdb82
-#define mmTCC_PERFCOUNTER0_SELECT1 0xdb81
-#define mmTCC_PERFCOUNTER1_SELECT1 0xdb83
-#define mmTCC_PERFCOUNTER2_SELECT 0xdb84
-#define mmTCC_PERFCOUNTER3_SELECT 0xdb85
-#define mmTCC_PERFCOUNTER0_LO 0xd380
-#define mmTCC_PERFCOUNTER1_LO 0xd382
-#define mmTCC_PERFCOUNTER2_LO 0xd384
-#define mmTCC_PERFCOUNTER3_LO 0xd386
-#define mmTCC_PERFCOUNTER0_HI 0xd381
-#define mmTCC_PERFCOUNTER1_HI 0xd383
-#define mmTCC_PERFCOUNTER2_HI 0xd385
-#define mmTCC_PERFCOUNTER3_HI 0xd387
-#define mmTCA_CTRL 0x2bc0
-#define mmTCA_PERFCOUNTER0_SELECT 0xdb90
-#define mmTCA_PERFCOUNTER1_SELECT 0xdb92
-#define mmTCA_PERFCOUNTER0_SELECT1 0xdb91
-#define mmTCA_PERFCOUNTER1_SELECT1 0xdb93
-#define mmTCA_PERFCOUNTER2_SELECT 0xdb94
-#define mmTCA_PERFCOUNTER3_SELECT 0xdb95
-#define mmTCA_PERFCOUNTER0_LO 0xd390
-#define mmTCA_PERFCOUNTER1_LO 0xd392
-#define mmTCA_PERFCOUNTER2_LO 0xd394
-#define mmTCA_PERFCOUNTER3_LO 0xd396
-#define mmTCA_PERFCOUNTER0_HI 0xd391
-#define mmTCA_PERFCOUNTER1_HI 0xd393
-#define mmTCA_PERFCOUNTER2_HI 0xd395
-#define mmTCA_PERFCOUNTER3_HI 0xd397
-#define mmTA_BC_BASE_ADDR 0xa020
-#define mmTA_BC_BASE_ADDR_HI 0xa021
-#define mmTD_CNTL 0x2525
-#define mmTD_STATUS 0x2526
-#define mmTD_DEBUG_INDEX 0x2528
-#define mmTD_DEBUG_DATA 0x2529
-#define mmTD_DSM_CNTL 0x252f
-#define mmTD_PERFCOUNTER0_SELECT 0xdb00
-#define mmTD_PERFCOUNTER1_SELECT 0xdb02
-#define mmTD_PERFCOUNTER0_SELECT1 0xdb01
-#define mmTD_PERFCOUNTER0_LO 0xd300
-#define mmTD_PERFCOUNTER1_LO 0xd302
-#define mmTD_PERFCOUNTER0_HI 0xd301
-#define mmTD_PERFCOUNTER1_HI 0xd303
-#define mmTD_SCRATCH 0x2533
-#define mmTA_CNTL 0x2541
-#define mmTA_CNTL_AUX 0x2542
-#define mmTA_RESERVED_010C 0x2543
-#define mmTA_CS_BC_BASE_ADDR 0xc380
-#define mmTA_CS_BC_BASE_ADDR_HI 0xc381
-#define mmTA_STATUS 0x2548
-#define mmTA_DEBUG_INDEX 0x254c
-#define mmTA_DEBUG_DATA 0x254d
-#define mmTA_PERFCOUNTER0_SELECT 0xdac0
-#define mmTA_PERFCOUNTER1_SELECT 0xdac2
-#define mmTA_PERFCOUNTER0_SELECT1 0xdac1
-#define mmTA_PERFCOUNTER0_LO 0xd2c0
-#define mmTA_PERFCOUNTER1_LO 0xd2c2
-#define mmTA_PERFCOUNTER0_HI 0xd2c1
-#define mmTA_PERFCOUNTER1_HI 0xd2c3
-#define mmTA_SCRATCH 0x2564
-#define mmSH_HIDDEN_PRIVATE_BASE_VMID 0x2580
-#define mmSH_STATIC_MEM_CONFIG 0x2581
-#define mmTCP_INVALIDATE 0x2b00
-#define mmTCP_STATUS 0x2b01
-#define mmTCP_CNTL 0x2b02
-#define mmTCP_CHAN_STEER_LO 0x2b03
-#define mmTCP_CHAN_STEER_HI 0x2b04
-#define mmTCP_ADDR_CONFIG 0x2b05
-#define mmTCP_CREDIT 0x2b06
-#define mmTCP_PERFCOUNTER0_SELECT 0xdb40
-#define mmTCP_PERFCOUNTER1_SELECT 0xdb42
-#define mmTCP_PERFCOUNTER0_SELECT1 0xdb41
-#define mmTCP_PERFCOUNTER1_SELECT1 0xdb43
-#define mmTCP_PERFCOUNTER2_SELECT 0xdb44
-#define mmTCP_PERFCOUNTER3_SELECT 0xdb45
-#define mmTCP_PERFCOUNTER0_LO 0xd340
-#define mmTCP_PERFCOUNTER1_LO 0xd342
-#define mmTCP_PERFCOUNTER2_LO 0xd344
-#define mmTCP_PERFCOUNTER3_LO 0xd346
-#define mmTCP_PERFCOUNTER0_HI 0xd341
-#define mmTCP_PERFCOUNTER1_HI 0xd343
-#define mmTCP_PERFCOUNTER2_HI 0xd345
-#define mmTCP_PERFCOUNTER3_HI 0xd347
-#define mmTCP_BUFFER_ADDR_HASH_CNTL 0x2b16
-#define mmTCP_EDC_CNT 0x2b17
-#define mmTC_CFG_L1_LOAD_POLICY0 0x2b1a
-#define mmTC_CFG_L1_LOAD_POLICY1 0x2b1b
-#define mmTC_CFG_L1_STORE_POLICY 0x2b1c
-#define mmTC_CFG_L2_LOAD_POLICY0 0x2b1d
-#define mmTC_CFG_L2_LOAD_POLICY1 0x2b1e
-#define mmTC_CFG_L2_STORE_POLICY0 0x2b1f
-#define mmTC_CFG_L2_STORE_POLICY1 0x2b20
-#define mmTC_CFG_L2_ATOMIC_POLICY 0x2b21
-#define mmTC_CFG_L1_VOLATILE 0x2b22
-#define mmTC_CFG_L2_VOLATILE 0x2b23
-#define mmTCP_WATCH0_ADDR_H 0x32a0
-#define mmTCP_WATCH1_ADDR_H 0x32a3
-#define mmTCP_WATCH2_ADDR_H 0x32a6
-#define mmTCP_WATCH3_ADDR_H 0x32a9
-#define mmTCP_WATCH0_ADDR_L 0x32a1
-#define mmTCP_WATCH1_ADDR_L 0x32a4
-#define mmTCP_WATCH2_ADDR_L 0x32a7
-#define mmTCP_WATCH3_ADDR_L 0x32aa
-#define mmTCP_WATCH0_CNTL 0x32a2
-#define mmTCP_WATCH1_CNTL 0x32a5
-#define mmTCP_WATCH2_CNTL 0x32a8
-#define mmTCP_WATCH3_CNTL 0x32ab
-#define mmTCP_GATCL1_CNTL 0x32b0
-#define mmTCP_ATC_EDC_GATCL1_CNT 0x32b1
-#define mmTCP_GATCL1_DSM_CNTL 0x32b2
-#define mmTCP_DSM_CNTL 0x32b3
-#define mmTCP_CNTL2 0x32b4
-#define mmTD_CGTT_CTRL 0xf09c
-#define mmTA_CGTT_CTRL 0xf09d
-#define mmCGTT_TCP_CLK_CTRL 0xf09e
-#define mmCGTT_TCI_CLK_CTRL 0xf09f
-#define mmTCI_STATUS 0x2b61
-#define mmTCI_CNTL_1 0x2b62
-#define mmTCI_CNTL_2 0x2b63
-#define mmGDS_CONFIG 0x25c0
-#define mmGDS_CNTL_STATUS 0x25c1
-#define mmGDS_ENHANCE2 0x25c2
-#define mmGDS_PROTECTION_FAULT 0x25c3
-#define mmGDS_VM_PROTECTION_FAULT 0x25c4
-#define mmGDS_EDC_CNT 0x25c5
-#define mmGDS_EDC_GRBM_CNT 0x25c6
-#define mmGDS_EDC_OA_DED 0x25c7
-#define mmGDS_DEBUG_CNTL 0x25c8
-#define mmGDS_DEBUG_DATA 0x25c9
-#define mmGDS_DSM_CNTL 0x25ca
-#define mmCGTT_GDS_CLK_CTRL 0xf0a0
-#define mmGDS_RD_ADDR 0xc400
-#define mmGDS_RD_DATA 0xc401
-#define mmGDS_RD_BURST_ADDR 0xc402
-#define mmGDS_RD_BURST_COUNT 0xc403
-#define mmGDS_RD_BURST_DATA 0xc404
-#define mmGDS_WR_ADDR 0xc405
-#define mmGDS_WR_DATA 0xc406
-#define mmGDS_WR_BURST_ADDR 0xc407
-#define mmGDS_WR_BURST_DATA 0xc408
-#define mmGDS_WRITE_COMPLETE 0xc409
-#define mmGDS_ATOM_CNTL 0xc40a
-#define mmGDS_ATOM_COMPLETE 0xc40b
-#define mmGDS_ATOM_BASE 0xc40c
-#define mmGDS_ATOM_SIZE 0xc40d
-#define mmGDS_ATOM_OFFSET0 0xc40e
-#define mmGDS_ATOM_OFFSET1 0xc40f
-#define mmGDS_ATOM_DST 0xc410
-#define mmGDS_ATOM_OP 0xc411
-#define mmGDS_ATOM_SRC0 0xc412
-#define mmGDS_ATOM_SRC0_U 0xc413
-#define mmGDS_ATOM_SRC1 0xc414
-#define mmGDS_ATOM_SRC1_U 0xc415
-#define mmGDS_ATOM_READ0 0xc416
-#define mmGDS_ATOM_READ0_U 0xc417
-#define mmGDS_ATOM_READ1 0xc418
-#define mmGDS_ATOM_READ1_U 0xc419
-#define mmGDS_GWS_RESOURCE_CNTL 0xc41a
-#define mmGDS_GWS_RESOURCE 0xc41b
-#define mmGDS_GWS_RESOURCE_CNT 0xc41c
-#define mmGDS_OA_CNTL 0xc41d
-#define mmGDS_OA_COUNTER 0xc41e
-#define mmGDS_OA_ADDRESS 0xc41f
-#define mmGDS_OA_INCDEC 0xc420
-#define mmGDS_OA_RING_SIZE 0xc421
-#define ixGDS_DEBUG_REG0 0x0
-#define ixGDS_DEBUG_REG1 0x1
-#define ixGDS_DEBUG_REG2 0x2
-#define ixGDS_DEBUG_REG3 0x3
-#define ixGDS_DEBUG_REG4 0x4
-#define ixGDS_DEBUG_REG5 0x5
-#define ixGDS_DEBUG_REG6 0x6
-#define mmGDS_PERFCOUNTER0_SELECT 0xda80
-#define mmGDS_PERFCOUNTER1_SELECT 0xda81
-#define mmGDS_PERFCOUNTER2_SELECT 0xda82
-#define mmGDS_PERFCOUNTER3_SELECT 0xda83
-#define mmGDS_PERFCOUNTER0_LO 0xd280
-#define mmGDS_PERFCOUNTER1_LO 0xd282
-#define mmGDS_PERFCOUNTER2_LO 0xd284
-#define mmGDS_PERFCOUNTER3_LO 0xd286
-#define mmGDS_PERFCOUNTER0_HI 0xd281
-#define mmGDS_PERFCOUNTER1_HI 0xd283
-#define mmGDS_PERFCOUNTER2_HI 0xd285
-#define mmGDS_PERFCOUNTER3_HI 0xd287
-#define mmGDS_PERFCOUNTER0_SELECT1 0xda84
-#define mmGDS_VMID0_BASE 0x3300
-#define mmGDS_VMID1_BASE 0x3302
-#define mmGDS_VMID2_BASE 0x3304
-#define mmGDS_VMID3_BASE 0x3306
-#define mmGDS_VMID4_BASE 0x3308
-#define mmGDS_VMID5_BASE 0x330a
-#define mmGDS_VMID6_BASE 0x330c
-#define mmGDS_VMID7_BASE 0x330e
-#define mmGDS_VMID8_BASE 0x3310
-#define mmGDS_VMID9_BASE 0x3312
-#define mmGDS_VMID10_BASE 0x3314
-#define mmGDS_VMID11_BASE 0x3316
-#define mmGDS_VMID12_BASE 0x3318
-#define mmGDS_VMID13_BASE 0x331a
-#define mmGDS_VMID14_BASE 0x331c
-#define mmGDS_VMID15_BASE 0x331e
-#define mmGDS_VMID0_SIZE 0x3301
-#define mmGDS_VMID1_SIZE 0x3303
-#define mmGDS_VMID2_SIZE 0x3305
-#define mmGDS_VMID3_SIZE 0x3307
-#define mmGDS_VMID4_SIZE 0x3309
-#define mmGDS_VMID5_SIZE 0x330b
-#define mmGDS_VMID6_SIZE 0x330d
-#define mmGDS_VMID7_SIZE 0x330f
-#define mmGDS_VMID8_SIZE 0x3311
-#define mmGDS_VMID9_SIZE 0x3313
-#define mmGDS_VMID10_SIZE 0x3315
-#define mmGDS_VMID11_SIZE 0x3317
-#define mmGDS_VMID12_SIZE 0x3319
-#define mmGDS_VMID13_SIZE 0x331b
-#define mmGDS_VMID14_SIZE 0x331d
-#define mmGDS_VMID15_SIZE 0x331f
-#define mmGDS_GWS_VMID0 0x3320
-#define mmGDS_GWS_VMID1 0x3321
-#define mmGDS_GWS_VMID2 0x3322
-#define mmGDS_GWS_VMID3 0x3323
-#define mmGDS_GWS_VMID4 0x3324
-#define mmGDS_GWS_VMID5 0x3325
-#define mmGDS_GWS_VMID6 0x3326
-#define mmGDS_GWS_VMID7 0x3327
-#define mmGDS_GWS_VMID8 0x3328
-#define mmGDS_GWS_VMID9 0x3329
-#define mmGDS_GWS_VMID10 0x332a
-#define mmGDS_GWS_VMID11 0x332b
-#define mmGDS_GWS_VMID12 0x332c
-#define mmGDS_GWS_VMID13 0x332d
-#define mmGDS_GWS_VMID14 0x332e
-#define mmGDS_GWS_VMID15 0x332f
-#define mmGDS_OA_VMID0 0x3330
-#define mmGDS_OA_VMID1 0x3331
-#define mmGDS_OA_VMID2 0x3332
-#define mmGDS_OA_VMID3 0x3333
-#define mmGDS_OA_VMID4 0x3334
-#define mmGDS_OA_VMID5 0x3335
-#define mmGDS_OA_VMID6 0x3336
-#define mmGDS_OA_VMID7 0x3337
-#define mmGDS_OA_VMID8 0x3338
-#define mmGDS_OA_VMID9 0x3339
-#define mmGDS_OA_VMID10 0x333a
-#define mmGDS_OA_VMID11 0x333b
-#define mmGDS_OA_VMID12 0x333c
-#define mmGDS_OA_VMID13 0x333d
-#define mmGDS_OA_VMID14 0x333e
-#define mmGDS_OA_VMID15 0x333f
-#define mmGDS_GWS_RESET0 0x3344
-#define mmGDS_GWS_RESET1 0x3345
-#define mmGDS_GWS_RESOURCE_RESET 0x3346
-#define mmGDS_COMPUTE_MAX_WAVE_ID 0x3348
-#define mmGDS_OA_RESET_MASK 0x3349
-#define mmGDS_OA_RESET 0x334a
-#define mmGDS_ENHANCE 0x334b
-#define mmGDS_OA_CGPG_RESTORE 0x334c
-#define mmGDS_CS_CTXSW_STATUS 0x334d
-#define mmGDS_CS_CTXSW_CNT0 0x334e
-#define mmGDS_CS_CTXSW_CNT1 0x334f
-#define mmGDS_CS_CTXSW_CNT2 0x3350
-#define mmGDS_CS_CTXSW_CNT3 0x3351
-#define mmGDS_GFX_CTXSW_STATUS 0x3352
-#define mmGDS_VS_CTXSW_CNT0 0x3353
-#define mmGDS_VS_CTXSW_CNT1 0x3354
-#define mmGDS_VS_CTXSW_CNT2 0x3355
-#define mmGDS_VS_CTXSW_CNT3 0x3356
-#define mmGDS_PS0_CTXSW_CNT0 0x3357
-#define mmGDS_PS1_CTXSW_CNT0 0x335b
-#define mmGDS_PS2_CTXSW_CNT0 0x335f
-#define mmGDS_PS3_CTXSW_CNT0 0x3363
-#define mmGDS_PS4_CTXSW_CNT0 0x3367
-#define mmGDS_PS5_CTXSW_CNT0 0x336b
-#define mmGDS_PS6_CTXSW_CNT0 0x336f
-#define mmGDS_PS7_CTXSW_CNT0 0x3373
-#define mmGDS_PS0_CTXSW_CNT1 0x3358
-#define mmGDS_PS1_CTXSW_CNT1 0x335c
-#define mmGDS_PS2_CTXSW_CNT1 0x3360
-#define mmGDS_PS3_CTXSW_CNT1 0x3364
-#define mmGDS_PS4_CTXSW_CNT1 0x3368
-#define mmGDS_PS5_CTXSW_CNT1 0x336c
-#define mmGDS_PS6_CTXSW_CNT1 0x3370
-#define mmGDS_PS7_CTXSW_CNT1 0x3374
-#define mmGDS_PS0_CTXSW_CNT2 0x3359
-#define mmGDS_PS1_CTXSW_CNT2 0x335d
-#define mmGDS_PS2_CTXSW_CNT2 0x3361
-#define mmGDS_PS3_CTXSW_CNT2 0x3365
-#define mmGDS_PS4_CTXSW_CNT2 0x3369
-#define mmGDS_PS5_CTXSW_CNT2 0x336d
-#define mmGDS_PS6_CTXSW_CNT2 0x3371
-#define mmGDS_PS7_CTXSW_CNT2 0x3375
-#define mmGDS_PS0_CTXSW_CNT3 0x335a
-#define mmGDS_PS1_CTXSW_CNT3 0x335e
-#define mmGDS_PS2_CTXSW_CNT3 0x3362
-#define mmGDS_PS3_CTXSW_CNT3 0x3366
-#define mmGDS_PS4_CTXSW_CNT3 0x336a
-#define mmGDS_PS5_CTXSW_CNT3 0x336e
-#define mmGDS_PS6_CTXSW_CNT3 0x3372
-#define mmGDS_PS7_CTXSW_CNT3 0x3376
-#define mmCS_COPY_STATE 0xa1f3
-#define mmGFX_COPY_STATE 0xa1f4
-#define mmVGT_DRAW_INITIATOR 0xa1fc
-#define mmVGT_EVENT_INITIATOR 0xa2a4
-#define mmVGT_EVENT_ADDRESS_REG 0xa1fe
-#define mmVGT_DMA_BASE_HI 0xa1f9
-#define mmVGT_DMA_BASE 0xa1fa
-#define mmVGT_DMA_INDEX_TYPE 0xa29f
-#define mmVGT_DMA_NUM_INSTANCES 0xa2a2
-#define mmIA_ENHANCE 0xa29c
-#define mmVGT_DMA_SIZE 0xa29d
-#define mmVGT_DMA_MAX_SIZE 0xa29e
-#define mmVGT_DMA_PRIMITIVE_TYPE 0x2271
-#define mmVGT_DMA_CONTROL 0x2272
-#define mmVGT_IMMED_DATA 0xa1fd
-#define mmVGT_INDEX_TYPE 0xc243
-#define mmVGT_NUM_INDICES 0xc24c
-#define mmVGT_NUM_INSTANCES 0xc24d
-#define mmVGT_PRIMITIVE_TYPE 0xc242
-#define mmVGT_PRIMITIVEID_EN 0xa2a1
-#define mmVGT_PRIMITIVEID_RESET 0xa2a3
-#define mmVGT_VTX_CNT_EN 0xa2ae
-#define mmVGT_REUSE_OFF 0xa2ad
-#define mmVGT_INSTANCE_STEP_RATE_0 0xa2a8
-#define mmVGT_INSTANCE_STEP_RATE_1 0xa2a9
-#define mmVGT_MAX_VTX_INDX 0xa100
-#define mmVGT_MIN_VTX_INDX 0xa101
-#define mmVGT_INDX_OFFSET 0xa102
-#define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0xa316
-#define mmVGT_OUT_DEALLOC_CNTL 0xa317
-#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0xa103
-#define mmVGT_MULTI_PRIM_IB_RESET_EN 0xa2a5
-#define mmVGT_ENHANCE 0xa294
-#define mmVGT_OUTPUT_PATH_CNTL 0xa284
-#define mmVGT_HOS_CNTL 0xa285
-#define mmVGT_HOS_MAX_TESS_LEVEL 0xa286
-#define mmVGT_HOS_MIN_TESS_LEVEL 0xa287
-#define mmVGT_HOS_REUSE_DEPTH 0xa288
-#define mmVGT_GROUP_PRIM_TYPE 0xa289
-#define mmVGT_GROUP_FIRST_DECR 0xa28a
-#define mmVGT_GROUP_DECR 0xa28b
-#define mmVGT_GROUP_VECT_0_CNTL 0xa28c
-#define mmVGT_GROUP_VECT_1_CNTL 0xa28d
-#define mmVGT_GROUP_VECT_0_FMT_CNTL 0xa28e
-#define mmVGT_GROUP_VECT_1_FMT_CNTL 0xa28f
-#define mmVGT_VTX_VECT_EJECT_REG 0x222c
-#define mmVGT_DMA_DATA_FIFO_DEPTH 0x222d
-#define mmVGT_DMA_REQ_FIFO_DEPTH 0x222e
-#define mmVGT_DRAW_INIT_FIFO_DEPTH 0x222f
-#define mmVGT_LAST_COPY_STATE 0x2230
-#define mmCC_GC_SHADER_ARRAY_CONFIG 0x226f
-#define mmGC_USER_SHADER_ARRAY_CONFIG 0x2270
-#define mmVGT_GS_MODE 0xa290
-#define mmVGT_GS_ONCHIP_CNTL 0xa291
-#define mmVGT_GS_OUT_PRIM_TYPE 0xa29b
-#define mmVGT_CACHE_INVALIDATION 0x2231
-#define mmVGT_RESET_DEBUG 0x2232
-#define mmVGT_STRMOUT_DELAY 0x2233
-#define mmVGT_FIFO_DEPTHS 0x2234
-#define mmVGT_GS_PER_ES 0xa295
-#define mmVGT_ES_PER_GS 0xa296
-#define mmVGT_GS_PER_VS 0xa297
-#define mmVGT_GS_VERTEX_REUSE 0x2235
-#define mmVGT_MC_LAT_CNTL 0x2236
-#define mmIA_CNTL_STATUS 0x2237
-#define mmVGT_STRMOUT_CONFIG 0xa2e5
-#define mmVGT_STRMOUT_BUFFER_SIZE_0 0xa2b4
-#define mmVGT_STRMOUT_BUFFER_SIZE_1 0xa2b8
-#define mmVGT_STRMOUT_BUFFER_SIZE_2 0xa2bc
-#define mmVGT_STRMOUT_BUFFER_SIZE_3 0xa2c0
-#define mmVGT_STRMOUT_BUFFER_OFFSET_0 0xa2b7
-#define mmVGT_STRMOUT_BUFFER_OFFSET_1 0xa2bb
-#define mmVGT_STRMOUT_BUFFER_OFFSET_2 0xa2bf
-#define mmVGT_STRMOUT_BUFFER_OFFSET_3 0xa2c3
-#define mmVGT_STRMOUT_VTX_STRIDE_0 0xa2b5
-#define mmVGT_STRMOUT_VTX_STRIDE_1 0xa2b9
-#define mmVGT_STRMOUT_VTX_STRIDE_2 0xa2bd
-#define mmVGT_STRMOUT_VTX_STRIDE_3 0xa2c1
-#define mmVGT_STRMOUT_BUFFER_CONFIG 0xa2e6
-#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 0xc244
-#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 0xc245
-#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 0xc246
-#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 0xc247
-#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0xa2ca
-#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0xa2cb
-#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0xa2cc
-#define mmVGT_GS_MAX_VERT_OUT 0xa2ce
-#define mmVGT_SHADER_STAGES_EN 0xa2d5
-#define mmVGT_DISPATCH_DRAW_INDEX 0xa2dd
-#define mmVGT_LS_HS_CONFIG 0xa2d6
-#define mmVGT_DMA_LS_HS_CONFIG 0x2273
-#define mmVGT_TF_PARAM 0xa2db
-#define mmVGT_TESS_DISTRIBUTION 0xa2d4
-#define mmVGT_TF_RING_SIZE 0xc24e
-#define mmVGT_SYS_CONFIG 0x2263
-#define mmVGT_HS_OFFCHIP_PARAM 0xc24f
-#define mmVGT_TF_MEMORY_BASE 0xc250
-#define mmVGT_GS_INSTANCE_CNT 0xa2e4
-#define mmIA_MULTI_VGT_PARAM 0xa2aa
-#define mmVGT_VS_MAX_WAVE_ID 0x2268
-#define mmVGT_ESGS_RING_SIZE 0xc240
-#define mmVGT_GSVS_RING_SIZE 0xc241
-#define mmVGT_GSVS_RING_OFFSET_1 0xa298
-#define mmVGT_GSVS_RING_OFFSET_2 0xa299
-#define mmVGT_GSVS_RING_OFFSET_3 0xa29a
-#define mmVGT_ESGS_RING_ITEMSIZE 0xa2ab
-#define mmVGT_GSVS_RING_ITEMSIZE 0xa2ac
-#define mmVGT_GS_VERT_ITEMSIZE 0xa2d7
-#define mmVGT_GS_VERT_ITEMSIZE_1 0xa2d8
-#define mmVGT_GS_VERT_ITEMSIZE_2 0xa2d9
-#define mmVGT_GS_VERT_ITEMSIZE_3 0xa2da
-#define mmWD_CNTL_STATUS 0x223f
-#define mmWD_ENHANCE 0xa2a0
-#define mmGFX_PIPE_CONTROL 0x226d
-#define mmCGTT_VGT_CLK_CTRL 0xf084
-#define mmCGTT_IA_CLK_CTRL 0xf085
-#define mmCGTT_WD_CLK_CTRL 0xf086
-#define mmVGT_DEBUG_CNTL 0x2238
-#define mmVGT_DEBUG_DATA 0x2239
-#define mmIA_DEBUG_CNTL 0x223a
-#define mmIA_DEBUG_DATA 0x223b
-#define mmVGT_CNTL_STATUS 0x223c
-#define mmWD_DEBUG_CNTL 0x223d
-#define mmWD_DEBUG_DATA 0x223e
-#define mmWD_QOS 0x2242
-#define mmCC_GC_PRIM_CONFIG 0x2240
-#define mmGC_USER_PRIM_CONFIG 0x2241
-#define ixWD_DEBUG_REG0 0x0
-#define ixWD_DEBUG_REG1 0x1
-#define ixWD_DEBUG_REG2 0x2
-#define ixWD_DEBUG_REG3 0x3
-#define ixWD_DEBUG_REG4 0x4
-#define ixWD_DEBUG_REG5 0x5
-#define ixWD_DEBUG_REG6 0x6
-#define ixWD_DEBUG_REG7 0x7
-#define ixWD_DEBUG_REG8 0x8
-#define ixWD_DEBUG_REG9 0x9
-#define ixWD_DEBUG_REG10 0xa
-#define ixIA_DEBUG_REG0 0x0
-#define ixIA_DEBUG_REG1 0x1
-#define ixIA_DEBUG_REG2 0x2
-#define ixIA_DEBUG_REG3 0x3
-#define ixIA_DEBUG_REG4 0x4
-#define ixIA_DEBUG_REG5 0x5
-#define ixIA_DEBUG_REG6 0x6
-#define ixIA_DEBUG_REG7 0x7
-#define ixIA_DEBUG_REG8 0x8
-#define ixIA_DEBUG_REG9 0x9
-#define ixVGT_DEBUG_REG0 0x0
-#define ixVGT_DEBUG_REG1 0x1
-#define ixVGT_DEBUG_REG2 0x1e
-#define ixVGT_DEBUG_REG3 0x1f
-#define ixVGT_DEBUG_REG4 0x20
-#define ixVGT_DEBUG_REG5 0x21
-#define ixVGT_DEBUG_REG6 0x22
-#define ixVGT_DEBUG_REG7 0x23
-#define ixVGT_DEBUG_REG8 0x8
-#define ixVGT_DEBUG_REG9 0x9
-#define ixVGT_DEBUG_REG10 0xa
-#define ixVGT_DEBUG_REG11 0xb
-#define ixVGT_DEBUG_REG12 0xc
-#define ixVGT_DEBUG_REG13 0xd
-#define ixVGT_DEBUG_REG14 0xe
-#define ixVGT_DEBUG_REG15 0xf
-#define ixVGT_DEBUG_REG16 0x10
-#define ixVGT_DEBUG_REG17 0x11
-#define ixVGT_DEBUG_REG18 0x7
-#define ixVGT_DEBUG_REG19 0x13
-#define ixVGT_DEBUG_REG20 0x14
-#define ixVGT_DEBUG_REG21 0x15
-#define ixVGT_DEBUG_REG22 0x16
-#define ixVGT_DEBUG_REG23 0x17
-#define ixVGT_DEBUG_REG24 0x18
-#define ixVGT_DEBUG_REG25 0x19
-#define ixVGT_DEBUG_REG26 0x24
-#define ixVGT_DEBUG_REG27 0x1b
-#define ixVGT_DEBUG_REG28 0x1c
-#define ixVGT_DEBUG_REG29 0x1d
-#define ixVGT_DEBUG_REG31 0x26
-#define ixVGT_DEBUG_REG32 0x27
-#define ixVGT_DEBUG_REG33 0x28
-#define ixVGT_DEBUG_REG34 0x29
-#define ixVGT_DEBUG_REG36 0x2b
-#define mmVGT_PERFCOUNTER_SEID_MASK 0xd894
-#define mmVGT_PERFCOUNTER0_SELECT 0xd88c
-#define mmVGT_PERFCOUNTER1_SELECT 0xd88d
-#define mmVGT_PERFCOUNTER2_SELECT 0xd88e
-#define mmVGT_PERFCOUNTER3_SELECT 0xd88f
-#define mmVGT_PERFCOUNTER0_SELECT1 0xd890
-#define mmVGT_PERFCOUNTER1_SELECT1 0xd891
-#define mmVGT_PERFCOUNTER0_LO 0xd090
-#define mmVGT_PERFCOUNTER1_LO 0xd092
-#define mmVGT_PERFCOUNTER2_LO 0xd094
-#define mmVGT_PERFCOUNTER3_LO 0xd096
-#define mmVGT_PERFCOUNTER0_HI 0xd091
-#define mmVGT_PERFCOUNTER1_HI 0xd093
-#define mmVGT_PERFCOUNTER2_HI 0xd095
-#define mmVGT_PERFCOUNTER3_HI 0xd097
-#define mmIA_PERFCOUNTER0_SELECT 0xd884
-#define mmIA_PERFCOUNTER1_SELECT 0xd885
-#define mmIA_PERFCOUNTER2_SELECT 0xd886
-#define mmIA_PERFCOUNTER3_SELECT 0xd887
-#define mmIA_PERFCOUNTER0_SELECT1 0xd888
-#define mmIA_PERFCOUNTER0_LO 0xd088
-#define mmIA_PERFCOUNTER1_LO 0xd08a
-#define mmIA_PERFCOUNTER2_LO 0xd08c
-#define mmIA_PERFCOUNTER3_LO 0xd08e
-#define mmIA_PERFCOUNTER0_HI 0xd089
-#define mmIA_PERFCOUNTER1_HI 0xd08b
-#define mmIA_PERFCOUNTER2_HI 0xd08d
-#define mmIA_PERFCOUNTER3_HI 0xd08f
-#define mmWD_PERFCOUNTER0_SELECT 0xd880
-#define mmWD_PERFCOUNTER1_SELECT 0xd881
-#define mmWD_PERFCOUNTER2_SELECT 0xd882
-#define mmWD_PERFCOUNTER3_SELECT 0xd883
-#define mmWD_PERFCOUNTER0_LO 0xd080
-#define mmWD_PERFCOUNTER1_LO 0xd082
-#define mmWD_PERFCOUNTER2_LO 0xd084
-#define mmWD_PERFCOUNTER3_LO 0xd086
-#define mmWD_PERFCOUNTER0_HI 0xd081
-#define mmWD_PERFCOUNTER1_HI 0xd083
-#define mmWD_PERFCOUNTER2_HI 0xd085
-#define mmWD_PERFCOUNTER3_HI 0xd087
-#define mmDIDT_IND_INDEX 0x3280
-#define mmDIDT_IND_DATA 0x3281
-#define ixDIDT_SQ_CTRL0 0x0
-#define ixDIDT_SQ_CTRL1 0x1
-#define ixDIDT_SQ_CTRL2 0x2
-#define ixDIDT_SQ_CTRL_OCP 0x3
-#define ixDIDT_SQ_WEIGHT0_3 0x10
-#define ixDIDT_SQ_WEIGHT4_7 0x11
-#define ixDIDT_SQ_WEIGHT8_11 0x12
-#define ixDIDT_DB_CTRL0 0x20
-#define ixDIDT_DB_CTRL1 0x21
-#define ixDIDT_DB_CTRL2 0x22
-#define ixDIDT_DB_CTRL_OCP 0x23
-#define ixDIDT_DB_WEIGHT0_3 0x30
-#define ixDIDT_DB_WEIGHT4_7 0x31
-#define ixDIDT_DB_WEIGHT8_11 0x32
-#define ixDIDT_TD_CTRL0 0x40
-#define ixDIDT_TD_CTRL1 0x41
-#define ixDIDT_TD_CTRL2 0x42
-#define ixDIDT_TD_CTRL_OCP 0x43
-#define ixDIDT_TD_WEIGHT0_3 0x50
-#define ixDIDT_TD_WEIGHT4_7 0x51
-#define ixDIDT_TD_WEIGHT8_11 0x52
-#define ixDIDT_TCP_CTRL0 0x60
-#define ixDIDT_TCP_CTRL1 0x61
-#define ixDIDT_TCP_CTRL2 0x62
-#define ixDIDT_TCP_CTRL_OCP 0x63
-#define ixDIDT_TCP_WEIGHT0_3 0x70
-#define ixDIDT_TCP_WEIGHT4_7 0x71
-#define ixDIDT_TCP_WEIGHT8_11 0x72
-#define ixDIDT_DBR_CTRL0 0x80
-#define ixDIDT_DBR_CTRL1 0x81
-#define ixDIDT_DBR_CTRL2 0x82
-#define ixDIDT_DBR_CTRL_OCP 0x83
-#define ixDIDT_DBR_WEIGHT0_3 0x90
-#define ixDIDT_DBR_WEIGHT4_7 0x91
-#define ixDIDT_DBR_WEIGHT8_11 0x92
-
-#endif /* GFX_8_1_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_enum.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_enum.h
deleted file mode 100644
index f9022097f..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_enum.h
+++ /dev/null
@@ -1,6808 +0,0 @@
-/*
- * GFX_8_1 Register documentation
- *
- * Copyright (C) 2014 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef GFX_8_1_ENUM_H
-#define GFX_8_1_ENUM_H
-
-typedef enum SurfaceNumber {
- NUMBER_UNORM = 0x0,
- NUMBER_SNORM = 0x1,
- NUMBER_USCALED = 0x2,
- NUMBER_SSCALED = 0x3,
- NUMBER_UINT = 0x4,
- NUMBER_SINT = 0x5,
- NUMBER_SRGB = 0x6,
- NUMBER_FLOAT = 0x7,
-} SurfaceNumber;
-typedef enum SurfaceSwap {
- SWAP_STD = 0x0,
- SWAP_ALT = 0x1,
- SWAP_STD_REV = 0x2,
- SWAP_ALT_REV = 0x3,
-} SurfaceSwap;
-typedef enum CBMode {
- CB_DISABLE = 0x0,
- CB_NORMAL = 0x1,
- CB_ELIMINATE_FAST_CLEAR = 0x2,
- CB_RESOLVE = 0x3,
- CB_DECOMPRESS = 0x4,
- CB_FMASK_DECOMPRESS = 0x5,
- CB_DCC_DECOMPRESS = 0x6,
-} CBMode;
-typedef enum RoundMode {
- ROUND_BY_HALF = 0x0,
- ROUND_TRUNCATE = 0x1,
-} RoundMode;
-typedef enum SourceFormat {
- EXPORT_4C_32BPC = 0x0,
- EXPORT_4C_16BPC = 0x1,
- EXPORT_2C_32BPC_GR = 0x2,
- EXPORT_2C_32BPC_AR = 0x3,
-} SourceFormat;
-typedef enum BlendOp {
- BLEND_ZERO = 0x0,
- BLEND_ONE = 0x1,
- BLEND_SRC_COLOR = 0x2,
- BLEND_ONE_MINUS_SRC_COLOR = 0x3,
- BLEND_SRC_ALPHA = 0x4,
- BLEND_ONE_MINUS_SRC_ALPHA = 0x5,
- BLEND_DST_ALPHA = 0x6,
- BLEND_ONE_MINUS_DST_ALPHA = 0x7,
- BLEND_DST_COLOR = 0x8,
- BLEND_ONE_MINUS_DST_COLOR = 0x9,
- BLEND_SRC_ALPHA_SATURATE = 0xa,
- BLEND_BOTH_SRC_ALPHA = 0xb,
- BLEND_BOTH_INV_SRC_ALPHA = 0xc,
- BLEND_CONSTANT_COLOR = 0xd,
- BLEND_ONE_MINUS_CONSTANT_COLOR = 0xe,
- BLEND_SRC1_COLOR = 0xf,
- BLEND_INV_SRC1_COLOR = 0x10,
- BLEND_SRC1_ALPHA = 0x11,
- BLEND_INV_SRC1_ALPHA = 0x12,
- BLEND_CONSTANT_ALPHA = 0x13,
- BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14,
-} BlendOp;
-typedef enum CombFunc {
- COMB_DST_PLUS_SRC = 0x0,
- COMB_SRC_MINUS_DST = 0x1,
- COMB_MIN_DST_SRC = 0x2,
- COMB_MAX_DST_SRC = 0x3,
- COMB_DST_MINUS_SRC = 0x4,
-} CombFunc;
-typedef enum BlendOpt {
- FORCE_OPT_AUTO = 0x0,
- FORCE_OPT_DISABLE = 0x1,
- FORCE_OPT_ENABLE_IF_SRC_A_0 = 0x2,
- FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 0x3,
- FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 0x4,
- FORCE_OPT_ENABLE_IF_SRC_A_1 = 0x5,
- FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 0x6,
- FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 0x7,
-} BlendOpt;
-typedef enum CmaskCode {
- CMASK_CLR00_F0 = 0x0,
- CMASK_CLR00_F1 = 0x1,
- CMASK_CLR00_F2 = 0x2,
- CMASK_CLR00_FX = 0x3,
- CMASK_CLR01_F0 = 0x4,
- CMASK_CLR01_F1 = 0x5,
- CMASK_CLR01_F2 = 0x6,
- CMASK_CLR01_FX = 0x7,
- CMASK_CLR10_F0 = 0x8,
- CMASK_CLR10_F1 = 0x9,
- CMASK_CLR10_F2 = 0xa,
- CMASK_CLR10_FX = 0xb,
- CMASK_CLR11_F0 = 0xc,
- CMASK_CLR11_F1 = 0xd,
- CMASK_CLR11_F2 = 0xe,
- CMASK_CLR11_FX = 0xf,
-} CmaskCode;
-typedef enum CmaskAddr {
- CMASK_ADDR_TILED = 0x0,
- CMASK_ADDR_LINEAR = 0x1,
- CMASK_ADDR_COMPATIBLE = 0x2,
-} CmaskAddr;
-typedef enum CBPerfSel {
- CB_PERF_SEL_NONE = 0x0,
- CB_PERF_SEL_BUSY = 0x1,
- CB_PERF_SEL_CORE_SCLK_VLD = 0x2,
- CB_PERF_SEL_REG_SCLK0_VLD = 0x3,
- CB_PERF_SEL_REG_SCLK1_VLD = 0x4,
- CB_PERF_SEL_DRAWN_QUAD = 0x5,
- CB_PERF_SEL_DRAWN_PIXEL = 0x6,
- CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 0x7,
- CB_PERF_SEL_DRAWN_TILE = 0x8,
- CB_PERF_SEL_DB_CB_TILE_VALID_READY = 0x9,
- CB_PERF_SEL_DB_CB_TILE_VALID_READYB = 0xa,
- CB_PERF_SEL_DB_CB_TILE_VALIDB_READY = 0xb,
- CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB = 0xc,
- CB_PERF_SEL_CM_FC_TILE_VALID_READY = 0xd,
- CB_PERF_SEL_CM_FC_TILE_VALID_READYB = 0xe,
- CB_PERF_SEL_CM_FC_TILE_VALIDB_READY = 0xf,
- CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB = 0x10,
- CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY = 0x11,
- CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB = 0x12,
- CB_PERF_SEL_DB_CB_LQUAD_VALID_READY = 0x13,
- CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB = 0x14,
- CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY = 0x15,
- CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB = 0x16,
- CB_PERF_SEL_LQUAD_NO_TILE = 0x17,
- CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R = 0x18,
- CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR = 0x19,
- CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR = 0x1a,
- CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR = 0x1b,
- CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR = 0x1c,
- CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 0x1d,
- CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR= 0x1e,
- CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT = 0x1f,
- CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID = 0x20,
- CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK= 0x21,
- CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK = 0x22,
- CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL = 0x23,
- CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY = 0x24,
- CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB = 0x25,
- CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY = 0x26,
- CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB = 0x27,
- CB_PERF_SEL_FOP_IN_VALID_READY = 0x28,
- CB_PERF_SEL_FOP_IN_VALID_READYB = 0x29,
- CB_PERF_SEL_FOP_IN_VALIDB_READY = 0x2a,
- CB_PERF_SEL_FOP_IN_VALIDB_READYB = 0x2b,
- CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY = 0x2c,
- CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB = 0x2d,
- CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY = 0x2e,
- CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB = 0x2f,
- CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY = 0x30,
- CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB = 0x31,
- CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY = 0x32,
- CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB = 0x33,
- CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY = 0x34,
- CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB = 0x35,
- CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY = 0x36,
- CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB = 0x37,
- CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY = 0x38,
- CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB = 0x39,
- CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY = 0x3a,
- CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB = 0x3b,
- CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY = 0x3c,
- CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB = 0x3d,
- CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY = 0x3e,
- CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB = 0x3f,
- CB_PERF_SEL_CC_BC_CS_FRAG_VALID = 0x40,
- CB_PERF_SEL_CM_CACHE_HIT = 0x41,
- CB_PERF_SEL_CM_CACHE_TAG_MISS = 0x42,
- CB_PERF_SEL_CM_CACHE_SECTOR_MISS = 0x43,
- CB_PERF_SEL_CM_CACHE_REEVICTION_STALL = 0x44,
- CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x45,
- CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 0x46,
- CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x47,
- CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL = 0x48,
- CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL = 0x49,
- CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL = 0x4a,
- CB_PERF_SEL_CM_CACHE_STALL = 0x4b,
- CB_PERF_SEL_CM_CACHE_FLUSH = 0x4c,
- CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED = 0x4d,
- CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED = 0x4e,
- CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED = 0x4f,
- CB_PERF_SEL_FC_CACHE_HIT = 0x50,
- CB_PERF_SEL_FC_CACHE_TAG_MISS = 0x51,
- CB_PERF_SEL_FC_CACHE_SECTOR_MISS = 0x52,
- CB_PERF_SEL_FC_CACHE_REEVICTION_STALL = 0x53,
- CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x54,
- CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x55,
- CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x56,
- CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL = 0x57,
- CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL = 0x58,
- CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL = 0x59,
- CB_PERF_SEL_FC_CACHE_STALL = 0x5a,
- CB_PERF_SEL_FC_CACHE_FLUSH = 0x5b,
- CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED = 0x5c,
- CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED = 0x5d,
- CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED = 0x5e,
- CB_PERF_SEL_CC_CACHE_HIT = 0x5f,
- CB_PERF_SEL_CC_CACHE_TAG_MISS = 0x60,
- CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 0x61,
- CB_PERF_SEL_CC_CACHE_REEVICTION_STALL = 0x62,
- CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x63,
- CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x64,
- CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x65,
- CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 0x66,
- CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 0x67,
- CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 0x68,
- CB_PERF_SEL_CC_CACHE_STALL = 0x69,
- CB_PERF_SEL_CC_CACHE_FLUSH = 0x6a,
- CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED = 0x6b,
- CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 0x6c,
- CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 0x6d,
- CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 0x6e,
- CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC = 0x6f,
- CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY = 0x70,
- CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB = 0x71,
- CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY = 0x72,
- CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB = 0x73,
- CB_PERF_SEL_CM_MC_WRITE_REQUEST = 0x74,
- CB_PERF_SEL_FC_MC_WRITE_REQUEST = 0x75,
- CB_PERF_SEL_CC_MC_WRITE_REQUEST = 0x76,
- CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT = 0x77,
- CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x78,
- CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x79,
- CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY = 0x7a,
- CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB = 0x7b,
- CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY = 0x7c,
- CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB = 0x7d,
- CB_PERF_SEL_CM_MC_READ_REQUEST = 0x7e,
- CB_PERF_SEL_FC_MC_READ_REQUEST = 0x7f,
- CB_PERF_SEL_CC_MC_READ_REQUEST = 0x80,
- CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT = 0x81,
- CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT = 0x82,
- CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT = 0x83,
- CB_PERF_SEL_CM_TQ_FULL = 0x84,
- CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL = 0x85,
- CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL = 0x86,
- CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL = 0x87,
- CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL = 0x88,
- CB_PERF_SEL_FOP_FMASK_RAW_STALL = 0x89,
- CB_PERF_SEL_FOP_FMASK_BYPASS_STALL = 0x8a,
- CB_PERF_SEL_CC_SF_FULL = 0x8b,
- CB_PERF_SEL_CC_RB_FULL = 0x8c,
- CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL = 0x8d,
- CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL = 0x8e,
- CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL = 0x8f,
- CB_PERF_SEL_EVENT = 0x90,
- CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 0x91,
- CB_PERF_SEL_EVENT_CONTEXT_DONE = 0x92,
- CB_PERF_SEL_EVENT_CACHE_FLUSH = 0x93,
- CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 0x94,
- CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 0x95,
- CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 0x96,
- CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 0x97,
- CB_PERF_SEL_CC_SURFACE_SYNC = 0x98,
- CB_PERF_SEL_CMASK_READ_DATA_0xC = 0x99,
- CB_PERF_SEL_CMASK_READ_DATA_0xD = 0x9a,
- CB_PERF_SEL_CMASK_READ_DATA_0xE = 0x9b,
- CB_PERF_SEL_CMASK_READ_DATA_0xF = 0x9c,
- CB_PERF_SEL_CMASK_WRITE_DATA_0xC = 0x9d,
- CB_PERF_SEL_CMASK_WRITE_DATA_0xD = 0x9e,
- CB_PERF_SEL_CMASK_WRITE_DATA_0xE = 0x9f,
- CB_PERF_SEL_CMASK_WRITE_DATA_0xF = 0xa0,
- CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT = 0xa1,
- CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT = 0xa2,
- CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT = 0xa3,
- CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE = 0xa4,
- CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE = 0xa5,
- CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE = 0xa6,
- CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE = 0xa7,
- CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE = 0xa8,
- CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE = 0xa9,
- CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE = 0xaa,
- CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE = 0xab,
- CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE = 0xac,
- CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE = 0xad,
- CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE = 0xae,
- CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE = 0xaf,
- CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE = 0xb0,
- CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE = 0xb1,
- CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE = 0xb2,
- CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE = 0xb3,
- CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT = 0xb4,
- CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS = 0xb5,
- CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS = 0xb6,
- CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS = 0xb7,
- CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS = 0xb8,
- CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS = 0xb9,
- CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS = 0xba,
- CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT = 0xbb,
- CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS = 0xbc,
- CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS = 0xbd,
- CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS = 0xbe,
- CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS = 0xbf,
- CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS = 0xc0,
- CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS = 0xc1,
- CB_PERF_SEL_QUAD_READS_FRAGMENT_0 = 0xc2,
- CB_PERF_SEL_QUAD_READS_FRAGMENT_1 = 0xc3,
- CB_PERF_SEL_QUAD_READS_FRAGMENT_2 = 0xc4,
- CB_PERF_SEL_QUAD_READS_FRAGMENT_3 = 0xc5,
- CB_PERF_SEL_QUAD_READS_FRAGMENT_4 = 0xc6,
- CB_PERF_SEL_QUAD_READS_FRAGMENT_5 = 0xc7,
- CB_PERF_SEL_QUAD_READS_FRAGMENT_6 = 0xc8,
- CB_PERF_SEL_QUAD_READS_FRAGMENT_7 = 0xc9,
- CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0 = 0xca,
- CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1 = 0xcb,
- CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2 = 0xcc,
- CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3 = 0xcd,
- CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4 = 0xce,
- CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5 = 0xcf,
- CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6 = 0xd0,
- CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7 = 0xd1,
- CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST = 0xd2,
- CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS = 0xd3,
- CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS = 0xd4,
- CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED= 0xd5,
- CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED= 0xd6,
- CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED = 0xd7,
- CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 0xd8,
- CB_PERF_SEL_DRAWN_BUSY = 0xd9,
- CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY = 0xda,
- CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY = 0xdb,
- CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY = 0xdc,
- CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY = 0xdd,
- CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED= 0xde,
- CB_PERF_SEL_FC_SEQUENCER_CLEAR = 0xdf,
- CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR = 0xe0,
- CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS = 0xe1,
- CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE= 0xe2,
- CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL = 0xe3,
- CB_PERF_SEL_FC_DOC_IS_STALLED = 0xe4,
- CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED = 0xe5,
- CB_PERF_SEL_FC_DOC_MRTS_COMBINED = 0xe6,
- CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS = 0xe7,
- CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT = 0xe8,
- CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS = 0xe9,
- CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT = 0xea,
- CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL = 0xeb,
- CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR = 0xec,
- CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS = 0xed,
- CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS = 0xee,
- CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS = 0xef,
- CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS = 0xf0,
- CB_PERF_SEL_FC_DCC_CACHE_HIT = 0xf1,
- CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS = 0xf2,
- CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS = 0xf3,
- CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL = 0xf4,
- CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0xf5,
- CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL= 0xf6,
- CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0xf7,
- CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL = 0xf8,
- CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL = 0xf9,
- CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL = 0xfa,
- CB_PERF_SEL_FC_DCC_CACHE_STALL = 0xfb,
- CB_PERF_SEL_FC_DCC_CACHE_FLUSH = 0xfc,
- CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED = 0xfd,
- CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED = 0xfe,
- CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED = 0xff,
- CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT = 0x100,
- CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST = 0x101,
- CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT = 0x102,
- CB_PERF_SEL_FC_MC_DCC_READ_REQUEST = 0x103,
- CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT = 0x104,
- CB_PERF_SEL_CC_DCC_RDREQ_STALL = 0x105,
- CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN = 0x106,
- CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT = 0x107,
- CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN = 0x108,
- CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT = 0x109,
- CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR = 0x10a,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1 = 0x10b,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2= 0x10c,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1= 0x10d,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1= 0x10e,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1= 0x10f,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2= 0x110,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1= 0x111,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2= 0x112,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1= 0x113,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1= 0x114,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2= 0x115,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2= 0x116,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2= 0x117,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2= 0x118,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1= 0x119,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1 = 0x11a,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2= 0x11b,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3= 0x11c,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4= 0x11d,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1= 0x11e,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2 = 0x11f,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3= 0x120,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4= 0x121,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1= 0x122,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2= 0x123,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3 = 0x124,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4= 0x125,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1= 0x126,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2= 0x127,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3= 0x128,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1= 0x129,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2= 0x12a,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3= 0x12b,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4= 0x12c,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1= 0x12d,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2= 0x12e,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3= 0x12f,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4= 0x130,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1= 0x131,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2= 0x132,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3= 0x133,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4= 0x134,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1= 0x135,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2= 0x136,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3= 0x137,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1= 0x138,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1= 0x139,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1= 0x13a,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1= 0x13b,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1= 0x13c,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1= 0x13d,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1= 0x13e,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1= 0x13f,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2= 0x140,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2= 0x141,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2= 0x142,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2= 0x143,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2= 0x144,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2= 0x145,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2= 0x146,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1= 0x147,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1= 0x148,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1= 0x149,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1= 0x14a,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2= 0x14b,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2= 0x14c,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2= 0x14d,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2= 0x14e,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2= 0x14f,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2= 0x150,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2= 0x151,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1= 0x152,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1= 0x153,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1= 0x154,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1= 0x155,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1= 0x156,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2= 0x157,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3= 0x158,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4= 0x159,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5= 0x15a,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6= 0x15b,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0 = 0x15c,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1 = 0x15d,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1= 0x15e,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2= 0x15f,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3= 0x160,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4= 0x161,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5= 0x162,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0 = 0x163,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1 = 0x164,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1= 0x165,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1= 0x166,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1= 0x167,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1= 0x168,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1= 0x169,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1= 0x16a,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1 = 0x16b,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1 = 0x16c,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2= 0x16d,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2= 0x16e,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2= 0x16f,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2= 0x170,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2= 0x171,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2 = 0x172,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2 = 0x173,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1 = 0x174,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2 = 0x175,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3 = 0x176,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4 = 0x177,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5 = 0x178,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6 = 0x179,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7 = 0x17a,
- CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED = 0x17b,
- CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1 = 0x17c,
- CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1 = 0x17d,
- CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2 = 0x17e,
- CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3 = 0x17f,
- CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1 = 0x180,
- CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2 = 0x181,
- CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3 = 0x182,
- CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4 = 0x183,
- CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5 = 0x184,
- CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1 = 0x185,
- CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2 = 0x186,
- CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3 = 0x187,
- CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4 = 0x188,
- CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5 = 0x189,
- CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6 = 0x18a,
- CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7 = 0x18b,
- CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH = 0x18c,
- CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT = 0x18d,
- CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT = 0x18e,
- CB_PERF_SEL_RBP_SPLIT_MICROTILE = 0x18f,
- CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK = 0x190,
- CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK = 0x191,
- CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING = 0x192,
- CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS = 0x193,
- CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD = 0x194,
-} CBPerfSel;
-typedef enum CBPerfOpFilterSel {
- CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0x0,
- CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 0x1,
- CB_PERF_OP_FILTER_SEL_RESOLVE = 0x2,
- CB_PERF_OP_FILTER_SEL_DECOMPRESS = 0x3,
- CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 0x4,
- CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 0x5,
-} CBPerfOpFilterSel;
-typedef enum CBPerfClearFilterSel {
- CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0x0,
- CB_PERF_CLEAR_FILTER_SEL_CLEAR = 0x1,
-} CBPerfClearFilterSel;
-typedef enum CP_RING_ID {
- RINGID0 = 0x0,
- RINGID1 = 0x1,
- RINGID2 = 0x2,
- RINGID3 = 0x3,
-} CP_RING_ID;
-typedef enum CP_PIPE_ID {
- PIPE_ID0 = 0x0,
- PIPE_ID1 = 0x1,
- PIPE_ID2 = 0x2,
- PIPE_ID3 = 0x3,
-} CP_PIPE_ID;
-typedef enum CP_ME_ID {
- ME_ID0 = 0x0,
- ME_ID1 = 0x1,
- ME_ID2 = 0x2,
- ME_ID3 = 0x3,
-} CP_ME_ID;
-typedef enum SPM_PERFMON_STATE {
- STRM_PERFMON_STATE_DISABLE_AND_RESET = 0x0,
- STRM_PERFMON_STATE_START_COUNTING = 0x1,
- STRM_PERFMON_STATE_STOP_COUNTING = 0x2,
- STRM_PERFMON_STATE_RESERVED_3 = 0x3,
- STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x4,
- STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x5,
-} SPM_PERFMON_STATE;
-typedef enum CP_PERFMON_STATE {
- CP_PERFMON_STATE_DISABLE_AND_RESET = 0x0,
- CP_PERFMON_STATE_START_COUNTING = 0x1,
- CP_PERFMON_STATE_STOP_COUNTING = 0x2,
- CP_PERFMON_STATE_RESERVED_3 = 0x3,
- CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x4,
- CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x5,
-} CP_PERFMON_STATE;
-typedef enum CP_PERFMON_ENABLE_MODE {
- CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0x0,
- CP_PERFMON_ENABLE_MODE_RESERVED_1 = 0x1,
- CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 0x2,
- CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 0x3,
-} CP_PERFMON_ENABLE_MODE;
-typedef enum CPG_PERFCOUNT_SEL {
- CPG_PERF_SEL_ALWAYS_COUNT = 0x0,
- CPG_PERF_SEL_RBIU_FIFO_FULL = 0x1,
- CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR = 0x2,
- CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL = 0x3,
- CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 0x4,
- CPG_PERF_SEL_ME_PARSER_BUSY = 0x5,
- CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 0x6,
- CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 0x7,
- CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0x8,
- CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 0x9,
- CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 0xa,
- CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 0xb,
- CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 0xc,
- CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 0xd,
- CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 0xe,
- CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 0xf,
- CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 0x10,
- CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 0x11,
- CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 0x12,
- CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 0x13,
- CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 0x14,
- CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 0x15,
- CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 0x16,
- CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 0x17,
- CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 0x18,
- CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 0x19,
- CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 0x1a,
- CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 0x1b,
- CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 0x1c,
- CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 0x1d,
- CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS = 0x1e,
- CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 0x1f,
- CPG_PERF_SEL_DYNAMIC_CLK_VALID = 0x20,
- CPG_PERF_SEL_REGISTER_CLK_VALID = 0x21,
- CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT = 0x22,
- CPG_PERF_SEL_MIU_READ_REQUEST_SENT = 0x23,
- CPG_PERF_SEL_CE_STALL_RAM_DUMP = 0x24,
- CPG_PERF_SEL_CE_STALL_RAM_WRITE = 0x25,
- CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 0x26,
- CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 0x27,
- CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU = 0x28,
- CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 0x29,
- CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 0x2a,
- CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 0x2b,
- CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x2c,
- CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 0x2d,
- CPG_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE = 0x2e,
- CPG_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS = 0x2f,
- CPG_PERF_SEL_ATCL1_STALL_ON_TRANSLATION = 0x30,
-} CPG_PERFCOUNT_SEL;
-typedef enum CPF_PERFCOUNT_SEL {
- CPF_PERF_SEL_ALWAYS_COUNT = 0x0,
- CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE = 0x1,
- CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 0x2,
- CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 0x3,
- CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 0x4,
- CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 0x5,
- CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 0x6,
- CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE = 0x7,
- CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS = 0x8,
- CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR = 0x9,
- CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 0xa,
- CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0xb,
- CPF_PERF_SEL_GRBM_DWORDS_SENT = 0xc,
- CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 0xd,
- CPF_PERF_SEL_REGISTER_CLOCK_VALID = 0xe,
- CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND = 0xf,
- CPF_PERF_SEL_MIU_READ_REQUEST_SEND = 0x10,
- CPF_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE = 0x11,
- CPF_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS = 0x12,
- CPF_PERF_SEL_ATCL1_STALL_ON_TRANSLATION = 0x13,
-} CPF_PERFCOUNT_SEL;
-typedef enum CPC_PERFCOUNT_SEL {
- CPC_PERF_SEL_ALWAYS_COUNT = 0x0,
- CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x1,
- CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 0x2,
- CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE = 0x3,
- CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE = 0x4,
- CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x5,
- CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 0x6,
- CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 0x7,
- CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 0x8,
- CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ = 0x9,
- CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE = 0xa,
- CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 0xb,
- CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 0xc,
- CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 0xd,
- CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 0xe,
- CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 0xf,
- CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 0x10,
- CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ = 0x11,
- CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE = 0x12,
- CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 0x13,
- CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 0x14,
- CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 0x15,
- CPC_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE = 0x16,
- CPC_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS = 0x17,
- CPC_PERF_SEL_ATCL1_STALL_ON_TRANSLATION = 0x18,
-} CPC_PERFCOUNT_SEL;
-typedef enum CP_ALPHA_TAG_RAM_SEL {
- CPG_TAG_RAM = 0x0,
- CPC_TAG_RAM = 0x1,
- CPF_TAG_RAM = 0x2,
- RSV_TAG_RAM = 0x3,
-} CP_ALPHA_TAG_RAM_SEL;
-#define SEM_ECC_ERROR 0x0
-#define SEM_RESERVED 0x1
-#define SEM_FAILED 0x2
-#define SEM_PASSED 0x3
-#define IQ_QUEUE_SLEEP 0x0
-#define IQ_OFFLOAD_RETRY 0x1
-#define IQ_SCH_WAVE_MSG 0x2
-#define IQ_SEM_REARM 0x3
-#define IQ_DEQUEUE_RETRY 0x4
-#define IQ_INTR_TYPE_PQ 0x0
-#define IQ_INTR_TYPE_IB 0x1
-#define IQ_INTR_TYPE_MQD 0x2
-#define VMID_SZ 0x4
-#define CONFIG_SPACE_START 0x2000
-#define CONFIG_SPACE_END 0x9fff
-#define CONFIG_SPACE1_START 0x2000
-#define CONFIG_SPACE1_END 0x2bff
-#define CONFIG_SPACE2_START 0x3000
-#define CONFIG_SPACE2_END 0x9fff
-#define UCONFIG_SPACE_START 0xc000
-#define UCONFIG_SPACE_END 0xffff
-#define PERSISTENT_SPACE_START 0x2c00
-#define PERSISTENT_SPACE_END 0x2fff
-#define CONTEXT_SPACE_START 0xa000
-#define CONTEXT_SPACE_END 0xbfff
-typedef enum ForceControl {
- FORCE_OFF = 0x0,
- FORCE_ENABLE = 0x1,
- FORCE_DISABLE = 0x2,
- FORCE_RESERVED = 0x3,
-} ForceControl;
-typedef enum ZSamplePosition {
- Z_SAMPLE_CENTER = 0x0,
- Z_SAMPLE_CENTROID = 0x1,
-} ZSamplePosition;
-typedef enum ZOrder {
- LATE_Z = 0x0,
- EARLY_Z_THEN_LATE_Z = 0x1,
- RE_Z = 0x2,
- EARLY_Z_THEN_RE_Z = 0x3,
-} ZOrder;
-typedef enum ZpassControl {
- ZPASS_DISABLE = 0x0,
- ZPASS_SAMPLES = 0x1,
- ZPASS_PIXELS = 0x2,
-} ZpassControl;
-typedef enum ZModeForce {
- NO_FORCE = 0x0,
- FORCE_EARLY_Z = 0x1,
- FORCE_LATE_Z = 0x2,
- FORCE_RE_Z = 0x3,
-} ZModeForce;
-typedef enum ZLimitSumm {
- FORCE_SUMM_OFF = 0x0,
- FORCE_SUMM_MINZ = 0x1,
- FORCE_SUMM_MAXZ = 0x2,
- FORCE_SUMM_BOTH = 0x3,
-} ZLimitSumm;
-typedef enum CompareFrag {
- FRAG_NEVER = 0x0,
- FRAG_LESS = 0x1,
- FRAG_EQUAL = 0x2,
- FRAG_LEQUAL = 0x3,
- FRAG_GREATER = 0x4,
- FRAG_NOTEQUAL = 0x5,
- FRAG_GEQUAL = 0x6,
- FRAG_ALWAYS = 0x7,
-} CompareFrag;
-typedef enum StencilOp {
- STENCIL_KEEP = 0x0,
- STENCIL_ZERO = 0x1,
- STENCIL_ONES = 0x2,
- STENCIL_REPLACE_TEST = 0x3,
- STENCIL_REPLACE_OP = 0x4,
- STENCIL_ADD_CLAMP = 0x5,
- STENCIL_SUB_CLAMP = 0x6,
- STENCIL_INVERT = 0x7,
- STENCIL_ADD_WRAP = 0x8,
- STENCIL_SUB_WRAP = 0x9,
- STENCIL_AND = 0xa,
- STENCIL_OR = 0xb,
- STENCIL_XOR = 0xc,
- STENCIL_NAND = 0xd,
- STENCIL_NOR = 0xe,
- STENCIL_XNOR = 0xf,
-} StencilOp;
-typedef enum ConservativeZExport {
- EXPORT_ANY_Z = 0x0,
- EXPORT_LESS_THAN_Z = 0x1,
- EXPORT_GREATER_THAN_Z = 0x2,
- EXPORT_RESERVED = 0x3,
-} ConservativeZExport;
-typedef enum DbPSLControl {
- PSLC_AUTO = 0x0,
- PSLC_ON_HANG_ONLY = 0x1,
- PSLC_ASAP = 0x2,
- PSLC_COUNTDOWN = 0x3,
-} DbPSLControl;
-typedef enum PerfCounter_Vals {
- DB_PERF_SEL_SC_DB_tile_sends = 0x0,
- DB_PERF_SEL_SC_DB_tile_busy = 0x1,
- DB_PERF_SEL_SC_DB_tile_stalls = 0x2,
- DB_PERF_SEL_SC_DB_tile_events = 0x3,
- DB_PERF_SEL_SC_DB_tile_tiles = 0x4,
- DB_PERF_SEL_SC_DB_tile_covered = 0x5,
- DB_PERF_SEL_hiz_tc_read_starved = 0x6,
- DB_PERF_SEL_hiz_tc_write_stall = 0x7,
- DB_PERF_SEL_hiz_qtiles_culled = 0x8,
- DB_PERF_SEL_his_qtiles_culled = 0x9,
- DB_PERF_SEL_DB_SC_tile_sends = 0xa,
- DB_PERF_SEL_DB_SC_tile_busy = 0xb,
- DB_PERF_SEL_DB_SC_tile_stalls = 0xc,
- DB_PERF_SEL_DB_SC_tile_df_stalls = 0xd,
- DB_PERF_SEL_DB_SC_tile_tiles = 0xe,
- DB_PERF_SEL_DB_SC_tile_culled = 0xf,
- DB_PERF_SEL_DB_SC_tile_hier_kill = 0x10,
- DB_PERF_SEL_DB_SC_tile_fast_ops = 0x11,
- DB_PERF_SEL_DB_SC_tile_no_ops = 0x12,
- DB_PERF_SEL_DB_SC_tile_tile_rate = 0x13,
- DB_PERF_SEL_DB_SC_tile_ssaa_kill = 0x14,
- DB_PERF_SEL_DB_SC_tile_fast_z_ops = 0x15,
- DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 0x16,
- DB_PERF_SEL_SC_DB_quad_sends = 0x17,
- DB_PERF_SEL_SC_DB_quad_busy = 0x18,
- DB_PERF_SEL_SC_DB_quad_squads = 0x19,
- DB_PERF_SEL_SC_DB_quad_tiles = 0x1a,
- DB_PERF_SEL_SC_DB_quad_pixels = 0x1b,
- DB_PERF_SEL_SC_DB_quad_killed_tiles = 0x1c,
- DB_PERF_SEL_DB_SC_quad_sends = 0x1d,
- DB_PERF_SEL_DB_SC_quad_busy = 0x1e,
- DB_PERF_SEL_DB_SC_quad_stalls = 0x1f,
- DB_PERF_SEL_DB_SC_quad_tiles = 0x20,
- DB_PERF_SEL_DB_SC_quad_lit_quad = 0x21,
- DB_PERF_SEL_DB_CB_tile_sends = 0x22,
- DB_PERF_SEL_DB_CB_tile_busy = 0x23,
- DB_PERF_SEL_DB_CB_tile_stalls = 0x24,
- DB_PERF_SEL_SX_DB_quad_sends = 0x25,
- DB_PERF_SEL_SX_DB_quad_busy = 0x26,
- DB_PERF_SEL_SX_DB_quad_stalls = 0x27,
- DB_PERF_SEL_SX_DB_quad_quads = 0x28,
- DB_PERF_SEL_SX_DB_quad_pixels = 0x29,
- DB_PERF_SEL_SX_DB_quad_exports = 0x2a,
- DB_PERF_SEL_SH_quads_outstanding_sum = 0x2b,
- DB_PERF_SEL_DB_CB_lquad_sends = 0x2c,
- DB_PERF_SEL_DB_CB_lquad_busy = 0x2d,
- DB_PERF_SEL_DB_CB_lquad_stalls = 0x2e,
- DB_PERF_SEL_DB_CB_lquad_quads = 0x2f,
- DB_PERF_SEL_tile_rd_sends = 0x30,
- DB_PERF_SEL_mi_tile_rd_outstanding_sum = 0x31,
- DB_PERF_SEL_quad_rd_sends = 0x32,
- DB_PERF_SEL_quad_rd_busy = 0x33,
- DB_PERF_SEL_quad_rd_mi_stall = 0x34,
- DB_PERF_SEL_quad_rd_rw_collision = 0x35,
- DB_PERF_SEL_quad_rd_tag_stall = 0x36,
- DB_PERF_SEL_quad_rd_32byte_reqs = 0x37,
- DB_PERF_SEL_quad_rd_panic = 0x38,
- DB_PERF_SEL_mi_quad_rd_outstanding_sum = 0x39,
- DB_PERF_SEL_quad_rdret_sends = 0x3a,
- DB_PERF_SEL_quad_rdret_busy = 0x3b,
- DB_PERF_SEL_tile_wr_sends = 0x3c,
- DB_PERF_SEL_tile_wr_acks = 0x3d,
- DB_PERF_SEL_mi_tile_wr_outstanding_sum = 0x3e,
- DB_PERF_SEL_quad_wr_sends = 0x3f,
- DB_PERF_SEL_quad_wr_busy = 0x40,
- DB_PERF_SEL_quad_wr_mi_stall = 0x41,
- DB_PERF_SEL_quad_wr_coherency_stall = 0x42,
- DB_PERF_SEL_quad_wr_acks = 0x43,
- DB_PERF_SEL_mi_quad_wr_outstanding_sum = 0x44,
- DB_PERF_SEL_Tile_Cache_misses = 0x45,
- DB_PERF_SEL_Tile_Cache_hits = 0x46,
- DB_PERF_SEL_Tile_Cache_flushes = 0x47,
- DB_PERF_SEL_Tile_Cache_surface_stall = 0x48,
- DB_PERF_SEL_Tile_Cache_starves = 0x49,
- DB_PERF_SEL_Tile_Cache_mem_return_starve = 0x4a,
- DB_PERF_SEL_tcp_dispatcher_reads = 0x4b,
- DB_PERF_SEL_tcp_prefetcher_reads = 0x4c,
- DB_PERF_SEL_tcp_preloader_reads = 0x4d,
- DB_PERF_SEL_tcp_dispatcher_flushes = 0x4e,
- DB_PERF_SEL_tcp_prefetcher_flushes = 0x4f,
- DB_PERF_SEL_tcp_preloader_flushes = 0x50,
- DB_PERF_SEL_Depth_Tile_Cache_sends = 0x51,
- DB_PERF_SEL_Depth_Tile_Cache_busy = 0x52,
- DB_PERF_SEL_Depth_Tile_Cache_starves = 0x53,
- DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 0x54,
- DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 0x55,
- DB_PERF_SEL_Depth_Tile_Cache_misses = 0x56,
- DB_PERF_SEL_Depth_Tile_Cache_hits = 0x57,
- DB_PERF_SEL_Depth_Tile_Cache_flushes = 0x58,
- DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 0x59,
- DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 0x5a,
- DB_PERF_SEL_Depth_Tile_Cache_event = 0x5b,
- DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 0x5c,
- DB_PERF_SEL_Depth_Tile_Cache_data_frees = 0x5d,
- DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 0x5e,
- DB_PERF_SEL_Stencil_Cache_misses = 0x5f,
- DB_PERF_SEL_Stencil_Cache_hits = 0x60,
- DB_PERF_SEL_Stencil_Cache_flushes = 0x61,
- DB_PERF_SEL_Stencil_Cache_starves = 0x62,
- DB_PERF_SEL_Stencil_Cache_frees = 0x63,
- DB_PERF_SEL_Z_Cache_separate_Z_misses = 0x64,
- DB_PERF_SEL_Z_Cache_separate_Z_hits = 0x65,
- DB_PERF_SEL_Z_Cache_separate_Z_flushes = 0x66,
- DB_PERF_SEL_Z_Cache_separate_Z_starves = 0x67,
- DB_PERF_SEL_Z_Cache_pmask_misses = 0x68,
- DB_PERF_SEL_Z_Cache_pmask_hits = 0x69,
- DB_PERF_SEL_Z_Cache_pmask_flushes = 0x6a,
- DB_PERF_SEL_Z_Cache_pmask_starves = 0x6b,
- DB_PERF_SEL_Z_Cache_frees = 0x6c,
- DB_PERF_SEL_Plane_Cache_misses = 0x6d,
- DB_PERF_SEL_Plane_Cache_hits = 0x6e,
- DB_PERF_SEL_Plane_Cache_flushes = 0x6f,
- DB_PERF_SEL_Plane_Cache_starves = 0x70,
- DB_PERF_SEL_Plane_Cache_frees = 0x71,
- DB_PERF_SEL_flush_expanded_stencil = 0x72,
- DB_PERF_SEL_flush_compressed_stencil = 0x73,
- DB_PERF_SEL_flush_single_stencil = 0x74,
- DB_PERF_SEL_planes_flushed = 0x75,
- DB_PERF_SEL_flush_1plane = 0x76,
- DB_PERF_SEL_flush_2plane = 0x77,
- DB_PERF_SEL_flush_3plane = 0x78,
- DB_PERF_SEL_flush_4plane = 0x79,
- DB_PERF_SEL_flush_5plane = 0x7a,
- DB_PERF_SEL_flush_6plane = 0x7b,
- DB_PERF_SEL_flush_7plane = 0x7c,
- DB_PERF_SEL_flush_8plane = 0x7d,
- DB_PERF_SEL_flush_9plane = 0x7e,
- DB_PERF_SEL_flush_10plane = 0x7f,
- DB_PERF_SEL_flush_11plane = 0x80,
- DB_PERF_SEL_flush_12plane = 0x81,
- DB_PERF_SEL_flush_13plane = 0x82,
- DB_PERF_SEL_flush_14plane = 0x83,
- DB_PERF_SEL_flush_15plane = 0x84,
- DB_PERF_SEL_flush_16plane = 0x85,
- DB_PERF_SEL_flush_expanded_z = 0x86,
- DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 0x87,
- DB_PERF_SEL_reZ_waiting_for_postZ_done = 0x88,
- DB_PERF_SEL_dk_tile_sends = 0x89,
- DB_PERF_SEL_dk_tile_busy = 0x8a,
- DB_PERF_SEL_dk_tile_quad_starves = 0x8b,
- DB_PERF_SEL_dk_tile_stalls = 0x8c,
- DB_PERF_SEL_dk_squad_sends = 0x8d,
- DB_PERF_SEL_dk_squad_busy = 0x8e,
- DB_PERF_SEL_dk_squad_stalls = 0x8f,
- DB_PERF_SEL_Op_Pipe_Busy = 0x90,
- DB_PERF_SEL_Op_Pipe_MC_Read_stall = 0x91,
- DB_PERF_SEL_qc_busy = 0x92,
- DB_PERF_SEL_qc_xfc = 0x93,
- DB_PERF_SEL_qc_conflicts = 0x94,
- DB_PERF_SEL_qc_full_stall = 0x95,
- DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 0x96,
- DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 0x97,
- DB_PERF_SEL_tsc_insert_summarize_stall = 0x98,
- DB_PERF_SEL_tl_busy = 0x99,
- DB_PERF_SEL_tl_dtc_read_starved = 0x9a,
- DB_PERF_SEL_tl_z_fetch_stall = 0x9b,
- DB_PERF_SEL_tl_stencil_stall = 0x9c,
- DB_PERF_SEL_tl_z_decompress_stall = 0x9d,
- DB_PERF_SEL_tl_stencil_locked_stall = 0x9e,
- DB_PERF_SEL_tl_events = 0x9f,
- DB_PERF_SEL_tl_summarize_squads = 0xa0,
- DB_PERF_SEL_tl_flush_expand_squads = 0xa1,
- DB_PERF_SEL_tl_expand_squads = 0xa2,
- DB_PERF_SEL_tl_preZ_squads = 0xa3,
- DB_PERF_SEL_tl_postZ_squads = 0xa4,
- DB_PERF_SEL_tl_preZ_noop_squads = 0xa5,
- DB_PERF_SEL_tl_postZ_noop_squads = 0xa6,
- DB_PERF_SEL_tl_tile_ops = 0xa7,
- DB_PERF_SEL_tl_in_xfc = 0xa8,
- DB_PERF_SEL_tl_in_single_stencil_expand_stall = 0xa9,
- DB_PERF_SEL_tl_in_fast_z_stall = 0xaa,
- DB_PERF_SEL_tl_out_xfc = 0xab,
- DB_PERF_SEL_tl_out_squads = 0xac,
- DB_PERF_SEL_zf_plane_multicycle = 0xad,
- DB_PERF_SEL_PostZ_Samples_passing_Z = 0xae,
- DB_PERF_SEL_PostZ_Samples_failing_Z = 0xaf,
- DB_PERF_SEL_PostZ_Samples_failing_S = 0xb0,
- DB_PERF_SEL_PreZ_Samples_passing_Z = 0xb1,
- DB_PERF_SEL_PreZ_Samples_failing_Z = 0xb2,
- DB_PERF_SEL_PreZ_Samples_failing_S = 0xb3,
- DB_PERF_SEL_ts_tc_update_stall = 0xb4,
- DB_PERF_SEL_sc_kick_start = 0xb5,
- DB_PERF_SEL_sc_kick_end = 0xb6,
- DB_PERF_SEL_clock_reg_active = 0xb7,
- DB_PERF_SEL_clock_main_active = 0xb8,
- DB_PERF_SEL_clock_mem_export_active = 0xb9,
- DB_PERF_SEL_esr_ps_out_busy = 0xba,
- DB_PERF_SEL_esr_ps_lqf_busy = 0xbb,
- DB_PERF_SEL_esr_ps_lqf_stall = 0xbc,
- DB_PERF_SEL_etr_out_send = 0xbd,
- DB_PERF_SEL_etr_out_busy = 0xbe,
- DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 0xbf,
- DB_PERF_SEL_etr_out_cb_tile_stall = 0xc0,
- DB_PERF_SEL_etr_out_esr_stall = 0xc1,
- DB_PERF_SEL_esr_ps_sqq_busy = 0xc2,
- DB_PERF_SEL_esr_ps_sqq_stall = 0xc3,
- DB_PERF_SEL_esr_eot_fwd_busy = 0xc4,
- DB_PERF_SEL_esr_eot_fwd_holding_squad = 0xc5,
- DB_PERF_SEL_esr_eot_fwd_forward = 0xc6,
- DB_PERF_SEL_esr_sqq_zi_busy = 0xc7,
- DB_PERF_SEL_esr_sqq_zi_stall = 0xc8,
- DB_PERF_SEL_postzl_sq_pt_busy = 0xc9,
- DB_PERF_SEL_postzl_sq_pt_stall = 0xca,
- DB_PERF_SEL_postzl_se_busy = 0xcb,
- DB_PERF_SEL_postzl_se_stall = 0xcc,
- DB_PERF_SEL_postzl_partial_launch = 0xcd,
- DB_PERF_SEL_postzl_full_launch = 0xce,
- DB_PERF_SEL_postzl_partial_waiting = 0xcf,
- DB_PERF_SEL_postzl_tile_mem_stall = 0xd0,
- DB_PERF_SEL_postzl_tile_init_stall = 0xd1,
- DB_PEFF_SEL_prezl_tile_mem_stall = 0xd2,
- DB_PERF_SEL_prezl_tile_init_stall = 0xd3,
- DB_PERF_SEL_dtt_sm_clash_stall = 0xd4,
- DB_PERF_SEL_dtt_sm_slot_stall = 0xd5,
- DB_PERF_SEL_dtt_sm_miss_stall = 0xd6,
- DB_PERF_SEL_mi_rdreq_busy = 0xd7,
- DB_PERF_SEL_mi_rdreq_stall = 0xd8,
- DB_PERF_SEL_mi_wrreq_busy = 0xd9,
- DB_PERF_SEL_mi_wrreq_stall = 0xda,
- DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 0xdb,
- DB_PERF_SEL_dkg_tile_rate_tile = 0xdc,
- DB_PERF_SEL_prezl_src_in_sends = 0xdd,
- DB_PERF_SEL_prezl_src_in_stall = 0xde,
- DB_PERF_SEL_prezl_src_in_squads = 0xdf,
- DB_PERF_SEL_prezl_src_in_squads_unrolled = 0xe0,
- DB_PERF_SEL_prezl_src_in_tile_rate = 0xe1,
- DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 0xe2,
- DB_PERF_SEL_prezl_src_out_stall = 0xe3,
- DB_PERF_SEL_postzl_src_in_sends = 0xe4,
- DB_PERF_SEL_postzl_src_in_stall = 0xe5,
- DB_PERF_SEL_postzl_src_in_squads = 0xe6,
- DB_PERF_SEL_postzl_src_in_squads_unrolled = 0xe7,
- DB_PERF_SEL_postzl_src_in_tile_rate = 0xe8,
- DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 0xe9,
- DB_PERF_SEL_postzl_src_out_stall = 0xea,
- DB_PERF_SEL_esr_ps_src_in_sends = 0xeb,
- DB_PERF_SEL_esr_ps_src_in_stall = 0xec,
- DB_PERF_SEL_esr_ps_src_in_squads = 0xed,
- DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 0xee,
- DB_PERF_SEL_esr_ps_src_in_tile_rate = 0xef,
- DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 0xf0,
- DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate= 0xf1,
- DB_PERF_SEL_esr_ps_src_out_stall = 0xf2,
- DB_PERF_SEL_depth_bounds_qtiles_culled = 0xf3,
- DB_PERF_SEL_PreZ_Samples_failing_DB = 0xf4,
- DB_PERF_SEL_PostZ_Samples_failing_DB = 0xf5,
- DB_PERF_SEL_flush_compressed = 0xf6,
- DB_PERF_SEL_flush_plane_le4 = 0xf7,
- DB_PERF_SEL_tiles_z_fully_summarized = 0xf8,
- DB_PERF_SEL_tiles_stencil_fully_summarized = 0xf9,
- DB_PERF_SEL_tiles_z_clear_on_expclear = 0xfa,
- DB_PERF_SEL_tiles_s_clear_on_expclear = 0xfb,
- DB_PERF_SEL_tiles_decomp_on_expclear = 0xfc,
- DB_PERF_SEL_tiles_compressed_to_decompressed = 0xfd,
- DB_PERF_SEL_Op_Pipe_Prez_Busy = 0xfe,
- DB_PERF_SEL_Op_Pipe_Postz_Busy = 0xff,
- DB_PERF_SEL_di_dt_stall = 0x100,
- DB_PERF_SEL_DB_SC_quad_double_quad = 0x101,
- DB_PERF_SEL_SX_DB_quad_export_quads = 0x102,
- DB_PERF_SEL_SX_DB_quad_double_format = 0x103,
- DB_PERF_SEL_SX_DB_quad_fast_format = 0x104,
- DB_PERF_SEL_SX_DB_quad_slow_format = 0x105,
- DB_PERF_SEL_DB_CB_lquad_export_quads = 0x106,
- DB_PERF_SEL_DB_CB_lquad_double_format = 0x107,
- DB_PERF_SEL_DB_CB_lquad_fast_format = 0x108,
- DB_PERF_SEL_DB_CB_lquad_slow_format = 0x109,
-} PerfCounter_Vals;
-typedef enum RingCounterControl {
- COUNTER_RING_SPLIT = 0x0,
- COUNTER_RING_0 = 0x1,
- COUNTER_RING_1 = 0x2,
-} RingCounterControl;
-typedef enum PixelPipeCounterId {
- PIXEL_PIPE_OCCLUSION_COUNT_0 = 0x0,
- PIXEL_PIPE_OCCLUSION_COUNT_1 = 0x1,
- PIXEL_PIPE_OCCLUSION_COUNT_2 = 0x2,
- PIXEL_PIPE_OCCLUSION_COUNT_3 = 0x3,
- PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 0x4,
- PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 0x5,
- PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 0x6,
- PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 0x7,
-} PixelPipeCounterId;
-typedef enum PixelPipeStride {
- PIXEL_PIPE_STRIDE_32_BITS = 0x0,
- PIXEL_PIPE_STRIDE_64_BITS = 0x1,
- PIXEL_PIPE_STRIDE_128_BITS = 0x2,
- PIXEL_PIPE_STRIDE_256_BITS = 0x3,
-} PixelPipeStride;
-typedef enum GB_EDC_DED_MODE {
- GB_EDC_DED_MODE_LOG = 0x0,
- GB_EDC_DED_MODE_HALT = 0x1,
- GB_EDC_DED_MODE_INT_HALT = 0x2,
-} GB_EDC_DED_MODE;
-#define GB_TILING_CONFIG_TABLE_SIZE 0x20
-#define GB_TILING_CONFIG_MACROTABLE_SIZE 0x10
-typedef enum GRBM_PERF_SEL {
- GRBM_PERF_SEL_COUNT = 0x0,
- GRBM_PERF_SEL_USER_DEFINED = 0x1,
- GRBM_PERF_SEL_GUI_ACTIVE = 0x2,
- GRBM_PERF_SEL_CP_BUSY = 0x3,
- GRBM_PERF_SEL_CP_COHER_BUSY = 0x4,
- GRBM_PERF_SEL_CP_DMA_BUSY = 0x5,
- GRBM_PERF_SEL_CB_BUSY = 0x6,
- GRBM_PERF_SEL_DB_BUSY = 0x7,
- GRBM_PERF_SEL_PA_BUSY = 0x8,
- GRBM_PERF_SEL_SC_BUSY = 0x9,
- GRBM_PERF_SEL_RESERVED_6 = 0xa,
- GRBM_PERF_SEL_SPI_BUSY = 0xb,
- GRBM_PERF_SEL_SX_BUSY = 0xc,
- GRBM_PERF_SEL_TA_BUSY = 0xd,
- GRBM_PERF_SEL_CB_CLEAN = 0xe,
- GRBM_PERF_SEL_DB_CLEAN = 0xf,
- GRBM_PERF_SEL_RESERVED_5 = 0x10,
- GRBM_PERF_SEL_VGT_BUSY = 0x11,
- GRBM_PERF_SEL_RESERVED_4 = 0x12,
- GRBM_PERF_SEL_RESERVED_3 = 0x13,
- GRBM_PERF_SEL_RESERVED_2 = 0x14,
- GRBM_PERF_SEL_RESERVED_1 = 0x15,
- GRBM_PERF_SEL_RESERVED_0 = 0x16,
- GRBM_PERF_SEL_IA_BUSY = 0x17,
- GRBM_PERF_SEL_IA_NO_DMA_BUSY = 0x18,
- GRBM_PERF_SEL_GDS_BUSY = 0x19,
- GRBM_PERF_SEL_BCI_BUSY = 0x1a,
- GRBM_PERF_SEL_RLC_BUSY = 0x1b,
- GRBM_PERF_SEL_TC_BUSY = 0x1c,
- GRBM_PERF_SEL_CPG_BUSY = 0x1d,
- GRBM_PERF_SEL_CPC_BUSY = 0x1e,
- GRBM_PERF_SEL_CPF_BUSY = 0x1f,
- GRBM_PERF_SEL_WD_BUSY = 0x20,
- GRBM_PERF_SEL_WD_NO_DMA_BUSY = 0x21,
-} GRBM_PERF_SEL;
-typedef enum GRBM_SE0_PERF_SEL {
- GRBM_SE0_PERF_SEL_COUNT = 0x0,
- GRBM_SE0_PERF_SEL_USER_DEFINED = 0x1,
- GRBM_SE0_PERF_SEL_CB_BUSY = 0x2,
- GRBM_SE0_PERF_SEL_DB_BUSY = 0x3,
- GRBM_SE0_PERF_SEL_SC_BUSY = 0x4,
- GRBM_SE0_PERF_SEL_RESERVED_1 = 0x5,
- GRBM_SE0_PERF_SEL_SPI_BUSY = 0x6,
- GRBM_SE0_PERF_SEL_SX_BUSY = 0x7,
- GRBM_SE0_PERF_SEL_TA_BUSY = 0x8,
- GRBM_SE0_PERF_SEL_CB_CLEAN = 0x9,
- GRBM_SE0_PERF_SEL_DB_CLEAN = 0xa,
- GRBM_SE0_PERF_SEL_RESERVED_0 = 0xb,
- GRBM_SE0_PERF_SEL_PA_BUSY = 0xc,
- GRBM_SE0_PERF_SEL_VGT_BUSY = 0xd,
- GRBM_SE0_PERF_SEL_BCI_BUSY = 0xe,
-} GRBM_SE0_PERF_SEL;
-typedef enum GRBM_SE1_PERF_SEL {
- GRBM_SE1_PERF_SEL_COUNT = 0x0,
- GRBM_SE1_PERF_SEL_USER_DEFINED = 0x1,
- GRBM_SE1_PERF_SEL_CB_BUSY = 0x2,
- GRBM_SE1_PERF_SEL_DB_BUSY = 0x3,
- GRBM_SE1_PERF_SEL_SC_BUSY = 0x4,
- GRBM_SE1_PERF_SEL_RESERVED_1 = 0x5,
- GRBM_SE1_PERF_SEL_SPI_BUSY = 0x6,
- GRBM_SE1_PERF_SEL_SX_BUSY = 0x7,
- GRBM_SE1_PERF_SEL_TA_BUSY = 0x8,
- GRBM_SE1_PERF_SEL_CB_CLEAN = 0x9,
- GRBM_SE1_PERF_SEL_DB_CLEAN = 0xa,
- GRBM_SE1_PERF_SEL_RESERVED_0 = 0xb,
- GRBM_SE1_PERF_SEL_PA_BUSY = 0xc,
- GRBM_SE1_PERF_SEL_VGT_BUSY = 0xd,
- GRBM_SE1_PERF_SEL_BCI_BUSY = 0xe,
-} GRBM_SE1_PERF_SEL;
-typedef enum GRBM_SE2_PERF_SEL {
- GRBM_SE2_PERF_SEL_COUNT = 0x0,
- GRBM_SE2_PERF_SEL_USER_DEFINED = 0x1,
- GRBM_SE2_PERF_SEL_CB_BUSY = 0x2,
- GRBM_SE2_PERF_SEL_DB_BUSY = 0x3,
- GRBM_SE2_PERF_SEL_SC_BUSY = 0x4,
- GRBM_SE2_PERF_SEL_RESERVED_1 = 0x5,
- GRBM_SE2_PERF_SEL_SPI_BUSY = 0x6,
- GRBM_SE2_PERF_SEL_SX_BUSY = 0x7,
- GRBM_SE2_PERF_SEL_TA_BUSY = 0x8,
- GRBM_SE2_PERF_SEL_CB_CLEAN = 0x9,
- GRBM_SE2_PERF_SEL_DB_CLEAN = 0xa,
- GRBM_SE2_PERF_SEL_RESERVED_0 = 0xb,
- GRBM_SE2_PERF_SEL_PA_BUSY = 0xc,
- GRBM_SE2_PERF_SEL_VGT_BUSY = 0xd,
- GRBM_SE2_PERF_SEL_BCI_BUSY = 0xe,
-} GRBM_SE2_PERF_SEL;
-typedef enum GRBM_SE3_PERF_SEL {
- GRBM_SE3_PERF_SEL_COUNT = 0x0,
- GRBM_SE3_PERF_SEL_USER_DEFINED = 0x1,
- GRBM_SE3_PERF_SEL_CB_BUSY = 0x2,
- GRBM_SE3_PERF_SEL_DB_BUSY = 0x3,
- GRBM_SE3_PERF_SEL_SC_BUSY = 0x4,
- GRBM_SE3_PERF_SEL_RESERVED_1 = 0x5,
- GRBM_SE3_PERF_SEL_SPI_BUSY = 0x6,
- GRBM_SE3_PERF_SEL_SX_BUSY = 0x7,
- GRBM_SE3_PERF_SEL_TA_BUSY = 0x8,
- GRBM_SE3_PERF_SEL_CB_CLEAN = 0x9,
- GRBM_SE3_PERF_SEL_DB_CLEAN = 0xa,
- GRBM_SE3_PERF_SEL_RESERVED_0 = 0xb,
- GRBM_SE3_PERF_SEL_PA_BUSY = 0xc,
- GRBM_SE3_PERF_SEL_VGT_BUSY = 0xd,
- GRBM_SE3_PERF_SEL_BCI_BUSY = 0xe,
-} GRBM_SE3_PERF_SEL;
-typedef enum SU_PERFCNT_SEL {
- PERF_PAPC_PASX_REQ = 0x0,
- PERF_PAPC_PASX_DISABLE_PIPE = 0x1,
- PERF_PAPC_PASX_FIRST_VECTOR = 0x2,
- PERF_PAPC_PASX_SECOND_VECTOR = 0x3,
- PERF_PAPC_PASX_FIRST_DEAD = 0x4,
- PERF_PAPC_PASX_SECOND_DEAD = 0x5,
- PERF_PAPC_PASX_VTX_KILL_DISCARD = 0x6,
- PERF_PAPC_PASX_VTX_NAN_DISCARD = 0x7,
- PERF_PAPC_PA_INPUT_PRIM = 0x8,
- PERF_PAPC_PA_INPUT_NULL_PRIM = 0x9,
- PERF_PAPC_PA_INPUT_EVENT_FLAG = 0xa,
- PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 0xb,
- PERF_PAPC_PA_INPUT_END_OF_PACKET = 0xc,
- PERF_PAPC_PA_INPUT_EXTENDED_EVENT = 0xd,
- PERF_PAPC_CLPR_CULL_PRIM = 0xe,
- PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 0xf,
- PERF_PAPC_CLPR_VV_CULL_PRIM = 0x10,
- PERF_PAPC_CLPR_UCP_CULL_PRIM = 0x11,
- PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 0x12,
- PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 0x13,
- PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 0x14,
- PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 0x15,
- PERF_PAPC_CLPR_VV_CLIP_PRIM = 0x16,
- PERF_PAPC_CLPR_UCP_CLIP_PRIM = 0x17,
- PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 0x18,
- PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 0x19,
- PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 0x1a,
- PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 0x1b,
- PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 0x1c,
- PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 0x1d,
- PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 = 0x1e,
- PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 0x1f,
- PERF_PAPC_CLPR_CLIP_PLANE_FAR = 0x20,
- PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 0x21,
- PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 0x22,
- PERF_PAPC_CLPR_CLIP_PLANE_TOP = 0x23,
- PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 0x24,
- PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM = 0x25,
- PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 0x26,
- PERF_PAPC_CLSM_NULL_PRIM = 0x27,
- PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 0x28,
- PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 0x29,
- PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 0x2a,
- PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 0x2b,
- PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 0x2c,
- PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 0x2d,
- PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 0x2e,
- PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 = 0x2f,
- PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 0x30,
- PERF_PAPC_SU_INPUT_PRIM = 0x31,
- PERF_PAPC_SU_INPUT_CLIP_PRIM = 0x32,
- PERF_PAPC_SU_INPUT_NULL_PRIM = 0x33,
- PERF_PAPC_SU_INPUT_PRIM_DUAL = 0x34,
- PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 0x35,
- PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 0x36,
- PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 0x37,
- PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 0x38,
- PERF_PAPC_SU_POLYMODE_FACE_CULL = 0x39,
- PERF_PAPC_SU_POLYMODE_BACK_CULL = 0x3a,
- PERF_PAPC_SU_POLYMODE_FRONT_CULL = 0x3b,
- PERF_PAPC_SU_POLYMODE_INVALID_FILL = 0x3c,
- PERF_PAPC_SU_OUTPUT_PRIM = 0x3d,
- PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 0x3e,
- PERF_PAPC_SU_OUTPUT_NULL_PRIM = 0x3f,
- PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 0x40,
- PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 0x41,
- PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 0x42,
- PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 0x43,
- PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 0x44,
- PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 0x45,
- PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 0x46,
- PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 0x47,
- PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 0x48,
- PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 0x49,
- PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 0x4a,
- PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 0x4b,
- PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 0x4c,
- PERF_PAPC_PASX_REQ_IDLE = 0x4d,
- PERF_PAPC_PASX_REQ_BUSY = 0x4e,
- PERF_PAPC_PASX_REQ_STALLED = 0x4f,
- PERF_PAPC_PASX_REC_IDLE = 0x50,
- PERF_PAPC_PASX_REC_BUSY = 0x51,
- PERF_PAPC_PASX_REC_STARVED_SX = 0x52,
- PERF_PAPC_PASX_REC_STALLED = 0x53,
- PERF_PAPC_PASX_REC_STALLED_POS_MEM = 0x54,
- PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 0x55,
- PERF_PAPC_CCGSM_IDLE = 0x56,
- PERF_PAPC_CCGSM_BUSY = 0x57,
- PERF_PAPC_CCGSM_STALLED = 0x58,
- PERF_PAPC_CLPRIM_IDLE = 0x59,
- PERF_PAPC_CLPRIM_BUSY = 0x5a,
- PERF_PAPC_CLPRIM_STALLED = 0x5b,
- PERF_PAPC_CLPRIM_STARVED_CCGSM = 0x5c,
- PERF_PAPC_CLIPSM_IDLE = 0x5d,
- PERF_PAPC_CLIPSM_BUSY = 0x5e,
- PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 0x5f,
- PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 0x60,
- PERF_PAPC_CLIPSM_WAIT_CLIPGA = 0x61,
- PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 0x62,
- PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 0x63,
- PERF_PAPC_CLIPGA_IDLE = 0x64,
- PERF_PAPC_CLIPGA_BUSY = 0x65,
- PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 0x66,
- PERF_PAPC_CLIPGA_STALLED = 0x67,
- PERF_PAPC_CLIP_IDLE = 0x68,
- PERF_PAPC_CLIP_BUSY = 0x69,
- PERF_PAPC_SU_IDLE = 0x6a,
- PERF_PAPC_SU_BUSY = 0x6b,
- PERF_PAPC_SU_STARVED_CLIP = 0x6c,
- PERF_PAPC_SU_STALLED_SC = 0x6d,
- PERF_PAPC_CL_DYN_SCLK_VLD = 0x6e,
- PERF_PAPC_SU_DYN_SCLK_VLD = 0x6f,
- PERF_PAPC_PA_REG_SCLK_VLD = 0x70,
- PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL = 0x71,
- PERF_PAPC_PASX_SE0_REQ = 0x72,
- PERF_PAPC_PASX_SE1_REQ = 0x73,
- PERF_PAPC_PASX_SE0_FIRST_VECTOR = 0x74,
- PERF_PAPC_PASX_SE0_SECOND_VECTOR = 0x75,
- PERF_PAPC_PASX_SE1_FIRST_VECTOR = 0x76,
- PERF_PAPC_PASX_SE1_SECOND_VECTOR = 0x77,
- PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 0x78,
- PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 0x79,
- PERF_PAPC_SU_SE01_PRIM_FILTER_CULL = 0x7a,
- PERF_PAPC_SU_SE0_OUTPUT_PRIM = 0x7b,
- PERF_PAPC_SU_SE1_OUTPUT_PRIM = 0x7c,
- PERF_PAPC_SU_SE01_OUTPUT_PRIM = 0x7d,
- PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 0x7e,
- PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 0x7f,
- PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM = 0x80,
- PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT = 0x81,
- PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT = 0x82,
- PERF_PAPC_SU_SE0_STALLED_SC = 0x83,
- PERF_PAPC_SU_SE1_STALLED_SC = 0x84,
- PERF_PAPC_SU_SE01_STALLED_SC = 0x85,
- PERF_PAPC_CLSM_CLIPPING_PRIM = 0x86,
- PERF_PAPC_SU_CULLED_PRIM = 0x87,
- PERF_PAPC_SU_OUTPUT_EOPG = 0x88,
- PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 0x89,
- PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 0x8a,
- PERF_PAPC_SU_SE2_OUTPUT_PRIM = 0x8b,
- PERF_PAPC_SU_SE3_OUTPUT_PRIM = 0x8c,
- PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 0x8d,
- PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 0x8e,
- PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET = 0x8f,
- PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET = 0x90,
- PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET = 0x91,
- PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET = 0x92,
- PERF_PAPC_SU_SE0_OUTPUT_EOPG = 0x93,
- PERF_PAPC_SU_SE1_OUTPUT_EOPG = 0x94,
- PERF_PAPC_SU_SE2_OUTPUT_EOPG = 0x95,
- PERF_PAPC_SU_SE3_OUTPUT_EOPG = 0x96,
- PERF_PAPC_SU_SE2_STALLED_SC = 0x97,
- PERF_PAPC_SU_SE3_STALLED_SC = 0x98,
-} SU_PERFCNT_SEL;
-typedef enum SC_PERFCNT_SEL {
- SC_SRPS_WINDOW_VALID = 0x0,
- SC_PSSW_WINDOW_VALID = 0x1,
- SC_TPQZ_WINDOW_VALID = 0x2,
- SC_QZQP_WINDOW_VALID = 0x3,
- SC_TRPK_WINDOW_VALID = 0x4,
- SC_SRPS_WINDOW_VALID_BUSY = 0x5,
- SC_PSSW_WINDOW_VALID_BUSY = 0x6,
- SC_TPQZ_WINDOW_VALID_BUSY = 0x7,
- SC_QZQP_WINDOW_VALID_BUSY = 0x8,
- SC_TRPK_WINDOW_VALID_BUSY = 0x9,
- SC_STARVED_BY_PA = 0xa,
- SC_STALLED_BY_PRIMFIFO = 0xb,
- SC_STALLED_BY_DB_TILE = 0xc,
- SC_STARVED_BY_DB_TILE = 0xd,
- SC_STALLED_BY_TILEORDERFIFO = 0xe,
- SC_STALLED_BY_TILEFIFO = 0xf,
- SC_STALLED_BY_DB_QUAD = 0x10,
- SC_STARVED_BY_DB_QUAD = 0x11,
- SC_STALLED_BY_QUADFIFO = 0x12,
- SC_STALLED_BY_BCI = 0x13,
- SC_STALLED_BY_SPI = 0x14,
- SC_SCISSOR_DISCARD = 0x15,
- SC_BB_DISCARD = 0x16,
- SC_SUPERTILE_COUNT = 0x17,
- SC_SUPERTILE_PER_PRIM_H0 = 0x18,
- SC_SUPERTILE_PER_PRIM_H1 = 0x19,
- SC_SUPERTILE_PER_PRIM_H2 = 0x1a,
- SC_SUPERTILE_PER_PRIM_H3 = 0x1b,
- SC_SUPERTILE_PER_PRIM_H4 = 0x1c,
- SC_SUPERTILE_PER_PRIM_H5 = 0x1d,
- SC_SUPERTILE_PER_PRIM_H6 = 0x1e,
- SC_SUPERTILE_PER_PRIM_H7 = 0x1f,
- SC_SUPERTILE_PER_PRIM_H8 = 0x20,
- SC_SUPERTILE_PER_PRIM_H9 = 0x21,
- SC_SUPERTILE_PER_PRIM_H10 = 0x22,
- SC_SUPERTILE_PER_PRIM_H11 = 0x23,
- SC_SUPERTILE_PER_PRIM_H12 = 0x24,
- SC_SUPERTILE_PER_PRIM_H13 = 0x25,
- SC_SUPERTILE_PER_PRIM_H14 = 0x26,
- SC_SUPERTILE_PER_PRIM_H15 = 0x27,
- SC_SUPERTILE_PER_PRIM_H16 = 0x28,
- SC_TILE_PER_PRIM_H0 = 0x29,
- SC_TILE_PER_PRIM_H1 = 0x2a,
- SC_TILE_PER_PRIM_H2 = 0x2b,
- SC_TILE_PER_PRIM_H3 = 0x2c,
- SC_TILE_PER_PRIM_H4 = 0x2d,
- SC_TILE_PER_PRIM_H5 = 0x2e,
- SC_TILE_PER_PRIM_H6 = 0x2f,
- SC_TILE_PER_PRIM_H7 = 0x30,
- SC_TILE_PER_PRIM_H8 = 0x31,
- SC_TILE_PER_PRIM_H9 = 0x32,
- SC_TILE_PER_PRIM_H10 = 0x33,
- SC_TILE_PER_PRIM_H11 = 0x34,
- SC_TILE_PER_PRIM_H12 = 0x35,
- SC_TILE_PER_PRIM_H13 = 0x36,
- SC_TILE_PER_PRIM_H14 = 0x37,
- SC_TILE_PER_PRIM_H15 = 0x38,
- SC_TILE_PER_PRIM_H16 = 0x39,
- SC_TILE_PER_SUPERTILE_H0 = 0x3a,
- SC_TILE_PER_SUPERTILE_H1 = 0x3b,
- SC_TILE_PER_SUPERTILE_H2 = 0x3c,
- SC_TILE_PER_SUPERTILE_H3 = 0x3d,
- SC_TILE_PER_SUPERTILE_H4 = 0x3e,
- SC_TILE_PER_SUPERTILE_H5 = 0x3f,
- SC_TILE_PER_SUPERTILE_H6 = 0x40,
- SC_TILE_PER_SUPERTILE_H7 = 0x41,
- SC_TILE_PER_SUPERTILE_H8 = 0x42,
- SC_TILE_PER_SUPERTILE_H9 = 0x43,
- SC_TILE_PER_SUPERTILE_H10 = 0x44,
- SC_TILE_PER_SUPERTILE_H11 = 0x45,
- SC_TILE_PER_SUPERTILE_H12 = 0x46,
- SC_TILE_PER_SUPERTILE_H13 = 0x47,
- SC_TILE_PER_SUPERTILE_H14 = 0x48,
- SC_TILE_PER_SUPERTILE_H15 = 0x49,
- SC_TILE_PER_SUPERTILE_H16 = 0x4a,
- SC_TILE_PICKED_H1 = 0x4b,
- SC_TILE_PICKED_H2 = 0x4c,
- SC_TILE_PICKED_H3 = 0x4d,
- SC_TILE_PICKED_H4 = 0x4e,
- SC_QZ0_MULTI_GPU_TILE_DISCARD = 0x4f,
- SC_QZ1_MULTI_GPU_TILE_DISCARD = 0x50,
- SC_QZ2_MULTI_GPU_TILE_DISCARD = 0x51,
- SC_QZ3_MULTI_GPU_TILE_DISCARD = 0x52,
- SC_QZ0_TILE_COUNT = 0x53,
- SC_QZ1_TILE_COUNT = 0x54,
- SC_QZ2_TILE_COUNT = 0x55,
- SC_QZ3_TILE_COUNT = 0x56,
- SC_QZ0_TILE_COVERED_COUNT = 0x57,
- SC_QZ1_TILE_COVERED_COUNT = 0x58,
- SC_QZ2_TILE_COVERED_COUNT = 0x59,
- SC_QZ3_TILE_COVERED_COUNT = 0x5a,
- SC_QZ0_TILE_NOT_COVERED_COUNT = 0x5b,
- SC_QZ1_TILE_NOT_COVERED_COUNT = 0x5c,
- SC_QZ2_TILE_NOT_COVERED_COUNT = 0x5d,
- SC_QZ3_TILE_NOT_COVERED_COUNT = 0x5e,
- SC_QZ0_QUAD_PER_TILE_H0 = 0x5f,
- SC_QZ0_QUAD_PER_TILE_H1 = 0x60,
- SC_QZ0_QUAD_PER_TILE_H2 = 0x61,
- SC_QZ0_QUAD_PER_TILE_H3 = 0x62,
- SC_QZ0_QUAD_PER_TILE_H4 = 0x63,
- SC_QZ0_QUAD_PER_TILE_H5 = 0x64,
- SC_QZ0_QUAD_PER_TILE_H6 = 0x65,
- SC_QZ0_QUAD_PER_TILE_H7 = 0x66,
- SC_QZ0_QUAD_PER_TILE_H8 = 0x67,
- SC_QZ0_QUAD_PER_TILE_H9 = 0x68,
- SC_QZ0_QUAD_PER_TILE_H10 = 0x69,
- SC_QZ0_QUAD_PER_TILE_H11 = 0x6a,
- SC_QZ0_QUAD_PER_TILE_H12 = 0x6b,
- SC_QZ0_QUAD_PER_TILE_H13 = 0x6c,
- SC_QZ0_QUAD_PER_TILE_H14 = 0x6d,
- SC_QZ0_QUAD_PER_TILE_H15 = 0x6e,
- SC_QZ0_QUAD_PER_TILE_H16 = 0x6f,
- SC_QZ1_QUAD_PER_TILE_H0 = 0x70,
- SC_QZ1_QUAD_PER_TILE_H1 = 0x71,
- SC_QZ1_QUAD_PER_TILE_H2 = 0x72,
- SC_QZ1_QUAD_PER_TILE_H3 = 0x73,
- SC_QZ1_QUAD_PER_TILE_H4 = 0x74,
- SC_QZ1_QUAD_PER_TILE_H5 = 0x75,
- SC_QZ1_QUAD_PER_TILE_H6 = 0x76,
- SC_QZ1_QUAD_PER_TILE_H7 = 0x77,
- SC_QZ1_QUAD_PER_TILE_H8 = 0x78,
- SC_QZ1_QUAD_PER_TILE_H9 = 0x79,
- SC_QZ1_QUAD_PER_TILE_H10 = 0x7a,
- SC_QZ1_QUAD_PER_TILE_H11 = 0x7b,
- SC_QZ1_QUAD_PER_TILE_H12 = 0x7c,
- SC_QZ1_QUAD_PER_TILE_H13 = 0x7d,
- SC_QZ1_QUAD_PER_TILE_H14 = 0x7e,
- SC_QZ1_QUAD_PER_TILE_H15 = 0x7f,
- SC_QZ1_QUAD_PER_TILE_H16 = 0x80,
- SC_QZ2_QUAD_PER_TILE_H0 = 0x81,
- SC_QZ2_QUAD_PER_TILE_H1 = 0x82,
- SC_QZ2_QUAD_PER_TILE_H2 = 0x83,
- SC_QZ2_QUAD_PER_TILE_H3 = 0x84,
- SC_QZ2_QUAD_PER_TILE_H4 = 0x85,
- SC_QZ2_QUAD_PER_TILE_H5 = 0x86,
- SC_QZ2_QUAD_PER_TILE_H6 = 0x87,
- SC_QZ2_QUAD_PER_TILE_H7 = 0x88,
- SC_QZ2_QUAD_PER_TILE_H8 = 0x89,
- SC_QZ2_QUAD_PER_TILE_H9 = 0x8a,
- SC_QZ2_QUAD_PER_TILE_H10 = 0x8b,
- SC_QZ2_QUAD_PER_TILE_H11 = 0x8c,
- SC_QZ2_QUAD_PER_TILE_H12 = 0x8d,
- SC_QZ2_QUAD_PER_TILE_H13 = 0x8e,
- SC_QZ2_QUAD_PER_TILE_H14 = 0x8f,
- SC_QZ2_QUAD_PER_TILE_H15 = 0x90,
- SC_QZ2_QUAD_PER_TILE_H16 = 0x91,
- SC_QZ3_QUAD_PER_TILE_H0 = 0x92,
- SC_QZ3_QUAD_PER_TILE_H1 = 0x93,
- SC_QZ3_QUAD_PER_TILE_H2 = 0x94,
- SC_QZ3_QUAD_PER_TILE_H3 = 0x95,
- SC_QZ3_QUAD_PER_TILE_H4 = 0x96,
- SC_QZ3_QUAD_PER_TILE_H5 = 0x97,
- SC_QZ3_QUAD_PER_TILE_H6 = 0x98,
- SC_QZ3_QUAD_PER_TILE_H7 = 0x99,
- SC_QZ3_QUAD_PER_TILE_H8 = 0x9a,
- SC_QZ3_QUAD_PER_TILE_H9 = 0x9b,
- SC_QZ3_QUAD_PER_TILE_H10 = 0x9c,
- SC_QZ3_QUAD_PER_TILE_H11 = 0x9d,
- SC_QZ3_QUAD_PER_TILE_H12 = 0x9e,
- SC_QZ3_QUAD_PER_TILE_H13 = 0x9f,
- SC_QZ3_QUAD_PER_TILE_H14 = 0xa0,
- SC_QZ3_QUAD_PER_TILE_H15 = 0xa1,
- SC_QZ3_QUAD_PER_TILE_H16 = 0xa2,
- SC_QZ0_QUAD_COUNT = 0xa3,
- SC_QZ1_QUAD_COUNT = 0xa4,
- SC_QZ2_QUAD_COUNT = 0xa5,
- SC_QZ3_QUAD_COUNT = 0xa6,
- SC_P0_HIZ_TILE_COUNT = 0xa7,
- SC_P1_HIZ_TILE_COUNT = 0xa8,
- SC_P2_HIZ_TILE_COUNT = 0xa9,
- SC_P3_HIZ_TILE_COUNT = 0xaa,
- SC_P0_HIZ_QUAD_PER_TILE_H0 = 0xab,
- SC_P0_HIZ_QUAD_PER_TILE_H1 = 0xac,
- SC_P0_HIZ_QUAD_PER_TILE_H2 = 0xad,
- SC_P0_HIZ_QUAD_PER_TILE_H3 = 0xae,
- SC_P0_HIZ_QUAD_PER_TILE_H4 = 0xaf,
- SC_P0_HIZ_QUAD_PER_TILE_H5 = 0xb0,
- SC_P0_HIZ_QUAD_PER_TILE_H6 = 0xb1,
- SC_P0_HIZ_QUAD_PER_TILE_H7 = 0xb2,
- SC_P0_HIZ_QUAD_PER_TILE_H8 = 0xb3,
- SC_P0_HIZ_QUAD_PER_TILE_H9 = 0xb4,
- SC_P0_HIZ_QUAD_PER_TILE_H10 = 0xb5,
- SC_P0_HIZ_QUAD_PER_TILE_H11 = 0xb6,
- SC_P0_HIZ_QUAD_PER_TILE_H12 = 0xb7,
- SC_P0_HIZ_QUAD_PER_TILE_H13 = 0xb8,
- SC_P0_HIZ_QUAD_PER_TILE_H14 = 0xb9,
- SC_P0_HIZ_QUAD_PER_TILE_H15 = 0xba,
- SC_P0_HIZ_QUAD_PER_TILE_H16 = 0xbb,
- SC_P1_HIZ_QUAD_PER_TILE_H0 = 0xbc,
- SC_P1_HIZ_QUAD_PER_TILE_H1 = 0xbd,
- SC_P1_HIZ_QUAD_PER_TILE_H2 = 0xbe,
- SC_P1_HIZ_QUAD_PER_TILE_H3 = 0xbf,
- SC_P1_HIZ_QUAD_PER_TILE_H4 = 0xc0,
- SC_P1_HIZ_QUAD_PER_TILE_H5 = 0xc1,
- SC_P1_HIZ_QUAD_PER_TILE_H6 = 0xc2,
- SC_P1_HIZ_QUAD_PER_TILE_H7 = 0xc3,
- SC_P1_HIZ_QUAD_PER_TILE_H8 = 0xc4,
- SC_P1_HIZ_QUAD_PER_TILE_H9 = 0xc5,
- SC_P1_HIZ_QUAD_PER_TILE_H10 = 0xc6,
- SC_P1_HIZ_QUAD_PER_TILE_H11 = 0xc7,
- SC_P1_HIZ_QUAD_PER_TILE_H12 = 0xc8,
- SC_P1_HIZ_QUAD_PER_TILE_H13 = 0xc9,
- SC_P1_HIZ_QUAD_PER_TILE_H14 = 0xca,
- SC_P1_HIZ_QUAD_PER_TILE_H15 = 0xcb,
- SC_P1_HIZ_QUAD_PER_TILE_H16 = 0xcc,
- SC_P2_HIZ_QUAD_PER_TILE_H0 = 0xcd,
- SC_P2_HIZ_QUAD_PER_TILE_H1 = 0xce,
- SC_P2_HIZ_QUAD_PER_TILE_H2 = 0xcf,
- SC_P2_HIZ_QUAD_PER_TILE_H3 = 0xd0,
- SC_P2_HIZ_QUAD_PER_TILE_H4 = 0xd1,
- SC_P2_HIZ_QUAD_PER_TILE_H5 = 0xd2,
- SC_P2_HIZ_QUAD_PER_TILE_H6 = 0xd3,
- SC_P2_HIZ_QUAD_PER_TILE_H7 = 0xd4,
- SC_P2_HIZ_QUAD_PER_TILE_H8 = 0xd5,
- SC_P2_HIZ_QUAD_PER_TILE_H9 = 0xd6,
- SC_P2_HIZ_QUAD_PER_TILE_H10 = 0xd7,
- SC_P2_HIZ_QUAD_PER_TILE_H11 = 0xd8,
- SC_P2_HIZ_QUAD_PER_TILE_H12 = 0xd9,
- SC_P2_HIZ_QUAD_PER_TILE_H13 = 0xda,
- SC_P2_HIZ_QUAD_PER_TILE_H14 = 0xdb,
- SC_P2_HIZ_QUAD_PER_TILE_H15 = 0xdc,
- SC_P2_HIZ_QUAD_PER_TILE_H16 = 0xdd,
- SC_P3_HIZ_QUAD_PER_TILE_H0 = 0xde,
- SC_P3_HIZ_QUAD_PER_TILE_H1 = 0xdf,
- SC_P3_HIZ_QUAD_PER_TILE_H2 = 0xe0,
- SC_P3_HIZ_QUAD_PER_TILE_H3 = 0xe1,
- SC_P3_HIZ_QUAD_PER_TILE_H4 = 0xe2,
- SC_P3_HIZ_QUAD_PER_TILE_H5 = 0xe3,
- SC_P3_HIZ_QUAD_PER_TILE_H6 = 0xe4,
- SC_P3_HIZ_QUAD_PER_TILE_H7 = 0xe5,
- SC_P3_HIZ_QUAD_PER_TILE_H8 = 0xe6,
- SC_P3_HIZ_QUAD_PER_TILE_H9 = 0xe7,
- SC_P3_HIZ_QUAD_PER_TILE_H10 = 0xe8,
- SC_P3_HIZ_QUAD_PER_TILE_H11 = 0xe9,
- SC_P3_HIZ_QUAD_PER_TILE_H12 = 0xea,
- SC_P3_HIZ_QUAD_PER_TILE_H13 = 0xeb,
- SC_P3_HIZ_QUAD_PER_TILE_H14 = 0xec,
- SC_P3_HIZ_QUAD_PER_TILE_H15 = 0xed,
- SC_P3_HIZ_QUAD_PER_TILE_H16 = 0xee,
- SC_P0_HIZ_QUAD_COUNT = 0xef,
- SC_P1_HIZ_QUAD_COUNT = 0xf0,
- SC_P2_HIZ_QUAD_COUNT = 0xf1,
- SC_P3_HIZ_QUAD_COUNT = 0xf2,
- SC_P0_DETAIL_QUAD_COUNT = 0xf3,
- SC_P1_DETAIL_QUAD_COUNT = 0xf4,
- SC_P2_DETAIL_QUAD_COUNT = 0xf5,
- SC_P3_DETAIL_QUAD_COUNT = 0xf6,
- SC_P0_DETAIL_QUAD_WITH_1_PIX = 0xf7,
- SC_P0_DETAIL_QUAD_WITH_2_PIX = 0xf8,
- SC_P0_DETAIL_QUAD_WITH_3_PIX = 0xf9,
- SC_P0_DETAIL_QUAD_WITH_4_PIX = 0xfa,
- SC_P1_DETAIL_QUAD_WITH_1_PIX = 0xfb,
- SC_P1_DETAIL_QUAD_WITH_2_PIX = 0xfc,
- SC_P1_DETAIL_QUAD_WITH_3_PIX = 0xfd,
- SC_P1_DETAIL_QUAD_WITH_4_PIX = 0xfe,
- SC_P2_DETAIL_QUAD_WITH_1_PIX = 0xff,
- SC_P2_DETAIL_QUAD_WITH_2_PIX = 0x100,
- SC_P2_DETAIL_QUAD_WITH_3_PIX = 0x101,
- SC_P2_DETAIL_QUAD_WITH_4_PIX = 0x102,
- SC_P3_DETAIL_QUAD_WITH_1_PIX = 0x103,
- SC_P3_DETAIL_QUAD_WITH_2_PIX = 0x104,
- SC_P3_DETAIL_QUAD_WITH_3_PIX = 0x105,
- SC_P3_DETAIL_QUAD_WITH_4_PIX = 0x106,
- SC_EARLYZ_QUAD_COUNT = 0x107,
- SC_EARLYZ_QUAD_WITH_1_PIX = 0x108,
- SC_EARLYZ_QUAD_WITH_2_PIX = 0x109,
- SC_EARLYZ_QUAD_WITH_3_PIX = 0x10a,
- SC_EARLYZ_QUAD_WITH_4_PIX = 0x10b,
- SC_PKR_QUAD_PER_ROW_H1 = 0x10c,
- SC_PKR_QUAD_PER_ROW_H2 = 0x10d,
- SC_PKR_4X2_QUAD_SPLIT = 0x10e,
- SC_PKR_4X2_FILL_QUAD = 0x10f,
- SC_PKR_END_OF_VECTOR = 0x110,
- SC_PKR_CONTROL_XFER = 0x111,
- SC_PKR_DBHANG_FORCE_EOV = 0x112,
- SC_REG_SCLK_BUSY = 0x113,
- SC_GRP0_DYN_SCLK_BUSY = 0x114,
- SC_GRP1_DYN_SCLK_BUSY = 0x115,
- SC_GRP2_DYN_SCLK_BUSY = 0x116,
- SC_GRP3_DYN_SCLK_BUSY = 0x117,
- SC_GRP4_DYN_SCLK_BUSY = 0x118,
- SC_PA0_SC_DATA_FIFO_RD = 0x119,
- SC_PA0_SC_DATA_FIFO_WE = 0x11a,
- SC_PA1_SC_DATA_FIFO_RD = 0x11b,
- SC_PA1_SC_DATA_FIFO_WE = 0x11c,
- SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x11d,
- SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 0x11e,
- SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x11f,
- SC_PS_ARB_STALLED_FROM_BELOW = 0x120,
- SC_PS_ARB_STARVED_FROM_ABOVE = 0x121,
- SC_PS_ARB_SC_BUSY = 0x122,
- SC_PS_ARB_PA_SC_BUSY = 0x123,
- SC_PA2_SC_DATA_FIFO_RD = 0x124,
- SC_PA2_SC_DATA_FIFO_WE = 0x125,
- SC_PA3_SC_DATA_FIFO_RD = 0x126,
- SC_PA3_SC_DATA_FIFO_WE = 0x127,
- SC_PA_SC_DEALLOC_0_0_WE = 0x128,
- SC_PA_SC_DEALLOC_0_1_WE = 0x129,
- SC_PA_SC_DEALLOC_1_0_WE = 0x12a,
- SC_PA_SC_DEALLOC_1_1_WE = 0x12b,
- SC_PA_SC_DEALLOC_2_0_WE = 0x12c,
- SC_PA_SC_DEALLOC_2_1_WE = 0x12d,
- SC_PA_SC_DEALLOC_3_0_WE = 0x12e,
- SC_PA_SC_DEALLOC_3_1_WE = 0x12f,
- SC_PA0_SC_EOP_WE = 0x130,
- SC_PA0_SC_EOPG_WE = 0x131,
- SC_PA0_SC_EVENT_WE = 0x132,
- SC_PA1_SC_EOP_WE = 0x133,
- SC_PA1_SC_EOPG_WE = 0x134,
- SC_PA1_SC_EVENT_WE = 0x135,
- SC_PA2_SC_EOP_WE = 0x136,
- SC_PA2_SC_EOPG_WE = 0x137,
- SC_PA2_SC_EVENT_WE = 0x138,
- SC_PA3_SC_EOP_WE = 0x139,
- SC_PA3_SC_EOPG_WE = 0x13a,
- SC_PA3_SC_EVENT_WE = 0x13b,
- SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO = 0x13c,
- SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH = 0x13d,
- SC_PS_ARB_NULL_PRIM_BUBBLE_POP = 0x13e,
- SC_PS_ARB_EOP_POP_SYNC_POP = 0x13f,
- SC_PS_ARB_EVENT_SYNC_POP = 0x140,
- SC_SC_PS_ENG_MULTICYCLE_BUBBLE = 0x141,
- SC_PA0_SC_FPOV_WE = 0x142,
- SC_PA1_SC_FPOV_WE = 0x143,
- SC_PA2_SC_FPOV_WE = 0x144,
- SC_PA3_SC_FPOV_WE = 0x145,
- SC_PA0_SC_LPOV_WE = 0x146,
- SC_PA1_SC_LPOV_WE = 0x147,
- SC_PA2_SC_LPOV_WE = 0x148,
- SC_PA3_SC_LPOV_WE = 0x149,
- SC_SC_SPI_DEALLOC_0_0 = 0x14a,
- SC_SC_SPI_DEALLOC_0_1 = 0x14b,
- SC_SC_SPI_DEALLOC_0_2 = 0x14c,
- SC_SC_SPI_DEALLOC_1_0 = 0x14d,
- SC_SC_SPI_DEALLOC_1_1 = 0x14e,
- SC_SC_SPI_DEALLOC_1_2 = 0x14f,
- SC_SC_SPI_DEALLOC_2_0 = 0x150,
- SC_SC_SPI_DEALLOC_2_1 = 0x151,
- SC_SC_SPI_DEALLOC_2_2 = 0x152,
- SC_SC_SPI_DEALLOC_3_0 = 0x153,
- SC_SC_SPI_DEALLOC_3_1 = 0x154,
- SC_SC_SPI_DEALLOC_3_2 = 0x155,
- SC_SC_SPI_FPOV_0 = 0x156,
- SC_SC_SPI_FPOV_1 = 0x157,
- SC_SC_SPI_FPOV_2 = 0x158,
- SC_SC_SPI_FPOV_3 = 0x159,
- SC_SC_SPI_EVENT = 0x15a,
- SC_PS_TS_EVENT_FIFO_PUSH = 0x15b,
- SC_PS_TS_EVENT_FIFO_POP = 0x15c,
- SC_PS_CTX_DONE_FIFO_PUSH = 0x15d,
- SC_PS_CTX_DONE_FIFO_POP = 0x15e,
- SC_MULTICYCLE_BUBBLE_FREEZE = 0x15f,
- SC_EOP_SYNC_WINDOW = 0x160,
- SC_PA0_SC_NULL_WE = 0x161,
- SC_PA0_SC_NULL_DEALLOC_WE = 0x162,
- SC_PA0_SC_DATA_FIFO_EOPG_RD = 0x163,
- SC_PA0_SC_DATA_FIFO_EOP_RD = 0x164,
- SC_PA0_SC_DEALLOC_0_RD = 0x165,
- SC_PA0_SC_DEALLOC_1_RD = 0x166,
- SC_PA1_SC_DATA_FIFO_EOPG_RD = 0x167,
- SC_PA1_SC_DATA_FIFO_EOP_RD = 0x168,
- SC_PA1_SC_DEALLOC_0_RD = 0x169,
- SC_PA1_SC_DEALLOC_1_RD = 0x16a,
- SC_PA1_SC_NULL_WE = 0x16b,
- SC_PA1_SC_NULL_DEALLOC_WE = 0x16c,
- SC_PA2_SC_DATA_FIFO_EOPG_RD = 0x16d,
- SC_PA2_SC_DATA_FIFO_EOP_RD = 0x16e,
- SC_PA2_SC_DEALLOC_0_RD = 0x16f,
- SC_PA2_SC_DEALLOC_1_RD = 0x170,
- SC_PA2_SC_NULL_WE = 0x171,
- SC_PA2_SC_NULL_DEALLOC_WE = 0x172,
- SC_PA3_SC_DATA_FIFO_EOPG_RD = 0x173,
- SC_PA3_SC_DATA_FIFO_EOP_RD = 0x174,
- SC_PA3_SC_DEALLOC_0_RD = 0x175,
- SC_PA3_SC_DEALLOC_1_RD = 0x176,
- SC_PA3_SC_NULL_WE = 0x177,
- SC_PA3_SC_NULL_DEALLOC_WE = 0x178,
- SC_PS_PA0_SC_FIFO_EMPTY = 0x179,
- SC_PS_PA0_SC_FIFO_FULL = 0x17a,
- SC_PA0_PS_DATA_SEND = 0x17b,
- SC_PS_PA1_SC_FIFO_EMPTY = 0x17c,
- SC_PS_PA1_SC_FIFO_FULL = 0x17d,
- SC_PA1_PS_DATA_SEND = 0x17e,
- SC_PS_PA2_SC_FIFO_EMPTY = 0x17f,
- SC_PS_PA2_SC_FIFO_FULL = 0x180,
- SC_PA2_PS_DATA_SEND = 0x181,
- SC_PS_PA3_SC_FIFO_EMPTY = 0x182,
- SC_PS_PA3_SC_FIFO_FULL = 0x183,
- SC_PA3_PS_DATA_SEND = 0x184,
- SC_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x185,
- SC_BUSY_CNT_NOT_ZERO = 0x186,
- SC_BM_BUSY = 0x187,
- SC_BACKEND_BUSY = 0x188,
- SC_SCF_SCB_INTERFACE_BUSY = 0x189,
- SC_SCB_BUSY = 0x18a,
- SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 0x18b,
- SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 0x18c,
-} SC_PERFCNT_SEL;
-typedef enum SePairXsel {
- RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0x0,
- RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 0x1,
- RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 0x2,
- RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 0x3,
-} SePairXsel;
-typedef enum SePairYsel {
- RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0x0,
- RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 0x1,
- RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 0x2,
- RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 0x3,
-} SePairYsel;
-typedef enum SePairMap {
- RASTER_CONFIG_SE_PAIR_MAP_0 = 0x0,
- RASTER_CONFIG_SE_PAIR_MAP_1 = 0x1,
- RASTER_CONFIG_SE_PAIR_MAP_2 = 0x2,
- RASTER_CONFIG_SE_PAIR_MAP_3 = 0x3,
-} SePairMap;
-typedef enum SeXsel {
- RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0x0,
- RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 0x1,
- RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 0x2,
- RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 0x3,
-} SeXsel;
-typedef enum SeYsel {
- RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0x0,
- RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 0x1,
- RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 0x2,
- RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 0x3,
-} SeYsel;
-typedef enum SeMap {
- RASTER_CONFIG_SE_MAP_0 = 0x0,
- RASTER_CONFIG_SE_MAP_1 = 0x1,
- RASTER_CONFIG_SE_MAP_2 = 0x2,
- RASTER_CONFIG_SE_MAP_3 = 0x3,
-} SeMap;
-typedef enum ScXsel {
- RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0x0,
- RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 0x1,
- RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 0x2,
- RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 0x3,
-} ScXsel;
-typedef enum ScYsel {
- RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0x0,
- RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 0x1,
- RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 0x2,
- RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 0x3,
-} ScYsel;
-typedef enum ScMap {
- RASTER_CONFIG_SC_MAP_0 = 0x0,
- RASTER_CONFIG_SC_MAP_1 = 0x1,
- RASTER_CONFIG_SC_MAP_2 = 0x2,
- RASTER_CONFIG_SC_MAP_3 = 0x3,
-} ScMap;
-typedef enum PkrXsel2 {
- RASTER_CONFIG_PKR_XSEL2_0 = 0x0,
- RASTER_CONFIG_PKR_XSEL2_1 = 0x1,
- RASTER_CONFIG_PKR_XSEL2_2 = 0x2,
- RASTER_CONFIG_PKR_XSEL2_3 = 0x3,
-} PkrXsel2;
-typedef enum PkrXsel {
- RASTER_CONFIG_PKR_XSEL_0 = 0x0,
- RASTER_CONFIG_PKR_XSEL_1 = 0x1,
- RASTER_CONFIG_PKR_XSEL_2 = 0x2,
- RASTER_CONFIG_PKR_XSEL_3 = 0x3,
-} PkrXsel;
-typedef enum PkrYsel {
- RASTER_CONFIG_PKR_YSEL_0 = 0x0,
- RASTER_CONFIG_PKR_YSEL_1 = 0x1,
- RASTER_CONFIG_PKR_YSEL_2 = 0x2,
- RASTER_CONFIG_PKR_YSEL_3 = 0x3,
-} PkrYsel;
-typedef enum PkrMap {
- RASTER_CONFIG_PKR_MAP_0 = 0x0,
- RASTER_CONFIG_PKR_MAP_1 = 0x1,
- RASTER_CONFIG_PKR_MAP_2 = 0x2,
- RASTER_CONFIG_PKR_MAP_3 = 0x3,
-} PkrMap;
-typedef enum RbXsel {
- RASTER_CONFIG_RB_XSEL_0 = 0x0,
- RASTER_CONFIG_RB_XSEL_1 = 0x1,
-} RbXsel;
-typedef enum RbYsel {
- RASTER_CONFIG_RB_YSEL_0 = 0x0,
- RASTER_CONFIG_RB_YSEL_1 = 0x1,
-} RbYsel;
-typedef enum RbXsel2 {
- RASTER_CONFIG_RB_XSEL2_0 = 0x0,
- RASTER_CONFIG_RB_XSEL2_1 = 0x1,
- RASTER_CONFIG_RB_XSEL2_2 = 0x2,
- RASTER_CONFIG_RB_XSEL2_3 = 0x3,
-} RbXsel2;
-typedef enum RbMap {
- RASTER_CONFIG_RB_MAP_0 = 0x0,
- RASTER_CONFIG_RB_MAP_1 = 0x1,
- RASTER_CONFIG_RB_MAP_2 = 0x2,
- RASTER_CONFIG_RB_MAP_3 = 0x3,
-} RbMap;
-typedef enum CSDATA_TYPE {
- CSDATA_TYPE_TG = 0x0,
- CSDATA_TYPE_STATE = 0x1,
- CSDATA_TYPE_EVENT = 0x2,
- CSDATA_TYPE_PRIVATE = 0x3,
-} CSDATA_TYPE;
-#define CSDATA_TYPE_WIDTH 0x2
-#define CSDATA_ADDR_WIDTH 0x7
-#define CSDATA_DATA_WIDTH 0x20
-typedef enum SPI_SAMPLE_CNTL {
- CENTROIDS_ONLY = 0x0,
- CENTERS_ONLY = 0x1,
- CENTROIDS_AND_CENTERS = 0x2,
- UNDEF = 0x3,
-} SPI_SAMPLE_CNTL;
-typedef enum SPI_FOG_MODE {
- SPI_FOG_NONE = 0x0,
- SPI_FOG_EXP = 0x1,
- SPI_FOG_EXP2 = 0x2,
- SPI_FOG_LINEAR = 0x3,
-} SPI_FOG_MODE;
-typedef enum SPI_PNT_SPRITE_OVERRIDE {
- SPI_PNT_SPRITE_SEL_0 = 0x0,
- SPI_PNT_SPRITE_SEL_1 = 0x1,
- SPI_PNT_SPRITE_SEL_S = 0x2,
- SPI_PNT_SPRITE_SEL_T = 0x3,
- SPI_PNT_SPRITE_SEL_NONE = 0x4,
-} SPI_PNT_SPRITE_OVERRIDE;
-typedef enum SPI_PERFCNT_SEL {
- SPI_PERF_VS_WINDOW_VALID = 0x0,
- SPI_PERF_VS_BUSY = 0x1,
- SPI_PERF_VS_FIRST_WAVE = 0x2,
- SPI_PERF_VS_LAST_WAVE = 0x3,
- SPI_PERF_VS_LSHS_DEALLOC = 0x4,
- SPI_PERF_VS_PC_STALL = 0x5,
- SPI_PERF_VS_POS0_STALL = 0x6,
- SPI_PERF_VS_POS1_STALL = 0x7,
- SPI_PERF_VS_CRAWLER_STALL = 0x8,
- SPI_PERF_VS_EVENT_WAVE = 0x9,
- SPI_PERF_VS_WAVE = 0xa,
- SPI_PERF_VS_PERS_UPD_FULL0 = 0xb,
- SPI_PERF_VS_PERS_UPD_FULL1 = 0xc,
- SPI_PERF_VS_LATE_ALLOC_FULL = 0xd,
- SPI_PERF_VS_FIRST_SUBGRP = 0xe,
- SPI_PERF_VS_LAST_SUBGRP = 0xf,
- SPI_PERF_GS_WINDOW_VALID = 0x10,
- SPI_PERF_GS_BUSY = 0x11,
- SPI_PERF_GS_CRAWLER_STALL = 0x12,
- SPI_PERF_GS_EVENT_WAVE = 0x13,
- SPI_PERF_GS_WAVE = 0x14,
- SPI_PERF_GS_PERS_UPD_FULL0 = 0x15,
- SPI_PERF_GS_PERS_UPD_FULL1 = 0x16,
- SPI_PERF_GS_FIRST_SUBGRP = 0x17,
- SPI_PERF_GS_LAST_SUBGRP = 0x18,
- SPI_PERF_ES_WINDOW_VALID = 0x19,
- SPI_PERF_ES_BUSY = 0x1a,
- SPI_PERF_ES_CRAWLER_STALL = 0x1b,
- SPI_PERF_ES_FIRST_WAVE = 0x1c,
- SPI_PERF_ES_LAST_WAVE = 0x1d,
- SPI_PERF_ES_LSHS_DEALLOC = 0x1e,
- SPI_PERF_ES_EVENT_WAVE = 0x1f,
- SPI_PERF_ES_WAVE = 0x20,
- SPI_PERF_ES_PERS_UPD_FULL0 = 0x21,
- SPI_PERF_ES_PERS_UPD_FULL1 = 0x22,
- SPI_PERF_ES_FIRST_SUBGRP = 0x23,
- SPI_PERF_ES_LAST_SUBGRP = 0x24,
- SPI_PERF_HS_WINDOW_VALID = 0x25,
- SPI_PERF_HS_BUSY = 0x26,
- SPI_PERF_HS_CRAWLER_STALL = 0x27,
- SPI_PERF_HS_FIRST_WAVE = 0x28,
- SPI_PERF_HS_LAST_WAVE = 0x29,
- SPI_PERF_HS_LSHS_DEALLOC = 0x2a,
- SPI_PERF_HS_EVENT_WAVE = 0x2b,
- SPI_PERF_HS_WAVE = 0x2c,
- SPI_PERF_HS_PERS_UPD_FULL0 = 0x2d,
- SPI_PERF_HS_PERS_UPD_FULL1 = 0x2e,
- SPI_PERF_LS_WINDOW_VALID = 0x2f,
- SPI_PERF_LS_BUSY = 0x30,
- SPI_PERF_LS_CRAWLER_STALL = 0x31,
- SPI_PERF_LS_FIRST_WAVE = 0x32,
- SPI_PERF_LS_LAST_WAVE = 0x33,
- SPI_PERF_OFFCHIP_LDS_STALL_LS = 0x34,
- SPI_PERF_LS_EVENT_WAVE = 0x35,
- SPI_PERF_LS_WAVE = 0x36,
- SPI_PERF_LS_PERS_UPD_FULL0 = 0x37,
- SPI_PERF_LS_PERS_UPD_FULL1 = 0x38,
- SPI_PERF_CSG_WINDOW_VALID = 0x39,
- SPI_PERF_CSG_BUSY = 0x3a,
- SPI_PERF_CSG_NUM_THREADGROUPS = 0x3b,
- SPI_PERF_CSG_CRAWLER_STALL = 0x3c,
- SPI_PERF_CSG_EVENT_WAVE = 0x3d,
- SPI_PERF_CSG_WAVE = 0x3e,
- SPI_PERF_CSN_WINDOW_VALID = 0x3f,
- SPI_PERF_CSN_BUSY = 0x40,
- SPI_PERF_CSN_NUM_THREADGROUPS = 0x41,
- SPI_PERF_CSN_CRAWLER_STALL = 0x42,
- SPI_PERF_CSN_EVENT_WAVE = 0x43,
- SPI_PERF_CSN_WAVE = 0x44,
- SPI_PERF_PS_CTL_WINDOW_VALID = 0x45,
- SPI_PERF_PS_CTL_BUSY = 0x46,
- SPI_PERF_PS_CTL_ACTIVE = 0x47,
- SPI_PERF_PS_CTL_DEALLOC_BIN0 = 0x48,
- SPI_PERF_PS_CTL_FPOS_BIN1_STALL = 0x49,
- SPI_PERF_PS_CTL_EVENT_WAVE = 0x4a,
- SPI_PERF_PS_CTL_WAVE = 0x4b,
- SPI_PERF_PS_CTL_OPT_WAVE = 0x4c,
- SPI_PERF_PS_CTL_PASS_BIN0 = 0x4d,
- SPI_PERF_PS_CTL_PASS_BIN1 = 0x4e,
- SPI_PERF_PS_CTL_FPOS_BIN2 = 0x4f,
- SPI_PERF_PS_CTL_PRIM_BIN0 = 0x50,
- SPI_PERF_PS_CTL_PRIM_BIN1 = 0x51,
- SPI_PERF_PS_CTL_CNF_BIN2 = 0x52,
- SPI_PERF_PS_CTL_CNF_BIN3 = 0x53,
- SPI_PERF_PS_CTL_CRAWLER_STALL = 0x54,
- SPI_PERF_PS_CTL_LDS_RES_FULL = 0x55,
- SPI_PERF_PS_PERS_UPD_FULL0 = 0x56,
- SPI_PERF_PS_PERS_UPD_FULL1 = 0x57,
- SPI_PERF_PIX_ALLOC_PEND_CNT = 0x58,
- SPI_PERF_PIX_ALLOC_SCB_STALL = 0x59,
- SPI_PERF_PIX_ALLOC_DB0_STALL = 0x5a,
- SPI_PERF_PIX_ALLOC_DB1_STALL = 0x5b,
- SPI_PERF_PIX_ALLOC_DB2_STALL = 0x5c,
- SPI_PERF_PIX_ALLOC_DB3_STALL = 0x5d,
- SPI_PERF_LDS0_PC_VALID = 0x5e,
- SPI_PERF_LDS1_PC_VALID = 0x5f,
- SPI_PERF_RA_PIPE_REQ_BIN2 = 0x60,
- SPI_PERF_RA_TASK_REQ_BIN3 = 0x61,
- SPI_PERF_RA_WR_CTL_FULL = 0x62,
- SPI_PERF_RA_REQ_NO_ALLOC = 0x63,
- SPI_PERF_RA_REQ_NO_ALLOC_PS = 0x64,
- SPI_PERF_RA_REQ_NO_ALLOC_VS = 0x65,
- SPI_PERF_RA_REQ_NO_ALLOC_GS = 0x66,
- SPI_PERF_RA_REQ_NO_ALLOC_ES = 0x67,
- SPI_PERF_RA_REQ_NO_ALLOC_HS = 0x68,
- SPI_PERF_RA_REQ_NO_ALLOC_LS = 0x69,
- SPI_PERF_RA_REQ_NO_ALLOC_CSG = 0x6a,
- SPI_PERF_RA_REQ_NO_ALLOC_CSN = 0x6b,
- SPI_PERF_RA_RES_STALL_PS = 0x6c,
- SPI_PERF_RA_RES_STALL_VS = 0x6d,
- SPI_PERF_RA_RES_STALL_GS = 0x6e,
- SPI_PERF_RA_RES_STALL_ES = 0x6f,
- SPI_PERF_RA_RES_STALL_HS = 0x70,
- SPI_PERF_RA_RES_STALL_LS = 0x71,
- SPI_PERF_RA_RES_STALL_CSG = 0x72,
- SPI_PERF_RA_RES_STALL_CSN = 0x73,
- SPI_PERF_RA_TMP_STALL_PS = 0x74,
- SPI_PERF_RA_TMP_STALL_VS = 0x75,
- SPI_PERF_RA_TMP_STALL_GS = 0x76,
- SPI_PERF_RA_TMP_STALL_ES = 0x77,
- SPI_PERF_RA_TMP_STALL_HS = 0x78,
- SPI_PERF_RA_TMP_STALL_LS = 0x79,
- SPI_PERF_RA_TMP_STALL_CSG = 0x7a,
- SPI_PERF_RA_TMP_STALL_CSN = 0x7b,
- SPI_PERF_RA_WAVE_SIMD_FULL_PS = 0x7c,
- SPI_PERF_RA_WAVE_SIMD_FULL_VS = 0x7d,
- SPI_PERF_RA_WAVE_SIMD_FULL_GS = 0x7e,
- SPI_PERF_RA_WAVE_SIMD_FULL_ES = 0x7f,
- SPI_PERF_RA_WAVE_SIMD_FULL_HS = 0x80,
- SPI_PERF_RA_WAVE_SIMD_FULL_LS = 0x81,
- SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 0x82,
- SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 0x83,
- SPI_PERF_RA_VGPR_SIMD_FULL_PS = 0x84,
- SPI_PERF_RA_VGPR_SIMD_FULL_VS = 0x85,
- SPI_PERF_RA_VGPR_SIMD_FULL_GS = 0x86,
- SPI_PERF_RA_VGPR_SIMD_FULL_ES = 0x87,
- SPI_PERF_RA_VGPR_SIMD_FULL_HS = 0x88,
- SPI_PERF_RA_VGPR_SIMD_FULL_LS = 0x89,
- SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 0x8a,
- SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 0x8b,
- SPI_PERF_RA_SGPR_SIMD_FULL_PS = 0x8c,
- SPI_PERF_RA_SGPR_SIMD_FULL_VS = 0x8d,
- SPI_PERF_RA_SGPR_SIMD_FULL_GS = 0x8e,
- SPI_PERF_RA_SGPR_SIMD_FULL_ES = 0x8f,
- SPI_PERF_RA_SGPR_SIMD_FULL_HS = 0x90,
- SPI_PERF_RA_SGPR_SIMD_FULL_LS = 0x91,
- SPI_PERF_RA_SGPR_SIMD_FULL_CSG = 0x92,
- SPI_PERF_RA_SGPR_SIMD_FULL_CSN = 0x93,
- SPI_PERF_RA_LDS_CU_FULL_PS = 0x94,
- SPI_PERF_RA_LDS_CU_FULL_LS = 0x95,
- SPI_PERF_RA_LDS_CU_FULL_ES = 0x96,
- SPI_PERF_RA_LDS_CU_FULL_CSG = 0x97,
- SPI_PERF_RA_LDS_CU_FULL_CSN = 0x98,
- SPI_PERF_RA_BAR_CU_FULL_HS = 0x99,
- SPI_PERF_RA_BAR_CU_FULL_CSG = 0x9a,
- SPI_PERF_RA_BAR_CU_FULL_CSN = 0x9b,
- SPI_PERF_RA_BULKY_CU_FULL_CSG = 0x9c,
- SPI_PERF_RA_BULKY_CU_FULL_CSN = 0x9d,
- SPI_PERF_RA_TGLIM_CU_FULL_CSG = 0x9e,
- SPI_PERF_RA_TGLIM_CU_FULL_CSN = 0x9f,
- SPI_PERF_RA_WVLIM_STALL_PS = 0xa0,
- SPI_PERF_RA_WVLIM_STALL_VS = 0xa1,
- SPI_PERF_RA_WVLIM_STALL_GS = 0xa2,
- SPI_PERF_RA_WVLIM_STALL_ES = 0xa3,
- SPI_PERF_RA_WVLIM_STALL_HS = 0xa4,
- SPI_PERF_RA_WVLIM_STALL_LS = 0xa5,
- SPI_PERF_RA_WVLIM_STALL_CSG = 0xa6,
- SPI_PERF_RA_WVLIM_STALL_CSN = 0xa7,
- SPI_PERF_RA_PS_LOCK_NA = 0xa8,
- SPI_PERF_RA_VS_LOCK = 0xa9,
- SPI_PERF_RA_GS_LOCK = 0xaa,
- SPI_PERF_RA_ES_LOCK = 0xab,
- SPI_PERF_RA_HS_LOCK = 0xac,
- SPI_PERF_RA_LS_LOCK = 0xad,
- SPI_PERF_RA_CSG_LOCK = 0xae,
- SPI_PERF_RA_CSN_LOCK = 0xaf,
- SPI_PERF_RA_RSV_UPD = 0xb0,
- SPI_PERF_EXP_ARB_COL_CNT = 0xb1,
- SPI_PERF_EXP_ARB_PAR_CNT = 0xb2,
- SPI_PERF_EXP_ARB_POS_CNT = 0xb3,
- SPI_PERF_EXP_ARB_GDS_CNT = 0xb4,
- SPI_PERF_CLKGATE_BUSY_STALL = 0xb5,
- SPI_PERF_CLKGATE_ACTIVE_STALL = 0xb6,
- SPI_PERF_CLKGATE_ALL_CLOCKS_ON = 0xb7,
- SPI_PERF_CLKGATE_CGTT_DYN_ON = 0xb8,
- SPI_PERF_CLKGATE_CGTT_REG_ON = 0xb9,
- SPI_PERF_NUM_VS_POS_EXPORTS = 0xba,
- SPI_PERF_NUM_VS_PARAM_EXPORTS = 0xbb,
- SPI_PERF_NUM_PS_COL_EXPORTS = 0xbc,
- SPI_PERF_ES_GRP_FIFO_FULL = 0xbd,
- SPI_PERF_GS_GRP_FIFO_FULL = 0xbe,
- SPI_PERF_HS_GRP_FIFO_FULL = 0xbf,
- SPI_PERF_LS_GRP_FIFO_FULL = 0xc0,
- SPI_PERF_VS_ALLOC_CNT = 0xc1,
- SPI_PERF_VS_LATE_ALLOC_ACCUM = 0xc2,
- SPI_PERF_PC_ALLOC_CNT = 0xc3,
- SPI_PERF_PC_ALLOC_ACCUM = 0xc4,
-} SPI_PERFCNT_SEL;
-typedef enum SPI_SHADER_FORMAT {
- SPI_SHADER_NONE = 0x0,
- SPI_SHADER_1COMP = 0x1,
- SPI_SHADER_2COMP = 0x2,
- SPI_SHADER_4COMPRESS = 0x3,
- SPI_SHADER_4COMP = 0x4,
-} SPI_SHADER_FORMAT;
-typedef enum SPI_SHADER_EX_FORMAT {
- SPI_SHADER_ZERO = 0x0,
- SPI_SHADER_32_R = 0x1,
- SPI_SHADER_32_GR = 0x2,
- SPI_SHADER_32_AR = 0x3,
- SPI_SHADER_FP16_ABGR = 0x4,
- SPI_SHADER_UNORM16_ABGR = 0x5,
- SPI_SHADER_SNORM16_ABGR = 0x6,
- SPI_SHADER_UINT16_ABGR = 0x7,
- SPI_SHADER_SINT16_ABGR = 0x8,
- SPI_SHADER_32_ABGR = 0x9,
-} SPI_SHADER_EX_FORMAT;
-typedef enum CLKGATE_SM_MODE {
- ON_SEQ = 0x0,
- OFF_SEQ = 0x1,
- PROG_SEQ = 0x2,
- READ_SEQ = 0x3,
- SM_MODE_RESERVED = 0x4,
-} CLKGATE_SM_MODE;
-typedef enum CLKGATE_BASE_MODE {
- MULT_8 = 0x0,
- MULT_16 = 0x1,
-} CLKGATE_BASE_MODE;
-typedef enum SQ_TEX_CLAMP {
- SQ_TEX_WRAP = 0x0,
- SQ_TEX_MIRROR = 0x1,
- SQ_TEX_CLAMP_LAST_TEXEL = 0x2,
- SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x3,
- SQ_TEX_CLAMP_HALF_BORDER = 0x4,
- SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x5,
- SQ_TEX_CLAMP_BORDER = 0x6,
- SQ_TEX_MIRROR_ONCE_BORDER = 0x7,
-} SQ_TEX_CLAMP;
-typedef enum SQ_TEX_XY_FILTER {
- SQ_TEX_XY_FILTER_POINT = 0x0,
- SQ_TEX_XY_FILTER_BILINEAR = 0x1,
- SQ_TEX_XY_FILTER_ANISO_POINT = 0x2,
- SQ_TEX_XY_FILTER_ANISO_BILINEAR = 0x3,
-} SQ_TEX_XY_FILTER;
-typedef enum SQ_TEX_Z_FILTER {
- SQ_TEX_Z_FILTER_NONE = 0x0,
- SQ_TEX_Z_FILTER_POINT = 0x1,
- SQ_TEX_Z_FILTER_LINEAR = 0x2,
-} SQ_TEX_Z_FILTER;
-typedef enum SQ_TEX_MIP_FILTER {
- SQ_TEX_MIP_FILTER_NONE = 0x0,
- SQ_TEX_MIP_FILTER_POINT = 0x1,
- SQ_TEX_MIP_FILTER_LINEAR = 0x2,
- SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ = 0x3,
-} SQ_TEX_MIP_FILTER;
-typedef enum SQ_TEX_ANISO_RATIO {
- SQ_TEX_ANISO_RATIO_1 = 0x0,
- SQ_TEX_ANISO_RATIO_2 = 0x1,
- SQ_TEX_ANISO_RATIO_4 = 0x2,
- SQ_TEX_ANISO_RATIO_8 = 0x3,
- SQ_TEX_ANISO_RATIO_16 = 0x4,
-} SQ_TEX_ANISO_RATIO;
-typedef enum SQ_TEX_DEPTH_COMPARE {
- SQ_TEX_DEPTH_COMPARE_NEVER = 0x0,
- SQ_TEX_DEPTH_COMPARE_LESS = 0x1,
- SQ_TEX_DEPTH_COMPARE_EQUAL = 0x2,
- SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 0x3,
- SQ_TEX_DEPTH_COMPARE_GREATER = 0x4,
- SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 0x5,
- SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 0x6,
- SQ_TEX_DEPTH_COMPARE_ALWAYS = 0x7,
-} SQ_TEX_DEPTH_COMPARE;
-typedef enum SQ_TEX_BORDER_COLOR {
- SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x0,
- SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x1,
- SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x2,
- SQ_TEX_BORDER_COLOR_REGISTER = 0x3,
-} SQ_TEX_BORDER_COLOR;
-typedef enum SQ_RSRC_BUF_TYPE {
- SQ_RSRC_BUF = 0x0,
- SQ_RSRC_BUF_RSVD_1 = 0x1,
- SQ_RSRC_BUF_RSVD_2 = 0x2,
- SQ_RSRC_BUF_RSVD_3 = 0x3,
-} SQ_RSRC_BUF_TYPE;
-typedef enum SQ_RSRC_IMG_TYPE {
- SQ_RSRC_IMG_RSVD_0 = 0x0,
- SQ_RSRC_IMG_RSVD_1 = 0x1,
- SQ_RSRC_IMG_RSVD_2 = 0x2,
- SQ_RSRC_IMG_RSVD_3 = 0x3,
- SQ_RSRC_IMG_RSVD_4 = 0x4,
- SQ_RSRC_IMG_RSVD_5 = 0x5,
- SQ_RSRC_IMG_RSVD_6 = 0x6,
- SQ_RSRC_IMG_RSVD_7 = 0x7,
- SQ_RSRC_IMG_1D = 0x8,
- SQ_RSRC_IMG_2D = 0x9,
- SQ_RSRC_IMG_3D = 0xa,
- SQ_RSRC_IMG_CUBE = 0xb,
- SQ_RSRC_IMG_1D_ARRAY = 0xc,
- SQ_RSRC_IMG_2D_ARRAY = 0xd,
- SQ_RSRC_IMG_2D_MSAA = 0xe,
- SQ_RSRC_IMG_2D_MSAA_ARRAY = 0xf,
-} SQ_RSRC_IMG_TYPE;
-typedef enum SQ_RSRC_FLAT_TYPE {
- SQ_RSRC_FLAT_RSVD_0 = 0x0,
- SQ_RSRC_FLAT = 0x1,
- SQ_RSRC_FLAT_RSVD_2 = 0x2,
- SQ_RSRC_FLAT_RSVD_3 = 0x3,
-} SQ_RSRC_FLAT_TYPE;
-typedef enum SQ_IMG_FILTER_TYPE {
- SQ_IMG_FILTER_MODE_BLEND = 0x0,
- SQ_IMG_FILTER_MODE_MIN = 0x1,
- SQ_IMG_FILTER_MODE_MAX = 0x2,
-} SQ_IMG_FILTER_TYPE;
-typedef enum SQ_SEL_XYZW01 {
- SQ_SEL_0 = 0x0,
- SQ_SEL_1 = 0x1,
- SQ_SEL_RESERVED_0 = 0x2,
- SQ_SEL_RESERVED_1 = 0x3,
- SQ_SEL_X = 0x4,
- SQ_SEL_Y = 0x5,
- SQ_SEL_Z = 0x6,
- SQ_SEL_W = 0x7,
-} SQ_SEL_XYZW01;
-typedef enum SQ_WAVE_TYPE {
- SQ_WAVE_TYPE_PS = 0x0,
- SQ_WAVE_TYPE_VS = 0x1,
- SQ_WAVE_TYPE_GS = 0x2,
- SQ_WAVE_TYPE_ES = 0x3,
- SQ_WAVE_TYPE_HS = 0x4,
- SQ_WAVE_TYPE_LS = 0x5,
- SQ_WAVE_TYPE_CS = 0x6,
- SQ_WAVE_TYPE_PS1 = 0x7,
-} SQ_WAVE_TYPE;
-typedef enum SQ_THREAD_TRACE_TOKEN_TYPE {
- SQ_THREAD_TRACE_TOKEN_MISC = 0x0,
- SQ_THREAD_TRACE_TOKEN_TIMESTAMP = 0x1,
- SQ_THREAD_TRACE_TOKEN_REG = 0x2,
- SQ_THREAD_TRACE_TOKEN_WAVE_START = 0x3,
- SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC = 0x4,
- SQ_THREAD_TRACE_TOKEN_REG_CSPRIV = 0x5,
- SQ_THREAD_TRACE_TOKEN_WAVE_END = 0x6,
- SQ_THREAD_TRACE_TOKEN_EVENT = 0x7,
- SQ_THREAD_TRACE_TOKEN_EVENT_CS = 0x8,
- SQ_THREAD_TRACE_TOKEN_EVENT_GFX1 = 0x9,
- SQ_THREAD_TRACE_TOKEN_INST = 0xa,
- SQ_THREAD_TRACE_TOKEN_INST_PC = 0xb,
- SQ_THREAD_TRACE_TOKEN_INST_USERDATA = 0xc,
- SQ_THREAD_TRACE_TOKEN_ISSUE = 0xd,
- SQ_THREAD_TRACE_TOKEN_PERF = 0xe,
- SQ_THREAD_TRACE_TOKEN_REG_CS = 0xf,
-} SQ_THREAD_TRACE_TOKEN_TYPE;
-typedef enum SQ_THREAD_TRACE_MISC_TOKEN_TYPE {
- SQ_THREAD_TRACE_MISC_TOKEN_TIME = 0x0,
- SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET = 0x1,
- SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST = 0x2,
- SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC = 0x3,
- SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN = 0x4,
- SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END = 0x5,
- SQ_THREAD_TRACE_MISC_TOKEN_SAVECTX = 0x6,
- SQ_THREAD_TRACE_MISC_TOKEN_SHOOT_DOWN = 0x7,
-} SQ_THREAD_TRACE_MISC_TOKEN_TYPE;
-typedef enum SQ_THREAD_TRACE_INST_TYPE {
- SQ_THREAD_TRACE_INST_TYPE_SMEM_RD = 0x0,
- SQ_THREAD_TRACE_INST_TYPE_SALU_32 = 0x1,
- SQ_THREAD_TRACE_INST_TYPE_VMEM_RD = 0x2,
- SQ_THREAD_TRACE_INST_TYPE_VMEM_WR = 0x3,
- SQ_THREAD_TRACE_INST_TYPE_FLAT_WR = 0x4,
- SQ_THREAD_TRACE_INST_TYPE_VALU_32 = 0x5,
- SQ_THREAD_TRACE_INST_TYPE_LDS = 0x6,
- SQ_THREAD_TRACE_INST_TYPE_PC = 0x7,
- SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS = 0x8,
- SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX = 0x9,
- SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL = 0xa,
- SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS = 0xb,
- SQ_THREAD_TRACE_INST_TYPE_JUMP = 0xc,
- SQ_THREAD_TRACE_INST_TYPE_NEXT = 0xd,
- SQ_THREAD_TRACE_INST_TYPE_FLAT_RD = 0xe,
- SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG = 0xf,
- SQ_THREAD_TRACE_INST_TYPE_SMEM_WR = 0x10,
- SQ_THREAD_TRACE_INST_TYPE_SALU_64 = 0x11,
- SQ_THREAD_TRACE_INST_TYPE_VALU_64 = 0x12,
- SQ_THREAD_TRACE_INST_TYPE_SMEM_RD_REPLAY = 0x13,
- SQ_THREAD_TRACE_INST_TYPE_SMEM_WR_REPLAY = 0x14,
- SQ_THREAD_TRACE_INST_TYPE_VMEM_RD_REPLAY = 0x15,
- SQ_THREAD_TRACE_INST_TYPE_VMEM_WR_REPLAY = 0x16,
- SQ_THREAD_TRACE_INST_TYPE_FLAT_RD_REPLAY = 0x17,
- SQ_THREAD_TRACE_INST_TYPE_FLAT_WR_REPLAY = 0x18,
-} SQ_THREAD_TRACE_INST_TYPE;
-typedef enum SQ_THREAD_TRACE_REG_TYPE {
- SQ_THREAD_TRACE_REG_TYPE_EVENT = 0x0,
- SQ_THREAD_TRACE_REG_TYPE_DRAW = 0x1,
- SQ_THREAD_TRACE_REG_TYPE_DISPATCH = 0x2,
- SQ_THREAD_TRACE_REG_TYPE_USERDATA = 0x3,
- SQ_THREAD_TRACE_REG_TYPE_MARKER = 0x4,
- SQ_THREAD_TRACE_REG_TYPE_GFXDEC = 0x5,
- SQ_THREAD_TRACE_REG_TYPE_SHDEC = 0x6,
- SQ_THREAD_TRACE_REG_TYPE_OTHER = 0x7,
-} SQ_THREAD_TRACE_REG_TYPE;
-typedef enum SQ_THREAD_TRACE_REG_OP {
- SQ_THREAD_TRACE_REG_OP_READ = 0x0,
- SQ_THREAD_TRACE_REG_OP_WRITE = 0x1,
-} SQ_THREAD_TRACE_REG_OP;
-typedef enum SQ_THREAD_TRACE_MODE_SEL {
- SQ_THREAD_TRACE_MODE_OFF = 0x0,
- SQ_THREAD_TRACE_MODE_ON = 0x1,
-} SQ_THREAD_TRACE_MODE_SEL;
-typedef enum SQ_THREAD_TRACE_CAPTURE_MODE {
- SQ_THREAD_TRACE_CAPTURE_MODE_ALL = 0x0,
- SQ_THREAD_TRACE_CAPTURE_MODE_SELECT = 0x1,
- SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL = 0x2,
-} SQ_THREAD_TRACE_CAPTURE_MODE;
-typedef enum SQ_THREAD_TRACE_VM_ID_MASK {
- SQ_THREAD_TRACE_VM_ID_MASK_SINGLE = 0x0,
- SQ_THREAD_TRACE_VM_ID_MASK_ALL = 0x1,
- SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL = 0x2,
-} SQ_THREAD_TRACE_VM_ID_MASK;
-typedef enum SQ_THREAD_TRACE_WAVE_MASK {
- SQ_THREAD_TRACE_WAVE_MASK_NONE = 0x0,
- SQ_THREAD_TRACE_WAVE_MASK_ALL = 0x1,
-} SQ_THREAD_TRACE_WAVE_MASK;
-typedef enum SQ_THREAD_TRACE_ISSUE {
- SQ_THREAD_TRACE_ISSUE_NULL = 0x0,
- SQ_THREAD_TRACE_ISSUE_STALL = 0x1,
- SQ_THREAD_TRACE_ISSUE_INST = 0x2,
- SQ_THREAD_TRACE_ISSUE_IMMED = 0x3,
-} SQ_THREAD_TRACE_ISSUE;
-typedef enum SQ_THREAD_TRACE_ISSUE_MASK {
- SQ_THREAD_TRACE_ISSUE_MASK_ALL = 0x0,
- SQ_THREAD_TRACE_ISSUE_MASK_STALLED = 0x1,
- SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED = 0x2,
- SQ_THREAD_TRACE_ISSUE_MASK_IMMED = 0x3,
-} SQ_THREAD_TRACE_ISSUE_MASK;
-typedef enum SQ_PERF_SEL {
- SQ_PERF_SEL_NONE = 0x0,
- SQ_PERF_SEL_ACCUM_PREV = 0x1,
- SQ_PERF_SEL_CYCLES = 0x2,
- SQ_PERF_SEL_BUSY_CYCLES = 0x3,
- SQ_PERF_SEL_WAVES = 0x4,
- SQ_PERF_SEL_LEVEL_WAVES = 0x5,
- SQ_PERF_SEL_WAVES_EQ_64 = 0x6,
- SQ_PERF_SEL_WAVES_LT_64 = 0x7,
- SQ_PERF_SEL_WAVES_LT_48 = 0x8,
- SQ_PERF_SEL_WAVES_LT_32 = 0x9,
- SQ_PERF_SEL_WAVES_LT_16 = 0xa,
- SQ_PERF_SEL_WAVES_CU = 0xb,
- SQ_PERF_SEL_LEVEL_WAVES_CU = 0xc,
- SQ_PERF_SEL_BUSY_CU_CYCLES = 0xd,
- SQ_PERF_SEL_ITEMS = 0xe,
- SQ_PERF_SEL_QUADS = 0xf,
- SQ_PERF_SEL_EVENTS = 0x10,
- SQ_PERF_SEL_SURF_SYNCS = 0x11,
- SQ_PERF_SEL_TTRACE_REQS = 0x12,
- SQ_PERF_SEL_TTRACE_INFLIGHT_REQS = 0x13,
- SQ_PERF_SEL_TTRACE_STALL = 0x14,
- SQ_PERF_SEL_MSG_CNTR = 0x15,
- SQ_PERF_SEL_MSG_PERF = 0x16,
- SQ_PERF_SEL_MSG_GSCNT = 0x17,
- SQ_PERF_SEL_MSG_INTERRUPT = 0x18,
- SQ_PERF_SEL_INSTS = 0x19,
- SQ_PERF_SEL_INSTS_VALU = 0x1a,
- SQ_PERF_SEL_INSTS_VMEM_WR = 0x1b,
- SQ_PERF_SEL_INSTS_VMEM_RD = 0x1c,
- SQ_PERF_SEL_INSTS_VMEM = 0x1d,
- SQ_PERF_SEL_INSTS_SALU = 0x1e,
- SQ_PERF_SEL_INSTS_SMEM = 0x1f,
- SQ_PERF_SEL_INSTS_FLAT = 0x20,
- SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY = 0x21,
- SQ_PERF_SEL_INSTS_LDS = 0x22,
- SQ_PERF_SEL_INSTS_GDS = 0x23,
- SQ_PERF_SEL_INSTS_EXP = 0x24,
- SQ_PERF_SEL_INSTS_EXP_GDS = 0x25,
- SQ_PERF_SEL_INSTS_BRANCH = 0x26,
- SQ_PERF_SEL_INSTS_SENDMSG = 0x27,
- SQ_PERF_SEL_INSTS_VSKIPPED = 0x28,
- SQ_PERF_SEL_INST_LEVEL_VMEM = 0x29,
- SQ_PERF_SEL_INST_LEVEL_SMEM = 0x2a,
- SQ_PERF_SEL_INST_LEVEL_LDS = 0x2b,
- SQ_PERF_SEL_INST_LEVEL_GDS = 0x2c,
- SQ_PERF_SEL_INST_LEVEL_EXP = 0x2d,
- SQ_PERF_SEL_WAVE_CYCLES = 0x2e,
- SQ_PERF_SEL_WAVE_READY = 0x2f,
- SQ_PERF_SEL_WAIT_CNT_VM = 0x30,
- SQ_PERF_SEL_WAIT_CNT_LGKM = 0x31,
- SQ_PERF_SEL_WAIT_CNT_EXP = 0x32,
- SQ_PERF_SEL_WAIT_CNT_ANY = 0x33,
- SQ_PERF_SEL_WAIT_BARRIER = 0x34,
- SQ_PERF_SEL_WAIT_EXP_ALLOC = 0x35,
- SQ_PERF_SEL_WAIT_SLEEP = 0x36,
- SQ_PERF_SEL_WAIT_OTHER = 0x37,
- SQ_PERF_SEL_WAIT_ANY = 0x38,
- SQ_PERF_SEL_WAIT_TTRACE = 0x39,
- SQ_PERF_SEL_WAIT_IFETCH = 0x3a,
- SQ_PERF_SEL_WAIT_INST_VMEM = 0x3b,
- SQ_PERF_SEL_WAIT_INST_SCA = 0x3c,
- SQ_PERF_SEL_WAIT_INST_LDS = 0x3d,
- SQ_PERF_SEL_WAIT_INST_VALU = 0x3e,
- SQ_PERF_SEL_WAIT_INST_EXP_GDS = 0x3f,
- SQ_PERF_SEL_WAIT_INST_MISC = 0x40,
- SQ_PERF_SEL_WAIT_INST_FLAT = 0x41,
- SQ_PERF_SEL_ACTIVE_INST_ANY = 0x42,
- SQ_PERF_SEL_ACTIVE_INST_VMEM = 0x43,
- SQ_PERF_SEL_ACTIVE_INST_LDS = 0x44,
- SQ_PERF_SEL_ACTIVE_INST_VALU = 0x45,
- SQ_PERF_SEL_ACTIVE_INST_SCA = 0x46,
- SQ_PERF_SEL_ACTIVE_INST_EXP_GDS = 0x47,
- SQ_PERF_SEL_ACTIVE_INST_MISC = 0x48,
- SQ_PERF_SEL_ACTIVE_INST_FLAT = 0x49,
- SQ_PERF_SEL_INST_CYCLES_VMEM_WR = 0x4a,
- SQ_PERF_SEL_INST_CYCLES_VMEM_RD = 0x4b,
- SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR = 0x4c,
- SQ_PERF_SEL_INST_CYCLES_VMEM_DATA = 0x4d,
- SQ_PERF_SEL_INST_CYCLES_VMEM_CMD = 0x4e,
- SQ_PERF_SEL_INST_CYCLES_VMEM = 0x4f,
- SQ_PERF_SEL_INST_CYCLES_LDS = 0x50,
- SQ_PERF_SEL_INST_CYCLES_VALU = 0x51,
- SQ_PERF_SEL_INST_CYCLES_EXP = 0x52,
- SQ_PERF_SEL_INST_CYCLES_GDS = 0x53,
- SQ_PERF_SEL_INST_CYCLES_SCA = 0x54,
- SQ_PERF_SEL_INST_CYCLES_SMEM = 0x55,
- SQ_PERF_SEL_INST_CYCLES_SALU = 0x56,
- SQ_PERF_SEL_INST_CYCLES_EXP_GDS = 0x57,
- SQ_PERF_SEL_INST_CYCLES_MISC = 0x58,
- SQ_PERF_SEL_THREAD_CYCLES_VALU = 0x59,
- SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX = 0x5a,
- SQ_PERF_SEL_IFETCH = 0x5b,
- SQ_PERF_SEL_IFETCH_LEVEL = 0x5c,
- SQ_PERF_SEL_CBRANCH_FORK = 0x5d,
- SQ_PERF_SEL_CBRANCH_FORK_SPLIT = 0x5e,
- SQ_PERF_SEL_VALU_LDS_DIRECT_RD = 0x5f,
- SQ_PERF_SEL_VALU_LDS_INTERP_OP = 0x60,
- SQ_PERF_SEL_LDS_BANK_CONFLICT = 0x61,
- SQ_PERF_SEL_LDS_ADDR_CONFLICT = 0x62,
- SQ_PERF_SEL_LDS_UNALIGNED_STALL = 0x63,
- SQ_PERF_SEL_LDS_MEM_VIOLATIONS = 0x64,
- SQ_PERF_SEL_LDS_ATOMIC_RETURN = 0x65,
- SQ_PERF_SEL_LDS_IDX_ACTIVE = 0x66,
- SQ_PERF_SEL_VALU_DEP_STALL = 0x67,
- SQ_PERF_SEL_VALU_STARVE = 0x68,
- SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 0x69,
- SQ_PERF_SEL_LDS_BACK2BACK_STALL = 0x6a,
- SQ_PERF_SEL_LDS_DATA_FIFO_FULL = 0x6b,
- SQ_PERF_SEL_LDS_CMD_FIFO_FULL = 0x6c,
- SQ_PERF_SEL_VMEM_BACK2BACK_STALL = 0x6d,
- SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL = 0x6e,
- SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL = 0x6f,
- SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY = 0x70,
- SQ_PERF_SEL_VMEM_WR_BACK2BACK_STALL = 0x71,
- SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL = 0x72,
- SQ_PERF_SEL_VALU_SRC_C_CONFLICT = 0x73,
- SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT = 0x74,
- SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT = 0x75,
- SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT = 0x76,
- SQ_PERF_SEL_LDS_SRC_CD_CONFLICT = 0x77,
- SQ_PERF_SEL_SRC_CD_BUSY = 0x78,
- SQ_PERF_SEL_PT_POWER_STALL = 0x79,
- SQ_PERF_SEL_USER0 = 0x7a,
- SQ_PERF_SEL_USER1 = 0x7b,
- SQ_PERF_SEL_USER2 = 0x7c,
- SQ_PERF_SEL_USER3 = 0x7d,
- SQ_PERF_SEL_USER4 = 0x7e,
- SQ_PERF_SEL_USER5 = 0x7f,
- SQ_PERF_SEL_USER6 = 0x80,
- SQ_PERF_SEL_USER7 = 0x81,
- SQ_PERF_SEL_USER8 = 0x82,
- SQ_PERF_SEL_USER9 = 0x83,
- SQ_PERF_SEL_USER10 = 0x84,
- SQ_PERF_SEL_USER11 = 0x85,
- SQ_PERF_SEL_USER12 = 0x86,
- SQ_PERF_SEL_USER13 = 0x87,
- SQ_PERF_SEL_USER14 = 0x88,
- SQ_PERF_SEL_USER15 = 0x89,
- SQ_PERF_SEL_USER_LEVEL0 = 0x8a,
- SQ_PERF_SEL_USER_LEVEL1 = 0x8b,
- SQ_PERF_SEL_USER_LEVEL2 = 0x8c,
- SQ_PERF_SEL_USER_LEVEL3 = 0x8d,
- SQ_PERF_SEL_USER_LEVEL4 = 0x8e,
- SQ_PERF_SEL_USER_LEVEL5 = 0x8f,
- SQ_PERF_SEL_USER_LEVEL6 = 0x90,
- SQ_PERF_SEL_USER_LEVEL7 = 0x91,
- SQ_PERF_SEL_USER_LEVEL8 = 0x92,
- SQ_PERF_SEL_USER_LEVEL9 = 0x93,
- SQ_PERF_SEL_USER_LEVEL10 = 0x94,
- SQ_PERF_SEL_USER_LEVEL11 = 0x95,
- SQ_PERF_SEL_USER_LEVEL12 = 0x96,
- SQ_PERF_SEL_USER_LEVEL13 = 0x97,
- SQ_PERF_SEL_USER_LEVEL14 = 0x98,
- SQ_PERF_SEL_USER_LEVEL15 = 0x99,
- SQ_PERF_SEL_POWER_VALU = 0x9a,
- SQ_PERF_SEL_POWER_VALU0 = 0x9b,
- SQ_PERF_SEL_POWER_VALU1 = 0x9c,
- SQ_PERF_SEL_POWER_VALU2 = 0x9d,
- SQ_PERF_SEL_POWER_GPR_RD = 0x9e,
- SQ_PERF_SEL_POWER_GPR_WR = 0x9f,
- SQ_PERF_SEL_POWER_LDS_BUSY = 0xa0,
- SQ_PERF_SEL_POWER_ALU_BUSY = 0xa1,
- SQ_PERF_SEL_POWER_TEX_BUSY = 0xa2,
- SQ_PERF_SEL_ACCUM_PREV_HIRES = 0xa3,
- SQ_PERF_SEL_WAVES_RESTORED = 0xa4,
- SQ_PERF_SEL_WAVES_SAVED = 0xa5,
- SQ_PERF_SEL_DUMMY_LAST = 0xa7,
- SQC_PERF_SEL_ICACHE_INPUT_VALID_READY = 0xa8,
- SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 0xa9,
- SQC_PERF_SEL_ICACHE_INPUT_VALIDB = 0xaa,
- SQC_PERF_SEL_DCACHE_INPUT_VALID_READY = 0xab,
- SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 0xac,
- SQC_PERF_SEL_DCACHE_INPUT_VALIDB = 0xad,
- SQC_PERF_SEL_TC_REQ = 0xae,
- SQC_PERF_SEL_TC_INST_REQ = 0xaf,
- SQC_PERF_SEL_TC_DATA_READ_REQ = 0xb0,
- SQC_PERF_SEL_TC_DATA_WRITE_REQ = 0xb1,
- SQC_PERF_SEL_TC_DATA_ATOMIC_REQ = 0xb2,
- SQC_PERF_SEL_TC_STALL = 0xb3,
- SQC_PERF_SEL_TC_STARVE = 0xb4,
- SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 0xb5,
- SQC_PERF_SEL_ICACHE_REQ = 0xb6,
- SQC_PERF_SEL_ICACHE_HITS = 0xb7,
- SQC_PERF_SEL_ICACHE_MISSES = 0xb8,
- SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 0xb9,
- SQC_PERF_SEL_ICACHE_INVAL_INST = 0xba,
- SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 0xbb,
- SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 0xbc,
- SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 0xbd,
- SQC_PERF_SEL_ICACHE_CACHE_STALLED = 0xbe,
- SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO = 0xbf,
- SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 0xc0,
- SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT = 0xc1,
- SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0xc2,
- SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 0xc3,
- SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF = 0xc4,
- SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0xc5,
- SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 0xc6,
- SQC_PERF_SEL_DCACHE_REQ = 0xc7,
- SQC_PERF_SEL_DCACHE_HITS = 0xc8,
- SQC_PERF_SEL_DCACHE_MISSES = 0xc9,
- SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 0xca,
- SQC_PERF_SEL_DCACHE_HIT_LRU_READ = 0xcb,
- SQC_PERF_SEL_DCACHE_MISS_EVICT_READ = 0xcc,
- SQC_PERF_SEL_DCACHE_WC_LRU_WRITE = 0xcd,
- SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE = 0xce,
- SQC_PERF_SEL_DCACHE_ATOMIC = 0xcf,
- SQC_PERF_SEL_DCACHE_VOLATILE = 0xd0,
- SQC_PERF_SEL_DCACHE_INVAL_INST = 0xd1,
- SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 0xd2,
- SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST = 0xd3,
- SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC = 0xd4,
- SQC_PERF_SEL_DCACHE_WB_INST = 0xd5,
- SQC_PERF_SEL_DCACHE_WB_ASYNC = 0xd6,
- SQC_PERF_SEL_DCACHE_WB_VOLATILE_INST = 0xd7,
- SQC_PERF_SEL_DCACHE_WB_VOLATILE_ASYNC = 0xd8,
- SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 0xd9,
- SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 0xda,
- SQC_PERF_SEL_DCACHE_CACHE_STALLED = 0xdb,
- SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 0xdc,
- SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 0xdd,
- SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT = 0xde,
- SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED = 0xdf,
- SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE= 0xe0,
- SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT = 0xe1,
- SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH = 0xe2,
- SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE = 0xe3,
- SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0xe4,
- SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 0xe5,
- SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF = 0xe6,
- SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0xe7,
- SQC_PERF_SEL_DCACHE_REQ_READ_1 = 0xe8,
- SQC_PERF_SEL_DCACHE_REQ_READ_2 = 0xe9,
- SQC_PERF_SEL_DCACHE_REQ_READ_4 = 0xea,
- SQC_PERF_SEL_DCACHE_REQ_READ_8 = 0xeb,
- SQC_PERF_SEL_DCACHE_REQ_READ_16 = 0xec,
- SQC_PERF_SEL_DCACHE_REQ_TIME = 0xed,
- SQC_PERF_SEL_DCACHE_REQ_WRITE_1 = 0xee,
- SQC_PERF_SEL_DCACHE_REQ_WRITE_2 = 0xef,
- SQC_PERF_SEL_DCACHE_REQ_WRITE_4 = 0xf0,
- SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE = 0xf1,
- SQC_PERF_SEL_SQ_DCACHE_REQS = 0xf2,
- SQC_PERF_SEL_DCACHE_FLAT_REQ = 0xf3,
- SQC_PERF_SEL_DCACHE_NONFLAT_REQ = 0xf4,
- SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 0xf5,
- SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 0xf6,
- SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 0xf7,
- SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 0xf8,
- SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 0xf9,
- SQC_PERF_SEL_ICACHE_GATCL1_TRANSLATION_MISS = 0xfa,
- SQC_PERF_SEL_ICACHE_GATCL1_PERMISSION_MISS = 0xfb,
- SQC_PERF_SEL_ICACHE_GATCL1_REQUEST = 0xfc,
- SQC_PERF_SEL_ICACHE_GATCL1_STALL_INFLIGHT_MAX = 0xfd,
- SQC_PERF_SEL_ICACHE_GATCL1_STALL_LRU_INFLIGHT = 0xfe,
- SQC_PERF_SEL_ICACHE_GATCL1_LFIFO_FULL = 0xff,
- SQC_PERF_SEL_ICACHE_GATCL1_STALL_LFIFO_NOT_RES = 0x100,
- SQC_PERF_SEL_ICACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS= 0x101,
- SQC_PERF_SEL_ICACHE_GATCL1_ATCL2_INFLIGHT = 0x102,
- SQC_PERF_SEL_ICACHE_GATCL1_STALL_MISSFIFO_FULL = 0x103,
- SQC_PERF_SEL_DCACHE_GATCL1_TRANSLATION_MISS = 0x104,
- SQC_PERF_SEL_DCACHE_GATCL1_PERMISSION_MISS = 0x105,
- SQC_PERF_SEL_DCACHE_GATCL1_REQUEST = 0x106,
- SQC_PERF_SEL_DCACHE_GATCL1_STALL_INFLIGHT_MAX = 0x107,
- SQC_PERF_SEL_DCACHE_GATCL1_STALL_LRU_INFLIGHT = 0x108,
- SQC_PERF_SEL_DCACHE_GATCL1_LFIFO_FULL = 0x109,
- SQC_PERF_SEL_DCACHE_GATCL1_STALL_LFIFO_NOT_RES = 0x10a,
- SQC_PERF_SEL_DCACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS= 0x10b,
- SQC_PERF_SEL_DCACHE_GATCL1_ATCL2_INFLIGHT = 0x10c,
- SQC_PERF_SEL_DCACHE_GATCL1_STALL_MISSFIFO_FULL = 0x10d,
- SQC_PERF_SEL_DCACHE_GATCL1_STALL_MULTI_MISS = 0x10e,
- SQC_PERF_SEL_DCACHE_GATCL1_HIT_FIFO_FULL = 0x10f,
- SQC_PERF_SEL_DUMMY_LAST = 0x110,
- SQ_PERF_SEL_INSTS_SMEM_NORM = 0x111,
- SQ_PERF_SEL_ATC_INSTS_VMEM = 0x112,
- SQ_PERF_SEL_ATC_INST_LEVEL_VMEM = 0x113,
- SQ_PERF_SEL_ATC_XNACK_FIRST = 0x114,
- SQ_PERF_SEL_ATC_XNACK_ALL = 0x115,
- SQ_PERF_SEL_ATC_XNACK_FIFO_FULL = 0x116,
- SQ_PERF_SEL_ATC_INSTS_SMEM = 0x117,
- SQ_PERF_SEL_ATC_INST_LEVEL_SMEM = 0x118,
- SQ_PERF_SEL_IFETCH_XNACK = 0x119,
- SQ_PERF_SEL_TLB_SHOOTDOWN = 0x11a,
- SQ_PERF_SEL_TLB_SHOOTDOWN_CYCLES = 0x11b,
- SQ_PERF_SEL_INSTS_VMEM_WR_REPLAY = 0x11c,
- SQ_PERF_SEL_INSTS_VMEM_RD_REPLAY = 0x11d,
- SQ_PERF_SEL_INSTS_VMEM_REPLAY = 0x11e,
- SQ_PERF_SEL_INSTS_SMEM_REPLAY = 0x11f,
- SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY = 0x120,
- SQ_PERF_SEL_INSTS_FLAT_REPLAY = 0x121,
- SQ_PERF_SEL_ATC_INSTS_VMEM_REPLAY = 0x122,
- SQ_PERF_SEL_ATC_INSTS_SMEM_REPLAY = 0x123,
- SQ_PERF_SEL_DUMMY_LAST1 = 0x12a,
-} SQ_PERF_SEL;
-typedef enum SQ_CAC_POWER_SEL {
- SQ_CAC_POWER_VALU = 0x0,
- SQ_CAC_POWER_VALU0 = 0x1,
- SQ_CAC_POWER_VALU1 = 0x2,
- SQ_CAC_POWER_VALU2 = 0x3,
- SQ_CAC_POWER_GPR_RD = 0x4,
- SQ_CAC_POWER_GPR_WR = 0x5,
- SQ_CAC_POWER_LDS_BUSY = 0x6,
- SQ_CAC_POWER_ALU_BUSY = 0x7,
- SQ_CAC_POWER_TEX_BUSY = 0x8,
-} SQ_CAC_POWER_SEL;
-typedef enum SQ_IND_CMD_CMD {
- SQ_IND_CMD_CMD_NULL = 0x0,
- SQ_IND_CMD_CMD_SETHALT = 0x1,
- SQ_IND_CMD_CMD_SAVECTX = 0x2,
- SQ_IND_CMD_CMD_KILL = 0x3,
- SQ_IND_CMD_CMD_DEBUG = 0x4,
- SQ_IND_CMD_CMD_TRAP = 0x5,
- SQ_IND_CMD_CMD_SET_SPI_PRIO = 0x6,
-} SQ_IND_CMD_CMD;
-typedef enum SQ_IND_CMD_MODE {
- SQ_IND_CMD_MODE_SINGLE = 0x0,
- SQ_IND_CMD_MODE_BROADCAST = 0x1,
- SQ_IND_CMD_MODE_BROADCAST_QUEUE = 0x2,
- SQ_IND_CMD_MODE_BROADCAST_PIPE = 0x3,
- SQ_IND_CMD_MODE_BROADCAST_ME = 0x4,
-} SQ_IND_CMD_MODE;
-typedef enum SQ_EDC_INFO_SOURCE {
- SQ_EDC_INFO_SOURCE_INVALID = 0x0,
- SQ_EDC_INFO_SOURCE_INST = 0x1,
- SQ_EDC_INFO_SOURCE_SGPR = 0x2,
- SQ_EDC_INFO_SOURCE_VGPR = 0x3,
- SQ_EDC_INFO_SOURCE_LDS = 0x4,
- SQ_EDC_INFO_SOURCE_GDS = 0x5,
- SQ_EDC_INFO_SOURCE_TA = 0x6,
-} SQ_EDC_INFO_SOURCE;
-typedef enum SQ_ROUND_MODE {
- SQ_ROUND_NEAREST_EVEN = 0x0,
- SQ_ROUND_PLUS_INFINITY = 0x1,
- SQ_ROUND_MINUS_INFINITY = 0x2,
- SQ_ROUND_TO_ZERO = 0x3,
-} SQ_ROUND_MODE;
-typedef enum SQ_INTERRUPT_WORD_ENCODING {
- SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x0,
- SQ_INTERRUPT_WORD_ENCODING_INST = 0x1,
- SQ_INTERRUPT_WORD_ENCODING_ERROR = 0x2,
-} SQ_INTERRUPT_WORD_ENCODING;
-typedef enum ENUM_SQ_EXPORT_RAT_INST {
- SQ_EXPORT_RAT_INST_NOP = 0x0,
- SQ_EXPORT_RAT_INST_STORE_TYPED = 0x1,
- SQ_EXPORT_RAT_INST_STORE_RAW = 0x2,
- SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM = 0x3,
- SQ_EXPORT_RAT_INST_CMPXCHG_INT = 0x4,
- SQ_EXPORT_RAT_INST_CMPXCHG_FLT = 0x5,
- SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM = 0x6,
- SQ_EXPORT_RAT_INST_ADD = 0x7,
- SQ_EXPORT_RAT_INST_SUB = 0x8,
- SQ_EXPORT_RAT_INST_RSUB = 0x9,
- SQ_EXPORT_RAT_INST_MIN_INT = 0xa,
- SQ_EXPORT_RAT_INST_MIN_UINT = 0xb,
- SQ_EXPORT_RAT_INST_MAX_INT = 0xc,
- SQ_EXPORT_RAT_INST_MAX_UINT = 0xd,
- SQ_EXPORT_RAT_INST_AND = 0xe,
- SQ_EXPORT_RAT_INST_OR = 0xf,
- SQ_EXPORT_RAT_INST_XOR = 0x10,
- SQ_EXPORT_RAT_INST_MSKOR = 0x11,
- SQ_EXPORT_RAT_INST_INC_UINT = 0x12,
- SQ_EXPORT_RAT_INST_DEC_UINT = 0x13,
- SQ_EXPORT_RAT_INST_STORE_DWORD = 0x14,
- SQ_EXPORT_RAT_INST_STORE_SHORT = 0x15,
- SQ_EXPORT_RAT_INST_STORE_BYTE = 0x16,
- SQ_EXPORT_RAT_INST_NOP_RTN = 0x20,
- SQ_EXPORT_RAT_INST_XCHG_RTN = 0x22,
- SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN = 0x23,
- SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN = 0x24,
- SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN = 0x25,
- SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN = 0x26,
- SQ_EXPORT_RAT_INST_ADD_RTN = 0x27,
- SQ_EXPORT_RAT_INST_SUB_RTN = 0x28,
- SQ_EXPORT_RAT_INST_RSUB_RTN = 0x29,
- SQ_EXPORT_RAT_INST_MIN_INT_RTN = 0x2a,
- SQ_EXPORT_RAT_INST_MIN_UINT_RTN = 0x2b,
- SQ_EXPORT_RAT_INST_MAX_INT_RTN = 0x2c,
- SQ_EXPORT_RAT_INST_MAX_UINT_RTN = 0x2d,
- SQ_EXPORT_RAT_INST_AND_RTN = 0x2e,
- SQ_EXPORT_RAT_INST_OR_RTN = 0x2f,
- SQ_EXPORT_RAT_INST_XOR_RTN = 0x30,
- SQ_EXPORT_RAT_INST_MSKOR_RTN = 0x31,
- SQ_EXPORT_RAT_INST_INC_UINT_RTN = 0x32,
- SQ_EXPORT_RAT_INST_DEC_UINT_RTN = 0x33,
-} ENUM_SQ_EXPORT_RAT_INST;
-typedef enum SQ_IBUF_ST {
- SQ_IBUF_IB_IDLE = 0x0,
- SQ_IBUF_IB_INI_WAIT_GNT = 0x1,
- SQ_IBUF_IB_INI_WAIT_DRET = 0x2,
- SQ_IBUF_IB_LE_4DW = 0x3,
- SQ_IBUF_IB_WAIT_DRET = 0x4,
- SQ_IBUF_IB_EMPTY_WAIT_DRET = 0x5,
- SQ_IBUF_IB_DRET = 0x6,
- SQ_IBUF_IB_EMPTY_WAIT_GNT = 0x7,
-} SQ_IBUF_ST;
-typedef enum SQ_INST_STR_ST {
- SQ_INST_STR_IB_WAVE_NORML = 0x0,
- SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 0x1,
- SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 0x2,
- SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 0x3,
- SQ_INST_STR_IB_WAVE_SETVSKIP_ST0 = 0x4,
- SQ_INST_STR_IB_WAVE_SETVSKIP_ST1 = 0x5,
- SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 0x6,
- SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 0x7,
-} SQ_INST_STR_ST;
-typedef enum SQ_WAVE_IB_ECC_ST {
- SQ_WAVE_IB_ECC_CLEAN = 0x0,
- SQ_WAVE_IB_ECC_ERR_CONTINUE = 0x1,
- SQ_WAVE_IB_ECC_ERR_HALT = 0x2,
- SQ_WAVE_IB_ECC_WITH_ERR_MSG = 0x3,
-} SQ_WAVE_IB_ECC_ST;
-typedef enum SH_MEM_ADDRESS_MODE {
- SH_MEM_ADDRESS_MODE_GPUVM64 = 0x0,
- SH_MEM_ADDRESS_MODE_GPUVM32 = 0x1,
- SH_MEM_ADDRESS_MODE_HSA64 = 0x2,
- SH_MEM_ADDRESS_MODE_HSA32 = 0x3,
-} SH_MEM_ADDRESS_MODE;
-typedef enum SH_MEM_ALIGNMENT_MODE {
- SH_MEM_ALIGNMENT_MODE_DWORD = 0x0,
- SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 0x1,
- SH_MEM_ALIGNMENT_MODE_STRICT = 0x2,
- SH_MEM_ALIGNMENT_MODE_UNALIGNED = 0x3,
-} SH_MEM_ALIGNMENT_MODE;
-typedef enum SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX {
- SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_WREXEC = 0x18,
- SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_RESTORE = 0x19,
-} SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX;
-#define SQ_WAVE_TYPE_PS0 0x0
-#define SQIND_GLOBAL_REGS_OFFSET 0x0
-#define SQIND_GLOBAL_REGS_SIZE 0x8
-#define SQIND_LOCAL_REGS_OFFSET 0x8
-#define SQIND_LOCAL_REGS_SIZE 0x8
-#define SQIND_WAVE_HWREGS_OFFSET 0x10
-#define SQIND_WAVE_HWREGS_SIZE 0x1f0
-#define SQIND_WAVE_SGPRS_OFFSET 0x200
-#define SQIND_WAVE_SGPRS_SIZE 0x200
-#define SQ_GFXDEC_BEGIN 0xa000
-#define SQ_GFXDEC_END 0xc000
-#define SQ_GFXDEC_STATE_ID_SHIFT 0xa
-#define SQDEC_BEGIN 0x2300
-#define SQDEC_END 0x23ff
-#define SQPERFSDEC_BEGIN 0xd9c0
-#define SQPERFSDEC_END 0xda40
-#define SQPERFDDEC_BEGIN 0xd1c0
-#define SQPERFDDEC_END 0xd240
-#define SQGFXUDEC_BEGIN 0xc330
-#define SQGFXUDEC_END 0xc380
-#define SQPWRDEC_BEGIN 0xf08c
-#define SQPWRDEC_END 0xf094
-#define SQ_DISPATCHER_GFX_MIN 0x10
-#define SQ_DISPATCHER_GFX_CNT_PER_RING 0x8
-#define SQ_MAX_PGM_SGPRS 0x68
-#define SQ_MAX_PGM_VGPRS 0x100
-#define SQ_THREAD_TRACE_TIME_UNIT 0x4
-#define SQ_EX_MODE_EXCP_VALU_BASE 0x0
-#define SQ_EX_MODE_EXCP_VALU_SIZE 0x7
-#define SQ_EX_MODE_EXCP_INVALID 0x0
-#define SQ_EX_MODE_EXCP_INPUT_DENORM 0x1
-#define SQ_EX_MODE_EXCP_DIV0 0x2
-#define SQ_EX_MODE_EXCP_OVERFLOW 0x3
-#define SQ_EX_MODE_EXCP_UNDERFLOW 0x4
-#define SQ_EX_MODE_EXCP_INEXACT 0x5
-#define SQ_EX_MODE_EXCP_INT_DIV0 0x6
-#define SQ_EX_MODE_EXCP_ADDR_WATCH 0x7
-#define SQ_EX_MODE_EXCP_MEM_VIOL 0x8
-#define INST_ID_PRIV_START 0x80000000
-#define INST_ID_ECC_INTERRUPT_MSG 0xfffffff0
-#define INST_ID_TTRACE_NEW_PC_MSG 0xfffffff1
-#define INST_ID_HW_TRAP 0xfffffff2
-#define INST_ID_KILL_SEQ 0xfffffff3
-#define INST_ID_SPI_WREXEC 0xfffffff4
-#define INST_ID_HOST_REG_TRAP_MSG 0xfffffffe
-#define SQ_ENC_SOP1_BITS 0xbe800000
-#define SQ_ENC_SOP1_MASK 0xff800000
-#define SQ_ENC_SOP1_FIELD 0x17d
-#define SQ_ENC_SOPC_BITS 0xbf000000
-#define SQ_ENC_SOPC_MASK 0xff800000
-#define SQ_ENC_SOPC_FIELD 0x17e
-#define SQ_ENC_SOPP_BITS 0xbf800000
-#define SQ_ENC_SOPP_MASK 0xff800000
-#define SQ_ENC_SOPP_FIELD 0x17f
-#define SQ_ENC_SOPK_BITS 0xb0000000
-#define SQ_ENC_SOPK_MASK 0xf0000000
-#define SQ_ENC_SOPK_FIELD 0xb
-#define SQ_ENC_SOP2_BITS 0x80000000
-#define SQ_ENC_SOP2_MASK 0xc0000000
-#define SQ_ENC_SOP2_FIELD 0x2
-#define SQ_ENC_SMEM_BITS 0xc0000000
-#define SQ_ENC_SMEM_MASK 0xfc000000
-#define SQ_ENC_SMEM_FIELD 0x30
-#define SQ_ENC_VOP1_BITS 0x7e000000
-#define SQ_ENC_VOP1_MASK 0xfe000000
-#define SQ_ENC_VOP1_FIELD 0x3f
-#define SQ_ENC_VOPC_BITS 0x7c000000
-#define SQ_ENC_VOPC_MASK 0xfe000000
-#define SQ_ENC_VOPC_FIELD 0x3e
-#define SQ_ENC_VOP2_BITS 0x0
-#define SQ_ENC_VOP2_MASK 0x80000000
-#define SQ_ENC_VOP2_FIELD 0x0
-#define SQ_ENC_VINTRP_BITS 0xd4000000
-#define SQ_ENC_VINTRP_MASK 0xfc000000
-#define SQ_ENC_VINTRP_FIELD 0x35
-#define SQ_ENC_VOP3_BITS 0xd0000000
-#define SQ_ENC_VOP3_MASK 0xfc000000
-#define SQ_ENC_VOP3_FIELD 0x34
-#define SQ_ENC_DS_BITS 0xd8000000
-#define SQ_ENC_DS_MASK 0xfc000000
-#define SQ_ENC_DS_FIELD 0x36
-#define SQ_ENC_MUBUF_BITS 0xe0000000
-#define SQ_ENC_MUBUF_MASK 0xfc000000
-#define SQ_ENC_MUBUF_FIELD 0x38
-#define SQ_ENC_MTBUF_BITS 0xe8000000
-#define SQ_ENC_MTBUF_MASK 0xfc000000
-#define SQ_ENC_MTBUF_FIELD 0x3a
-#define SQ_ENC_MIMG_BITS 0xf0000000
-#define SQ_ENC_MIMG_MASK 0xfc000000
-#define SQ_ENC_MIMG_FIELD 0x3c
-#define SQ_ENC_EXP_BITS 0xc4000000
-#define SQ_ENC_EXP_MASK 0xfc000000
-#define SQ_ENC_EXP_FIELD 0x31
-#define SQ_ENC_FLAT_BITS 0xdc000000
-#define SQ_ENC_FLAT_MASK 0xfc000000
-#define SQ_ENC_FLAT_FIELD 0x37
-#define SQ_V_OP3_INTRP_OFFSET 0x274
-#define SQ_WAITCNT_VM_SHIFT 0x0
-#define SQ_SENDMSG_STREAMID_SIZE 0x2
-#define SQ_V_OPC_COUNT 0x100
-#define SQ_V_OP3_INTRP_COUNT 0xc
-#define SQ_XLATE_VOP3_TO_VOP2_OFFSET 0x100
-#define SQ_HWREG_OFFSET_SIZE 0x5
-#define SQ_HWREG_OFFSET_SHIFT 0x6
-#define SQ_V_OP3_3IN_OFFSET 0x1c0
-#define SQ_NUM_ATTR 0x21
-#define SQ_NUM_VGPR 0x100
-#define SQ_XLATE_VOP3_TO_VINTRP_COUNT 0x4
-#define SQ_SENDMSG_MSG_SIZE 0x4
-#define SQ_NUM_TTMP 0xc
-#define SQ_HWREG_ID_SIZE 0x6
-#define SQ_SENDMSG_GSOP_SIZE 0x2
-#define SQ_NUM_SGPR 0x66
-#define SQ_EXP_NUM_MRT 0x8
-#define SQ_SENDMSG_SYSTEM_SIZE 0x3
-#define SQ_WAITCNT_LGKM_SHIFT 0x8
-#define SQ_XLATE_VOP3_TO_VOP2_COUNT 0x40
-#define SQ_V_OP3_3IN_COUNT 0xb0
-#define SQ_V_INTRP_COUNT 0x4
-#define SQ_WAITCNT_EXP_SIZE 0x3
-#define SQ_SENDMSG_SYSTEM_SHIFT 0x4
-#define SQ_EXP_NUM_GDS 0x5
-#define SQ_HWREG_SIZE_SHIFT 0xb
-#define SQ_XLATE_VOP3_TO_VOPC_OFFSET 0x0
-#define SQ_V_OP3_2IN_COUNT 0x80
-#define SQ_XLATE_VOP3_TO_VINTRP_OFFSET 0x270
-#define SQ_SENDMSG_MSG_SHIFT 0x0
-#define SQ_WAITCNT_EXP_SHIFT 0x4
-#define SQ_WAITCNT_VM_SIZE 0x4
-#define SQ_XLATE_VOP3_TO_VOP1_OFFSET 0x140
-#define SQ_SENDMSG_GSOP_SHIFT 0x4
-#define SQ_XLATE_VOP3_TO_VOP1_COUNT 0x80
-#define SQ_SRC_VGPR_BIT 0x100
-#define SQ_V_OP2_COUNT 0x40
-#define SQ_EXP_NUM_PARAM 0x20
-#define SQ_V_OP1_COUNT 0x80
-#define SQ_SENDMSG_STREAMID_SHIFT 0x8
-#define SQ_V_OP3_2IN_OFFSET 0x280
-#define SQ_WAITCNT_LGKM_SIZE 0x4
-#define SQ_XLATE_VOP3_TO_VOPC_COUNT 0x100
-#define SQ_EXP_NUM_POS 0x4
-#define SQ_HWREG_SIZE_SIZE 0x5
-#define SQ_HWREG_ID_SHIFT 0x0
-#define SQ_S_MOV_B32 0x0
-#define SQ_S_MOV_B64 0x1
-#define SQ_S_CMOV_B32 0x2
-#define SQ_S_CMOV_B64 0x3
-#define SQ_S_NOT_B32 0x4
-#define SQ_S_NOT_B64 0x5
-#define SQ_S_WQM_B32 0x6
-#define SQ_S_WQM_B64 0x7
-#define SQ_S_BREV_B32 0x8
-#define SQ_S_BREV_B64 0x9
-#define SQ_S_BCNT0_I32_B32 0xa
-#define SQ_S_BCNT0_I32_B64 0xb
-#define SQ_S_BCNT1_I32_B32 0xc
-#define SQ_S_BCNT1_I32_B64 0xd
-#define SQ_S_FF0_I32_B32 0xe
-#define SQ_S_FF0_I32_B64 0xf
-#define SQ_S_FF1_I32_B32 0x10
-#define SQ_S_FF1_I32_B64 0x11
-#define SQ_S_FLBIT_I32_B32 0x12
-#define SQ_S_FLBIT_I32_B64 0x13
-#define SQ_S_FLBIT_I32 0x14
-#define SQ_S_FLBIT_I32_I64 0x15
-#define SQ_S_SEXT_I32_I8 0x16
-#define SQ_S_SEXT_I32_I16 0x17
-#define SQ_S_BITSET0_B32 0x18
-#define SQ_S_BITSET0_B64 0x19
-#define SQ_S_BITSET1_B32 0x1a
-#define SQ_S_BITSET1_B64 0x1b
-#define SQ_S_GETPC_B64 0x1c
-#define SQ_S_SETPC_B64 0x1d
-#define SQ_S_SWAPPC_B64 0x1e
-#define SQ_S_RFE_B64 0x1f
-#define SQ_S_AND_SAVEEXEC_B64 0x20
-#define SQ_S_OR_SAVEEXEC_B64 0x21
-#define SQ_S_XOR_SAVEEXEC_B64 0x22
-#define SQ_S_ANDN2_SAVEEXEC_B64 0x23
-#define SQ_S_ORN2_SAVEEXEC_B64 0x24
-#define SQ_S_NAND_SAVEEXEC_B64 0x25
-#define SQ_S_NOR_SAVEEXEC_B64 0x26
-#define SQ_S_XNOR_SAVEEXEC_B64 0x27
-#define SQ_S_QUADMASK_B32 0x28
-#define SQ_S_QUADMASK_B64 0x29
-#define SQ_S_MOVRELS_B32 0x2a
-#define SQ_S_MOVRELS_B64 0x2b
-#define SQ_S_MOVRELD_B32 0x2c
-#define SQ_S_MOVRELD_B64 0x2d
-#define SQ_S_CBRANCH_JOIN 0x2e
-#define SQ_S_MOV_REGRD_B32 0x2f
-#define SQ_S_ABS_I32 0x30
-#define SQ_S_MOV_FED_B32 0x31
-#define SQ_S_SET_GPR_IDX_IDX 0x32
-#define SQ_ATTR0 0x0
-#define SQ_S_MOVK_I32 0x0
-#define SQ_S_CMOVK_I32 0x1
-#define SQ_S_CMPK_EQ_I32 0x2
-#define SQ_S_CMPK_LG_I32 0x3
-#define SQ_S_CMPK_GT_I32 0x4
-#define SQ_S_CMPK_GE_I32 0x5
-#define SQ_S_CMPK_LT_I32 0x6
-#define SQ_S_CMPK_LE_I32 0x7
-#define SQ_S_CMPK_EQ_U32 0x8
-#define SQ_S_CMPK_LG_U32 0x9
-#define SQ_S_CMPK_GT_U32 0xa
-#define SQ_S_CMPK_GE_U32 0xb
-#define SQ_S_CMPK_LT_U32 0xc
-#define SQ_S_CMPK_LE_U32 0xd
-#define SQ_S_ADDK_I32 0xe
-#define SQ_S_MULK_I32 0xf
-#define SQ_S_CBRANCH_I_FORK 0x10
-#define SQ_S_GETREG_B32 0x11
-#define SQ_S_SETREG_B32 0x12
-#define SQ_S_GETREG_REGRD_B32 0x13
-#define SQ_S_SETREG_IMM32_B32 0x14
-#define SQ_TBA_LO 0x6c
-#define SQ_TBA_HI 0x6d
-#define SQ_TMA_LO 0x6e
-#define SQ_TMA_HI 0x6f
-#define SQ_TTMP0 0x70
-#define SQ_TTMP1 0x71
-#define SQ_TTMP2 0x72
-#define SQ_TTMP3 0x73
-#define SQ_TTMP4 0x74
-#define SQ_TTMP5 0x75
-#define SQ_TTMP6 0x76
-#define SQ_TTMP7 0x77
-#define SQ_TTMP8 0x78
-#define SQ_TTMP9 0x79
-#define SQ_TTMP10 0x7a
-#define SQ_TTMP11 0x7b
-#define SQ_VGPR0 0x0
-#define SQ_EXP 0x0
-#define SQ_EXP_MRT0 0x0
-#define SQ_EXP_MRTZ 0x8
-#define SQ_EXP_NULL 0x9
-#define SQ_EXP_POS0 0xc
-#define SQ_EXP_PARAM0 0x20
-#define SQ_CNT1 0x0
-#define SQ_CNT2 0x1
-#define SQ_CNT3 0x2
-#define SQ_CNT4 0x3
-#define SQ_S_LOAD_DWORD 0x0
-#define SQ_S_LOAD_DWORDX2 0x1
-#define SQ_S_LOAD_DWORDX4 0x2
-#define SQ_S_LOAD_DWORDX8 0x3
-#define SQ_S_LOAD_DWORDX16 0x4
-#define SQ_S_BUFFER_LOAD_DWORD 0x8
-#define SQ_S_BUFFER_LOAD_DWORDX2 0x9
-#define SQ_S_BUFFER_LOAD_DWORDX4 0xa
-#define SQ_S_BUFFER_LOAD_DWORDX8 0xb
-#define SQ_S_BUFFER_LOAD_DWORDX16 0xc
-#define SQ_S_STORE_DWORD 0x10
-#define SQ_S_STORE_DWORDX2 0x11
-#define SQ_S_STORE_DWORDX4 0x12
-#define SQ_S_BUFFER_STORE_DWORD 0x18
-#define SQ_S_BUFFER_STORE_DWORDX2 0x19
-#define SQ_S_BUFFER_STORE_DWORDX4 0x1a
-#define SQ_S_DCACHE_INV 0x20
-#define SQ_S_DCACHE_WB 0x21
-#define SQ_S_DCACHE_INV_VOL 0x22
-#define SQ_S_DCACHE_WB_VOL 0x23
-#define SQ_S_MEMTIME 0x24
-#define SQ_S_MEMREALTIME 0x25
-#define SQ_S_ATC_PROBE 0x26
-#define SQ_S_ATC_PROBE_BUFFER 0x27
-#define SQ_S_BUFFER_ATOMIC_SWAP 0x40
-#define SQ_S_BUFFER_ATOMIC_CMPSWAP 0x41
-#define SQ_S_BUFFER_ATOMIC_ADD 0x42
-#define SQ_S_BUFFER_ATOMIC_SUB 0x43
-#define SQ_S_BUFFER_ATOMIC_SMIN 0x44
-#define SQ_S_BUFFER_ATOMIC_UMIN 0x45
-#define SQ_S_BUFFER_ATOMIC_SMAX 0x46
-#define SQ_S_BUFFER_ATOMIC_UMAX 0x47
-#define SQ_S_BUFFER_ATOMIC_AND 0x48
-#define SQ_S_BUFFER_ATOMIC_OR 0x49
-#define SQ_S_BUFFER_ATOMIC_XOR 0x4a
-#define SQ_S_BUFFER_ATOMIC_INC 0x4b
-#define SQ_S_BUFFER_ATOMIC_DEC 0x4c
-#define SQ_S_BUFFER_ATOMIC_SWAP_X2 0x60
-#define SQ_S_BUFFER_ATOMIC_CMPSWAP_X2 0x61
-#define SQ_S_BUFFER_ATOMIC_ADD_X2 0x62
-#define SQ_S_BUFFER_ATOMIC_SUB_X2 0x63
-#define SQ_S_BUFFER_ATOMIC_SMIN_X2 0x64
-#define SQ_S_BUFFER_ATOMIC_UMIN_X2 0x65
-#define SQ_S_BUFFER_ATOMIC_SMAX_X2 0x66
-#define SQ_S_BUFFER_ATOMIC_UMAX_X2 0x67
-#define SQ_S_BUFFER_ATOMIC_AND_X2 0x68
-#define SQ_S_BUFFER_ATOMIC_OR_X2 0x69
-#define SQ_S_BUFFER_ATOMIC_XOR_X2 0x6a
-#define SQ_S_BUFFER_ATOMIC_INC_X2 0x6b
-#define SQ_S_BUFFER_ATOMIC_DEC_X2 0x6c
-#define SQ_F 0x0
-#define SQ_LT 0x1
-#define SQ_EQ 0x2
-#define SQ_LE 0x3
-#define SQ_GT 0x4
-#define SQ_LG 0x5
-#define SQ_GE 0x6
-#define SQ_O 0x7
-#define SQ_U 0x8
-#define SQ_NGE 0x9
-#define SQ_NLG 0xa
-#define SQ_NGT 0xb
-#define SQ_NLE 0xc
-#define SQ_NEQ 0xd
-#define SQ_NLT 0xe
-#define SQ_TRU 0xf
-#define SQ_V_CMP_CLASS_F32 0x10
-#define SQ_V_CMPX_CLASS_F32 0x11
-#define SQ_V_CMP_CLASS_F64 0x12
-#define SQ_V_CMPX_CLASS_F64 0x13
-#define SQ_V_CMP_CLASS_F16 0x14
-#define SQ_V_CMPX_CLASS_F16 0x15
-#define SQ_V_CMP_F_F16 0x20
-#define SQ_V_CMP_LT_F16 0x21
-#define SQ_V_CMP_EQ_F16 0x22
-#define SQ_V_CMP_LE_F16 0x23
-#define SQ_V_CMP_GT_F16 0x24
-#define SQ_V_CMP_LG_F16 0x25
-#define SQ_V_CMP_GE_F16 0x26
-#define SQ_V_CMP_O_F16 0x27
-#define SQ_V_CMP_U_F16 0x28
-#define SQ_V_CMP_NGE_F16 0x29
-#define SQ_V_CMP_NLG_F16 0x2a
-#define SQ_V_CMP_NGT_F16 0x2b
-#define SQ_V_CMP_NLE_F16 0x2c
-#define SQ_V_CMP_NEQ_F16 0x2d
-#define SQ_V_CMP_NLT_F16 0x2e
-#define SQ_V_CMP_TRU_F16 0x2f
-#define SQ_V_CMPX_F_F16 0x30
-#define SQ_V_CMPX_LT_F16 0x31
-#define SQ_V_CMPX_EQ_F16 0x32
-#define SQ_V_CMPX_LE_F16 0x33
-#define SQ_V_CMPX_GT_F16 0x34
-#define SQ_V_CMPX_LG_F16 0x35
-#define SQ_V_CMPX_GE_F16 0x36
-#define SQ_V_CMPX_O_F16 0x37
-#define SQ_V_CMPX_U_F16 0x38
-#define SQ_V_CMPX_NGE_F16 0x39
-#define SQ_V_CMPX_NLG_F16 0x3a
-#define SQ_V_CMPX_NGT_F16 0x3b
-#define SQ_V_CMPX_NLE_F16 0x3c
-#define SQ_V_CMPX_NEQ_F16 0x3d
-#define SQ_V_CMPX_NLT_F16 0x3e
-#define SQ_V_CMPX_TRU_F16 0x3f
-#define SQ_V_CMP_F_F32 0x40
-#define SQ_V_CMP_LT_F32 0x41
-#define SQ_V_CMP_EQ_F32 0x42
-#define SQ_V_CMP_LE_F32 0x43
-#define SQ_V_CMP_GT_F32 0x44
-#define SQ_V_CMP_LG_F32 0x45
-#define SQ_V_CMP_GE_F32 0x46
-#define SQ_V_CMP_O_F32 0x47
-#define SQ_V_CMP_U_F32 0x48
-#define SQ_V_CMP_NGE_F32 0x49
-#define SQ_V_CMP_NLG_F32 0x4a
-#define SQ_V_CMP_NGT_F32 0x4b
-#define SQ_V_CMP_NLE_F32 0x4c
-#define SQ_V_CMP_NEQ_F32 0x4d
-#define SQ_V_CMP_NLT_F32 0x4e
-#define SQ_V_CMP_TRU_F32 0x4f
-#define SQ_V_CMPX_F_F32 0x50
-#define SQ_V_CMPX_LT_F32 0x51
-#define SQ_V_CMPX_EQ_F32 0x52
-#define SQ_V_CMPX_LE_F32 0x53
-#define SQ_V_CMPX_GT_F32 0x54
-#define SQ_V_CMPX_LG_F32 0x55
-#define SQ_V_CMPX_GE_F32 0x56
-#define SQ_V_CMPX_O_F32 0x57
-#define SQ_V_CMPX_U_F32 0x58
-#define SQ_V_CMPX_NGE_F32 0x59
-#define SQ_V_CMPX_NLG_F32 0x5a
-#define SQ_V_CMPX_NGT_F32 0x5b
-#define SQ_V_CMPX_NLE_F32 0x5c
-#define SQ_V_CMPX_NEQ_F32 0x5d
-#define SQ_V_CMPX_NLT_F32 0x5e
-#define SQ_V_CMPX_TRU_F32 0x5f
-#define SQ_V_CMP_F_F64 0x60
-#define SQ_V_CMP_LT_F64 0x61
-#define SQ_V_CMP_EQ_F64 0x62
-#define SQ_V_CMP_LE_F64 0x63
-#define SQ_V_CMP_GT_F64 0x64
-#define SQ_V_CMP_LG_F64 0x65
-#define SQ_V_CMP_GE_F64 0x66
-#define SQ_V_CMP_O_F64 0x67
-#define SQ_V_CMP_U_F64 0x68
-#define SQ_V_CMP_NGE_F64 0x69
-#define SQ_V_CMP_NLG_F64 0x6a
-#define SQ_V_CMP_NGT_F64 0x6b
-#define SQ_V_CMP_NLE_F64 0x6c
-#define SQ_V_CMP_NEQ_F64 0x6d
-#define SQ_V_CMP_NLT_F64 0x6e
-#define SQ_V_CMP_TRU_F64 0x6f
-#define SQ_V_CMPX_F_F64 0x70
-#define SQ_V_CMPX_LT_F64 0x71
-#define SQ_V_CMPX_EQ_F64 0x72
-#define SQ_V_CMPX_LE_F64 0x73
-#define SQ_V_CMPX_GT_F64 0x74
-#define SQ_V_CMPX_LG_F64 0x75
-#define SQ_V_CMPX_GE_F64 0x76
-#define SQ_V_CMPX_O_F64 0x77
-#define SQ_V_CMPX_U_F64 0x78
-#define SQ_V_CMPX_NGE_F64 0x79
-#define SQ_V_CMPX_NLG_F64 0x7a
-#define SQ_V_CMPX_NGT_F64 0x7b
-#define SQ_V_CMPX_NLE_F64 0x7c
-#define SQ_V_CMPX_NEQ_F64 0x7d
-#define SQ_V_CMPX_NLT_F64 0x7e
-#define SQ_V_CMPX_TRU_F64 0x7f
-#define SQ_V_CMP_F_I16 0xa0
-#define SQ_V_CMP_LT_I16 0xa1
-#define SQ_V_CMP_EQ_I16 0xa2
-#define SQ_V_CMP_LE_I16 0xa3
-#define SQ_V_CMP_GT_I16 0xa4
-#define SQ_V_CMP_NE_I16 0xa5
-#define SQ_V_CMP_GE_I16 0xa6
-#define SQ_V_CMP_T_I16 0xa7
-#define SQ_V_CMP_F_U16 0xa8
-#define SQ_V_CMP_LT_U16 0xa9
-#define SQ_V_CMP_EQ_U16 0xaa
-#define SQ_V_CMP_LE_U16 0xab
-#define SQ_V_CMP_GT_U16 0xac
-#define SQ_V_CMP_NE_U16 0xad
-#define SQ_V_CMP_GE_U16 0xae
-#define SQ_V_CMP_T_U16 0xaf
-#define SQ_V_CMPX_F_I16 0xb0
-#define SQ_V_CMPX_LT_I16 0xb1
-#define SQ_V_CMPX_EQ_I16 0xb2
-#define SQ_V_CMPX_LE_I16 0xb3
-#define SQ_V_CMPX_GT_I16 0xb4
-#define SQ_V_CMPX_NE_I16 0xb5
-#define SQ_V_CMPX_GE_I16 0xb6
-#define SQ_V_CMPX_T_I16 0xb7
-#define SQ_V_CMPX_F_U16 0xb8
-#define SQ_V_CMPX_LT_U16 0xb9
-#define SQ_V_CMPX_EQ_U16 0xba
-#define SQ_V_CMPX_LE_U16 0xbb
-#define SQ_V_CMPX_GT_U16 0xbc
-#define SQ_V_CMPX_NE_U16 0xbd
-#define SQ_V_CMPX_GE_U16 0xbe
-#define SQ_V_CMPX_T_U16 0xbf
-#define SQ_V_CMP_F_I32 0xc0
-#define SQ_V_CMP_LT_I32 0xc1
-#define SQ_V_CMP_EQ_I32 0xc2
-#define SQ_V_CMP_LE_I32 0xc3
-#define SQ_V_CMP_GT_I32 0xc4
-#define SQ_V_CMP_NE_I32 0xc5
-#define SQ_V_CMP_GE_I32 0xc6
-#define SQ_V_CMP_T_I32 0xc7
-#define SQ_V_CMP_F_U32 0xc8
-#define SQ_V_CMP_LT_U32 0xc9
-#define SQ_V_CMP_EQ_U32 0xca
-#define SQ_V_CMP_LE_U32 0xcb
-#define SQ_V_CMP_GT_U32 0xcc
-#define SQ_V_CMP_NE_U32 0xcd
-#define SQ_V_CMP_GE_U32 0xce
-#define SQ_V_CMP_T_U32 0xcf
-#define SQ_V_CMPX_F_I32 0xd0
-#define SQ_V_CMPX_LT_I32 0xd1
-#define SQ_V_CMPX_EQ_I32 0xd2
-#define SQ_V_CMPX_LE_I32 0xd3
-#define SQ_V_CMPX_GT_I32 0xd4
-#define SQ_V_CMPX_NE_I32 0xd5
-#define SQ_V_CMPX_GE_I32 0xd6
-#define SQ_V_CMPX_T_I32 0xd7
-#define SQ_V_CMPX_F_U32 0xd8
-#define SQ_V_CMPX_LT_U32 0xd9
-#define SQ_V_CMPX_EQ_U32 0xda
-#define SQ_V_CMPX_LE_U32 0xdb
-#define SQ_V_CMPX_GT_U32 0xdc
-#define SQ_V_CMPX_NE_U32 0xdd
-#define SQ_V_CMPX_GE_U32 0xde
-#define SQ_V_CMPX_T_U32 0xdf
-#define SQ_V_CMP_F_I64 0xe0
-#define SQ_V_CMP_LT_I64 0xe1
-#define SQ_V_CMP_EQ_I64 0xe2
-#define SQ_V_CMP_LE_I64 0xe3
-#define SQ_V_CMP_GT_I64 0xe4
-#define SQ_V_CMP_NE_I64 0xe5
-#define SQ_V_CMP_GE_I64 0xe6
-#define SQ_V_CMP_T_I64 0xe7
-#define SQ_V_CMP_F_U64 0xe8
-#define SQ_V_CMP_LT_U64 0xe9
-#define SQ_V_CMP_EQ_U64 0xea
-#define SQ_V_CMP_LE_U64 0xeb
-#define SQ_V_CMP_GT_U64 0xec
-#define SQ_V_CMP_NE_U64 0xed
-#define SQ_V_CMP_GE_U64 0xee
-#define SQ_V_CMP_T_U64 0xef
-#define SQ_V_CMPX_F_I64 0xf0
-#define SQ_V_CMPX_LT_I64 0xf1
-#define SQ_V_CMPX_EQ_I64 0xf2
-#define SQ_V_CMPX_LE_I64 0xf3
-#define SQ_V_CMPX_GT_I64 0xf4
-#define SQ_V_CMPX_NE_I64 0xf5
-#define SQ_V_CMPX_GE_I64 0xf6
-#define SQ_V_CMPX_T_I64 0xf7
-#define SQ_V_CMPX_F_U64 0xf8
-#define SQ_V_CMPX_LT_U64 0xf9
-#define SQ_V_CMPX_EQ_U64 0xfa
-#define SQ_V_CMPX_LE_U64 0xfb
-#define SQ_V_CMPX_GT_U64 0xfc
-#define SQ_V_CMPX_NE_U64 0xfd
-#define SQ_V_CMPX_GE_U64 0xfe
-#define SQ_V_CMPX_T_U64 0xff
-#define SQ_L1 0x1
-#define SQ_L2 0x2
-#define SQ_L3 0x3
-#define SQ_L4 0x4
-#define SQ_L5 0x5
-#define SQ_L6 0x6
-#define SQ_L7 0x7
-#define SQ_L8 0x8
-#define SQ_L9 0x9
-#define SQ_L10 0xa
-#define SQ_L11 0xb
-#define SQ_L12 0xc
-#define SQ_L13 0xd
-#define SQ_L14 0xe
-#define SQ_L15 0xf
-#define SQ_SGPR0 0x0
-#define SQ_SDWA_UNUSED_PAD 0x0
-#define SQ_SDWA_UNUSED_SEXT 0x1
-#define SQ_SDWA_UNUSED_PRESERVE 0x2
-#define SQ_F 0x0
-#define SQ_LT 0x1
-#define SQ_EQ 0x2
-#define SQ_LE 0x3
-#define SQ_GT 0x4
-#define SQ_NE 0x5
-#define SQ_GE 0x6
-#define SQ_T 0x7
-#define SQ_SRC_64_INT 0xc0
-#define SQ_SRC_M_1_INT 0xc1
-#define SQ_SRC_M_2_INT 0xc2
-#define SQ_SRC_M_3_INT 0xc3
-#define SQ_SRC_M_4_INT 0xc4
-#define SQ_SRC_M_5_INT 0xc5
-#define SQ_SRC_M_6_INT 0xc6
-#define SQ_SRC_M_7_INT 0xc7
-#define SQ_SRC_M_8_INT 0xc8
-#define SQ_SRC_M_9_INT 0xc9
-#define SQ_SRC_M_10_INT 0xca
-#define SQ_SRC_M_11_INT 0xcb
-#define SQ_SRC_M_12_INT 0xcc
-#define SQ_SRC_M_13_INT 0xcd
-#define SQ_SRC_M_14_INT 0xce
-#define SQ_SRC_M_15_INT 0xcf
-#define SQ_SRC_M_16_INT 0xd0
-#define SQ_SRC_0_5 0xf0
-#define SQ_SRC_M_0_5 0xf1
-#define SQ_SRC_1 0xf2
-#define SQ_SRC_M_1 0xf3
-#define SQ_SRC_2 0xf4
-#define SQ_SRC_M_2 0xf5
-#define SQ_SRC_4 0xf6
-#define SQ_SRC_M_4 0xf7
-#define SQ_SRC_INV_2PI 0xf8
-#define SQ_SRC_0 0x80
-#define SQ_SRC_1_INT 0x81
-#define SQ_SRC_2_INT 0x82
-#define SQ_SRC_3_INT 0x83
-#define SQ_SRC_4_INT 0x84
-#define SQ_SRC_5_INT 0x85
-#define SQ_SRC_6_INT 0x86
-#define SQ_SRC_7_INT 0x87
-#define SQ_SRC_8_INT 0x88
-#define SQ_SRC_9_INT 0x89
-#define SQ_SRC_10_INT 0x8a
-#define SQ_SRC_11_INT 0x8b
-#define SQ_SRC_12_INT 0x8c
-#define SQ_SRC_13_INT 0x8d
-#define SQ_SRC_14_INT 0x8e
-#define SQ_SRC_15_INT 0x8f
-#define SQ_SRC_16_INT 0x90
-#define SQ_SRC_17_INT 0x91
-#define SQ_SRC_18_INT 0x92
-#define SQ_SRC_19_INT 0x93
-#define SQ_SRC_20_INT 0x94
-#define SQ_SRC_21_INT 0x95
-#define SQ_SRC_22_INT 0x96
-#define SQ_SRC_23_INT 0x97
-#define SQ_SRC_24_INT 0x98
-#define SQ_SRC_25_INT 0x99
-#define SQ_SRC_26_INT 0x9a
-#define SQ_SRC_27_INT 0x9b
-#define SQ_SRC_28_INT 0x9c
-#define SQ_SRC_29_INT 0x9d
-#define SQ_SRC_30_INT 0x9e
-#define SQ_SRC_31_INT 0x9f
-#define SQ_SRC_32_INT 0xa0
-#define SQ_SRC_33_INT 0xa1
-#define SQ_SRC_34_INT 0xa2
-#define SQ_SRC_35_INT 0xa3
-#define SQ_SRC_36_INT 0xa4
-#define SQ_SRC_37_INT 0xa5
-#define SQ_SRC_38_INT 0xa6
-#define SQ_SRC_39_INT 0xa7
-#define SQ_SRC_40_INT 0xa8
-#define SQ_SRC_41_INT 0xa9
-#define SQ_SRC_42_INT 0xaa
-#define SQ_SRC_43_INT 0xab
-#define SQ_SRC_44_INT 0xac
-#define SQ_SRC_45_INT 0xad
-#define SQ_SRC_46_INT 0xae
-#define SQ_SRC_47_INT 0xaf
-#define SQ_SRC_48_INT 0xb0
-#define SQ_SRC_49_INT 0xb1
-#define SQ_SRC_50_INT 0xb2
-#define SQ_SRC_51_INT 0xb3
-#define SQ_SRC_52_INT 0xb4
-#define SQ_SRC_53_INT 0xb5
-#define SQ_SRC_54_INT 0xb6
-#define SQ_SRC_55_INT 0xb7
-#define SQ_SRC_56_INT 0xb8
-#define SQ_SRC_57_INT 0xb9
-#define SQ_SRC_58_INT 0xba
-#define SQ_SRC_59_INT 0xbb
-#define SQ_SRC_60_INT 0xbc
-#define SQ_SRC_61_INT 0xbd
-#define SQ_SRC_62_INT 0xbe
-#define SQ_SRC_63_INT 0xbf
-#define SQ_DS_ADD_U32 0x0
-#define SQ_DS_SUB_U32 0x1
-#define SQ_DS_RSUB_U32 0x2
-#define SQ_DS_INC_U32 0x3
-#define SQ_DS_DEC_U32 0x4
-#define SQ_DS_MIN_I32 0x5
-#define SQ_DS_MAX_I32 0x6
-#define SQ_DS_MIN_U32 0x7
-#define SQ_DS_MAX_U32 0x8
-#define SQ_DS_AND_B32 0x9
-#define SQ_DS_OR_B32 0xa
-#define SQ_DS_XOR_B32 0xb
-#define SQ_DS_MSKOR_B32 0xc
-#define SQ_DS_WRITE_B32 0xd
-#define SQ_DS_WRITE2_B32 0xe
-#define SQ_DS_WRITE2ST64_B32 0xf
-#define SQ_DS_CMPST_B32 0x10
-#define SQ_DS_CMPST_F32 0x11
-#define SQ_DS_MIN_F32 0x12
-#define SQ_DS_MAX_F32 0x13
-#define SQ_DS_NOP 0x14
-#define SQ_DS_ADD_F32 0x15
-#define SQ_DS_WRITE_B8 0x1e
-#define SQ_DS_WRITE_B16 0x1f
-#define SQ_DS_ADD_RTN_U32 0x20
-#define SQ_DS_SUB_RTN_U32 0x21
-#define SQ_DS_RSUB_RTN_U32 0x22
-#define SQ_DS_INC_RTN_U32 0x23
-#define SQ_DS_DEC_RTN_U32 0x24
-#define SQ_DS_MIN_RTN_I32 0x25
-#define SQ_DS_MAX_RTN_I32 0x26
-#define SQ_DS_MIN_RTN_U32 0x27
-#define SQ_DS_MAX_RTN_U32 0x28
-#define SQ_DS_AND_RTN_B32 0x29
-#define SQ_DS_OR_RTN_B32 0x2a
-#define SQ_DS_XOR_RTN_B32 0x2b
-#define SQ_DS_MSKOR_RTN_B32 0x2c
-#define SQ_DS_WRXCHG_RTN_B32 0x2d
-#define SQ_DS_WRXCHG2_RTN_B32 0x2e
-#define SQ_DS_WRXCHG2ST64_RTN_B32 0x2f
-#define SQ_DS_CMPST_RTN_B32 0x30
-#define SQ_DS_CMPST_RTN_F32 0x31
-#define SQ_DS_MIN_RTN_F32 0x32
-#define SQ_DS_MAX_RTN_F32 0x33
-#define SQ_DS_WRAP_RTN_B32 0x34
-#define SQ_DS_ADD_RTN_F32 0x35
-#define SQ_DS_READ_B32 0x36
-#define SQ_DS_READ2_B32 0x37
-#define SQ_DS_READ2ST64_B32 0x38
-#define SQ_DS_READ_I8 0x39
-#define SQ_DS_READ_U8 0x3a
-#define SQ_DS_READ_I16 0x3b
-#define SQ_DS_READ_U16 0x3c
-#define SQ_DS_SWIZZLE_B32 0x3d
-#define SQ_DS_PERMUTE_B32 0x3e
-#define SQ_DS_BPERMUTE_B32 0x3f
-#define SQ_DS_ADD_U64 0x40
-#define SQ_DS_SUB_U64 0x41
-#define SQ_DS_RSUB_U64 0x42
-#define SQ_DS_INC_U64 0x43
-#define SQ_DS_DEC_U64 0x44
-#define SQ_DS_MIN_I64 0x45
-#define SQ_DS_MAX_I64 0x46
-#define SQ_DS_MIN_U64 0x47
-#define SQ_DS_MAX_U64 0x48
-#define SQ_DS_AND_B64 0x49
-#define SQ_DS_OR_B64 0x4a
-#define SQ_DS_XOR_B64 0x4b
-#define SQ_DS_MSKOR_B64 0x4c
-#define SQ_DS_WRITE_B64 0x4d
-#define SQ_DS_WRITE2_B64 0x4e
-#define SQ_DS_WRITE2ST64_B64 0x4f
-#define SQ_DS_CMPST_B64 0x50
-#define SQ_DS_CMPST_F64 0x51
-#define SQ_DS_MIN_F64 0x52
-#define SQ_DS_MAX_F64 0x53
-#define SQ_DS_ADD_RTN_U64 0x60
-#define SQ_DS_SUB_RTN_U64 0x61
-#define SQ_DS_RSUB_RTN_U64 0x62
-#define SQ_DS_INC_RTN_U64 0x63
-#define SQ_DS_DEC_RTN_U64 0x64
-#define SQ_DS_MIN_RTN_I64 0x65
-#define SQ_DS_MAX_RTN_I64 0x66
-#define SQ_DS_MIN_RTN_U64 0x67
-#define SQ_DS_MAX_RTN_U64 0x68
-#define SQ_DS_AND_RTN_B64 0x69
-#define SQ_DS_OR_RTN_B64 0x6a
-#define SQ_DS_XOR_RTN_B64 0x6b
-#define SQ_DS_MSKOR_RTN_B64 0x6c
-#define SQ_DS_WRXCHG_RTN_B64 0x6d
-#define SQ_DS_WRXCHG2_RTN_B64 0x6e
-#define SQ_DS_WRXCHG2ST64_RTN_B64 0x6f
-#define SQ_DS_CMPST_RTN_B64 0x70
-#define SQ_DS_CMPST_RTN_F64 0x71
-#define SQ_DS_MIN_RTN_F64 0x72
-#define SQ_DS_MAX_RTN_F64 0x73
-#define SQ_DS_READ_B64 0x76
-#define SQ_DS_READ2_B64 0x77
-#define SQ_DS_READ2ST64_B64 0x78
-#define SQ_DS_CONDXCHG32_RTN_B64 0x7e
-#define SQ_DS_ADD_SRC2_U32 0x80
-#define SQ_DS_SUB_SRC2_U32 0x81
-#define SQ_DS_RSUB_SRC2_U32 0x82
-#define SQ_DS_INC_SRC2_U32 0x83
-#define SQ_DS_DEC_SRC2_U32 0x84
-#define SQ_DS_MIN_SRC2_I32 0x85
-#define SQ_DS_MAX_SRC2_I32 0x86
-#define SQ_DS_MIN_SRC2_U32 0x87
-#define SQ_DS_MAX_SRC2_U32 0x88
-#define SQ_DS_AND_SRC2_B32 0x89
-#define SQ_DS_OR_SRC2_B32 0x8a
-#define SQ_DS_XOR_SRC2_B32 0x8b
-#define SQ_DS_WRITE_SRC2_B32 0x8d
-#define SQ_DS_MIN_SRC2_F32 0x92
-#define SQ_DS_MAX_SRC2_F32 0x93
-#define SQ_DS_ADD_SRC2_F32 0x95
-#define SQ_DS_GWS_SEMA_RELEASE_ALL 0x98
-#define SQ_DS_GWS_INIT 0x99
-#define SQ_DS_GWS_SEMA_V 0x9a
-#define SQ_DS_GWS_SEMA_BR 0x9b
-#define SQ_DS_GWS_SEMA_P 0x9c
-#define SQ_DS_GWS_BARRIER 0x9d
-#define SQ_DS_CONSUME 0xbd
-#define SQ_DS_APPEND 0xbe
-#define SQ_DS_ORDERED_COUNT 0xbf
-#define SQ_DS_ADD_SRC2_U64 0xc0
-#define SQ_DS_SUB_SRC2_U64 0xc1
-#define SQ_DS_RSUB_SRC2_U64 0xc2
-#define SQ_DS_INC_SRC2_U64 0xc3
-#define SQ_DS_DEC_SRC2_U64 0xc4
-#define SQ_DS_MIN_SRC2_I64 0xc5
-#define SQ_DS_MAX_SRC2_I64 0xc6
-#define SQ_DS_MIN_SRC2_U64 0xc7
-#define SQ_DS_MAX_SRC2_U64 0xc8
-#define SQ_DS_AND_SRC2_B64 0xc9
-#define SQ_DS_OR_SRC2_B64 0xca
-#define SQ_DS_XOR_SRC2_B64 0xcb
-#define SQ_DS_WRITE_SRC2_B64 0xcd
-#define SQ_DS_MIN_SRC2_F64 0xd2
-#define SQ_DS_MAX_SRC2_F64 0xd3
-#define SQ_DS_WRITE_B96 0xde
-#define SQ_DS_WRITE_B128 0xdf
-#define SQ_DS_CONDXCHG32_RTN_B128 0xfd
-#define SQ_DS_READ_B96 0xfe
-#define SQ_DS_READ_B128 0xff
-#define SQ_BUFFER_LOAD_FORMAT_X 0x0
-#define SQ_BUFFER_LOAD_FORMAT_XY 0x1
-#define SQ_BUFFER_LOAD_FORMAT_XYZ 0x2
-#define SQ_BUFFER_LOAD_FORMAT_XYZW 0x3
-#define SQ_BUFFER_STORE_FORMAT_X 0x4
-#define SQ_BUFFER_STORE_FORMAT_XY 0x5
-#define SQ_BUFFER_STORE_FORMAT_XYZ 0x6
-#define SQ_BUFFER_STORE_FORMAT_XYZW 0x7
-#define SQ_BUFFER_LOAD_FORMAT_D16_X 0x8
-#define SQ_BUFFER_LOAD_FORMAT_D16_XY 0x9
-#define SQ_BUFFER_LOAD_FORMAT_D16_XYZ 0xa
-#define SQ_BUFFER_LOAD_FORMAT_D16_XYZW 0xb
-#define SQ_BUFFER_STORE_FORMAT_D16_X 0xc
-#define SQ_BUFFER_STORE_FORMAT_D16_XY 0xd
-#define SQ_BUFFER_STORE_FORMAT_D16_XYZ 0xe
-#define SQ_BUFFER_STORE_FORMAT_D16_XYZW 0xf
-#define SQ_BUFFER_LOAD_UBYTE 0x10
-#define SQ_BUFFER_LOAD_SBYTE 0x11
-#define SQ_BUFFER_LOAD_USHORT 0x12
-#define SQ_BUFFER_LOAD_SSHORT 0x13
-#define SQ_BUFFER_LOAD_DWORD 0x14
-#define SQ_BUFFER_LOAD_DWORDX2 0x15
-#define SQ_BUFFER_LOAD_DWORDX3 0x16
-#define SQ_BUFFER_LOAD_DWORDX4 0x17
-#define SQ_BUFFER_STORE_BYTE 0x18
-#define SQ_BUFFER_STORE_SHORT 0x1a
-#define SQ_BUFFER_STORE_DWORD 0x1c
-#define SQ_BUFFER_STORE_DWORDX2 0x1d
-#define SQ_BUFFER_STORE_DWORDX3 0x1e
-#define SQ_BUFFER_STORE_DWORDX4 0x1f
-#define SQ_BUFFER_STORE_LDS_DWORD 0x3d
-#define SQ_BUFFER_WBINVL1 0x3e
-#define SQ_BUFFER_WBINVL1_VOL 0x3f
-#define SQ_BUFFER_ATOMIC_SWAP 0x40
-#define SQ_BUFFER_ATOMIC_CMPSWAP 0x41
-#define SQ_BUFFER_ATOMIC_ADD 0x42
-#define SQ_BUFFER_ATOMIC_SUB 0x43
-#define SQ_BUFFER_ATOMIC_SMIN 0x44
-#define SQ_BUFFER_ATOMIC_UMIN 0x45
-#define SQ_BUFFER_ATOMIC_SMAX 0x46
-#define SQ_BUFFER_ATOMIC_UMAX 0x47
-#define SQ_BUFFER_ATOMIC_AND 0x48
-#define SQ_BUFFER_ATOMIC_OR 0x49
-#define SQ_BUFFER_ATOMIC_XOR 0x4a
-#define SQ_BUFFER_ATOMIC_INC 0x4b
-#define SQ_BUFFER_ATOMIC_DEC 0x4c
-#define SQ_BUFFER_ATOMIC_SWAP_X2 0x60
-#define SQ_BUFFER_ATOMIC_CMPSWAP_X2 0x61
-#define SQ_BUFFER_ATOMIC_ADD_X2 0x62
-#define SQ_BUFFER_ATOMIC_SUB_X2 0x63
-#define SQ_BUFFER_ATOMIC_SMIN_X2 0x64
-#define SQ_BUFFER_ATOMIC_UMIN_X2 0x65
-#define SQ_BUFFER_ATOMIC_SMAX_X2 0x66
-#define SQ_BUFFER_ATOMIC_UMAX_X2 0x67
-#define SQ_BUFFER_ATOMIC_AND_X2 0x68
-#define SQ_BUFFER_ATOMIC_OR_X2 0x69
-#define SQ_BUFFER_ATOMIC_XOR_X2 0x6a
-#define SQ_BUFFER_ATOMIC_INC_X2 0x6b
-#define SQ_BUFFER_ATOMIC_DEC_X2 0x6c
-#define SQ_EXEC_LO 0x7e
-#define SQ_EXEC_HI 0x7f
-#define SQ_SRC_SCC 0xfd
-#define SQ_OMOD_OFF 0x0
-#define SQ_OMOD_M2 0x1
-#define SQ_OMOD_M4 0x2
-#define SQ_OMOD_D2 0x3
-#define SQ_DPP_QUAD_PERM 0x0
-#define SQ_DPP_ROW_SL1 0x101
-#define SQ_DPP_ROW_SL2 0x102
-#define SQ_DPP_ROW_SL3 0x103
-#define SQ_DPP_ROW_SL4 0x104
-#define SQ_DPP_ROW_SL5 0x105
-#define SQ_DPP_ROW_SL6 0x106
-#define SQ_DPP_ROW_SL7 0x107
-#define SQ_DPP_ROW_SL8 0x108
-#define SQ_DPP_ROW_SL9 0x109
-#define SQ_DPP_ROW_SL10 0x10a
-#define SQ_DPP_ROW_SL11 0x10b
-#define SQ_DPP_ROW_SL12 0x10c
-#define SQ_DPP_ROW_SL13 0x10d
-#define SQ_DPP_ROW_SL14 0x10e
-#define SQ_DPP_ROW_SL15 0x10f
-#define SQ_DPP_ROW_SR1 0x111
-#define SQ_DPP_ROW_SR2 0x112
-#define SQ_DPP_ROW_SR3 0x113
-#define SQ_DPP_ROW_SR4 0x114
-#define SQ_DPP_ROW_SR5 0x115
-#define SQ_DPP_ROW_SR6 0x116
-#define SQ_DPP_ROW_SR7 0x117
-#define SQ_DPP_ROW_SR8 0x118
-#define SQ_DPP_ROW_SR9 0x119
-#define SQ_DPP_ROW_SR10 0x11a
-#define SQ_DPP_ROW_SR11 0x11b
-#define SQ_DPP_ROW_SR12 0x11c
-#define SQ_DPP_ROW_SR13 0x11d
-#define SQ_DPP_ROW_SR14 0x11e
-#define SQ_DPP_ROW_SR15 0x11f
-#define SQ_DPP_ROW_RR1 0x121
-#define SQ_DPP_ROW_RR2 0x122
-#define SQ_DPP_ROW_RR3 0x123
-#define SQ_DPP_ROW_RR4 0x124
-#define SQ_DPP_ROW_RR5 0x125
-#define SQ_DPP_ROW_RR6 0x126
-#define SQ_DPP_ROW_RR7 0x127
-#define SQ_DPP_ROW_RR8 0x128
-#define SQ_DPP_ROW_RR9 0x129
-#define SQ_DPP_ROW_RR10 0x12a
-#define SQ_DPP_ROW_RR11 0x12b
-#define SQ_DPP_ROW_RR12 0x12c
-#define SQ_DPP_ROW_RR13 0x12d
-#define SQ_DPP_ROW_RR14 0x12e
-#define SQ_DPP_ROW_RR15 0x12f
-#define SQ_DPP_WF_SL1 0x130
-#define SQ_DPP_WF_RL1 0x134
-#define SQ_DPP_WF_SR1 0x138
-#define SQ_DPP_WF_RR1 0x13c
-#define SQ_DPP_ROW_MIRROR 0x140
-#define SQ_DPP_ROW_HALF_MIRROR 0x141
-#define SQ_DPP_ROW_BCAST15 0x142
-#define SQ_DPP_ROW_BCAST31 0x143
-#define SQ_EXP_GDS0 0x18
-#define SQ_GS_OP_NOP 0x0
-#define SQ_GS_OP_CUT 0x1
-#define SQ_GS_OP_EMIT 0x2
-#define SQ_GS_OP_EMIT_CUT 0x3
-#define SQ_IMAGE_LOAD 0x0
-#define SQ_IMAGE_LOAD_MIP 0x1
-#define SQ_IMAGE_LOAD_PCK 0x2
-#define SQ_IMAGE_LOAD_PCK_SGN 0x3
-#define SQ_IMAGE_LOAD_MIP_PCK 0x4
-#define SQ_IMAGE_LOAD_MIP_PCK_SGN 0x5
-#define SQ_IMAGE_STORE 0x8
-#define SQ_IMAGE_STORE_MIP 0x9
-#define SQ_IMAGE_STORE_PCK 0xa
-#define SQ_IMAGE_STORE_MIP_PCK 0xb
-#define SQ_IMAGE_GET_RESINFO 0xe
-#define SQ_IMAGE_ATOMIC_SWAP 0x10
-#define SQ_IMAGE_ATOMIC_CMPSWAP 0x11
-#define SQ_IMAGE_ATOMIC_ADD 0x12
-#define SQ_IMAGE_ATOMIC_SUB 0x13
-#define SQ_IMAGE_ATOMIC_SMIN 0x14
-#define SQ_IMAGE_ATOMIC_UMIN 0x15
-#define SQ_IMAGE_ATOMIC_SMAX 0x16
-#define SQ_IMAGE_ATOMIC_UMAX 0x17
-#define SQ_IMAGE_ATOMIC_AND 0x18
-#define SQ_IMAGE_ATOMIC_OR 0x19
-#define SQ_IMAGE_ATOMIC_XOR 0x1a
-#define SQ_IMAGE_ATOMIC_INC 0x1b
-#define SQ_IMAGE_ATOMIC_DEC 0x1c
-#define SQ_IMAGE_SAMPLE 0x20
-#define SQ_IMAGE_SAMPLE_CL 0x21
-#define SQ_IMAGE_SAMPLE_D 0x22
-#define SQ_IMAGE_SAMPLE_D_CL 0x23
-#define SQ_IMAGE_SAMPLE_L 0x24
-#define SQ_IMAGE_SAMPLE_B 0x25
-#define SQ_IMAGE_SAMPLE_B_CL 0x26
-#define SQ_IMAGE_SAMPLE_LZ 0x27
-#define SQ_IMAGE_SAMPLE_C 0x28
-#define SQ_IMAGE_SAMPLE_C_CL 0x29
-#define SQ_IMAGE_SAMPLE_C_D 0x2a
-#define SQ_IMAGE_SAMPLE_C_D_CL 0x2b
-#define SQ_IMAGE_SAMPLE_C_L 0x2c
-#define SQ_IMAGE_SAMPLE_C_B 0x2d
-#define SQ_IMAGE_SAMPLE_C_B_CL 0x2e
-#define SQ_IMAGE_SAMPLE_C_LZ 0x2f
-#define SQ_IMAGE_SAMPLE_O 0x30
-#define SQ_IMAGE_SAMPLE_CL_O 0x31
-#define SQ_IMAGE_SAMPLE_D_O 0x32
-#define SQ_IMAGE_SAMPLE_D_CL_O 0x33
-#define SQ_IMAGE_SAMPLE_L_O 0x34
-#define SQ_IMAGE_SAMPLE_B_O 0x35
-#define SQ_IMAGE_SAMPLE_B_CL_O 0x36
-#define SQ_IMAGE_SAMPLE_LZ_O 0x37
-#define SQ_IMAGE_SAMPLE_C_O 0x38
-#define SQ_IMAGE_SAMPLE_C_CL_O 0x39
-#define SQ_IMAGE_SAMPLE_C_D_O 0x3a
-#define SQ_IMAGE_SAMPLE_C_D_CL_O 0x3b
-#define SQ_IMAGE_SAMPLE_C_L_O 0x3c
-#define SQ_IMAGE_SAMPLE_C_B_O 0x3d
-#define SQ_IMAGE_SAMPLE_C_B_CL_O 0x3e
-#define SQ_IMAGE_SAMPLE_C_LZ_O 0x3f
-#define SQ_IMAGE_GATHER4 0x40
-#define SQ_IMAGE_GATHER4_CL 0x41
-#define SQ_IMAGE_GATHER4_L 0x44
-#define SQ_IMAGE_GATHER4_B 0x45
-#define SQ_IMAGE_GATHER4_B_CL 0x46
-#define SQ_IMAGE_GATHER4_LZ 0x47
-#define SQ_IMAGE_GATHER4_C 0x48
-#define SQ_IMAGE_GATHER4_C_CL 0x49
-#define SQ_IMAGE_GATHER4_C_L 0x4c
-#define SQ_IMAGE_GATHER4_C_B 0x4d
-#define SQ_IMAGE_GATHER4_C_B_CL 0x4e
-#define SQ_IMAGE_GATHER4_C_LZ 0x4f
-#define SQ_IMAGE_GATHER4_O 0x50
-#define SQ_IMAGE_GATHER4_CL_O 0x51
-#define SQ_IMAGE_GATHER4_L_O 0x54
-#define SQ_IMAGE_GATHER4_B_O 0x55
-#define SQ_IMAGE_GATHER4_B_CL_O 0x56
-#define SQ_IMAGE_GATHER4_LZ_O 0x57
-#define SQ_IMAGE_GATHER4_C_O 0x58
-#define SQ_IMAGE_GATHER4_C_CL_O 0x59
-#define SQ_IMAGE_GATHER4_C_L_O 0x5c
-#define SQ_IMAGE_GATHER4_C_B_O 0x5d
-#define SQ_IMAGE_GATHER4_C_B_CL_O 0x5e
-#define SQ_IMAGE_GATHER4_C_LZ_O 0x5f
-#define SQ_IMAGE_GET_LOD 0x60
-#define SQ_IMAGE_SAMPLE_CD 0x68
-#define SQ_IMAGE_SAMPLE_CD_CL 0x69
-#define SQ_IMAGE_SAMPLE_C_CD 0x6a
-#define SQ_IMAGE_SAMPLE_C_CD_CL 0x6b
-#define SQ_IMAGE_SAMPLE_CD_O 0x6c
-#define SQ_IMAGE_SAMPLE_CD_CL_O 0x6d
-#define SQ_IMAGE_SAMPLE_C_CD_O 0x6e
-#define SQ_IMAGE_SAMPLE_C_CD_CL_O 0x6f
-#define SQ_IMAGE_RSRC256 0x7e
-#define SQ_IMAGE_SAMPLER 0x7f
-#define SQ_SRC_VCCZ 0xfb
-#define SQ_SRC_VGPR0 0x100
-#define SQ_SDWA_BYTE_0 0x0
-#define SQ_SDWA_BYTE_1 0x1
-#define SQ_SDWA_BYTE_2 0x2
-#define SQ_SDWA_BYTE_3 0x3
-#define SQ_SDWA_WORD_0 0x4
-#define SQ_SDWA_WORD_1 0x5
-#define SQ_SDWA_DWORD 0x6
-#define SQ_XNACK_MASK_LO 0x68
-#define SQ_XNACK_MASK_HI 0x69
-#define SQ_TBUFFER_LOAD_FORMAT_X 0x0
-#define SQ_TBUFFER_LOAD_FORMAT_XY 0x1
-#define SQ_TBUFFER_LOAD_FORMAT_XYZ 0x2
-#define SQ_TBUFFER_LOAD_FORMAT_XYZW 0x3
-#define SQ_TBUFFER_STORE_FORMAT_X 0x4
-#define SQ_TBUFFER_STORE_FORMAT_XY 0x5
-#define SQ_TBUFFER_STORE_FORMAT_XYZ 0x6
-#define SQ_TBUFFER_STORE_FORMAT_XYZW 0x7
-#define SQ_TBUFFER_LOAD_FORMAT_D16_X 0x8
-#define SQ_TBUFFER_LOAD_FORMAT_D16_XY 0x9
-#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZ 0xa
-#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZW 0xb
-#define SQ_TBUFFER_STORE_FORMAT_D16_X 0xc
-#define SQ_TBUFFER_STORE_FORMAT_D16_XY 0xd
-#define SQ_TBUFFER_STORE_FORMAT_D16_XYZ 0xe
-#define SQ_TBUFFER_STORE_FORMAT_D16_XYZW 0xf
-#define SQ_CHAN_X 0x0
-#define SQ_CHAN_Y 0x1
-#define SQ_CHAN_Z 0x2
-#define SQ_CHAN_W 0x3
-#define SQ_V_NOP 0x0
-#define SQ_V_MOV_B32 0x1
-#define SQ_V_READFIRSTLANE_B32 0x2
-#define SQ_V_CVT_I32_F64 0x3
-#define SQ_V_CVT_F64_I32 0x4
-#define SQ_V_CVT_F32_I32 0x5
-#define SQ_V_CVT_F32_U32 0x6
-#define SQ_V_CVT_U32_F32 0x7
-#define SQ_V_CVT_I32_F32 0x8
-#define SQ_V_MOV_FED_B32 0x9
-#define SQ_V_CVT_F16_F32 0xa
-#define SQ_V_CVT_F32_F16 0xb
-#define SQ_V_CVT_RPI_I32_F32 0xc
-#define SQ_V_CVT_FLR_I32_F32 0xd
-#define SQ_V_CVT_OFF_F32_I4 0xe
-#define SQ_V_CVT_F32_F64 0xf
-#define SQ_V_CVT_F64_F32 0x10
-#define SQ_V_CVT_F32_UBYTE0 0x11
-#define SQ_V_CVT_F32_UBYTE1 0x12
-#define SQ_V_CVT_F32_UBYTE2 0x13
-#define SQ_V_CVT_F32_UBYTE3 0x14
-#define SQ_V_CVT_U32_F64 0x15
-#define SQ_V_CVT_F64_U32 0x16
-#define SQ_V_TRUNC_F64 0x17
-#define SQ_V_CEIL_F64 0x18
-#define SQ_V_RNDNE_F64 0x19
-#define SQ_V_FLOOR_F64 0x1a
-#define SQ_V_FRACT_F32 0x1b
-#define SQ_V_TRUNC_F32 0x1c
-#define SQ_V_CEIL_F32 0x1d
-#define SQ_V_RNDNE_F32 0x1e
-#define SQ_V_FLOOR_F32 0x1f
-#define SQ_V_EXP_F32 0x20
-#define SQ_V_LOG_F32 0x21
-#define SQ_V_RCP_F32 0x22
-#define SQ_V_RCP_IFLAG_F32 0x23
-#define SQ_V_RSQ_F32 0x24
-#define SQ_V_RCP_F64 0x25
-#define SQ_V_RSQ_F64 0x26
-#define SQ_V_SQRT_F32 0x27
-#define SQ_V_SQRT_F64 0x28
-#define SQ_V_SIN_F32 0x29
-#define SQ_V_COS_F32 0x2a
-#define SQ_V_NOT_B32 0x2b
-#define SQ_V_BFREV_B32 0x2c
-#define SQ_V_FFBH_U32 0x2d
-#define SQ_V_FFBL_B32 0x2e
-#define SQ_V_FFBH_I32 0x2f
-#define SQ_V_FREXP_EXP_I32_F64 0x30
-#define SQ_V_FREXP_MANT_F64 0x31
-#define SQ_V_FRACT_F64 0x32
-#define SQ_V_FREXP_EXP_I32_F32 0x33
-#define SQ_V_FREXP_MANT_F32 0x34
-#define SQ_V_CLREXCP 0x35
-#define SQ_V_MOVRELD_B32 0x36
-#define SQ_V_MOVRELS_B32 0x37
-#define SQ_V_MOVRELSD_B32 0x38
-#define SQ_V_CVT_F16_U16 0x39
-#define SQ_V_CVT_F16_I16 0x3a
-#define SQ_V_CVT_U16_F16 0x3b
-#define SQ_V_CVT_I16_F16 0x3c
-#define SQ_V_RCP_F16 0x3d
-#define SQ_V_SQRT_F16 0x3e
-#define SQ_V_RSQ_F16 0x3f
-#define SQ_V_LOG_F16 0x40
-#define SQ_V_EXP_F16 0x41
-#define SQ_V_FREXP_MANT_F16 0x42
-#define SQ_V_FREXP_EXP_I16_F16 0x43
-#define SQ_V_FLOOR_F16 0x44
-#define SQ_V_CEIL_F16 0x45
-#define SQ_V_TRUNC_F16 0x46
-#define SQ_V_RNDNE_F16 0x47
-#define SQ_V_FRACT_F16 0x48
-#define SQ_V_SIN_F16 0x49
-#define SQ_V_COS_F16 0x4a
-#define SQ_V_EXP_LEGACY_F32 0x4b
-#define SQ_V_LOG_LEGACY_F32 0x4c
-#define SQ_V_CVT_NORM_I16_F16 0x4d
-#define SQ_V_CVT_NORM_U16_F16 0x4e
-#define SQ_SRC_SDWA 0xf9
-#define SQ_V_OPC_OFFSET 0x0
-#define SQ_V_OP2_OFFSET 0x100
-#define SQ_V_OP1_OFFSET 0x140
-#define SQ_V_INTRP_OFFSET 0x270
-#define SQ_V_INTERP_P1_F32 0x0
-#define SQ_V_INTERP_P2_F32 0x1
-#define SQ_V_INTERP_MOV_F32 0x2
-#define SQ_S_NOP 0x0
-#define SQ_S_ENDPGM 0x1
-#define SQ_S_BRANCH 0x2
-#define SQ_S_WAKEUP 0x3
-#define SQ_S_CBRANCH_SCC0 0x4
-#define SQ_S_CBRANCH_SCC1 0x5
-#define SQ_S_CBRANCH_VCCZ 0x6
-#define SQ_S_CBRANCH_VCCNZ 0x7
-#define SQ_S_CBRANCH_EXECZ 0x8
-#define SQ_S_CBRANCH_EXECNZ 0x9
-#define SQ_S_BARRIER 0xa
-#define SQ_S_SETKILL 0xb
-#define SQ_S_WAITCNT 0xc
-#define SQ_S_SETHALT 0xd
-#define SQ_S_SLEEP 0xe
-#define SQ_S_SETPRIO 0xf
-#define SQ_S_SENDMSG 0x10
-#define SQ_S_SENDMSGHALT 0x11
-#define SQ_S_TRAP 0x12
-#define SQ_S_ICACHE_INV 0x13
-#define SQ_S_INCPERFLEVEL 0x14
-#define SQ_S_DECPERFLEVEL 0x15
-#define SQ_S_TTRACEDATA 0x16
-#define SQ_S_CBRANCH_CDBGSYS 0x17
-#define SQ_S_CBRANCH_CDBGUSER 0x18
-#define SQ_S_CBRANCH_CDBGSYS_OR_USER 0x19
-#define SQ_S_CBRANCH_CDBGSYS_AND_USER 0x1a
-#define SQ_S_ENDPGM_SAVED 0x1b
-#define SQ_S_SET_GPR_IDX_OFF 0x1c
-#define SQ_S_SET_GPR_IDX_MODE 0x1d
-#define SQ_SRC_DPP 0xfa
-#define SQ_SRC_LITERAL 0xff
-#define SQ_VCC_LO 0x6a
-#define SQ_VCC_HI 0x6b
-#define SQ_PARAM_P10 0x0
-#define SQ_PARAM_P20 0x1
-#define SQ_PARAM_P0 0x2
-#define SQ_SRC_LDS_DIRECT 0xfe
-#define SQ_V_CNDMASK_B32 0x0
-#define SQ_V_ADD_F32 0x1
-#define SQ_V_SUB_F32 0x2
-#define SQ_V_SUBREV_F32 0x3
-#define SQ_V_MUL_LEGACY_F32 0x4
-#define SQ_V_MUL_F32 0x5
-#define SQ_V_MUL_I32_I24 0x6
-#define SQ_V_MUL_HI_I32_I24 0x7
-#define SQ_V_MUL_U32_U24 0x8
-#define SQ_V_MUL_HI_U32_U24 0x9
-#define SQ_V_MIN_F32 0xa
-#define SQ_V_MAX_F32 0xb
-#define SQ_V_MIN_I32 0xc
-#define SQ_V_MAX_I32 0xd
-#define SQ_V_MIN_U32 0xe
-#define SQ_V_MAX_U32 0xf
-#define SQ_V_LSHRREV_B32 0x10
-#define SQ_V_ASHRREV_I32 0x11
-#define SQ_V_LSHLREV_B32 0x12
-#define SQ_V_AND_B32 0x13
-#define SQ_V_OR_B32 0x14
-#define SQ_V_XOR_B32 0x15
-#define SQ_V_MAC_F32 0x16
-#define SQ_V_MADMK_F32 0x17
-#define SQ_V_MADAK_F32 0x18
-#define SQ_V_ADD_U32 0x19
-#define SQ_V_SUB_U32 0x1a
-#define SQ_V_SUBREV_U32 0x1b
-#define SQ_V_ADDC_U32 0x1c
-#define SQ_V_SUBB_U32 0x1d
-#define SQ_V_SUBBREV_U32 0x1e
-#define SQ_V_ADD_F16 0x1f
-#define SQ_V_SUB_F16 0x20
-#define SQ_V_SUBREV_F16 0x21
-#define SQ_V_MUL_F16 0x22
-#define SQ_V_MAC_F16 0x23
-#define SQ_V_MADMK_F16 0x24
-#define SQ_V_MADAK_F16 0x25
-#define SQ_V_ADD_U16 0x26
-#define SQ_V_SUB_U16 0x27
-#define SQ_V_SUBREV_U16 0x28
-#define SQ_V_MUL_LO_U16 0x29
-#define SQ_V_LSHLREV_B16 0x2a
-#define SQ_V_LSHRREV_B16 0x2b
-#define SQ_V_ASHRREV_I16 0x2c
-#define SQ_V_MAX_F16 0x2d
-#define SQ_V_MIN_F16 0x2e
-#define SQ_V_MAX_U16 0x2f
-#define SQ_V_MAX_I16 0x30
-#define SQ_V_MIN_U16 0x31
-#define SQ_V_MIN_I16 0x32
-#define SQ_V_LDEXP_F16 0x33
-#define SQ_FLAT_LOAD_UBYTE 0x10
-#define SQ_FLAT_LOAD_SBYTE 0x11
-#define SQ_FLAT_LOAD_USHORT 0x12
-#define SQ_FLAT_LOAD_SSHORT 0x13
-#define SQ_FLAT_LOAD_DWORD 0x14
-#define SQ_FLAT_LOAD_DWORDX2 0x15
-#define SQ_FLAT_LOAD_DWORDX3 0x16
-#define SQ_FLAT_LOAD_DWORDX4 0x17
-#define SQ_FLAT_STORE_BYTE 0x18
-#define SQ_FLAT_STORE_SHORT 0x1a
-#define SQ_FLAT_STORE_DWORD 0x1c
-#define SQ_FLAT_STORE_DWORDX2 0x1d
-#define SQ_FLAT_STORE_DWORDX3 0x1e
-#define SQ_FLAT_STORE_DWORDX4 0x1f
-#define SQ_FLAT_ATOMIC_SWAP 0x40
-#define SQ_FLAT_ATOMIC_CMPSWAP 0x41
-#define SQ_FLAT_ATOMIC_ADD 0x42
-#define SQ_FLAT_ATOMIC_SUB 0x43
-#define SQ_FLAT_ATOMIC_SMIN 0x44
-#define SQ_FLAT_ATOMIC_UMIN 0x45
-#define SQ_FLAT_ATOMIC_SMAX 0x46
-#define SQ_FLAT_ATOMIC_UMAX 0x47
-#define SQ_FLAT_ATOMIC_AND 0x48
-#define SQ_FLAT_ATOMIC_OR 0x49
-#define SQ_FLAT_ATOMIC_XOR 0x4a
-#define SQ_FLAT_ATOMIC_INC 0x4b
-#define SQ_FLAT_ATOMIC_DEC 0x4c
-#define SQ_FLAT_ATOMIC_SWAP_X2 0x60
-#define SQ_FLAT_ATOMIC_CMPSWAP_X2 0x61
-#define SQ_FLAT_ATOMIC_ADD_X2 0x62
-#define SQ_FLAT_ATOMIC_SUB_X2 0x63
-#define SQ_FLAT_ATOMIC_SMIN_X2 0x64
-#define SQ_FLAT_ATOMIC_UMIN_X2 0x65
-#define SQ_FLAT_ATOMIC_SMAX_X2 0x66
-#define SQ_FLAT_ATOMIC_UMAX_X2 0x67
-#define SQ_FLAT_ATOMIC_AND_X2 0x68
-#define SQ_FLAT_ATOMIC_OR_X2 0x69
-#define SQ_FLAT_ATOMIC_XOR_X2 0x6a
-#define SQ_FLAT_ATOMIC_INC_X2 0x6b
-#define SQ_FLAT_ATOMIC_DEC_X2 0x6c
-#define SQ_S_CMP_EQ_I32 0x0
-#define SQ_S_CMP_LG_I32 0x1
-#define SQ_S_CMP_GT_I32 0x2
-#define SQ_S_CMP_GE_I32 0x3
-#define SQ_S_CMP_LT_I32 0x4
-#define SQ_S_CMP_LE_I32 0x5
-#define SQ_S_CMP_EQ_U32 0x6
-#define SQ_S_CMP_LG_U32 0x7
-#define SQ_S_CMP_GT_U32 0x8
-#define SQ_S_CMP_GE_U32 0x9
-#define SQ_S_CMP_LT_U32 0xa
-#define SQ_S_CMP_LE_U32 0xb
-#define SQ_S_BITCMP0_B32 0xc
-#define SQ_S_BITCMP1_B32 0xd
-#define SQ_S_BITCMP0_B64 0xe
-#define SQ_S_BITCMP1_B64 0xf
-#define SQ_S_SETVSKIP 0x10
-#define SQ_S_SET_GPR_IDX_ON 0x11
-#define SQ_S_CMP_EQ_U64 0x12
-#define SQ_S_CMP_LG_U64 0x13
-#define SQ_M0 0x7c
-#define SQ_V_MAD_LEGACY_F32 0x1c0
-#define SQ_V_MAD_F32 0x1c1
-#define SQ_V_MAD_I32_I24 0x1c2
-#define SQ_V_MAD_U32_U24 0x1c3
-#define SQ_V_CUBEID_F32 0x1c4
-#define SQ_V_CUBESC_F32 0x1c5
-#define SQ_V_CUBETC_F32 0x1c6
-#define SQ_V_CUBEMA_F32 0x1c7
-#define SQ_V_BFE_U32 0x1c8
-#define SQ_V_BFE_I32 0x1c9
-#define SQ_V_BFI_B32 0x1ca
-#define SQ_V_FMA_F32 0x1cb
-#define SQ_V_FMA_F64 0x1cc
-#define SQ_V_LERP_U8 0x1cd
-#define SQ_V_ALIGNBIT_B32 0x1ce
-#define SQ_V_ALIGNBYTE_B32 0x1cf
-#define SQ_V_MIN3_F32 0x1d0
-#define SQ_V_MIN3_I32 0x1d1
-#define SQ_V_MIN3_U32 0x1d2
-#define SQ_V_MAX3_F32 0x1d3
-#define SQ_V_MAX3_I32 0x1d4
-#define SQ_V_MAX3_U32 0x1d5
-#define SQ_V_MED3_F32 0x1d6
-#define SQ_V_MED3_I32 0x1d7
-#define SQ_V_MED3_U32 0x1d8
-#define SQ_V_SAD_U8 0x1d9
-#define SQ_V_SAD_HI_U8 0x1da
-#define SQ_V_SAD_U16 0x1db
-#define SQ_V_SAD_U32 0x1dc
-#define SQ_V_CVT_PK_U8_F32 0x1dd
-#define SQ_V_DIV_FIXUP_F32 0x1de
-#define SQ_V_DIV_FIXUP_F64 0x1df
-#define SQ_V_DIV_SCALE_F32 0x1e0
-#define SQ_V_DIV_SCALE_F64 0x1e1
-#define SQ_V_DIV_FMAS_F32 0x1e2
-#define SQ_V_DIV_FMAS_F64 0x1e3
-#define SQ_V_MSAD_U8 0x1e4
-#define SQ_V_QSAD_PK_U16_U8 0x1e5
-#define SQ_V_MQSAD_PK_U16_U8 0x1e6
-#define SQ_V_MQSAD_U32_U8 0x1e7
-#define SQ_V_MAD_U64_U32 0x1e8
-#define SQ_V_MAD_I64_I32 0x1e9
-#define SQ_V_MAD_F16 0x1ea
-#define SQ_V_MAD_U16 0x1eb
-#define SQ_V_MAD_I16 0x1ec
-#define SQ_V_PERM_B32 0x1ed
-#define SQ_V_FMA_F16 0x1ee
-#define SQ_V_DIV_FIXUP_F16 0x1ef
-#define SQ_V_CVT_PKACCUM_U8_F32 0x1f0
-#define SQ_V_INTERP_P1LL_F16 0x274
-#define SQ_V_INTERP_P1LV_F16 0x275
-#define SQ_V_INTERP_P2_F16 0x276
-#define SQ_V_ADD_F64 0x280
-#define SQ_V_MUL_F64 0x281
-#define SQ_V_MIN_F64 0x282
-#define SQ_V_MAX_F64 0x283
-#define SQ_V_LDEXP_F64 0x284
-#define SQ_V_MUL_LO_U32 0x285
-#define SQ_V_MUL_HI_U32 0x286
-#define SQ_V_MUL_HI_I32 0x287
-#define SQ_V_LDEXP_F32 0x288
-#define SQ_V_READLANE_B32 0x289
-#define SQ_V_WRITELANE_B32 0x28a
-#define SQ_V_BCNT_U32_B32 0x28b
-#define SQ_V_MBCNT_LO_U32_B32 0x28c
-#define SQ_V_MBCNT_HI_U32_B32 0x28d
-#define SQ_V_MAC_LEGACY_F32 0x28e
-#define SQ_V_LSHLREV_B64 0x28f
-#define SQ_V_LSHRREV_B64 0x290
-#define SQ_V_ASHRREV_I64 0x291
-#define SQ_V_TRIG_PREOP_F64 0x292
-#define SQ_V_BFM_B32 0x293
-#define SQ_V_CVT_PKNORM_I16_F32 0x294
-#define SQ_V_CVT_PKNORM_U16_F32 0x295
-#define SQ_V_CVT_PKRTZ_F16_F32 0x296
-#define SQ_V_CVT_PK_U16_U32 0x297
-#define SQ_V_CVT_PK_I16_I32 0x298
-#define SQ_V_CVT_PKNORM_I16_F16 0x299
-#define SQ_V_CVT_PKNORM_U16_F16 0x29a
-#define SQ_VCC_ALL 0x0
-#define SQ_SRC_EXECZ 0xfc
-#define SQ_FLAT_SCRATCH_LO 0x66
-#define SQ_FLAT_SCRATCH_HI 0x67
-#define SQ_SYSMSG_OP_ECC_ERR_INTERRUPT 0x1
-#define SQ_SYSMSG_OP_REG_RD 0x2
-#define SQ_SYSMSG_OP_HOST_TRAP_ACK 0x3
-#define SQ_SYSMSG_OP_TTRACE_PC 0x4
-#define SQ_HW_REG_MODE 0x1
-#define SQ_HW_REG_STATUS 0x2
-#define SQ_HW_REG_TRAPSTS 0x3
-#define SQ_HW_REG_HW_ID 0x4
-#define SQ_HW_REG_GPR_ALLOC 0x5
-#define SQ_HW_REG_LDS_ALLOC 0x6
-#define SQ_HW_REG_IB_STS 0x7
-#define SQ_HW_REG_PC_LO 0x8
-#define SQ_HW_REG_PC_HI 0x9
-#define SQ_HW_REG_INST_DW0 0xa
-#define SQ_HW_REG_INST_DW1 0xb
-#define SQ_HW_REG_IB_DBG0 0xc
-#define SQ_HW_REG_IB_DBG1 0xd
-#define SQ_DPP_BOUND_OFF 0x0
-#define SQ_DPP_BOUND_ZERO 0x1
-#define SQ_R1 0x1
-#define SQ_R2 0x2
-#define SQ_R3 0x3
-#define SQ_R4 0x4
-#define SQ_R5 0x5
-#define SQ_R6 0x6
-#define SQ_R7 0x7
-#define SQ_R8 0x8
-#define SQ_R9 0x9
-#define SQ_R10 0xa
-#define SQ_R11 0xb
-#define SQ_R12 0xc
-#define SQ_R13 0xd
-#define SQ_R14 0xe
-#define SQ_R15 0xf
-#define SQ_S_ADD_U32 0x0
-#define SQ_S_SUB_U32 0x1
-#define SQ_S_ADD_I32 0x2
-#define SQ_S_SUB_I32 0x3
-#define SQ_S_ADDC_U32 0x4
-#define SQ_S_SUBB_U32 0x5
-#define SQ_S_MIN_I32 0x6
-#define SQ_S_MIN_U32 0x7
-#define SQ_S_MAX_I32 0x8
-#define SQ_S_MAX_U32 0x9
-#define SQ_S_CSELECT_B32 0xa
-#define SQ_S_CSELECT_B64 0xb
-#define SQ_S_AND_B32 0xc
-#define SQ_S_AND_B64 0xd
-#define SQ_S_OR_B32 0xe
-#define SQ_S_OR_B64 0xf
-#define SQ_S_XOR_B32 0x10
-#define SQ_S_XOR_B64 0x11
-#define SQ_S_ANDN2_B32 0x12
-#define SQ_S_ANDN2_B64 0x13
-#define SQ_S_ORN2_B32 0x14
-#define SQ_S_ORN2_B64 0x15
-#define SQ_S_NAND_B32 0x16
-#define SQ_S_NAND_B64 0x17
-#define SQ_S_NOR_B32 0x18
-#define SQ_S_NOR_B64 0x19
-#define SQ_S_XNOR_B32 0x1a
-#define SQ_S_XNOR_B64 0x1b
-#define SQ_S_LSHL_B32 0x1c
-#define SQ_S_LSHL_B64 0x1d
-#define SQ_S_LSHR_B32 0x1e
-#define SQ_S_LSHR_B64 0x1f
-#define SQ_S_ASHR_I32 0x20
-#define SQ_S_ASHR_I64 0x21
-#define SQ_S_BFM_B32 0x22
-#define SQ_S_BFM_B64 0x23
-#define SQ_S_MUL_I32 0x24
-#define SQ_S_BFE_U32 0x25
-#define SQ_S_BFE_I32 0x26
-#define SQ_S_BFE_U64 0x27
-#define SQ_S_BFE_I64 0x28
-#define SQ_S_CBRANCH_G_FORK 0x29
-#define SQ_S_ABSDIFF_I32 0x2a
-#define SQ_S_RFE_RESTORE_B64 0x2b
-#define SQ_MSG_INTERRUPT 0x1
-#define SQ_MSG_GS 0x2
-#define SQ_MSG_GS_DONE 0x3
-#define SQ_MSG_SAVEWAVE 0x4
-#define SQ_MSG_SYSMSG 0xf
-typedef enum SX_BLEND_OPT {
- BLEND_OPT_PRESERVE_NONE_IGNORE_ALL = 0x0,
- BLEND_OPT_PRESERVE_ALL_IGNORE_NONE = 0x1,
- BLEND_OPT_PRESERVE_C1_IGNORE_C0 = 0x2,
- BLEND_OPT_PRESERVE_C0_IGNORE_C1 = 0x3,
- BLEND_OPT_PRESERVE_A1_IGNORE_A0 = 0x4,
- BLEND_OPT_PRESERVE_A0_IGNORE_A1 = 0x5,
- BLEND_OPT_PRESERVE_NONE_IGNORE_A0 = 0x6,
- BLEND_OPT_PRESERVE_NONE_IGNORE_NONE = 0x7,
-} SX_BLEND_OPT;
-typedef enum SX_OPT_COMB_FCN {
- OPT_COMB_NONE = 0x0,
- OPT_COMB_ADD = 0x1,
- OPT_COMB_SUBTRACT = 0x2,
- OPT_COMB_MIN = 0x3,
- OPT_COMB_MAX = 0x4,
- OPT_COMB_REVSUBTRACT = 0x5,
- OPT_COMB_BLEND_DISABLED = 0x6,
- OPT_COMB_SAFE_ADD = 0x7,
-} SX_OPT_COMB_FCN;
-typedef enum SX_DOWNCONVERT_FORMAT {
- SX_RT_EXPORT_NO_CONVERSION = 0x0,
- SX_RT_EXPORT_32_R = 0x1,
- SX_RT_EXPORT_32_A = 0x2,
- SX_RT_EXPORT_10_11_11 = 0x3,
- SX_RT_EXPORT_2_10_10_10 = 0x4,
- SX_RT_EXPORT_8_8_8_8 = 0x5,
- SX_RT_EXPORT_5_6_5 = 0x6,
- SX_RT_EXPORT_1_5_5_5 = 0x7,
- SX_RT_EXPORT_4_4_4_4 = 0x8,
- SX_RT_EXPORT_16_16_GR = 0x9,
- SX_RT_EXPORT_16_16_AR = 0xa,
-} SX_DOWNCONVERT_FORMAT;
-typedef enum TEX_BORDER_COLOR_TYPE {
- TEX_BorderColor_TransparentBlack = 0x0,
- TEX_BorderColor_OpaqueBlack = 0x1,
- TEX_BorderColor_OpaqueWhite = 0x2,
- TEX_BorderColor_Register = 0x3,
-} TEX_BORDER_COLOR_TYPE;
-typedef enum TEX_CHROMA_KEY {
- TEX_ChromaKey_Disabled = 0x0,
- TEX_ChromaKey_Kill = 0x1,
- TEX_ChromaKey_Blend = 0x2,
- TEX_ChromaKey_RESERVED_3 = 0x3,
-} TEX_CHROMA_KEY;
-typedef enum TEX_CLAMP {
- TEX_Clamp_Repeat = 0x0,
- TEX_Clamp_Mirror = 0x1,
- TEX_Clamp_ClampToLast = 0x2,
- TEX_Clamp_MirrorOnceToLast = 0x3,
- TEX_Clamp_ClampHalfToBorder = 0x4,
- TEX_Clamp_MirrorOnceHalfToBorder = 0x5,
- TEX_Clamp_ClampToBorder = 0x6,
- TEX_Clamp_MirrorOnceToBorder = 0x7,
-} TEX_CLAMP;
-typedef enum TEX_COORD_TYPE {
- TEX_CoordType_Unnormalized = 0x0,
- TEX_CoordType_Normalized = 0x1,
-} TEX_COORD_TYPE;
-typedef enum TEX_DEPTH_COMPARE_FUNCTION {
- TEX_DepthCompareFunction_Never = 0x0,
- TEX_DepthCompareFunction_Less = 0x1,
- TEX_DepthCompareFunction_Equal = 0x2,
- TEX_DepthCompareFunction_LessEqual = 0x3,
- TEX_DepthCompareFunction_Greater = 0x4,
- TEX_DepthCompareFunction_NotEqual = 0x5,
- TEX_DepthCompareFunction_GreaterEqual = 0x6,
- TEX_DepthCompareFunction_Always = 0x7,
-} TEX_DEPTH_COMPARE_FUNCTION;
-typedef enum TEX_DIM {
- TEX_Dim_1D = 0x0,
- TEX_Dim_2D = 0x1,
- TEX_Dim_3D = 0x2,
- TEX_Dim_CubeMap = 0x3,
- TEX_Dim_1DArray = 0x4,
- TEX_Dim_2DArray = 0x5,
- TEX_Dim_2D_MSAA = 0x6,
- TEX_Dim_2DArray_MSAA = 0x7,
-} TEX_DIM;
-typedef enum TEX_FORMAT_COMP {
- TEX_FormatComp_Unsigned = 0x0,
- TEX_FormatComp_Signed = 0x1,
- TEX_FormatComp_UnsignedBiased = 0x2,
- TEX_FormatComp_RESERVED_3 = 0x3,
-} TEX_FORMAT_COMP;
-typedef enum TEX_MAX_ANISO_RATIO {
- TEX_MaxAnisoRatio_1to1 = 0x0,
- TEX_MaxAnisoRatio_2to1 = 0x1,
- TEX_MaxAnisoRatio_4to1 = 0x2,
- TEX_MaxAnisoRatio_8to1 = 0x3,
- TEX_MaxAnisoRatio_16to1 = 0x4,
- TEX_MaxAnisoRatio_RESERVED_5 = 0x5,
- TEX_MaxAnisoRatio_RESERVED_6 = 0x6,
- TEX_MaxAnisoRatio_RESERVED_7 = 0x7,
-} TEX_MAX_ANISO_RATIO;
-typedef enum TEX_MIP_FILTER {
- TEX_MipFilter_None = 0x0,
- TEX_MipFilter_Point = 0x1,
- TEX_MipFilter_Linear = 0x2,
- TEX_MipFilter_Point_Aniso_Adj = 0x3,
-} TEX_MIP_FILTER;
-typedef enum TEX_REQUEST_SIZE {
- TEX_RequestSize_32B = 0x0,
- TEX_RequestSize_64B = 0x1,
- TEX_RequestSize_128B = 0x2,
- TEX_RequestSize_2X64B = 0x3,
-} TEX_REQUEST_SIZE;
-typedef enum TEX_SAMPLER_TYPE {
- TEX_SamplerType_Invalid = 0x0,
- TEX_SamplerType_Valid = 0x1,
-} TEX_SAMPLER_TYPE;
-typedef enum TEX_XY_FILTER {
- TEX_XYFilter_Point = 0x0,
- TEX_XYFilter_Linear = 0x1,
- TEX_XYFilter_AnisoPoint = 0x2,
- TEX_XYFilter_AnisoLinear = 0x3,
-} TEX_XY_FILTER;
-typedef enum TEX_Z_FILTER {
- TEX_ZFilter_None = 0x0,
- TEX_ZFilter_Point = 0x1,
- TEX_ZFilter_Linear = 0x2,
- TEX_ZFilter_RESERVED_3 = 0x3,
-} TEX_Z_FILTER;
-typedef enum VTX_CLAMP {
- VTX_Clamp_ClampToZero = 0x0,
- VTX_Clamp_ClampToNAN = 0x1,
-} VTX_CLAMP;
-typedef enum VTX_FETCH_TYPE {
- VTX_FetchType_VertexData = 0x0,
- VTX_FetchType_InstanceData = 0x1,
- VTX_FetchType_NoIndexOffset = 0x2,
- VTX_FetchType_RESERVED_3 = 0x3,
-} VTX_FETCH_TYPE;
-typedef enum VTX_FORMAT_COMP_ALL {
- VTX_FormatCompAll_Unsigned = 0x0,
- VTX_FormatCompAll_Signed = 0x1,
-} VTX_FORMAT_COMP_ALL;
-typedef enum VTX_MEM_REQUEST_SIZE {
- VTX_MemRequestSize_32B = 0x0,
- VTX_MemRequestSize_64B = 0x1,
-} VTX_MEM_REQUEST_SIZE;
-typedef enum TVX_DATA_FORMAT {
- TVX_FMT_INVALID = 0x0,
- TVX_FMT_8 = 0x1,
- TVX_FMT_4_4 = 0x2,
- TVX_FMT_3_3_2 = 0x3,
- TVX_FMT_RESERVED_4 = 0x4,
- TVX_FMT_16 = 0x5,
- TVX_FMT_16_FLOAT = 0x6,
- TVX_FMT_8_8 = 0x7,
- TVX_FMT_5_6_5 = 0x8,
- TVX_FMT_6_5_5 = 0x9,
- TVX_FMT_1_5_5_5 = 0xa,
- TVX_FMT_4_4_4_4 = 0xb,
- TVX_FMT_5_5_5_1 = 0xc,
- TVX_FMT_32 = 0xd,
- TVX_FMT_32_FLOAT = 0xe,
- TVX_FMT_16_16 = 0xf,
- TVX_FMT_16_16_FLOAT = 0x10,
- TVX_FMT_8_24 = 0x11,
- TVX_FMT_8_24_FLOAT = 0x12,
- TVX_FMT_24_8 = 0x13,
- TVX_FMT_24_8_FLOAT = 0x14,
- TVX_FMT_10_11_11 = 0x15,
- TVX_FMT_10_11_11_FLOAT = 0x16,
- TVX_FMT_11_11_10 = 0x17,
- TVX_FMT_11_11_10_FLOAT = 0x18,
- TVX_FMT_2_10_10_10 = 0x19,
- TVX_FMT_8_8_8_8 = 0x1a,
- TVX_FMT_10_10_10_2 = 0x1b,
- TVX_FMT_X24_8_32_FLOAT = 0x1c,
- TVX_FMT_32_32 = 0x1d,
- TVX_FMT_32_32_FLOAT = 0x1e,
- TVX_FMT_16_16_16_16 = 0x1f,
- TVX_FMT_16_16_16_16_FLOAT = 0x20,
- TVX_FMT_RESERVED_33 = 0x21,
- TVX_FMT_32_32_32_32 = 0x22,
- TVX_FMT_32_32_32_32_FLOAT = 0x23,
- TVX_FMT_RESERVED_36 = 0x24,
- TVX_FMT_1 = 0x25,
- TVX_FMT_1_REVERSED = 0x26,
- TVX_FMT_GB_GR = 0x27,
- TVX_FMT_BG_RG = 0x28,
- TVX_FMT_32_AS_8 = 0x29,
- TVX_FMT_32_AS_8_8 = 0x2a,
- TVX_FMT_5_9_9_9_SHAREDEXP = 0x2b,
- TVX_FMT_8_8_8 = 0x2c,
- TVX_FMT_16_16_16 = 0x2d,
- TVX_FMT_16_16_16_FLOAT = 0x2e,
- TVX_FMT_32_32_32 = 0x2f,
- TVX_FMT_32_32_32_FLOAT = 0x30,
- TVX_FMT_BC1 = 0x31,
- TVX_FMT_BC2 = 0x32,
- TVX_FMT_BC3 = 0x33,
- TVX_FMT_BC4 = 0x34,
- TVX_FMT_BC5 = 0x35,
- TVX_FMT_APC0 = 0x36,
- TVX_FMT_APC1 = 0x37,
- TVX_FMT_APC2 = 0x38,
- TVX_FMT_APC3 = 0x39,
- TVX_FMT_APC4 = 0x3a,
- TVX_FMT_APC5 = 0x3b,
- TVX_FMT_APC6 = 0x3c,
- TVX_FMT_APC7 = 0x3d,
- TVX_FMT_CTX1 = 0x3e,
- TVX_FMT_RESERVED_63 = 0x3f,
-} TVX_DATA_FORMAT;
-typedef enum TVX_DST_SEL {
- TVX_DstSel_X = 0x0,
- TVX_DstSel_Y = 0x1,
- TVX_DstSel_Z = 0x2,
- TVX_DstSel_W = 0x3,
- TVX_DstSel_0f = 0x4,
- TVX_DstSel_1f = 0x5,
- TVX_DstSel_RESERVED_6 = 0x6,
- TVX_DstSel_Mask = 0x7,
-} TVX_DST_SEL;
-typedef enum TVX_ENDIAN_SWAP {
- TVX_EndianSwap_None = 0x0,
- TVX_EndianSwap_8in16 = 0x1,
- TVX_EndianSwap_8in32 = 0x2,
- TVX_EndianSwap_8in64 = 0x3,
-} TVX_ENDIAN_SWAP;
-typedef enum TVX_INST {
- TVX_Inst_NormalVertexFetch = 0x0,
- TVX_Inst_SemanticVertexFetch = 0x1,
- TVX_Inst_RESERVED_2 = 0x2,
- TVX_Inst_LD = 0x3,
- TVX_Inst_GetTextureResInfo = 0x4,
- TVX_Inst_GetNumberOfSamples = 0x5,
- TVX_Inst_GetLOD = 0x6,
- TVX_Inst_GetGradientsH = 0x7,
- TVX_Inst_GetGradientsV = 0x8,
- TVX_Inst_SetTextureOffsets = 0x9,
- TVX_Inst_KeepGradients = 0xa,
- TVX_Inst_SetGradientsH = 0xb,
- TVX_Inst_SetGradientsV = 0xc,
- TVX_Inst_Pass = 0xd,
- TVX_Inst_GetBufferResInfo = 0xe,
- TVX_Inst_RESERVED_15 = 0xf,
- TVX_Inst_Sample = 0x10,
- TVX_Inst_Sample_L = 0x11,
- TVX_Inst_Sample_LB = 0x12,
- TVX_Inst_Sample_LZ = 0x13,
- TVX_Inst_Sample_G = 0x14,
- TVX_Inst_Gather4 = 0x15,
- TVX_Inst_Sample_G_LB = 0x16,
- TVX_Inst_Gather4_O = 0x17,
- TVX_Inst_Sample_C = 0x18,
- TVX_Inst_Sample_C_L = 0x19,
- TVX_Inst_Sample_C_LB = 0x1a,
- TVX_Inst_Sample_C_LZ = 0x1b,
- TVX_Inst_Sample_C_G = 0x1c,
- TVX_Inst_Gather4_C = 0x1d,
- TVX_Inst_Sample_C_G_LB = 0x1e,
- TVX_Inst_Gather4_C_O = 0x1f,
-} TVX_INST;
-typedef enum TVX_NUM_FORMAT_ALL {
- TVX_NumFormatAll_Norm = 0x0,
- TVX_NumFormatAll_Int = 0x1,
- TVX_NumFormatAll_Scaled = 0x2,
- TVX_NumFormatAll_RESERVED_3 = 0x3,
-} TVX_NUM_FORMAT_ALL;
-typedef enum TVX_SRC_SEL {
- TVX_SrcSel_X = 0x0,
- TVX_SrcSel_Y = 0x1,
- TVX_SrcSel_Z = 0x2,
- TVX_SrcSel_W = 0x3,
- TVX_SrcSel_0f = 0x4,
- TVX_SrcSel_1f = 0x5,
-} TVX_SRC_SEL;
-typedef enum TVX_SRF_MODE_ALL {
- TVX_SRFModeAll_ZCMO = 0x0,
- TVX_SRFModeAll_NZ = 0x1,
-} TVX_SRF_MODE_ALL;
-typedef enum TVX_TYPE {
- TVX_Type_InvalidTextureResource = 0x0,
- TVX_Type_InvalidVertexBuffer = 0x1,
- TVX_Type_ValidTextureResource = 0x2,
- TVX_Type_ValidVertexBuffer = 0x3,
-} TVX_TYPE;
-typedef enum TC_OP_MASKS {
- TC_OP_MASK_FLUSH_DENROM = 0x8,
- TC_OP_MASK_64 = 0x20,
- TC_OP_MASK_NO_RTN = 0x40,
-} TC_OP_MASKS;
-typedef enum TC_OP {
- TC_OP_READ = 0x0,
- TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 0x1,
- TC_OP_ATOMIC_FMIN_RTN_32 = 0x2,
- TC_OP_ATOMIC_FMAX_RTN_32 = 0x3,
- TC_OP_RESERVED_FOP_RTN_32_0 = 0x4,
- TC_OP_RESERVED_FOP_RTN_32_1 = 0x5,
- TC_OP_RESERVED_FOP_RTN_32_2 = 0x6,
- TC_OP_ATOMIC_SWAP_RTN_32 = 0x7,
- TC_OP_ATOMIC_CMPSWAP_RTN_32 = 0x8,
- TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x9,
- TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 0xa,
- TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 0xb,
- TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_0 = 0xc,
- TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1 = 0xd,
- TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0xe,
- TC_OP_ATOMIC_ADD_RTN_32 = 0xf,
- TC_OP_ATOMIC_SUB_RTN_32 = 0x10,
- TC_OP_ATOMIC_SMIN_RTN_32 = 0x11,
- TC_OP_ATOMIC_UMIN_RTN_32 = 0x12,
- TC_OP_ATOMIC_SMAX_RTN_32 = 0x13,
- TC_OP_ATOMIC_UMAX_RTN_32 = 0x14,
- TC_OP_ATOMIC_AND_RTN_32 = 0x15,
- TC_OP_ATOMIC_OR_RTN_32 = 0x16,
- TC_OP_ATOMIC_XOR_RTN_32 = 0x17,
- TC_OP_ATOMIC_INC_RTN_32 = 0x18,
- TC_OP_ATOMIC_DEC_RTN_32 = 0x19,
- TC_OP_WBINVL1_VOL = 0x1a,
- TC_OP_WBINVL1_SD = 0x1b,
- TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 0x1c,
- TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 0x1d,
- TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 0x1e,
- TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 0x1f,
- TC_OP_WRITE = 0x20,
- TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 0x21,
- TC_OP_ATOMIC_FMIN_RTN_64 = 0x22,
- TC_OP_ATOMIC_FMAX_RTN_64 = 0x23,
- TC_OP_RESERVED_FOP_RTN_64_0 = 0x24,
- TC_OP_RESERVED_FOP_RTN_64_1 = 0x25,
- TC_OP_RESERVED_FOP_RTN_64_2 = 0x26,
- TC_OP_ATOMIC_SWAP_RTN_64 = 0x27,
- TC_OP_ATOMIC_CMPSWAP_RTN_64 = 0x28,
- TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x29,
- TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 0x2a,
- TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 0x2b,
- TC_OP_WBINVL2_SD = 0x2c,
- TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 0x2d,
- TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 0x2e,
- TC_OP_ATOMIC_ADD_RTN_64 = 0x2f,
- TC_OP_ATOMIC_SUB_RTN_64 = 0x30,
- TC_OP_ATOMIC_SMIN_RTN_64 = 0x31,
- TC_OP_ATOMIC_UMIN_RTN_64 = 0x32,
- TC_OP_ATOMIC_SMAX_RTN_64 = 0x33,
- TC_OP_ATOMIC_UMAX_RTN_64 = 0x34,
- TC_OP_ATOMIC_AND_RTN_64 = 0x35,
- TC_OP_ATOMIC_OR_RTN_64 = 0x36,
- TC_OP_ATOMIC_XOR_RTN_64 = 0x37,
- TC_OP_ATOMIC_INC_RTN_64 = 0x38,
- TC_OP_ATOMIC_DEC_RTN_64 = 0x39,
- TC_OP_WBL2_NC = 0x3a,
- TC_OP_RESERVED_NON_FLOAT_RTN_64_0 = 0x3b,
- TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 0x3c,
- TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 0x3d,
- TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 0x3e,
- TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 0x3f,
- TC_OP_WBINVL1 = 0x40,
- TC_OP_ATOMIC_FCMPSWAP_32 = 0x41,
- TC_OP_ATOMIC_FMIN_32 = 0x42,
- TC_OP_ATOMIC_FMAX_32 = 0x43,
- TC_OP_RESERVED_FOP_32_0 = 0x44,
- TC_OP_RESERVED_FOP_32_1 = 0x45,
- TC_OP_RESERVED_FOP_32_2 = 0x46,
- TC_OP_ATOMIC_SWAP_32 = 0x47,
- TC_OP_ATOMIC_CMPSWAP_32 = 0x48,
- TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 0x49,
- TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 0x4a,
- TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 0x4b,
- TC_OP_RESERVED_FOP_FLUSH_DENORM_32_0 = 0x4c,
- TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1 = 0x4d,
- TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 0x4e,
- TC_OP_ATOMIC_ADD_32 = 0x4f,
- TC_OP_ATOMIC_SUB_32 = 0x50,
- TC_OP_ATOMIC_SMIN_32 = 0x51,
- TC_OP_ATOMIC_UMIN_32 = 0x52,
- TC_OP_ATOMIC_SMAX_32 = 0x53,
- TC_OP_ATOMIC_UMAX_32 = 0x54,
- TC_OP_ATOMIC_AND_32 = 0x55,
- TC_OP_ATOMIC_OR_32 = 0x56,
- TC_OP_ATOMIC_XOR_32 = 0x57,
- TC_OP_ATOMIC_INC_32 = 0x58,
- TC_OP_ATOMIC_DEC_32 = 0x59,
- TC_OP_INVL2_NC = 0x5a,
- TC_OP_RESERVED_NON_FLOAT_32_0 = 0x5b,
- TC_OP_RESERVED_NON_FLOAT_32_1 = 0x5c,
- TC_OP_RESERVED_NON_FLOAT_32_2 = 0x5d,
- TC_OP_RESERVED_NON_FLOAT_32_3 = 0x5e,
- TC_OP_RESERVED_NON_FLOAT_32_4 = 0x5f,
- TC_OP_WBINVL2 = 0x60,
- TC_OP_ATOMIC_FCMPSWAP_64 = 0x61,
- TC_OP_ATOMIC_FMIN_64 = 0x62,
- TC_OP_ATOMIC_FMAX_64 = 0x63,
- TC_OP_RESERVED_FOP_64_0 = 0x64,
- TC_OP_RESERVED_FOP_64_1 = 0x65,
- TC_OP_RESERVED_FOP_64_2 = 0x66,
- TC_OP_ATOMIC_SWAP_64 = 0x67,
- TC_OP_ATOMIC_CMPSWAP_64 = 0x68,
- TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 0x69,
- TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 0x6a,
- TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 0x6b,
- TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 0x6c,
- TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 0x6d,
- TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 0x6e,
- TC_OP_ATOMIC_ADD_64 = 0x6f,
- TC_OP_ATOMIC_SUB_64 = 0x70,
- TC_OP_ATOMIC_SMIN_64 = 0x71,
- TC_OP_ATOMIC_UMIN_64 = 0x72,
- TC_OP_ATOMIC_SMAX_64 = 0x73,
- TC_OP_ATOMIC_UMAX_64 = 0x74,
- TC_OP_ATOMIC_AND_64 = 0x75,
- TC_OP_ATOMIC_OR_64 = 0x76,
- TC_OP_ATOMIC_XOR_64 = 0x77,
- TC_OP_ATOMIC_INC_64 = 0x78,
- TC_OP_ATOMIC_DEC_64 = 0x79,
- TC_OP_WBINVL2_NC = 0x7a,
- TC_OP_RESERVED_NON_FLOAT_64_0 = 0x7b,
- TC_OP_RESERVED_NON_FLOAT_64_1 = 0x7c,
- TC_OP_RESERVED_NON_FLOAT_64_2 = 0x7d,
- TC_OP_RESERVED_NON_FLOAT_64_3 = 0x7e,
- TC_OP_RESERVED_NON_FLOAT_64_4 = 0x7f,
-} TC_OP;
-typedef enum TC_CHUB_REQ_CREDITS_ENUM {
- TC_CHUB_REQ_CREDITS = 0x10,
-} TC_CHUB_REQ_CREDITS_ENUM;
-typedef enum CHUB_TC_RET_CREDITS_ENUM {
- CHUB_TC_RET_CREDITS = 0x20,
-} CHUB_TC_RET_CREDITS_ENUM;
-typedef enum TC_NACKS {
- TC_NACK_NO_FAULT = 0x0,
- TC_NACK_PAGE_FAULT = 0x1,
- TC_NACK_PROTECTION_FAULT = 0x2,
- TC_NACK_DATA_ERROR = 0x3,
-} TC_NACKS;
-typedef enum TCC_PERF_SEL {
- TCC_PERF_SEL_NONE = 0x0,
- TCC_PERF_SEL_CYCLE = 0x1,
- TCC_PERF_SEL_BUSY = 0x2,
- TCC_PERF_SEL_REQ = 0x3,
- TCC_PERF_SEL_STREAMING_REQ = 0x4,
- TCC_PERF_SEL_EXE_REQ = 0x5,
- TCC_PERF_SEL_COMPRESSED_REQ = 0x6,
- TCC_PERF_SEL_COMPRESSED_0_REQ = 0x7,
- TCC_PERF_SEL_METADATA_REQ = 0x8,
- TCC_PERF_SEL_NC_VIRTUAL_REQ = 0x9,
- TCC_PERF_SEL_NC_PHYSICAL_REQ = 0xa,
- TCC_PERF_SEL_UC_VIRTUAL_REQ = 0xb,
- TCC_PERF_SEL_UC_PHYSICAL_REQ = 0xc,
- TCC_PERF_SEL_CC_PHYSICAL_REQ = 0xd,
- TCC_PERF_SEL_PROBE = 0xe,
- TCC_PERF_SEL_READ = 0xf,
- TCC_PERF_SEL_WRITE = 0x10,
- TCC_PERF_SEL_ATOMIC = 0x11,
- TCC_PERF_SEL_HIT = 0x12,
- TCC_PERF_SEL_MISS = 0x13,
- TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT = 0x14,
- TCC_PERF_SEL_FULLY_WRITTEN_HIT = 0x15,
- TCC_PERF_SEL_WRITEBACK = 0x16,
- TCC_PERF_SEL_LATENCY_FIFO_FULL = 0x17,
- TCC_PERF_SEL_SRC_FIFO_FULL = 0x18,
- TCC_PERF_SEL_HOLE_FIFO_FULL = 0x19,
- TCC_PERF_SEL_MC_WRREQ = 0x1a,
- TCC_PERF_SEL_MC_WRREQ_UNCACHED = 0x1b,
- TCC_PERF_SEL_MC_WRREQ_STALL = 0x1c,
- TCC_PERF_SEL_MC_WRREQ_CREDIT_STALL = 0x1d,
- TCC_PERF_SEL_MC_WRREQ_MC_HALT_STALL = 0x1e,
- TCC_PERF_SEL_TOO_MANY_MC_WRREQS_STALL = 0x1f,
- TCC_PERF_SEL_MC_WRREQ_LEVEL = 0x20,
- TCC_PERF_SEL_MC_ATOMIC = 0x21,
- TCC_PERF_SEL_MC_ATOMIC_LEVEL = 0x22,
- TCC_PERF_SEL_MC_RDREQ = 0x23,
- TCC_PERF_SEL_MC_RDREQ_UNCACHED = 0x24,
- TCC_PERF_SEL_MC_RDREQ_MDC = 0x25,
- TCC_PERF_SEL_MC_RDREQ_COMPRESSED = 0x26,
- TCC_PERF_SEL_MC_RDREQ_CREDIT_STALL = 0x27,
- TCC_PERF_SEL_MC_RDREQ_MC_HALT_STALL = 0x28,
- TCC_PERF_SEL_MC_RDREQ_LEVEL = 0x29,
- TCC_PERF_SEL_TAG_STALL = 0x2a,
- TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 0x2b,
- TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 0x2c,
- TCC_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL= 0x2d,
- TCC_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL= 0x2e,
- TCC_PERF_SEL_TAG_PROBE_STALL = 0x2f,
- TCC_PERF_SEL_TAG_PROBE_FILTER_STALL = 0x30,
- TCC_PERF_SEL_READ_RETURN_TIMEOUT = 0x31,
- TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT = 0x32,
- TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE = 0x33,
- TCC_PERF_SEL_BUBBLE = 0x34,
- TCC_PERF_SEL_RETURN_ACK = 0x35,
- TCC_PERF_SEL_RETURN_DATA = 0x36,
- TCC_PERF_SEL_RETURN_HOLE = 0x37,
- TCC_PERF_SEL_RETURN_ACK_HOLE = 0x38,
- TCC_PERF_SEL_IB_REQ = 0x39,
- TCC_PERF_SEL_IB_STALL = 0x3a,
- TCC_PERF_SEL_IB_TAG_STALL = 0x3b,
- TCC_PERF_SEL_IB_MDC_STALL = 0x3c,
- TCC_PERF_SEL_TCA_LEVEL = 0x3d,
- TCC_PERF_SEL_HOLE_LEVEL = 0x3e,
- TCC_PERF_SEL_MC_RDRET_NACK = 0x3f,
- TCC_PERF_SEL_MC_WRRET_NACK = 0x40,
- TCC_PERF_SEL_NORMAL_WRITEBACK = 0x41,
- TCC_PERF_SEL_TC_OP_WBL2_NC_WRITEBACK = 0x42,
- TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK = 0x43,
- TCC_PERF_SEL_TC_OP_WBINVL2_NC_WRITEBACK = 0x44,
- TCC_PERF_SEL_TC_OP_WBINVL2_SD_WRITEBACK = 0x45,
- TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK = 0x46,
- TCC_PERF_SEL_NORMAL_EVICT = 0x47,
- TCC_PERF_SEL_TC_OP_WBL2_NC_EVICT = 0x48,
- TCC_PERF_SEL_TC_OP_INVL2_NC_EVICT = 0x49,
- TCC_PERF_SEL_TC_OP_WBINVL2_EVICT = 0x4a,
- TCC_PERF_SEL_TC_OP_WBINVL2_NC_EVICT = 0x4b,
- TCC_PERF_SEL_TC_OP_WBINVL2_SD_EVICT = 0x4c,
- TCC_PERF_SEL_ALL_TC_OP_INV_EVICT = 0x4d,
- TCC_PERF_SEL_PROBE_EVICT = 0x4e,
- TCC_PERF_SEL_TC_OP_WBL2_NC_CYCLE = 0x4f,
- TCC_PERF_SEL_TC_OP_INVL2_NC_CYCLE = 0x50,
- TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE = 0x51,
- TCC_PERF_SEL_TC_OP_WBINVL2_NC_CYCLE = 0x52,
- TCC_PERF_SEL_TC_OP_WBINVL2_SD_CYCLE = 0x53,
- TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE = 0x54,
- TCC_PERF_SEL_TC_OP_WBL2_NC_START = 0x55,
- TCC_PERF_SEL_TC_OP_INVL2_NC_START = 0x56,
- TCC_PERF_SEL_TC_OP_WBINVL2_START = 0x57,
- TCC_PERF_SEL_TC_OP_WBINVL2_NC_START = 0x58,
- TCC_PERF_SEL_TC_OP_WBINVL2_SD_START = 0x59,
- TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 0x5a,
- TCC_PERF_SEL_TC_OP_WBL2_NC_FINISH = 0x5b,
- TCC_PERF_SEL_TC_OP_INVL2_NC_FINISH = 0x5c,
- TCC_PERF_SEL_TC_OP_WBINVL2_FINISH = 0x5d,
- TCC_PERF_SEL_TC_OP_WBINVL2_NC_FINISH = 0x5e,
- TCC_PERF_SEL_TC_OP_WBINVL2_SD_FINISH = 0x5f,
- TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH = 0x60,
- TCC_PERF_SEL_MDC_REQ = 0x61,
- TCC_PERF_SEL_MDC_LEVEL = 0x62,
- TCC_PERF_SEL_MDC_TAG_HIT = 0x63,
- TCC_PERF_SEL_MDC_SECTOR_HIT = 0x64,
- TCC_PERF_SEL_MDC_SECTOR_MISS = 0x65,
- TCC_PERF_SEL_MDC_TAG_STALL = 0x66,
- TCC_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL= 0x67,
- TCC_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL= 0x68,
- TCC_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL= 0x69,
- TCC_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION = 0x6a,
- TCC_PERF_SEL_PROBE_FILTER_DISABLED = 0x6b,
- TCC_PERF_SEL_CLIENT0_REQ = 0x80,
- TCC_PERF_SEL_CLIENT1_REQ = 0x81,
- TCC_PERF_SEL_CLIENT2_REQ = 0x82,
- TCC_PERF_SEL_CLIENT3_REQ = 0x83,
- TCC_PERF_SEL_CLIENT4_REQ = 0x84,
- TCC_PERF_SEL_CLIENT5_REQ = 0x85,
- TCC_PERF_SEL_CLIENT6_REQ = 0x86,
- TCC_PERF_SEL_CLIENT7_REQ = 0x87,
- TCC_PERF_SEL_CLIENT8_REQ = 0x88,
- TCC_PERF_SEL_CLIENT9_REQ = 0x89,
- TCC_PERF_SEL_CLIENT10_REQ = 0x8a,
- TCC_PERF_SEL_CLIENT11_REQ = 0x8b,
- TCC_PERF_SEL_CLIENT12_REQ = 0x8c,
- TCC_PERF_SEL_CLIENT13_REQ = 0x8d,
- TCC_PERF_SEL_CLIENT14_REQ = 0x8e,
- TCC_PERF_SEL_CLIENT15_REQ = 0x8f,
- TCC_PERF_SEL_CLIENT16_REQ = 0x90,
- TCC_PERF_SEL_CLIENT17_REQ = 0x91,
- TCC_PERF_SEL_CLIENT18_REQ = 0x92,
- TCC_PERF_SEL_CLIENT19_REQ = 0x93,
- TCC_PERF_SEL_CLIENT20_REQ = 0x94,
- TCC_PERF_SEL_CLIENT21_REQ = 0x95,
- TCC_PERF_SEL_CLIENT22_REQ = 0x96,
- TCC_PERF_SEL_CLIENT23_REQ = 0x97,
- TCC_PERF_SEL_CLIENT24_REQ = 0x98,
- TCC_PERF_SEL_CLIENT25_REQ = 0x99,
- TCC_PERF_SEL_CLIENT26_REQ = 0x9a,
- TCC_PERF_SEL_CLIENT27_REQ = 0x9b,
- TCC_PERF_SEL_CLIENT28_REQ = 0x9c,
- TCC_PERF_SEL_CLIENT29_REQ = 0x9d,
- TCC_PERF_SEL_CLIENT30_REQ = 0x9e,
- TCC_PERF_SEL_CLIENT31_REQ = 0x9f,
- TCC_PERF_SEL_CLIENT32_REQ = 0xa0,
- TCC_PERF_SEL_CLIENT33_REQ = 0xa1,
- TCC_PERF_SEL_CLIENT34_REQ = 0xa2,
- TCC_PERF_SEL_CLIENT35_REQ = 0xa3,
- TCC_PERF_SEL_CLIENT36_REQ = 0xa4,
- TCC_PERF_SEL_CLIENT37_REQ = 0xa5,
- TCC_PERF_SEL_CLIENT38_REQ = 0xa6,
- TCC_PERF_SEL_CLIENT39_REQ = 0xa7,
- TCC_PERF_SEL_CLIENT40_REQ = 0xa8,
- TCC_PERF_SEL_CLIENT41_REQ = 0xa9,
- TCC_PERF_SEL_CLIENT42_REQ = 0xaa,
- TCC_PERF_SEL_CLIENT43_REQ = 0xab,
- TCC_PERF_SEL_CLIENT44_REQ = 0xac,
- TCC_PERF_SEL_CLIENT45_REQ = 0xad,
- TCC_PERF_SEL_CLIENT46_REQ = 0xae,
- TCC_PERF_SEL_CLIENT47_REQ = 0xaf,
- TCC_PERF_SEL_CLIENT48_REQ = 0xb0,
- TCC_PERF_SEL_CLIENT49_REQ = 0xb1,
- TCC_PERF_SEL_CLIENT50_REQ = 0xb2,
- TCC_PERF_SEL_CLIENT51_REQ = 0xb3,
- TCC_PERF_SEL_CLIENT52_REQ = 0xb4,
- TCC_PERF_SEL_CLIENT53_REQ = 0xb5,
- TCC_PERF_SEL_CLIENT54_REQ = 0xb6,
- TCC_PERF_SEL_CLIENT55_REQ = 0xb7,
- TCC_PERF_SEL_CLIENT56_REQ = 0xb8,
- TCC_PERF_SEL_CLIENT57_REQ = 0xb9,
- TCC_PERF_SEL_CLIENT58_REQ = 0xba,
- TCC_PERF_SEL_CLIENT59_REQ = 0xbb,
- TCC_PERF_SEL_CLIENT60_REQ = 0xbc,
- TCC_PERF_SEL_CLIENT61_REQ = 0xbd,
- TCC_PERF_SEL_CLIENT62_REQ = 0xbe,
- TCC_PERF_SEL_CLIENT63_REQ = 0xbf,
- TCC_PERF_SEL_CLIENT64_REQ = 0xc0,
- TCC_PERF_SEL_CLIENT65_REQ = 0xc1,
- TCC_PERF_SEL_CLIENT66_REQ = 0xc2,
- TCC_PERF_SEL_CLIENT67_REQ = 0xc3,
- TCC_PERF_SEL_CLIENT68_REQ = 0xc4,
- TCC_PERF_SEL_CLIENT69_REQ = 0xc5,
- TCC_PERF_SEL_CLIENT70_REQ = 0xc6,
- TCC_PERF_SEL_CLIENT71_REQ = 0xc7,
- TCC_PERF_SEL_CLIENT72_REQ = 0xc8,
- TCC_PERF_SEL_CLIENT73_REQ = 0xc9,
- TCC_PERF_SEL_CLIENT74_REQ = 0xca,
- TCC_PERF_SEL_CLIENT75_REQ = 0xcb,
- TCC_PERF_SEL_CLIENT76_REQ = 0xcc,
- TCC_PERF_SEL_CLIENT77_REQ = 0xcd,
- TCC_PERF_SEL_CLIENT78_REQ = 0xce,
- TCC_PERF_SEL_CLIENT79_REQ = 0xcf,
- TCC_PERF_SEL_CLIENT80_REQ = 0xd0,
- TCC_PERF_SEL_CLIENT81_REQ = 0xd1,
- TCC_PERF_SEL_CLIENT82_REQ = 0xd2,
- TCC_PERF_SEL_CLIENT83_REQ = 0xd3,
- TCC_PERF_SEL_CLIENT84_REQ = 0xd4,
- TCC_PERF_SEL_CLIENT85_REQ = 0xd5,
- TCC_PERF_SEL_CLIENT86_REQ = 0xd6,
- TCC_PERF_SEL_CLIENT87_REQ = 0xd7,
- TCC_PERF_SEL_CLIENT88_REQ = 0xd8,
- TCC_PERF_SEL_CLIENT89_REQ = 0xd9,
- TCC_PERF_SEL_CLIENT90_REQ = 0xda,
- TCC_PERF_SEL_CLIENT91_REQ = 0xdb,
- TCC_PERF_SEL_CLIENT92_REQ = 0xdc,
- TCC_PERF_SEL_CLIENT93_REQ = 0xdd,
- TCC_PERF_SEL_CLIENT94_REQ = 0xde,
- TCC_PERF_SEL_CLIENT95_REQ = 0xdf,
- TCC_PERF_SEL_CLIENT96_REQ = 0xe0,
- TCC_PERF_SEL_CLIENT97_REQ = 0xe1,
- TCC_PERF_SEL_CLIENT98_REQ = 0xe2,
- TCC_PERF_SEL_CLIENT99_REQ = 0xe3,
- TCC_PERF_SEL_CLIENT100_REQ = 0xe4,
- TCC_PERF_SEL_CLIENT101_REQ = 0xe5,
- TCC_PERF_SEL_CLIENT102_REQ = 0xe6,
- TCC_PERF_SEL_CLIENT103_REQ = 0xe7,
- TCC_PERF_SEL_CLIENT104_REQ = 0xe8,
- TCC_PERF_SEL_CLIENT105_REQ = 0xe9,
- TCC_PERF_SEL_CLIENT106_REQ = 0xea,
- TCC_PERF_SEL_CLIENT107_REQ = 0xeb,
- TCC_PERF_SEL_CLIENT108_REQ = 0xec,
- TCC_PERF_SEL_CLIENT109_REQ = 0xed,
- TCC_PERF_SEL_CLIENT110_REQ = 0xee,
- TCC_PERF_SEL_CLIENT111_REQ = 0xef,
- TCC_PERF_SEL_CLIENT112_REQ = 0xf0,
- TCC_PERF_SEL_CLIENT113_REQ = 0xf1,
- TCC_PERF_SEL_CLIENT114_REQ = 0xf2,
- TCC_PERF_SEL_CLIENT115_REQ = 0xf3,
- TCC_PERF_SEL_CLIENT116_REQ = 0xf4,
- TCC_PERF_SEL_CLIENT117_REQ = 0xf5,
- TCC_PERF_SEL_CLIENT118_REQ = 0xf6,
- TCC_PERF_SEL_CLIENT119_REQ = 0xf7,
- TCC_PERF_SEL_CLIENT120_REQ = 0xf8,
- TCC_PERF_SEL_CLIENT121_REQ = 0xf9,
- TCC_PERF_SEL_CLIENT122_REQ = 0xfa,
- TCC_PERF_SEL_CLIENT123_REQ = 0xfb,
- TCC_PERF_SEL_CLIENT124_REQ = 0xfc,
- TCC_PERF_SEL_CLIENT125_REQ = 0xfd,
- TCC_PERF_SEL_CLIENT126_REQ = 0xfe,
- TCC_PERF_SEL_CLIENT127_REQ = 0xff,
-} TCC_PERF_SEL;
-typedef enum TCA_PERF_SEL {
- TCA_PERF_SEL_NONE = 0x0,
- TCA_PERF_SEL_CYCLE = 0x1,
- TCA_PERF_SEL_BUSY = 0x2,
- TCA_PERF_SEL_FORCED_HOLE_TCC0 = 0x3,
- TCA_PERF_SEL_FORCED_HOLE_TCC1 = 0x4,
- TCA_PERF_SEL_FORCED_HOLE_TCC2 = 0x5,
- TCA_PERF_SEL_FORCED_HOLE_TCC3 = 0x6,
- TCA_PERF_SEL_FORCED_HOLE_TCC4 = 0x7,
- TCA_PERF_SEL_FORCED_HOLE_TCC5 = 0x8,
- TCA_PERF_SEL_FORCED_HOLE_TCC6 = 0x9,
- TCA_PERF_SEL_FORCED_HOLE_TCC7 = 0xa,
- TCA_PERF_SEL_REQ_TCC0 = 0xb,
- TCA_PERF_SEL_REQ_TCC1 = 0xc,
- TCA_PERF_SEL_REQ_TCC2 = 0xd,
- TCA_PERF_SEL_REQ_TCC3 = 0xe,
- TCA_PERF_SEL_REQ_TCC4 = 0xf,
- TCA_PERF_SEL_REQ_TCC5 = 0x10,
- TCA_PERF_SEL_REQ_TCC6 = 0x11,
- TCA_PERF_SEL_REQ_TCC7 = 0x12,
- TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0 = 0x13,
- TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1 = 0x14,
- TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2 = 0x15,
- TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3 = 0x16,
- TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4 = 0x17,
- TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5 = 0x18,
- TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6 = 0x19,
- TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7 = 0x1a,
- TCA_PERF_SEL_CROSSBAR_STALL_TCC0 = 0x1b,
- TCA_PERF_SEL_CROSSBAR_STALL_TCC1 = 0x1c,
- TCA_PERF_SEL_CROSSBAR_STALL_TCC2 = 0x1d,
- TCA_PERF_SEL_CROSSBAR_STALL_TCC3 = 0x1e,
- TCA_PERF_SEL_CROSSBAR_STALL_TCC4 = 0x1f,
- TCA_PERF_SEL_CROSSBAR_STALL_TCC5 = 0x20,
- TCA_PERF_SEL_CROSSBAR_STALL_TCC6 = 0x21,
- TCA_PERF_SEL_CROSSBAR_STALL_TCC7 = 0x22,
-} TCA_PERF_SEL;
-typedef enum TA_TC_ADDR_MODES {
- TA_TC_ADDR_MODE_DEFAULT = 0x0,
- TA_TC_ADDR_MODE_COMP0 = 0x1,
- TA_TC_ADDR_MODE_COMP1 = 0x2,
- TA_TC_ADDR_MODE_COMP2 = 0x3,
- TA_TC_ADDR_MODE_COMP3 = 0x4,
- TA_TC_ADDR_MODE_UNALIGNED = 0x5,
- TA_TC_ADDR_MODE_BORDER_COLOR = 0x6,
-} TA_TC_ADDR_MODES;
-typedef enum TA_PERFCOUNT_SEL {
- TA_PERF_SEL_NULL = 0x0,
- TA_PERF_SEL_sh_fifo_busy = 0x1,
- TA_PERF_SEL_sh_fifo_cmd_busy = 0x2,
- TA_PERF_SEL_sh_fifo_addr_busy = 0x3,
- TA_PERF_SEL_sh_fifo_data_busy = 0x4,
- TA_PERF_SEL_sh_fifo_data_sfifo_busy = 0x5,
- TA_PERF_SEL_sh_fifo_data_tfifo_busy = 0x6,
- TA_PERF_SEL_gradient_busy = 0x7,
- TA_PERF_SEL_gradient_fifo_busy = 0x8,
- TA_PERF_SEL_lod_busy = 0x9,
- TA_PERF_SEL_lod_fifo_busy = 0xa,
- TA_PERF_SEL_addresser_busy = 0xb,
- TA_PERF_SEL_addresser_fifo_busy = 0xc,
- TA_PERF_SEL_aligner_busy = 0xd,
- TA_PERF_SEL_write_path_busy = 0xe,
- TA_PERF_SEL_ta_busy = 0xf,
- TA_PERF_SEL_sq_ta_cmd_cycles = 0x10,
- TA_PERF_SEL_sp_ta_addr_cycles = 0x11,
- TA_PERF_SEL_sp_ta_data_cycles = 0x12,
- TA_PERF_SEL_ta_fa_data_state_cycles = 0x13,
- TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles = 0x14,
- TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles = 0x15,
- TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles= 0x16,
- TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles= 0x17,
- TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles= 0x18,
- TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles= 0x19,
- TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles= 0x1a,
- TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles= 0x1b,
- TA_PERF_SEL_RESERVED_28 = 0x1c,
- TA_PERF_SEL_RESERVED_29 = 0x1d,
- TA_PERF_SEL_sh_fifo_addr_cycles = 0x1e,
- TA_PERF_SEL_sh_fifo_data_cycles = 0x1f,
- TA_PERF_SEL_total_wavefronts = 0x20,
- TA_PERF_SEL_gradient_cycles = 0x21,
- TA_PERF_SEL_walker_cycles = 0x22,
- TA_PERF_SEL_aligner_cycles = 0x23,
- TA_PERF_SEL_image_wavefronts = 0x24,
- TA_PERF_SEL_image_read_wavefronts = 0x25,
- TA_PERF_SEL_image_write_wavefronts = 0x26,
- TA_PERF_SEL_image_atomic_wavefronts = 0x27,
- TA_PERF_SEL_image_total_cycles = 0x28,
- TA_PERF_SEL_RESERVED_41 = 0x29,
- TA_PERF_SEL_RESERVED_42 = 0x2a,
- TA_PERF_SEL_RESERVED_43 = 0x2b,
- TA_PERF_SEL_buffer_wavefronts = 0x2c,
- TA_PERF_SEL_buffer_read_wavefronts = 0x2d,
- TA_PERF_SEL_buffer_write_wavefronts = 0x2e,
- TA_PERF_SEL_buffer_atomic_wavefronts = 0x2f,
- TA_PERF_SEL_buffer_coalescable_wavefronts = 0x30,
- TA_PERF_SEL_buffer_total_cycles = 0x31,
- TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles= 0x32,
- TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles= 0x33,
- TA_PERF_SEL_buffer_coalesced_read_cycles = 0x34,
- TA_PERF_SEL_buffer_coalesced_write_cycles = 0x35,
- TA_PERF_SEL_addr_stalled_by_tc_cycles = 0x36,
- TA_PERF_SEL_addr_stalled_by_td_cycles = 0x37,
- TA_PERF_SEL_data_stalled_by_tc_cycles = 0x38,
- TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles= 0x39,
- TA_PERF_SEL_addresser_stalled_cycles = 0x3a,
- TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles= 0x3b,
- TA_PERF_SEL_aniso_stalled_cycles = 0x3c,
- TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 0x3d,
- TA_PERF_SEL_deriv_stalled_cycles = 0x3e,
- TA_PERF_SEL_aniso_gt1_cycle_quads = 0x3f,
- TA_PERF_SEL_color_1_cycle_pixels = 0x40,
- TA_PERF_SEL_color_2_cycle_pixels = 0x41,
- TA_PERF_SEL_color_3_cycle_pixels = 0x42,
- TA_PERF_SEL_color_4_cycle_pixels = 0x43,
- TA_PERF_SEL_mip_1_cycle_pixels = 0x44,
- TA_PERF_SEL_mip_2_cycle_pixels = 0x45,
- TA_PERF_SEL_vol_1_cycle_pixels = 0x46,
- TA_PERF_SEL_vol_2_cycle_pixels = 0x47,
- TA_PERF_SEL_bilin_point_1_cycle_pixels = 0x48,
- TA_PERF_SEL_mipmap_lod_0_samples = 0x49,
- TA_PERF_SEL_mipmap_lod_1_samples = 0x4a,
- TA_PERF_SEL_mipmap_lod_2_samples = 0x4b,
- TA_PERF_SEL_mipmap_lod_3_samples = 0x4c,
- TA_PERF_SEL_mipmap_lod_4_samples = 0x4d,
- TA_PERF_SEL_mipmap_lod_5_samples = 0x4e,
- TA_PERF_SEL_mipmap_lod_6_samples = 0x4f,
- TA_PERF_SEL_mipmap_lod_7_samples = 0x50,
- TA_PERF_SEL_mipmap_lod_8_samples = 0x51,
- TA_PERF_SEL_mipmap_lod_9_samples = 0x52,
- TA_PERF_SEL_mipmap_lod_10_samples = 0x53,
- TA_PERF_SEL_mipmap_lod_11_samples = 0x54,
- TA_PERF_SEL_mipmap_lod_12_samples = 0x55,
- TA_PERF_SEL_mipmap_lod_13_samples = 0x56,
- TA_PERF_SEL_mipmap_lod_14_samples = 0x57,
- TA_PERF_SEL_mipmap_invalid_samples = 0x58,
- TA_PERF_SEL_aniso_1_cycle_quads = 0x59,
- TA_PERF_SEL_aniso_2_cycle_quads = 0x5a,
- TA_PERF_SEL_aniso_4_cycle_quads = 0x5b,
- TA_PERF_SEL_aniso_6_cycle_quads = 0x5c,
- TA_PERF_SEL_aniso_8_cycle_quads = 0x5d,
- TA_PERF_SEL_aniso_10_cycle_quads = 0x5e,
- TA_PERF_SEL_aniso_12_cycle_quads = 0x5f,
- TA_PERF_SEL_aniso_14_cycle_quads = 0x60,
- TA_PERF_SEL_aniso_16_cycle_quads = 0x61,
- TA_PERF_SEL_write_path_input_cycles = 0x62,
- TA_PERF_SEL_write_path_output_cycles = 0x63,
- TA_PERF_SEL_flat_wavefronts = 0x64,
- TA_PERF_SEL_flat_read_wavefronts = 0x65,
- TA_PERF_SEL_flat_write_wavefronts = 0x66,
- TA_PERF_SEL_flat_atomic_wavefronts = 0x67,
- TA_PERF_SEL_flat_coalesceable_wavefronts = 0x68,
- TA_PERF_SEL_reg_sclk_vld = 0x69,
- TA_PERF_SEL_local_cg_dyn_sclk_grp0_en = 0x6a,
- TA_PERF_SEL_local_cg_dyn_sclk_grp1_en = 0x6b,
- TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en = 0x6c,
- TA_PERF_SEL_local_cg_dyn_sclk_grp4_en = 0x6d,
- TA_PERF_SEL_local_cg_dyn_sclk_grp5_en = 0x6e,
- TA_PERF_SEL_xnack_on_phase0 = 0x6f,
- TA_PERF_SEL_xnack_on_phase1 = 0x70,
- TA_PERF_SEL_xnack_on_phase2 = 0x71,
- TA_PERF_SEL_xnack_on_phase3 = 0x72,
- TA_PERF_SEL_first_xnack_on_phase0 = 0x73,
- TA_PERF_SEL_first_xnack_on_phase1 = 0x74,
- TA_PERF_SEL_first_xnack_on_phase2 = 0x75,
- TA_PERF_SEL_first_xnack_on_phase3 = 0x76,
-} TA_PERFCOUNT_SEL;
-typedef enum TD_PERFCOUNT_SEL {
- TD_PERF_SEL_none = 0x0,
- TD_PERF_SEL_td_busy = 0x1,
- TD_PERF_SEL_input_busy = 0x2,
- TD_PERF_SEL_output_busy = 0x3,
- TD_PERF_SEL_lerp_busy = 0x4,
- TD_PERF_SEL_reg_sclk_vld = 0x5,
- TD_PERF_SEL_local_cg_dyn_sclk_grp0_en = 0x6,
- TD_PERF_SEL_local_cg_dyn_sclk_grp1_en = 0x7,
- TD_PERF_SEL_local_cg_dyn_sclk_grp4_en = 0x8,
- TD_PERF_SEL_local_cg_dyn_sclk_grp5_en = 0x9,
- TD_PERF_SEL_tc_td_fifo_full = 0xa,
- TD_PERF_SEL_constant_state_full = 0xb,
- TD_PERF_SEL_sample_state_full = 0xc,
- TD_PERF_SEL_output_fifo_full = 0xd,
- TD_PERF_SEL_RESERVED_14 = 0xe,
- TD_PERF_SEL_tc_stall = 0xf,
- TD_PERF_SEL_pc_stall = 0x10,
- TD_PERF_SEL_gds_stall = 0x11,
- TD_PERF_SEL_RESERVED_18 = 0x12,
- TD_PERF_SEL_RESERVED_19 = 0x13,
- TD_PERF_SEL_gather4_wavefront = 0x14,
- TD_PERF_SEL_sample_c_wavefront = 0x15,
- TD_PERF_SEL_load_wavefront = 0x16,
- TD_PERF_SEL_atomic_wavefront = 0x17,
- TD_PERF_SEL_store_wavefront = 0x18,
- TD_PERF_SEL_ldfptr_wavefront = 0x19,
- TD_PERF_SEL_RESERVED_26 = 0x1a,
- TD_PERF_SEL_RESERVED_27 = 0x1b,
- TD_PERF_SEL_d16_en_wavefront = 0x1c,
- TD_PERF_SEL_bicubic_filter_wavefront = 0x1d,
- TD_PERF_SEL_bypass_filter_wavefront = 0x1e,
- TD_PERF_SEL_min_max_filter_wavefront = 0x1f,
- TD_PERF_SEL_coalescable_wavefront = 0x20,
- TD_PERF_SEL_coalesced_phase = 0x21,
- TD_PERF_SEL_four_phase_wavefront = 0x22,
- TD_PERF_SEL_eight_phase_wavefront = 0x23,
- TD_PERF_SEL_sixteen_phase_wavefront = 0x24,
- TD_PERF_SEL_four_phase_forward_wavefront = 0x25,
- TD_PERF_SEL_write_ack_wavefront = 0x26,
- TD_PERF_SEL_RESERVED_39 = 0x27,
- TD_PERF_SEL_user_defined_border = 0x28,
- TD_PERF_SEL_white_border = 0x29,
- TD_PERF_SEL_opaque_black_border = 0x2a,
- TD_PERF_SEL_RESERVED_43 = 0x2b,
- TD_PERF_SEL_RESERVED_44 = 0x2c,
- TD_PERF_SEL_nack = 0x2d,
- TD_PERF_SEL_td_sp_traffic = 0x2e,
- TD_PERF_SEL_consume_gds_traffic = 0x2f,
- TD_PERF_SEL_addresscmd_poison = 0x30,
- TD_PERF_SEL_data_poison = 0x31,
- TD_PERF_SEL_start_cycle_0 = 0x32,
- TD_PERF_SEL_start_cycle_1 = 0x33,
- TD_PERF_SEL_start_cycle_2 = 0x34,
- TD_PERF_SEL_start_cycle_3 = 0x35,
- TD_PERF_SEL_null_cycle_output = 0x36,
- TD_PERF_SEL_d16_data_packed = 0x37,
-} TD_PERFCOUNT_SEL;
-typedef enum TCP_PERFCOUNT_SELECT {
- TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES = 0x0,
- TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES = 0x1,
- TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES = 0x2,
- TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES = 0x3,
- TCP_PERF_SEL_TD_TCP_STALL_CYCLES = 0x4,
- TCP_PERF_SEL_TCR_TCP_STALL_CYCLES = 0x5,
- TCP_PERF_SEL_LOD_STALL_CYCLES = 0x6,
- TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES = 0x7,
- TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES = 0x8,
- TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES = 0x9,
- TCP_PERF_SEL_ALLOC_STALL_CYCLES = 0xa,
- TCP_PERF_SEL_LFIFO_STALL_CYCLES = 0xb,
- TCP_PERF_SEL_RFIFO_STALL_CYCLES = 0xc,
- TCP_PERF_SEL_TCR_RDRET_STALL = 0xd,
- TCP_PERF_SEL_WRITE_CONFLICT_STALL = 0xe,
- TCP_PERF_SEL_HOLE_READ_STALL = 0xf,
- TCP_PERF_SEL_READCONFLICT_STALL_CYCLES = 0x10,
- TCP_PERF_SEL_PENDING_STALL_CYCLES = 0x11,
- TCP_PERF_SEL_READFIFO_STALL_CYCLES = 0x12,
- TCP_PERF_SEL_TCP_LATENCY = 0x13,
- TCP_PERF_SEL_TCC_READ_REQ_LATENCY = 0x14,
- TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY = 0x15,
- TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY = 0x16,
- TCP_PERF_SEL_TCC_READ_REQ = 0x17,
- TCP_PERF_SEL_TCC_WRITE_REQ = 0x18,
- TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ = 0x19,
- TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ = 0x1a,
- TCP_PERF_SEL_TOTAL_LOCAL_READ = 0x1b,
- TCP_PERF_SEL_TOTAL_GLOBAL_READ = 0x1c,
- TCP_PERF_SEL_TOTAL_LOCAL_WRITE = 0x1d,
- TCP_PERF_SEL_TOTAL_GLOBAL_WRITE = 0x1e,
- TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET = 0x1f,
- TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET = 0x20,
- TCP_PERF_SEL_TOTAL_WBINVL1 = 0x21,
- TCP_PERF_SEL_IMG_READ_FMT_1 = 0x22,
- TCP_PERF_SEL_IMG_READ_FMT_8 = 0x23,
- TCP_PERF_SEL_IMG_READ_FMT_16 = 0x24,
- TCP_PERF_SEL_IMG_READ_FMT_32 = 0x25,
- TCP_PERF_SEL_IMG_READ_FMT_32_AS_8 = 0x26,
- TCP_PERF_SEL_IMG_READ_FMT_32_AS_16 = 0x27,
- TCP_PERF_SEL_IMG_READ_FMT_32_AS_128 = 0x28,
- TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE = 0x29,
- TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE = 0x2a,
- TCP_PERF_SEL_IMG_READ_FMT_96 = 0x2b,
- TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE = 0x2c,
- TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE = 0x2d,
- TCP_PERF_SEL_IMG_READ_FMT_BC1 = 0x2e,
- TCP_PERF_SEL_IMG_READ_FMT_BC2 = 0x2f,
- TCP_PERF_SEL_IMG_READ_FMT_BC3 = 0x30,
- TCP_PERF_SEL_IMG_READ_FMT_BC4 = 0x31,
- TCP_PERF_SEL_IMG_READ_FMT_BC5 = 0x32,
- TCP_PERF_SEL_IMG_READ_FMT_BC6 = 0x33,
- TCP_PERF_SEL_IMG_READ_FMT_BC7 = 0x34,
- TCP_PERF_SEL_IMG_READ_FMT_I8 = 0x35,
- TCP_PERF_SEL_IMG_READ_FMT_I16 = 0x36,
- TCP_PERF_SEL_IMG_READ_FMT_I32 = 0x37,
- TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8 = 0x38,
- TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16 = 0x39,
- TCP_PERF_SEL_IMG_READ_FMT_D8 = 0x3a,
- TCP_PERF_SEL_IMG_READ_FMT_D16 = 0x3b,
- TCP_PERF_SEL_IMG_READ_FMT_D32 = 0x3c,
- TCP_PERF_SEL_IMG_WRITE_FMT_8 = 0x3d,
- TCP_PERF_SEL_IMG_WRITE_FMT_16 = 0x3e,
- TCP_PERF_SEL_IMG_WRITE_FMT_32 = 0x3f,
- TCP_PERF_SEL_IMG_WRITE_FMT_64 = 0x40,
- TCP_PERF_SEL_IMG_WRITE_FMT_128 = 0x41,
- TCP_PERF_SEL_IMG_WRITE_FMT_D8 = 0x42,
- TCP_PERF_SEL_IMG_WRITE_FMT_D16 = 0x43,
- TCP_PERF_SEL_IMG_WRITE_FMT_D32 = 0x44,
- TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32 = 0x45,
- TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32 = 0x46,
- TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64 = 0x47,
- TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64 = 0x48,
- TCP_PERF_SEL_BUF_READ_FMT_8 = 0x49,
- TCP_PERF_SEL_BUF_READ_FMT_16 = 0x4a,
- TCP_PERF_SEL_BUF_READ_FMT_32 = 0x4b,
- TCP_PERF_SEL_BUF_WRITE_FMT_8 = 0x4c,
- TCP_PERF_SEL_BUF_WRITE_FMT_16 = 0x4d,
- TCP_PERF_SEL_BUF_WRITE_FMT_32 = 0x4e,
- TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32 = 0x4f,
- TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32 = 0x50,
- TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64 = 0x51,
- TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64 = 0x52,
- TCP_PERF_SEL_ARR_LINEAR_GENERAL = 0x53,
- TCP_PERF_SEL_ARR_LINEAR_ALIGNED = 0x54,
- TCP_PERF_SEL_ARR_1D_THIN1 = 0x55,
- TCP_PERF_SEL_ARR_1D_THICK = 0x56,
- TCP_PERF_SEL_ARR_2D_THIN1 = 0x57,
- TCP_PERF_SEL_ARR_2D_THICK = 0x58,
- TCP_PERF_SEL_ARR_2D_XTHICK = 0x59,
- TCP_PERF_SEL_ARR_3D_THIN1 = 0x5a,
- TCP_PERF_SEL_ARR_3D_THICK = 0x5b,
- TCP_PERF_SEL_ARR_3D_XTHICK = 0x5c,
- TCP_PERF_SEL_DIM_1D = 0x5d,
- TCP_PERF_SEL_DIM_2D = 0x5e,
- TCP_PERF_SEL_DIM_3D = 0x5f,
- TCP_PERF_SEL_DIM_1D_ARRAY = 0x60,
- TCP_PERF_SEL_DIM_2D_ARRAY = 0x61,
- TCP_PERF_SEL_DIM_2D_MSAA = 0x62,
- TCP_PERF_SEL_DIM_2D_ARRAY_MSAA = 0x63,
- TCP_PERF_SEL_DIM_CUBE_ARRAY = 0x64,
- TCP_PERF_SEL_CP_TCP_INVALIDATE = 0x65,
- TCP_PERF_SEL_TA_TCP_STATE_READ = 0x66,
- TCP_PERF_SEL_TAGRAM0_REQ = 0x67,
- TCP_PERF_SEL_TAGRAM1_REQ = 0x68,
- TCP_PERF_SEL_TAGRAM2_REQ = 0x69,
- TCP_PERF_SEL_TAGRAM3_REQ = 0x6a,
- TCP_PERF_SEL_GATE_EN1 = 0x6b,
- TCP_PERF_SEL_GATE_EN2 = 0x6c,
- TCP_PERF_SEL_CORE_REG_SCLK_VLD = 0x6d,
- TCP_PERF_SEL_TCC_REQ = 0x6e,
- TCP_PERF_SEL_TCC_NON_READ_REQ = 0x6f,
- TCP_PERF_SEL_TCC_BYPASS_READ_REQ = 0x70,
- TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ = 0x71,
- TCP_PERF_SEL_TCC_VOLATILE_READ_REQ = 0x72,
- TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ = 0x73,
- TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ = 0x74,
- TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ = 0x75,
- TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ = 0x76,
- TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ = 0x77,
- TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ = 0x78,
- TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ = 0x79,
- TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ = 0x7a,
- TCP_PERF_SEL_TCC_ATOMIC_REQ = 0x7b,
- TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ = 0x7c,
- TCP_PERF_SEL_TCC_DATA_BUS_BUSY = 0x7d,
- TCP_PERF_SEL_TOTAL_ACCESSES = 0x7e,
- TCP_PERF_SEL_TOTAL_READ = 0x7f,
- TCP_PERF_SEL_TOTAL_HIT_LRU_READ = 0x80,
- TCP_PERF_SEL_TOTAL_HIT_EVICT_READ = 0x81,
- TCP_PERF_SEL_TOTAL_MISS_LRU_READ = 0x82,
- TCP_PERF_SEL_TOTAL_MISS_EVICT_READ = 0x83,
- TCP_PERF_SEL_TOTAL_NON_READ = 0x84,
- TCP_PERF_SEL_TOTAL_WRITE = 0x85,
- TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE = 0x86,
- TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE = 0x87,
- TCP_PERF_SEL_TOTAL_WBINVL1_VOL = 0x88,
- TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES = 0x89,
- TCP_PERF_SEL_DISPLAY_MICROTILING = 0x8a,
- TCP_PERF_SEL_THIN_MICROTILING = 0x8b,
- TCP_PERF_SEL_DEPTH_MICROTILING = 0x8c,
- TCP_PERF_SEL_ARR_PRT_THIN1 = 0x8d,
- TCP_PERF_SEL_ARR_PRT_2D_THIN1 = 0x8e,
- TCP_PERF_SEL_ARR_PRT_3D_THIN1 = 0x8f,
- TCP_PERF_SEL_ARR_PRT_THICK = 0x90,
- TCP_PERF_SEL_ARR_PRT_2D_THICK = 0x91,
- TCP_PERF_SEL_ARR_PRT_3D_THICK = 0x92,
- TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL = 0x93,
- TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL = 0x94,
- TCP_PERF_SEL_UNALIGNED = 0x95,
- TCP_PERF_SEL_ROTATED_MICROTILING = 0x96,
- TCP_PERF_SEL_THICK_MICROTILING = 0x97,
- TCP_PERF_SEL_ATC = 0x98,
- TCP_PERF_SEL_POWER_STALL = 0x99,
- TCP_PERF_SEL_RESERVED_154 = 0x9a,
- TCP_PERF_SEL_TCC_LRU_REQ = 0x9b,
- TCP_PERF_SEL_TCC_STREAM_REQ = 0x9c,
- TCP_PERF_SEL_TCC_NC_READ_REQ = 0x9d,
- TCP_PERF_SEL_TCC_NC_WRITE_REQ = 0x9e,
- TCP_PERF_SEL_TCC_NC_ATOMIC_REQ = 0x9f,
- TCP_PERF_SEL_TCC_UC_READ_REQ = 0xa0,
- TCP_PERF_SEL_TCC_UC_WRITE_REQ = 0xa1,
- TCP_PERF_SEL_TCC_UC_ATOMIC_REQ = 0xa2,
- TCP_PERF_SEL_TCC_CC_READ_REQ = 0xa3,
- TCP_PERF_SEL_TCC_CC_WRITE_REQ = 0xa4,
- TCP_PERF_SEL_TCC_CC_ATOMIC_REQ = 0xa5,
- TCP_PERF_SEL_TCC_DCC_REQ = 0xa6,
- TCP_PERF_SEL_TCC_PHYSICAL_REQ = 0xa7,
- TCP_PERF_SEL_UNORDERED_MTYPE_STALL = 0xa8,
- TCP_PERF_SEL_VOLATILE = 0xa9,
- TCP_PERF_SEL_TC_TA_XNACK_STALL = 0xaa,
- TCP_PERF_SEL_ATCL1_SERIALIZATION_STALL = 0xab,
- TCP_PERF_SEL_SHOOTDOWN = 0xac,
- TCP_PERF_SEL_GATCL1_TRANSLATION_MISS = 0xad,
- TCP_PERF_SEL_GATCL1_PERMISSION_MISS = 0xae,
- TCP_PERF_SEL_GATCL1_REQUEST = 0xaf,
- TCP_PERF_SEL_GATCL1_STALL_INFLIGHT_MAX = 0xb0,
- TCP_PERF_SEL_GATCL1_STALL_LRU_INFLIGHT = 0xb1,
- TCP_PERF_SEL_GATCL1_LFIFO_FULL = 0xb2,
- TCP_PERF_SEL_GATCL1_STALL_LFIFO_NOT_RES = 0xb3,
- TCP_PERF_SEL_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS= 0xb4,
- TCP_PERF_SEL_GATCL1_ATCL2_INFLIGHT = 0xb5,
- TCP_PERF_SEL_GATCL1_STALL_MISSFIFO_FULL = 0xb6,
- TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGB = 0xb7,
- TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA = 0xb8,
- TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA1 = 0xb9,
- TCP_PERF_SEL_IMG_READ_FMT_ETC2_R = 0xba,
- TCP_PERF_SEL_IMG_READ_FMT_ETC2_RG = 0xbb,
- TCP_PERF_SEL_IMG_READ_FMT_8_AS_32 = 0xbc,
- TCP_PERF_SEL_IMG_READ_FMT_8_AS_64 = 0xbd,
- TCP_PERF_SEL_IMG_READ_FMT_16_AS_64 = 0xbe,
- TCP_PERF_SEL_IMG_READ_FMT_16_AS_128 = 0xbf,
- TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_32 = 0xc0,
- TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_64 = 0xc1,
- TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_64 = 0xc2,
- TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_128 = 0xc3,
-} TCP_PERFCOUNT_SELECT;
-typedef enum TCP_CACHE_POLICIES {
- TCP_CACHE_POLICY_MISS_LRU = 0x0,
- TCP_CACHE_POLICY_MISS_EVICT = 0x1,
- TCP_CACHE_POLICY_HIT_LRU = 0x2,
- TCP_CACHE_POLICY_HIT_EVICT = 0x3,
-} TCP_CACHE_POLICIES;
-typedef enum TCP_CACHE_STORE_POLICIES {
- TCP_CACHE_STORE_POLICY_WT_LRU = 0x0,
- TCP_CACHE_STORE_POLICY_WT_EVICT = 0x1,
-} TCP_CACHE_STORE_POLICIES;
-typedef enum TCP_WATCH_MODES {
- TCP_WATCH_MODE_READ = 0x0,
- TCP_WATCH_MODE_NONREAD = 0x1,
- TCP_WATCH_MODE_ATOMIC = 0x2,
- TCP_WATCH_MODE_ALL = 0x3,
-} TCP_WATCH_MODES;
-typedef enum TCP_DSM_DATA_SEL {
- TCP_DSM_DISABLE = 0x0,
- TCP_DSM_SEL0 = 0x1,
- TCP_DSM_SEL1 = 0x2,
- TCP_DSM_SEL_BOTH = 0x3,
-} TCP_DSM_DATA_SEL;
-typedef enum TCP_DSM_SINGLE_WRITE {
- TCP_DSM_SINGLE_WRITE_EN = 0x1,
-} TCP_DSM_SINGLE_WRITE;
-typedef enum VGT_OUT_PRIM_TYPE {
- VGT_OUT_POINT = 0x0,
- VGT_OUT_LINE = 0x1,
- VGT_OUT_TRI = 0x2,
- VGT_OUT_RECT_V0 = 0x3,
- VGT_OUT_RECT_V1 = 0x4,
- VGT_OUT_RECT_V2 = 0x5,
- VGT_OUT_RECT_V3 = 0x6,
- VGT_OUT_RESERVED = 0x7,
- VGT_TE_QUAD = 0x8,
- VGT_TE_PRIM_INDEX_LINE = 0x9,
- VGT_TE_PRIM_INDEX_TRI = 0xa,
- VGT_TE_PRIM_INDEX_QUAD = 0xb,
- VGT_OUT_LINE_ADJ = 0xc,
- VGT_OUT_TRI_ADJ = 0xd,
- VGT_OUT_PATCH = 0xe,
-} VGT_OUT_PRIM_TYPE;
-typedef enum VGT_DI_PRIM_TYPE {
- DI_PT_NONE = 0x0,
- DI_PT_POINTLIST = 0x1,
- DI_PT_LINELIST = 0x2,
- DI_PT_LINESTRIP = 0x3,
- DI_PT_TRILIST = 0x4,
- DI_PT_TRIFAN = 0x5,
- DI_PT_TRISTRIP = 0x6,
- DI_PT_UNUSED_0 = 0x7,
- DI_PT_UNUSED_1 = 0x8,
- DI_PT_PATCH = 0x9,
- DI_PT_LINELIST_ADJ = 0xa,
- DI_PT_LINESTRIP_ADJ = 0xb,
- DI_PT_TRILIST_ADJ = 0xc,
- DI_PT_TRISTRIP_ADJ = 0xd,
- DI_PT_UNUSED_3 = 0xe,
- DI_PT_UNUSED_4 = 0xf,
- DI_PT_TRI_WITH_WFLAGS = 0x10,
- DI_PT_RECTLIST = 0x11,
- DI_PT_LINELOOP = 0x12,
- DI_PT_QUADLIST = 0x13,
- DI_PT_QUADSTRIP = 0x14,
- DI_PT_POLYGON = 0x15,
- DI_PT_2D_COPY_RECT_LIST_V0 = 0x16,
- DI_PT_2D_COPY_RECT_LIST_V1 = 0x17,
- DI_PT_2D_COPY_RECT_LIST_V2 = 0x18,
- DI_PT_2D_COPY_RECT_LIST_V3 = 0x19,
- DI_PT_2D_FILL_RECT_LIST = 0x1a,
- DI_PT_2D_LINE_STRIP = 0x1b,
- DI_PT_2D_TRI_STRIP = 0x1c,
-} VGT_DI_PRIM_TYPE;
-typedef enum VGT_DI_SOURCE_SELECT {
- DI_SRC_SEL_DMA = 0x0,
- DI_SRC_SEL_IMMEDIATE = 0x1,
- DI_SRC_SEL_AUTO_INDEX = 0x2,
- DI_SRC_SEL_RESERVED = 0x3,
-} VGT_DI_SOURCE_SELECT;
-typedef enum VGT_DI_MAJOR_MODE_SELECT {
- DI_MAJOR_MODE_0 = 0x0,
- DI_MAJOR_MODE_1 = 0x1,
-} VGT_DI_MAJOR_MODE_SELECT;
-typedef enum VGT_DI_INDEX_SIZE {
- DI_INDEX_SIZE_16_BIT = 0x0,
- DI_INDEX_SIZE_32_BIT = 0x1,
- DI_INDEX_SIZE_8_BIT = 0x2,
-} VGT_DI_INDEX_SIZE;
-typedef enum VGT_EVENT_TYPE {
- Reserved_0x00 = 0x0,
- SAMPLE_STREAMOUTSTATS1 = 0x1,
- SAMPLE_STREAMOUTSTATS2 = 0x2,
- SAMPLE_STREAMOUTSTATS3 = 0x3,
- CACHE_FLUSH_TS = 0x4,
- CONTEXT_DONE = 0x5,
- CACHE_FLUSH = 0x6,
- CS_PARTIAL_FLUSH = 0x7,
- VGT_STREAMOUT_SYNC = 0x8,
- Reserved_0x09 = 0x9,
- VGT_STREAMOUT_RESET = 0xa,
- END_OF_PIPE_INCR_DE = 0xb,
- END_OF_PIPE_IB_END = 0xc,
- RST_PIX_CNT = 0xd,
- Reserved_0x0E = 0xe,
- VS_PARTIAL_FLUSH = 0xf,
- PS_PARTIAL_FLUSH = 0x10,
- FLUSH_HS_OUTPUT = 0x11,
- FLUSH_LS_OUTPUT = 0x12,
- Reserved_0x13 = 0x13,
- CACHE_FLUSH_AND_INV_TS_EVENT = 0x14,
- ZPASS_DONE = 0x15,
- CACHE_FLUSH_AND_INV_EVENT = 0x16,
- PERFCOUNTER_START = 0x17,
- PERFCOUNTER_STOP = 0x18,
- PIPELINESTAT_START = 0x19,
- PIPELINESTAT_STOP = 0x1a,
- PERFCOUNTER_SAMPLE = 0x1b,
- FLUSH_ES_OUTPUT = 0x1c,
- FLUSH_GS_OUTPUT = 0x1d,
- SAMPLE_PIPELINESTAT = 0x1e,
- SO_VGTSTREAMOUT_FLUSH = 0x1f,
- SAMPLE_STREAMOUTSTATS = 0x20,
- RESET_VTX_CNT = 0x21,
- BLOCK_CONTEXT_DONE = 0x22,
- CS_CONTEXT_DONE = 0x23,
- VGT_FLUSH = 0x24,
- TGID_ROLLOVER = 0x25,
- SQ_NON_EVENT = 0x26,
- SC_SEND_DB_VPZ = 0x27,
- BOTTOM_OF_PIPE_TS = 0x28,
- FLUSH_SX_TS = 0x29,
- DB_CACHE_FLUSH_AND_INV = 0x2a,
- FLUSH_AND_INV_DB_DATA_TS = 0x2b,
- FLUSH_AND_INV_DB_META = 0x2c,
- FLUSH_AND_INV_CB_DATA_TS = 0x2d,
- FLUSH_AND_INV_CB_META = 0x2e,
- CS_DONE = 0x2f,
- PS_DONE = 0x30,
- FLUSH_AND_INV_CB_PIXEL_DATA = 0x31,
- SX_CB_RAT_ACK_REQUEST = 0x32,
- THREAD_TRACE_START = 0x33,
- THREAD_TRACE_STOP = 0x34,
- THREAD_TRACE_MARKER = 0x35,
- THREAD_TRACE_FLUSH = 0x36,
- THREAD_TRACE_FINISH = 0x37,
- PIXEL_PIPE_STAT_CONTROL = 0x38,
- PIXEL_PIPE_STAT_DUMP = 0x39,
- PIXEL_PIPE_STAT_RESET = 0x3a,
- CONTEXT_SUSPEND = 0x3b,
- OFFCHIP_HS_DEALLOC = 0x3c,
-} VGT_EVENT_TYPE;
-typedef enum VGT_DMA_SWAP_MODE {
- VGT_DMA_SWAP_NONE = 0x0,
- VGT_DMA_SWAP_16_BIT = 0x1,
- VGT_DMA_SWAP_32_BIT = 0x2,
- VGT_DMA_SWAP_WORD = 0x3,
-} VGT_DMA_SWAP_MODE;
-typedef enum VGT_INDEX_TYPE_MODE {
- VGT_INDEX_16 = 0x0,
- VGT_INDEX_32 = 0x1,
- VGT_INDEX_8 = 0x2,
-} VGT_INDEX_TYPE_MODE;
-typedef enum VGT_DMA_BUF_TYPE {
- VGT_DMA_BUF_MEM = 0x0,
- VGT_DMA_BUF_RING = 0x1,
- VGT_DMA_BUF_SETUP = 0x2,
- VGT_DMA_PTR_UPDATE = 0x3,
-} VGT_DMA_BUF_TYPE;
-typedef enum VGT_OUTPATH_SELECT {
- VGT_OUTPATH_VTX_REUSE = 0x0,
- VGT_OUTPATH_TESS_EN = 0x1,
- VGT_OUTPATH_PASSTHRU = 0x2,
- VGT_OUTPATH_GS_BLOCK = 0x3,
- VGT_OUTPATH_HS_BLOCK = 0x4,
-} VGT_OUTPATH_SELECT;
-typedef enum VGT_GRP_PRIM_TYPE {
- VGT_GRP_3D_POINT = 0x0,
- VGT_GRP_3D_LINE = 0x1,
- VGT_GRP_3D_TRI = 0x2,
- VGT_GRP_3D_RECT = 0x3,
- VGT_GRP_3D_QUAD = 0x4,
- VGT_GRP_2D_COPY_RECT_V0 = 0x5,
- VGT_GRP_2D_COPY_RECT_V1 = 0x6,
- VGT_GRP_2D_COPY_RECT_V2 = 0x7,
- VGT_GRP_2D_COPY_RECT_V3 = 0x8,
- VGT_GRP_2D_FILL_RECT = 0x9,
- VGT_GRP_2D_LINE = 0xa,
- VGT_GRP_2D_TRI = 0xb,
- VGT_GRP_PRIM_INDEX_LINE = 0xc,
- VGT_GRP_PRIM_INDEX_TRI = 0xd,
- VGT_GRP_PRIM_INDEX_QUAD = 0xe,
- VGT_GRP_3D_LINE_ADJ = 0xf,
- VGT_GRP_3D_TRI_ADJ = 0x10,
- VGT_GRP_3D_PATCH = 0x11,
-} VGT_GRP_PRIM_TYPE;
-typedef enum VGT_GRP_PRIM_ORDER {
- VGT_GRP_LIST = 0x0,
- VGT_GRP_STRIP = 0x1,
- VGT_GRP_FAN = 0x2,
- VGT_GRP_LOOP = 0x3,
- VGT_GRP_POLYGON = 0x4,
-} VGT_GRP_PRIM_ORDER;
-typedef enum VGT_GROUP_CONV_SEL {
- VGT_GRP_INDEX_16 = 0x0,
- VGT_GRP_INDEX_32 = 0x1,
- VGT_GRP_UINT_16 = 0x2,
- VGT_GRP_UINT_32 = 0x3,
- VGT_GRP_SINT_16 = 0x4,
- VGT_GRP_SINT_32 = 0x5,
- VGT_GRP_FLOAT_32 = 0x6,
- VGT_GRP_AUTO_PRIM = 0x7,
- VGT_GRP_FIX_1_23_TO_FLOAT = 0x8,
-} VGT_GROUP_CONV_SEL;
-typedef enum VGT_GS_MODE_TYPE {
- GS_OFF = 0x0,
- GS_SCENARIO_A = 0x1,
- GS_SCENARIO_B = 0x2,
- GS_SCENARIO_G = 0x3,
- GS_SCENARIO_C = 0x4,
- SPRITE_EN = 0x5,
-} VGT_GS_MODE_TYPE;
-typedef enum VGT_GS_CUT_MODE {
- GS_CUT_1024 = 0x0,
- GS_CUT_512 = 0x1,
- GS_CUT_256 = 0x2,
- GS_CUT_128 = 0x3,
-} VGT_GS_CUT_MODE;
-typedef enum VGT_GS_OUTPRIM_TYPE {
- POINTLIST = 0x0,
- LINESTRIP = 0x1,
- TRISTRIP = 0x2,
-} VGT_GS_OUTPRIM_TYPE;
-typedef enum VGT_CACHE_INVALID_MODE {
- VC_ONLY = 0x0,
- TC_ONLY = 0x1,
- VC_AND_TC = 0x2,
-} VGT_CACHE_INVALID_MODE;
-typedef enum VGT_TESS_TYPE {
- TESS_ISOLINE = 0x0,
- TESS_TRIANGLE = 0x1,
- TESS_QUAD = 0x2,
-} VGT_TESS_TYPE;
-typedef enum VGT_TESS_PARTITION {
- PART_INTEGER = 0x0,
- PART_POW2 = 0x1,
- PART_FRAC_ODD = 0x2,
- PART_FRAC_EVEN = 0x3,
-} VGT_TESS_PARTITION;
-typedef enum VGT_TESS_TOPOLOGY {
- OUTPUT_POINT = 0x0,
- OUTPUT_LINE = 0x1,
- OUTPUT_TRIANGLE_CW = 0x2,
- OUTPUT_TRIANGLE_CCW = 0x3,
-} VGT_TESS_TOPOLOGY;
-typedef enum VGT_RDREQ_POLICY {
- VGT_POLICY_LRU = 0x0,
- VGT_POLICY_STREAM = 0x1,
-} VGT_RDREQ_POLICY;
-typedef enum VGT_DIST_MODE {
- NO_DIST = 0x0,
- PATCHES = 0x1,
- DONUTS = 0x2,
-} VGT_DIST_MODE;
-typedef enum VGT_STAGES_LS_EN {
- LS_STAGE_OFF = 0x0,
- LS_STAGE_ON = 0x1,
- CS_STAGE_ON = 0x2,
- RESERVED_LS = 0x3,
-} VGT_STAGES_LS_EN;
-typedef enum VGT_STAGES_HS_EN {
- HS_STAGE_OFF = 0x0,
- HS_STAGE_ON = 0x1,
-} VGT_STAGES_HS_EN;
-typedef enum VGT_STAGES_ES_EN {
- ES_STAGE_OFF = 0x0,
- ES_STAGE_DS = 0x1,
- ES_STAGE_REAL = 0x2,
- RESERVED_ES = 0x3,
-} VGT_STAGES_ES_EN;
-typedef enum VGT_STAGES_GS_EN {
- GS_STAGE_OFF = 0x0,
- GS_STAGE_ON = 0x1,
-} VGT_STAGES_GS_EN;
-typedef enum VGT_STAGES_VS_EN {
- VS_STAGE_REAL = 0x0,
- VS_STAGE_DS = 0x1,
- VS_STAGE_COPY_SHADER = 0x2,
- RESERVED_VS = 0x3,
-} VGT_STAGES_VS_EN;
-typedef enum VGT_PERFCOUNT_SELECT {
- vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE = 0x0,
- vgt_perf_VGT_SPI_ESVERT_VALID = 0x1,
- vgt_perf_VGT_SPI_ESVERT_EOV = 0x2,
- vgt_perf_VGT_SPI_ESVERT_STALLED = 0x3,
- vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY = 0x4,
- vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE = 0x5,
- vgt_perf_VGT_SPI_ESVERT_STATIC = 0x6,
- vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT = 0x7,
- vgt_perf_VGT_SPI_ESTHREAD_SEND = 0x8,
- vgt_perf_VGT_SPI_GSPRIM_VALID = 0x9,
- vgt_perf_VGT_SPI_GSPRIM_EOV = 0xa,
- vgt_perf_VGT_SPI_GSPRIM_CONT = 0xb,
- vgt_perf_VGT_SPI_GSPRIM_STALLED = 0xc,
- vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY = 0xd,
- vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE = 0xe,
- vgt_perf_VGT_SPI_GSPRIM_STATIC = 0xf,
- vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE = 0x10,
- vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT = 0x11,
- vgt_perf_VGT_SPI_GSTHREAD_SEND = 0x12,
- vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE = 0x13,
- vgt_perf_VGT_SPI_VSVERT_SEND = 0x14,
- vgt_perf_VGT_SPI_VSVERT_EOV = 0x15,
- vgt_perf_VGT_SPI_VSVERT_STALLED = 0x16,
- vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY = 0x17,
- vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE = 0x18,
- vgt_perf_VGT_SPI_VSVERT_STATIC = 0x19,
- vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT = 0x1a,
- vgt_perf_VGT_SPI_VSTHREAD_SEND = 0x1b,
- vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE = 0x1c,
- vgt_perf_VGT_PA_CLIPV_SEND = 0x1d,
- vgt_perf_VGT_PA_CLIPV_FIRSTVERT = 0x1e,
- vgt_perf_VGT_PA_CLIPV_STALLED = 0x1f,
- vgt_perf_VGT_PA_CLIPV_STARVED_BUSY = 0x20,
- vgt_perf_VGT_PA_CLIPV_STARVED_IDLE = 0x21,
- vgt_perf_VGT_PA_CLIPV_STATIC = 0x22,
- vgt_perf_VGT_PA_CLIPP_SEND = 0x23,
- vgt_perf_VGT_PA_CLIPP_EOP = 0x24,
- vgt_perf_VGT_PA_CLIPP_IS_EVENT = 0x25,
- vgt_perf_VGT_PA_CLIPP_NULL_PRIM = 0x26,
- vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT = 0x27,
- vgt_perf_VGT_PA_CLIPP_STALLED = 0x28,
- vgt_perf_VGT_PA_CLIPP_STARVED_BUSY = 0x29,
- vgt_perf_VGT_PA_CLIPP_STARVED_IDLE = 0x2a,
- vgt_perf_VGT_PA_CLIPP_STATIC = 0x2b,
- vgt_perf_VGT_PA_CLIPS_SEND = 0x2c,
- vgt_perf_VGT_PA_CLIPS_STALLED = 0x2d,
- vgt_perf_VGT_PA_CLIPS_STARVED_BUSY = 0x2e,
- vgt_perf_VGT_PA_CLIPS_STARVED_IDLE = 0x2f,
- vgt_perf_VGT_PA_CLIPS_STATIC = 0x30,
- vgt_perf_vsvert_ds_send = 0x31,
- vgt_perf_vsvert_api_send = 0x32,
- vgt_perf_hs_tif_stall = 0x33,
- vgt_perf_hs_input_stall = 0x34,
- vgt_perf_hs_interface_stall = 0x35,
- vgt_perf_hs_tfm_stall = 0x36,
- vgt_perf_te11_starved = 0x37,
- vgt_perf_gs_event_stall = 0x38,
- vgt_perf_vgt_pa_clipp_send_not_event = 0x39,
- vgt_perf_vgt_pa_clipp_valid_prim = 0x3a,
- vgt_perf_reused_es_indices = 0x3b,
- vgt_perf_vs_cache_hits = 0x3c,
- vgt_perf_gs_cache_hits = 0x3d,
- vgt_perf_ds_cache_hits = 0x3e,
- vgt_perf_total_cache_hits = 0x3f,
- vgt_perf_vgt_busy = 0x40,
- vgt_perf_vgt_gs_busy = 0x41,
- vgt_perf_esvert_stalled_es_tbl = 0x42,
- vgt_perf_esvert_stalled_gs_tbl = 0x43,
- vgt_perf_esvert_stalled_gs_event = 0x44,
- vgt_perf_esvert_stalled_gsprim = 0x45,
- vgt_perf_gsprim_stalled_es_tbl = 0x46,
- vgt_perf_gsprim_stalled_gs_tbl = 0x47,
- vgt_perf_gsprim_stalled_gs_event = 0x48,
- vgt_perf_gsprim_stalled_esvert = 0x49,
- vgt_perf_esthread_stalled_es_rb_full = 0x4a,
- vgt_perf_esthread_stalled_spi_bp = 0x4b,
- vgt_perf_counters_avail_stalled = 0x4c,
- vgt_perf_gs_rb_space_avail_stalled = 0x4d,
- vgt_perf_gs_issue_rtr_stalled = 0x4e,
- vgt_perf_gsthread_stalled = 0x4f,
- vgt_perf_strmout_stalled = 0x50,
- vgt_perf_wait_for_es_done_stalled = 0x51,
- vgt_perf_cm_stalled_by_gog = 0x52,
- vgt_perf_cm_reading_stalled = 0x53,
- vgt_perf_cm_stalled_by_gsfetch_done = 0x54,
- vgt_perf_gog_vs_tbl_stalled = 0x55,
- vgt_perf_gog_out_indx_stalled = 0x56,
- vgt_perf_gog_out_prim_stalled = 0x57,
- vgt_perf_waveid_stalled = 0x58,
- vgt_perf_gog_busy = 0x59,
- vgt_perf_reused_vs_indices = 0x5a,
- vgt_perf_sclk_reg_vld_event = 0x5b,
- vgt_perf_vs_conflicting_indices = 0x5c,
- vgt_perf_sclk_core_vld_event = 0x5d,
- vgt_perf_hswave_stalled = 0x5e,
- vgt_perf_sclk_gs_vld_event = 0x5f,
- vgt_perf_VGT_SPI_LSVERT_VALID = 0x60,
- vgt_perf_VGT_SPI_LSVERT_EOV = 0x61,
- vgt_perf_VGT_SPI_LSVERT_STALLED = 0x62,
- vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY = 0x63,
- vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE = 0x64,
- vgt_perf_VGT_SPI_LSVERT_STATIC = 0x65,
- vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE = 0x66,
- vgt_perf_VGT_SPI_LSWAVE_IS_EVENT = 0x67,
- vgt_perf_VGT_SPI_LSWAVE_SEND = 0x68,
- vgt_perf_VGT_SPI_HSVERT_VALID = 0x69,
- vgt_perf_VGT_SPI_HSVERT_EOV = 0x6a,
- vgt_perf_VGT_SPI_HSVERT_STALLED = 0x6b,
- vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY = 0x6c,
- vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE = 0x6d,
- vgt_perf_VGT_SPI_HSVERT_STATIC = 0x6e,
- vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE = 0x6f,
- vgt_perf_VGT_SPI_HSWAVE_IS_EVENT = 0x70,
- vgt_perf_VGT_SPI_HSWAVE_SEND = 0x71,
- vgt_perf_ds_prims = 0x72,
- vgt_perf_ls_thread_groups = 0x73,
- vgt_perf_hs_thread_groups = 0x74,
- vgt_perf_es_thread_groups = 0x75,
- vgt_perf_vs_thread_groups = 0x76,
- vgt_perf_ls_done_latency = 0x77,
- vgt_perf_hs_done_latency = 0x78,
- vgt_perf_es_done_latency = 0x79,
- vgt_perf_gs_done_latency = 0x7a,
- vgt_perf_vgt_hs_busy = 0x7b,
- vgt_perf_vgt_te11_busy = 0x7c,
- vgt_perf_ls_flush = 0x7d,
- vgt_perf_hs_flush = 0x7e,
- vgt_perf_es_flush = 0x7f,
- vgt_perf_vgt_pa_clipp_eopg = 0x80,
- vgt_perf_ls_done = 0x81,
- vgt_perf_hs_done = 0x82,
- vgt_perf_es_done = 0x83,
- vgt_perf_gs_done = 0x84,
- vgt_perf_vsfetch_done = 0x85,
- vgt_perf_gs_done_received = 0x86,
- vgt_perf_es_ring_high_water_mark = 0x87,
- vgt_perf_gs_ring_high_water_mark = 0x88,
- vgt_perf_vs_table_high_water_mark = 0x89,
- vgt_perf_hs_tgs_active_high_water_mark = 0x8a,
- vgt_perf_pa_clipp_dealloc = 0x8b,
- vgt_perf_cut_mem_flush_stalled = 0x8c,
- vgt_perf_vsvert_work_received = 0x8d,
- vgt_perf_vgt_pa_clipp_starved_after_work = 0x8e,
- vgt_perf_te11_con_starved_after_work = 0x8f,
- vgt_perf_hs_waiting_on_ls_done_stall = 0x90,
- vgt_spi_vsvert_valid = 0x91,
-} VGT_PERFCOUNT_SELECT;
-typedef enum IA_PERFCOUNT_SELECT {
- ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE = 0x0,
- ia_perf_dma_data_fifo_full = 0x1,
- ia_perf_RESERVED1 = 0x2,
- ia_perf_RESERVED2 = 0x3,
- ia_perf_RESERVED3 = 0x4,
- ia_perf_RESERVED4 = 0x5,
- ia_perf_RESERVED5 = 0x6,
- ia_perf_MC_LAT_BIN_0 = 0x7,
- ia_perf_MC_LAT_BIN_1 = 0x8,
- ia_perf_MC_LAT_BIN_2 = 0x9,
- ia_perf_MC_LAT_BIN_3 = 0xa,
- ia_perf_MC_LAT_BIN_4 = 0xb,
- ia_perf_MC_LAT_BIN_5 = 0xc,
- ia_perf_MC_LAT_BIN_6 = 0xd,
- ia_perf_MC_LAT_BIN_7 = 0xe,
- ia_perf_ia_busy = 0xf,
- ia_perf_ia_sclk_reg_vld_event = 0x10,
- ia_perf_RESERVED6 = 0x11,
- ia_perf_ia_sclk_core_vld_event = 0x12,
- ia_perf_RESERVED7 = 0x13,
- ia_perf_ia_dma_return = 0x14,
- ia_perf_ia_stalled = 0x15,
- ia_perf_shift_starved_pipe0_event = 0x16,
- ia_perf_shift_starved_pipe1_event = 0x17,
-} IA_PERFCOUNT_SELECT;
-typedef enum WD_PERFCOUNT_SELECT {
- wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 0x0,
- wd_perf_RBIU_DR_FIFO_STARVED = 0x1,
- wd_perf_RBIU_DR_FIFO_STALLED = 0x2,
- wd_perf_RBIU_DI_FIFO_STARVED = 0x3,
- wd_perf_RBIU_DI_FIFO_STALLED = 0x4,
- wd_perf_wd_busy = 0x5,
- wd_perf_wd_sclk_reg_vld_event = 0x6,
- wd_perf_wd_sclk_input_vld_event = 0x7,
- wd_perf_wd_sclk_core_vld_event = 0x8,
- wd_perf_wd_stalled = 0x9,
- wd_perf_inside_tf_bin_0 = 0xa,
- wd_perf_inside_tf_bin_1 = 0xb,
- wd_perf_inside_tf_bin_2 = 0xc,
- wd_perf_inside_tf_bin_3 = 0xd,
- wd_perf_inside_tf_bin_4 = 0xe,
- wd_perf_inside_tf_bin_5 = 0xf,
- wd_perf_inside_tf_bin_6 = 0x10,
- wd_perf_inside_tf_bin_7 = 0x11,
- wd_perf_inside_tf_bin_8 = 0x12,
- wd_perf_tfreq_lat_bin_0 = 0x13,
- wd_perf_tfreq_lat_bin_1 = 0x14,
- wd_perf_tfreq_lat_bin_2 = 0x15,
- wd_perf_tfreq_lat_bin_3 = 0x16,
- wd_perf_tfreq_lat_bin_4 = 0x17,
- wd_perf_tfreq_lat_bin_5 = 0x18,
- wd_perf_tfreq_lat_bin_6 = 0x19,
- wd_perf_tfreq_lat_bin_7 = 0x1a,
- wd_starved_on_hs_done = 0x1b,
- wd_perf_se0_hs_done_latency = 0x1c,
- wd_perf_se1_hs_done_latency = 0x1d,
- wd_perf_se2_hs_done_latency = 0x1e,
- wd_perf_se3_hs_done_latency = 0x1f,
- wd_perf_hs_done_se0 = 0x20,
- wd_perf_hs_done_se1 = 0x21,
- wd_perf_hs_done_se2 = 0x22,
- wd_perf_hs_done_se3 = 0x23,
- wd_perf_null_patches = 0x24,
-} WD_PERFCOUNT_SELECT;
-typedef enum WD_IA_DRAW_TYPE {
- WD_IA_DRAW_TYPE_DI_MM0 = 0x0,
- WD_IA_DRAW_TYPE_DI_MM1 = 0x1,
- WD_IA_DRAW_TYPE_EVENT_INIT = 0x2,
- WD_IA_DRAW_TYPE_EVENT_ADDR = 0x3,
- WD_IA_DRAW_TYPE_MIN_INDX = 0x4,
- WD_IA_DRAW_TYPE_MAX_INDX = 0x5,
- WD_IA_DRAW_TYPE_INDX_OFF = 0x6,
- WD_IA_DRAW_TYPE_IMM_DATA = 0x7,
-} WD_IA_DRAW_TYPE;
-typedef enum WD_IA_DRAW_SOURCE {
- WD_IA_DRAW_SOURCE_DMA = 0x0,
- WD_IA_DRAW_SOURCE_IMMD = 0x1,
- WD_IA_DRAW_SOURCE_AUTO = 0x2,
- WD_IA_DRAW_SOURCE_OPAQ = 0x3,
-} WD_IA_DRAW_SOURCE;
-#define GSTHREADID_SIZE 0x2
-typedef enum DebugBlockId {
- DBG_BLOCK_ID_RESERVED = 0x0,
- DBG_BLOCK_ID_DBG = 0x1,
- DBG_BLOCK_ID_VMC = 0x2,
- DBG_BLOCK_ID_PDMA = 0x3,
- DBG_BLOCK_ID_CG = 0x4,
- DBG_BLOCK_ID_SRBM = 0x5,
- DBG_BLOCK_ID_GRBM = 0x6,
- DBG_BLOCK_ID_RLC = 0x7,
- DBG_BLOCK_ID_CSC = 0x8,
- DBG_BLOCK_ID_SEM = 0x9,
- DBG_BLOCK_ID_IH = 0xa,
- DBG_BLOCK_ID_SC = 0xb,
- DBG_BLOCK_ID_SQ = 0xc,
- DBG_BLOCK_ID_UVDU = 0xd,
- DBG_BLOCK_ID_SQA = 0xe,
- DBG_BLOCK_ID_SDMA0 = 0xf,
- DBG_BLOCK_ID_SDMA1 = 0x10,
- DBG_BLOCK_ID_SPIM = 0x11,
- DBG_BLOCK_ID_GDS = 0x12,
- DBG_BLOCK_ID_VC0 = 0x13,
- DBG_BLOCK_ID_VC1 = 0x14,
- DBG_BLOCK_ID_PA0 = 0x15,
- DBG_BLOCK_ID_PA1 = 0x16,
- DBG_BLOCK_ID_CP0 = 0x17,
- DBG_BLOCK_ID_CP1 = 0x18,
- DBG_BLOCK_ID_CP2 = 0x19,
- DBG_BLOCK_ID_XBR = 0x1a,
- DBG_BLOCK_ID_UVDM = 0x1b,
- DBG_BLOCK_ID_VGT0 = 0x1c,
- DBG_BLOCK_ID_VGT1 = 0x1d,
- DBG_BLOCK_ID_IA = 0x1e,
- DBG_BLOCK_ID_SXM0 = 0x1f,
- DBG_BLOCK_ID_SXM1 = 0x20,
- DBG_BLOCK_ID_SCT0 = 0x21,
- DBG_BLOCK_ID_SCT1 = 0x22,
- DBG_BLOCK_ID_SPM0 = 0x23,
- DBG_BLOCK_ID_SPM1 = 0x24,
- DBG_BLOCK_ID_UNUSED0 = 0x25,
- DBG_BLOCK_ID_UNUSED1 = 0x26,
- DBG_BLOCK_ID_TCAA = 0x27,
- DBG_BLOCK_ID_TCAB = 0x28,
- DBG_BLOCK_ID_TCCA = 0x29,
- DBG_BLOCK_ID_TCCB = 0x2a,
- DBG_BLOCK_ID_MCC0 = 0x2b,
- DBG_BLOCK_ID_MCC1 = 0x2c,
- DBG_BLOCK_ID_MCC2 = 0x2d,
- DBG_BLOCK_ID_MCC3 = 0x2e,
- DBG_BLOCK_ID_SXS0 = 0x2f,
- DBG_BLOCK_ID_SXS1 = 0x30,
- DBG_BLOCK_ID_SXS2 = 0x31,
- DBG_BLOCK_ID_SXS3 = 0x32,
- DBG_BLOCK_ID_SXS4 = 0x33,
- DBG_BLOCK_ID_SXS5 = 0x34,
- DBG_BLOCK_ID_SXS6 = 0x35,
- DBG_BLOCK_ID_SXS7 = 0x36,
- DBG_BLOCK_ID_SXS8 = 0x37,
- DBG_BLOCK_ID_SXS9 = 0x38,
- DBG_BLOCK_ID_BCI0 = 0x39,
- DBG_BLOCK_ID_BCI1 = 0x3a,
- DBG_BLOCK_ID_BCI2 = 0x3b,
- DBG_BLOCK_ID_BCI3 = 0x3c,
- DBG_BLOCK_ID_MCB = 0x3d,
- DBG_BLOCK_ID_UNUSED6 = 0x3e,
- DBG_BLOCK_ID_SQA00 = 0x3f,
- DBG_BLOCK_ID_SQA01 = 0x40,
- DBG_BLOCK_ID_SQA02 = 0x41,
- DBG_BLOCK_ID_SQA10 = 0x42,
- DBG_BLOCK_ID_SQA11 = 0x43,
- DBG_BLOCK_ID_SQA12 = 0x44,
- DBG_BLOCK_ID_UNUSED7 = 0x45,
- DBG_BLOCK_ID_UNUSED8 = 0x46,
- DBG_BLOCK_ID_SQB00 = 0x47,
- DBG_BLOCK_ID_SQB01 = 0x48,
- DBG_BLOCK_ID_SQB10 = 0x49,
- DBG_BLOCK_ID_SQB11 = 0x4a,
- DBG_BLOCK_ID_SQ00 = 0x4b,
- DBG_BLOCK_ID_SQ01 = 0x4c,
- DBG_BLOCK_ID_SQ10 = 0x4d,
- DBG_BLOCK_ID_SQ11 = 0x4e,
- DBG_BLOCK_ID_CB00 = 0x4f,
- DBG_BLOCK_ID_CB01 = 0x50,
- DBG_BLOCK_ID_CB02 = 0x51,
- DBG_BLOCK_ID_CB03 = 0x52,
- DBG_BLOCK_ID_CB04 = 0x53,
- DBG_BLOCK_ID_UNUSED9 = 0x54,
- DBG_BLOCK_ID_UNUSED10 = 0x55,
- DBG_BLOCK_ID_UNUSED11 = 0x56,
- DBG_BLOCK_ID_CB10 = 0x57,
- DBG_BLOCK_ID_CB11 = 0x58,
- DBG_BLOCK_ID_CB12 = 0x59,
- DBG_BLOCK_ID_CB13 = 0x5a,
- DBG_BLOCK_ID_CB14 = 0x5b,
- DBG_BLOCK_ID_UNUSED12 = 0x5c,
- DBG_BLOCK_ID_UNUSED13 = 0x5d,
- DBG_BLOCK_ID_UNUSED14 = 0x5e,
- DBG_BLOCK_ID_TCP0 = 0x5f,
- DBG_BLOCK_ID_TCP1 = 0x60,
- DBG_BLOCK_ID_TCP2 = 0x61,
- DBG_BLOCK_ID_TCP3 = 0x62,
- DBG_BLOCK_ID_TCP4 = 0x63,
- DBG_BLOCK_ID_TCP5 = 0x64,
- DBG_BLOCK_ID_TCP6 = 0x65,
- DBG_BLOCK_ID_TCP7 = 0x66,
- DBG_BLOCK_ID_TCP8 = 0x67,
- DBG_BLOCK_ID_TCP9 = 0x68,
- DBG_BLOCK_ID_TCP10 = 0x69,
- DBG_BLOCK_ID_TCP11 = 0x6a,
- DBG_BLOCK_ID_TCP12 = 0x6b,
- DBG_BLOCK_ID_TCP13 = 0x6c,
- DBG_BLOCK_ID_TCP14 = 0x6d,
- DBG_BLOCK_ID_TCP15 = 0x6e,
- DBG_BLOCK_ID_TCP16 = 0x6f,
- DBG_BLOCK_ID_TCP17 = 0x70,
- DBG_BLOCK_ID_TCP18 = 0x71,
- DBG_BLOCK_ID_TCP19 = 0x72,
- DBG_BLOCK_ID_TCP20 = 0x73,
- DBG_BLOCK_ID_TCP21 = 0x74,
- DBG_BLOCK_ID_TCP22 = 0x75,
- DBG_BLOCK_ID_TCP23 = 0x76,
- DBG_BLOCK_ID_TCP_RESERVED0 = 0x77,
- DBG_BLOCK_ID_TCP_RESERVED1 = 0x78,
- DBG_BLOCK_ID_TCP_RESERVED2 = 0x79,
- DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a,
- DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b,
- DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c,
- DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d,
- DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e,
- DBG_BLOCK_ID_DB00 = 0x7f,
- DBG_BLOCK_ID_DB01 = 0x80,
- DBG_BLOCK_ID_DB02 = 0x81,
- DBG_BLOCK_ID_DB03 = 0x82,
- DBG_BLOCK_ID_DB04 = 0x83,
- DBG_BLOCK_ID_UNUSED15 = 0x84,
- DBG_BLOCK_ID_UNUSED16 = 0x85,
- DBG_BLOCK_ID_UNUSED17 = 0x86,
- DBG_BLOCK_ID_DB10 = 0x87,
- DBG_BLOCK_ID_DB11 = 0x88,
- DBG_BLOCK_ID_DB12 = 0x89,
- DBG_BLOCK_ID_DB13 = 0x8a,
- DBG_BLOCK_ID_DB14 = 0x8b,
- DBG_BLOCK_ID_UNUSED18 = 0x8c,
- DBG_BLOCK_ID_UNUSED19 = 0x8d,
- DBG_BLOCK_ID_UNUSED20 = 0x8e,
- DBG_BLOCK_ID_TCC0 = 0x8f,
- DBG_BLOCK_ID_TCC1 = 0x90,
- DBG_BLOCK_ID_TCC2 = 0x91,
- DBG_BLOCK_ID_TCC3 = 0x92,
- DBG_BLOCK_ID_TCC4 = 0x93,
- DBG_BLOCK_ID_TCC5 = 0x94,
- DBG_BLOCK_ID_TCC6 = 0x95,
- DBG_BLOCK_ID_TCC7 = 0x96,
- DBG_BLOCK_ID_SPS00 = 0x97,
- DBG_BLOCK_ID_SPS01 = 0x98,
- DBG_BLOCK_ID_SPS02 = 0x99,
- DBG_BLOCK_ID_SPS10 = 0x9a,
- DBG_BLOCK_ID_SPS11 = 0x9b,
- DBG_BLOCK_ID_SPS12 = 0x9c,
- DBG_BLOCK_ID_UNUSED21 = 0x9d,
- DBG_BLOCK_ID_UNUSED22 = 0x9e,
- DBG_BLOCK_ID_TA00 = 0x9f,
- DBG_BLOCK_ID_TA01 = 0xa0,
- DBG_BLOCK_ID_TA02 = 0xa1,
- DBG_BLOCK_ID_TA03 = 0xa2,
- DBG_BLOCK_ID_TA04 = 0xa3,
- DBG_BLOCK_ID_TA05 = 0xa4,
- DBG_BLOCK_ID_TA06 = 0xa5,
- DBG_BLOCK_ID_TA07 = 0xa6,
- DBG_BLOCK_ID_TA08 = 0xa7,
- DBG_BLOCK_ID_TA09 = 0xa8,
- DBG_BLOCK_ID_TA0A = 0xa9,
- DBG_BLOCK_ID_TA0B = 0xaa,
- DBG_BLOCK_ID_UNUSED23 = 0xab,
- DBG_BLOCK_ID_UNUSED24 = 0xac,
- DBG_BLOCK_ID_UNUSED25 = 0xad,
- DBG_BLOCK_ID_UNUSED26 = 0xae,
- DBG_BLOCK_ID_TA10 = 0xaf,
- DBG_BLOCK_ID_TA11 = 0xb0,
- DBG_BLOCK_ID_TA12 = 0xb1,
- DBG_BLOCK_ID_TA13 = 0xb2,
- DBG_BLOCK_ID_TA14 = 0xb3,
- DBG_BLOCK_ID_TA15 = 0xb4,
- DBG_BLOCK_ID_TA16 = 0xb5,
- DBG_BLOCK_ID_TA17 = 0xb6,
- DBG_BLOCK_ID_TA18 = 0xb7,
- DBG_BLOCK_ID_TA19 = 0xb8,
- DBG_BLOCK_ID_TA1A = 0xb9,
- DBG_BLOCK_ID_TA1B = 0xba,
- DBG_BLOCK_ID_UNUSED27 = 0xbb,
- DBG_BLOCK_ID_UNUSED28 = 0xbc,
- DBG_BLOCK_ID_UNUSED29 = 0xbd,
- DBG_BLOCK_ID_UNUSED30 = 0xbe,
- DBG_BLOCK_ID_TD00 = 0xbf,
- DBG_BLOCK_ID_TD01 = 0xc0,
- DBG_BLOCK_ID_TD02 = 0xc1,
- DBG_BLOCK_ID_TD03 = 0xc2,
- DBG_BLOCK_ID_TD04 = 0xc3,
- DBG_BLOCK_ID_TD05 = 0xc4,
- DBG_BLOCK_ID_TD06 = 0xc5,
- DBG_BLOCK_ID_TD07 = 0xc6,
- DBG_BLOCK_ID_TD08 = 0xc7,
- DBG_BLOCK_ID_TD09 = 0xc8,
- DBG_BLOCK_ID_TD0A = 0xc9,
- DBG_BLOCK_ID_TD0B = 0xca,
- DBG_BLOCK_ID_UNUSED31 = 0xcb,
- DBG_BLOCK_ID_UNUSED32 = 0xcc,
- DBG_BLOCK_ID_UNUSED33 = 0xcd,
- DBG_BLOCK_ID_UNUSED34 = 0xce,
- DBG_BLOCK_ID_TD10 = 0xcf,
- DBG_BLOCK_ID_TD11 = 0xd0,
- DBG_BLOCK_ID_TD12 = 0xd1,
- DBG_BLOCK_ID_TD13 = 0xd2,
- DBG_BLOCK_ID_TD14 = 0xd3,
- DBG_BLOCK_ID_TD15 = 0xd4,
- DBG_BLOCK_ID_TD16 = 0xd5,
- DBG_BLOCK_ID_TD17 = 0xd6,
- DBG_BLOCK_ID_TD18 = 0xd7,
- DBG_BLOCK_ID_TD19 = 0xd8,
- DBG_BLOCK_ID_TD1A = 0xd9,
- DBG_BLOCK_ID_TD1B = 0xda,
- DBG_BLOCK_ID_UNUSED35 = 0xdb,
- DBG_BLOCK_ID_UNUSED36 = 0xdc,
- DBG_BLOCK_ID_UNUSED37 = 0xdd,
- DBG_BLOCK_ID_UNUSED38 = 0xde,
- DBG_BLOCK_ID_LDS00 = 0xdf,
- DBG_BLOCK_ID_LDS01 = 0xe0,
- DBG_BLOCK_ID_LDS02 = 0xe1,
- DBG_BLOCK_ID_LDS03 = 0xe2,
- DBG_BLOCK_ID_LDS04 = 0xe3,
- DBG_BLOCK_ID_LDS05 = 0xe4,
- DBG_BLOCK_ID_LDS06 = 0xe5,
- DBG_BLOCK_ID_LDS07 = 0xe6,
- DBG_BLOCK_ID_LDS08 = 0xe7,
- DBG_BLOCK_ID_LDS09 = 0xe8,
- DBG_BLOCK_ID_LDS0A = 0xe9,
- DBG_BLOCK_ID_LDS0B = 0xea,
- DBG_BLOCK_ID_UNUSED39 = 0xeb,
- DBG_BLOCK_ID_UNUSED40 = 0xec,
- DBG_BLOCK_ID_UNUSED41 = 0xed,
- DBG_BLOCK_ID_UNUSED42 = 0xee,
- DBG_BLOCK_ID_LDS10 = 0xef,
- DBG_BLOCK_ID_LDS11 = 0xf0,
- DBG_BLOCK_ID_LDS12 = 0xf1,
- DBG_BLOCK_ID_LDS13 = 0xf2,
- DBG_BLOCK_ID_LDS14 = 0xf3,
- DBG_BLOCK_ID_LDS15 = 0xf4,
- DBG_BLOCK_ID_LDS16 = 0xf5,
- DBG_BLOCK_ID_LDS17 = 0xf6,
- DBG_BLOCK_ID_LDS18 = 0xf7,
- DBG_BLOCK_ID_LDS19 = 0xf8,
- DBG_BLOCK_ID_LDS1A = 0xf9,
- DBG_BLOCK_ID_LDS1B = 0xfa,
- DBG_BLOCK_ID_UNUSED43 = 0xfb,
- DBG_BLOCK_ID_UNUSED44 = 0xfc,
- DBG_BLOCK_ID_UNUSED45 = 0xfd,
- DBG_BLOCK_ID_UNUSED46 = 0xfe,
-} DebugBlockId;
-typedef enum DebugBlockId_BY2 {
- DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
- DBG_BLOCK_ID_VMC_BY2 = 0x1,
- DBG_BLOCK_ID_UNUSED0_BY2 = 0x2,
- DBG_BLOCK_ID_GRBM_BY2 = 0x3,
- DBG_BLOCK_ID_CSC_BY2 = 0x4,
- DBG_BLOCK_ID_IH_BY2 = 0x5,
- DBG_BLOCK_ID_SQ_BY2 = 0x6,
- DBG_BLOCK_ID_UVD_BY2 = 0x7,
- DBG_BLOCK_ID_SDMA0_BY2 = 0x8,
- DBG_BLOCK_ID_SPIM_BY2 = 0x9,
- DBG_BLOCK_ID_VC0_BY2 = 0xa,
- DBG_BLOCK_ID_PA_BY2 = 0xb,
- DBG_BLOCK_ID_CP0_BY2 = 0xc,
- DBG_BLOCK_ID_CP2_BY2 = 0xd,
- DBG_BLOCK_ID_PC0_BY2 = 0xe,
- DBG_BLOCK_ID_BCI0_BY2 = 0xf,
- DBG_BLOCK_ID_SXM0_BY2 = 0x10,
- DBG_BLOCK_ID_SCT0_BY2 = 0x11,
- DBG_BLOCK_ID_SPM0_BY2 = 0x12,
- DBG_BLOCK_ID_BCI2_BY2 = 0x13,
- DBG_BLOCK_ID_TCA_BY2 = 0x14,
- DBG_BLOCK_ID_TCCA_BY2 = 0x15,
- DBG_BLOCK_ID_MCC_BY2 = 0x16,
- DBG_BLOCK_ID_MCC2_BY2 = 0x17,
- DBG_BLOCK_ID_MCD_BY2 = 0x18,
- DBG_BLOCK_ID_MCD2_BY2 = 0x19,
- DBG_BLOCK_ID_MCD4_BY2 = 0x1a,
- DBG_BLOCK_ID_MCB_BY2 = 0x1b,
- DBG_BLOCK_ID_SQA_BY2 = 0x1c,
- DBG_BLOCK_ID_SQA02_BY2 = 0x1d,
- DBG_BLOCK_ID_SQA11_BY2 = 0x1e,
- DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f,
- DBG_BLOCK_ID_SQB_BY2 = 0x20,
- DBG_BLOCK_ID_SQB10_BY2 = 0x21,
- DBG_BLOCK_ID_UNUSED10_BY2 = 0x22,
- DBG_BLOCK_ID_UNUSED12_BY2 = 0x23,
- DBG_BLOCK_ID_CB_BY2 = 0x24,
- DBG_BLOCK_ID_CB02_BY2 = 0x25,
- DBG_BLOCK_ID_CB10_BY2 = 0x26,
- DBG_BLOCK_ID_CB12_BY2 = 0x27,
- DBG_BLOCK_ID_SXS_BY2 = 0x28,
- DBG_BLOCK_ID_SXS2_BY2 = 0x29,
- DBG_BLOCK_ID_SXS4_BY2 = 0x2a,
- DBG_BLOCK_ID_SXS6_BY2 = 0x2b,
- DBG_BLOCK_ID_DB_BY2 = 0x2c,
- DBG_BLOCK_ID_DB02_BY2 = 0x2d,
- DBG_BLOCK_ID_DB10_BY2 = 0x2e,
- DBG_BLOCK_ID_DB12_BY2 = 0x2f,
- DBG_BLOCK_ID_TCP_BY2 = 0x30,
- DBG_BLOCK_ID_TCP2_BY2 = 0x31,
- DBG_BLOCK_ID_TCP4_BY2 = 0x32,
- DBG_BLOCK_ID_TCP6_BY2 = 0x33,
- DBG_BLOCK_ID_TCP8_BY2 = 0x34,
- DBG_BLOCK_ID_TCP10_BY2 = 0x35,
- DBG_BLOCK_ID_TCP12_BY2 = 0x36,
- DBG_BLOCK_ID_TCP14_BY2 = 0x37,
- DBG_BLOCK_ID_TCP16_BY2 = 0x38,
- DBG_BLOCK_ID_TCP18_BY2 = 0x39,
- DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
- DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
- DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
- DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
- DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
- DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
- DBG_BLOCK_ID_TCC_BY2 = 0x40,
- DBG_BLOCK_ID_TCC2_BY2 = 0x41,
- DBG_BLOCK_ID_TCC4_BY2 = 0x42,
- DBG_BLOCK_ID_TCC6_BY2 = 0x43,
- DBG_BLOCK_ID_SPS_BY2 = 0x44,
- DBG_BLOCK_ID_SPS02_BY2 = 0x45,
- DBG_BLOCK_ID_SPS11_BY2 = 0x46,
- DBG_BLOCK_ID_UNUSED14_BY2 = 0x47,
- DBG_BLOCK_ID_TA_BY2 = 0x48,
- DBG_BLOCK_ID_TA02_BY2 = 0x49,
- DBG_BLOCK_ID_TA04_BY2 = 0x4a,
- DBG_BLOCK_ID_TA06_BY2 = 0x4b,
- DBG_BLOCK_ID_TA08_BY2 = 0x4c,
- DBG_BLOCK_ID_TA0A_BY2 = 0x4d,
- DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e,
- DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f,
- DBG_BLOCK_ID_TA10_BY2 = 0x50,
- DBG_BLOCK_ID_TA12_BY2 = 0x51,
- DBG_BLOCK_ID_TA14_BY2 = 0x52,
- DBG_BLOCK_ID_TA16_BY2 = 0x53,
- DBG_BLOCK_ID_TA18_BY2 = 0x54,
- DBG_BLOCK_ID_TA1A_BY2 = 0x55,
- DBG_BLOCK_ID_UNUSED24_BY2 = 0x56,
- DBG_BLOCK_ID_UNUSED26_BY2 = 0x57,
- DBG_BLOCK_ID_TD_BY2 = 0x58,
- DBG_BLOCK_ID_TD02_BY2 = 0x59,
- DBG_BLOCK_ID_TD04_BY2 = 0x5a,
- DBG_BLOCK_ID_TD06_BY2 = 0x5b,
- DBG_BLOCK_ID_TD08_BY2 = 0x5c,
- DBG_BLOCK_ID_TD0A_BY2 = 0x5d,
- DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e,
- DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f,
- DBG_BLOCK_ID_TD10_BY2 = 0x60,
- DBG_BLOCK_ID_TD12_BY2 = 0x61,
- DBG_BLOCK_ID_TD14_BY2 = 0x62,
- DBG_BLOCK_ID_TD16_BY2 = 0x63,
- DBG_BLOCK_ID_TD18_BY2 = 0x64,
- DBG_BLOCK_ID_TD1A_BY2 = 0x65,
- DBG_BLOCK_ID_UNUSED32_BY2 = 0x66,
- DBG_BLOCK_ID_UNUSED34_BY2 = 0x67,
- DBG_BLOCK_ID_LDS_BY2 = 0x68,
- DBG_BLOCK_ID_LDS02_BY2 = 0x69,
- DBG_BLOCK_ID_LDS04_BY2 = 0x6a,
- DBG_BLOCK_ID_LDS06_BY2 = 0x6b,
- DBG_BLOCK_ID_LDS08_BY2 = 0x6c,
- DBG_BLOCK_ID_LDS0A_BY2 = 0x6d,
- DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e,
- DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f,
- DBG_BLOCK_ID_LDS10_BY2 = 0x70,
- DBG_BLOCK_ID_LDS12_BY2 = 0x71,
- DBG_BLOCK_ID_LDS14_BY2 = 0x72,
- DBG_BLOCK_ID_LDS16_BY2 = 0x73,
- DBG_BLOCK_ID_LDS18_BY2 = 0x74,
- DBG_BLOCK_ID_LDS1A_BY2 = 0x75,
- DBG_BLOCK_ID_UNUSED40_BY2 = 0x76,
- DBG_BLOCK_ID_UNUSED42_BY2 = 0x77,
-} DebugBlockId_BY2;
-typedef enum DebugBlockId_BY4 {
- DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
- DBG_BLOCK_ID_UNUSED0_BY4 = 0x1,
- DBG_BLOCK_ID_CSC_BY4 = 0x2,
- DBG_BLOCK_ID_SQ_BY4 = 0x3,
- DBG_BLOCK_ID_SDMA0_BY4 = 0x4,
- DBG_BLOCK_ID_VC0_BY4 = 0x5,
- DBG_BLOCK_ID_CP0_BY4 = 0x6,
- DBG_BLOCK_ID_UNUSED1_BY4 = 0x7,
- DBG_BLOCK_ID_SXM0_BY4 = 0x8,
- DBG_BLOCK_ID_SPM0_BY4 = 0x9,
- DBG_BLOCK_ID_TCAA_BY4 = 0xa,
- DBG_BLOCK_ID_MCC_BY4 = 0xb,
- DBG_BLOCK_ID_MCD_BY4 = 0xc,
- DBG_BLOCK_ID_MCD4_BY4 = 0xd,
- DBG_BLOCK_ID_SQA_BY4 = 0xe,
- DBG_BLOCK_ID_SQA11_BY4 = 0xf,
- DBG_BLOCK_ID_SQB_BY4 = 0x10,
- DBG_BLOCK_ID_UNUSED10_BY4 = 0x11,
- DBG_BLOCK_ID_CB_BY4 = 0x12,
- DBG_BLOCK_ID_CB10_BY4 = 0x13,
- DBG_BLOCK_ID_SXS_BY4 = 0x14,
- DBG_BLOCK_ID_SXS4_BY4 = 0x15,
- DBG_BLOCK_ID_DB_BY4 = 0x16,
- DBG_BLOCK_ID_DB10_BY4 = 0x17,
- DBG_BLOCK_ID_TCP_BY4 = 0x18,
- DBG_BLOCK_ID_TCP4_BY4 = 0x19,
- DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
- DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
- DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
- DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
- DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
- DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
- DBG_BLOCK_ID_TCC_BY4 = 0x20,
- DBG_BLOCK_ID_TCC4_BY4 = 0x21,
- DBG_BLOCK_ID_SPS_BY4 = 0x22,
- DBG_BLOCK_ID_SPS11_BY4 = 0x23,
- DBG_BLOCK_ID_TA_BY4 = 0x24,
- DBG_BLOCK_ID_TA04_BY4 = 0x25,
- DBG_BLOCK_ID_TA08_BY4 = 0x26,
- DBG_BLOCK_ID_UNUSED20_BY4 = 0x27,
- DBG_BLOCK_ID_TA10_BY4 = 0x28,
- DBG_BLOCK_ID_TA14_BY4 = 0x29,
- DBG_BLOCK_ID_TA18_BY4 = 0x2a,
- DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b,
- DBG_BLOCK_ID_TD_BY4 = 0x2c,
- DBG_BLOCK_ID_TD04_BY4 = 0x2d,
- DBG_BLOCK_ID_TD08_BY4 = 0x2e,
- DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f,
- DBG_BLOCK_ID_TD10_BY4 = 0x30,
- DBG_BLOCK_ID_TD14_BY4 = 0x31,
- DBG_BLOCK_ID_TD18_BY4 = 0x32,
- DBG_BLOCK_ID_UNUSED32_BY4 = 0x33,
- DBG_BLOCK_ID_LDS_BY4 = 0x34,
- DBG_BLOCK_ID_LDS04_BY4 = 0x35,
- DBG_BLOCK_ID_LDS08_BY4 = 0x36,
- DBG_BLOCK_ID_UNUSED36_BY4 = 0x37,
- DBG_BLOCK_ID_LDS10_BY4 = 0x38,
- DBG_BLOCK_ID_LDS14_BY4 = 0x39,
- DBG_BLOCK_ID_LDS18_BY4 = 0x3a,
- DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b,
-} DebugBlockId_BY4;
-typedef enum DebugBlockId_BY8 {
- DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
- DBG_BLOCK_ID_CSC_BY8 = 0x1,
- DBG_BLOCK_ID_SDMA0_BY8 = 0x2,
- DBG_BLOCK_ID_CP0_BY8 = 0x3,
- DBG_BLOCK_ID_SXM0_BY8 = 0x4,
- DBG_BLOCK_ID_TCA_BY8 = 0x5,
- DBG_BLOCK_ID_MCD_BY8 = 0x6,
- DBG_BLOCK_ID_SQA_BY8 = 0x7,
- DBG_BLOCK_ID_SQB_BY8 = 0x8,
- DBG_BLOCK_ID_CB_BY8 = 0x9,
- DBG_BLOCK_ID_SXS_BY8 = 0xa,
- DBG_BLOCK_ID_DB_BY8 = 0xb,
- DBG_BLOCK_ID_TCP_BY8 = 0xc,
- DBG_BLOCK_ID_TCP8_BY8 = 0xd,
- DBG_BLOCK_ID_TCP16_BY8 = 0xe,
- DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
- DBG_BLOCK_ID_TCC_BY8 = 0x10,
- DBG_BLOCK_ID_SPS_BY8 = 0x11,
- DBG_BLOCK_ID_TA_BY8 = 0x12,
- DBG_BLOCK_ID_TA08_BY8 = 0x13,
- DBG_BLOCK_ID_TA10_BY8 = 0x14,
- DBG_BLOCK_ID_TA18_BY8 = 0x15,
- DBG_BLOCK_ID_TD_BY8 = 0x16,
- DBG_BLOCK_ID_TD08_BY8 = 0x17,
- DBG_BLOCK_ID_TD10_BY8 = 0x18,
- DBG_BLOCK_ID_TD18_BY8 = 0x19,
- DBG_BLOCK_ID_LDS_BY8 = 0x1a,
- DBG_BLOCK_ID_LDS08_BY8 = 0x1b,
- DBG_BLOCK_ID_LDS10_BY8 = 0x1c,
- DBG_BLOCK_ID_LDS18_BY8 = 0x1d,
-} DebugBlockId_BY8;
-typedef enum DebugBlockId_BY16 {
- DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
- DBG_BLOCK_ID_SDMA0_BY16 = 0x1,
- DBG_BLOCK_ID_SXM_BY16 = 0x2,
- DBG_BLOCK_ID_MCD_BY16 = 0x3,
- DBG_BLOCK_ID_SQB_BY16 = 0x4,
- DBG_BLOCK_ID_SXS_BY16 = 0x5,
- DBG_BLOCK_ID_TCP_BY16 = 0x6,
- DBG_BLOCK_ID_TCP16_BY16 = 0x7,
- DBG_BLOCK_ID_TCC_BY16 = 0x8,
- DBG_BLOCK_ID_TA_BY16 = 0x9,
- DBG_BLOCK_ID_TA10_BY16 = 0xa,
- DBG_BLOCK_ID_TD_BY16 = 0xb,
- DBG_BLOCK_ID_TD10_BY16 = 0xc,
- DBG_BLOCK_ID_LDS_BY16 = 0xd,
- DBG_BLOCK_ID_LDS10_BY16 = 0xe,
-} DebugBlockId_BY16;
-typedef enum SurfaceEndian {
- ENDIAN_NONE = 0x0,
- ENDIAN_8IN16 = 0x1,
- ENDIAN_8IN32 = 0x2,
- ENDIAN_8IN64 = 0x3,
-} SurfaceEndian;
-typedef enum ArrayMode {
- ARRAY_LINEAR_GENERAL = 0x0,
- ARRAY_LINEAR_ALIGNED = 0x1,
- ARRAY_1D_TILED_THIN1 = 0x2,
- ARRAY_1D_TILED_THICK = 0x3,
- ARRAY_2D_TILED_THIN1 = 0x4,
- ARRAY_PRT_TILED_THIN1 = 0x5,
- ARRAY_PRT_2D_TILED_THIN1 = 0x6,
- ARRAY_2D_TILED_THICK = 0x7,
- ARRAY_2D_TILED_XTHICK = 0x8,
- ARRAY_PRT_TILED_THICK = 0x9,
- ARRAY_PRT_2D_TILED_THICK = 0xa,
- ARRAY_PRT_3D_TILED_THIN1 = 0xb,
- ARRAY_3D_TILED_THIN1 = 0xc,
- ARRAY_3D_TILED_THICK = 0xd,
- ARRAY_3D_TILED_XTHICK = 0xe,
- ARRAY_PRT_3D_TILED_THICK = 0xf,
-} ArrayMode;
-typedef enum PipeTiling {
- CONFIG_1_PIPE = 0x0,
- CONFIG_2_PIPE = 0x1,
- CONFIG_4_PIPE = 0x2,
- CONFIG_8_PIPE = 0x3,
-} PipeTiling;
-typedef enum BankTiling {
- CONFIG_4_BANK = 0x0,
- CONFIG_8_BANK = 0x1,
-} BankTiling;
-typedef enum GroupInterleave {
- CONFIG_256B_GROUP = 0x0,
- CONFIG_512B_GROUP = 0x1,
-} GroupInterleave;
-typedef enum RowTiling {
- CONFIG_1KB_ROW = 0x0,
- CONFIG_2KB_ROW = 0x1,
- CONFIG_4KB_ROW = 0x2,
- CONFIG_8KB_ROW = 0x3,
- CONFIG_1KB_ROW_OPT = 0x4,
- CONFIG_2KB_ROW_OPT = 0x5,
- CONFIG_4KB_ROW_OPT = 0x6,
- CONFIG_8KB_ROW_OPT = 0x7,
-} RowTiling;
-typedef enum BankSwapBytes {
- CONFIG_128B_SWAPS = 0x0,
- CONFIG_256B_SWAPS = 0x1,
- CONFIG_512B_SWAPS = 0x2,
- CONFIG_1KB_SWAPS = 0x3,
-} BankSwapBytes;
-typedef enum SampleSplitBytes {
- CONFIG_1KB_SPLIT = 0x0,
- CONFIG_2KB_SPLIT = 0x1,
- CONFIG_4KB_SPLIT = 0x2,
- CONFIG_8KB_SPLIT = 0x3,
-} SampleSplitBytes;
-typedef enum NumPipes {
- ADDR_CONFIG_1_PIPE = 0x0,
- ADDR_CONFIG_2_PIPE = 0x1,
- ADDR_CONFIG_4_PIPE = 0x2,
- ADDR_CONFIG_8_PIPE = 0x3,
-} NumPipes;
-typedef enum PipeInterleaveSize {
- ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
- ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
-} PipeInterleaveSize;
-typedef enum BankInterleaveSize {
- ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
- ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
- ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
- ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
-} BankInterleaveSize;
-typedef enum NumShaderEngines {
- ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
- ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
-} NumShaderEngines;
-typedef enum ShaderEngineTileSize {
- ADDR_CONFIG_SE_TILE_16 = 0x0,
- ADDR_CONFIG_SE_TILE_32 = 0x1,
-} ShaderEngineTileSize;
-typedef enum NumGPUs {
- ADDR_CONFIG_1_GPU = 0x0,
- ADDR_CONFIG_2_GPU = 0x1,
- ADDR_CONFIG_4_GPU = 0x2,
-} NumGPUs;
-typedef enum MultiGPUTileSize {
- ADDR_CONFIG_GPU_TILE_16 = 0x0,
- ADDR_CONFIG_GPU_TILE_32 = 0x1,
- ADDR_CONFIG_GPU_TILE_64 = 0x2,
- ADDR_CONFIG_GPU_TILE_128 = 0x3,
-} MultiGPUTileSize;
-typedef enum RowSize {
- ADDR_CONFIG_1KB_ROW = 0x0,
- ADDR_CONFIG_2KB_ROW = 0x1,
- ADDR_CONFIG_4KB_ROW = 0x2,
-} RowSize;
-typedef enum NumLowerPipes {
- ADDR_CONFIG_1_LOWER_PIPES = 0x0,
- ADDR_CONFIG_2_LOWER_PIPES = 0x1,
-} NumLowerPipes;
-typedef enum ColorTransform {
- DCC_CT_AUTO = 0x0,
- DCC_CT_NONE = 0x1,
- ABGR_TO_A_BG_G_RB = 0x2,
- BGRA_TO_BG_G_RB_A = 0x3,
-} ColorTransform;
-typedef enum CompareRef {
- REF_NEVER = 0x0,
- REF_LESS = 0x1,
- REF_EQUAL = 0x2,
- REF_LEQUAL = 0x3,
- REF_GREATER = 0x4,
- REF_NOTEQUAL = 0x5,
- REF_GEQUAL = 0x6,
- REF_ALWAYS = 0x7,
-} CompareRef;
-typedef enum ReadSize {
- READ_256_BITS = 0x0,
- READ_512_BITS = 0x1,
-} ReadSize;
-typedef enum DepthFormat {
- DEPTH_INVALID = 0x0,
- DEPTH_16 = 0x1,
- DEPTH_X8_24 = 0x2,
- DEPTH_8_24 = 0x3,
- DEPTH_X8_24_FLOAT = 0x4,
- DEPTH_8_24_FLOAT = 0x5,
- DEPTH_32_FLOAT = 0x6,
- DEPTH_X24_8_32_FLOAT = 0x7,
-} DepthFormat;
-typedef enum ZFormat {
- Z_INVALID = 0x0,
- Z_16 = 0x1,
- Z_24 = 0x2,
- Z_32_FLOAT = 0x3,
-} ZFormat;
-typedef enum StencilFormat {
- STENCIL_INVALID = 0x0,
- STENCIL_8 = 0x1,
-} StencilFormat;
-typedef enum CmaskMode {
- CMASK_CLEAR_NONE = 0x0,
- CMASK_CLEAR_ONE = 0x1,
- CMASK_CLEAR_ALL = 0x2,
- CMASK_ANY_EXPANDED = 0x3,
- CMASK_ALPHA0_FRAG1 = 0x4,
- CMASK_ALPHA0_FRAG2 = 0x5,
- CMASK_ALPHA0_FRAG4 = 0x6,
- CMASK_ALPHA0_FRAGS = 0x7,
- CMASK_ALPHA1_FRAG1 = 0x8,
- CMASK_ALPHA1_FRAG2 = 0x9,
- CMASK_ALPHA1_FRAG4 = 0xa,
- CMASK_ALPHA1_FRAGS = 0xb,
- CMASK_ALPHAX_FRAG1 = 0xc,
- CMASK_ALPHAX_FRAG2 = 0xd,
- CMASK_ALPHAX_FRAG4 = 0xe,
- CMASK_ALPHAX_FRAGS = 0xf,
-} CmaskMode;
-typedef enum QuadExportFormat {
- EXPORT_UNUSED = 0x0,
- EXPORT_32_R = 0x1,
- EXPORT_32_GR = 0x2,
- EXPORT_32_AR = 0x3,
- EXPORT_FP16_ABGR = 0x4,
- EXPORT_UNSIGNED16_ABGR = 0x5,
- EXPORT_SIGNED16_ABGR = 0x6,
- EXPORT_32_ABGR = 0x7,
- EXPORT_32BPP_8PIX = 0x8,
- EXPORT_16_16_UNSIGNED_8PIX = 0x9,
- EXPORT_16_16_SIGNED_8PIX = 0xa,
- EXPORT_16_16_FLOAT_8PIX = 0xb,
-} QuadExportFormat;
-typedef enum QuadExportFormatOld {
- EXPORT_4P_32BPC_ABGR = 0x0,
- EXPORT_4P_16BPC_ABGR = 0x1,
- EXPORT_4P_32BPC_GR = 0x2,
- EXPORT_4P_32BPC_AR = 0x3,
- EXPORT_2P_32BPC_ABGR = 0x4,
- EXPORT_8P_32BPC_R = 0x5,
-} QuadExportFormatOld;
-typedef enum ColorFormat {
- COLOR_INVALID = 0x0,
- COLOR_8 = 0x1,
- COLOR_16 = 0x2,
- COLOR_8_8 = 0x3,
- COLOR_32 = 0x4,
- COLOR_16_16 = 0x5,
- COLOR_10_11_11 = 0x6,
- COLOR_11_11_10 = 0x7,
- COLOR_10_10_10_2 = 0x8,
- COLOR_2_10_10_10 = 0x9,
- COLOR_8_8_8_8 = 0xa,
- COLOR_32_32 = 0xb,
- COLOR_16_16_16_16 = 0xc,
- COLOR_RESERVED_13 = 0xd,
- COLOR_32_32_32_32 = 0xe,
- COLOR_RESERVED_15 = 0xf,
- COLOR_5_6_5 = 0x10,
- COLOR_1_5_5_5 = 0x11,
- COLOR_5_5_5_1 = 0x12,
- COLOR_4_4_4_4 = 0x13,
- COLOR_8_24 = 0x14,
- COLOR_24_8 = 0x15,
- COLOR_X24_8_32_FLOAT = 0x16,
- COLOR_RESERVED_23 = 0x17,
- COLOR_RESERVED_24 = 0x18,
- COLOR_RESERVED_25 = 0x19,
- COLOR_RESERVED_26 = 0x1a,
- COLOR_RESERVED_27 = 0x1b,
- COLOR_RESERVED_28 = 0x1c,
- COLOR_RESERVED_29 = 0x1d,
- COLOR_RESERVED_30 = 0x1e,
-} ColorFormat;
-typedef enum SurfaceFormat {
- FMT_INVALID = 0x0,
- FMT_8 = 0x1,
- FMT_16 = 0x2,
- FMT_8_8 = 0x3,
- FMT_32 = 0x4,
- FMT_16_16 = 0x5,
- FMT_10_11_11 = 0x6,
- FMT_11_11_10 = 0x7,
- FMT_10_10_10_2 = 0x8,
- FMT_2_10_10_10 = 0x9,
- FMT_8_8_8_8 = 0xa,
- FMT_32_32 = 0xb,
- FMT_16_16_16_16 = 0xc,
- FMT_32_32_32 = 0xd,
- FMT_32_32_32_32 = 0xe,
- FMT_RESERVED_4 = 0xf,
- FMT_5_6_5 = 0x10,
- FMT_1_5_5_5 = 0x11,
- FMT_5_5_5_1 = 0x12,
- FMT_4_4_4_4 = 0x13,
- FMT_8_24 = 0x14,
- FMT_24_8 = 0x15,
- FMT_X24_8_32_FLOAT = 0x16,
- FMT_RESERVED_33 = 0x17,
- FMT_11_11_10_FLOAT = 0x18,
- FMT_16_FLOAT = 0x19,
- FMT_32_FLOAT = 0x1a,
- FMT_16_16_FLOAT = 0x1b,
- FMT_8_24_FLOAT = 0x1c,
- FMT_24_8_FLOAT = 0x1d,
- FMT_32_32_FLOAT = 0x1e,
- FMT_10_11_11_FLOAT = 0x1f,
- FMT_16_16_16_16_FLOAT = 0x20,
- FMT_3_3_2 = 0x21,
- FMT_6_5_5 = 0x22,
- FMT_32_32_32_32_FLOAT = 0x23,
- FMT_RESERVED_36 = 0x24,
- FMT_1 = 0x25,
- FMT_1_REVERSED = 0x26,
- FMT_GB_GR = 0x27,
- FMT_BG_RG = 0x28,
- FMT_32_AS_8 = 0x29,
- FMT_32_AS_8_8 = 0x2a,
- FMT_5_9_9_9_SHAREDEXP = 0x2b,
- FMT_8_8_8 = 0x2c,
- FMT_16_16_16 = 0x2d,
- FMT_16_16_16_FLOAT = 0x2e,
- FMT_4_4 = 0x2f,
- FMT_32_32_32_FLOAT = 0x30,
- FMT_BC1 = 0x31,
- FMT_BC2 = 0x32,
- FMT_BC3 = 0x33,
- FMT_BC4 = 0x34,
- FMT_BC5 = 0x35,
- FMT_BC6 = 0x36,
- FMT_BC7 = 0x37,
- FMT_32_AS_32_32_32_32 = 0x38,
- FMT_APC3 = 0x39,
- FMT_APC4 = 0x3a,
- FMT_APC5 = 0x3b,
- FMT_APC6 = 0x3c,
- FMT_APC7 = 0x3d,
- FMT_CTX1 = 0x3e,
- FMT_RESERVED_63 = 0x3f,
-} SurfaceFormat;
-typedef enum BUF_DATA_FORMAT {
- BUF_DATA_FORMAT_INVALID = 0x0,
- BUF_DATA_FORMAT_8 = 0x1,
- BUF_DATA_FORMAT_16 = 0x2,
- BUF_DATA_FORMAT_8_8 = 0x3,
- BUF_DATA_FORMAT_32 = 0x4,
- BUF_DATA_FORMAT_16_16 = 0x5,
- BUF_DATA_FORMAT_10_11_11 = 0x6,
- BUF_DATA_FORMAT_11_11_10 = 0x7,
- BUF_DATA_FORMAT_10_10_10_2 = 0x8,
- BUF_DATA_FORMAT_2_10_10_10 = 0x9,
- BUF_DATA_FORMAT_8_8_8_8 = 0xa,
- BUF_DATA_FORMAT_32_32 = 0xb,
- BUF_DATA_FORMAT_16_16_16_16 = 0xc,
- BUF_DATA_FORMAT_32_32_32 = 0xd,
- BUF_DATA_FORMAT_32_32_32_32 = 0xe,
- BUF_DATA_FORMAT_RESERVED_15 = 0xf,
-} BUF_DATA_FORMAT;
-typedef enum IMG_DATA_FORMAT {
- IMG_DATA_FORMAT_INVALID = 0x0,
- IMG_DATA_FORMAT_8 = 0x1,
- IMG_DATA_FORMAT_16 = 0x2,
- IMG_DATA_FORMAT_8_8 = 0x3,
- IMG_DATA_FORMAT_32 = 0x4,
- IMG_DATA_FORMAT_16_16 = 0x5,
- IMG_DATA_FORMAT_10_11_11 = 0x6,
- IMG_DATA_FORMAT_11_11_10 = 0x7,
- IMG_DATA_FORMAT_10_10_10_2 = 0x8,
- IMG_DATA_FORMAT_2_10_10_10 = 0x9,
- IMG_DATA_FORMAT_8_8_8_8 = 0xa,
- IMG_DATA_FORMAT_32_32 = 0xb,
- IMG_DATA_FORMAT_16_16_16_16 = 0xc,
- IMG_DATA_FORMAT_32_32_32 = 0xd,
- IMG_DATA_FORMAT_32_32_32_32 = 0xe,
- IMG_DATA_FORMAT_16_AS_32_32 = 0xf,
- IMG_DATA_FORMAT_5_6_5 = 0x10,
- IMG_DATA_FORMAT_1_5_5_5 = 0x11,
- IMG_DATA_FORMAT_5_5_5_1 = 0x12,
- IMG_DATA_FORMAT_4_4_4_4 = 0x13,
- IMG_DATA_FORMAT_8_24 = 0x14,
- IMG_DATA_FORMAT_24_8 = 0x15,
- IMG_DATA_FORMAT_X24_8_32 = 0x16,
- IMG_DATA_FORMAT_8_AS_8_8_8_8 = 0x17,
- IMG_DATA_FORMAT_ETC2_RGB = 0x18,
- IMG_DATA_FORMAT_ETC2_RGBA = 0x19,
- IMG_DATA_FORMAT_ETC2_R = 0x1a,
- IMG_DATA_FORMAT_ETC2_RG = 0x1b,
- IMG_DATA_FORMAT_ETC2_RGBA1 = 0x1c,
- IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
- IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
- IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
- IMG_DATA_FORMAT_GB_GR = 0x20,
- IMG_DATA_FORMAT_BG_RG = 0x21,
- IMG_DATA_FORMAT_5_9_9_9 = 0x22,
- IMG_DATA_FORMAT_BC1 = 0x23,
- IMG_DATA_FORMAT_BC2 = 0x24,
- IMG_DATA_FORMAT_BC3 = 0x25,
- IMG_DATA_FORMAT_BC4 = 0x26,
- IMG_DATA_FORMAT_BC5 = 0x27,
- IMG_DATA_FORMAT_BC6 = 0x28,
- IMG_DATA_FORMAT_BC7 = 0x29,
- IMG_DATA_FORMAT_16_AS_16_16_16_16 = 0x2a,
- IMG_DATA_FORMAT_16_AS_32_32_32_32 = 0x2b,
- IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
- IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
- IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
- IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
- IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
- IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
- IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
- IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
- IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
- IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
- IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
- IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
- IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
- IMG_DATA_FORMAT_4_4 = 0x39,
- IMG_DATA_FORMAT_6_5_5 = 0x3a,
- IMG_DATA_FORMAT_1 = 0x3b,
- IMG_DATA_FORMAT_1_REVERSED = 0x3c,
- IMG_DATA_FORMAT_8_AS_32 = 0x3d,
- IMG_DATA_FORMAT_8_AS_32_32 = 0x3e,
- IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
-} IMG_DATA_FORMAT;
-typedef enum BUF_NUM_FORMAT {
- BUF_NUM_FORMAT_UNORM = 0x0,
- BUF_NUM_FORMAT_SNORM = 0x1,
- BUF_NUM_FORMAT_USCALED = 0x2,
- BUF_NUM_FORMAT_SSCALED = 0x3,
- BUF_NUM_FORMAT_UINT = 0x4,
- BUF_NUM_FORMAT_SINT = 0x5,
- BUF_NUM_FORMAT_RESERVED_6 = 0x6,
- BUF_NUM_FORMAT_FLOAT = 0x7,
-} BUF_NUM_FORMAT;
-typedef enum IMG_NUM_FORMAT {
- IMG_NUM_FORMAT_UNORM = 0x0,
- IMG_NUM_FORMAT_SNORM = 0x1,
- IMG_NUM_FORMAT_USCALED = 0x2,
- IMG_NUM_FORMAT_SSCALED = 0x3,
- IMG_NUM_FORMAT_UINT = 0x4,
- IMG_NUM_FORMAT_SINT = 0x5,
- IMG_NUM_FORMAT_RESERVED_6 = 0x6,
- IMG_NUM_FORMAT_FLOAT = 0x7,
- IMG_NUM_FORMAT_RESERVED_8 = 0x8,
- IMG_NUM_FORMAT_SRGB = 0x9,
- IMG_NUM_FORMAT_RESERVED_10 = 0xa,
- IMG_NUM_FORMAT_RESERVED_11 = 0xb,
- IMG_NUM_FORMAT_RESERVED_12 = 0xc,
- IMG_NUM_FORMAT_RESERVED_13 = 0xd,
- IMG_NUM_FORMAT_RESERVED_14 = 0xe,
- IMG_NUM_FORMAT_RESERVED_15 = 0xf,
-} IMG_NUM_FORMAT;
-typedef enum TileType {
- ARRAY_COLOR_TILE = 0x0,
- ARRAY_DEPTH_TILE = 0x1,
-} TileType;
-typedef enum NonDispTilingOrder {
- ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
- ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
-} NonDispTilingOrder;
-typedef enum MicroTileMode {
- ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
- ADDR_SURF_THIN_MICRO_TILING = 0x1,
- ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
- ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
- ADDR_SURF_THICK_MICRO_TILING = 0x4,
-} MicroTileMode;
-typedef enum TileSplit {
- ADDR_SURF_TILE_SPLIT_64B = 0x0,
- ADDR_SURF_TILE_SPLIT_128B = 0x1,
- ADDR_SURF_TILE_SPLIT_256B = 0x2,
- ADDR_SURF_TILE_SPLIT_512B = 0x3,
- ADDR_SURF_TILE_SPLIT_1KB = 0x4,
- ADDR_SURF_TILE_SPLIT_2KB = 0x5,
- ADDR_SURF_TILE_SPLIT_4KB = 0x6,
-} TileSplit;
-typedef enum SampleSplit {
- ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
- ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
- ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
- ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
-} SampleSplit;
-typedef enum PipeConfig {
- ADDR_SURF_P2 = 0x0,
- ADDR_SURF_P2_RESERVED0 = 0x1,
- ADDR_SURF_P2_RESERVED1 = 0x2,
- ADDR_SURF_P2_RESERVED2 = 0x3,
- ADDR_SURF_P4_8x16 = 0x4,
- ADDR_SURF_P4_16x16 = 0x5,
- ADDR_SURF_P4_16x32 = 0x6,
- ADDR_SURF_P4_32x32 = 0x7,
- ADDR_SURF_P8_16x16_8x16 = 0x8,
- ADDR_SURF_P8_16x32_8x16 = 0x9,
- ADDR_SURF_P8_32x32_8x16 = 0xa,
- ADDR_SURF_P8_16x32_16x16 = 0xb,
- ADDR_SURF_P8_32x32_16x16 = 0xc,
- ADDR_SURF_P8_32x32_16x32 = 0xd,
- ADDR_SURF_P8_32x64_32x32 = 0xe,
- ADDR_SURF_P8_RESERVED0 = 0xf,
- ADDR_SURF_P16_32x32_8x16 = 0x10,
- ADDR_SURF_P16_32x32_16x16 = 0x11,
-} PipeConfig;
-typedef enum NumBanks {
- ADDR_SURF_2_BANK = 0x0,
- ADDR_SURF_4_BANK = 0x1,
- ADDR_SURF_8_BANK = 0x2,
- ADDR_SURF_16_BANK = 0x3,
-} NumBanks;
-typedef enum BankWidth {
- ADDR_SURF_BANK_WIDTH_1 = 0x0,
- ADDR_SURF_BANK_WIDTH_2 = 0x1,
- ADDR_SURF_BANK_WIDTH_4 = 0x2,
- ADDR_SURF_BANK_WIDTH_8 = 0x3,
-} BankWidth;
-typedef enum BankHeight {
- ADDR_SURF_BANK_HEIGHT_1 = 0x0,
- ADDR_SURF_BANK_HEIGHT_2 = 0x1,
- ADDR_SURF_BANK_HEIGHT_4 = 0x2,
- ADDR_SURF_BANK_HEIGHT_8 = 0x3,
-} BankHeight;
-typedef enum BankWidthHeight {
- ADDR_SURF_BANK_WH_1 = 0x0,
- ADDR_SURF_BANK_WH_2 = 0x1,
- ADDR_SURF_BANK_WH_4 = 0x2,
- ADDR_SURF_BANK_WH_8 = 0x3,
-} BankWidthHeight;
-typedef enum MacroTileAspect {
- ADDR_SURF_MACRO_ASPECT_1 = 0x0,
- ADDR_SURF_MACRO_ASPECT_2 = 0x1,
- ADDR_SURF_MACRO_ASPECT_4 = 0x2,
- ADDR_SURF_MACRO_ASPECT_8 = 0x3,
-} MacroTileAspect;
-typedef enum GATCL1RequestType {
- GATCL1_TYPE_NORMAL = 0x0,
- GATCL1_TYPE_SHOOTDOWN = 0x1,
- GATCL1_TYPE_BYPASS = 0x2,
-} GATCL1RequestType;
-typedef enum TCC_CACHE_POLICIES {
- TCC_CACHE_POLICY_LRU = 0x0,
- TCC_CACHE_POLICY_STREAM = 0x1,
-} TCC_CACHE_POLICIES;
-typedef enum MTYPE {
- MTYPE_NC_NV = 0x0,
- MTYPE_NC = 0x1,
- MTYPE_CC = 0x2,
- MTYPE_UC = 0x3,
-} MTYPE;
-typedef enum PERFMON_COUNTER_MODE {
- PERFMON_COUNTER_MODE_ACCUM = 0x0,
- PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
- PERFMON_COUNTER_MODE_MAX = 0x2,
- PERFMON_COUNTER_MODE_DIRTY = 0x3,
- PERFMON_COUNTER_MODE_SAMPLE = 0x4,
- PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
- PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
- PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
- PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
- PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
- PERFMON_COUNTER_MODE_RESERVED = 0xf,
-} PERFMON_COUNTER_MODE;
-typedef enum PERFMON_SPM_MODE {
- PERFMON_SPM_MODE_OFF = 0x0,
- PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
- PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
- PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
- PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
- PERFMON_SPM_MODE_RESERVED_5 = 0x5,
- PERFMON_SPM_MODE_RESERVED_6 = 0x6,
- PERFMON_SPM_MODE_RESERVED_7 = 0x7,
- PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
- PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
- PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
-} PERFMON_SPM_MODE;
-typedef enum SurfaceTiling {
- ARRAY_LINEAR = 0x0,
- ARRAY_TILED = 0x1,
-} SurfaceTiling;
-typedef enum SurfaceArray {
- ARRAY_1D = 0x0,
- ARRAY_2D = 0x1,
- ARRAY_3D = 0x2,
- ARRAY_3D_SLICE = 0x3,
-} SurfaceArray;
-typedef enum ColorArray {
- ARRAY_2D_ALT_COLOR = 0x0,
- ARRAY_2D_COLOR = 0x1,
- ARRAY_3D_SLICE_COLOR = 0x3,
-} ColorArray;
-typedef enum DepthArray {
- ARRAY_2D_ALT_DEPTH = 0x0,
- ARRAY_2D_DEPTH = 0x1,
-} DepthArray;
-typedef enum ENUM_NUM_SIMD_PER_CU {
- NUM_SIMD_PER_CU = 0x4,
-} ENUM_NUM_SIMD_PER_CU;
-typedef enum MEM_PWR_FORCE_CTRL {
- NO_FORCE_REQUEST = 0x0,
- FORCE_LIGHT_SLEEP_REQUEST = 0x1,
- FORCE_DEEP_SLEEP_REQUEST = 0x2,
- FORCE_SHUT_DOWN_REQUEST = 0x3,
-} MEM_PWR_FORCE_CTRL;
-typedef enum MEM_PWR_FORCE_CTRL2 {
- NO_FORCE_REQ = 0x0,
- FORCE_LIGHT_SLEEP_REQ = 0x1,
-} MEM_PWR_FORCE_CTRL2;
-typedef enum MEM_PWR_DIS_CTRL {
- ENABLE_MEM_PWR_CTRL = 0x0,
- DISABLE_MEM_PWR_CTRL = 0x1,
-} MEM_PWR_DIS_CTRL;
-typedef enum MEM_PWR_SEL_CTRL {
- DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
- DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
- DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
-} MEM_PWR_SEL_CTRL;
-typedef enum MEM_PWR_SEL_CTRL2 {
- DYNAMIC_DEEP_SLEEP_EN = 0x0,
- DYNAMIC_LIGHT_SLEEP_EN = 0x1,
-} MEM_PWR_SEL_CTRL2;
-
-#endif /* GFX_8_1_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h
deleted file mode 100644
index 397705a6b..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h
+++ /dev/null
@@ -1,21368 +0,0 @@
-/*
- * GFX_8_1 Register documentation
- *
- * Copyright (C) 2014 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef GFX_8_1_SH_MASK_H
-#define GFX_8_1_SH_MASK_H
-
-#define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
-#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
-#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
-#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
-#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
-#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
-#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
-#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
-#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
-#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
-#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE_MASK 0x2
-#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE__SHIFT 0x1
-#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK 0x7c
-#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT 0x2
-#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD_MASK 0x1
-#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD__SHIFT 0x0
-#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
-#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
-#define CB_COLOR_CONTROL__MODE_MASK 0x70
-#define CB_COLOR_CONTROL__MODE__SHIFT 0x4
-#define CB_COLOR_CONTROL__ROP3_MASK 0xff0000
-#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10
-#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x1f
-#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
-#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0xe0
-#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
-#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
-#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
-#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
-#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
-#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
-#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
-#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
-#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
-#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
-#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
-#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000
-#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e
-#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000
-#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f
-#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x1f
-#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
-#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0xe0
-#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
-#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
-#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
-#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
-#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
-#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
-#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
-#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
-#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
-#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
-#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
-#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000
-#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e
-#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000
-#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f
-#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x1f
-#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
-#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0xe0
-#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
-#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
-#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
-#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
-#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
-#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
-#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
-#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
-#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
-#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
-#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
-#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000
-#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e
-#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000
-#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f
-#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x1f
-#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
-#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0xe0
-#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
-#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
-#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
-#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
-#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
-#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
-#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
-#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
-#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
-#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
-#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
-#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000
-#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e
-#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000
-#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f
-#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x1f
-#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
-#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0xe0
-#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
-#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
-#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
-#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
-#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
-#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
-#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
-#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
-#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
-#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
-#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
-#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000
-#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e
-#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000
-#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f
-#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x1f
-#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
-#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0xe0
-#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
-#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
-#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
-#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
-#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
-#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
-#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
-#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
-#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
-#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
-#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
-#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000
-#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e
-#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000
-#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f
-#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x1f
-#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
-#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0xe0
-#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
-#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
-#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
-#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
-#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
-#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
-#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
-#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
-#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
-#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
-#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
-#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000
-#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e
-#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000
-#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f
-#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x1f
-#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
-#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0xe0
-#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
-#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
-#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
-#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
-#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
-#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
-#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
-#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
-#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
-#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
-#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
-#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000
-#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e
-#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000
-#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f
-#define CB_COLOR0_BASE__BASE_256B_MASK 0xffffffff
-#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR1_BASE__BASE_256B_MASK 0xffffffff
-#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR2_BASE__BASE_256B_MASK 0xffffffff
-#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR3_BASE__BASE_256B_MASK 0xffffffff
-#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR4_BASE__BASE_256B_MASK 0xffffffff
-#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR5_BASE__BASE_256B_MASK 0xffffffff
-#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR6_BASE__BASE_256B_MASK 0xffffffff
-#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR7_BASE__BASE_256B_MASK 0xffffffff
-#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR0_PITCH__TILE_MAX_MASK 0x7ff
-#define CB_COLOR0_PITCH__TILE_MAX__SHIFT 0x0
-#define CB_COLOR0_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
-#define CB_COLOR0_PITCH__FMASK_TILE_MAX__SHIFT 0x14
-#define CB_COLOR1_PITCH__TILE_MAX_MASK 0x7ff
-#define CB_COLOR1_PITCH__TILE_MAX__SHIFT 0x0
-#define CB_COLOR1_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
-#define CB_COLOR1_PITCH__FMASK_TILE_MAX__SHIFT 0x14
-#define CB_COLOR2_PITCH__TILE_MAX_MASK 0x7ff
-#define CB_COLOR2_PITCH__TILE_MAX__SHIFT 0x0
-#define CB_COLOR2_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
-#define CB_COLOR2_PITCH__FMASK_TILE_MAX__SHIFT 0x14
-#define CB_COLOR3_PITCH__TILE_MAX_MASK 0x7ff
-#define CB_COLOR3_PITCH__TILE_MAX__SHIFT 0x0
-#define CB_COLOR3_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
-#define CB_COLOR3_PITCH__FMASK_TILE_MAX__SHIFT 0x14
-#define CB_COLOR4_PITCH__TILE_MAX_MASK 0x7ff
-#define CB_COLOR4_PITCH__TILE_MAX__SHIFT 0x0
-#define CB_COLOR4_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
-#define CB_COLOR4_PITCH__FMASK_TILE_MAX__SHIFT 0x14
-#define CB_COLOR5_PITCH__TILE_MAX_MASK 0x7ff
-#define CB_COLOR5_PITCH__TILE_MAX__SHIFT 0x0
-#define CB_COLOR5_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
-#define CB_COLOR5_PITCH__FMASK_TILE_MAX__SHIFT 0x14
-#define CB_COLOR6_PITCH__TILE_MAX_MASK 0x7ff
-#define CB_COLOR6_PITCH__TILE_MAX__SHIFT 0x0
-#define CB_COLOR6_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
-#define CB_COLOR6_PITCH__FMASK_TILE_MAX__SHIFT 0x14
-#define CB_COLOR7_PITCH__TILE_MAX_MASK 0x7ff
-#define CB_COLOR7_PITCH__TILE_MAX__SHIFT 0x0
-#define CB_COLOR7_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
-#define CB_COLOR7_PITCH__FMASK_TILE_MAX__SHIFT 0x14
-#define CB_COLOR0_SLICE__TILE_MAX_MASK 0x3fffff
-#define CB_COLOR0_SLICE__TILE_MAX__SHIFT 0x0
-#define CB_COLOR1_SLICE__TILE_MAX_MASK 0x3fffff
-#define CB_COLOR1_SLICE__TILE_MAX__SHIFT 0x0
-#define CB_COLOR2_SLICE__TILE_MAX_MASK 0x3fffff
-#define CB_COLOR2_SLICE__TILE_MAX__SHIFT 0x0
-#define CB_COLOR3_SLICE__TILE_MAX_MASK 0x3fffff
-#define CB_COLOR3_SLICE__TILE_MAX__SHIFT 0x0
-#define CB_COLOR4_SLICE__TILE_MAX_MASK 0x3fffff
-#define CB_COLOR4_SLICE__TILE_MAX__SHIFT 0x0
-#define CB_COLOR5_SLICE__TILE_MAX_MASK 0x3fffff
-#define CB_COLOR5_SLICE__TILE_MAX__SHIFT 0x0
-#define CB_COLOR6_SLICE__TILE_MAX_MASK 0x3fffff
-#define CB_COLOR6_SLICE__TILE_MAX__SHIFT 0x0
-#define CB_COLOR7_SLICE__TILE_MAX_MASK 0x3fffff
-#define CB_COLOR7_SLICE__TILE_MAX__SHIFT 0x0
-#define CB_COLOR0_VIEW__SLICE_START_MASK 0x7ff
-#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0
-#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0xffe000
-#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd
-#define CB_COLOR1_VIEW__SLICE_START_MASK 0x7ff
-#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0
-#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0xffe000
-#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd
-#define CB_COLOR2_VIEW__SLICE_START_MASK 0x7ff
-#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0
-#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0xffe000
-#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd
-#define CB_COLOR3_VIEW__SLICE_START_MASK 0x7ff
-#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0
-#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0xffe000
-#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd
-#define CB_COLOR4_VIEW__SLICE_START_MASK 0x7ff
-#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0
-#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0xffe000
-#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd
-#define CB_COLOR5_VIEW__SLICE_START_MASK 0x7ff
-#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0
-#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0xffe000
-#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd
-#define CB_COLOR6_VIEW__SLICE_START_MASK 0x7ff
-#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0
-#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0xffe000
-#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd
-#define CB_COLOR7_VIEW__SLICE_START_MASK 0x7ff
-#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0
-#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0xffe000
-#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd
-#define CB_COLOR0_INFO__ENDIAN_MASK 0x3
-#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0
-#define CB_COLOR0_INFO__FORMAT_MASK 0x7c
-#define CB_COLOR0_INFO__FORMAT__SHIFT 0x2
-#define CB_COLOR0_INFO__LINEAR_GENERAL_MASK 0x80
-#define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT 0x7
-#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x700
-#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8
-#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x1800
-#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb
-#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x2000
-#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd
-#define CB_COLOR0_INFO__COMPRESSION_MASK 0x4000
-#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe
-#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x8000
-#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf
-#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x10000
-#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10
-#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x20000
-#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11
-#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x40000
-#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12
-#define CB_COLOR0_INFO__CMASK_IS_LINEAR_MASK 0x80000
-#define CB_COLOR0_INFO__CMASK_IS_LINEAR__SHIFT 0x13
-#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
-#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
-#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
-#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
-#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
-#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
-#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
-#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
-#define CB_COLOR0_INFO__DCC_ENABLE_MASK 0x10000000
-#define CB_COLOR0_INFO__DCC_ENABLE__SHIFT 0x1c
-#define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
-#define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
-#define CB_COLOR1_INFO__ENDIAN_MASK 0x3
-#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0
-#define CB_COLOR1_INFO__FORMAT_MASK 0x7c
-#define CB_COLOR1_INFO__FORMAT__SHIFT 0x2
-#define CB_COLOR1_INFO__LINEAR_GENERAL_MASK 0x80
-#define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT 0x7
-#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x700
-#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8
-#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x1800
-#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb
-#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x2000
-#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd
-#define CB_COLOR1_INFO__COMPRESSION_MASK 0x4000
-#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe
-#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x8000
-#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf
-#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x10000
-#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10
-#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x20000
-#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11
-#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x40000
-#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12
-#define CB_COLOR1_INFO__CMASK_IS_LINEAR_MASK 0x80000
-#define CB_COLOR1_INFO__CMASK_IS_LINEAR__SHIFT 0x13
-#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
-#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
-#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
-#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
-#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
-#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
-#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
-#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
-#define CB_COLOR1_INFO__DCC_ENABLE_MASK 0x10000000
-#define CB_COLOR1_INFO__DCC_ENABLE__SHIFT 0x1c
-#define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
-#define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
-#define CB_COLOR2_INFO__ENDIAN_MASK 0x3
-#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0
-#define CB_COLOR2_INFO__FORMAT_MASK 0x7c
-#define CB_COLOR2_INFO__FORMAT__SHIFT 0x2
-#define CB_COLOR2_INFO__LINEAR_GENERAL_MASK 0x80
-#define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT 0x7
-#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x700
-#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8
-#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x1800
-#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb
-#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x2000
-#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd
-#define CB_COLOR2_INFO__COMPRESSION_MASK 0x4000
-#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe
-#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x8000
-#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf
-#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x10000
-#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10
-#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x20000
-#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11
-#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x40000
-#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12
-#define CB_COLOR2_INFO__CMASK_IS_LINEAR_MASK 0x80000
-#define CB_COLOR2_INFO__CMASK_IS_LINEAR__SHIFT 0x13
-#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
-#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
-#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
-#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
-#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
-#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
-#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
-#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
-#define CB_COLOR2_INFO__DCC_ENABLE_MASK 0x10000000
-#define CB_COLOR2_INFO__DCC_ENABLE__SHIFT 0x1c
-#define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
-#define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
-#define CB_COLOR3_INFO__ENDIAN_MASK 0x3
-#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0
-#define CB_COLOR3_INFO__FORMAT_MASK 0x7c
-#define CB_COLOR3_INFO__FORMAT__SHIFT 0x2
-#define CB_COLOR3_INFO__LINEAR_GENERAL_MASK 0x80
-#define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT 0x7
-#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x700
-#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8
-#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x1800
-#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb
-#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x2000
-#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd
-#define CB_COLOR3_INFO__COMPRESSION_MASK 0x4000
-#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe
-#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x8000
-#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf
-#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x10000
-#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10
-#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x20000
-#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11
-#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x40000
-#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12
-#define CB_COLOR3_INFO__CMASK_IS_LINEAR_MASK 0x80000
-#define CB_COLOR3_INFO__CMASK_IS_LINEAR__SHIFT 0x13
-#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
-#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
-#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
-#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
-#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
-#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
-#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
-#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
-#define CB_COLOR3_INFO__DCC_ENABLE_MASK 0x10000000
-#define CB_COLOR3_INFO__DCC_ENABLE__SHIFT 0x1c
-#define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
-#define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
-#define CB_COLOR4_INFO__ENDIAN_MASK 0x3
-#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0
-#define CB_COLOR4_INFO__FORMAT_MASK 0x7c
-#define CB_COLOR4_INFO__FORMAT__SHIFT 0x2
-#define CB_COLOR4_INFO__LINEAR_GENERAL_MASK 0x80
-#define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT 0x7
-#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x700
-#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8
-#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x1800
-#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb
-#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x2000
-#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd
-#define CB_COLOR4_INFO__COMPRESSION_MASK 0x4000
-#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe
-#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x8000
-#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf
-#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x10000
-#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10
-#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x20000
-#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11
-#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x40000
-#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12
-#define CB_COLOR4_INFO__CMASK_IS_LINEAR_MASK 0x80000
-#define CB_COLOR4_INFO__CMASK_IS_LINEAR__SHIFT 0x13
-#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
-#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
-#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
-#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
-#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
-#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
-#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
-#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
-#define CB_COLOR4_INFO__DCC_ENABLE_MASK 0x10000000
-#define CB_COLOR4_INFO__DCC_ENABLE__SHIFT 0x1c
-#define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
-#define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
-#define CB_COLOR5_INFO__ENDIAN_MASK 0x3
-#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0
-#define CB_COLOR5_INFO__FORMAT_MASK 0x7c
-#define CB_COLOR5_INFO__FORMAT__SHIFT 0x2
-#define CB_COLOR5_INFO__LINEAR_GENERAL_MASK 0x80
-#define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT 0x7
-#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x700
-#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8
-#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x1800
-#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb
-#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x2000
-#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd
-#define CB_COLOR5_INFO__COMPRESSION_MASK 0x4000
-#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe
-#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x8000
-#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf
-#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x10000
-#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10
-#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x20000
-#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11
-#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x40000
-#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12
-#define CB_COLOR5_INFO__CMASK_IS_LINEAR_MASK 0x80000
-#define CB_COLOR5_INFO__CMASK_IS_LINEAR__SHIFT 0x13
-#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
-#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
-#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
-#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
-#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
-#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
-#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
-#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
-#define CB_COLOR5_INFO__DCC_ENABLE_MASK 0x10000000
-#define CB_COLOR5_INFO__DCC_ENABLE__SHIFT 0x1c
-#define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
-#define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
-#define CB_COLOR6_INFO__ENDIAN_MASK 0x3
-#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0
-#define CB_COLOR6_INFO__FORMAT_MASK 0x7c
-#define CB_COLOR6_INFO__FORMAT__SHIFT 0x2
-#define CB_COLOR6_INFO__LINEAR_GENERAL_MASK 0x80
-#define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT 0x7
-#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x700
-#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8
-#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x1800
-#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb
-#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x2000
-#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd
-#define CB_COLOR6_INFO__COMPRESSION_MASK 0x4000
-#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe
-#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x8000
-#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf
-#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x10000
-#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10
-#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x20000
-#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11
-#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x40000
-#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12
-#define CB_COLOR6_INFO__CMASK_IS_LINEAR_MASK 0x80000
-#define CB_COLOR6_INFO__CMASK_IS_LINEAR__SHIFT 0x13
-#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
-#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
-#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
-#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
-#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
-#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
-#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
-#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
-#define CB_COLOR6_INFO__DCC_ENABLE_MASK 0x10000000
-#define CB_COLOR6_INFO__DCC_ENABLE__SHIFT 0x1c
-#define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
-#define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
-#define CB_COLOR7_INFO__ENDIAN_MASK 0x3
-#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0
-#define CB_COLOR7_INFO__FORMAT_MASK 0x7c
-#define CB_COLOR7_INFO__FORMAT__SHIFT 0x2
-#define CB_COLOR7_INFO__LINEAR_GENERAL_MASK 0x80
-#define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT 0x7
-#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x700
-#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8
-#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x1800
-#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb
-#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x2000
-#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd
-#define CB_COLOR7_INFO__COMPRESSION_MASK 0x4000
-#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe
-#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x8000
-#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf
-#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x10000
-#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10
-#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x20000
-#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11
-#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x40000
-#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12
-#define CB_COLOR7_INFO__CMASK_IS_LINEAR_MASK 0x80000
-#define CB_COLOR7_INFO__CMASK_IS_LINEAR__SHIFT 0x13
-#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
-#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
-#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
-#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
-#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
-#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
-#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
-#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
-#define CB_COLOR7_INFO__DCC_ENABLE_MASK 0x10000000
-#define CB_COLOR7_INFO__DCC_ENABLE__SHIFT 0x1c
-#define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
-#define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
-#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
-#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
-#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
-#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
-#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
-#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
-#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x7000
-#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc
-#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
-#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
-#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
-#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
-#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
-#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
-#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
-#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
-#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
-#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
-#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x7000
-#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc
-#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
-#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
-#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
-#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
-#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
-#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
-#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
-#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
-#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
-#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
-#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x7000
-#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc
-#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
-#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
-#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
-#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
-#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
-#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
-#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
-#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
-#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
-#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
-#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x7000
-#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc
-#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
-#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
-#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
-#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
-#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
-#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
-#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
-#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
-#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
-#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
-#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x7000
-#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc
-#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
-#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
-#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
-#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
-#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
-#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
-#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
-#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
-#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
-#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
-#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x7000
-#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc
-#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
-#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
-#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
-#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
-#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
-#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
-#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
-#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
-#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
-#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
-#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x7000
-#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc
-#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
-#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
-#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
-#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
-#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
-#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
-#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
-#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
-#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
-#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
-#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x7000
-#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc
-#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
-#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
-#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
-#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
-#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
-#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
-#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
-#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
-#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
-#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
-#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
-#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
-#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
-#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
-#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
-#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
-#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
-#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
-#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
-#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
-#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
-#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
-#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
-#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
-#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
-#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
-#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
-#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
-#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
-#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
-#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
-#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
-#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
-#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
-#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
-#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
-#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
-#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
-#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
-#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
-#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
-#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
-#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
-#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
-#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
-#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
-#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
-#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
-#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
-#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
-#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
-#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
-#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
-#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
-#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
-#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
-#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
-#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
-#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
-#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
-#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
-#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
-#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
-#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
-#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
-#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
-#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
-#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
-#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
-#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
-#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
-#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
-#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
-#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
-#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
-#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
-#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
-#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
-#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
-#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
-#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
-#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
-#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
-#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
-#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
-#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
-#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
-#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
-#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
-#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
-#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
-#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
-#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
-#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
-#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
-#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
-#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
-#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
-#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
-#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
-#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
-#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
-#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
-#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
-#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
-#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
-#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
-#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
-#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
-#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
-#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
-#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
-#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
-#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
-#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
-#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
-#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
-#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
-#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
-#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
-#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
-#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
-#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
-#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
-#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
-#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
-#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
-#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
-#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
-#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
-#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
-#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
-#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
-#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
-#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
-#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
-#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
-#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
-#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
-#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
-#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
-#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
-#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
-#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
-#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
-#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
-#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
-#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
-#define CB_COLOR0_CMASK__BASE_256B_MASK 0xffffffff
-#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR1_CMASK__BASE_256B_MASK 0xffffffff
-#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR2_CMASK__BASE_256B_MASK 0xffffffff
-#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR3_CMASK__BASE_256B_MASK 0xffffffff
-#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR4_CMASK__BASE_256B_MASK 0xffffffff
-#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR5_CMASK__BASE_256B_MASK 0xffffffff
-#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR6_CMASK__BASE_256B_MASK 0xffffffff
-#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR7_CMASK__BASE_256B_MASK 0xffffffff
-#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR0_CMASK_SLICE__TILE_MAX_MASK 0x3fff
-#define CB_COLOR0_CMASK_SLICE__TILE_MAX__SHIFT 0x0
-#define CB_COLOR1_CMASK_SLICE__TILE_MAX_MASK 0x3fff
-#define CB_COLOR1_CMASK_SLICE__TILE_MAX__SHIFT 0x0
-#define CB_COLOR2_CMASK_SLICE__TILE_MAX_MASK 0x3fff
-#define CB_COLOR2_CMASK_SLICE__TILE_MAX__SHIFT 0x0
-#define CB_COLOR3_CMASK_SLICE__TILE_MAX_MASK 0x3fff
-#define CB_COLOR3_CMASK_SLICE__TILE_MAX__SHIFT 0x0
-#define CB_COLOR4_CMASK_SLICE__TILE_MAX_MASK 0x3fff
-#define CB_COLOR4_CMASK_SLICE__TILE_MAX__SHIFT 0x0
-#define CB_COLOR5_CMASK_SLICE__TILE_MAX_MASK 0x3fff
-#define CB_COLOR5_CMASK_SLICE__TILE_MAX__SHIFT 0x0
-#define CB_COLOR6_CMASK_SLICE__TILE_MAX_MASK 0x3fff
-#define CB_COLOR6_CMASK_SLICE__TILE_MAX__SHIFT 0x0
-#define CB_COLOR7_CMASK_SLICE__TILE_MAX_MASK 0x3fff
-#define CB_COLOR7_CMASK_SLICE__TILE_MAX__SHIFT 0x0
-#define CB_COLOR0_FMASK__BASE_256B_MASK 0xffffffff
-#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR1_FMASK__BASE_256B_MASK 0xffffffff
-#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR2_FMASK__BASE_256B_MASK 0xffffffff
-#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR3_FMASK__BASE_256B_MASK 0xffffffff
-#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR4_FMASK__BASE_256B_MASK 0xffffffff
-#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR5_FMASK__BASE_256B_MASK 0xffffffff
-#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR6_FMASK__BASE_256B_MASK 0xffffffff
-#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR7_FMASK__BASE_256B_MASK 0xffffffff
-#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0
-#define CB_COLOR0_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
-#define CB_COLOR0_FMASK_SLICE__TILE_MAX__SHIFT 0x0
-#define CB_COLOR1_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
-#define CB_COLOR1_FMASK_SLICE__TILE_MAX__SHIFT 0x0
-#define CB_COLOR2_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
-#define CB_COLOR2_FMASK_SLICE__TILE_MAX__SHIFT 0x0
-#define CB_COLOR3_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
-#define CB_COLOR3_FMASK_SLICE__TILE_MAX__SHIFT 0x0
-#define CB_COLOR4_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
-#define CB_COLOR4_FMASK_SLICE__TILE_MAX__SHIFT 0x0
-#define CB_COLOR5_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
-#define CB_COLOR5_FMASK_SLICE__TILE_MAX__SHIFT 0x0
-#define CB_COLOR6_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
-#define CB_COLOR6_FMASK_SLICE__TILE_MAX__SHIFT 0x0
-#define CB_COLOR7_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
-#define CB_COLOR7_FMASK_SLICE__TILE_MAX__SHIFT 0x0
-#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
-#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
-#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
-#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
-#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
-#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
-#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
-#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
-#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
-#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
-#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
-#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
-#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
-#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
-#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
-#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
-#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
-#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
-#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
-#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
-#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
-#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
-#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
-#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
-#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
-#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
-#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
-#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
-#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
-#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
-#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
-#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
-#define CB_COLOR0_DCC_BASE__BASE_256B_MASK 0xffffffff
-#define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR1_DCC_BASE__BASE_256B_MASK 0xffffffff
-#define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR2_DCC_BASE__BASE_256B_MASK 0xffffffff
-#define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR3_DCC_BASE__BASE_256B_MASK 0xffffffff
-#define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR4_DCC_BASE__BASE_256B_MASK 0xffffffff
-#define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR5_DCC_BASE__BASE_256B_MASK 0xffffffff
-#define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR6_DCC_BASE__BASE_256B_MASK 0xffffffff
-#define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT 0x0
-#define CB_COLOR7_DCC_BASE__BASE_256B_MASK 0xffffffff
-#define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT 0x0
-#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0xf
-#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0
-#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0xf0
-#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4
-#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0xf00
-#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8
-#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0xf000
-#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc
-#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0xf0000
-#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10
-#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0xf00000
-#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14
-#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0xf000000
-#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18
-#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xf0000000
-#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c
-#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0xf
-#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0
-#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0xf0
-#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4
-#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0xf00
-#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8
-#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0xf000
-#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc
-#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0xf0000
-#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10
-#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0xf00000
-#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14
-#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0xf000000
-#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18
-#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xf0000000
-#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c
-#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0xf
-#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0
-#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x3c0
-#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6
-#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0xf000
-#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc
-#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x10000
-#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10
-#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x40000
-#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12
-#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x80000
-#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13
-#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x100000
-#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14
-#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x200000
-#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15
-#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x400000
-#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16
-#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x800000
-#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17
-#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x1000000
-#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18
-#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x2000000
-#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19
-#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x4000000
-#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a
-#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x8000000
-#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b
-#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000
-#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c
-#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000
-#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d
-#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000
-#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e
-#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000
-#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f
-#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x1f
-#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0
-#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x7e0
-#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5
-#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x1f800
-#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb
-#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x3fe0000
-#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11
-#define CB_HW_CONTROL_1__CHICKEN_BITS_MASK 0xfc000000
-#define CB_HW_CONTROL_1__CHICKEN_BITS__SHIFT 0x1a
-#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0xff
-#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0
-#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x7f00
-#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8
-#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x7f8000
-#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf
-#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK 0xf000000
-#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT 0x18
-#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xf0000000
-#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x1c
-#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x1
-#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0
-#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK 0x2
-#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT 0x1
-#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK 0x4
-#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT 0x2
-#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK 0x8
-#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT 0x3
-#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK 0x10
-#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT 0x4
-#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK 0x20
-#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT 0x5
-#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK 0x80
-#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT 0x7
-#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK 0x100
-#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT 0x8
-#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK 0x200
-#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT 0x9
-#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK 0x400
-#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT 0xa
-#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION_MASK 0x800
-#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION__SHIFT 0xb
-#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967_MASK 0x1000
-#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967__SHIFT 0xc
-#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657_MASK 0x2000
-#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657__SHIFT 0xd
-#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK 0x1f
-#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT 0x0
-#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK 0x20
-#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT 0x5
-#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK 0x40
-#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT 0x6
-#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK 0xff00
-#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT 0x8
-#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK 0x7f0000
-#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT 0x10
-#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT_MASK 0xf000000
-#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT__SHIFT 0x18
-#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK 0xf0000000
-#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT 0x1c
-#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x1
-#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0
-#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0xe
-#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1
-#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x10
-#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4
-#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x3e0
-#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5
-#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x400
-#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa
-#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x800
-#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb
-#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x1000
-#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc
-#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0xe000
-#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd
-#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x20000
-#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11
-#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x1c0000
-#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12
-#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x200000
-#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15
-#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0xc00000
-#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16
-#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x1ff
-#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x7fc00
-#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
-#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
-#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
-#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
-#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x1ff
-#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x7fc00
-#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
-#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
-#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
-#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x1ff
-#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
-#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x1ff
-#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
-#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
-#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x1ff
-#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
-#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
-#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf
-#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
-#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
-#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
-#define CB_DEBUG_BUS_1__CB_BUSY_MASK 0x1
-#define CB_DEBUG_BUS_1__CB_BUSY__SHIFT 0x0
-#define CB_DEBUG_BUS_1__DB_CB_TILE_VALID_READY_MASK 0x2
-#define CB_DEBUG_BUS_1__DB_CB_TILE_VALID_READY__SHIFT 0x1
-#define CB_DEBUG_BUS_1__DB_CB_TILE_VALID_READYB_MASK 0x4
-#define CB_DEBUG_BUS_1__DB_CB_TILE_VALID_READYB__SHIFT 0x2
-#define CB_DEBUG_BUS_1__DB_CB_TILE_VALIDB_READY_MASK 0x8
-#define CB_DEBUG_BUS_1__DB_CB_TILE_VALIDB_READY__SHIFT 0x3
-#define CB_DEBUG_BUS_1__DB_CB_TILE_VALIDB_READYB_MASK 0x10
-#define CB_DEBUG_BUS_1__DB_CB_TILE_VALIDB_READYB__SHIFT 0x4
-#define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALID_READY_MASK 0x20
-#define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALID_READY__SHIFT 0x5
-#define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALID_READYB_MASK 0x40
-#define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALID_READYB__SHIFT 0x6
-#define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALIDB_READY_MASK 0x80
-#define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALIDB_READY__SHIFT 0x7
-#define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALIDB_READYB_MASK 0x100
-#define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALIDB_READYB__SHIFT 0x8
-#define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALID_READY_MASK 0x200
-#define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALID_READY__SHIFT 0x9
-#define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALID_READYB_MASK 0x400
-#define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALID_READYB__SHIFT 0xa
-#define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALIDB_READY_MASK 0x800
-#define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALIDB_READY__SHIFT 0xb
-#define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALIDB_READYB_MASK 0x1000
-#define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALIDB_READYB__SHIFT 0xc
-#define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALID_READY_MASK 0x2000
-#define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALID_READY__SHIFT 0xd
-#define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALID_READYB_MASK 0x4000
-#define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALID_READYB__SHIFT 0xe
-#define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALIDB_READY_MASK 0x8000
-#define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALIDB_READY__SHIFT 0xf
-#define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALIDB_READYB_MASK 0x10000
-#define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALIDB_READYB__SHIFT 0x10
-#define CB_DEBUG_BUS_1__CM_FC_TILE_VALID_READY_MASK 0x20000
-#define CB_DEBUG_BUS_1__CM_FC_TILE_VALID_READY__SHIFT 0x11
-#define CB_DEBUG_BUS_1__CM_FC_TILE_VALID_READYB_MASK 0x40000
-#define CB_DEBUG_BUS_1__CM_FC_TILE_VALID_READYB__SHIFT 0x12
-#define CB_DEBUG_BUS_1__CM_FC_TILE_VALIDB_READY_MASK 0x80000
-#define CB_DEBUG_BUS_1__CM_FC_TILE_VALIDB_READY__SHIFT 0x13
-#define CB_DEBUG_BUS_1__CM_FC_TILE_VALIDB_READYB_MASK 0x100000
-#define CB_DEBUG_BUS_1__CM_FC_TILE_VALIDB_READYB__SHIFT 0x14
-#define CB_DEBUG_BUS_1__FC_CLEAR_QUAD_VALID_READY_MASK 0x200000
-#define CB_DEBUG_BUS_1__FC_CLEAR_QUAD_VALID_READY__SHIFT 0x15
-#define CB_DEBUG_BUS_1__FC_CLEAR_QUAD_VALID_READYB_MASK 0x400000
-#define CB_DEBUG_BUS_1__FC_CLEAR_QUAD_VALID_READYB__SHIFT 0x16
-#define CB_DEBUG_BUS_1__FC_CLEAR_QUAD_VALIDB_READY_MASK 0x800000
-#define CB_DEBUG_BUS_1__FC_CLEAR_QUAD_VALIDB_READY__SHIFT 0x17
-#define CB_DEBUG_BUS_2__FC_CLEAR_QUAD_VALIDB_READYB_MASK 0x1
-#define CB_DEBUG_BUS_2__FC_CLEAR_QUAD_VALIDB_READYB__SHIFT 0x0
-#define CB_DEBUG_BUS_2__FC_QUAD_RESIDENCY_STALL_MASK 0x2
-#define CB_DEBUG_BUS_2__FC_QUAD_RESIDENCY_STALL__SHIFT 0x1
-#define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALID_READY_MASK 0x4
-#define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALID_READY__SHIFT 0x2
-#define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALID_READYB_MASK 0x8
-#define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALID_READYB__SHIFT 0x3
-#define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALIDB_READY_MASK 0x10
-#define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALIDB_READY__SHIFT 0x4
-#define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALIDB_READYB_MASK 0x20
-#define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALIDB_READYB__SHIFT 0x5
-#define CB_DEBUG_BUS_2__FOP_IN_VALID_READY_MASK 0x40
-#define CB_DEBUG_BUS_2__FOP_IN_VALID_READY__SHIFT 0x6
-#define CB_DEBUG_BUS_2__FOP_IN_VALID_READYB_MASK 0x80
-#define CB_DEBUG_BUS_2__FOP_IN_VALID_READYB__SHIFT 0x7
-#define CB_DEBUG_BUS_2__FOP_IN_VALIDB_READY_MASK 0x100
-#define CB_DEBUG_BUS_2__FOP_IN_VALIDB_READY__SHIFT 0x8
-#define CB_DEBUG_BUS_2__FOP_IN_VALIDB_READYB_MASK 0x200
-#define CB_DEBUG_BUS_2__FOP_IN_VALIDB_READYB__SHIFT 0x9
-#define CB_DEBUG_BUS_2__FOP_FMASK_RAW_STALL_MASK 0x400
-#define CB_DEBUG_BUS_2__FOP_FMASK_RAW_STALL__SHIFT 0xa
-#define CB_DEBUG_BUS_2__FOP_FMASK_BYPASS_STALL_MASK 0x800
-#define CB_DEBUG_BUS_2__FOP_FMASK_BYPASS_STALL__SHIFT 0xb
-#define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALID_READY_MASK 0x1000
-#define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALID_READY__SHIFT 0xc
-#define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALID_READYB_MASK 0x2000
-#define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALID_READYB__SHIFT 0xd
-#define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALIDB_READY_MASK 0x4000
-#define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALIDB_READY__SHIFT 0xe
-#define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALIDB_READYB_MASK 0x8000
-#define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALIDB_READYB__SHIFT 0xf
-#define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALID_READY_MASK 0x10000
-#define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALID_READY__SHIFT 0x10
-#define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALID_READYB_MASK 0x20000
-#define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALID_READYB__SHIFT 0x11
-#define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALIDB_READY_MASK 0x40000
-#define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALIDB_READY__SHIFT 0x12
-#define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALIDB_READYB_MASK 0x80000
-#define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALIDB_READYB__SHIFT 0x13
-#define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALID_READY_MASK 0x100000
-#define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALID_READY__SHIFT 0x14
-#define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALID_READYB_MASK 0x200000
-#define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALID_READYB__SHIFT 0x15
-#define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALIDB_READY_MASK 0x400000
-#define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALIDB_READY__SHIFT 0x16
-#define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALIDB_READYB_MASK 0x800000
-#define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALIDB_READYB__SHIFT 0x17
-#define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALID_READY_MASK 0x1
-#define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALID_READY__SHIFT 0x0
-#define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALID_READYB_MASK 0x2
-#define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALID_READYB__SHIFT 0x1
-#define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALIDB_READY_MASK 0x4
-#define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALIDB_READY__SHIFT 0x2
-#define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALIDB_READYB_MASK 0x8
-#define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALIDB_READYB__SHIFT 0x3
-#define CB_DEBUG_BUS_3__CC_BC_CS_FRAG_VALID_MASK 0x10
-#define CB_DEBUG_BUS_3__CC_BC_CS_FRAG_VALID__SHIFT 0x4
-#define CB_DEBUG_BUS_3__CC_SF_FULL_MASK 0x20
-#define CB_DEBUG_BUS_3__CC_SF_FULL__SHIFT 0x5
-#define CB_DEBUG_BUS_3__CC_RB_FULL_MASK 0x40
-#define CB_DEBUG_BUS_3__CC_RB_FULL__SHIFT 0x6
-#define CB_DEBUG_BUS_3__CC_EVENFIFO_QUAD_RESIDENCY_STALL_MASK 0x80
-#define CB_DEBUG_BUS_3__CC_EVENFIFO_QUAD_RESIDENCY_STALL__SHIFT 0x7
-#define CB_DEBUG_BUS_3__CC_ODDFIFO_QUAD_RESIDENCY_STALL_MASK 0x100
-#define CB_DEBUG_BUS_3__CC_ODDFIFO_QUAD_RESIDENCY_STALL__SHIFT 0x8
-#define CB_DEBUG_BUS_3__CM_TQ_FULL_MASK 0x200
-#define CB_DEBUG_BUS_3__CM_TQ_FULL__SHIFT 0x9
-#define CB_DEBUG_BUS_3__CM_TILE_RESIDENCY_STALL_MASK 0x400
-#define CB_DEBUG_BUS_3__CM_TILE_RESIDENCY_STALL__SHIFT 0xa
-#define CB_DEBUG_BUS_3__LQUAD_NO_TILE_MASK 0x800
-#define CB_DEBUG_BUS_3__LQUAD_NO_TILE__SHIFT 0xb
-#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_R_MASK 0x1000
-#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_R__SHIFT 0xc
-#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_AR_MASK 0x2000
-#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_AR__SHIFT 0xd
-#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_GR_MASK 0x4000
-#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_GR__SHIFT 0xe
-#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_ABGR_MASK 0x8000
-#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_ABGR__SHIFT 0xf
-#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_FP16_ABGR_MASK 0x10000
-#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_FP16_ABGR__SHIFT 0x10
-#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR_MASK 0x20000
-#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR__SHIFT 0x11
-#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR_MASK 0x40000
-#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR__SHIFT 0x12
-#define CB_DEBUG_BUS_3__CM_CACHE_HIT_MASK 0x80000
-#define CB_DEBUG_BUS_3__CM_CACHE_HIT__SHIFT 0x13
-#define CB_DEBUG_BUS_3__CM_CACHE_TAG_MISS_MASK 0x100000
-#define CB_DEBUG_BUS_3__CM_CACHE_TAG_MISS__SHIFT 0x14
-#define CB_DEBUG_BUS_3__CM_CACHE_SECTOR_MISS_MASK 0x200000
-#define CB_DEBUG_BUS_3__CM_CACHE_SECTOR_MISS__SHIFT 0x15
-#define CB_DEBUG_BUS_3__CM_CACHE_REEVICTION_STALL_MASK 0x400000
-#define CB_DEBUG_BUS_3__CM_CACHE_REEVICTION_STALL__SHIFT 0x16
-#define CB_DEBUG_BUS_3__CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL_MASK 0x800000
-#define CB_DEBUG_BUS_3__CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL__SHIFT 0x17
-#define CB_DEBUG_BUS_4__CM_CACHE_REPLACE_PENDING_EVICT_STALL_MASK 0x1
-#define CB_DEBUG_BUS_4__CM_CACHE_REPLACE_PENDING_EVICT_STALL__SHIFT 0x0
-#define CB_DEBUG_BUS_4__CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL_MASK 0x2
-#define CB_DEBUG_BUS_4__CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL__SHIFT 0x1
-#define CB_DEBUG_BUS_4__CM_CACHE_READ_OUTPUT_STALL_MASK 0x4
-#define CB_DEBUG_BUS_4__CM_CACHE_READ_OUTPUT_STALL__SHIFT 0x2
-#define CB_DEBUG_BUS_4__CM_CACHE_WRITE_OUTPUT_STALL_MASK 0x8
-#define CB_DEBUG_BUS_4__CM_CACHE_WRITE_OUTPUT_STALL__SHIFT 0x3
-#define CB_DEBUG_BUS_4__CM_CACHE_ACK_OUTPUT_STALL_MASK 0x10
-#define CB_DEBUG_BUS_4__CM_CACHE_ACK_OUTPUT_STALL__SHIFT 0x4
-#define CB_DEBUG_BUS_4__CM_CACHE_STALL_MASK 0x20
-#define CB_DEBUG_BUS_4__CM_CACHE_STALL__SHIFT 0x5
-#define CB_DEBUG_BUS_4__FC_CACHE_HIT_MASK 0x40
-#define CB_DEBUG_BUS_4__FC_CACHE_HIT__SHIFT 0x6
-#define CB_DEBUG_BUS_4__FC_CACHE_TAG_MISS_MASK 0x80
-#define CB_DEBUG_BUS_4__FC_CACHE_TAG_MISS__SHIFT 0x7
-#define CB_DEBUG_BUS_4__FC_CACHE_SECTOR_MISS_MASK 0x100
-#define CB_DEBUG_BUS_4__FC_CACHE_SECTOR_MISS__SHIFT 0x8
-#define CB_DEBUG_BUS_4__FC_CACHE_REEVICTION_STALL_MASK 0x200
-#define CB_DEBUG_BUS_4__FC_CACHE_REEVICTION_STALL__SHIFT 0x9
-#define CB_DEBUG_BUS_4__FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL_MASK 0x400
-#define CB_DEBUG_BUS_4__FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL__SHIFT 0xa
-#define CB_DEBUG_BUS_4__FC_CACHE_REPLACE_PENDING_EVICT_STALL_MASK 0x800
-#define CB_DEBUG_BUS_4__FC_CACHE_REPLACE_PENDING_EVICT_STALL__SHIFT 0xb
-#define CB_DEBUG_BUS_4__FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL_MASK 0x1000
-#define CB_DEBUG_BUS_4__FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL__SHIFT 0xc
-#define CB_DEBUG_BUS_4__FC_CACHE_READ_OUTPUT_STALL_MASK 0x2000
-#define CB_DEBUG_BUS_4__FC_CACHE_READ_OUTPUT_STALL__SHIFT 0xd
-#define CB_DEBUG_BUS_4__FC_CACHE_WRITE_OUTPUT_STALL_MASK 0x4000
-#define CB_DEBUG_BUS_4__FC_CACHE_WRITE_OUTPUT_STALL__SHIFT 0xe
-#define CB_DEBUG_BUS_4__FC_CACHE_ACK_OUTPUT_STALL_MASK 0x8000
-#define CB_DEBUG_BUS_4__FC_CACHE_ACK_OUTPUT_STALL__SHIFT 0xf
-#define CB_DEBUG_BUS_4__FC_CACHE_STALL_MASK 0x10000
-#define CB_DEBUG_BUS_4__FC_CACHE_STALL__SHIFT 0x10
-#define CB_DEBUG_BUS_4__CC_CACHE_HIT_MASK 0x20000
-#define CB_DEBUG_BUS_4__CC_CACHE_HIT__SHIFT 0x11
-#define CB_DEBUG_BUS_4__CC_CACHE_TAG_MISS_MASK 0x40000
-#define CB_DEBUG_BUS_4__CC_CACHE_TAG_MISS__SHIFT 0x12
-#define CB_DEBUG_BUS_4__CC_CACHE_SECTOR_MISS_MASK 0x80000
-#define CB_DEBUG_BUS_4__CC_CACHE_SECTOR_MISS__SHIFT 0x13
-#define CB_DEBUG_BUS_4__CC_CACHE_REEVICTION_STALL_MASK 0x100000
-#define CB_DEBUG_BUS_4__CC_CACHE_REEVICTION_STALL__SHIFT 0x14
-#define CB_DEBUG_BUS_4__CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL_MASK 0x200000
-#define CB_DEBUG_BUS_4__CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL__SHIFT 0x15
-#define CB_DEBUG_BUS_4__CC_CACHE_REPLACE_PENDING_EVICT_STALL_MASK 0x400000
-#define CB_DEBUG_BUS_4__CC_CACHE_REPLACE_PENDING_EVICT_STALL__SHIFT 0x16
-#define CB_DEBUG_BUS_4__CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL_MASK 0x800000
-#define CB_DEBUG_BUS_4__CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL__SHIFT 0x17
-#define CB_DEBUG_BUS_5__CC_CACHE_READ_OUTPUT_STALL_MASK 0x1
-#define CB_DEBUG_BUS_5__CC_CACHE_READ_OUTPUT_STALL__SHIFT 0x0
-#define CB_DEBUG_BUS_5__CC_CACHE_WRITE_OUTPUT_STALL_MASK 0x2
-#define CB_DEBUG_BUS_5__CC_CACHE_WRITE_OUTPUT_STALL__SHIFT 0x1
-#define CB_DEBUG_BUS_5__CC_CACHE_ACK_OUTPUT_STALL_MASK 0x4
-#define CB_DEBUG_BUS_5__CC_CACHE_ACK_OUTPUT_STALL__SHIFT 0x2
-#define CB_DEBUG_BUS_5__CC_CACHE_STALL_MASK 0x8
-#define CB_DEBUG_BUS_5__CC_CACHE_STALL__SHIFT 0x3
-#define CB_DEBUG_BUS_5__CC_CACHE_WA_TO_RMW_CONVERSION_MASK 0x10
-#define CB_DEBUG_BUS_5__CC_CACHE_WA_TO_RMW_CONVERSION__SHIFT 0x4
-#define CB_DEBUG_BUS_5__CM_CACHE_FLUSH_MASK 0x20
-#define CB_DEBUG_BUS_5__CM_CACHE_FLUSH__SHIFT 0x5
-#define CB_DEBUG_BUS_5__CM_CACHE_TAGS_FLUSHED_MASK 0x40
-#define CB_DEBUG_BUS_5__CM_CACHE_TAGS_FLUSHED__SHIFT 0x6
-#define CB_DEBUG_BUS_5__CM_CACHE_SECTORS_FLUSHED_MASK 0x80
-#define CB_DEBUG_BUS_5__CM_CACHE_SECTORS_FLUSHED__SHIFT 0x7
-#define CB_DEBUG_BUS_5__CM_CACHE_DIRTY_SECTORS_FLUSHED_MASK 0x100
-#define CB_DEBUG_BUS_5__CM_CACHE_DIRTY_SECTORS_FLUSHED__SHIFT 0x8
-#define CB_DEBUG_BUS_5__FC_CACHE_FLUSH_MASK 0x200
-#define CB_DEBUG_BUS_5__FC_CACHE_FLUSH__SHIFT 0x9
-#define CB_DEBUG_BUS_5__FC_CACHE_TAGS_FLUSHED_MASK 0x400
-#define CB_DEBUG_BUS_5__FC_CACHE_TAGS_FLUSHED__SHIFT 0xa
-#define CB_DEBUG_BUS_5__FC_CACHE_SECTORS_FLUSHED_MASK 0x3800
-#define CB_DEBUG_BUS_5__FC_CACHE_SECTORS_FLUSHED__SHIFT 0xb
-#define CB_DEBUG_BUS_5__FC_CACHE_DIRTY_SECTORS_FLUSHED_MASK 0x1c000
-#define CB_DEBUG_BUS_5__FC_CACHE_DIRTY_SECTORS_FLUSHED__SHIFT 0xe
-#define CB_DEBUG_BUS_5__CC_CACHE_FLUSH_MASK 0x20000
-#define CB_DEBUG_BUS_5__CC_CACHE_FLUSH__SHIFT 0x11
-#define CB_DEBUG_BUS_5__CC_CACHE_TAGS_FLUSHED_MASK 0x40000
-#define CB_DEBUG_BUS_5__CC_CACHE_TAGS_FLUSHED__SHIFT 0x12
-#define CB_DEBUG_BUS_5__CC_CACHE_SECTORS_FLUSHED_MASK 0x380000
-#define CB_DEBUG_BUS_5__CC_CACHE_SECTORS_FLUSHED__SHIFT 0x13
-#define CB_DEBUG_BUS_6__CC_CACHE_DIRTY_SECTORS_FLUSHED_MASK 0x7
-#define CB_DEBUG_BUS_6__CC_CACHE_DIRTY_SECTORS_FLUSHED__SHIFT 0x0
-#define CB_DEBUG_BUS_6__CM_MC_READ_REQUEST_MASK 0x8
-#define CB_DEBUG_BUS_6__CM_MC_READ_REQUEST__SHIFT 0x3
-#define CB_DEBUG_BUS_6__FC_MC_READ_REQUEST_MASK 0x10
-#define CB_DEBUG_BUS_6__FC_MC_READ_REQUEST__SHIFT 0x4
-#define CB_DEBUG_BUS_6__CC_MC_READ_REQUEST_MASK 0x20
-#define CB_DEBUG_BUS_6__CC_MC_READ_REQUEST__SHIFT 0x5
-#define CB_DEBUG_BUS_6__CM_MC_WRITE_REQUEST_MASK 0x40
-#define CB_DEBUG_BUS_6__CM_MC_WRITE_REQUEST__SHIFT 0x6
-#define CB_DEBUG_BUS_6__FC_MC_WRITE_REQUEST_MASK 0x80
-#define CB_DEBUG_BUS_6__FC_MC_WRITE_REQUEST__SHIFT 0x7
-#define CB_DEBUG_BUS_6__CC_MC_WRITE_REQUEST_MASK 0x100
-#define CB_DEBUG_BUS_6__CC_MC_WRITE_REQUEST__SHIFT 0x8
-#define CB_DEBUG_BUS_6__CM_MC_READ_REQUESTS_IN_FLIGHT_MASK 0x1fe00
-#define CB_DEBUG_BUS_6__CM_MC_READ_REQUESTS_IN_FLIGHT__SHIFT 0x9
-#define CB_DEBUG_BUS_7__FC_MC_READ_REQUESTS_IN_FLIGHT_MASK 0x7ff
-#define CB_DEBUG_BUS_7__FC_MC_READ_REQUESTS_IN_FLIGHT__SHIFT 0x0
-#define CB_DEBUG_BUS_7__CC_MC_READ_REQUESTS_IN_FLIGHT_MASK 0x1ff800
-#define CB_DEBUG_BUS_7__CC_MC_READ_REQUESTS_IN_FLIGHT__SHIFT 0xb
-#define CB_DEBUG_BUS_8__CM_MC_WRITE_REQUESTS_IN_FLIGHT_MASK 0xff
-#define CB_DEBUG_BUS_8__CM_MC_WRITE_REQUESTS_IN_FLIGHT__SHIFT 0x0
-#define CB_DEBUG_BUS_8__FC_MC_WRITE_REQUESTS_IN_FLIGHT_MASK 0x7ff00
-#define CB_DEBUG_BUS_8__FC_MC_WRITE_REQUESTS_IN_FLIGHT__SHIFT 0x8
-#define CB_DEBUG_BUS_8__FC_SEQUENCER_FMASK_COMPRESSION_DISABLE_MASK 0x80000
-#define CB_DEBUG_BUS_8__FC_SEQUENCER_FMASK_COMPRESSION_DISABLE__SHIFT 0x13
-#define CB_DEBUG_BUS_8__FC_SEQUENCER_FMASK_DECOMPRESS_MASK 0x100000
-#define CB_DEBUG_BUS_8__FC_SEQUENCER_FMASK_DECOMPRESS__SHIFT 0x14
-#define CB_DEBUG_BUS_8__FC_SEQUENCER_ELIMINATE_FAST_CLEAR_MASK 0x200000
-#define CB_DEBUG_BUS_8__FC_SEQUENCER_ELIMINATE_FAST_CLEAR__SHIFT 0x15
-#define CB_DEBUG_BUS_8__FC_SEQUENCER_CLEAR_MASK 0x400000
-#define CB_DEBUG_BUS_8__FC_SEQUENCER_CLEAR__SHIFT 0x16
-#define CB_DEBUG_BUS_9__CC_MC_WRITE_REQUESTS_IN_FLIGHT_MASK 0x3ff
-#define CB_DEBUG_BUS_9__CC_MC_WRITE_REQUESTS_IN_FLIGHT__SHIFT 0x0
-#define CB_DEBUG_BUS_9__CC_SURFACE_SYNC_MASK 0x400
-#define CB_DEBUG_BUS_9__CC_SURFACE_SYNC__SHIFT 0xa
-#define CB_DEBUG_BUS_9__TWO_PROBE_QUAD_FRAGMENT_MASK 0x800
-#define CB_DEBUG_BUS_9__TWO_PROBE_QUAD_FRAGMENT__SHIFT 0xb
-#define CB_DEBUG_BUS_9__EXPORT_32_ABGR_QUAD_FRAGMENT_MASK 0x1000
-#define CB_DEBUG_BUS_9__EXPORT_32_ABGR_QUAD_FRAGMENT__SHIFT 0xc
-#define CB_DEBUG_BUS_9__DUAL_SOURCE_COLOR_QUAD_FRAGMENT_MASK 0x2000
-#define CB_DEBUG_BUS_9__DUAL_SOURCE_COLOR_QUAD_FRAGMENT__SHIFT 0xd
-#define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_QUAD_MASK 0x4000
-#define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_QUAD__SHIFT 0xe
-#define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_PIXEL_MASK 0x78000
-#define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_PIXEL__SHIFT 0xf
-#define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_QUAD_FRAGMENT_MASK 0x80000
-#define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_QUAD_FRAGMENT__SHIFT 0x13
-#define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_TILE_MASK 0x100000
-#define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_TILE__SHIFT 0x14
-#define CB_DEBUG_BUS_9__EVENT_ALL_MASK 0x200000
-#define CB_DEBUG_BUS_9__EVENT_ALL__SHIFT 0x15
-#define CB_DEBUG_BUS_9__EVENT_CACHE_FLUSH_TS_MASK 0x400000
-#define CB_DEBUG_BUS_9__EVENT_CACHE_FLUSH_TS__SHIFT 0x16
-#define CB_DEBUG_BUS_9__EVENT_CONTEXT_DONE_MASK 0x800000
-#define CB_DEBUG_BUS_9__EVENT_CONTEXT_DONE__SHIFT 0x17
-#define CB_DEBUG_BUS_10__EVENT_CACHE_FLUSH_MASK 0x1
-#define CB_DEBUG_BUS_10__EVENT_CACHE_FLUSH__SHIFT 0x0
-#define CB_DEBUG_BUS_10__EVENT_CACHE_FLUSH_AND_INV_TS_EVENT_MASK 0x2
-#define CB_DEBUG_BUS_10__EVENT_CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT 0x1
-#define CB_DEBUG_BUS_10__EVENT_CACHE_FLUSH_AND_INV_EVENT_MASK 0x4
-#define CB_DEBUG_BUS_10__EVENT_CACHE_FLUSH_AND_INV_EVENT__SHIFT 0x2
-#define CB_DEBUG_BUS_10__EVENT_FLUSH_AND_INV_CB_DATA_TS_MASK 0x8
-#define CB_DEBUG_BUS_10__EVENT_FLUSH_AND_INV_CB_DATA_TS__SHIFT 0x3
-#define CB_DEBUG_BUS_10__EVENT_FLUSH_AND_INV_CB_META_MASK 0x10
-#define CB_DEBUG_BUS_10__EVENT_FLUSH_AND_INV_CB_META__SHIFT 0x4
-#define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XC_MASK 0x20
-#define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XC__SHIFT 0x5
-#define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XD_MASK 0x40
-#define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XD__SHIFT 0x6
-#define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XE_MASK 0x80
-#define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XE__SHIFT 0x7
-#define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XF_MASK 0x100
-#define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XF__SHIFT 0x8
-#define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XC_MASK 0x200
-#define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XC__SHIFT 0x9
-#define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XD_MASK 0x400
-#define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XD__SHIFT 0xa
-#define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XE_MASK 0x800
-#define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XE__SHIFT 0xb
-#define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XF_MASK 0x1000
-#define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XF__SHIFT 0xc
-#define CB_DEBUG_BUS_10__CORE_SCLK_VLD_MASK 0x2000
-#define CB_DEBUG_BUS_10__CORE_SCLK_VLD__SHIFT 0xd
-#define CB_DEBUG_BUS_10__REG_SCLK0_VLD_MASK 0x4000
-#define CB_DEBUG_BUS_10__REG_SCLK0_VLD__SHIFT 0xe
-#define CB_DEBUG_BUS_10__REG_SCLK1_VLD_MASK 0x8000
-#define CB_DEBUG_BUS_10__REG_SCLK1_VLD__SHIFT 0xf
-#define CB_DEBUG_BUS_10__MERGE_TILE_ONLY_VALID_READY_MASK 0x10000
-#define CB_DEBUG_BUS_10__MERGE_TILE_ONLY_VALID_READY__SHIFT 0x10
-#define CB_DEBUG_BUS_10__MERGE_TILE_ONLY_VALID_READYB_MASK 0x20000
-#define CB_DEBUG_BUS_10__MERGE_TILE_ONLY_VALID_READYB__SHIFT 0x11
-#define CB_DEBUG_BUS_10__FC_QUAD_RDLAT_FIFO_FULL_MASK 0x40000
-#define CB_DEBUG_BUS_10__FC_QUAD_RDLAT_FIFO_FULL__SHIFT 0x12
-#define CB_DEBUG_BUS_10__FC_TILE_RDLAT_FIFO_FULL_MASK 0x80000
-#define CB_DEBUG_BUS_10__FC_TILE_RDLAT_FIFO_FULL__SHIFT 0x13
-#define CB_DEBUG_BUS_10__FOP_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE_MASK 0x100000
-#define CB_DEBUG_BUS_10__FOP_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE__SHIFT 0x14
-#define CB_DEBUG_BUS_10__FOP_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE_MASK 0x200000
-#define CB_DEBUG_BUS_10__FOP_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE__SHIFT 0x15
-#define CB_DEBUG_BUS_10__FOP_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE_MASK 0x400000
-#define CB_DEBUG_BUS_10__FOP_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE__SHIFT 0x16
-#define CB_DEBUG_BUS_10__FOP_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE_MASK 0x800000
-#define CB_DEBUG_BUS_10__FOP_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE__SHIFT 0x17
-#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE_MASK 0x1
-#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE__SHIFT 0x0
-#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE_MASK 0x2
-#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE__SHIFT 0x1
-#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE_MASK 0x4
-#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE__SHIFT 0x2
-#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE_MASK 0x8
-#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE__SHIFT 0x3
-#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE_MASK 0x10
-#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE__SHIFT 0x4
-#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE_MASK 0x20
-#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE__SHIFT 0x5
-#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE_MASK 0x40
-#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE__SHIFT 0x6
-#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE_MASK 0x80
-#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE__SHIFT 0x7
-#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE_MASK 0x100
-#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE__SHIFT 0x8
-#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE_MASK 0x200
-#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE__SHIFT 0x9
-#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE_MASK 0x400
-#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE__SHIFT 0xa
-#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE_MASK 0x800
-#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE__SHIFT 0xb
-#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_1_FRAGMENT_MASK 0x1000
-#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_1_FRAGMENT__SHIFT 0xc
-#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_2_FRAGMENTS_MASK 0x2000
-#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_2_FRAGMENTS__SHIFT 0xd
-#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_3_FRAGMENTS_MASK 0x4000
-#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_3_FRAGMENTS__SHIFT 0xe
-#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_4_FRAGMENTS_MASK 0x8000
-#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_4_FRAGMENTS__SHIFT 0xf
-#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_5_FRAGMENTS_MASK 0x10000
-#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_5_FRAGMENTS__SHIFT 0x10
-#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_6_FRAGMENTS_MASK 0x20000
-#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_6_FRAGMENTS__SHIFT 0x11
-#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_7_FRAGMENTS_MASK 0x40000
-#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_7_FRAGMENTS__SHIFT 0x12
-#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_1_FRAGMENT_MASK 0x80000
-#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_1_FRAGMENT__SHIFT 0x13
-#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_2_FRAGMENTS_MASK 0x100000
-#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_2_FRAGMENTS__SHIFT 0x14
-#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_3_FRAGMENTS_MASK 0x200000
-#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_3_FRAGMENTS__SHIFT 0x15
-#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_4_FRAGMENTS_MASK 0x400000
-#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_4_FRAGMENTS__SHIFT 0x16
-#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_5_FRAGMENTS_MASK 0x800000
-#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_5_FRAGMENTS__SHIFT 0x17
-#define CB_DEBUG_BUS_12__FOP_QUAD_REMOVED_6_FRAGMENTS_MASK 0x1
-#define CB_DEBUG_BUS_12__FOP_QUAD_REMOVED_6_FRAGMENTS__SHIFT 0x0
-#define CB_DEBUG_BUS_12__FOP_QUAD_REMOVED_7_FRAGMENTS_MASK 0x2
-#define CB_DEBUG_BUS_12__FOP_QUAD_REMOVED_7_FRAGMENTS__SHIFT 0x1
-#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_0_MASK 0x4
-#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_0__SHIFT 0x2
-#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_1_MASK 0x8
-#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_1__SHIFT 0x3
-#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_2_MASK 0x10
-#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_2__SHIFT 0x4
-#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_3_MASK 0x20
-#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_3__SHIFT 0x5
-#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_4_MASK 0x40
-#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_4__SHIFT 0x6
-#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_5_MASK 0x80
-#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_5__SHIFT 0x7
-#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_6_MASK 0x100
-#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_6__SHIFT 0x8
-#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_7_MASK 0x200
-#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_7__SHIFT 0x9
-#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_0_MASK 0x400
-#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_0__SHIFT 0xa
-#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_1_MASK 0x800
-#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_1__SHIFT 0xb
-#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_2_MASK 0x1000
-#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_2__SHIFT 0xc
-#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_3_MASK 0x2000
-#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_3__SHIFT 0xd
-#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_4_MASK 0x4000
-#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_4__SHIFT 0xe
-#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_5_MASK 0x8000
-#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_5__SHIFT 0xf
-#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_6_MASK 0x10000
-#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_6__SHIFT 0x10
-#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_7_MASK 0x20000
-#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_7__SHIFT 0x11
-#define CB_DEBUG_BUS_12__FC_QUAD_BLEND_OPT_DONT_READ_DST_MASK 0x40000
-#define CB_DEBUG_BUS_12__FC_QUAD_BLEND_OPT_DONT_READ_DST__SHIFT 0x12
-#define CB_DEBUG_BUS_12__FC_QUAD_BLEND_OPT_BLEND_BYPASS_MASK 0x80000
-#define CB_DEBUG_BUS_12__FC_QUAD_BLEND_OPT_BLEND_BYPASS__SHIFT 0x13
-#define CB_DEBUG_BUS_12__FC_QUAD_BLEND_OPT_DISCARD_PIXELS_MASK 0x100000
-#define CB_DEBUG_BUS_12__FC_QUAD_BLEND_OPT_DISCARD_PIXELS__SHIFT 0x14
-#define CB_DEBUG_BUS_12__FC_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT_MASK 0x200000
-#define CB_DEBUG_BUS_12__FC_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT__SHIFT 0x15
-#define CB_DEBUG_BUS_12__FC_QUAD_KILLED_BY_COLOR_INVALID_MASK 0x400000
-#define CB_DEBUG_BUS_12__FC_QUAD_KILLED_BY_COLOR_INVALID__SHIFT 0x16
-#define CB_DEBUG_BUS_12__FC_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK_MASK 0x800000
-#define CB_DEBUG_BUS_12__FC_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK__SHIFT 0x17
-#define CB_DEBUG_BUS_13__FC_PF_FC_KEYID_RDLAT_FIFO_FULL_MASK 0x1
-#define CB_DEBUG_BUS_13__FC_PF_FC_KEYID_RDLAT_FIFO_FULL__SHIFT 0x0
-#define CB_DEBUG_BUS_13__FC_DOC_QTILE_CAM_MISS_MASK 0x2
-#define CB_DEBUG_BUS_13__FC_DOC_QTILE_CAM_MISS__SHIFT 0x1
-#define CB_DEBUG_BUS_13__FC_DOC_QTILE_CAM_HIT_MASK 0x4
-#define CB_DEBUG_BUS_13__FC_DOC_QTILE_CAM_HIT__SHIFT 0x2
-#define CB_DEBUG_BUS_13__FC_DOC_CLINE_CAM_MISS_MASK 0x8
-#define CB_DEBUG_BUS_13__FC_DOC_CLINE_CAM_MISS__SHIFT 0x3
-#define CB_DEBUG_BUS_13__FC_DOC_CLINE_CAM_HIT_MASK 0x10
-#define CB_DEBUG_BUS_13__FC_DOC_CLINE_CAM_HIT__SHIFT 0x4
-#define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_1_SECTOR_MASK 0x20
-#define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_1_SECTOR__SHIFT 0x5
-#define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_2_SECTORS_MASK 0x40
-#define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_2_SECTORS__SHIFT 0x6
-#define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_3_SECTORS_MASK 0x80
-#define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_3_SECTORS__SHIFT 0x7
-#define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_4_SECTORS_MASK 0x100
-#define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_4_SECTORS__SHIFT 0x8
-#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_HIT_MASK 0x200
-#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_HIT__SHIFT 0x9
-#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_TAG_MISS_MASK 0x400
-#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_TAG_MISS__SHIFT 0xa
-#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_SECTOR_MISS_MASK 0x800
-#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_SECTOR_MISS__SHIFT 0xb
-#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_REEVICTION_STALL_MASK 0x1000
-#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_REEVICTION_STALL__SHIFT 0xc
-#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL_MASK 0x2000
-#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL__SHIFT 0xd
-#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_REPLACE_PENDING_EVICT_STALL_MASK 0x4000
-#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_REPLACE_PENDING_EVICT_STALL__SHIFT 0xe
-#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL_MASK 0x8000
-#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL__SHIFT 0xf
-#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_READ_OUTPUT_STALL_MASK 0x10000
-#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_READ_OUTPUT_STALL__SHIFT 0x10
-#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_WRITE_OUTPUT_STALL_MASK 0x20000
-#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_WRITE_OUTPUT_STALL__SHIFT 0x11
-#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_ACK_OUTPUT_STALL_MASK 0x40000
-#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_ACK_OUTPUT_STALL__SHIFT 0x12
-#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_STALL_MASK 0x80000
-#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_STALL__SHIFT 0x13
-#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_FLUSH_MASK 0x100000
-#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_FLUSH__SHIFT 0x14
-#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_SECTORS_FLUSHED_MASK 0x200000
-#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_SECTORS_FLUSHED__SHIFT 0x15
-#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_DIRTY_SECTORS_FLUSHED_MASK 0x400000
-#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_DIRTY_SECTORS_FLUSHED__SHIFT 0x16
-#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_TAGS_FLUSHED_MASK 0x800000
-#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_TAGS_FLUSHED__SHIFT 0x17
-#define CB_DEBUG_BUS_14__FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT_MASK 0x7ff
-#define CB_DEBUG_BUS_14__FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT__SHIFT 0x0
-#define CB_DEBUG_BUS_14__FC_MC_DCC_READ_REQUESTS_IN_FLIGHT_MASK 0x3ff800
-#define CB_DEBUG_BUS_14__FC_MC_DCC_READ_REQUESTS_IN_FLIGHT__SHIFT 0xb
-#define CB_DEBUG_BUS_14__CC_PF_DCC_BEYOND_TILE_SPLIT_MASK 0x400000
-#define CB_DEBUG_BUS_14__CC_PF_DCC_BEYOND_TILE_SPLIT__SHIFT 0x16
-#define CB_DEBUG_BUS_14__CC_PF_DCC_RDREQ_STALL_MASK 0x800000
-#define CB_DEBUG_BUS_14__CC_PF_DCC_RDREQ_STALL__SHIFT 0x17
-#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_2TO1_MASK 0x7
-#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_2TO1__SHIFT 0x0
-#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_4TO1_MASK 0x18
-#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_4TO1__SHIFT 0x3
-#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_4TO2_MASK 0x60
-#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_4TO2__SHIFT 0x5
-#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_4TO3_MASK 0x180
-#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_4TO3__SHIFT 0x7
-#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO1_MASK 0x600
-#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO1__SHIFT 0x9
-#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO2_MASK 0x1800
-#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO2__SHIFT 0xb
-#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO3_MASK 0x6000
-#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO3__SHIFT 0xd
-#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO4_MASK 0x18000
-#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO4__SHIFT 0xf
-#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO5_MASK 0x60000
-#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO5__SHIFT 0x11
-#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO1_MASK 0x1
-#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO1__SHIFT 0x0
-#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO2_MASK 0x2
-#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO2__SHIFT 0x1
-#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO3_MASK 0x4
-#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO3__SHIFT 0x2
-#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO4_MASK 0x8
-#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO4__SHIFT 0x3
-#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO5_MASK 0x10
-#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO5__SHIFT 0x4
-#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO6_MASK 0x20
-#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO6__SHIFT 0x5
-#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO7_MASK 0x40
-#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO7__SHIFT 0x6
-#define CB_DEBUG_BUS_17__TILE_INTFC_BUSY_MASK 0x1
-#define CB_DEBUG_BUS_17__TILE_INTFC_BUSY__SHIFT 0x0
-#define CB_DEBUG_BUS_17__MU_BUSY_MASK 0x2
-#define CB_DEBUG_BUS_17__MU_BUSY__SHIFT 0x1
-#define CB_DEBUG_BUS_17__TQ_BUSY_MASK 0x4
-#define CB_DEBUG_BUS_17__TQ_BUSY__SHIFT 0x2
-#define CB_DEBUG_BUS_17__AC_BUSY_MASK 0x8
-#define CB_DEBUG_BUS_17__AC_BUSY__SHIFT 0x3
-#define CB_DEBUG_BUS_17__CRW_BUSY_MASK 0x10
-#define CB_DEBUG_BUS_17__CRW_BUSY__SHIFT 0x4
-#define CB_DEBUG_BUS_17__CACHE_CTRL_BUSY_MASK 0x20
-#define CB_DEBUG_BUS_17__CACHE_CTRL_BUSY__SHIFT 0x5
-#define CB_DEBUG_BUS_17__MC_WR_PENDING_MASK 0x40
-#define CB_DEBUG_BUS_17__MC_WR_PENDING__SHIFT 0x6
-#define CB_DEBUG_BUS_17__FC_WR_PENDING_MASK 0x80
-#define CB_DEBUG_BUS_17__FC_WR_PENDING__SHIFT 0x7
-#define CB_DEBUG_BUS_17__FC_RD_PENDING_MASK 0x100
-#define CB_DEBUG_BUS_17__FC_RD_PENDING__SHIFT 0x8
-#define CB_DEBUG_BUS_17__EVICT_PENDING_MASK 0x200
-#define CB_DEBUG_BUS_17__EVICT_PENDING__SHIFT 0x9
-#define CB_DEBUG_BUS_17__LAST_RD_ARB_WINNER_MASK 0x400
-#define CB_DEBUG_BUS_17__LAST_RD_ARB_WINNER__SHIFT 0xa
-#define CB_DEBUG_BUS_17__MU_STATE_MASK 0x7f800
-#define CB_DEBUG_BUS_17__MU_STATE__SHIFT 0xb
-#define CB_DEBUG_BUS_18__TILE_RETIREMENT_BUSY_MASK 0x1
-#define CB_DEBUG_BUS_18__TILE_RETIREMENT_BUSY__SHIFT 0x0
-#define CB_DEBUG_BUS_18__FOP_BUSY_MASK 0x2
-#define CB_DEBUG_BUS_18__FOP_BUSY__SHIFT 0x1
-#define CB_DEBUG_BUS_18__CLEAR_BUSY_MASK 0x4
-#define CB_DEBUG_BUS_18__CLEAR_BUSY__SHIFT 0x2
-#define CB_DEBUG_BUS_18__LAT_BUSY_MASK 0x8
-#define CB_DEBUG_BUS_18__LAT_BUSY__SHIFT 0x3
-#define CB_DEBUG_BUS_18__CACHE_CTL_BUSY_MASK 0x10
-#define CB_DEBUG_BUS_18__CACHE_CTL_BUSY__SHIFT 0x4
-#define CB_DEBUG_BUS_18__ADDR_BUSY_MASK 0x20
-#define CB_DEBUG_BUS_18__ADDR_BUSY__SHIFT 0x5
-#define CB_DEBUG_BUS_18__MERGE_BUSY_MASK 0x40
-#define CB_DEBUG_BUS_18__MERGE_BUSY__SHIFT 0x6
-#define CB_DEBUG_BUS_18__QUAD_BUSY_MASK 0x80
-#define CB_DEBUG_BUS_18__QUAD_BUSY__SHIFT 0x7
-#define CB_DEBUG_BUS_18__TILE_BUSY_MASK 0x100
-#define CB_DEBUG_BUS_18__TILE_BUSY__SHIFT 0x8
-#define CB_DEBUG_BUS_18__DCC_BUSY_MASK 0x200
-#define CB_DEBUG_BUS_18__DCC_BUSY__SHIFT 0x9
-#define CB_DEBUG_BUS_18__DOC_BUSY_MASK 0x400
-#define CB_DEBUG_BUS_18__DOC_BUSY__SHIFT 0xa
-#define CB_DEBUG_BUS_18__DAG_BUSY_MASK 0x800
-#define CB_DEBUG_BUS_18__DAG_BUSY__SHIFT 0xb
-#define CB_DEBUG_BUS_18__DOC_STALL_MASK 0x1000
-#define CB_DEBUG_BUS_18__DOC_STALL__SHIFT 0xc
-#define CB_DEBUG_BUS_18__DOC_QT_CAM_FULL_MASK 0x2000
-#define CB_DEBUG_BUS_18__DOC_QT_CAM_FULL__SHIFT 0xd
-#define CB_DEBUG_BUS_18__DOC_CL_CAM_FULL_MASK 0x4000
-#define CB_DEBUG_BUS_18__DOC_CL_CAM_FULL__SHIFT 0xe
-#define CB_DEBUG_BUS_18__DOC_QUAD_PTR_FIFO_FULL_MASK 0x8000
-#define CB_DEBUG_BUS_18__DOC_QUAD_PTR_FIFO_FULL__SHIFT 0xf
-#define CB_DEBUG_BUS_18__DOC_SECTOR_MASK_FIFO_FULL_MASK 0x10000
-#define CB_DEBUG_BUS_18__DOC_SECTOR_MASK_FIFO_FULL__SHIFT 0x10
-#define CB_DEBUG_BUS_18__DCS_READ_WINNER_LAST_MASK 0x20000
-#define CB_DEBUG_BUS_18__DCS_READ_WINNER_LAST__SHIFT 0x11
-#define CB_DEBUG_BUS_18__DCS_READ_EV_PENDING_MASK 0x40000
-#define CB_DEBUG_BUS_18__DCS_READ_EV_PENDING__SHIFT 0x12
-#define CB_DEBUG_BUS_18__DCS_WRITE_CC_PENDING_MASK 0x80000
-#define CB_DEBUG_BUS_18__DCS_WRITE_CC_PENDING__SHIFT 0x13
-#define CB_DEBUG_BUS_18__DCS_READ_CC_PENDING_MASK 0x100000
-#define CB_DEBUG_BUS_18__DCS_READ_CC_PENDING__SHIFT 0x14
-#define CB_DEBUG_BUS_18__DCS_WRITE_MC_PENDING_MASK 0x200000
-#define CB_DEBUG_BUS_18__DCS_WRITE_MC_PENDING__SHIFT 0x15
-#define CB_DEBUG_BUS_19__SURF_SYNC_STATE_MASK 0x3
-#define CB_DEBUG_BUS_19__SURF_SYNC_STATE__SHIFT 0x0
-#define CB_DEBUG_BUS_19__SURF_SYNC_START_MASK 0x4
-#define CB_DEBUG_BUS_19__SURF_SYNC_START__SHIFT 0x2
-#define CB_DEBUG_BUS_19__SF_BUSY_MASK 0x8
-#define CB_DEBUG_BUS_19__SF_BUSY__SHIFT 0x3
-#define CB_DEBUG_BUS_19__CS_BUSY_MASK 0x10
-#define CB_DEBUG_BUS_19__CS_BUSY__SHIFT 0x4
-#define CB_DEBUG_BUS_19__RB_BUSY_MASK 0x20
-#define CB_DEBUG_BUS_19__RB_BUSY__SHIFT 0x5
-#define CB_DEBUG_BUS_19__DS_BUSY_MASK 0x40
-#define CB_DEBUG_BUS_19__DS_BUSY__SHIFT 0x6
-#define CB_DEBUG_BUS_19__TB_BUSY_MASK 0x80
-#define CB_DEBUG_BUS_19__TB_BUSY__SHIFT 0x7
-#define CB_DEBUG_BUS_19__IB_BUSY_MASK 0x100
-#define CB_DEBUG_BUS_19__IB_BUSY__SHIFT 0x8
-#define CB_DEBUG_BUS_19__DRR_BUSY_MASK 0x200
-#define CB_DEBUG_BUS_19__DRR_BUSY__SHIFT 0x9
-#define CB_DEBUG_BUS_19__DF_BUSY_MASK 0x400
-#define CB_DEBUG_BUS_19__DF_BUSY__SHIFT 0xa
-#define CB_DEBUG_BUS_19__DD_BUSY_MASK 0x800
-#define CB_DEBUG_BUS_19__DD_BUSY__SHIFT 0xb
-#define CB_DEBUG_BUS_19__DC_BUSY_MASK 0x1000
-#define CB_DEBUG_BUS_19__DC_BUSY__SHIFT 0xc
-#define CB_DEBUG_BUS_19__DK_BUSY_MASK 0x2000
-#define CB_DEBUG_BUS_19__DK_BUSY__SHIFT 0xd
-#define CB_DEBUG_BUS_19__DF_SKID_FIFO_EMPTY_MASK 0x4000
-#define CB_DEBUG_BUS_19__DF_SKID_FIFO_EMPTY__SHIFT 0xe
-#define CB_DEBUG_BUS_19__DF_CLEAR_FIFO_EMPTY_MASK 0x8000
-#define CB_DEBUG_BUS_19__DF_CLEAR_FIFO_EMPTY__SHIFT 0xf
-#define CB_DEBUG_BUS_19__DD_READY_MASK 0x10000
-#define CB_DEBUG_BUS_19__DD_READY__SHIFT 0x10
-#define CB_DEBUG_BUS_19__DC_FIFO_FULL_MASK 0x20000
-#define CB_DEBUG_BUS_19__DC_FIFO_FULL__SHIFT 0x11
-#define CB_DEBUG_BUS_19__DC_READY_MASK 0x40000
-#define CB_DEBUG_BUS_19__DC_READY__SHIFT 0x12
-#define CB_DEBUG_BUS_20__MC_RDREQ_CREDITS_MASK 0x3f
-#define CB_DEBUG_BUS_20__MC_RDREQ_CREDITS__SHIFT 0x0
-#define CB_DEBUG_BUS_20__MC_WRREQ_CREDITS_MASK 0xfc0
-#define CB_DEBUG_BUS_20__MC_WRREQ_CREDITS__SHIFT 0x6
-#define CB_DEBUG_BUS_20__CC_RDREQ_HAD_ITS_TURN_MASK 0x1000
-#define CB_DEBUG_BUS_20__CC_RDREQ_HAD_ITS_TURN__SHIFT 0xc
-#define CB_DEBUG_BUS_20__FC_RDREQ_HAD_ITS_TURN_MASK 0x2000
-#define CB_DEBUG_BUS_20__FC_RDREQ_HAD_ITS_TURN__SHIFT 0xd
-#define CB_DEBUG_BUS_20__CM_RDREQ_HAD_ITS_TURN_MASK 0x4000
-#define CB_DEBUG_BUS_20__CM_RDREQ_HAD_ITS_TURN__SHIFT 0xe
-#define CB_DEBUG_BUS_20__CC_WRREQ_HAD_ITS_TURN_MASK 0x10000
-#define CB_DEBUG_BUS_20__CC_WRREQ_HAD_ITS_TURN__SHIFT 0x10
-#define CB_DEBUG_BUS_20__FC_WRREQ_HAD_ITS_TURN_MASK 0x20000
-#define CB_DEBUG_BUS_20__FC_WRREQ_HAD_ITS_TURN__SHIFT 0x11
-#define CB_DEBUG_BUS_20__CM_WRREQ_HAD_ITS_TURN_MASK 0x40000
-#define CB_DEBUG_BUS_20__CM_WRREQ_HAD_ITS_TURN__SHIFT 0x12
-#define CB_DEBUG_BUS_20__CC_WRREQ_FIFO_EMPTY_MASK 0x100000
-#define CB_DEBUG_BUS_20__CC_WRREQ_FIFO_EMPTY__SHIFT 0x14
-#define CB_DEBUG_BUS_20__FC_WRREQ_FIFO_EMPTY_MASK 0x200000
-#define CB_DEBUG_BUS_20__FC_WRREQ_FIFO_EMPTY__SHIFT 0x15
-#define CB_DEBUG_BUS_20__CM_WRREQ_FIFO_EMPTY_MASK 0x400000
-#define CB_DEBUG_BUS_20__CM_WRREQ_FIFO_EMPTY__SHIFT 0x16
-#define CB_DEBUG_BUS_20__DCC_WRREQ_FIFO_EMPTY_MASK 0x800000
-#define CB_DEBUG_BUS_20__DCC_WRREQ_FIFO_EMPTY__SHIFT 0x17
-#define CB_DEBUG_BUS_21__CM_BUSY_MASK 0x1
-#define CB_DEBUG_BUS_21__CM_BUSY__SHIFT 0x0
-#define CB_DEBUG_BUS_21__FC_BUSY_MASK 0x2
-#define CB_DEBUG_BUS_21__FC_BUSY__SHIFT 0x1
-#define CB_DEBUG_BUS_21__CC_BUSY_MASK 0x4
-#define CB_DEBUG_BUS_21__CC_BUSY__SHIFT 0x2
-#define CB_DEBUG_BUS_21__BB_BUSY_MASK 0x8
-#define CB_DEBUG_BUS_21__BB_BUSY__SHIFT 0x3
-#define CB_DEBUG_BUS_21__MA_BUSY_MASK 0x10
-#define CB_DEBUG_BUS_21__MA_BUSY__SHIFT 0x4
-#define CB_DEBUG_BUS_21__CORE_SCLK_VLD_MASK 0x20
-#define CB_DEBUG_BUS_21__CORE_SCLK_VLD__SHIFT 0x5
-#define CB_DEBUG_BUS_21__REG_SCLK1_VLD_MASK 0x40
-#define CB_DEBUG_BUS_21__REG_SCLK1_VLD__SHIFT 0x6
-#define CB_DEBUG_BUS_21__REG_SCLK0_VLD_MASK 0x80
-#define CB_DEBUG_BUS_21__REG_SCLK0_VLD__SHIFT 0x7
-#define CB_DEBUG_BUS_22__OUTSTANDING_MC_READS_MASK 0xfff
-#define CB_DEBUG_BUS_22__OUTSTANDING_MC_READS__SHIFT 0x0
-#define CB_DEBUG_BUS_22__OUTSTANDING_MC_WRITES_MASK 0xfff000
-#define CB_DEBUG_BUS_22__OUTSTANDING_MC_WRITES__SHIFT 0xc
-#define CP_DFY_CNTL__POLICY_MASK 0x1
-#define CP_DFY_CNTL__POLICY__SHIFT 0x0
-#define CP_DFY_CNTL__MTYPE_MASK 0xc
-#define CP_DFY_CNTL__MTYPE__SHIFT 0x2
-#define CP_DFY_CNTL__LFSR_RESET_MASK 0x10000000
-#define CP_DFY_CNTL__LFSR_RESET__SHIFT 0x1c
-#define CP_DFY_CNTL__MODE_MASK 0x60000000
-#define CP_DFY_CNTL__MODE__SHIFT 0x1d
-#define CP_DFY_CNTL__ENABLE_MASK 0x80000000
-#define CP_DFY_CNTL__ENABLE__SHIFT 0x1f
-#define CP_DFY_STAT__BURST_COUNT_MASK 0xffff
-#define CP_DFY_STAT__BURST_COUNT__SHIFT 0x0
-#define CP_DFY_STAT__TAGS_PENDING_MASK 0x1ff0000
-#define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x10
-#define CP_DFY_STAT__BUSY_MASK 0x80000000
-#define CP_DFY_STAT__BUSY__SHIFT 0x1f
-#define CP_DFY_ADDR_HI__ADDR_HI_MASK 0xffffffff
-#define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x0
-#define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xffffffe0
-#define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x5
-#define CP_DFY_DATA_0__DATA_MASK 0xffffffff
-#define CP_DFY_DATA_0__DATA__SHIFT 0x0
-#define CP_DFY_DATA_1__DATA_MASK 0xffffffff
-#define CP_DFY_DATA_1__DATA__SHIFT 0x0
-#define CP_DFY_DATA_2__DATA_MASK 0xffffffff
-#define CP_DFY_DATA_2__DATA__SHIFT 0x0
-#define CP_DFY_DATA_3__DATA_MASK 0xffffffff
-#define CP_DFY_DATA_3__DATA__SHIFT 0x0
-#define CP_DFY_DATA_4__DATA_MASK 0xffffffff
-#define CP_DFY_DATA_4__DATA__SHIFT 0x0
-#define CP_DFY_DATA_5__DATA_MASK 0xffffffff
-#define CP_DFY_DATA_5__DATA__SHIFT 0x0
-#define CP_DFY_DATA_6__DATA_MASK 0xffffffff
-#define CP_DFY_DATA_6__DATA__SHIFT 0x0
-#define CP_DFY_DATA_7__DATA_MASK 0xffffffff
-#define CP_DFY_DATA_7__DATA__SHIFT 0x0
-#define CP_DFY_DATA_8__DATA_MASK 0xffffffff
-#define CP_DFY_DATA_8__DATA__SHIFT 0x0
-#define CP_DFY_DATA_9__DATA_MASK 0xffffffff
-#define CP_DFY_DATA_9__DATA__SHIFT 0x0
-#define CP_DFY_DATA_10__DATA_MASK 0xffffffff
-#define CP_DFY_DATA_10__DATA__SHIFT 0x0
-#define CP_DFY_DATA_11__DATA_MASK 0xffffffff
-#define CP_DFY_DATA_11__DATA__SHIFT 0x0
-#define CP_DFY_DATA_12__DATA_MASK 0xffffffff
-#define CP_DFY_DATA_12__DATA__SHIFT 0x0
-#define CP_DFY_DATA_13__DATA_MASK 0xffffffff
-#define CP_DFY_DATA_13__DATA__SHIFT 0x0
-#define CP_DFY_DATA_14__DATA_MASK 0xffffffff
-#define CP_DFY_DATA_14__DATA__SHIFT 0x0
-#define CP_DFY_DATA_15__DATA_MASK 0xffffffff
-#define CP_DFY_DATA_15__DATA__SHIFT 0x0
-#define CP_DFY_CMD__OFFSET_MASK 0x1ff
-#define CP_DFY_CMD__OFFSET__SHIFT 0x0
-#define CP_DFY_CMD__SIZE_MASK 0xffff0000
-#define CP_DFY_CMD__SIZE__SHIFT 0x10
-#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0xff
-#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0
-#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0xff00
-#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8
-#define CP_ATCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x3ff
-#define CP_ATCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
-#define CP_RB0_BASE__RB_BASE_MASK 0xffffffff
-#define CP_RB0_BASE__RB_BASE__SHIFT 0x0
-#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0xff
-#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0
-#define CP_RB_BASE__RB_BASE_MASK 0xffffffff
-#define CP_RB_BASE__RB_BASE__SHIFT 0x0
-#define CP_RB1_BASE__RB_BASE_MASK 0xffffffff
-#define CP_RB1_BASE__RB_BASE__SHIFT 0x0
-#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0xff
-#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0
-#define CP_RB2_BASE__RB_BASE_MASK 0xffffffff
-#define CP_RB2_BASE__RB_BASE__SHIFT 0x0
-#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x3f
-#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0
-#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x3f00
-#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8
-#define CP_RB0_CNTL__MTYPE_MASK 0x18000
-#define CP_RB0_CNTL__MTYPE__SHIFT 0xf
-#define CP_RB0_CNTL__BUF_SWAP_MASK 0x60000
-#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x11
-#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x300000
-#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14
-#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
-#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
-#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x1000000
-#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18
-#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x8000000
-#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b
-#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
-#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
-#define CP_RB_CNTL__RB_BUFSZ_MASK 0x3f
-#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0
-#define CP_RB_CNTL__RB_BLKSZ_MASK 0x3f00
-#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8
-#define CP_RB_CNTL__MTYPE_MASK 0x18000
-#define CP_RB_CNTL__MTYPE__SHIFT 0xf
-#define CP_RB_CNTL__BUF_SWAP_MASK 0x60000
-#define CP_RB_CNTL__BUF_SWAP__SHIFT 0x11
-#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x300000
-#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14
-#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
-#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
-#define CP_RB_CNTL__CACHE_POLICY_MASK 0x1000000
-#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18
-#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x8000000
-#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b
-#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
-#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
-#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x3f
-#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0
-#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x3f00
-#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8
-#define CP_RB1_CNTL__MTYPE_MASK 0x18000
-#define CP_RB1_CNTL__MTYPE__SHIFT 0xf
-#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x300000
-#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14
-#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
-#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
-#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x1000000
-#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18
-#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x8000000
-#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b
-#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
-#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
-#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x3f
-#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0
-#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x3f00
-#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8
-#define CP_RB2_CNTL__MTYPE_MASK 0x18000
-#define CP_RB2_CNTL__MTYPE__SHIFT 0xf
-#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x300000
-#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14
-#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
-#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
-#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x1000000
-#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18
-#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x8000000
-#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b
-#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
-#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
-#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0xfffff
-#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0
-#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
-#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
-#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
-#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
-#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
-#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
-#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
-#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
-#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
-#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
-#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
-#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
-#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
-#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
-#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
-#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
-#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
-#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
-#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
-#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
-#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
-#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
-#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
-#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
-#define CP_RB0_WPTR__RB_WPTR_MASK 0xfffff
-#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0
-#define CP_RB_WPTR__RB_WPTR_MASK 0xfffff
-#define CP_RB_WPTR__RB_WPTR__SHIFT 0x0
-#define CP_RB1_WPTR__RB_WPTR_MASK 0xfffff
-#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0
-#define CP_RB2_WPTR__RB_WPTR_MASK 0xfffff
-#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0
-#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xfffffffc
-#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2
-#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0xff
-#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0
-#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
-#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
-#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
-#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
-#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK 0x40000
-#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT 0x12
-#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x80000
-#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
-#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
-#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
-#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK 0x200000
-#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT 0x15
-#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x400000
-#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
-#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
-#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
-#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
-#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
-#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
-#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
-#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
-#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
-#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
-#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
-#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
-#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK 0x40000
-#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT 0x12
-#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x80000
-#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
-#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
-#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
-#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK 0x200000
-#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT 0x15
-#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000
-#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
-#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000
-#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
-#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x4000000
-#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
-#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000
-#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000
-#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000
-#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
-#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
-#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
-#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
-#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK 0x40000
-#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT 0x12
-#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x80000
-#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
-#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
-#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
-#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK 0x200000
-#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT 0x15
-#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x400000
-#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
-#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x800000
-#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
-#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x4000000
-#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
-#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000
-#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000
-#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000
-#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
-#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
-#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
-#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
-#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK 0x40000
-#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT 0x12
-#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x80000
-#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
-#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
-#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
-#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK 0x200000
-#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT 0x15
-#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x400000
-#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
-#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x800000
-#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
-#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x4000000
-#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
-#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000
-#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000
-#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000
-#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
-#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
-#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x4000
-#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
-#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
-#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
-#define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK 0x40000
-#define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT 0x12
-#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x80000
-#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13
-#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x100000
-#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14
-#define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x200000
-#define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT 0x15
-#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x400000
-#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16
-#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x800000
-#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17
-#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x1000000
-#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18
-#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x4000000
-#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a
-#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
-#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
-#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000
-#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d
-#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000
-#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e
-#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000
-#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f
-#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
-#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
-#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x4000
-#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
-#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
-#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
-#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK 0x40000
-#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT 0x12
-#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK 0x80000
-#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT 0x13
-#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x100000
-#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14
-#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK 0x200000
-#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT 0x15
-#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x400000
-#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16
-#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x800000
-#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17
-#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x1000000
-#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18
-#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x4000000
-#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a
-#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
-#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
-#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000
-#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d
-#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000
-#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e
-#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000
-#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f
-#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
-#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
-#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x4000
-#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
-#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
-#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
-#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK 0x40000
-#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT 0x12
-#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x80000
-#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13
-#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x100000
-#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14
-#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK 0x200000
-#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT 0x15
-#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x400000
-#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16
-#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x800000
-#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17
-#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x1000000
-#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18
-#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x4000000
-#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a
-#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
-#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
-#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000
-#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d
-#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000
-#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e
-#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000
-#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f
-#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
-#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
-#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x4000
-#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
-#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
-#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
-#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK 0x40000
-#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT 0x12
-#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x80000
-#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13
-#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x100000
-#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14
-#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK 0x200000
-#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT 0x15
-#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x400000
-#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16
-#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x800000
-#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17
-#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x1000000
-#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18
-#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x4000000
-#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a
-#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
-#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
-#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000
-#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d
-#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000
-#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e
-#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000
-#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f
-#define CP_DEVICE_ID__DEVICE_ID_MASK 0xff
-#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0
-#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
-#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
-#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
-#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
-#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
-#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
-#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
-#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
-#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
-#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
-#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
-#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
-#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
-#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
-#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
-#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
-#define CP_RING0_PRIORITY__PRIORITY_MASK 0x3
-#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x3
-#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_RING1_PRIORITY__PRIORITY_MASK 0x3
-#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x3
-#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_RING2_PRIORITY__PRIORITY_MASK 0x3
-#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x3
-#define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_ENDIAN_SWAP__ENDIAN_SWAP_MASK 0x3
-#define CP_ENDIAN_SWAP__ENDIAN_SWAP__SHIFT 0x0
-#define CP_RB_VMID__RB0_VMID_MASK 0xf
-#define CP_RB_VMID__RB0_VMID__SHIFT 0x0
-#define CP_RB_VMID__RB1_VMID_MASK 0xf00
-#define CP_RB_VMID__RB1_VMID__SHIFT 0x8
-#define CP_RB_VMID__RB2_VMID_MASK 0xf0000
-#define CP_RB_VMID__RB2_VMID__SHIFT 0x10
-#define CP_ME0_PIPE0_VMID__VMID_MASK 0xf
-#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0
-#define CP_ME0_PIPE1_VMID__VMID_MASK 0xf
-#define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0
-#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc
-#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
-#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000
-#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
-#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000
-#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
-#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x7ffffc
-#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2
-#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x7ffffc
-#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2
-#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x7ffffc
-#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2
-#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x7ffffc
-#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2
-#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x1fff
-#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
-#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
-#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0
-#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x1fff
-#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0
-#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x1fff
-#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0
-#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffff
-#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0
-#define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0xf
-#define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
-#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000
-#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
-#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
-#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
-#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
-#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
-#define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0xf
-#define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
-#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000
-#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
-#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
-#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
-#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
-#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
-#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0xf
-#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
-#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000
-#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
-#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
-#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
-#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
-#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
-#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
-#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
-#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
-#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0
-#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x1ffff
-#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
-#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
-#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0
-#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x1ffff
-#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
-#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
-#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0
-#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
-#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
-#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
-#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
-#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
-#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
-#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x1
-#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0
-#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK 0x2
-#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1
-#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x4
-#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2
-#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x8
-#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3
-#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x10
-#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4
-#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x20
-#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5
-#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x40
-#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6
-#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x80
-#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7
-#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x100
-#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8
-#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK 0x200
-#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9
-#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x1
-#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0
-#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK 0x2
-#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1
-#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x4
-#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2
-#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x8
-#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3
-#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x10
-#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4
-#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x20
-#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5
-#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x40
-#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6
-#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x80
-#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7
-#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x100
-#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8
-#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK 0x200
-#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9
-#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x1
-#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT 0x0
-#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x2
-#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT 0x1
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK 0x100
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK 0x200
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x400
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK 0x800
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT 0xb
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x10000
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK 0x20000
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT 0x11
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x40000
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT 0x12
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x80000
-#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13
-#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x1
-#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0
-#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x2
-#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1
-#define CP_MEM_SLP_CNTL__RESERVED_MASK 0x7c
-#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
-#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK 0x80
-#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT 0x7
-#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0xff00
-#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8
-#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0xff0000
-#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10
-#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000
-#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
-#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x3
-#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0
-#define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK 0xf0
-#define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT 0x4
-#define CP_ECC_FIRSTOCCURRENCE__ME_MASK 0x300
-#define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT 0x8
-#define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK 0xc00
-#define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa
-#define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK 0x7000
-#define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT 0xc
-#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0xf0000
-#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10
-#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK 0xffffffff
-#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT 0x0
-#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK 0xffffffff
-#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT 0x0
-#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK 0xffffffff
-#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT 0x0
-#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0xff
-#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0
-#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000
-#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e
-#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000
-#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f
-#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xffffffff
-#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0
-#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
-#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
-#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
-#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
-#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
-#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
-#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
-#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
-#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
-#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
-#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
-#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
-#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
-#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
-#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
-#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
-#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
-#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
-#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
-#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
-#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
-#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
-#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
-#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
-#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
-#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
-#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
-#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
-#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
-#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
-#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
-#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
-#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
-#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
-#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
-#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
-#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
-#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
-#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
-#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
-#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
-#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
-#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
-#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
-#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
-#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
-#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
-#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
-#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
-#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
-#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
-#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
-#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
-#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
-#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
-#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
-#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
-#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
-#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
-#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
-#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
-#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
-#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
-#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
-#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
-#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
-#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
-#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
-#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
-#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
-#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
-#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
-#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
-#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
-#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
-#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
-#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
-#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
-#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
-#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
-#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
-#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
-#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
-#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
-#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
-#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
-#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
-#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
-#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
-#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
-#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
-#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
-#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
-#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
-#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
-#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
-#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
-#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
-#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
-#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
-#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
-#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
-#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
-#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
-#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
-#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
-#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
-#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
-#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
-#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
-#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
-#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
-#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
-#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
-#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
-#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
-#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
-#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
-#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
-#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
-#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
-#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
-#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
-#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
-#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
-#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
-#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
-#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
-#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
-#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
-#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
-#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
-#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
-#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
-#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
-#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
-#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
-#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
-#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
-#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
-#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
-#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
-#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
-#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
-#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
-#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
-#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
-#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
-#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
-#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
-#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
-#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
-#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
-#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
-#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
-#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
-#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
-#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
-#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
-#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
-#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
-#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
-#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
-#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
-#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
-#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
-#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
-#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
-#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
-#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
-#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
-#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
-#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
-#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
-#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
-#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
-#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
-#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
-#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
-#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
-#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
-#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
-#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
-#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
-#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
-#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
-#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
-#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
-#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
-#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
-#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
-#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
-#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
-#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
-#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
-#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
-#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
-#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
-#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
-#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
-#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
-#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
-#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
-#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
-#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
-#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
-#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
-#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
-#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
-#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
-#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
-#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
-#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
-#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
-#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
-#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
-#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
-#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
-#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
-#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
-#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
-#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
-#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
-#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
-#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
-#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
-#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
-#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
-#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
-#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
-#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
-#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
-#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
-#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
-#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
-#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
-#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
-#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
-#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
-#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
-#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
-#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
-#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
-#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
-#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
-#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
-#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
-#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
-#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
-#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
-#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
-#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
-#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
-#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
-#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
-#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
-#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
-#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
-#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
-#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
-#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
-#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
-#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
-#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
-#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
-#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
-#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
-#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
-#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
-#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
-#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
-#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
-#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
-#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
-#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
-#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
-#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
-#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
-#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
-#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
-#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
-#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
-#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
-#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
-#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
-#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
-#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
-#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
-#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
-#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
-#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
-#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
-#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
-#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
-#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
-#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
-#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
-#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
-#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
-#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
-#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
-#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
-#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
-#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
-#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
-#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
-#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
-#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
-#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
-#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
-#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
-#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
-#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
-#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
-#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
-#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
-#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
-#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
-#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
-#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
-#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
-#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
-#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
-#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
-#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
-#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
-#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
-#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
-#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
-#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
-#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
-#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
-#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
-#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
-#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
-#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
-#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
-#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
-#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
-#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
-#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
-#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
-#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
-#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
-#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
-#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
-#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
-#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
-#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
-#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
-#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
-#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
-#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
-#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
-#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
-#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
-#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
-#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
-#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
-#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
-#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x1000
-#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc
-#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000
-#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd
-#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
-#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
-#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x8000
-#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
-#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
-#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
-#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
-#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
-#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
-#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
-#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
-#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
-#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
-#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
-#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
-#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
-#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
-#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
-#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
-#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
-#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x1000
-#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc
-#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000
-#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd
-#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
-#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
-#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x8000
-#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
-#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
-#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
-#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
-#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
-#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
-#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
-#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
-#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
-#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
-#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
-#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
-#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
-#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
-#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
-#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
-#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
-#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
-#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
-#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
-#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
-#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
-#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
-#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
-#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
-#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x3
-#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x3
-#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x3
-#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x3
-#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
-#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
-#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
-#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
-#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
-#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
-#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
-#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
-#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x3
-#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x3
-#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x3
-#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x3
-#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
-#define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x7ff
-#define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0
-#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0xfff
-#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0
-#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0xfff
-#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0
-#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0xffff
-#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0
-#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0xffff
-#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0
-#define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x7ff
-#define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0
-#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0xfff
-#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0
-#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0xfff
-#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0
-#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0xffff
-#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0
-#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0xffff
-#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0
-#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x7
-#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x0
-#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x70
-#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4
-#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x70000
-#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x10
-#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x700000
-#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14
-#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x7
-#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0
-#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0xff
-#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0
-#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0xff00
-#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8
-#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0xff0000
-#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10
-#define CP_IQ_WAIT_TIME1__GWS_MASK 0xff000000
-#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18
-#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0xff
-#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0
-#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0xff00
-#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8
-#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0xff0000
-#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10
-#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xff000000
-#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18
-#define CP_VMID_RESET__RESET_REQUEST_MASK 0xffff
-#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0
-#define CP_VMID_RESET__RESET_STATUS_MASK 0xffff0000
-#define CP_VMID_RESET__RESET_STATUS__SHIFT 0x10
-#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0xffff
-#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0
-#define CP_VMID_PREEMPT__VIRT_COMMAND_MASK 0xf0000
-#define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT 0x10
-#define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0xffff
-#define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT 0x0
-#define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xffff0000
-#define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10
-#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xfffffff
-#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0
-#define CPC_INT_CNTX_ID__QUEUE_ID_MASK 0x70000000
-#define CPC_INT_CNTX_ID__QUEUE_ID__SHIFT 0x1c
-#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x1
-#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0
-#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x2
-#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1
-#define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK 0xfffff000
-#define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc
-#define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK 0xffff
-#define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0
-#define CP_CPC_IC_BASE_CNTL__VMID_MASK 0xf
-#define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0
-#define CP_CPC_IC_BASE_CNTL__ATC_MASK 0x800000
-#define CP_CPC_IC_BASE_CNTL__ATC__SHIFT 0x17
-#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK 0x1000000
-#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18
-#define CP_CPC_IC_BASE_CNTL__MTYPE_MASK 0x18000000
-#define CP_CPC_IC_BASE_CNTL__MTYPE__SHIFT 0x1b
-#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x1
-#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0
-#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK 0x10
-#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4
-#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x20
-#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5
-#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x1
-#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0
-#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x2
-#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1
-#define CP_CPC_STATUS__DC0_BUSY_MASK 0x4
-#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2
-#define CP_CPC_STATUS__DC1_BUSY_MASK 0x8
-#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3
-#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x10
-#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4
-#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x20
-#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5
-#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x40
-#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6
-#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x80
-#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7
-#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x400
-#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa
-#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x800
-#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb
-#define CP_CPC_STATUS__QU_BUSY_MASK 0x1000
-#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc
-#define CP_CPC_STATUS__ATCL2IU_BUSY_MASK 0x2000
-#define CP_CPC_STATUS__ATCL2IU_BUSY__SHIFT 0xd
-#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000
-#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d
-#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000
-#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e
-#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000
-#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f
-#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x1
-#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0
-#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x2
-#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1
-#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x4
-#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2
-#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x8
-#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3
-#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x10
-#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4
-#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x20
-#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5
-#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x40
-#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6
-#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x80
-#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7
-#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x100
-#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8
-#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x200
-#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9
-#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x400
-#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa
-#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x800
-#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb
-#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x1000
-#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc
-#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x2000
-#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd
-#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x10000
-#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10
-#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x20000
-#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11
-#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x40000
-#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12
-#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x80000
-#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13
-#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x100000
-#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14
-#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x200000
-#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15
-#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x400000
-#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16
-#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x800000
-#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17
-#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x1000000
-#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18
-#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x2000000
-#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19
-#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x4000000
-#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a
-#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x8000000
-#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b
-#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000
-#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c
-#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000
-#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d
-#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x8
-#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3
-#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x10
-#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4
-#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x40
-#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6
-#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x100
-#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8
-#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x200
-#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9
-#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x400
-#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa
-#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x2000
-#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd
-#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x10000
-#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10
-#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x20000
-#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11
-#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x40000
-#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12
-#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x200000
-#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15
-#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE_MASK 0x400000
-#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE__SHIFT 0x16
-#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS_MASK 0x800000
-#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x17
-#define CP_CPC_STALLED_STAT1__ATCL1_WAITING_ON_TRANS_MASK 0x1000000
-#define CP_CPC_STALLED_STAT1__ATCL1_WAITING_ON_TRANS__SHIFT 0x18
-#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x1
-#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0
-#define CP_CPF_STATUS__CSF_BUSY_MASK 0x2
-#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1
-#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x10
-#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4
-#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x20
-#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5
-#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x40
-#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6
-#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x80
-#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7
-#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x100
-#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8
-#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x200
-#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9
-#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x400
-#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa
-#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x800
-#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb
-#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x1000
-#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc
-#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x2000
-#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd
-#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x4000
-#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe
-#define CP_CPF_STATUS__HQD_BUSY_MASK 0x8000
-#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf
-#define CP_CPF_STATUS__PRT_BUSY_MASK 0x10000
-#define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10
-#define CP_CPF_STATUS__ATCL2IU_BUSY_MASK 0x20000
-#define CP_CPF_STATUS__ATCL2IU_BUSY__SHIFT 0x11
-#define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x4000000
-#define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a
-#define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x8000000
-#define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b
-#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000
-#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c
-#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000
-#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e
-#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000
-#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f
-#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1
-#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
-#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x2
-#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1
-#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x4
-#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2
-#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x8
-#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3
-#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x10
-#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4
-#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x20
-#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5
-#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x40
-#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6
-#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x80
-#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7
-#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x100
-#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8
-#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x200
-#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9
-#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x800
-#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb
-#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x1000
-#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc
-#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x2000
-#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd
-#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x4000
-#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe
-#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x8000
-#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf
-#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x10000
-#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10
-#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x20000
-#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11
-#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x40000
-#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12
-#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x80000
-#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13
-#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x100000
-#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14
-#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x200000
-#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15
-#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x400000
-#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16
-#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x800000
-#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17
-#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x1000000
-#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18
-#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x2000000
-#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19
-#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x4000000
-#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a
-#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x8000000
-#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b
-#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000
-#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c
-#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000
-#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d
-#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000
-#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e
-#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000
-#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f
-#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x1
-#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0
-#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x2
-#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1
-#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x4
-#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2
-#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x8
-#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3
-#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x20
-#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5
-#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x40
-#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6
-#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE_MASK 0x80
-#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE__SHIFT 0x7
-#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS_MASK 0x100
-#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x8
-#define CP_CPF_STALLED_STAT1__ATCL1_WAITING_ON_TRANS_MASK 0x200
-#define CP_CPF_STALLED_STAT1__ATCL1_WAITING_ON_TRANS__SHIFT 0x9
-#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f
-#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
-#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x10
-#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4
-#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x10000
-#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10
-#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x20000
-#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11
-#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x40000
-#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12
-#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x80000
-#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13
-#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x100000
-#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14
-#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x200000
-#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15
-#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000
-#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c
-#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000
-#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d
-#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000
-#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e
-#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000
-#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f
-#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff
-#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
-#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff
-#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
-#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x1ff
-#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
-#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff
-#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
-#define CPG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
-#define CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
-#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
-#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define CPG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
-#define CPG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
-#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
-#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define CPC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
-#define CPC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
-#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
-#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define CPC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
-#define CPC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
-#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
-#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define CPF_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
-#define CPF_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
-#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
-#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define CPF_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
-#define CPF_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
-#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
-#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0xf
-#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0
-#define CP_DRAW_OBJECT__OBJECT_MASK 0xffffffff
-#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0
-#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0xffff
-#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0
-#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xffffffff
-#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0
-#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xffffffff
-#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0
-#define CP_DRAW_WINDOW_LO__MIN_MASK 0xffff
-#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0
-#define CP_DRAW_WINDOW_LO__MAX_MASK 0xffff0000
-#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10
-#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x1
-#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0
-#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x2
-#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1
-#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x4
-#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2
-#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x100
-#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8
-#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK 0xffffffff
-#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT 0x0
-#define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK 0xffffffff
-#define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT 0x0
-#define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK 0x3
-#define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT 0x0
-#define CP_PRT_LOD_STATS_CNTL2__INTERVAL_MASK 0x3fc
-#define CP_PRT_LOD_STATS_CNTL2__INTERVAL__SHIFT 0x2
-#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT_MASK 0x3fc00
-#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT__SHIFT 0xa
-#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE_MASK 0x40000
-#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE__SHIFT 0x12
-#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET_MASK 0x80000
-#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET__SHIFT 0x13
-#define CP_PRT_LOD_STATS_CNTL2__MC_VMID_MASK 0x7800000
-#define CP_PRT_LOD_STATS_CNTL2__MC_VMID__SHIFT 0x17
-#define CP_PRT_LOD_STATS_CNTL2__CACHE_POLICY_MASK 0x10000000
-#define CP_PRT_LOD_STATS_CNTL2__CACHE_POLICY__SHIFT 0x1c
-#define CP_PRT_LOD_STATS_CNTL2__MTYPE_MASK 0xc0000000
-#define CP_PRT_LOD_STATS_CNTL2__MTYPE__SHIFT 0x1e
-#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xffffffff
-#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0
-#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff
-#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
-#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xffffffff
-#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0
-#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xffffffff
-#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0
-#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff
-#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
-#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x7f
-#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x0
-#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x3f000
-#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0xc
-#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL_MASK 0x2000000
-#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL__SHIFT 0x19
-#define CP_EOP_DONE_EVENT_CNTL__MTYPE_MASK 0x18000000
-#define CP_EOP_DONE_EVENT_CNTL__MTYPE__SHIFT 0x1b
-#define CP_EOP_DONE_DATA_CNTL__CNTX_ID_MASK 0xffff
-#define CP_EOP_DONE_DATA_CNTL__CNTX_ID__SHIFT 0x0
-#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x30000
-#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10
-#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x7000000
-#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18
-#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xe0000000
-#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d
-#define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK 0xfffffff
-#define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT 0x0
-#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xfffffffc
-#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2
-#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0xffff
-#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0
-#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xffffffff
-#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0
-#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xffffffff
-#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0
-#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xffffffff
-#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0
-#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xffffffff
-#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0
-#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xfffffffc
-#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2
-#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0xffff
-#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0
-#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xffffffff
-#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0
-#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xffffffff
-#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0
-#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xffffffff
-#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0
-#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xffffffff
-#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0
-#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xffffffff
-#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0
-#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xffffffff
-#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0
-#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xffffffff
-#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0
-#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xffffffff
-#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0
-#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xffffffff
-#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0
-#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xffffffff
-#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0
-#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xffffffff
-#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0
-#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xffffffff
-#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0
-#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xffffffff
-#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0
-#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xffffffff
-#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0
-#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xffffffff
-#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0
-#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xffffffff
-#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0
-#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xfffffffc
-#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2
-#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0xffff
-#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0
-#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xffffffff
-#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0
-#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xffffffff
-#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0
-#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xffffffff
-#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0
-#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xffffffff
-#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0
-#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xffffffff
-#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0
-#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xffffffff
-#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0
-#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xffffffff
-#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0
-#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xffffffff
-#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0
-#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xffffffff
-#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0
-#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xffffffff
-#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0
-#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xffffffff
-#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0
-#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xffffffff
-#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0
-#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xffffffff
-#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0
-#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xffffffff
-#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0
-#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xffffffff
-#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0
-#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xffffffff
-#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0
-#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xffffffff
-#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0
-#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xffffffff
-#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0
-#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xffffffff
-#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0
-#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xffffffff
-#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0
-#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xffffffff
-#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0
-#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xffffffff
-#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0
-#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xffffffff
-#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0
-#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xffffffff
-#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0
-#define CP_PIPE_STATS_CONTROL__CACHE_CONTROL_MASK 0x2000000
-#define CP_PIPE_STATS_CONTROL__CACHE_CONTROL__SHIFT 0x19
-#define CP_PIPE_STATS_CONTROL__MTYPE_MASK 0x18000000
-#define CP_PIPE_STATS_CONTROL__MTYPE__SHIFT 0x1b
-#define CP_STREAM_OUT_CONTROL__CACHE_CONTROL_MASK 0x2000000
-#define CP_STREAM_OUT_CONTROL__CACHE_CONTROL__SHIFT 0x19
-#define CP_STREAM_OUT_CONTROL__MTYPE_MASK 0x18000000
-#define CP_STREAM_OUT_CONTROL__MTYPE__SHIFT 0x1b
-#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x1
-#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0
-#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff
-#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
-#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff
-#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
-#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff
-#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
-#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff
-#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
-#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff
-#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
-#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff
-#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
-#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff
-#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
-#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff
-#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
-#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0xff
-#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0
-#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x30000
-#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10
-#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xffffffff
-#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0
-#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
-#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
-#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
-#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
-#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
-#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
-#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
-#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
-#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
-#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
-#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
-#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
-#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xfffffffc
-#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2
-#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0xffff
-#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0
-#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x10000
-#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10
-#define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK 0x2000000
-#define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT 0x19
-#define CP_APPEND_ADDR_HI__MTYPE_MASK 0x18000000
-#define CP_APPEND_ADDR_HI__MTYPE__SHIFT 0x1b
-#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xe0000000
-#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d
-#define CP_APPEND_DATA__DATA_MASK 0xffffffff
-#define CP_APPEND_DATA__DATA__SHIFT 0x0
-#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK 0xffffffff
-#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT 0x0
-#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK 0xffffffff
-#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT 0x0
-#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
-#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
-#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
-#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
-#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
-#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
-#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
-#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
-#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
-#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
-#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
-#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
-#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
-#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
-#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
-#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
-#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
-#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
-#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
-#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
-#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
-#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
-#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
-#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
-#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP_MASK 0x3
-#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP__SHIFT 0x0
-#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xfffffffc
-#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2
-#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0xffff
-#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0
-#define CP_ME_MC_WADDR_HI__MTYPE_MASK 0x300000
-#define CP_ME_MC_WADDR_HI__MTYPE__SHIFT 0x14
-#define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK 0x400000
-#define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT 0x16
-#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xffffffff
-#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0
-#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xffffffff
-#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0
-#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP_MASK 0x3
-#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP__SHIFT 0x0
-#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xfffffffc
-#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2
-#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0xffff
-#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0
-#define CP_ME_MC_RADDR_HI__MTYPE_MASK 0x300000
-#define CP_ME_MC_RADDR_HI__MTYPE__SHIFT 0x14
-#define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK 0x400000
-#define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x16
-#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xffffffff
-#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0
-#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3
-#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
-#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8
-#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
-#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff
-#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
-#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000
-#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
-#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000
-#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
-#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000
-#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
-#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000
-#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
-#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3
-#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
-#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8
-#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
-#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff
-#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
-#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000
-#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
-#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000
-#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
-#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000
-#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
-#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000
-#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
-#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xffffffff
-#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0
-#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x3f
-#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0
-#define CP_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x1
-#define CP_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0
-#define CP_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x2
-#define CP_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1
-#define CP_COHER_CNTL__TC_SD_ACTION_ENA_MASK 0x4
-#define CP_COHER_CNTL__TC_SD_ACTION_ENA__SHIFT 0x2
-#define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK 0x8
-#define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT 0x3
-#define CP_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x40
-#define CP_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6
-#define CP_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x80
-#define CP_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7
-#define CP_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x100
-#define CP_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8
-#define CP_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x200
-#define CP_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9
-#define CP_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x400
-#define CP_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa
-#define CP_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x800
-#define CP_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb
-#define CP_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x1000
-#define CP_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc
-#define CP_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x2000
-#define CP_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd
-#define CP_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x4000
-#define CP_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe
-#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x8000
-#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf
-#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x40000
-#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12
-#define CP_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x80000
-#define CP_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13
-#define CP_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x200000
-#define CP_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15
-#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x400000
-#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16
-#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x800000
-#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17
-#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x2000000
-#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19
-#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x4000000
-#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a
-#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x8000000
-#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b
-#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000
-#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c
-#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000
-#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d
-#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK 0x40000000
-#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT 0x1e
-#define CP_COHER_CNTL__SH_SD_ACTION_ENA_MASK 0x80000000
-#define CP_COHER_CNTL__SH_SD_ACTION_ENA__SHIFT 0x1f
-#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xffffffff
-#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0
-#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0xff
-#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0
-#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xffffffff
-#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0
-#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0xff
-#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0
-#define CP_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0xff
-#define CP_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0
-#define CP_COHER_STATUS__MEID_MASK 0x3000000
-#define CP_COHER_STATUS__MEID__SHIFT 0x18
-#define CP_COHER_STATUS__PHASE1_STATUS_MASK 0x40000000
-#define CP_COHER_STATUS__PHASE1_STATUS__SHIFT 0x1e
-#define CP_COHER_STATUS__STATUS_MASK 0x80000000
-#define CP_COHER_STATUS__STATUS__SHIFT 0x1f
-#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xffffffff
-#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0
-#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xffffffff
-#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0
-#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xffffffff
-#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0
-#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xffffffff
-#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0
-#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0xffffffff
-#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0
-#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0xffffffff
-#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0
-#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0xffffffff
-#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0
-#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0xffffffff
-#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0
-#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xffffffff
-#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0
-#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff
-#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
-#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xffffffff
-#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0
-#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff
-#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
-#define CP_DMA_ME_CONTROL__SRC_MTYPE_MASK 0xc00
-#define CP_DMA_ME_CONTROL__SRC_MTYPE__SHIFT 0xa
-#define CP_DMA_ME_CONTROL__SRC_ATC_MASK 0x1000
-#define CP_DMA_ME_CONTROL__SRC_ATC__SHIFT 0xc
-#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x2000
-#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
-#define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x300000
-#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14
-#define CP_DMA_ME_CONTROL__DST_MTYPE_MASK 0xc00000
-#define CP_DMA_ME_CONTROL__DST_MTYPE__SHIFT 0x16
-#define CP_DMA_ME_CONTROL__DST_ATC_MASK 0x1000000
-#define CP_DMA_ME_CONTROL__DST_ATC__SHIFT 0x18
-#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x2000000
-#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
-#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000
-#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d
-#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x1fffff
-#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0
-#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x200000
-#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x15
-#define CP_DMA_ME_COMMAND__SRC_SWAP_MASK 0xc00000
-#define CP_DMA_ME_COMMAND__SRC_SWAP__SHIFT 0x16
-#define CP_DMA_ME_COMMAND__DST_SWAP_MASK 0x3000000
-#define CP_DMA_ME_COMMAND__DST_SWAP__SHIFT 0x18
-#define CP_DMA_ME_COMMAND__SAS_MASK 0x4000000
-#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a
-#define CP_DMA_ME_COMMAND__DAS_MASK 0x8000000
-#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b
-#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000
-#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c
-#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000
-#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d
-#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000
-#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e
-#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xffffffff
-#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0
-#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff
-#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
-#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xffffffff
-#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0
-#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff
-#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
-#define CP_DMA_PFP_CONTROL__SRC_MTYPE_MASK 0xc00
-#define CP_DMA_PFP_CONTROL__SRC_MTYPE__SHIFT 0xa
-#define CP_DMA_PFP_CONTROL__SRC_ATC_MASK 0x1000
-#define CP_DMA_PFP_CONTROL__SRC_ATC__SHIFT 0xc
-#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x2000
-#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
-#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x300000
-#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14
-#define CP_DMA_PFP_CONTROL__DST_MTYPE_MASK 0xc00000
-#define CP_DMA_PFP_CONTROL__DST_MTYPE__SHIFT 0x16
-#define CP_DMA_PFP_CONTROL__DST_ATC_MASK 0x1000000
-#define CP_DMA_PFP_CONTROL__DST_ATC__SHIFT 0x18
-#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x2000000
-#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
-#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000
-#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d
-#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x1fffff
-#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0
-#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x200000
-#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x15
-#define CP_DMA_PFP_COMMAND__SRC_SWAP_MASK 0xc00000
-#define CP_DMA_PFP_COMMAND__SRC_SWAP__SHIFT 0x16
-#define CP_DMA_PFP_COMMAND__DST_SWAP_MASK 0x3000000
-#define CP_DMA_PFP_COMMAND__DST_SWAP__SHIFT 0x18
-#define CP_DMA_PFP_COMMAND__SAS_MASK 0x4000000
-#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a
-#define CP_DMA_PFP_COMMAND__DAS_MASK 0x8000000
-#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b
-#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000
-#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c
-#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000
-#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d
-#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000
-#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e
-#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x30
-#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4
-#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0xf0000
-#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10
-#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000
-#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c
-#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000
-#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d
-#define CP_DMA_CNTL__PIO_COUNT_MASK 0xc0000000
-#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e
-#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x3ffffff
-#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0
-#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000
-#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c
-#define CP_PFP_IB_CONTROL__IB_EN_MASK 0xff
-#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0
-#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x1
-#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0
-#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x2
-#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1
-#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x10000
-#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10
-#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x1000000
-#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18
-#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0xff
-#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
-#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff
-#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
-#define CP_RB_OFFSET__RB_OFFSET_MASK 0xfffff
-#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0
-#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff
-#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
-#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff
-#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
-#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0xfffff
-#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0
-#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0xfffff
-#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0
-#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0xfffff
-#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0
-#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0xfffff
-#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0
-#define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff
-#define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
-#define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff
-#define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
-#define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xffffffff
-#define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0
-#define CP_CE_RB_OFFSET__RB_OFFSET_MASK 0xfffff
-#define CP_CE_RB_OFFSET__RB_OFFSET__SHIFT 0x0
-#define CP_PFP_COMPLETION_STATUS__STATUS_MASK 0x3
-#define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT 0x0
-#define CP_CE_COMPLETION_STATUS__STATUS_MASK 0x3
-#define CP_CE_COMPLETION_STATUS__STATUS__SHIFT 0x0
-#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK 0x1
-#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT 0x0
-#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK 0xffffffff
-#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0
-#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0xffff
-#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
-#define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK 0xffffffff
-#define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0
-#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0xffff
-#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
-#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK 0xffffffff
-#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT 0x0
-#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK 0xffff
-#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0
-#define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK 0xffffffff
-#define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT 0x0
-#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK 0xffff
-#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0
-#define CP_INDEX_BASE_ADDR__ADDR_LO_MASK 0xffffffff
-#define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT 0x0
-#define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK 0xffff
-#define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
-#define CP_INDEX_TYPE__INDEX_TYPE_MASK 0x3
-#define CP_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
-#define CP_GDS_BKUP_ADDR__ADDR_LO_MASK 0xffffffff
-#define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT 0x0
-#define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK 0xffff
-#define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT 0x0
-#define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK 0x1
-#define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT 0x0
-#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK 0x2
-#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT 0x1
-#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK 0x4
-#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT 0x2
-#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK 0x8
-#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT 0x3
-#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK 0x10
-#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT 0x4
-#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK 0x20
-#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT 0x5
-#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK 0x40
-#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT 0x6
-#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK 0x80
-#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT 0x7
-#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x1
-#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0
-#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x4
-#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2
-#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x10
-#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4
-#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x400
-#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa
-#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x800
-#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb
-#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x1000
-#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc
-#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x2000
-#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd
-#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x4000
-#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe
-#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x8000
-#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf
-#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x800000
-#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17
-#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x1000000
-#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18
-#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x2000000
-#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19
-#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x4000000
-#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a
-#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x8000000
-#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b
-#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000
-#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c
-#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000
-#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d
-#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1
-#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
-#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x2
-#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1
-#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x4
-#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2
-#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x10
-#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4
-#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x20
-#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5
-#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x100
-#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8
-#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x200
-#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9
-#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x400
-#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa
-#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x800
-#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb
-#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x1000
-#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc
-#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x2000
-#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd
-#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x4000
-#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe
-#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x8000
-#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf
-#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x10000
-#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10
-#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x20000
-#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11
-#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x40000
-#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12
-#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x80000
-#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13
-#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x100000
-#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14
-#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x200000
-#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15
-#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x400000
-#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16
-#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x800000
-#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17
-#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x1000000
-#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18
-#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x2000000
-#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19
-#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x4000000
-#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a
-#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x8000000
-#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b
-#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000
-#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c
-#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000
-#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d
-#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000
-#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e
-#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000
-#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f
-#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1
-#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
-#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x2
-#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1
-#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x4
-#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2
-#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x8
-#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3
-#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x10
-#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4
-#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x20
-#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5
-#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x40
-#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6
-#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x80
-#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7
-#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x400
-#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa
-#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x800
-#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb
-#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x1000
-#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc
-#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x2000
-#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd
-#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x4000
-#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe
-#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x8000
-#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf
-#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x10000
-#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10
-#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x20000
-#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11
-#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_FREE_MASK 0x40000
-#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_FREE__SHIFT 0x12
-#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_TAGS_MASK 0x80000
-#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x13
-#define CP_STALLED_STAT3__ATCL1_WAITING_ON_TRANS_MASK 0x100000
-#define CP_STALLED_STAT3__ATCL1_WAITING_ON_TRANS__SHIFT 0x14
-#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1
-#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
-#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x40
-#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6
-#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x80
-#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7
-#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x100
-#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8
-#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x200
-#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9
-#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x400
-#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa
-#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x1000
-#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc
-#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x2000
-#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd
-#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x4000
-#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe
-#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x8000
-#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf
-#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x20000
-#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11
-#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x40000
-#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12
-#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x80000
-#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13
-#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x100000
-#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14
-#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x200000
-#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15
-#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x400000
-#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16
-#define CP_STAT__ROQ_RING_BUSY_MASK 0x200
-#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9
-#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x400
-#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa
-#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x800
-#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb
-#define CP_STAT__ROQ_STATE_BUSY_MASK 0x1000
-#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc
-#define CP_STAT__DC_BUSY_MASK 0x2000
-#define CP_STAT__DC_BUSY__SHIFT 0xd
-#define CP_STAT__ATCL2IU_BUSY_MASK 0x4000
-#define CP_STAT__ATCL2IU_BUSY__SHIFT 0xe
-#define CP_STAT__PFP_BUSY_MASK 0x8000
-#define CP_STAT__PFP_BUSY__SHIFT 0xf
-#define CP_STAT__MEQ_BUSY_MASK 0x10000
-#define CP_STAT__MEQ_BUSY__SHIFT 0x10
-#define CP_STAT__ME_BUSY_MASK 0x20000
-#define CP_STAT__ME_BUSY__SHIFT 0x11
-#define CP_STAT__QUERY_BUSY_MASK 0x40000
-#define CP_STAT__QUERY_BUSY__SHIFT 0x12
-#define CP_STAT__SEMAPHORE_BUSY_MASK 0x80000
-#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13
-#define CP_STAT__INTERRUPT_BUSY_MASK 0x100000
-#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14
-#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x200000
-#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15
-#define CP_STAT__DMA_BUSY_MASK 0x400000
-#define CP_STAT__DMA_BUSY__SHIFT 0x16
-#define CP_STAT__RCIU_BUSY_MASK 0x800000
-#define CP_STAT__RCIU_BUSY__SHIFT 0x17
-#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x1000000
-#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18
-#define CP_STAT__CPC_CPG_BUSY_MASK 0x2000000
-#define CP_STAT__CPC_CPG_BUSY__SHIFT 0x19
-#define CP_STAT__CE_BUSY_MASK 0x4000000
-#define CP_STAT__CE_BUSY__SHIFT 0x1a
-#define CP_STAT__TCIU_BUSY_MASK 0x8000000
-#define CP_STAT__TCIU_BUSY__SHIFT 0x1b
-#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000
-#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c
-#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000
-#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d
-#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000
-#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e
-#define CP_STAT__CP_BUSY_MASK 0x80000000
-#define CP_STAT__CP_BUSY__SHIFT 0x1f
-#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xffffffff
-#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0
-#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xffffffff
-#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0
-#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f
-#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
-#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x3f00
-#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8
-#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x3f0000
-#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10
-#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xffffffff
-#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0
-#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED_MASK 0xf
-#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED__SHIFT 0x0
-#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x1ff00
-#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8
-#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH_MASK 0xf
-#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH__SHIFT 0x0
-#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x10
-#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4
-#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x40
-#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6
-#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x100
-#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8
-#define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x10000
-#define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10
-#define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x40000
-#define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12
-#define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x100000
-#define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14
-#define CP_ME_CNTL__CE_HALT_MASK 0x1000000
-#define CP_ME_CNTL__CE_HALT__SHIFT 0x18
-#define CP_ME_CNTL__CE_STEP_MASK 0x2000000
-#define CP_ME_CNTL__CE_STEP__SHIFT 0x19
-#define CP_ME_CNTL__PFP_HALT_MASK 0x4000000
-#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a
-#define CP_ME_CNTL__PFP_STEP_MASK 0x8000000
-#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b
-#define CP_ME_CNTL__ME_HALT_MASK 0x10000000
-#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c
-#define CP_ME_CNTL__ME_STEP_MASK 0x20000000
-#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d
-#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0xff
-#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0
-#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x700
-#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8
-#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0xff00000
-#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14
-#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000
-#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c
-#define CP_ME_PREEMPTION__OBSOLETE_MASK 0x1
-#define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0
-#define CP_RB0_RPTR__RB_RPTR_MASK 0xfffff
-#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0
-#define CP_RB_RPTR__RB_RPTR_MASK 0xfffff
-#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0
-#define CP_RB1_RPTR__RB_RPTR_MASK 0xfffff
-#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0
-#define CP_RB2_RPTR__RB_RPTR_MASK 0xfffff
-#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0
-#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0xfffffff
-#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0
-#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000
-#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c
-#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0xffff
-#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0
-#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
-#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
-#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xffffffe0
-#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5
-#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0xffff
-#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0
-#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0xfff
-#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0
-#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc
-#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
-#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff
-#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
-#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff
-#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
-#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc
-#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
-#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff
-#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
-#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff
-#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
-#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc
-#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
-#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff
-#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
-#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff
-#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
-#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc
-#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
-#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff
-#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
-#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff
-#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
-#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xfffffffc
-#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2
-#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0xffff
-#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0
-#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0xfffff
-#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0
-#define CP_ROQ_THRESHOLDS__IB1_START_MASK 0xff
-#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0
-#define CP_ROQ_THRESHOLDS__IB2_START_MASK 0xff00
-#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8
-#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0xff
-#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0
-#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0xff
-#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0
-#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0xff00
-#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8
-#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0xff0000
-#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10
-#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xff000000
-#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18
-#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0xff
-#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0
-#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0xff00
-#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8
-#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0xff0000
-#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10
-#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xff000000
-#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18
-#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0xff
-#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0
-#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0xff00
-#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8
-#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0xff0000
-#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10
-#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x3f
-#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0
-#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x3f00
-#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8
-#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0xff
-#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0
-#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0xff00
-#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8
-#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x7ff
-#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0
-#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x7ff0000
-#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10
-#define CP_STQ_AVAIL__STQ_CNT_MASK 0x1ff
-#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0
-#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x7ff
-#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0
-#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x3ff
-#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0
-#define CP_CMD_INDEX__CMD_INDEX_MASK 0x7ff
-#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0
-#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x3000
-#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc
-#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x70000
-#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10
-#define CP_CMD_DATA__CMD_DATA_MASK 0xffffffff
-#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0
-#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x3ff
-#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0
-#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x3ff0000
-#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10
-#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x3ff
-#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0
-#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x3ff0000
-#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10
-#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x3ff
-#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0
-#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x3ff0000
-#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10
-#define CP_STQ_STAT__STQ_RPTR_MASK 0x3ff
-#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0
-#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x3ff
-#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0
-#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x3ff
-#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0
-#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x3ff0000
-#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10
-#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x7ff
-#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0
-#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x7ff0000
-#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10
-#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x7ff
-#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0
-#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x3ff
-#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0
-#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x3ff0000
-#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10
-#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x3ff
-#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0
-#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x3ff0000
-#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10
-#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x3ff
-#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0
-#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x3ff0000
-#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10
-#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED_MASK 0x800
-#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED__SHIFT 0xb
-#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
-#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
-#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
-#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
-#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED_MASK 0x40000
-#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED__SHIFT 0x12
-#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x80000
-#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x13
-#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x100000
-#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x14
-#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED_MASK 0x200000
-#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED__SHIFT 0x15
-#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x400000
-#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16
-#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
-#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
-#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
-#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
-#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
-#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
-#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
-#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
-#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
-#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
-#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
-#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
-#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
-#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
-#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0xf
-#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
-#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0xf0
-#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4
-#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300
-#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8
-#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400
-#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
-#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000
-#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f
-#define CP_RINGID__RINGID_MASK 0x3
-#define CP_RINGID__RINGID__SHIFT 0x0
-#define CP_PIPEID__PIPE_ID_MASK 0x3
-#define CP_PIPEID__PIPE_ID__SHIFT 0x0
-#define CP_VMID__VMID_MASK 0xf
-#define CP_VMID__VMID__SHIFT 0x0
-#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x7
-#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0
-#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x3f00
-#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8
-#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x3f0000
-#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10
-#define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x1f
-#define CP_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0
-#define CP_HPD_STATUS0__MAPPED_QUEUE_MASK 0xe0
-#define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5
-#define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0xff00
-#define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8
-#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xfffffffc
-#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2
-#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xffff
-#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
-#define CP_HQD_ACTIVE__ACTIVE_MASK 0x1
-#define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0
-#define CP_HQD_ACTIVE__BUSY_GATE_MASK 0x2
-#define CP_HQD_ACTIVE__BUSY_GATE__SHIFT 0x1
-#define CP_HQD_VMID__VMID_MASK 0xf
-#define CP_HQD_VMID__VMID__SHIFT 0x0
-#define CP_HQD_VMID__IB_VMID_MASK 0xf00
-#define CP_HQD_VMID__IB_VMID__SHIFT 0x8
-#define CP_HQD_VMID__VQID_MASK 0x3ff0000
-#define CP_HQD_VMID__VQID__SHIFT 0x10
-#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x1
-#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0
-#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x3ff00
-#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8
-#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK 0x10000000
-#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT 0x1c
-#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK 0x20000000
-#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x1d
-#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK 0x40000000
-#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT 0x1e
-#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000
-#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f
-#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x3
-#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0
-#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0xf
-#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0
-#define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x1
-#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0
-#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x10
-#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4
-#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x3f00
-#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8
-#define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000
-#define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f
-#define CP_HQD_PQ_BASE__ADDR_MASK 0xffffffff
-#define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0
-#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0xff
-#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0
-#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xffffffff
-#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0
-#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xfffffffc
-#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2
-#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0xffff
-#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0
-#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xfffffffc
-#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x2
-#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0xffff
-#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK 0x1
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x2
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_CARRY_BITS_MASK 0x3800000
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_CARRY_BITS__SHIFT 0x17
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000
-#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
-#define CP_HQD_PQ_WPTR__OFFSET_MASK 0xffffffff
-#define CP_HQD_PQ_WPTR__OFFSET__SHIFT 0x0
-#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x3f
-#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0
-#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x3f00
-#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8
-#define CP_HQD_PQ_CONTROL__MTYPE_MASK 0x18000
-#define CP_HQD_PQ_CONTROL__MTYPE__SHIFT 0xf
-#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x60000
-#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x11
-#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x300000
-#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14
-#define CP_HQD_PQ_CONTROL__PQ_ATC_MASK 0x800000
-#define CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT 0x17
-#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x1000000
-#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18
-#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x6000000
-#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x19
-#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x8000000
-#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b
-#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000
-#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c
-#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK 0x20000000
-#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d
-#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000
-#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e
-#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000
-#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f
-#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xfffffffc
-#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2
-#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0xffff
-#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0
-#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0xfffff
-#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0
-#define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0xfffff
-#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0
-#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x300000
-#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14
-#define CP_HQD_IB_CONTROL__IB_ATC_MASK 0x800000
-#define CP_HQD_IB_CONTROL__IB_ATC__SHIFT 0x17
-#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x1000000
-#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18
-#define CP_HQD_IB_CONTROL__MTYPE_MASK 0x18000000
-#define CP_HQD_IB_CONTROL__MTYPE__SHIFT 0x1b
-#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000
-#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f
-#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0xff
-#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0
-#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x700
-#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8
-#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x800
-#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb
-#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x3000
-#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc
-#define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0xc000
-#define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe
-#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x3f0000
-#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10
-#define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x400000
-#define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16
-#define CP_HQD_IQ_TIMER__IQ_ATC_MASK 0x800000
-#define CP_HQD_IQ_TIMER__IQ_ATC__SHIFT 0x17
-#define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x1000000
-#define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18
-#define CP_HQD_IQ_TIMER__MTYPE_MASK 0x18000000
-#define CP_HQD_IQ_TIMER__MTYPE__SHIFT 0x1b
-#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000
-#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d
-#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000
-#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e
-#define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000
-#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f
-#define CP_HQD_IQ_RPTR__OFFSET_MASK 0x3f
-#define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0
-#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x7
-#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0
-#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x10
-#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4
-#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x100
-#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8
-#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x200
-#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9
-#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x400
-#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa
-#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x1
-#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0
-#define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK 0x1
-#define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0
-#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x2
-#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1
-#define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK 0x10
-#define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4
-#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x20
-#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5
-#define CP_HQD_SEMA_CMD__RETRY_MASK 0x1
-#define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0
-#define CP_HQD_SEMA_CMD__RESULT_MASK 0x6
-#define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1
-#define CP_HQD_MSG_TYPE__ACTION_MASK 0x7
-#define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0
-#define CP_HQD_MSG_TYPE__SAVE_STATE_MASK 0x70
-#define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT 0x4
-#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xffffffff
-#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0
-#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xffffffff
-#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0
-#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xffffffff
-#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0
-#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xffffffff
-#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0
-#define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK 0xffffffff
-#define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT 0x0
-#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x3
-#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0
-#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK 0xc
-#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT 0x2
-#define CP_HQD_HQ_STATUS0__RSV_6_4_MASK 0x70
-#define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT 0x4
-#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK 0x80
-#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT 0x7
-#define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK 0x100
-#define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x8
-#define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK 0x200
-#define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT 0x9
-#define CP_HQD_HQ_STATUS0__RSVR_31_10_MASK 0xfffffc00
-#define CP_HQD_HQ_STATUS0__RSVR_31_10__SHIFT 0xa
-#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xffffffff
-#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0
-#define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xffffffff
-#define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT 0x0
-#define CP_MQD_CONTROL__VMID_MASK 0xf
-#define CP_MQD_CONTROL__VMID__SHIFT 0x0
-#define CP_MQD_CONTROL__PROCESSING_MQD_MASK 0x1000
-#define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc
-#define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x2000
-#define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd
-#define CP_MQD_CONTROL__MQD_ATC_MASK 0x800000
-#define CP_MQD_CONTROL__MQD_ATC__SHIFT 0x17
-#define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x1000000
-#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18
-#define CP_MQD_CONTROL__MTYPE_MASK 0x18000000
-#define CP_MQD_CONTROL__MTYPE__SHIFT 0x1b
-#define CP_HQD_HQ_STATUS1__STATUS_MASK 0xffffffff
-#define CP_HQD_HQ_STATUS1__STATUS__SHIFT 0x0
-#define CP_HQD_HQ_CONTROL1__CONTROL_MASK 0xffffffff
-#define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT 0x0
-#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xffffffff
-#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0
-#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xff
-#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
-#define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x3f
-#define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0
-#define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK 0x100
-#define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8
-#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x1000
-#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc
-#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x2000
-#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd
-#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x4000
-#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe
-#define CP_HQD_EOP_CONTROL__MTYPE_MASK 0x18000
-#define CP_HQD_EOP_CONTROL__MTYPE__SHIFT 0xf
-#define CP_HQD_EOP_CONTROL__EOP_ATC_MASK 0x800000
-#define CP_HQD_EOP_CONTROL__EOP_ATC__SHIFT 0x17
-#define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK 0x1000000
-#define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18
-#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK 0x60000000
-#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT 0x1d
-#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000
-#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f
-#define CP_HQD_EOP_RPTR__RPTR_MASK 0x1fff
-#define CP_HQD_EOP_RPTR__RPTR__SHIFT 0x0
-#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000
-#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT 0x1e
-#define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK 0x80000000
-#define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT 0x1f
-#define CP_HQD_EOP_WPTR__WPTR_MASK 0x1fff
-#define CP_HQD_EOP_WPTR__WPTR__SHIFT 0x0
-#define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK 0x1fff0000
-#define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT 0x10
-#define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK 0xfff
-#define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT 0x0
-#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK 0x10000
-#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT 0x10
-#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xfffff000
-#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc
-#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0xffff
-#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
-#define CP_HQD_CTX_SAVE_CONTROL__ATC_MASK 0x1
-#define CP_HQD_CTX_SAVE_CONTROL__ATC__SHIFT 0x0
-#define CP_HQD_CTX_SAVE_CONTROL__MTYPE_MASK 0x6
-#define CP_HQD_CTX_SAVE_CONTROL__MTYPE__SHIFT 0x1
-#define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK 0x8
-#define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3
-#define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK 0x7ffc
-#define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2
-#define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK 0x7000
-#define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT 0xc
-#define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x1fffffc
-#define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT 0x2
-#define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK 0x1fff000
-#define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT 0xc
-#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK 0x1
-#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT 0x0
-#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK 0x2
-#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT 0x1
-#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK 0x3f0
-#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT 0x4
-#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK 0x3f000
-#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT 0xc
-#define CP_HQD_ERROR__EDC_ERROR_ID_MASK 0xf
-#define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT 0x0
-#define CP_HQD_ERROR__SUA_ERROR_MASK 0x10
-#define CP_HQD_ERROR__SUA_ERROR__SHIFT 0x4
-#define CP_HQD_EOP_WPTR_MEM__WPTR_MASK 0x1fff
-#define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x0
-#define CP_HQD_EOP_DONES__DONE_COUNT_MASK 0xffffffff
-#define CP_HQD_EOP_DONES__DONE_COUNT__SHIFT 0x0
-#define DB_Z_READ_BASE__BASE_256B_MASK 0xffffffff
-#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0
-#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xffffffff
-#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0
-#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xffffffff
-#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0
-#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xffffffff
-#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0
-#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK_MASK 0xf
-#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK__SHIFT 0x0
-#define DB_DEPTH_INFO__ARRAY_MODE_MASK 0xf0
-#define DB_DEPTH_INFO__ARRAY_MODE__SHIFT 0x4
-#define DB_DEPTH_INFO__PIPE_CONFIG_MASK 0x1f00
-#define DB_DEPTH_INFO__PIPE_CONFIG__SHIFT 0x8
-#define DB_DEPTH_INFO__BANK_WIDTH_MASK 0x6000
-#define DB_DEPTH_INFO__BANK_WIDTH__SHIFT 0xd
-#define DB_DEPTH_INFO__BANK_HEIGHT_MASK 0x18000
-#define DB_DEPTH_INFO__BANK_HEIGHT__SHIFT 0xf
-#define DB_DEPTH_INFO__MACRO_TILE_ASPECT_MASK 0x60000
-#define DB_DEPTH_INFO__MACRO_TILE_ASPECT__SHIFT 0x11
-#define DB_DEPTH_INFO__NUM_BANKS_MASK 0x180000
-#define DB_DEPTH_INFO__NUM_BANKS__SHIFT 0x13
-#define DB_Z_INFO__FORMAT_MASK 0x3
-#define DB_Z_INFO__FORMAT__SHIFT 0x0
-#define DB_Z_INFO__NUM_SAMPLES_MASK 0xc
-#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2
-#define DB_Z_INFO__TILE_SPLIT_MASK 0xe000
-#define DB_Z_INFO__TILE_SPLIT__SHIFT 0xd
-#define DB_Z_INFO__TILE_MODE_INDEX_MASK 0x700000
-#define DB_Z_INFO__TILE_MODE_INDEX__SHIFT 0x14
-#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK 0x7800000
-#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT 0x17
-#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x8000000
-#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
-#define DB_Z_INFO__READ_SIZE_MASK 0x10000000
-#define DB_Z_INFO__READ_SIZE__SHIFT 0x1c
-#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000
-#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d
-#define DB_Z_INFO__CLEAR_DISALLOWED_MASK 0x40000000
-#define DB_Z_INFO__CLEAR_DISALLOWED__SHIFT 0x1e
-#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000
-#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f
-#define DB_STENCIL_INFO__FORMAT_MASK 0x1
-#define DB_STENCIL_INFO__FORMAT__SHIFT 0x0
-#define DB_STENCIL_INFO__TILE_SPLIT_MASK 0xe000
-#define DB_STENCIL_INFO__TILE_SPLIT__SHIFT 0xd
-#define DB_STENCIL_INFO__TILE_MODE_INDEX_MASK 0x700000
-#define DB_STENCIL_INFO__TILE_MODE_INDEX__SHIFT 0x14
-#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x8000000
-#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
-#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000
-#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d
-#define DB_STENCIL_INFO__CLEAR_DISALLOWED_MASK 0x40000000
-#define DB_STENCIL_INFO__CLEAR_DISALLOWED__SHIFT 0x1e
-#define DB_DEPTH_SIZE__PITCH_TILE_MAX_MASK 0x7ff
-#define DB_DEPTH_SIZE__PITCH_TILE_MAX__SHIFT 0x0
-#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX_MASK 0x3ff800
-#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX__SHIFT 0xb
-#define DB_DEPTH_SLICE__SLICE_TILE_MAX_MASK 0x3fffff
-#define DB_DEPTH_SLICE__SLICE_TILE_MAX__SHIFT 0x0
-#define DB_DEPTH_VIEW__SLICE_START_MASK 0x7ff
-#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0
-#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0xffe000
-#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd
-#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x1000000
-#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18
-#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x2000000
-#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19
-#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x1
-#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0
-#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x2
-#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1
-#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x4
-#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2
-#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x8
-#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3
-#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x10
-#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4
-#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x20
-#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5
-#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x40
-#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6
-#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x80
-#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7
-#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0xf00
-#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8
-#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK 0x1000
-#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT 0xc
-#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x1
-#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0
-#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x2
-#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1
-#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x70
-#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4
-#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0xf00
-#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8
-#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0xf000
-#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc
-#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0xf0000
-#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10
-#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0xf00000
-#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14
-#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0xf000000
-#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18
-#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xf0000000
-#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c
-#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x3
-#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0
-#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0xc
-#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2
-#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x30
-#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4
-#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x40
-#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6
-#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x80
-#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7
-#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x100
-#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8
-#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x200
-#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9
-#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x400
-#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa
-#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x800
-#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb
-#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x1000
-#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc
-#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x6000
-#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd
-#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x8000
-#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf
-#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x10000
-#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10
-#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x20000
-#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11
-#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x40000
-#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12
-#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x180000
-#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13
-#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x3e00000
-#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15
-#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x4000000
-#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a
-#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x8000000
-#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b
-#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000
-#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c
-#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000
-#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d
-#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000
-#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e
-#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000
-#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f
-#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x3
-#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0
-#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x1c
-#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2
-#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x20
-#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5
-#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x40
-#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6
-#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x80
-#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7
-#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x100
-#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8
-#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x200
-#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9
-#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x400
-#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa
-#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x800
-#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb
-#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x7000
-#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc
-#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x38000
-#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf
-#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x1c0000
-#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12
-#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x200000
-#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15
-#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x400000
-#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16
-#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x800000
-#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17
-#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x7
-#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0
-#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x70
-#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4
-#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x700
-#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8
-#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x7000
-#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc
-#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x10000
-#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10
-#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x20000
-#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11
-#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x40000
-#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12
-#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x80000
-#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13
-#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x100000
-#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14
-#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x200000
-#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15
-#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x7000000
-#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18
-#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x8000000
-#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b
-#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x1
-#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0
-#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x2
-#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1
-#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x4
-#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2
-#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x30
-#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4
-#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x40
-#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6
-#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x80
-#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7
-#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x100
-#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8
-#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x200
-#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9
-#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x400
-#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa
-#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x800
-#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb
-#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x1000
-#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc
-#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x6000
-#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd
-#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK 0x8000
-#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT 0xf
-#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xffffffff
-#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0
-#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xffffffff
-#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0
-#define DB_STENCIL_CLEAR__CLEAR_MASK 0xff
-#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0
-#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xffffffff
-#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0
-#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xffffffff
-#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0
-#define DB_HTILE_SURFACE__LINEAR_MASK 0x1
-#define DB_HTILE_SURFACE__LINEAR__SHIFT 0x0
-#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x2
-#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1
-#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x4
-#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x2
-#define DB_HTILE_SURFACE__PRELOAD_MASK 0x8
-#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x3
-#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x3f0
-#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x4
-#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0xfc00
-#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0xa
-#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x10000
-#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10
-#define DB_HTILE_SURFACE__TC_COMPATIBLE_MASK 0x20000
-#define DB_HTILE_SURFACE__TC_COMPATIBLE__SHIFT 0x11
-#define DB_PRELOAD_CONTROL__START_X_MASK 0xff
-#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0
-#define DB_PRELOAD_CONTROL__START_Y_MASK 0xff00
-#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8
-#define DB_PRELOAD_CONTROL__MAX_X_MASK 0xff0000
-#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10
-#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xff000000
-#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18
-#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0xff
-#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0
-#define DB_STENCILREFMASK__STENCILMASK_MASK 0xff00
-#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8
-#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0xff0000
-#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10
-#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xff000000
-#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18
-#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0xff
-#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0
-#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0xff00
-#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8
-#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0xff0000
-#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10
-#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xff000000
-#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18
-#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x7
-#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0
-#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0xff0
-#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4
-#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0xff000
-#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc
-#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x1000000
-#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18
-#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x7
-#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0
-#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0xff0
-#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4
-#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0xff000
-#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc
-#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x1000000
-#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18
-#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x1
-#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0
-#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x2
-#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1
-#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x4
-#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2
-#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x8
-#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3
-#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x70
-#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4
-#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x80
-#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7
-#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x700
-#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8
-#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x700000
-#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14
-#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000
-#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e
-#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000
-#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f
-#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0xf
-#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0
-#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0xf0
-#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4
-#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0xf00
-#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8
-#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0xf000
-#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc
-#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0xf0000
-#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10
-#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0xf00000
-#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14
-#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x1
-#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0
-#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x300
-#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8
-#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0xc00
-#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa
-#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x3000
-#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc
-#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0xc000
-#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe
-#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x10000
-#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10
-#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
-#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
-#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
-#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
-#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
-#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
-#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
-#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
-#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
-#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
-#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
-#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
-#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
-#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
-#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
-#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0xffc00
-#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
-#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
-#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
-#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0xf000000
-#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
-#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
-#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
-#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
-#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0xffc00
-#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
-#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
-#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
-#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0xf000000
-#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18
-#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
-#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
-#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
-#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
-#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
-#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
-#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
-#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
-#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
-#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
-#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
-#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000
-#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
-#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000
-#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x1
-#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0
-#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x2
-#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1
-#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x4
-#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2
-#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x8
-#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3
-#define DB_DEBUG__FORCE_Z_MODE_MASK 0x30
-#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4
-#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x40
-#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6
-#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x80
-#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7
-#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x300
-#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8
-#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0xc00
-#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa
-#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x3000
-#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc
-#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x4000
-#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe
-#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x8000
-#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf
-#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x10000
-#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10
-#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x20000
-#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11
-#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x40000
-#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12
-#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x180000
-#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13
-#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x200000
-#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15
-#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x400000
-#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16
-#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x800000
-#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17
-#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0xf000000
-#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18
-#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000
-#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c
-#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000
-#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d
-#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000
-#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e
-#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000
-#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f
-#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x1
-#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0
-#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x2
-#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1
-#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x4
-#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2
-#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x8
-#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3
-#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x10
-#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4
-#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_MASK 0x20
-#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL__SHIFT 0x5
-#define DB_DEBUG2__ENABLE_PREZL_CB_STALL_MASK 0x40
-#define DB_DEBUG2__ENABLE_PREZL_CB_STALL__SHIFT 0x6
-#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ_MASK 0x80
-#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ__SHIFT 0x7
-#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ_MASK 0x100
-#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ__SHIFT 0x8
-#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x3e00
-#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9
-#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x4000
-#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe
-#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x8000
-#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0xf
-#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK 0x10000
-#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT 0x10
-#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x20000
-#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11
-#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x40000
-#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12
-#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x80000
-#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13
-#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000
-#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c
-#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000
-#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d
-#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000
-#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e
-#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000
-#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f
-#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x4
-#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2
-#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x8
-#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3
-#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x10
-#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4
-#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x20
-#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5
-#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x40
-#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6
-#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x80
-#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7
-#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x100
-#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8
-#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x200
-#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9
-#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x400
-#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa
-#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x800
-#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb
-#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x1000
-#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc
-#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x2000
-#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd
-#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x4000
-#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe
-#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x8000
-#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf
-#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x10000
-#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x10
-#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x20000
-#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11
-#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x40000
-#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12
-#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x80000
-#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13
-#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x100000
-#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14
-#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x200000
-#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15
-#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x400000
-#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16
-#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x800000
-#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17
-#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x1000000
-#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18
-#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x2000000
-#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19
-#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x4000000
-#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a
-#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x8000000
-#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b
-#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000
-#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c
-#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000
-#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d
-#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE_MASK 0x40000000
-#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE__SHIFT 0x1e
-#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK_MASK 0x80000000
-#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK__SHIFT 0x1f
-#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x1
-#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0
-#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x2
-#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1
-#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x4
-#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2
-#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x8
-#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3
-#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF_MASK 0x10
-#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF__SHIFT 0x4
-#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK 0x20
-#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT 0x5
-#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE_MASK 0x40
-#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE__SHIFT 0x6
-#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0xffffff80
-#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x7
-#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x1f
-#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0
-#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x3e0
-#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5
-#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x1c00
-#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa
-#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7f000000
-#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18
-#define DB_WATERMARKS__DEPTH_FREE_MASK 0x1f
-#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0
-#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x7e0
-#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x5
-#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x7800
-#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0xb
-#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0xf8000
-#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0xf
-#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x7f00000
-#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x14
-#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE_MASK 0x8000000
-#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE__SHIFT 0x1b
-#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE_MASK 0x10000000
-#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE__SHIFT 0x1c
-#define DB_WATERMARKS__RE_Z_PANIC_DISABLE_MASK 0x20000000
-#define DB_WATERMARKS__RE_Z_PANIC_DISABLE__SHIFT 0x1d
-#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000
-#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x1e
-#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000
-#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x1f
-#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x3
-#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0
-#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0xc
-#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2
-#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x30
-#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4
-#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0xc0
-#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6
-#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x300
-#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8
-#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0xc00
-#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa
-#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x3000
-#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc
-#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0xc000
-#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe
-#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x30000
-#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10
-#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0xc0000
-#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12
-#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x7f
-#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0
-#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x3f80
-#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x7
-#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x1fc000
-#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0xe
-#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x1e00000
-#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x15
-#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xfe000000
-#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x19
-#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK 0x1f
-#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT 0x0
-#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK 0x3e0
-#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT 0x5
-#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0xfc00
-#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa
-#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x1f0000
-#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x10
-#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1fe00000
-#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x15
-#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0xff
-#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0
-#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x7f00
-#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8
-#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x1ff8000
-#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0xf
-#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xfe000000
-#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19
-#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0xf
-#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x0
-#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0xff0
-#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x4
-#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0xfff000
-#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0xc
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x1000000
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x18
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x2000000
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x19
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x4000000
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x1a
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x8000000
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x1b
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x1c
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1e
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000
-#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x1f
-#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xffffffff
-#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x0
-#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7fffffff
-#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x0
-#define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x3
-#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0
-#define DB_READ_DEBUG_0__BUSY_DATA0_MASK 0xffffffff
-#define DB_READ_DEBUG_0__BUSY_DATA0__SHIFT 0x0
-#define DB_READ_DEBUG_1__BUSY_DATA1_MASK 0xffffffff
-#define DB_READ_DEBUG_1__BUSY_DATA1__SHIFT 0x0
-#define DB_READ_DEBUG_2__BUSY_DATA2_MASK 0xffffffff
-#define DB_READ_DEBUG_2__BUSY_DATA2__SHIFT 0x0
-#define DB_READ_DEBUG_3__DEBUG_DATA_MASK 0xffffffff
-#define DB_READ_DEBUG_3__DEBUG_DATA__SHIFT 0x0
-#define DB_READ_DEBUG_4__DEBUG_DATA_MASK 0xffffffff
-#define DB_READ_DEBUG_4__DEBUG_DATA__SHIFT 0x0
-#define DB_READ_DEBUG_5__DEBUG_DATA_MASK 0xffffffff
-#define DB_READ_DEBUG_5__DEBUG_DATA__SHIFT 0x0
-#define DB_READ_DEBUG_6__DEBUG_DATA_MASK 0xffffffff
-#define DB_READ_DEBUG_6__DEBUG_DATA__SHIFT 0x0
-#define DB_READ_DEBUG_7__DEBUG_DATA_MASK 0xffffffff
-#define DB_READ_DEBUG_7__DEBUG_DATA__SHIFT 0x0
-#define DB_READ_DEBUG_8__DEBUG_DATA_MASK 0xffffffff
-#define DB_READ_DEBUG_8__DEBUG_DATA__SHIFT 0x0
-#define DB_READ_DEBUG_9__DEBUG_DATA_MASK 0xffffffff
-#define DB_READ_DEBUG_9__DEBUG_DATA__SHIFT 0x0
-#define DB_READ_DEBUG_A__DEBUG_DATA_MASK 0xffffffff
-#define DB_READ_DEBUG_A__DEBUG_DATA__SHIFT 0x0
-#define DB_READ_DEBUG_B__DEBUG_DATA_MASK 0xffffffff
-#define DB_READ_DEBUG_B__DEBUG_DATA__SHIFT 0x0
-#define DB_READ_DEBUG_C__DEBUG_DATA_MASK 0xffffffff
-#define DB_READ_DEBUG_C__DEBUG_DATA__SHIFT 0x0
-#define DB_READ_DEBUG_D__DEBUG_DATA_MASK 0xffffffff
-#define DB_READ_DEBUG_D__DEBUG_DATA__SHIFT 0x0
-#define DB_READ_DEBUG_E__DEBUG_DATA_MASK 0xffffffff
-#define DB_READ_DEBUG_E__DEBUG_DATA__SHIFT 0x0
-#define DB_READ_DEBUG_F__DEBUG_DATA_MASK 0xffffffff
-#define DB_READ_DEBUG_F__DEBUG_DATA__SHIFT 0x0
-#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xffffffff
-#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0
-#define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7fffffff
-#define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0
-#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xffffffff
-#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0
-#define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7fffffff
-#define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0
-#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xffffffff
-#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0
-#define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7fffffff
-#define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0
-#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xffffffff
-#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0
-#define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7fffffff
-#define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0
-#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00
-#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
-#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000
-#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
-#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000
-#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
-#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000
-#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
-#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
-#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
-#define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00
-#define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
-#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000
-#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
-#define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000
-#define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
-#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000
-#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
-#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
-#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
-#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x7
-#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
-#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
-#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
-#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
-#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
-#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
-#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
-#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
-#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
-#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
-#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
-#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
-#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
-#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
-#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
-#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
-#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
-#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xffffffff
-#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0
-#define GB_GPU_ID__GPU_ID_MASK 0xf
-#define GB_GPU_ID__GPU_ID__SHIFT 0x0
-#define CC_RB_DAISY_CHAIN__RB_0_MASK 0xf
-#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0
-#define CC_RB_DAISY_CHAIN__RB_1_MASK 0xf0
-#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4
-#define CC_RB_DAISY_CHAIN__RB_2_MASK 0xf00
-#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8
-#define CC_RB_DAISY_CHAIN__RB_3_MASK 0xf000
-#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc
-#define CC_RB_DAISY_CHAIN__RB_4_MASK 0xf0000
-#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10
-#define CC_RB_DAISY_CHAIN__RB_5_MASK 0xf00000
-#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14
-#define CC_RB_DAISY_CHAIN__RB_6_MASK 0xf000000
-#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18
-#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xf0000000
-#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c
-#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x3c
-#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x7c0
-#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x3800
-#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x1c00000
-#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x6000000
-#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x3c
-#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x7c0
-#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x3800
-#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x1c00000
-#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x6000000
-#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x3c
-#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x7c0
-#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x3800
-#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x1c00000
-#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x6000000
-#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x3c
-#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x7c0
-#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x3800
-#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x1c00000
-#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x6000000
-#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x3c
-#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x7c0
-#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x3800
-#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x1c00000
-#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x6000000
-#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x3c
-#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x7c0
-#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x3800
-#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x1c00000
-#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x6000000
-#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x3c
-#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x7c0
-#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x3800
-#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x1c00000
-#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x6000000
-#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x3c
-#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x7c0
-#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x3800
-#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x1c00000
-#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x6000000
-#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x3c
-#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x7c0
-#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x3800
-#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x1c00000
-#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x6000000
-#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x3c
-#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x7c0
-#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x3800
-#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x1c00000
-#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x6000000
-#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x3c
-#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x7c0
-#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x3800
-#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x1c00000
-#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x6000000
-#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x3c
-#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x7c0
-#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x3800
-#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x1c00000
-#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x6000000
-#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x3c
-#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x7c0
-#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x3800
-#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x1c00000
-#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x6000000
-#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x3c
-#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x7c0
-#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x3800
-#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x1c00000
-#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x6000000
-#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x3c
-#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x7c0
-#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x3800
-#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x1c00000
-#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x6000000
-#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x3c
-#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x7c0
-#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x3800
-#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x1c00000
-#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x6000000
-#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x3c
-#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x7c0
-#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x3800
-#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x1c00000
-#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x6000000
-#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x3c
-#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x7c0
-#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x3800
-#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x1c00000
-#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x6000000
-#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x3c
-#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x7c0
-#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x3800
-#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x1c00000
-#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x6000000
-#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x3c
-#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x7c0
-#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x3800
-#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x1c00000
-#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x6000000
-#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x3c
-#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x7c0
-#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x3800
-#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x1c00000
-#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x6000000
-#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x3c
-#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x7c0
-#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x3800
-#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x1c00000
-#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x6000000
-#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x3c
-#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x7c0
-#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x3800
-#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x1c00000
-#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x6000000
-#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x3c
-#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x7c0
-#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x3800
-#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x1c00000
-#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x6000000
-#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x3c
-#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x7c0
-#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x3800
-#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x1c00000
-#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x6000000
-#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x3c
-#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x7c0
-#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x3800
-#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x1c00000
-#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x6000000
-#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x3c
-#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x7c0
-#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x3800
-#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x1c00000
-#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x6000000
-#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x3c
-#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x7c0
-#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x3800
-#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x1c00000
-#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x6000000
-#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x3c
-#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x7c0
-#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x3800
-#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x1c00000
-#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x6000000
-#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x3c
-#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x7c0
-#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x3800
-#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x1c00000
-#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x6000000
-#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x3c
-#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x7c0
-#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x3800
-#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x1c00000
-#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x6000000
-#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x3c
-#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2
-#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x7c0
-#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6
-#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x3800
-#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb
-#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x1c00000
-#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16
-#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x6000000
-#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19
-#define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x3
-#define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0xc
-#define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x30
-#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0xc0
-#define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x3
-#define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0xc
-#define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x30
-#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0xc0
-#define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x3
-#define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0xc
-#define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x30
-#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0xc0
-#define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x3
-#define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0xc
-#define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x30
-#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0xc0
-#define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x3
-#define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0xc
-#define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x30
-#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0xc0
-#define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x3
-#define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0xc
-#define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x30
-#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0xc0
-#define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x3
-#define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0xc
-#define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x30
-#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0xc0
-#define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x3
-#define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0xc
-#define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x30
-#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0xc0
-#define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x3
-#define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0xc
-#define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x30
-#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0xc0
-#define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x3
-#define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0xc
-#define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x30
-#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0xc0
-#define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x3
-#define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0xc
-#define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x30
-#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0xc0
-#define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x3
-#define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0xc
-#define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x30
-#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0xc0
-#define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x3
-#define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0xc
-#define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x30
-#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0xc0
-#define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x3
-#define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0xc
-#define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x30
-#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0xc0
-#define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x3
-#define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0xc
-#define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x30
-#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0xc0
-#define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x6
-#define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x3
-#define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x0
-#define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0xc
-#define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x2
-#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x30
-#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x4
-#define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0xc0
-#define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x6
-#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x10000
-#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0x10
-#define GB_EDC_MODE__DED_MODE_MASK 0x300000
-#define GB_EDC_MODE__DED_MODE__SHIFT 0x14
-#define GB_EDC_MODE__PROP_FED_MASK 0x20000000
-#define GB_EDC_MODE__PROP_FED__SHIFT 0x1d
-#define GB_EDC_MODE__BYPASS_MASK 0x80000000
-#define GB_EDC_MODE__BYPASS__SHIFT 0x1f
-#define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x2
-#define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1
-#define RAS_SIGNATURE_CONTROL__ENABLE_MASK 0x1
-#define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT 0x0
-#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK 0xffffffff
-#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT 0x0
-#define RAS_SX_SIGNATURE0__SIGNATURE_MASK 0xffffffff
-#define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT 0x0
-#define RAS_SX_SIGNATURE1__SIGNATURE_MASK 0xffffffff
-#define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT 0x0
-#define RAS_SX_SIGNATURE2__SIGNATURE_MASK 0xffffffff
-#define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT 0x0
-#define RAS_SX_SIGNATURE3__SIGNATURE_MASK 0xffffffff
-#define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT 0x0
-#define RAS_DB_SIGNATURE0__SIGNATURE_MASK 0xffffffff
-#define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT 0x0
-#define RAS_PA_SIGNATURE0__SIGNATURE_MASK 0xffffffff
-#define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT 0x0
-#define RAS_VGT_SIGNATURE0__SIGNATURE_MASK 0xffffffff
-#define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT 0x0
-#define RAS_SC_SIGNATURE0__SIGNATURE_MASK 0xffffffff
-#define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT 0x0
-#define RAS_SC_SIGNATURE1__SIGNATURE_MASK 0xffffffff
-#define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT 0x0
-#define RAS_SC_SIGNATURE2__SIGNATURE_MASK 0xffffffff
-#define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT 0x0
-#define RAS_SC_SIGNATURE3__SIGNATURE_MASK 0xffffffff
-#define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT 0x0
-#define RAS_SC_SIGNATURE4__SIGNATURE_MASK 0xffffffff
-#define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT 0x0
-#define RAS_SC_SIGNATURE5__SIGNATURE_MASK 0xffffffff
-#define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT 0x0
-#define RAS_SC_SIGNATURE6__SIGNATURE_MASK 0xffffffff
-#define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT 0x0
-#define RAS_SC_SIGNATURE7__SIGNATURE_MASK 0xffffffff
-#define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT 0x0
-#define RAS_IA_SIGNATURE0__SIGNATURE_MASK 0xffffffff
-#define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT 0x0
-#define RAS_IA_SIGNATURE1__SIGNATURE_MASK 0xffffffff
-#define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT 0x0
-#define RAS_SPI_SIGNATURE0__SIGNATURE_MASK 0xffffffff
-#define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT 0x0
-#define RAS_SPI_SIGNATURE1__SIGNATURE_MASK 0xffffffff
-#define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT 0x0
-#define RAS_TA_SIGNATURE0__SIGNATURE_MASK 0xffffffff
-#define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT 0x0
-#define RAS_TD_SIGNATURE0__SIGNATURE_MASK 0xffffffff
-#define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT 0x0
-#define RAS_CB_SIGNATURE0__SIGNATURE_MASK 0xffffffff
-#define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT 0x0
-#define RAS_BCI_SIGNATURE0__SIGNATURE_MASK 0xffffffff
-#define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT 0x0
-#define RAS_BCI_SIGNATURE1__SIGNATURE_MASK 0xffffffff
-#define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT 0x0
-#define RAS_TA_SIGNATURE1__SIGNATURE_MASK 0xffffffff
-#define RAS_TA_SIGNATURE1__SIGNATURE__SHIFT 0x0
-#define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK 0x7
-#define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT 0x0
-#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x7
-#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0
-#define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK 0xffff
-#define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT 0x0
-#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000
-#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
-#define GRBM_CAM_DATA__CAM_ADDR_MASK 0xffff
-#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0
-#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000
-#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
-#define GRBM_CNTL__READ_TIMEOUT_MASK 0xff
-#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0
-#define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000
-#define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f
-#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x3f
-#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0
-#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0xfc0
-#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6
-#define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x3
-#define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0
-#define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0xc
-#define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2
-#define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x30
-#define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4
-#define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0xc0
-#define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6
-#define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x4000
-#define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe
-#define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x8000
-#define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf
-#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0xf
-#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0
-#define GRBM_STATUS__SRBM_RQ_PENDING_MASK 0x20
-#define GRBM_STATUS__SRBM_RQ_PENDING__SHIFT 0x5
-#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x80
-#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7
-#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x100
-#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8
-#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x200
-#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9
-#define GRBM_STATUS__DB_CLEAN_MASK 0x1000
-#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc
-#define GRBM_STATUS__CB_CLEAN_MASK 0x2000
-#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd
-#define GRBM_STATUS__TA_BUSY_MASK 0x4000
-#define GRBM_STATUS__TA_BUSY__SHIFT 0xe
-#define GRBM_STATUS__GDS_BUSY_MASK 0x8000
-#define GRBM_STATUS__GDS_BUSY__SHIFT 0xf
-#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x10000
-#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10
-#define GRBM_STATUS__VGT_BUSY_MASK 0x20000
-#define GRBM_STATUS__VGT_BUSY__SHIFT 0x11
-#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x40000
-#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12
-#define GRBM_STATUS__IA_BUSY_MASK 0x80000
-#define GRBM_STATUS__IA_BUSY__SHIFT 0x13
-#define GRBM_STATUS__SX_BUSY_MASK 0x100000
-#define GRBM_STATUS__SX_BUSY__SHIFT 0x14
-#define GRBM_STATUS__WD_BUSY_MASK 0x200000
-#define GRBM_STATUS__WD_BUSY__SHIFT 0x15
-#define GRBM_STATUS__SPI_BUSY_MASK 0x400000
-#define GRBM_STATUS__SPI_BUSY__SHIFT 0x16
-#define GRBM_STATUS__BCI_BUSY_MASK 0x800000
-#define GRBM_STATUS__BCI_BUSY__SHIFT 0x17
-#define GRBM_STATUS__SC_BUSY_MASK 0x1000000
-#define GRBM_STATUS__SC_BUSY__SHIFT 0x18
-#define GRBM_STATUS__PA_BUSY_MASK 0x2000000
-#define GRBM_STATUS__PA_BUSY__SHIFT 0x19
-#define GRBM_STATUS__DB_BUSY_MASK 0x4000000
-#define GRBM_STATUS__DB_BUSY__SHIFT 0x1a
-#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000
-#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c
-#define GRBM_STATUS__CP_BUSY_MASK 0x20000000
-#define GRBM_STATUS__CP_BUSY__SHIFT 0x1d
-#define GRBM_STATUS__CB_BUSY_MASK 0x40000000
-#define GRBM_STATUS__CB_BUSY__SHIFT 0x1e
-#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000
-#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f
-#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0xf
-#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0
-#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x10
-#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4
-#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x20
-#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5
-#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x40
-#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6
-#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x80
-#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7
-#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x100
-#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8
-#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x200
-#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9
-#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x400
-#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa
-#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x800
-#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb
-#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x1000
-#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc
-#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x2000
-#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd
-#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x4000
-#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe
-#define GRBM_STATUS2__RLC_BUSY_MASK 0x1000000
-#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18
-#define GRBM_STATUS2__TC_BUSY_MASK 0x2000000
-#define GRBM_STATUS2__TC_BUSY__SHIFT 0x19
-#define GRBM_STATUS2__TCC_CC_RESIDENT_MASK 0x4000000
-#define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT 0x1a
-#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000
-#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c
-#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000
-#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d
-#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000
-#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e
-#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x2
-#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1
-#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x4
-#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2
-#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x400000
-#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16
-#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x800000
-#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17
-#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x1000000
-#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18
-#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x2000000
-#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19
-#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x4000000
-#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a
-#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x8000000
-#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b
-#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000
-#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d
-#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000
-#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e
-#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000
-#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f
-#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x2
-#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1
-#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x4
-#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2
-#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x400000
-#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16
-#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x800000
-#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17
-#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x1000000
-#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18
-#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x2000000
-#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19
-#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x4000000
-#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a
-#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x8000000
-#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b
-#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000
-#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d
-#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000
-#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e
-#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000
-#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f
-#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x2
-#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1
-#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x4
-#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2
-#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x400000
-#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16
-#define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x800000
-#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17
-#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x1000000
-#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18
-#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x2000000
-#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19
-#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x4000000
-#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a
-#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x8000000
-#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b
-#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000
-#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d
-#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000
-#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e
-#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000
-#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f
-#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x2
-#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1
-#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x4
-#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2
-#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x400000
-#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16
-#define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x800000
-#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17
-#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x1000000
-#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18
-#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x2000000
-#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19
-#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x4000000
-#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a
-#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x8000000
-#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b
-#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000
-#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d
-#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000
-#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e
-#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000
-#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f
-#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x1
-#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0
-#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x4
-#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2
-#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x10000
-#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10
-#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x20000
-#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11
-#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x40000
-#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12
-#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x80000
-#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13
-#define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x100000
-#define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14
-#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX_MASK 0x3f
-#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX__SHIFT 0x0
-#define GRBM_DEBUG_DATA__DATA_MASK 0xffffffff
-#define GRBM_DEBUG_DATA__DATA__SHIFT 0x0
-#define GRBM_CGTT_CLK_CNTL__ON_DELAY_MASK 0xf
-#define GRBM_CGTT_CLK_CNTL__ON_DELAY__SHIFT 0x0
-#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS_MASK 0xff0
-#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS__SHIFT 0x4
-#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN_MASK 0x40000000
-#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
-#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0xff
-#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0
-#define GRBM_GFX_INDEX__SH_INDEX_MASK 0xff00
-#define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x8
-#define GRBM_GFX_INDEX__SE_INDEX_MASK 0xff0000
-#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10
-#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000
-#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d
-#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000
-#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e
-#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000
-#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f
-#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
-#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
-#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
-#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
-#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0xff
-#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0
-#define GRBM_DEBUG__IGNORE_RDY_MASK 0x2
-#define GRBM_DEBUG__IGNORE_RDY__SHIFT 0x1
-#define GRBM_DEBUG__IGNORE_FAO_MASK 0x20
-#define GRBM_DEBUG__IGNORE_FAO__SHIFT 0x5
-#define GRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x40
-#define GRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x6
-#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x80
-#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x7
-#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE_MASK 0xf00
-#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE__SHIFT 0x8
-#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE_MASK 0x1000
-#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xc
-#define GRBM_DEBUG__GRBM_TRAP_ENABLE_MASK 0x2000
-#define GRBM_DEBUG__GRBM_TRAP_ENABLE__SHIFT 0xd
-#define GRBM_DEBUG__DEBUG_BUS_FGCG_EN_MASK 0x80000000
-#define GRBM_DEBUG__DEBUG_BUS_FGCG_EN__SHIFT 0x1f
-#define GRBM_DEBUG_SNAPSHOT__CPF_RDY_MASK 0x1
-#define GRBM_DEBUG_SNAPSHOT__CPF_RDY__SHIFT 0x0
-#define GRBM_DEBUG_SNAPSHOT__CPG_RDY_MASK 0x2
-#define GRBM_DEBUG_SNAPSHOT__CPG_RDY__SHIFT 0x1
-#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY_MASK 0x4
-#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY__SHIFT 0x2
-#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY_MASK 0x8
-#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY__SHIFT 0x3
-#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY_MASK 0x10
-#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY__SHIFT 0x4
-#define GRBM_DEBUG_SNAPSHOT__GDS_RDY_MASK 0x20
-#define GRBM_DEBUG_SNAPSHOT__GDS_RDY__SHIFT 0x5
-#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0_MASK 0x40
-#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0__SHIFT 0x6
-#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0_MASK 0x80
-#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0__SHIFT 0x7
-#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0_MASK 0x100
-#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0__SHIFT 0x8
-#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0_MASK 0x200
-#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0__SHIFT 0x9
-#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0_MASK 0x400
-#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0__SHIFT 0xa
-#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0_MASK 0x800
-#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0__SHIFT 0xb
-#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0_MASK 0x1000
-#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0__SHIFT 0xc
-#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0_MASK 0x2000
-#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0__SHIFT 0xd
-#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1_MASK 0x4000
-#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1__SHIFT 0xe
-#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1_MASK 0x8000
-#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1__SHIFT 0xf
-#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1_MASK 0x10000
-#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1__SHIFT 0x10
-#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1_MASK 0x20000
-#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1__SHIFT 0x11
-#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1_MASK 0x40000
-#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1__SHIFT 0x12
-#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1_MASK 0x80000
-#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1__SHIFT 0x13
-#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1_MASK 0x100000
-#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1__SHIFT 0x14
-#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1_MASK 0x200000
-#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1__SHIFT 0x15
-#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc
-#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2
-#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x300000
-#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14
-#define GRBM_READ_ERROR__READ_MEID_MASK 0xc00000
-#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16
-#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000
-#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f
-#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM_MASK 0x20000
-#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM__SHIFT 0x11
-#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x40000
-#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12
-#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x80000
-#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x100000
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x200000
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x400000
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x800000
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x1000000
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x2000000
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x4000000
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x8000000
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000
-#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f
-#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x1
-#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0
-#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x80000
-#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13
-#define GRBM_TRAP_OP__RW_MASK 0x1
-#define GRBM_TRAP_OP__RW__SHIFT 0x0
-#define GRBM_TRAP_ADDR__DATA_MASK 0xffff
-#define GRBM_TRAP_ADDR__DATA__SHIFT 0x0
-#define GRBM_TRAP_ADDR_MSK__DATA_MASK 0xffff
-#define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0
-#define GRBM_TRAP_WD__DATA_MASK 0xffffffff
-#define GRBM_TRAP_WD__DATA__SHIFT 0x0
-#define GRBM_TRAP_WD_MSK__DATA_MASK 0xffffffff
-#define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0
-#define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x3
-#define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x0
-#define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x4
-#define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x2
-#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x1
-#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0
-#define GRBM_WRITE_ERROR__WRITE_REQUESTER_SRBM_MASK 0x2
-#define GRBM_WRITE_ERROR__WRITE_REQUESTER_SRBM__SHIFT 0x1
-#define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x1c
-#define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2
-#define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x1e0
-#define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x5
-#define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x1000
-#define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc
-#define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x1e000
-#define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd
-#define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x300000
-#define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14
-#define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0xc00000
-#define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16
-#define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000
-#define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f
-#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
-#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
-#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
-#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
-#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
-#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x1000
-#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc
-#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x2000
-#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
-#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x4000
-#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
-#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000
-#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
-#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x20000
-#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
-#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x40000
-#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
-#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x80000
-#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13
-#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x100000
-#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
-#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x200000
-#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
-#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x400000
-#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16
-#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x800000
-#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17
-#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x1000000
-#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18
-#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x2000000
-#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
-#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x4000000
-#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
-#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x8000000
-#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
-#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000
-#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
-#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
-#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
-#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
-#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
-#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
-#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x1000
-#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc
-#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x2000
-#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
-#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x4000
-#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
-#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000
-#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
-#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x20000
-#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
-#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x40000
-#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
-#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x80000
-#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13
-#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x100000
-#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
-#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x200000
-#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
-#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x400000
-#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16
-#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x800000
-#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17
-#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x1000000
-#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18
-#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x2000000
-#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
-#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x4000000
-#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
-#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x8000000
-#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
-#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000
-#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
-#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
-#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
-#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
-#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
-#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
-#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
-#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
-#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
-#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
-#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
-#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
-#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
-#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
-#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
-#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
-#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
-#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
-#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
-#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
-#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
-#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
-#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
-#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
-#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
-#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
-#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
-#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
-#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
-#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
-#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
-#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
-#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
-#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
-#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
-#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
-#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
-#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
-#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
-#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
-#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
-#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
-#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
-#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
-#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
-#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
-#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
-#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
-#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
-#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
-#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
-#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
-#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
-#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
-#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
-#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
-#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
-#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
-#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
-#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
-#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
-#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
-#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
-#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
-#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
-#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
-#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
-#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
-#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
-#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
-#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
-#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
-#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
-#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
-#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
-#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
-#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
-#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
-#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
-#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
-#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
-#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
-#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
-#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
-#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
-#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
-#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
-#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
-#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
-#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
-#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
-#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
-#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
-#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
-#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
-#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
-#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
-#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff
-#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
-#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff
-#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
-#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff
-#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
-#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff
-#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
-#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff
-#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
-#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff
-#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
-#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff
-#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
-#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff
-#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
-#define DEBUG_INDEX__DEBUG_INDEX_MASK 0x3ffff
-#define DEBUG_INDEX__DEBUG_INDEX__SHIFT 0x0
-#define DEBUG_DATA__DEBUG_DATA_MASK 0xffffffff
-#define DEBUG_DATA__DEBUG_DATA__SHIFT 0x0
-#define GRBM_NOWHERE__DATA_MASK 0xffffffff
-#define GRBM_NOWHERE__DATA__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xffffffff
-#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xffffffff
-#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0
-#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x1
-#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0
-#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x2
-#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1
-#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x4
-#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2
-#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x8
-#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3
-#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x10
-#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4
-#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x20
-#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5
-#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x100
-#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8
-#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x200
-#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9
-#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x400
-#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa
-#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x800
-#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x1
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x2
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x4
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x8
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x10
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x20
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x40
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x80
-#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x100
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x200
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x400
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x800
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x1000
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x2000
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x4000
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x8000
-#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf
-#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x10000
-#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10
-#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x20000
-#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11
-#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x40000
-#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12
-#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x80000
-#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13
-#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x100000
-#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14
-#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x200000
-#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15
-#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x400000
-#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16
-#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x800000
-#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17
-#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x1000000
-#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18
-#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x2000000
-#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x19
-#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK 0x4000000
-#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT 0x1a
-#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x1
-#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0
-#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x2
-#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1
-#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x4
-#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2
-#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x8
-#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3
-#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x10
-#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4
-#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x20
-#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5
-#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x40
-#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6
-#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x80
-#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7
-#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x100
-#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8
-#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x200
-#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9
-#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x400
-#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa
-#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x800
-#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb
-#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x1000
-#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc
-#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x2000
-#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd
-#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x4000
-#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe
-#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x100000
-#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14
-#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x1
-#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0
-#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x2
-#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1
-#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x4
-#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2
-#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x8
-#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3
-#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x10
-#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4
-#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x20
-#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5
-#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x2000
-#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd
-#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0xc000
-#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe
-#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x10000
-#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10
-#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x20000
-#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11
-#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x40000
-#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12
-#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x80000
-#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13
-#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x100000
-#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14
-#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x200000
-#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15
-#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x400000
-#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16
-#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x1000000
-#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18
-#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x2000000
-#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19
-#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x4000000
-#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a
-#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x8000000
-#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b
-#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffff
-#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xffffffff
-#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffff
-#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xffffffff
-#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xffffffff
-#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xffffffff
-#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xffffffff
-#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xffffffff
-#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xffffffff
-#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xffffffff
-#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xffffffff
-#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xffffffff
-#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xffffffff
-#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xffffffff
-#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xffffffff
-#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xffffffff
-#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xffffffff
-#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xffffffff
-#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xffffffff
-#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xffffffff
-#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xffffffff
-#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xffffffff
-#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xffffffff
-#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xffffffff
-#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xffffffff
-#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xffffffff
-#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xffffffff
-#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xffffffff
-#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xffffffff
-#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xffffffff
-#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xffffffff
-#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xffffffff
-#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0
-#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x1
-#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0
-#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x6
-#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1
-#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x8
-#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3
-#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x10
-#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4
-#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x20
-#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x5
-#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000
-#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c
-#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000
-#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d
-#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000
-#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e
-#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000
-#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f
-#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK 0x1
-#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT 0x0
-#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x1
-#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0
-#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x6
-#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1
-#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x38
-#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3
-#define PA_SU_POINT_SIZE__HEIGHT_MASK 0xffff
-#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0
-#define PA_SU_POINT_SIZE__WIDTH_MASK 0xffff0000
-#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10
-#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0xffff
-#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0
-#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xffff0000
-#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10
-#define PA_SU_LINE_CNTL__WIDTH_MASK 0xffff
-#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0
-#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x3
-#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0
-#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x4
-#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2
-#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x8
-#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3
-#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x10
-#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x4
-#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xffffffff
-#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0
-#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x1
-#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0
-#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x2
-#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1
-#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x4
-#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2
-#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x8
-#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3
-#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x10
-#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4
-#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x20
-#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5
-#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x40
-#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6
-#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x80
-#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7
-#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0xff00
-#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8
-#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000
-#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e
-#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000
-#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f
-#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x1
-#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0
-#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x2
-#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1
-#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x4
-#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2
-#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x18
-#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3
-#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0xe0
-#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5
-#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x700
-#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8
-#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x800
-#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb
-#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x1000
-#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc
-#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x2000
-#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd
-#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x10000
-#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10
-#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x80000
-#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13
-#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x100000
-#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14
-#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x200000
-#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15
-#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0xff
-#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0
-#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x100
-#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8
-#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xffffffff
-#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0
-#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xffffffff
-#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0
-#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xffffffff
-#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0
-#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xffffffff
-#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0
-#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xffffffff
-#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0
-#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x1ff
-#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0
-#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x1ff0000
-#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10
-#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0xffffff
-#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0
-#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
-#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
-#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
-#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
-#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
-#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
-#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
-#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
-#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
-#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
-#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
-#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
-#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
-#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
-#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
-#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
-#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
-#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
-#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
-#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
-#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffff
-#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffff
-#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffff
-#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffff
-#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x7
-#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0
-#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x10
-#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4
-#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x1e000
-#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd
-#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x700000
-#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14
-#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x3000000
-#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18
-#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0xffff
-#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0
-#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xffff0000
-#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10
-#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0xffff
-#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0
-#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xffff0000
-#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10
-#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK 0x3
-#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0xf
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0xf0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0xf00
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0xf000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0xf0000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0xf00000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0xf000000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xf0000000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0xf
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0xf0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0xf00
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0xf000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0xf0000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0xf00000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0xf000000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xf0000000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0xf
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0xf0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0xf00
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0xf000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0xf0000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0xf00000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0xf000000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xf0000000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0xf
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0xf0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0xf00
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0xf000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0xf0000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0xf00000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0xf000000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xf0000000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0xf
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0xf0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0xf00
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0xf000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0xf0000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0xf00000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0xf000000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xf0000000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0xf
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0xf0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0xf00
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0xf000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0xf0000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0xf00000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0xf000000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xf0000000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0xf
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0xf0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0xf00
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0xf000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0xf0000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0xf00000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0xf000000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xf0000000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0xf
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0xf0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0xf00
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0xf000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0xf0000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0xf00000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0xf000000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xf0000000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0xf
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0xf0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0xf00
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0xf000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0xf0000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0xf00000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0xf000000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xf0000000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0xf
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0xf0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0xf00
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0xf000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0xf0000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0xf00000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0xf000000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xf0000000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0xf
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0xf0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0xf00
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0xf000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0xf0000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0xf00000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0xf000000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xf0000000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0xf
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0xf0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0xf00
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0xf000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0xf0000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0xf00000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0xf000000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xf0000000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0xf
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0xf0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0xf00
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0xf000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0xf0000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0xf00000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0xf000000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xf0000000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0xf
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0xf0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0xf00
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0xf000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0xf0000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0xf00000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0xf000000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xf0000000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0xf
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0xf0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0xf00
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0xf000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0xf0000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0xf00000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0xf000000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xf0000000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0xf
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0xf0
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0xf00
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0xf000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0xf0000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0xf00000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0xf000000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xf0000000
-#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0xf
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0xf0
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0xf00
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0xf000
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0xf0000
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0xf00000
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0xf000000
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xf0000000
-#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0xf
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0xf0
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0xf00
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0xf000
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0xf0000
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0xf00000
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0xf000000
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xf0000000
-#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c
-#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x7fff
-#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0
-#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7fff0000
-#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10
-#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x7fff
-#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0
-#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7fff0000
-#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10
-#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x7fff
-#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0
-#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7fff0000
-#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10
-#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x7fff
-#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0
-#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7fff0000
-#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10
-#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x7fff
-#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0
-#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7fff0000
-#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10
-#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x7fff
-#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0
-#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7fff0000
-#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10
-#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x7fff
-#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0
-#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7fff0000
-#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10
-#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x7fff
-#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0
-#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7fff0000
-#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10
-#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0xffff
-#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0
-#define PA_SC_EDGERULE__ER_TRI_MASK 0xf
-#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0
-#define PA_SC_EDGERULE__ER_POINT_MASK 0xf0
-#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4
-#define PA_SC_EDGERULE__ER_RECT_MASK 0xf00
-#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8
-#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x3f000
-#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc
-#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0xfc0000
-#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12
-#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0xf000000
-#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18
-#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xf0000000
-#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c
-#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x200
-#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9
-#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x400
-#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa
-#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x800
-#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb
-#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x1000
-#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc
-#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0xffff
-#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0
-#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0xff0000
-#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10
-#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000
-#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c
-#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000
-#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d
-#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x1
-#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0
-#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x2
-#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1
-#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x4
-#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2
-#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x8
-#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3
-#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x1
-#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0
-#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x2
-#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1
-#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x4
-#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2
-#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x8
-#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3
-#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x70
-#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4
-#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x80
-#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7
-#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x100
-#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8
-#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x200
-#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9
-#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x400
-#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa
-#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x800
-#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb
-#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x1000
-#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc
-#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x2000
-#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd
-#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x4000
-#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe
-#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x8000
-#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf
-#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x10000
-#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10
-#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x20000
-#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11
-#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x40000
-#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12
-#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x80000
-#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13
-#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0xf00000
-#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14
-#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x1000000
-#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18
-#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x2000000
-#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19
-#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x4000000
-#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a
-#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x8000000
-#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b
-#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000
-#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c
-#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x3
-#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0
-#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0xc
-#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2
-#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x30
-#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4
-#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x40
-#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6
-#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x80
-#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7
-#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x300
-#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8
-#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0xc00
-#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa
-#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x3000
-#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc
-#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0xc000
-#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe
-#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x30000
-#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10
-#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0xc0000
-#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12
-#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x300000
-#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14
-#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x3000000
-#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18
-#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0xc000000
-#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a
-#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0x30000000
-#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1c
-#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x3
-#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0
-#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0xc
-#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2
-#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x30
-#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x4
-#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x3
-#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0
-#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0xc
-#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2
-#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x7fff
-#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0
-#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7fff0000
-#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10
-#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
-#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x7fff
-#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0
-#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7fff0000
-#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10
-#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0xffff
-#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0
-#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xffff0000
-#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10
-#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0xffff
-#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0
-#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xffff0000
-#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10
-#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0xffff
-#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0
-#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xffff0000
-#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10
-#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x7fff
-#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0
-#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7fff0000
-#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10
-#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
-#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x7fff
-#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0
-#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7fff0000
-#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x7fff
-#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7fff0000
-#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
-#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x7fff
-#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7fff0000
-#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
-#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x7fff
-#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7fff0000
-#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
-#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x7fff
-#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7fff0000
-#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
-#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x7fff
-#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7fff0000
-#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
-#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x7fff
-#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7fff0000
-#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
-#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x7fff
-#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7fff0000
-#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
-#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x7fff
-#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7fff0000
-#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
-#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x7fff
-#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7fff0000
-#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
-#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x7fff
-#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7fff0000
-#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
-#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x7fff
-#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7fff0000
-#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
-#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x7fff
-#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7fff0000
-#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
-#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x7fff
-#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7fff0000
-#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
-#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x7fff
-#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7fff0000
-#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
-#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x7fff
-#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7fff0000
-#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
-#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x7fff
-#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7fff0000
-#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
-#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
-#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x7fff
-#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7fff0000
-#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x7fff
-#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7fff0000
-#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x7fff
-#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7fff0000
-#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x7fff
-#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7fff0000
-#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x7fff
-#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7fff0000
-#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x7fff
-#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7fff0000
-#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x7fff
-#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7fff0000
-#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x7fff
-#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7fff0000
-#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x7fff
-#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7fff0000
-#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x7fff
-#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7fff0000
-#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x7fff
-#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7fff0000
-#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x7fff
-#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7fff0000
-#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x7fff
-#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7fff0000
-#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x7fff
-#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7fff0000
-#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x7fff
-#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7fff0000
-#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x7fff
-#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0
-#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7fff0000
-#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10
-#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xffffffff
-#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xffffffff
-#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xffffffff
-#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xffffffff
-#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xffffffff
-#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xffffffff
-#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xffffffff
-#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xffffffff
-#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xffffffff
-#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xffffffff
-#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xffffffff
-#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xffffffff
-#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xffffffff
-#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xffffffff
-#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xffffffff
-#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xffffffff
-#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xffffffff
-#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xffffffff
-#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xffffffff
-#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xffffffff
-#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xffffffff
-#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xffffffff
-#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xffffffff
-#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xffffffff
-#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xffffffff
-#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xffffffff
-#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xffffffff
-#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xffffffff
-#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xffffffff
-#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xffffffff
-#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xffffffff
-#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xffffffff
-#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0
-#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x1
-#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0
-#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x2
-#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1
-#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x4
-#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2
-#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x8
-#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3
-#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x10
-#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4
-#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x20
-#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5
-#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE_MASK 0xc0
-#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE__SHIFT 0x6
-#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x100
-#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x8
-#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x200
-#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x9
-#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x400
-#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0xa
-#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x800
-#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0xb
-#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x1000
-#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xc
-#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x2000
-#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xd
-#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x4000
-#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xe
-#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x8000
-#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xf
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x10000
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0x10
-#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x20000
-#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0x11
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x40000
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x12
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x80000
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x13
-#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x100000
-#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x14
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x200000
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x15
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x400000
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x16
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x800000
-#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x17
-#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x1000000
-#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x18
-#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x2000000
-#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x19
-#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x4000000
-#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x1a
-#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x8000000
-#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x1b
-#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x10000000
-#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1c
-#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x20000000
-#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1d
-#define PA_SC_ENHANCE__ECO_SPARE1_MASK 0x40000000
-#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT 0x1e
-#define PA_SC_ENHANCE__ECO_SPARE0_MASK 0x80000000
-#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT 0x1f
-#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK 0x1
-#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT 0x0
-#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK 0x6
-#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT 0x1
-#define PA_SC_ENHANCE_1__ENABLE_SC_BINNING_MASK 0x8
-#define PA_SC_ENHANCE_1__ENABLE_SC_BINNING__SHIFT 0x3
-#define PA_SC_ENHANCE_1__ECO_SPARE0_MASK 0x10
-#define PA_SC_ENHANCE_1__ECO_SPARE0__SHIFT 0x4
-#define PA_SC_ENHANCE_1__ECO_SPARE1_MASK 0x20
-#define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT 0x5
-#define PA_SC_ENHANCE_1__ECO_SPARE2_MASK 0x40
-#define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT 0x6
-#define PA_SC_ENHANCE_1__ECO_SPARE3_MASK 0x80
-#define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT 0x7
-#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK 0x1
-#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x0
-#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK 0x2
-#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT 0x1
-#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x3f
-#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0
-#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x7fc0
-#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6
-#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x1f8000
-#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf
-#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xff800000
-#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x17
-#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x3f
-#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0
-#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0xfc0
-#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6
-#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x3f000
-#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc
-#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0xfc0000
-#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12
-#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0xffff
-#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0
-#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xffff0000
-#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10
-#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0xf
-#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0
-#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0xff00
-#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8
-#define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0xffff
-#define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0
-#define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xffff0000
-#define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10
-#define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0xffff
-#define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0
-#define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xffff0000
-#define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10
-#define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0xffff
-#define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0
-#define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xffff0000
-#define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10
-#define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0xffff
-#define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0
-#define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xffff0000
-#define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10
-#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
-#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
-#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
-#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
-#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
-#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
-#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
-#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
-#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x3ff
-#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
-#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x3ff
-#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
-#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x3ff
-#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0
-#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x3ff
-#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0
-#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1
-#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
-#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2
-#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
-#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x3fff
-#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
-#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff
-#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
-#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff
-#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
-#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff
-#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
-#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1
-#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
-#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2
-#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
-#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x3fff
-#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
-#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff
-#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
-#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff
-#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
-#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff
-#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
-#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1
-#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
-#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2
-#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
-#define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x3fff
-#define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
-#define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff
-#define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
-#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff
-#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
-#define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff
-#define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
-#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1
-#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
-#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1
-#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
-#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1
-#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
-#define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000
-#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x1f
-#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000
-#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f
-#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x3ff
-#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0
-#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0xf
-#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
-#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
-#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
-#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
-#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
-#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
-#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000
-#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d
-#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000
-#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e
-#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000
-#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x1f
-#define CGTT_SC_CLK_CTRL__ON_DELAY_MASK 0xf
-#define CGTT_SC_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
-#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
-#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
-#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
-#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
-#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
-#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
-#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
-#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
-#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
-#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
-#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK 0x1f
-#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT 0x0
-#define PA_SU_DEBUG_DATA__DATA_MASK 0xffffffff
-#define PA_SU_DEBUG_DATA__DATA__SHIFT 0x0
-#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK 0x3f
-#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT 0x0
-#define PA_SC_DEBUG_DATA__DATA_MASK 0xffffffff
-#define PA_SC_DEBUG_DATA__DATA__SHIFT 0x0
-#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK 0xff
-#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT 0x0
-#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK 0x100
-#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT 0x8
-#define CLIPPER_DEBUG_REG00__su_clip_baryc_free_MASK 0x600
-#define CLIPPER_DEBUG_REG00__su_clip_baryc_free__SHIFT 0x9
-#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK 0x800
-#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT 0xb
-#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK 0x1000
-#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT 0xc
-#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x2000
-#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0xd
-#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x4000
-#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0xe
-#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x8000
-#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0xf
-#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK 0x10000
-#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x10
-#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK 0x20000
-#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x11
-#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK 0x40000
-#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x12
-#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK 0x80000
-#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x13
-#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK 0x100000
-#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x14
-#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x200000
-#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x15
-#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK 0x400000
-#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT 0x16
-#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x800000
-#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x17
-#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x1000000
-#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x18
-#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x2000000
-#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x19
-#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x4000000
-#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x1a
-#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x8000000
-#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x1b
-#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x10000000
-#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x1c
-#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write_MASK 0x20000000
-#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write__SHIFT 0x1d
-#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write_MASK 0x40000000
-#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write__SHIFT 0x1e
-#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write_MASK 0x80000000
-#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write__SHIFT 0x1f
-#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK 0xff
-#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT 0x0
-#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid_MASK 0x700
-#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid__SHIFT 0x8
-#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK 0x3800
-#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT 0xb
-#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate_MASK 0x1c000
-#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate__SHIFT 0xe
-#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0xe0000
-#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x11
-#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x100000
-#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x14
-#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2_MASK 0x200000
-#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2__SHIFT 0x15
-#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1_MASK 0x400000
-#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1__SHIFT 0x16
-#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0_MASK 0x800000
-#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0__SHIFT 0x17
-#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid_MASK 0x1000000
-#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid__SHIFT 0x18
-#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill_MASK 0x2000000
-#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill__SHIFT 0x19
-#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0xc000000
-#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x1a
-#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write_MASK 0x10000000
-#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write__SHIFT 0x1c
-#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write_MASK 0x20000000
-#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write__SHIFT 0x1d
-#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread_MASK 0x40000000
-#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread__SHIFT 0x1e
-#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty_MASK 0x80000000
-#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty__SHIFT 0x1f
-#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid_MASK 0x7
-#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid__SHIFT 0x0
-#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid_MASK 0x38
-#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid__SHIFT 0x3
-#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx_MASK 0xc0
-#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx__SHIFT 0x6
-#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2_MASK 0xf00
-#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2__SHIFT 0x8
-#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1_MASK 0xf000
-#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1__SHIFT 0xc
-#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0_MASK 0xf0000
-#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0__SHIFT 0x10
-#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords_MASK 0x100000
-#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords__SHIFT 0x14
-#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill_MASK 0x200000
-#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill__SHIFT 0x15
-#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet_MASK 0x400000
-#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet__SHIFT 0x16
-#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot_MASK 0x800000
-#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot__SHIFT 0x17
-#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim_MASK 0x1000000
-#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim__SHIFT 0x18
-#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive_MASK 0x2000000
-#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive__SHIFT 0x19
-#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full_MASK 0x4000000
-#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full__SHIFT 0x1a
-#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full_MASK 0x8000000
-#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full__SHIFT 0x1b
-#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write_MASK 0x10000000
-#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write__SHIFT 0x1c
-#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write_MASK 0x20000000
-#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write__SHIFT 0x1d
-#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread_MASK 0x40000000
-#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread__SHIFT 0x1e
-#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty_MASK 0x80000000
-#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty__SHIFT 0x1f
-#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x3fff
-#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x0
-#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id_MASK 0xfc000
-#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id__SHIFT 0xe
-#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx_MASK 0x700000
-#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x14
-#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x800000
-#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x17
-#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x7000000
-#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x18
-#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
-#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
-#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet_MASK 0x10000000
-#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet__SHIFT 0x1c
-#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_MASK 0x20000000
-#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event__SHIFT 0x1d
-#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000
-#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x1e
-#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
-#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f
-#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
-#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
-#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
-#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
-#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
-#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
-#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
-#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
-#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x20000000
-#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x1d
-#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000
-#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x1e
-#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
-#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f
-#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or_MASK 0x3fff
-#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or__SHIFT 0x0
-#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id_MASK 0xfc000
-#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id__SHIFT 0xe
-#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx_MASK 0x700000
-#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx__SHIFT 0x14
-#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive_MASK 0x800000
-#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x17
-#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot_MASK 0x7000000
-#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot__SHIFT 0x18
-#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
-#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
-#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet_MASK 0x10000000
-#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet__SHIFT 0x1c
-#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_MASK 0x20000000
-#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event__SHIFT 0x1d
-#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000
-#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x1e
-#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000
-#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1f
-#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
-#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
-#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
-#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
-#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
-#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
-#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
-#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
-#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event_MASK 0x20000000
-#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event__SHIFT 0x1d
-#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000
-#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x1e
-#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000
-#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1f
-#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or_MASK 0x3fff
-#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or__SHIFT 0x0
-#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id_MASK 0xfc000
-#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id__SHIFT 0xe
-#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx_MASK 0x700000
-#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx__SHIFT 0x14
-#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive_MASK 0x800000
-#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x17
-#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot_MASK 0x7000000
-#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot__SHIFT 0x18
-#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
-#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
-#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet_MASK 0x10000000
-#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet__SHIFT 0x1c
-#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_MASK 0x20000000
-#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event__SHIFT 0x1d
-#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000
-#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x1e
-#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000
-#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1f
-#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
-#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
-#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
-#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
-#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
-#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
-#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
-#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
-#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event_MASK 0x20000000
-#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event__SHIFT 0x1d
-#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000
-#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x1e
-#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000
-#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1f
-#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or_MASK 0x3fff
-#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or__SHIFT 0x0
-#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id_MASK 0xfc000
-#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id__SHIFT 0xe
-#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx_MASK 0x700000
-#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx__SHIFT 0x14
-#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive_MASK 0x800000
-#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x17
-#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot_MASK 0x7000000
-#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot__SHIFT 0x18
-#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
-#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
-#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet_MASK 0x10000000
-#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet__SHIFT 0x1c
-#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_MASK 0x20000000
-#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event__SHIFT 0x1d
-#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000
-#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x1e
-#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000
-#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x1f
-#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
-#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
-#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
-#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
-#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
-#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
-#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
-#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
-#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event_MASK 0x20000000
-#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event__SHIFT 0x1d
-#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000
-#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x1e
-#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000
-#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x1f
-#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event_MASK 0x1
-#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event__SHIFT 0x0
-#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event_MASK 0x2
-#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event__SHIFT 0x1
-#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event_MASK 0x4
-#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event__SHIFT 0x2
-#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event_MASK 0x8
-#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event__SHIFT 0x3
-#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive_MASK 0x10
-#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive__SHIFT 0x4
-#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive_MASK 0x20
-#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive__SHIFT 0x5
-#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive_MASK 0x40
-#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive__SHIFT 0x6
-#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive_MASK 0x80
-#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive__SHIFT 0x7
-#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf00
-#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x8
-#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf000
-#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0xc
-#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf0000
-#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x10
-#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf00000
-#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x14
-#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid_MASK 0x1000000
-#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid__SHIFT 0x18
-#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid_MASK 0x2000000
-#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid__SHIFT 0x19
-#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid_MASK 0x4000000
-#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid__SHIFT 0x1a
-#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid_MASK 0x8000000
-#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid__SHIFT 0x1b
-#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x10000000
-#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1c
-#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x20000000
-#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1d
-#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x40000000
-#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1e
-#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x80000000
-#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1f
-#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO_MASK 0xff
-#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO__SHIFT 0x0
-#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x1f00
-#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x8
-#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x3e000
-#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0xd
-#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out_MASK 0xc0000
-#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out__SHIFT 0x12
-#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert_MASK 0x300000
-#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert__SHIFT 0x14
-#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load_MASK 0xc00000
-#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load__SHIFT 0x16
-#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive_MASK 0x1000000
-#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x18
-#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid_MASK 0x2000000
-#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x19
-#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive_MASK 0x4000000
-#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x1a
-#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid_MASK 0x8000000
-#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1b
-#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive_MASK 0x10000000
-#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x1c
-#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid_MASK 0x20000000
-#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1d
-#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive_MASK 0x40000000
-#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x1e
-#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
-#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f
-#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx_MASK 0x7
-#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx__SHIFT 0x0
-#define CLIPPER_DEBUG_REG13__point_clip_candidate_MASK 0x8
-#define CLIPPER_DEBUG_REG13__point_clip_candidate__SHIFT 0x3
-#define CLIPPER_DEBUG_REG13__prim_nan_kill_MASK 0x10
-#define CLIPPER_DEBUG_REG13__prim_nan_kill__SHIFT 0x4
-#define CLIPPER_DEBUG_REG13__clprim_clip_primitive_MASK 0x20
-#define CLIPPER_DEBUG_REG13__clprim_clip_primitive__SHIFT 0x5
-#define CLIPPER_DEBUG_REG13__clprim_cull_primitive_MASK 0x40
-#define CLIPPER_DEBUG_REG13__clprim_cull_primitive__SHIFT 0x6
-#define CLIPPER_DEBUG_REG13__prim_back_valid_MASK 0x80
-#define CLIPPER_DEBUG_REG13__prim_back_valid__SHIFT 0x7
-#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid_MASK 0xf00
-#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid__SHIFT 0x8
-#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx_MASK 0x3000
-#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx__SHIFT 0xc
-#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty_MASK 0x4000
-#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty__SHIFT 0xe
-#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty_MASK 0x8000
-#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty__SHIFT 0xf
-#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty_MASK 0x10000
-#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty__SHIFT 0x10
-#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt_MASK 0x1e0000
-#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt__SHIFT 0x11
-#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices_MASK 0x600000
-#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices__SHIFT 0x15
-#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait_MASK 0x800000
-#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait__SHIFT 0x17
-#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents_MASK 0x1f000000
-#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents__SHIFT 0x18
-#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full_MASK 0x20000000
-#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full__SHIFT 0x1d
-#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread_MASK 0x40000000
-#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread__SHIFT 0x1e
-#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write_MASK 0x80000000
-#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write__SHIFT 0x1f
-#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2_MASK 0x3f
-#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2__SHIFT 0x0
-#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1_MASK 0xfc0
-#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1__SHIFT 0x6
-#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0_MASK 0x3f000
-#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0__SHIFT 0xc
-#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive_MASK 0x40000
-#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive__SHIFT 0x12
-#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet_MASK 0x80000
-#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet__SHIFT 0x13
-#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot_MASK 0x100000
-#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot__SHIFT 0x14
-#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot_MASK 0xe00000
-#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot__SHIFT 0x15
-#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id_MASK 0x3f000000
-#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id__SHIFT 0x18
-#define CLIPPER_DEBUG_REG14__clprim_in_back_event_MASK 0x40000000
-#define CLIPPER_DEBUG_REG14__clprim_in_back_event__SHIFT 0x1e
-#define CLIPPER_DEBUG_REG14__prim_back_valid_MASK 0x80000000
-#define CLIPPER_DEBUG_REG14__prim_back_valid__SHIFT 0x1f
-#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb_MASK 0xffff
-#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb__SHIFT 0x0
-#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x1f0000
-#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x10
-#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x3e00000
-#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x15
-#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x7c000000
-#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x1a
-#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid_MASK 0x80000000
-#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid__SHIFT 0x1f
-#define CLIPPER_DEBUG_REG16__sm0_prim_end_state_MASK 0x7f
-#define CLIPPER_DEBUG_REG16__sm0_prim_end_state__SHIFT 0x0
-#define CLIPPER_DEBUG_REG16__sm0_ps_expand_MASK 0x80
-#define CLIPPER_DEBUG_REG16__sm0_ps_expand__SHIFT 0x7
-#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt_MASK 0x1f00
-#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt__SHIFT 0x8
-#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt_MASK 0x3e000
-#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt__SHIFT 0xd
-#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1_MASK 0x40000
-#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1__SHIFT 0x12
-#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0_MASK 0x80000
-#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0__SHIFT 0x13
-#define CLIPPER_DEBUG_REG16__sm0_current_state_MASK 0x7f00000
-#define CLIPPER_DEBUG_REG16__sm0_current_state__SHIFT 0x14
-#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
-#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
-#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full_MASK 0x10000000
-#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full__SHIFT 0x1c
-#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq_MASK 0x20000000
-#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq__SHIFT 0x1d
-#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0_MASK 0x40000000
-#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0__SHIFT 0x1e
-#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid_MASK 0x80000000
-#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid__SHIFT 0x1f
-#define CLIPPER_DEBUG_REG17__sm1_prim_end_state_MASK 0x7f
-#define CLIPPER_DEBUG_REG17__sm1_prim_end_state__SHIFT 0x0
-#define CLIPPER_DEBUG_REG17__sm1_ps_expand_MASK 0x80
-#define CLIPPER_DEBUG_REG17__sm1_ps_expand__SHIFT 0x7
-#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt_MASK 0x1f00
-#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt__SHIFT 0x8
-#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt_MASK 0x3e000
-#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt__SHIFT 0xd
-#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1_MASK 0x40000
-#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1__SHIFT 0x12
-#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0_MASK 0x80000
-#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0__SHIFT 0x13
-#define CLIPPER_DEBUG_REG17__sm1_current_state_MASK 0x7f00000
-#define CLIPPER_DEBUG_REG17__sm1_current_state__SHIFT 0x14
-#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
-#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
-#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full_MASK 0x10000000
-#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full__SHIFT 0x1c
-#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq_MASK 0x20000000
-#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq__SHIFT 0x1d
-#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0_MASK 0x40000000
-#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0__SHIFT 0x1e
-#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid_MASK 0x80000000
-#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid__SHIFT 0x1f
-#define CLIPPER_DEBUG_REG18__sm2_prim_end_state_MASK 0x7f
-#define CLIPPER_DEBUG_REG18__sm2_prim_end_state__SHIFT 0x0
-#define CLIPPER_DEBUG_REG18__sm2_ps_expand_MASK 0x80
-#define CLIPPER_DEBUG_REG18__sm2_ps_expand__SHIFT 0x7
-#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt_MASK 0x1f00
-#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt__SHIFT 0x8
-#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt_MASK 0x3e000
-#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt__SHIFT 0xd
-#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1_MASK 0x40000
-#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1__SHIFT 0x12
-#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0_MASK 0x80000
-#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0__SHIFT 0x13
-#define CLIPPER_DEBUG_REG18__sm2_current_state_MASK 0x7f00000
-#define CLIPPER_DEBUG_REG18__sm2_current_state__SHIFT 0x14
-#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
-#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
-#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full_MASK 0x10000000
-#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full__SHIFT 0x1c
-#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq_MASK 0x20000000
-#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq__SHIFT 0x1d
-#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0_MASK 0x40000000
-#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0__SHIFT 0x1e
-#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid_MASK 0x80000000
-#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid__SHIFT 0x1f
-#define CLIPPER_DEBUG_REG19__sm3_prim_end_state_MASK 0x7f
-#define CLIPPER_DEBUG_REG19__sm3_prim_end_state__SHIFT 0x0
-#define CLIPPER_DEBUG_REG19__sm3_ps_expand_MASK 0x80
-#define CLIPPER_DEBUG_REG19__sm3_ps_expand__SHIFT 0x7
-#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt_MASK 0x1f00
-#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt__SHIFT 0x8
-#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt_MASK 0x3e000
-#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt__SHIFT 0xd
-#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1_MASK 0x40000
-#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1__SHIFT 0x12
-#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0_MASK 0x80000
-#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0__SHIFT 0x13
-#define CLIPPER_DEBUG_REG19__sm3_current_state_MASK 0x7f00000
-#define CLIPPER_DEBUG_REG19__sm3_current_state__SHIFT 0x14
-#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
-#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
-#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full_MASK 0x10000000
-#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full__SHIFT 0x1c
-#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq_MASK 0x20000000
-#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq__SHIFT 0x1d
-#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0_MASK 0x40000000
-#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0__SHIFT 0x1e
-#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid_MASK 0x80000000
-#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid__SHIFT 0x1f
-#define SXIFCCG_DEBUG_REG0__position_address_MASK 0x3f
-#define SXIFCCG_DEBUG_REG0__position_address__SHIFT 0x0
-#define SXIFCCG_DEBUG_REG0__point_address_MASK 0x1c0
-#define SXIFCCG_DEBUG_REG0__point_address__SHIFT 0x6
-#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0xe00
-#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x9
-#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK 0xf000
-#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT 0xc
-#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK 0x3ff0000
-#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT 0x10
-#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK 0xc000000
-#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT 0x1a
-#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id_MASK 0x30000000
-#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id__SHIFT 0x1c
-#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK 0x40000000
-#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT 0x1e
-#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance_MASK 0x80000000
-#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance__SHIFT 0x1f
-#define SXIFCCG_DEBUG_REG1__available_positions_MASK 0x7f
-#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT 0x0
-#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK 0x380
-#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT 0x7
-#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents_MASK 0x7c00
-#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents__SHIFT 0xa
-#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena_MASK 0x8000
-#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena__SHIFT 0xf
-#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp_MASK 0xf0000
-#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp__SHIFT 0x10
-#define SXIFCCG_DEBUG_REG1__aux_sel_MASK 0x300000
-#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT 0x14
-#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1_MASK 0x400000
-#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1__SHIFT 0x16
-#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0_MASK 0x800000
-#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0__SHIFT 0x17
-#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1_MASK 0xf000000
-#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1__SHIFT 0x18
-#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0_MASK 0xf0000000
-#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0__SHIFT 0x1c
-#define SXIFCCG_DEBUG_REG2__param_cache_base_MASK 0x7f
-#define SXIFCCG_DEBUG_REG2__param_cache_base__SHIFT 0x0
-#define SXIFCCG_DEBUG_REG2__sx_aux_MASK 0x180
-#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT 0x7
-#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK 0x7e00
-#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT 0x9
-#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK 0x8000
-#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0xf
-#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK 0x7f0000
-#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT 0x10
-#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x3800000
-#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x17
-#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0xfc000000
-#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x1a
-#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO_MASK 0xff
-#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO__SHIFT 0x0
-#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0xf00
-#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x8
-#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena_MASK 0x1000
-#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena__SHIFT 0xc
-#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena_MASK 0x2000
-#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena__SHIFT 0xd
-#define SXIFCCG_DEBUG_REG3__available_positions_MASK 0x1fc000
-#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT 0xe
-#define SXIFCCG_DEBUG_REG3__current_state_MASK 0x600000
-#define SXIFCCG_DEBUG_REG3__current_state__SHIFT 0x15
-#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK 0x800000
-#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT 0x17
-#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK 0x1000000
-#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT 0x18
-#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK 0x2000000
-#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT 0x19
-#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK 0x4000000
-#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT 0x1a
-#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK 0x8000000
-#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x1b
-#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK 0x10000000
-#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT 0x1c
-#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full_MASK 0x20000000
-#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full__SHIFT 0x1d
-#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write_MASK 0x40000000
-#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write__SHIFT 0x1e
-#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write_MASK 0x80000000
-#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write__SHIFT 0x1f
-#define SETUP_DEBUG_REG0__su_baryc_cntl_state_MASK 0x3
-#define SETUP_DEBUG_REG0__su_baryc_cntl_state__SHIFT 0x0
-#define SETUP_DEBUG_REG0__su_cntl_state_MASK 0x3c
-#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT 0x2
-#define SETUP_DEBUG_REG0__pmode_state_MASK 0x3f00
-#define SETUP_DEBUG_REG0__pmode_state__SHIFT 0x8
-#define SETUP_DEBUG_REG0__ge_stallb_MASK 0x4000
-#define SETUP_DEBUG_REG0__ge_stallb__SHIFT 0xe
-#define SETUP_DEBUG_REG0__geom_enable_MASK 0x8000
-#define SETUP_DEBUG_REG0__geom_enable__SHIFT 0xf
-#define SETUP_DEBUG_REG0__su_clip_baryc_free_MASK 0x30000
-#define SETUP_DEBUG_REG0__su_clip_baryc_free__SHIFT 0x10
-#define SETUP_DEBUG_REG0__su_clip_rtr_MASK 0x40000
-#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT 0x12
-#define SETUP_DEBUG_REG0__pfifo_busy_MASK 0x80000
-#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT 0x13
-#define SETUP_DEBUG_REG0__su_cntl_busy_MASK 0x100000
-#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT 0x14
-#define SETUP_DEBUG_REG0__geom_busy_MASK 0x200000
-#define SETUP_DEBUG_REG0__geom_busy__SHIFT 0x15
-#define SETUP_DEBUG_REG0__event_id_gated_MASK 0xfc00000
-#define SETUP_DEBUG_REG0__event_id_gated__SHIFT 0x16
-#define SETUP_DEBUG_REG0__event_gated_MASK 0x10000000
-#define SETUP_DEBUG_REG0__event_gated__SHIFT 0x1c
-#define SETUP_DEBUG_REG0__pmode_prim_gated_MASK 0x20000000
-#define SETUP_DEBUG_REG0__pmode_prim_gated__SHIFT 0x1d
-#define SETUP_DEBUG_REG0__su_dyn_sclk_vld_MASK 0x40000000
-#define SETUP_DEBUG_REG0__su_dyn_sclk_vld__SHIFT 0x1e
-#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld_MASK 0x80000000
-#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld__SHIFT 0x1f
-#define SETUP_DEBUG_REG1__y_sort0_gated_23_8_MASK 0xffff
-#define SETUP_DEBUG_REG1__y_sort0_gated_23_8__SHIFT 0x0
-#define SETUP_DEBUG_REG1__x_sort0_gated_23_8_MASK 0xffff0000
-#define SETUP_DEBUG_REG1__x_sort0_gated_23_8__SHIFT 0x10
-#define SETUP_DEBUG_REG2__y_sort1_gated_23_8_MASK 0xffff
-#define SETUP_DEBUG_REG2__y_sort1_gated_23_8__SHIFT 0x0
-#define SETUP_DEBUG_REG2__x_sort1_gated_23_8_MASK 0xffff0000
-#define SETUP_DEBUG_REG2__x_sort1_gated_23_8__SHIFT 0x10
-#define SETUP_DEBUG_REG3__y_sort2_gated_23_8_MASK 0xffff
-#define SETUP_DEBUG_REG3__y_sort2_gated_23_8__SHIFT 0x0
-#define SETUP_DEBUG_REG3__x_sort2_gated_23_8_MASK 0xffff0000
-#define SETUP_DEBUG_REG3__x_sort2_gated_23_8__SHIFT 0x10
-#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK 0x3fff
-#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT 0x0
-#define SETUP_DEBUG_REG4__null_prim_gated_MASK 0x4000
-#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT 0xe
-#define SETUP_DEBUG_REG4__backfacing_gated_MASK 0x8000
-#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT 0xf
-#define SETUP_DEBUG_REG4__st_indx_gated_MASK 0x70000
-#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT 0x10
-#define SETUP_DEBUG_REG4__clipped_gated_MASK 0x80000
-#define SETUP_DEBUG_REG4__clipped_gated__SHIFT 0x13
-#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK 0x700000
-#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT 0x14
-#define SETUP_DEBUG_REG4__xmajor_gated_MASK 0x800000
-#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT 0x17
-#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK 0x3000000
-#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT 0x18
-#define SETUP_DEBUG_REG4__type_gated_MASK 0x1c000000
-#define SETUP_DEBUG_REG4__type_gated__SHIFT 0x1a
-#define SETUP_DEBUG_REG4__fpov_gated_MASK 0x60000000
-#define SETUP_DEBUG_REG4__fpov_gated__SHIFT 0x1d
-#define SETUP_DEBUG_REG4__eop_gated_MASK 0x80000000
-#define SETUP_DEBUG_REG4__eop_gated__SHIFT 0x1f
-#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK 0x3fff
-#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT 0x0
-#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK 0xfffc000
-#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT 0xe
-#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK 0x30000000
-#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT 0x1c
-#define SETUP_DEBUG_REG5__valid_prim_gated_MASK 0x40000000
-#define SETUP_DEBUG_REG5__valid_prim_gated__SHIFT 0x1e
-#define SETUP_DEBUG_REG5__pa_reg_sclk_vld_MASK 0x80000000
-#define SETUP_DEBUG_REG5__pa_reg_sclk_vld__SHIFT 0x1f
-#define PA_SC_DEBUG_REG0__REG0_FIELD0_MASK 0x3
-#define PA_SC_DEBUG_REG0__REG0_FIELD0__SHIFT 0x0
-#define PA_SC_DEBUG_REG0__REG0_FIELD1_MASK 0xc
-#define PA_SC_DEBUG_REG0__REG0_FIELD1__SHIFT 0x2
-#define PA_SC_DEBUG_REG1__REG1_FIELD0_MASK 0x3
-#define PA_SC_DEBUG_REG1__REG1_FIELD0__SHIFT 0x0
-#define PA_SC_DEBUG_REG1__REG1_FIELD1_MASK 0xc
-#define PA_SC_DEBUG_REG1__REG1_FIELD1__SHIFT 0x2
-#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x1
-#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0
-#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x2
-#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1
-#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x4
-#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2
-#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x8
-#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3
-#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x10
-#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4
-#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x20
-#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5
-#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x40
-#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6
-#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL_MASK 0x380
-#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL__SHIFT 0x7
-#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x400
-#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa
-#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x800
-#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb
-#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC_MASK 0x1000
-#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC__SHIFT 0xc
-#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x4000
-#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe
-#define COMPUTE_DIM_X__SIZE_MASK 0xffffffff
-#define COMPUTE_DIM_X__SIZE__SHIFT 0x0
-#define COMPUTE_DIM_Y__SIZE_MASK 0xffffffff
-#define COMPUTE_DIM_Y__SIZE__SHIFT 0x0
-#define COMPUTE_DIM_Z__SIZE_MASK 0xffffffff
-#define COMPUTE_DIM_Z__SIZE__SHIFT 0x0
-#define COMPUTE_START_X__START_MASK 0xffffffff
-#define COMPUTE_START_X__START__SHIFT 0x0
-#define COMPUTE_START_Y__START_MASK 0xffffffff
-#define COMPUTE_START_Y__START__SHIFT 0x0
-#define COMPUTE_START_Z__START_MASK 0xffffffff
-#define COMPUTE_START_Z__START__SHIFT 0x0
-#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0xffff
-#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0
-#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xffff0000
-#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10
-#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0xffff
-#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0
-#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xffff0000
-#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10
-#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0xffff
-#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0
-#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xffff0000
-#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10
-#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x1
-#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0
-#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x1
-#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0
-#define COMPUTE_PGM_LO__DATA_MASK 0xffffffff
-#define COMPUTE_PGM_LO__DATA__SHIFT 0x0
-#define COMPUTE_PGM_HI__DATA_MASK 0xff
-#define COMPUTE_PGM_HI__DATA__SHIFT 0x0
-#define COMPUTE_PGM_HI__INST_ATC_MASK 0x100
-#define COMPUTE_PGM_HI__INST_ATC__SHIFT 0x8
-#define COMPUTE_TBA_LO__DATA_MASK 0xffffffff
-#define COMPUTE_TBA_LO__DATA__SHIFT 0x0
-#define COMPUTE_TBA_HI__DATA_MASK 0xff
-#define COMPUTE_TBA_HI__DATA__SHIFT 0x0
-#define COMPUTE_TMA_LO__DATA_MASK 0xffffffff
-#define COMPUTE_TMA_LO__DATA__SHIFT 0x0
-#define COMPUTE_TMA_HI__DATA_MASK 0xff
-#define COMPUTE_TMA_HI__DATA__SHIFT 0x0
-#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x3f
-#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0
-#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x3c0
-#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6
-#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0xc00
-#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa
-#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0xff000
-#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc
-#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x100000
-#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14
-#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x200000
-#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15
-#define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK 0x400000
-#define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT 0x16
-#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x800000
-#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17
-#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x1000000
-#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18
-#define COMPUTE_PGM_RSRC1__CDBG_USER_MASK 0x2000000
-#define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT 0x19
-#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x1
-#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0
-#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x3e
-#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1
-#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x40
-#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6
-#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x80
-#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7
-#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x100
-#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8
-#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x200
-#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9
-#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x400
-#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa
-#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x1800
-#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb
-#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x6000
-#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd
-#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0xff8000
-#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf
-#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7f000000
-#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18
-#define COMPUTE_VMID__DATA_MASK 0xf
-#define COMPUTE_VMID__DATA__SHIFT 0x0
-#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x3ff
-#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0
-#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0xf000
-#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc
-#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x3f0000
-#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10
-#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x400000
-#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16
-#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x800000
-#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17
-#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x7000000
-#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18
-#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0xffff
-#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x0
-#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xffff0000
-#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x10
-#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0xffff
-#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x0
-#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xffff0000
-#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x10
-#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0xfff
-#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0
-#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x1fff000
-#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc
-#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK 0xffff
-#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT 0x0
-#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK 0xffff0000
-#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT 0x10
-#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK 0xffff
-#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT 0x0
-#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK 0xffff0000
-#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT 0x10
-#define COMPUTE_RESTART_X__RESTART_MASK 0xffffffff
-#define COMPUTE_RESTART_X__RESTART__SHIFT 0x0
-#define COMPUTE_RESTART_Y__RESTART_MASK 0xffffffff
-#define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0
-#define COMPUTE_RESTART_Z__RESTART_MASK 0xffffffff
-#define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0
-#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x1
-#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0
-#define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x3
-#define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0
-#define COMPUTE_MISC_RESERVED__RESERVED2_MASK 0x4
-#define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT 0x2
-#define COMPUTE_MISC_RESERVED__RESERVED3_MASK 0x8
-#define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT 0x3
-#define COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x10
-#define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4
-#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK 0x1ffe0
-#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT 0x5
-#define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK 0xffffffff
-#define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT 0x0
-#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK 0xffffffff
-#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT 0x0
-#define COMPUTE_RELAUNCH__PAYLOAD_MASK 0x3fffffff
-#define COMPUTE_RELAUNCH__PAYLOAD__SHIFT 0x0
-#define COMPUTE_RELAUNCH__IS_EVENT_MASK 0x40000000
-#define COMPUTE_RELAUNCH__IS_EVENT__SHIFT 0x1e
-#define COMPUTE_RELAUNCH__IS_STATE_MASK 0x80000000
-#define COMPUTE_RELAUNCH__IS_STATE__SHIFT 0x1f
-#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK 0xffffffff
-#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT 0x0
-#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK 0xffff
-#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT 0x0
-#define COMPUTE_WAVE_RESTORE_CONTROL__ATC_MASK 0x1
-#define COMPUTE_WAVE_RESTORE_CONTROL__ATC__SHIFT 0x0
-#define COMPUTE_WAVE_RESTORE_CONTROL__MTYPE_MASK 0x6
-#define COMPUTE_WAVE_RESTORE_CONTROL__MTYPE__SHIFT 0x1
-#define COMPUTE_USER_DATA_0__DATA_MASK 0xffffffff
-#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_1__DATA_MASK 0xffffffff
-#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_2__DATA_MASK 0xffffffff
-#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_3__DATA_MASK 0xffffffff
-#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_4__DATA_MASK 0xffffffff
-#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_5__DATA_MASK 0xffffffff
-#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_6__DATA_MASK 0xffffffff
-#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_7__DATA_MASK 0xffffffff
-#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_8__DATA_MASK 0xffffffff
-#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_9__DATA_MASK 0xffffffff
-#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_10__DATA_MASK 0xffffffff
-#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_11__DATA_MASK 0xffffffff
-#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_12__DATA_MASK 0xffffffff
-#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_13__DATA_MASK 0xffffffff
-#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_14__DATA_MASK 0xffffffff
-#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0
-#define COMPUTE_USER_DATA_15__DATA_MASK 0xffffffff
-#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0
-#define COMPUTE_NOWHERE__DATA_MASK 0xffffffff
-#define COMPUTE_NOWHERE__DATA__SHIFT 0x0
-#define CSPRIV_CONNECT__DOORBELL_OFFSET_MASK 0x1fffff
-#define CSPRIV_CONNECT__DOORBELL_OFFSET__SHIFT 0x0
-#define CSPRIV_CONNECT__QUEUE_ID_MASK 0xe00000
-#define CSPRIV_CONNECT__QUEUE_ID__SHIFT 0x15
-#define CSPRIV_CONNECT__VMID_MASK 0x3c000000
-#define CSPRIV_CONNECT__VMID__SHIFT 0x1a
-#define CSPRIV_CONNECT__UNORD_DISP_MASK 0x80000000
-#define CSPRIV_CONNECT__UNORD_DISP__SHIFT 0x1f
-#define CSPRIV_THREAD_TRACE_TG0__TGID_X_MASK 0xffffffff
-#define CSPRIV_THREAD_TRACE_TG0__TGID_X__SHIFT 0x0
-#define CSPRIV_THREAD_TRACE_TG1__TGID_Y_MASK 0xffffffff
-#define CSPRIV_THREAD_TRACE_TG1__TGID_Y__SHIFT 0x0
-#define CSPRIV_THREAD_TRACE_TG2__TGID_Z_MASK 0xffffffff
-#define CSPRIV_THREAD_TRACE_TG2__TGID_Z__SHIFT 0x0
-#define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE_MASK 0xfff
-#define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE__SHIFT 0x0
-#define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP_MASK 0xfff000
-#define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP__SHIFT 0xc
-#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG_MASK 0x1000000
-#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG__SHIFT 0x18
-#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG_MASK 0x2000000
-#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG__SHIFT 0x19
-#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG_MASK 0x4000000
-#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG__SHIFT 0x1a
-#define CSPRIV_THREAD_TRACE_TG3__LAST_TG_MASK 0x8000000
-#define CSPRIV_THREAD_TRACE_TG3__LAST_TG__SHIFT 0x1b
-#define CSPRIV_THREAD_TRACE_TG3__FIRST_TG_MASK 0x10000000
-#define CSPRIV_THREAD_TRACE_TG3__FIRST_TG__SHIFT 0x1c
-#define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID_MASK 0x1f
-#define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID__SHIFT 0x0
-#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x1
-#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0
-#define RLC_CNTL__FORCE_RETRY_MASK 0x2
-#define RLC_CNTL__FORCE_RETRY__SHIFT 0x1
-#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x4
-#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2
-#define RLC_CNTL__RLC_STEP_F32_MASK 0x8
-#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3
-#define RLC_CNTL__SOFT_RESET_DEBUG_MODE_MASK 0x10
-#define RLC_CNTL__SOFT_RESET_DEBUG_MODE__SHIFT 0x4
-#define RLC_CNTL__RESERVED_MASK 0xffffff00
-#define RLC_CNTL__RESERVED__SHIFT 0x8
-#define RLC_DEBUG_SELECT__SELECT_MASK 0xff
-#define RLC_DEBUG_SELECT__SELECT__SHIFT 0x0
-#define RLC_DEBUG_SELECT__RESERVED_MASK 0xffffff00
-#define RLC_DEBUG_SELECT__RESERVED__SHIFT 0x8
-#define RLC_DEBUG__DATA_MASK 0xffffffff
-#define RLC_DEBUG__DATA__SHIFT 0x0
-#define RLC_MC_CNTL__WRREQ_SWAP_MASK 0x3
-#define RLC_MC_CNTL__WRREQ_SWAP__SHIFT 0x0
-#define RLC_MC_CNTL__WRREQ_TRAN_MASK 0x4
-#define RLC_MC_CNTL__WRREQ_TRAN__SHIFT 0x2
-#define RLC_MC_CNTL__WRREQ_PRIV_MASK 0x8
-#define RLC_MC_CNTL__WRREQ_PRIV__SHIFT 0x3
-#define RLC_MC_CNTL__WRNFO_STALL_MASK 0x10
-#define RLC_MC_CNTL__WRNFO_STALL__SHIFT 0x4
-#define RLC_MC_CNTL__WRNFO_URG_MASK 0x1e0
-#define RLC_MC_CNTL__WRNFO_URG__SHIFT 0x5
-#define RLC_MC_CNTL__WRREQ_DW_IMASK_MASK 0x1e00
-#define RLC_MC_CNTL__WRREQ_DW_IMASK__SHIFT 0x9
-#define RLC_MC_CNTL__RESERVED_B_MASK 0xfe000
-#define RLC_MC_CNTL__RESERVED_B__SHIFT 0xd
-#define RLC_MC_CNTL__RDNFO_URG_MASK 0xf00000
-#define RLC_MC_CNTL__RDNFO_URG__SHIFT 0x14
-#define RLC_MC_CNTL__RDREQ_SWAP_MASK 0x3000000
-#define RLC_MC_CNTL__RDREQ_SWAP__SHIFT 0x18
-#define RLC_MC_CNTL__RDREQ_TRAN_MASK 0x4000000
-#define RLC_MC_CNTL__RDREQ_TRAN__SHIFT 0x1a
-#define RLC_MC_CNTL__RDREQ_PRIV_MASK 0x8000000
-#define RLC_MC_CNTL__RDREQ_PRIV__SHIFT 0x1b
-#define RLC_MC_CNTL__RDNFO_STALL_MASK 0x10000000
-#define RLC_MC_CNTL__RDNFO_STALL__SHIFT 0x1c
-#define RLC_MC_CNTL__RESERVED_MASK 0xe0000000
-#define RLC_MC_CNTL__RESERVED__SHIFT 0x1d
-#define RLC_STAT__RLC_BUSY_MASK 0x1
-#define RLC_STAT__RLC_BUSY__SHIFT 0x0
-#define RLC_STAT__RLC_GPM_BUSY_MASK 0x2
-#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x1
-#define RLC_STAT__RLC_SPM_BUSY_MASK 0x4
-#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x2
-#define RLC_STAT__RLC_SRM_BUSY_MASK 0x8
-#define RLC_STAT__RLC_SRM_BUSY__SHIFT 0x3
-#define RLC_STAT__RESERVED_MASK 0xfffffff0
-#define RLC_STAT__RESERVED__SHIFT 0x4
-#define RLC_SAFE_MODE__CMD_MASK 0x1
-#define RLC_SAFE_MODE__CMD__SHIFT 0x0
-#define RLC_SAFE_MODE__MESSAGE_MASK 0x1e
-#define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1
-#define RLC_SAFE_MODE__RESERVED1_MASK 0xe0
-#define RLC_SAFE_MODE__RESERVED1__SHIFT 0x5
-#define RLC_SAFE_MODE__RESPONSE_MASK 0xf00
-#define RLC_SAFE_MODE__RESPONSE__SHIFT 0x8
-#define RLC_SAFE_MODE__RESERVED_MASK 0xfffff000
-#define RLC_SAFE_MODE__RESERVED__SHIFT 0xc
-#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x1
-#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0
-#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x2
-#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1
-#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x7c
-#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
-#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK 0x80
-#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT 0x7
-#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0xff00
-#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8
-#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0xff0000
-#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10
-#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000
-#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
-#define SMU_RLC_RESPONSE__RESP_MASK 0xffffffff
-#define SMU_RLC_RESPONSE__RESP__SHIFT 0x0
-#define RLC_RLCV_SAFE_MODE__CMD_MASK 0x1
-#define RLC_RLCV_SAFE_MODE__CMD__SHIFT 0x0
-#define RLC_RLCV_SAFE_MODE__MESSAGE_MASK 0x1e
-#define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT 0x1
-#define RLC_RLCV_SAFE_MODE__RESERVED1_MASK 0xe0
-#define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT 0x5
-#define RLC_RLCV_SAFE_MODE__RESPONSE_MASK 0xf00
-#define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT 0x8
-#define RLC_RLCV_SAFE_MODE__RESERVED_MASK 0xfffff000
-#define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT 0xc
-#define RLC_SMU_SAFE_MODE__CMD_MASK 0x1
-#define RLC_SMU_SAFE_MODE__CMD__SHIFT 0x0
-#define RLC_SMU_SAFE_MODE__MESSAGE_MASK 0x1e
-#define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT 0x1
-#define RLC_SMU_SAFE_MODE__RESERVED1_MASK 0xe0
-#define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT 0x5
-#define RLC_SMU_SAFE_MODE__RESPONSE_MASK 0xf00
-#define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT 0x8
-#define RLC_SMU_SAFE_MODE__RESERVED_MASK 0xfffff000
-#define RLC_SMU_SAFE_MODE__RESERVED__SHIFT 0xc
-#define RLC_RLCV_COMMAND__CMD_MASK 0xf
-#define RLC_RLCV_COMMAND__CMD__SHIFT 0x0
-#define RLC_RLCV_COMMAND__RESERVED_MASK 0xfffffff0
-#define RLC_RLCV_COMMAND__RESERVED__SHIFT 0x4
-#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL_MASK 0x1
-#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL__SHIFT 0x0
-#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK 0x2
-#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL__SHIFT 0x1
-#define RLC_CLK_CNTL__RESERVED_MASK 0xfffffffc
-#define RLC_CLK_CNTL__RESERVED__SHIFT 0x2
-#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK 0x1
-#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE__SHIFT 0x0
-#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x7
-#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
-#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400
-#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
-#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0xff
-#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
-#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0xff
-#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
-#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0xf
-#define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
-#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
-#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
-#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
-#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
-#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x1
-#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x0
-#define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x2
-#define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x1
-#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x4
-#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x2
-#define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x8
-#define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x3
-#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0xff0
-#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x4
-#define RLC_LB_CNTL__RESERVED_MASK 0xfffff000
-#define RLC_LB_CNTL__RESERVED__SHIFT 0xc
-#define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xffffffff
-#define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x0
-#define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xffffffff
-#define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x0
-#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xffffffff
-#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0
-#define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xffffffff
-#define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0
-#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0xff
-#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0
-#define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0xff00
-#define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8
-#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK 0xffff0000
-#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT 0x10
-#define RLC_GPM_DEBUG_SELECT__SELECT_MASK 0xff
-#define RLC_GPM_DEBUG_SELECT__SELECT__SHIFT 0x0
-#define RLC_GPM_DEBUG_SELECT__F32_DEBUG_SELECT_MASK 0x300
-#define RLC_GPM_DEBUG_SELECT__F32_DEBUG_SELECT__SHIFT 0x8
-#define RLC_GPM_DEBUG_SELECT__RESERVED_MASK 0xfffffc00
-#define RLC_GPM_DEBUG_SELECT__RESERVED__SHIFT 0xa
-#define RLC_GPM_DEBUG__DATA_MASK 0xffffffff
-#define RLC_GPM_DEBUG__DATA__SHIFT 0x0
-#define RLC_GPM_DEBUG_INST_A__INST_A_MASK 0xffffffff
-#define RLC_GPM_DEBUG_INST_A__INST_A__SHIFT 0x0
-#define RLC_GPM_DEBUG_INST_B__INST_B_MASK 0xffffffff
-#define RLC_GPM_DEBUG_INST_B__INST_B__SHIFT 0x0
-#define RLC_GPM_DEBUG_INST_ADDR__ADRR_A_MASK 0xffff
-#define RLC_GPM_DEBUG_INST_ADDR__ADRR_A__SHIFT 0x0
-#define RLC_GPM_DEBUG_INST_ADDR__ADDR_B_MASK 0xffff0000
-#define RLC_GPM_DEBUG_INST_ADDR__ADDR_B__SHIFT 0x10
-#define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
-#define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
-#define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xfffff000
-#define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xc
-#define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
-#define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0
-#define GPU_BIST_CONTROL__STOP_ON_FAIL_HW_MASK 0x1
-#define GPU_BIST_CONTROL__STOP_ON_FAIL_HW__SHIFT 0x0
-#define GPU_BIST_CONTROL__STOP_ON_FAIL_CU_HARV_MASK 0x2
-#define GPU_BIST_CONTROL__STOP_ON_FAIL_CU_HARV__SHIFT 0x1
-#define GPU_BIST_CONTROL__CU_HARV_LOOP_COUNT_MASK 0x3c
-#define GPU_BIST_CONTROL__CU_HARV_LOOP_COUNT__SHIFT 0x2
-#define GPU_BIST_CONTROL__RESERVED_MASK 0xffff80
-#define GPU_BIST_CONTROL__RESERVED__SHIFT 0x7
-#define GPU_BIST_CONTROL__GLOBAL_LOOP_COUNT_MASK 0xff000000
-#define GPU_BIST_CONTROL__GLOBAL_LOOP_COUNT__SHIFT 0x18
-#define RLC_ROM_CNTL__USE_ROM_MASK 0x1
-#define RLC_ROM_CNTL__USE_ROM__SHIFT 0x0
-#define RLC_ROM_CNTL__SLP_MODE_EN_MASK 0x2
-#define RLC_ROM_CNTL__SLP_MODE_EN__SHIFT 0x1
-#define RLC_ROM_CNTL__EFUSE_DISTRIB_EN_MASK 0x4
-#define RLC_ROM_CNTL__EFUSE_DISTRIB_EN__SHIFT 0x2
-#define RLC_ROM_CNTL__HELLOWORLD_EN_MASK 0x8
-#define RLC_ROM_CNTL__HELLOWORLD_EN__SHIFT 0x3
-#define RLC_ROM_CNTL__CU_HARVEST_EN_MASK 0x10
-#define RLC_ROM_CNTL__CU_HARVEST_EN__SHIFT 0x4
-#define RLC_ROM_CNTL__RESERVED_MASK 0xffffffe0
-#define RLC_ROM_CNTL__RESERVED__SHIFT 0x5
-#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xffffffff
-#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0
-#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xffffffff
-#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0
-#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x1
-#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0
-#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xfffffffe
-#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1
-#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xffffffff
-#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0
-#define RLC_GPM_STAT__RLC_BUSY_MASK 0x1
-#define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0
-#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x2
-#define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1
-#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x4
-#define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2
-#define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x8
-#define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3
-#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x10
-#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4
-#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x20
-#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5
-#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x40
-#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6
-#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x80
-#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7
-#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x100
-#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8
-#define RLC_GPM_STAT__SAVING_REGISTERS_MASK 0x200
-#define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9
-#define RLC_GPM_STAT__RESTORING_REGISTERS_MASK 0x400
-#define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa
-#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x800
-#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb
-#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x1000
-#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc
-#define RLC_GPM_STAT__STATIC_CU_POWERING_UP_MASK 0x2000
-#define RLC_GPM_STAT__STATIC_CU_POWERING_UP__SHIFT 0xd
-#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN_MASK 0x4000
-#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN__SHIFT 0xe
-#define RLC_GPM_STAT__DYN_CU_POWERING_UP_MASK 0x8000
-#define RLC_GPM_STAT__DYN_CU_POWERING_UP__SHIFT 0xf
-#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN_MASK 0x10000
-#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN__SHIFT 0x10
-#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x20000
-#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11
-#define RLC_GPM_STAT__RESERVED_MASK 0xfc0000
-#define RLC_GPM_STAT__RESERVED__SHIFT 0x12
-#define RLC_GPM_STAT__PG_ERROR_STATUS_MASK 0xff000000
-#define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18
-#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x3f
-#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0
-#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xffffffc0
-#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6
-#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xffffffff
-#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0
-#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x1
-#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0
-#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x2
-#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1
-#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x4
-#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x2
-#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x8
-#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x3
-#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK 0x10
-#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT 0x4
-#define RLC_PG_CNTL__RESERVED_MASK 0x3fe0
-#define RLC_PG_CNTL__RESERVED__SHIFT 0x5
-#define RLC_PG_CNTL__PG_OVERRIDE_MASK 0x4000
-#define RLC_PG_CNTL__PG_OVERRIDE__SHIFT 0xe
-#define RLC_PG_CNTL__CP_PG_DISABLE_MASK 0x8000
-#define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT 0xf
-#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x10000
-#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10
-#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x20000
-#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x11
-#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x40000
-#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x12
-#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE_MASK 0x80000
-#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE__SHIFT 0x13
-#define RLC_PG_CNTL__RESERVED1_MASK 0xf00000
-#define RLC_PG_CNTL__RESERVED1__SHIFT 0x14
-#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0xff
-#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0
-#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0xff00
-#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8
-#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0xff0000
-#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10
-#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xff000000
-#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18
-#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x1
-#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0
-#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x2
-#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1
-#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x4
-#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2
-#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x8
-#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3
-#define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xfffffff0
-#define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4
-#define RLC_GPM_VMID_THREAD0__RLC_VMID_MASK 0xf
-#define RLC_GPM_VMID_THREAD0__RLC_VMID__SHIFT 0x0
-#define RLC_GPM_VMID_THREAD0__RESERVED0_MASK 0xf0
-#define RLC_GPM_VMID_THREAD0__RESERVED0__SHIFT 0x4
-#define RLC_GPM_VMID_THREAD0__RLC_QUEUEID_MASK 0x700
-#define RLC_GPM_VMID_THREAD0__RLC_QUEUEID__SHIFT 0x8
-#define RLC_GPM_VMID_THREAD0__RESERVED1_MASK 0xfffff800
-#define RLC_GPM_VMID_THREAD0__RESERVED1__SHIFT 0xb
-#define RLC_GPM_VMID_THREAD1__RLC_VMID_MASK 0xf
-#define RLC_GPM_VMID_THREAD1__RLC_VMID__SHIFT 0x0
-#define RLC_GPM_VMID_THREAD1__RESERVED0_MASK 0xf0
-#define RLC_GPM_VMID_THREAD1__RESERVED0__SHIFT 0x4
-#define RLC_GPM_VMID_THREAD1__RLC_QUEUEID_MASK 0x700
-#define RLC_GPM_VMID_THREAD1__RLC_QUEUEID__SHIFT 0x8
-#define RLC_GPM_VMID_THREAD1__RESERVED1_MASK 0xfffff800
-#define RLC_GPM_VMID_THREAD1__RESERVED1__SHIFT 0xb
-#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE_MASK 0xffffffff
-#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE__SHIFT 0x0
-#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x1
-#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0
-#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x2
-#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1
-#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0xfc
-#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2
-#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x7ffff00
-#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8
-#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x8000000
-#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b
-#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000
-#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c
-#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000
-#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d
-#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK 0x80000000
-#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT 0x1f
-#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0xf
-#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0
-#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0xf0
-#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4
-#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0xf00
-#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8
-#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0xf000
-#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc
-#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0xfff0000
-#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10
-#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xf0000000
-#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c
-#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffff
-#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0
-#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xffffffff
-#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x0
-#define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0xff
-#define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0
-#define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0xff00
-#define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8
-#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0xff0000
-#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10
-#define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xff000000
-#define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18
-#define RLC_CU_STATUS__WORK_PENDING_MASK 0xffffffff
-#define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x0
-#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xffffffff
-#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x0
-#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xffffffff
-#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x0
-#define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x1
-#define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x0
-#define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0xfe
-#define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x1
-#define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0xff00
-#define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x8
-#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xffff0000
-#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x10
-#define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0xff
-#define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x0
-#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0xff00
-#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x8
-#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0xff0000
-#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x10
-#define RLC_THREAD1_DELAY__SPARE_MASK 0xff000000
-#define RLC_THREAD1_DELAY__SPARE__SHIFT 0x18
-#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xffffffff
-#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x0
-#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0xff
-#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x0
-#define RLC_MAX_PG_CU__SPARE_MASK 0xffffff00
-#define RLC_MAX_PG_CU__SPARE__SHIFT 0x8
-#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x1
-#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0
-#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x2
-#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1
-#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x4
-#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2
-#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x7fff8
-#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3
-#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xfff80000
-#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13
-#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x1
-#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x0
-#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xfffffffe
-#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x1
-#define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0xf
-#define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x0
-#define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x30
-#define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x4
-#define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x1c0
-#define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x6
-#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x200
-#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x9
-#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x400
-#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0xa
-#define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x7800
-#define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0xb
-#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0x18000
-#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0xf
-#define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xfffe0000
-#define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x11
-#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xffffffff
-#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0
-#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xffffffff
-#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0
-#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xffffffff
-#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0
-#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK 0xffffffff
-#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT 0x0
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK 0xffff
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT 0x0
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK 0x10000
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT 0x10
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK_MASK 0x20000
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK__SHIFT 0x11
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK 0x40000
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT 0x12
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK 0x80000
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT 0x13
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK 0x100000
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT 0x14
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK 0x200000
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT 0x15
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK 0x400000
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT 0x16
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK 0x800000
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT 0x17
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK 0xff000000
-#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT 0x18
-#define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0xff
-#define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x0
-#define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x100
-#define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x8
-#define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x200
-#define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x9
-#define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x400
-#define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0xa
-#define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x800
-#define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0xb
-#define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x1000
-#define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0xc
-#define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x2000
-#define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0xd
-#define RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK 0x4000
-#define RLC_SERDES_WR_CTRL__RDDATA_RESET__SHIFT 0xe
-#define RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK 0x8000
-#define RLC_SERDES_WR_CTRL__SHORT_FORMAT__SHIFT 0xf
-#define RLC_SERDES_WR_CTRL__BPM_DATA_MASK 0x3ff0000
-#define RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT 0x10
-#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK 0x4000000
-#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE__SHIFT 0x1a
-#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK 0x8000000
-#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR__SHIFT 0x1b
-#define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xf0000000
-#define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x1c
-#define RLC_SERDES_WR_DATA__DATA_MASK 0xffffffff
-#define RLC_SERDES_WR_DATA__DATA__SHIFT 0x0
-#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK 0xffffffff
-#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT 0x0
-#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK 0xffff
-#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT 0x0
-#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK 0x10000
-#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT 0x10
-#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY_MASK 0x20000
-#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY__SHIFT 0x11
-#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK 0x40000
-#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT 0x12
-#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK 0x80000
-#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT 0x13
-#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK 0x100000
-#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT 0x14
-#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK 0x200000
-#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT 0x15
-#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK 0x400000
-#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT 0x16
-#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK 0x800000
-#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT 0x17
-#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK 0xff000000
-#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT 0x18
-#define RLC_GPM_GENERAL_0__DATA_MASK 0xffffffff
-#define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_1__DATA_MASK 0xffffffff
-#define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_2__DATA_MASK 0xffffffff
-#define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_3__DATA_MASK 0xffffffff
-#define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_4__DATA_MASK 0xffffffff
-#define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_5__DATA_MASK 0xffffffff
-#define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_6__DATA_MASK 0xffffffff
-#define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_7__DATA_MASK 0xffffffff
-#define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0
-#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x1ff
-#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0
-#define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xfffffe00
-#define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x9
-#define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xffffffff
-#define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0
-#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffff
-#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0
-#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0xf
-#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0
-#define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0xf0
-#define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4
-#define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK 0xf00
-#define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT 0x8
-#define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK 0xf000
-#define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT 0xc
-#define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x30000
-#define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10
-#define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0xc0000
-#define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12
-#define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x100000
-#define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14
-#define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xffe00000
-#define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15
-#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0xf
-#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0
-#define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0xf0
-#define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4
-#define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK 0xf00
-#define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT 0x8
-#define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK 0xf000
-#define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT 0xc
-#define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x30000
-#define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10
-#define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0xc0000
-#define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12
-#define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x100000
-#define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14
-#define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xffe00000
-#define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15
-#define RLC_GPR_REG1__DATA_MASK 0xffffffff
-#define RLC_GPR_REG1__DATA__SHIFT 0x0
-#define RLC_GPR_REG2__DATA_MASK 0xffffffff
-#define RLC_GPR_REG2__DATA__SHIFT 0x0
-#define RLC_MGCG_CTRL__MGCG_EN_MASK 0x1
-#define RLC_MGCG_CTRL__MGCG_EN__SHIFT 0x0
-#define RLC_MGCG_CTRL__SILICON_EN_MASK 0x2
-#define RLC_MGCG_CTRL__SILICON_EN__SHIFT 0x1
-#define RLC_MGCG_CTRL__SIMULATION_EN_MASK 0x4
-#define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT 0x2
-#define RLC_MGCG_CTRL__ON_DELAY_MASK 0x78
-#define RLC_MGCG_CTRL__ON_DELAY__SHIFT 0x3
-#define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK 0x7f80
-#define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT 0x7
-#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL_MASK 0x8000
-#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL__SHIFT 0xf
-#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL_MASK 0x10000
-#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL__SHIFT 0x10
-#define RLC_MGCG_CTRL__SPARE_MASK 0xfffe0000
-#define RLC_MGCG_CTRL__SPARE__SHIFT 0x11
-#define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK 0x1
-#define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT 0x0
-#define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK 0x2
-#define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT 0x1
-#define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK 0x4
-#define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT 0x2
-#define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK 0x8
-#define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT 0x3
-#define RLC_GPM_THREAD_RESET__RESERVED_MASK 0xfffffff0
-#define RLC_GPM_THREAD_RESET__RESERVED__SHIFT 0x4
-#define RLC_SPM_VMID__RLC_SPM_VMID_MASK 0xf
-#define RLC_SPM_VMID__RLC_SPM_VMID__SHIFT 0x0
-#define RLC_SPM_VMID__RESERVED_MASK 0xfffffff0
-#define RLC_SPM_VMID__RESERVED__SHIFT 0x4
-#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x1
-#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0
-#define RLC_SPM_INT_CNTL__RESERVED_MASK 0xfffffffe
-#define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1
-#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x1
-#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0
-#define RLC_SPM_INT_STATUS__RESERVED_MASK 0xfffffffe
-#define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1
-#define RLC_SPM_DEBUG_SELECT__SELECT_MASK 0xff
-#define RLC_SPM_DEBUG_SELECT__SELECT__SHIFT 0x0
-#define RLC_SPM_DEBUG_SELECT__RESERVED_MASK 0x7f00
-#define RLC_SPM_DEBUG_SELECT__RESERVED__SHIFT 0x8
-#define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE_MASK 0x8000
-#define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE__SHIFT 0xf
-#define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE_MASK 0xffff0000
-#define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE__SHIFT 0x10
-#define RLC_SPM_DEBUG__DATA_MASK 0xffffffff
-#define RLC_SPM_DEBUG__DATA__SHIFT 0x0
-#define RLC_SMU_MESSAGE__CMD_MASK 0xffffffff
-#define RLC_SMU_MESSAGE__CMD__SHIFT 0x0
-#define RLC_GPM_LOG_SIZE__SIZE_MASK 0xffffffff
-#define RLC_GPM_LOG_SIZE__SIZE__SHIFT 0x0
-#define RLC_GPM_LOG_CONT__CONT_MASK 0xffffffff
-#define RLC_GPM_LOG_CONT__CONT__SHIFT 0x0
-#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK 0xff
-#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT 0x0
-#define RLC_PG_DELAY_3__RESERVED_MASK 0xffffff00
-#define RLC_PG_DELAY_3__RESERVED__SHIFT 0x8
-#define RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK 0xffffffff
-#define RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT 0x0
-#define RLC_GPM_INT_DISABLE_TH1__DISABLE_MASK 0xffffffff
-#define RLC_GPM_INT_DISABLE_TH1__DISABLE__SHIFT 0x0
-#define RLC_GPM_INT_FORCE_TH0__FORCE_MASK 0xffffffff
-#define RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT 0x0
-#define RLC_GPM_INT_FORCE_TH1__FORCE_MASK 0xffffffff
-#define RLC_GPM_INT_FORCE_TH1__FORCE__SHIFT 0x0
-#define RLC_SRM_CNTL__SRM_ENABLE_MASK 0x1
-#define RLC_SRM_CNTL__SRM_ENABLE__SHIFT 0x0
-#define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK 0x2
-#define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT 0x1
-#define RLC_SRM_CNTL__RESERVED_MASK 0xfffffffc
-#define RLC_SRM_CNTL__RESERVED__SHIFT 0x2
-#define RLC_SRM_DEBUG_SELECT__SELECT_MASK 0xff
-#define RLC_SRM_DEBUG_SELECT__SELECT__SHIFT 0x0
-#define RLC_SRM_DEBUG_SELECT__RESERVED_MASK 0xffffff00
-#define RLC_SRM_DEBUG_SELECT__RESERVED__SHIFT 0x8
-#define RLC_SRM_DEBUG__DATA_MASK 0xffffffff
-#define RLC_SRM_DEBUG__DATA__SHIFT 0x0
-#define RLC_SRM_ARAM_ADDR__ADDR_MASK 0x3ff
-#define RLC_SRM_ARAM_ADDR__ADDR__SHIFT 0x0
-#define RLC_SRM_ARAM_ADDR__RESERVED_MASK 0xfffffc00
-#define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT 0xa
-#define RLC_SRM_ARAM_DATA__DATA_MASK 0xffffffff
-#define RLC_SRM_ARAM_DATA__DATA__SHIFT 0x0
-#define RLC_SRM_DRAM_ADDR__ADDR_MASK 0x3ff
-#define RLC_SRM_DRAM_ADDR__ADDR__SHIFT 0x0
-#define RLC_SRM_DRAM_ADDR__RESERVED_MASK 0xfffffc00
-#define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT 0xa
-#define RLC_SRM_DRAM_DATA__DATA_MASK 0xffffffff
-#define RLC_SRM_DRAM_DATA__DATA__SHIFT 0x0
-#define RLC_SRM_GPM_COMMAND__OP_MASK 0x1
-#define RLC_SRM_GPM_COMMAND__OP__SHIFT 0x0
-#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK 0x2
-#define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT 0x1
-#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK 0x1c
-#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT 0x2
-#define RLC_SRM_GPM_COMMAND__SIZE_MASK 0x1ffe0
-#define RLC_SRM_GPM_COMMAND__SIZE__SHIFT 0x5
-#define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK 0x1ffe0000
-#define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT 0x11
-#define RLC_SRM_GPM_COMMAND__RESERVED1_MASK 0x60000000
-#define RLC_SRM_GPM_COMMAND__RESERVED1__SHIFT 0x1d
-#define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK 0x80000000
-#define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT 0x1f
-#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK 0x1
-#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0
-#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK 0x2
-#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1
-#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK 0xfffffffc
-#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT 0x2
-#define RLC_SRM_RLCV_COMMAND__OP_MASK 0x1
-#define RLC_SRM_RLCV_COMMAND__OP__SHIFT 0x0
-#define RLC_SRM_RLCV_COMMAND__RESERVED_MASK 0xe
-#define RLC_SRM_RLCV_COMMAND__RESERVED__SHIFT 0x1
-#define RLC_SRM_RLCV_COMMAND__SIZE_MASK 0xfff0
-#define RLC_SRM_RLCV_COMMAND__SIZE__SHIFT 0x4
-#define RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK 0xfff0000
-#define RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT 0x10
-#define RLC_SRM_RLCV_COMMAND__RESERVED1_MASK 0x70000000
-#define RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT 0x1c
-#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK 0x80000000
-#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT 0x1f
-#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK 0x1
-#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0
-#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK 0x2
-#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1
-#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK 0xfffffffc
-#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT 0x2
-#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK 0xffff
-#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK 0xffff0000
-#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT 0x10
-#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK 0xffff
-#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK 0xffff0000
-#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT 0x10
-#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK 0xffff
-#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK 0xffff0000
-#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT 0x10
-#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK 0xffff
-#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK 0xffff0000
-#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT 0x10
-#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK 0xffff
-#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK 0xffff0000
-#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT 0x10
-#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK 0xffff
-#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK 0xffff0000
-#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT 0x10
-#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK 0xffff
-#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK 0xffff0000
-#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT 0x10
-#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK 0xffff
-#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK 0xffff0000
-#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT 0x10
-#define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK 0xffffffff
-#define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK 0xffffffff
-#define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK 0xffffffff
-#define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK 0xffffffff
-#define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK 0xffffffff
-#define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK 0xffffffff
-#define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK 0xffffffff
-#define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT 0x0
-#define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK 0xffffffff
-#define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT 0x0
-#define RLC_SRM_STAT__SRM_STATUS_MASK 0x1
-#define RLC_SRM_STAT__SRM_STATUS__SHIFT 0x0
-#define RLC_SRM_STAT__RESERVED_MASK 0xfffffffe
-#define RLC_SRM_STAT__RESERVED__SHIFT 0x1
-#define RLC_SRM_GPM_ABORT__ABORT_MASK 0x1
-#define RLC_SRM_GPM_ABORT__ABORT__SHIFT 0x0
-#define RLC_SRM_GPM_ABORT__RESERVED_MASK 0xfffffffe
-#define RLC_SRM_GPM_ABORT__RESERVED__SHIFT 0x1
-#define RLC_CSIB_ADDR_LO__ADDRESS_MASK 0xffffffff
-#define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT 0x0
-#define RLC_CSIB_ADDR_HI__ADDRESS_MASK 0xffff
-#define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT 0x0
-#define RLC_CSIB_LENGTH__LENGTH_MASK 0xffffffff
-#define RLC_CSIB_LENGTH__LENGTH__SHIFT 0x0
-#define RLC_CP_RESPONSE0__RESPONSE_MASK 0xffffffff
-#define RLC_CP_RESPONSE0__RESPONSE__SHIFT 0x0
-#define RLC_CP_RESPONSE1__RESPONSE_MASK 0xffffffff
-#define RLC_CP_RESPONSE1__RESPONSE__SHIFT 0x0
-#define RLC_CP_RESPONSE2__RESPONSE_MASK 0xffffffff
-#define RLC_CP_RESPONSE2__RESPONSE__SHIFT 0x0
-#define RLC_CP_RESPONSE3__RESPONSE_MASK 0xffffffff
-#define RLC_CP_RESPONSE3__RESPONSE__SHIFT 0x0
-#define RLC_SMU_COMMAND__CMD_MASK 0xffffffff
-#define RLC_SMU_COMMAND__CMD__SHIFT 0x0
-#define RLC_CP_SCHEDULERS__scheduler0_MASK 0xff
-#define RLC_CP_SCHEDULERS__scheduler0__SHIFT 0x0
-#define RLC_CP_SCHEDULERS__scheduler1_MASK 0xff00
-#define RLC_CP_SCHEDULERS__scheduler1__SHIFT 0x8
-#define RLC_CP_SCHEDULERS__scheduler2_MASK 0xff0000
-#define RLC_CP_SCHEDULERS__scheduler2__SHIFT 0x10
-#define RLC_CP_SCHEDULERS__scheduler3_MASK 0xff000000
-#define RLC_CP_SCHEDULERS__scheduler3__SHIFT 0x18
-#define RLC_SMU_ARGUMENT_1__ARG_MASK 0xffffffff
-#define RLC_SMU_ARGUMENT_1__ARG__SHIFT 0x0
-#define RLC_SMU_ARGUMENT_2__ARG_MASK 0xffffffff
-#define RLC_SMU_ARGUMENT_2__ARG__SHIFT 0x0
-#define RLC_GPM_GENERAL_8__DATA_MASK 0xffffffff
-#define RLC_GPM_GENERAL_8__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_9__DATA_MASK 0xffffffff
-#define RLC_GPM_GENERAL_9__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_10__DATA_MASK 0xffffffff
-#define RLC_GPM_GENERAL_10__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_11__DATA_MASK 0xffffffff
-#define RLC_GPM_GENERAL_11__DATA__SHIFT 0x0
-#define RLC_GPM_GENERAL_12__DATA_MASK 0xffffffff
-#define RLC_GPM_GENERAL_12__DATA__SHIFT 0x0
-#define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0xfff
-#define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x0
-#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x3000
-#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc
-#define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0xc000
-#define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xe
-#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xffff0000
-#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10
-#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xffffffff
-#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0
-#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0xffff
-#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0
-#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xffff0000
-#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10
-#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xffffffff
-#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0xff
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK 0x700
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT 0x8
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0xf800
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0xb
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x1f0000
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x10
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x3e00000
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x15
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7c000000
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x1a
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK 0x80000000
-#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT 0x1f
-#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffff
-#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0
-#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffff
-#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0
-#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
-#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
-#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
-#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
-#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
-#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
-#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
-#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
-#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
-#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
-#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
-#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
-#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
-#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
-#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
-#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
-#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
-#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
-#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
-#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
-#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
-#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
-#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
-#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
-#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
-#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
-#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
-#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
-#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
-#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
-#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
-#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
-#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
-#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
-#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
-#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
-#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
-#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
-#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffff
-#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0
-#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffff
-#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0
-#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xffffffff
-#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0
-#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0xffffffff
-#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0
-#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK 0x1
-#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT 0x0
-#define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK 0xfffe
-#define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT 0x1
-#define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK 0xffff0000
-#define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT 0x10
-#define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK 0xffffffff
-#define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT 0x0
-#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0xf
-#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0
-#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK 0x7ffffff0
-#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4
-#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000
-#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f
-#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x3f
-#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x300
-#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x400
-#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x1e000
-#define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x20000
-#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x40000
-#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK 0x80000
-#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK 0x100000
-#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK 0x600000
-#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK 0x800000
-#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK 0x1000000
-#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK 0x2000000
-#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x3f
-#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x300
-#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x400
-#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x1e000
-#define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x20000
-#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x40000
-#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK 0x80000
-#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK 0x100000
-#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK 0x600000
-#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK 0x800000
-#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK 0x1000000
-#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK 0x2000000
-#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x3f
-#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x300
-#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x400
-#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x1e000
-#define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x20000
-#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x40000
-#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK 0x80000
-#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK 0x100000
-#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK 0x600000
-#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK 0x800000
-#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK 0x1000000
-#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK 0x2000000
-#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x3f
-#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x300
-#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x400
-#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x1e000
-#define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x20000
-#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x40000
-#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK 0x80000
-#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK 0x100000
-#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK 0x600000
-#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK 0x800000
-#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK 0x1000000
-#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK 0x2000000
-#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x3f
-#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x300
-#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x400
-#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x1e000
-#define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x20000
-#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x40000
-#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK 0x80000
-#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK 0x100000
-#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK 0x600000
-#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK 0x800000
-#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK 0x1000000
-#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK 0x2000000
-#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x3f
-#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x300
-#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x400
-#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x1e000
-#define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x20000
-#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x40000
-#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK 0x80000
-#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK 0x100000
-#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK 0x600000
-#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK 0x800000
-#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK 0x1000000
-#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK 0x2000000
-#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x3f
-#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x300
-#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x400
-#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x1e000
-#define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x20000
-#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x40000
-#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK 0x80000
-#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK 0x100000
-#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK 0x600000
-#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK 0x800000
-#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK 0x1000000
-#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK 0x2000000
-#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x3f
-#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x300
-#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x400
-#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x1e000
-#define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x20000
-#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x40000
-#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK 0x80000
-#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK 0x100000
-#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK 0x600000
-#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK 0x800000
-#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK 0x1000000
-#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK 0x2000000
-#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x3f
-#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x300
-#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x400
-#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x1e000
-#define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x20000
-#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x40000
-#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK 0x80000
-#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK 0x100000
-#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK 0x600000
-#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK 0x800000
-#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK 0x1000000
-#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK 0x2000000
-#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x3f
-#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x300
-#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x400
-#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x1e000
-#define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x20000
-#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x40000
-#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK 0x80000
-#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK 0x100000
-#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK 0x600000
-#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK 0x800000
-#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK 0x1000000
-#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK 0x2000000
-#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x3f
-#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x300
-#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x400
-#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x1e000
-#define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x20000
-#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x40000
-#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK 0x80000
-#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK 0x100000
-#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK 0x600000
-#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK 0x800000
-#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK 0x1000000
-#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK 0x2000000
-#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x3f
-#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x300
-#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x400
-#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x1e000
-#define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x20000
-#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x40000
-#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK 0x80000
-#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK 0x100000
-#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK 0x600000
-#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK 0x800000
-#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK 0x1000000
-#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK 0x2000000
-#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x3f
-#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x300
-#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x400
-#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x1e000
-#define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x20000
-#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x40000
-#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK 0x80000
-#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK 0x100000
-#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK 0x600000
-#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK 0x800000
-#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK 0x1000000
-#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK 0x2000000
-#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x3f
-#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x300
-#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x400
-#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x1e000
-#define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x20000
-#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x40000
-#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK 0x80000
-#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK 0x100000
-#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK 0x600000
-#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK 0x800000
-#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK 0x1000000
-#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK 0x2000000
-#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x3f
-#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x300
-#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x400
-#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x1e000
-#define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x20000
-#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x40000
-#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK 0x80000
-#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK 0x100000
-#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK 0x600000
-#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK 0x800000
-#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK 0x1000000
-#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK 0x2000000
-#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x3f
-#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x300
-#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x400
-#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x1e000
-#define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x20000
-#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x40000
-#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK 0x80000
-#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK 0x100000
-#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK 0x600000
-#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK 0x800000
-#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK 0x1000000
-#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK 0x2000000
-#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x3f
-#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x300
-#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x400
-#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x1e000
-#define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x20000
-#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x40000
-#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK 0x80000
-#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK 0x100000
-#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK 0x600000
-#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK 0x800000
-#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK 0x1000000
-#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK 0x2000000
-#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x3f
-#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x300
-#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x400
-#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x1e000
-#define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x20000
-#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x40000
-#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK 0x80000
-#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK 0x100000
-#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK 0x600000
-#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK 0x800000
-#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK 0x1000000
-#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK 0x2000000
-#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x3f
-#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x300
-#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x400
-#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x1e000
-#define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x20000
-#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x40000
-#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK 0x80000
-#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK 0x100000
-#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK 0x600000
-#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK 0x800000
-#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK 0x1000000
-#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK 0x2000000
-#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x3f
-#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x300
-#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x400
-#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x1e000
-#define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0xd
-#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x20000
-#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11
-#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x40000
-#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK 0x80000
-#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK 0x100000
-#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK 0x600000
-#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK 0x800000
-#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
-#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK 0x1000000
-#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK 0x2000000
-#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x3f
-#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x300
-#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x400
-#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x40000
-#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK 0x80000
-#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK 0x100000
-#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK 0x600000
-#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK 0x1000000
-#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK 0x2000000
-#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x3f
-#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x300
-#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x400
-#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x40000
-#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK 0x80000
-#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK 0x100000
-#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK 0x600000
-#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK 0x1000000
-#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK 0x2000000
-#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x3f
-#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x300
-#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x400
-#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x40000
-#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK 0x80000
-#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK 0x100000
-#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK 0x600000
-#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK 0x1000000
-#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK 0x2000000
-#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x3f
-#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x300
-#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x400
-#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x40000
-#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK 0x80000
-#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK 0x100000
-#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK 0x600000
-#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK 0x1000000
-#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK 0x2000000
-#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x3f
-#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x300
-#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x400
-#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x40000
-#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK 0x80000
-#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK 0x100000
-#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK 0x600000
-#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK 0x1000000
-#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK 0x2000000
-#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x3f
-#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x300
-#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x400
-#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x40000
-#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK 0x80000
-#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK 0x100000
-#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK 0x600000
-#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK 0x1000000
-#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK 0x2000000
-#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x3f
-#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x300
-#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x400
-#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x40000
-#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK 0x80000
-#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK 0x100000
-#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK 0x600000
-#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK 0x1000000
-#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK 0x2000000
-#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x3f
-#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x300
-#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x400
-#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x40000
-#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK 0x80000
-#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK 0x100000
-#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK 0x600000
-#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK 0x1000000
-#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK 0x2000000
-#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x3f
-#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x300
-#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x400
-#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x40000
-#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK 0x80000
-#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK 0x100000
-#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK 0x600000
-#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK 0x1000000
-#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK 0x2000000
-#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x3f
-#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x300
-#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x400
-#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x40000
-#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK 0x80000
-#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK 0x100000
-#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK 0x600000
-#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK 0x1000000
-#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK 0x2000000
-#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x3f
-#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x300
-#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x400
-#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x40000
-#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK 0x80000
-#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK 0x100000
-#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK 0x600000
-#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK 0x1000000
-#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK 0x2000000
-#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT 0x19
-#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x3f
-#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0
-#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x300
-#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8
-#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x400
-#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa
-#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x40000
-#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12
-#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK 0x80000
-#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT 0x13
-#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK 0x100000
-#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT 0x14
-#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK 0x600000
-#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT 0x15
-#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK 0x1000000
-#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT 0x18
-#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK 0x2000000
-#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT 0x19
-#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x3e
-#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1
-#define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x40
-#define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x6
-#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x1
-#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0
-#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x2
-#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1
-#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x4
-#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2
-#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x8
-#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3
-#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x10
-#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4
-#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x20
-#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5
-#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x40
-#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6
-#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x80
-#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7
-#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x100
-#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8
-#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x200
-#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9
-#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x400
-#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa
-#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x800
-#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb
-#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x1000
-#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc
-#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x2000
-#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd
-#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x4000
-#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe
-#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x8000
-#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf
-#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x1
-#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0
-#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x2
-#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1
-#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x4
-#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2
-#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x8
-#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3
-#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x10
-#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4
-#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x20
-#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5
-#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x40
-#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6
-#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x80
-#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7
-#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x100
-#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8
-#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x200
-#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9
-#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x400
-#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa
-#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x800
-#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb
-#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x1000
-#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc
-#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x2000
-#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd
-#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x4000
-#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe
-#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x8000
-#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf
-#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x1
-#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0
-#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x2
-#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1
-#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x1c
-#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2
-#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0xe0
-#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5
-#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x700
-#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8
-#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x3800
-#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb
-#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x4000
-#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe
-#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x3f
-#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0
-#define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x40
-#define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x6
-#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x4000
-#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe
-#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x1
-#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0
-#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x10
-#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4
-#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x100
-#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8
-#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x1000
-#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc
-#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x30000
-#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10
-#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x100000
-#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14
-#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x1000000
-#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18
-#define SPI_TMPRING_SIZE__WAVES_MASK 0xfff
-#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0
-#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x1fff000
-#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc
-#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0xf
-#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0
-#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0xf0
-#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4
-#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0xf00
-#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8
-#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0xf000
-#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc
-#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0xf
-#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0
-#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0xf
-#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0
-#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0xf0
-#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4
-#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0xf00
-#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8
-#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0xf000
-#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc
-#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0xf0000
-#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10
-#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0xf00000
-#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14
-#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0xf000000
-#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18
-#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xf0000000
-#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c
-#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x7
-#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0
-#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x38
-#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3
-#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x1c0
-#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6
-#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0xe00
-#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9
-#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x3000
-#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc
-#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0xc000
-#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe
-#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x30000
-#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10
-#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0xc0000
-#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12
-#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0xffff
-#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0
-#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xffff0000
-#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10
-#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0xffff
-#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0
-#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xffff0000
-#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10
-#define SPI_CDBG_SYS_GFX__PS_EN_MASK 0x1
-#define SPI_CDBG_SYS_GFX__PS_EN__SHIFT 0x0
-#define SPI_CDBG_SYS_GFX__VS_EN_MASK 0x2
-#define SPI_CDBG_SYS_GFX__VS_EN__SHIFT 0x1
-#define SPI_CDBG_SYS_GFX__GS_EN_MASK 0x4
-#define SPI_CDBG_SYS_GFX__GS_EN__SHIFT 0x2
-#define SPI_CDBG_SYS_GFX__ES_EN_MASK 0x8
-#define SPI_CDBG_SYS_GFX__ES_EN__SHIFT 0x3
-#define SPI_CDBG_SYS_GFX__HS_EN_MASK 0x10
-#define SPI_CDBG_SYS_GFX__HS_EN__SHIFT 0x4
-#define SPI_CDBG_SYS_GFX__LS_EN_MASK 0x20
-#define SPI_CDBG_SYS_GFX__LS_EN__SHIFT 0x5
-#define SPI_CDBG_SYS_GFX__CS_EN_MASK 0x40
-#define SPI_CDBG_SYS_GFX__CS_EN__SHIFT 0x6
-#define SPI_CDBG_SYS_HP3D__PS_EN_MASK 0x1
-#define SPI_CDBG_SYS_HP3D__PS_EN__SHIFT 0x0
-#define SPI_CDBG_SYS_HP3D__VS_EN_MASK 0x2
-#define SPI_CDBG_SYS_HP3D__VS_EN__SHIFT 0x1
-#define SPI_CDBG_SYS_HP3D__GS_EN_MASK 0x4
-#define SPI_CDBG_SYS_HP3D__GS_EN__SHIFT 0x2
-#define SPI_CDBG_SYS_HP3D__ES_EN_MASK 0x8
-#define SPI_CDBG_SYS_HP3D__ES_EN__SHIFT 0x3
-#define SPI_CDBG_SYS_HP3D__HS_EN_MASK 0x10
-#define SPI_CDBG_SYS_HP3D__HS_EN__SHIFT 0x4
-#define SPI_CDBG_SYS_HP3D__LS_EN_MASK 0x20
-#define SPI_CDBG_SYS_HP3D__LS_EN__SHIFT 0x5
-#define SPI_CDBG_SYS_CS0__PIPE0_MASK 0xff
-#define SPI_CDBG_SYS_CS0__PIPE0__SHIFT 0x0
-#define SPI_CDBG_SYS_CS0__PIPE1_MASK 0xff00
-#define SPI_CDBG_SYS_CS0__PIPE1__SHIFT 0x8
-#define SPI_CDBG_SYS_CS0__PIPE2_MASK 0xff0000
-#define SPI_CDBG_SYS_CS0__PIPE2__SHIFT 0x10
-#define SPI_CDBG_SYS_CS0__PIPE3_MASK 0xff000000
-#define SPI_CDBG_SYS_CS0__PIPE3__SHIFT 0x18
-#define SPI_CDBG_SYS_CS1__PIPE0_MASK 0xff
-#define SPI_CDBG_SYS_CS1__PIPE0__SHIFT 0x0
-#define SPI_CDBG_SYS_CS1__PIPE1_MASK 0xff00
-#define SPI_CDBG_SYS_CS1__PIPE1__SHIFT 0x8
-#define SPI_CDBG_SYS_CS1__PIPE2_MASK 0xff0000
-#define SPI_CDBG_SYS_CS1__PIPE2__SHIFT 0x10
-#define SPI_CDBG_SYS_CS1__PIPE3_MASK 0xff000000
-#define SPI_CDBG_SYS_CS1__PIPE3__SHIFT 0x18
-#define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x7f
-#define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0
-#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE_MASK 0xf80
-#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE__SHIFT 0x7
-#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK 0x1f000
-#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT 0xc
-#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE_MASK 0x3e0000
-#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE__SHIFT 0x11
-#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK 0x7c00000
-#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT 0x16
-#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x7f
-#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0
-#define SPI_WCL_PIPE_PERCENT_HP3D__LS_GRP_VALUE_MASK 0xf80
-#define SPI_WCL_PIPE_PERCENT_HP3D__LS_GRP_VALUE__SHIFT 0x7
-#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK 0x1f000
-#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT 0xc
-#define SPI_WCL_PIPE_PERCENT_HP3D__ES_GRP_VALUE_MASK 0x3e0000
-#define SPI_WCL_PIPE_PERCENT_HP3D__ES_GRP_VALUE__SHIFT 0x11
-#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK 0x7c00000
-#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT 0x16
-#define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x7f
-#define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0
-#define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x7f
-#define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0
-#define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x7f
-#define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0
-#define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x7f
-#define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0
-#define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x7f
-#define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0
-#define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x7f
-#define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0
-#define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x7f
-#define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0
-#define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x7f
-#define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0
-#define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x1
-#define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT 0x0
-#define SPI_GDBG_WAVE_CNTL__STALL_VMID_MASK 0x1fffe
-#define SPI_GDBG_WAVE_CNTL__STALL_VMID__SHIFT 0x1
-#define SPI_GDBG_TRAP_CONFIG__ME_SEL_MASK 0x3
-#define SPI_GDBG_TRAP_CONFIG__ME_SEL__SHIFT 0x0
-#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL_MASK 0xc
-#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL__SHIFT 0x2
-#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL_MASK 0x70
-#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL__SHIFT 0x4
-#define SPI_GDBG_TRAP_CONFIG__ME_MATCH_MASK 0x80
-#define SPI_GDBG_TRAP_CONFIG__ME_MATCH__SHIFT 0x7
-#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH_MASK 0x100
-#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH__SHIFT 0x8
-#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH_MASK 0x200
-#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH__SHIFT 0x9
-#define SPI_GDBG_TRAP_CONFIG__TRAP_EN_MASK 0x8000
-#define SPI_GDBG_TRAP_CONFIG__TRAP_EN__SHIFT 0xf
-#define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK 0xffff0000
-#define SPI_GDBG_TRAP_CONFIG__VMID_SEL__SHIFT 0x10
-#define SPI_GDBG_TRAP_MASK__EXCP_EN_MASK 0x1ff
-#define SPI_GDBG_TRAP_MASK__EXCP_EN__SHIFT 0x0
-#define SPI_GDBG_TRAP_MASK__REPLACE_MASK 0x200
-#define SPI_GDBG_TRAP_MASK__REPLACE__SHIFT 0x9
-#define SPI_GDBG_TBA_LO__MEM_BASE_MASK 0xffffffff
-#define SPI_GDBG_TBA_LO__MEM_BASE__SHIFT 0x0
-#define SPI_GDBG_TBA_HI__MEM_BASE_MASK 0xff
-#define SPI_GDBG_TBA_HI__MEM_BASE__SHIFT 0x0
-#define SPI_GDBG_TMA_LO__MEM_BASE_MASK 0xffffffff
-#define SPI_GDBG_TMA_LO__MEM_BASE__SHIFT 0x0
-#define SPI_GDBG_TMA_HI__MEM_BASE_MASK 0xff
-#define SPI_GDBG_TMA_HI__MEM_BASE__SHIFT 0x0
-#define SPI_GDBG_TRAP_DATA0__DATA_MASK 0xffffffff
-#define SPI_GDBG_TRAP_DATA0__DATA__SHIFT 0x0
-#define SPI_GDBG_TRAP_DATA1__DATA_MASK 0xffffffff
-#define SPI_GDBG_TRAP_DATA1__DATA__SHIFT 0x0
-#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_MASK 0x1
-#define SPI_RESET_DEBUG__DISABLE_GFX_RESET__SHIFT 0x0
-#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID_MASK 0x2
-#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID__SHIFT 0x1
-#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID_MASK 0x4
-#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID__SHIFT 0x2
-#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE_MASK 0x8
-#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE__SHIFT 0x3
-#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY_MASK 0x10
-#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY__SHIFT 0x4
-#define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x1
-#define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0xf
-#define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0xf0
-#define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0xf00
-#define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x7000
-#define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x78000
-#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0xf
-#define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0xf0
-#define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0xf00
-#define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x7000
-#define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x78000
-#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0xf
-#define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0xf0
-#define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0xf00
-#define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x7000
-#define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x78000
-#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0xf
-#define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0xf0
-#define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0xf00
-#define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x7000
-#define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x78000
-#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0xf
-#define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0xf0
-#define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0xf00
-#define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x7000
-#define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x78000
-#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0xf
-#define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0xf0
-#define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0xf00
-#define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x7000
-#define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x78000
-#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0xf
-#define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0xf0
-#define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0xf00
-#define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x7000
-#define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x78000
-#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0xf
-#define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0xf0
-#define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0xf00
-#define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x7000
-#define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x78000
-#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0xf
-#define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0xf0
-#define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0xf00
-#define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x7000
-#define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x78000
-#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0xf
-#define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0xf0
-#define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0xf00
-#define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x7000
-#define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x78000
-#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0xf
-#define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0xf0
-#define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0xf00
-#define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x7000
-#define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x78000
-#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0xf
-#define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0xf0
-#define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0xf00
-#define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x7000
-#define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x78000
-#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK 0xf
-#define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK 0xf0
-#define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK 0xf00
-#define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK 0x7000
-#define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK 0x78000
-#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK 0xf
-#define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK 0xf0
-#define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK 0xf00
-#define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK 0x7000
-#define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK 0x78000
-#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK 0xf
-#define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK 0xf0
-#define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK 0xf00
-#define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK 0x7000
-#define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK 0x78000
-#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK 0xf
-#define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK 0xf0
-#define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT 0x4
-#define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK 0xf00
-#define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT 0x8
-#define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK 0x7000
-#define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT 0xc
-#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK 0x78000
-#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT 0xf
-#define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0xfffe
-#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0xff0000
-#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK 0x1000000
-#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0xfffe
-#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0xff0000
-#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK 0x1000000
-#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0xfffe
-#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0xff0000
-#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK 0x1000000
-#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0xfffe
-#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0xff0000
-#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK 0x1000000
-#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0xfffe
-#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0xff0000
-#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK 0x1000000
-#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0xfffe
-#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0xff0000
-#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK 0x1000000
-#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0xfffe
-#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0xff0000
-#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK 0x1000000
-#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0xfffe
-#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0xff0000
-#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK 0x1000000
-#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0xfffe
-#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0xff0000
-#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK 0x1000000
-#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0xfffe
-#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0xff0000
-#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK 0x1000000
-#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0xfffe
-#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0xff0000
-#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK 0x1000000
-#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0xfffe
-#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0xff0000
-#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK 0x1000000
-#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK 0xfffe
-#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK 0xff0000
-#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY_MASK 0x1000000
-#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK 0xfffe
-#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK 0xff0000
-#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY_MASK 0x1000000
-#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK 0xfffe
-#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK 0xff0000
-#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY_MASK 0x1000000
-#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT 0x0
-#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK 0xfffe
-#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT 0x1
-#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK 0xff0000
-#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT 0x10
-#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY_MASK 0x1000000
-#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY__SHIFT 0x18
-#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK 0x1
-#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT 0x0
-#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK 0x2
-#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT 0x1
-#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK 0x4
-#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT 0x2
-#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK 0x40000000
-#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT 0x1e
-#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK 0x80000000
-#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT 0x1f
-#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff
-#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
-#define SPI_START_PHASE__VGPR_START_PHASE_MASK 0x3
-#define SPI_START_PHASE__VGPR_START_PHASE__SHIFT 0x0
-#define SPI_START_PHASE__SGPR_START_PHASE_MASK 0xc
-#define SPI_START_PHASE__SGPR_START_PHASE__SHIFT 0x2
-#define SPI_START_PHASE__WAVE_START_PHASE_MASK 0x30
-#define SPI_START_PHASE__WAVE_START_PHASE__SHIFT 0x4
-#define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x1
-#define SPI_GFX_CNTL__RESET_COUNTS__SHIFT 0x0
-#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x1fffff
-#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0
-#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0xe00000
-#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15
-#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x1000000
-#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18
-#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x2000000
-#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19
-#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x4000000
-#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x1a
-#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x8000000
-#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x1b
-#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE_MASK 0x1
-#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE__SHIFT 0x0
-#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL_MASK 0xe
-#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL__SHIFT 0x1
-#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL_MASK 0x3f0
-#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL__SHIFT 0x4
-#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL_MASK 0xfc00
-#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL__SHIFT 0xa
-#define SPI_DEBUG_CNTL__DEBUG_SH_SEL_MASK 0x10000
-#define SPI_DEBUG_CNTL__DEBUG_SH_SEL__SHIFT 0x10
-#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0_MASK 0x20000
-#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0__SHIFT 0x11
-#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1_MASK 0x40000
-#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1__SHIFT 0x12
-#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2_MASK 0x80000
-#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2__SHIFT 0x13
-#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3_MASK 0x100000
-#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3__SHIFT 0x14
-#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4_MASK 0x200000
-#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4__SHIFT 0x15
-#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5_MASK 0x400000
-#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5__SHIFT 0x16
-#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6_MASK 0x800000
-#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6__SHIFT 0x17
-#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7_MASK 0x1000000
-#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7__SHIFT 0x18
-#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL_MASK 0xe000000
-#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL__SHIFT 0x19
-#define SPI_DEBUG_CNTL__DEBUG_REG_EN_MASK 0x80000000
-#define SPI_DEBUG_CNTL__DEBUG_REG_EN__SHIFT 0x1f
-#define SPI_DEBUG_READ__DATA_MASK 0xffffff
-#define SPI_DEBUG_READ__DATA__SHIFT 0x0
-#define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data0_MASK 0x1
-#define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data0__SHIFT 0x0
-#define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data1_MASK 0x2
-#define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data1__SHIFT 0x1
-#define SPI_DSM_CNTL__SPI_Enable_Single_Write_MASK 0x4
-#define SPI_DSM_CNTL__SPI_Enable_Single_Write__SHIFT 0x2
-#define SPI_DSM_CNTL__UNUSED_MASK 0xfffffff8
-#define SPI_DSM_CNTL__UNUSED__SHIFT 0x3
-#define SPI_EDC_CNT__SED_MASK 0xff
-#define SPI_EDC_CNT__SED__SHIFT 0x0
-#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
-#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
-#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
-#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
-#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
-#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
-#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
-#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
-#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
-#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0xffc00
-#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
-#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
-#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
-#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
-#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0xffc00
-#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
-#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
-#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
-#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
-#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
-#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
-#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
-#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
-#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
-#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x3ff
-#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0
-#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0xffc00
-#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
-#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x3ff
-#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0
-#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0xffc00
-#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa
-#define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0xff
-#define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
-#define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0xff
-#define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
-#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0xf
-#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0
-#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0xf0
-#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4
-#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0xf00
-#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8
-#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0xf000
-#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc
-#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0xf0000
-#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10
-#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0xf00000
-#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14
-#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0xf000000
-#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18
-#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xf0000000
-#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c
-#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0xf
-#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0
-#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x10
-#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4
-#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x40
-#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x6
-#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x80
-#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7
-#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x100
-#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x8
-#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x200
-#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x9
-#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x3c00
-#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa
-#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK 0xffff0000
-#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT 0x10
-#define SPI_DEBUG_BUSY__LS_BUSY_MASK 0x1
-#define SPI_DEBUG_BUSY__LS_BUSY__SHIFT 0x0
-#define SPI_DEBUG_BUSY__HS_BUSY_MASK 0x2
-#define SPI_DEBUG_BUSY__HS_BUSY__SHIFT 0x1
-#define SPI_DEBUG_BUSY__ES_BUSY_MASK 0x4
-#define SPI_DEBUG_BUSY__ES_BUSY__SHIFT 0x2
-#define SPI_DEBUG_BUSY__GS_BUSY_MASK 0x8
-#define SPI_DEBUG_BUSY__GS_BUSY__SHIFT 0x3
-#define SPI_DEBUG_BUSY__VS_BUSY_MASK 0x10
-#define SPI_DEBUG_BUSY__VS_BUSY__SHIFT 0x4
-#define SPI_DEBUG_BUSY__PS0_BUSY_MASK 0x20
-#define SPI_DEBUG_BUSY__PS0_BUSY__SHIFT 0x5
-#define SPI_DEBUG_BUSY__PS1_BUSY_MASK 0x40
-#define SPI_DEBUG_BUSY__PS1_BUSY__SHIFT 0x6
-#define SPI_DEBUG_BUSY__CSG_BUSY_MASK 0x80
-#define SPI_DEBUG_BUSY__CSG_BUSY__SHIFT 0x7
-#define SPI_DEBUG_BUSY__CS0_BUSY_MASK 0x100
-#define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT 0x8
-#define SPI_DEBUG_BUSY__CS1_BUSY_MASK 0x200
-#define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT 0x9
-#define SPI_DEBUG_BUSY__CS2_BUSY_MASK 0x400
-#define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT 0xa
-#define SPI_DEBUG_BUSY__CS3_BUSY_MASK 0x800
-#define SPI_DEBUG_BUSY__CS3_BUSY__SHIFT 0xb
-#define SPI_DEBUG_BUSY__CS4_BUSY_MASK 0x1000
-#define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT 0xc
-#define SPI_DEBUG_BUSY__CS5_BUSY_MASK 0x2000
-#define SPI_DEBUG_BUSY__CS5_BUSY__SHIFT 0xd
-#define SPI_DEBUG_BUSY__CS6_BUSY_MASK 0x4000
-#define SPI_DEBUG_BUSY__CS6_BUSY__SHIFT 0xe
-#define SPI_DEBUG_BUSY__CS7_BUSY_MASK 0x8000
-#define SPI_DEBUG_BUSY__CS7_BUSY__SHIFT 0xf
-#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK 0x10000
-#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT 0x10
-#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK 0x20000
-#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT 0x11
-#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY_MASK 0x40000
-#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY__SHIFT 0x12
-#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY_MASK 0x80000
-#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY__SHIFT 0x13
-#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK 0x100000
-#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT 0x14
-#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK 0x200000
-#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT 0x15
-#define SPI_DEBUG_BUSY__GRBM_BUSY_MASK 0x400000
-#define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT 0x16
-#define SPI_DEBUG_BUSY__SPIS_BUSY_MASK 0x800000
-#define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT 0x17
-#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK 0xf
-#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT 0x0
-#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK 0xf0
-#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT 0x4
-#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0xf
-#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0
-#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0xff0
-#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4
-#define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x1000
-#define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0xc
-#define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x10000
-#define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x10
-#define CGTS_SM_CTRL_REG__SM_MODE_MASK 0xe0000
-#define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x11
-#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x100000
-#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14
-#define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x200000
-#define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x15
-#define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x400000
-#define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16
-#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x800000
-#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x17
-#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xff000000
-#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x18
-#define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x1f
-#define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x0
-#define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x1f00
-#define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x8
-#define CGTS_RD_REG__READ_DATA_MASK 0x3fff
-#define CGTS_RD_REG__READ_DATA__SHIFT 0x0
-#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000
-#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10
-#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000
-#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10
-#define CGTS_CU0_SP0_CTRL_REG__SP00_MASK 0x7f
-#define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
-#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU0_SP0_CTRL_REG__SP01_MASK 0x7f0000
-#define CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
-#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
-#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
-#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
-#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
-#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK 0x7f
-#define CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80
-#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000
-#define CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
-#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000
-#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
-#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU0_SP1_CTRL_REG__SP10_MASK 0x7f
-#define CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
-#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU0_SP1_CTRL_REG__SP11_MASK 0x7f0000
-#define CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
-#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU0_TD_TCP_CTRL_REG__TD_MASK 0x7f
-#define CGTS_CU0_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
-#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
-#define CGTS_CU0_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
-#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
-#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
-#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU1_SP0_CTRL_REG__SP00_MASK 0x7f
-#define CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
-#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU1_SP0_CTRL_REG__SP01_MASK 0x7f0000
-#define CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
-#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
-#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
-#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
-#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
-#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU1_TA_CTRL_REG__TA_MASK 0x7f
-#define CGTS_CU1_TA_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU1_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
-#define CGTS_CU1_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU1_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU1_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU1_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU1_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU1_SP1_CTRL_REG__SP10_MASK 0x7f
-#define CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
-#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU1_SP1_CTRL_REG__SP11_MASK 0x7f0000
-#define CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
-#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU1_TD_TCP_CTRL_REG__TD_MASK 0x7f
-#define CGTS_CU1_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
-#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
-#define CGTS_CU1_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
-#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
-#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
-#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU2_SP0_CTRL_REG__SP00_MASK 0x7f
-#define CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
-#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU2_SP0_CTRL_REG__SP01_MASK 0x7f0000
-#define CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
-#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
-#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
-#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
-#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
-#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU2_TA_CTRL_REG__TA_MASK 0x7f
-#define CGTS_CU2_TA_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU2_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
-#define CGTS_CU2_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU2_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU2_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU2_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU2_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU2_SP1_CTRL_REG__SP10_MASK 0x7f
-#define CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
-#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU2_SP1_CTRL_REG__SP11_MASK 0x7f0000
-#define CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
-#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU2_TD_TCP_CTRL_REG__TD_MASK 0x7f
-#define CGTS_CU2_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
-#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
-#define CGTS_CU2_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
-#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
-#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
-#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU3_SP0_CTRL_REG__SP00_MASK 0x7f
-#define CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
-#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU3_SP0_CTRL_REG__SP01_MASK 0x7f0000
-#define CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
-#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
-#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
-#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
-#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
-#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU3_TA_CTRL_REG__TA_MASK 0x7f
-#define CGTS_CU3_TA_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU3_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
-#define CGTS_CU3_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU3_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU3_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU3_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU3_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU3_SP1_CTRL_REG__SP10_MASK 0x7f
-#define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
-#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU3_SP1_CTRL_REG__SP11_MASK 0x7f0000
-#define CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
-#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU3_TD_TCP_CTRL_REG__TD_MASK 0x7f
-#define CGTS_CU3_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
-#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
-#define CGTS_CU3_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
-#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
-#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
-#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU4_SP0_CTRL_REG__SP00_MASK 0x7f
-#define CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
-#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU4_SP0_CTRL_REG__SP01_MASK 0x7f0000
-#define CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
-#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
-#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
-#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
-#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
-#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK 0x7f
-#define CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80
-#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000
-#define CGTS_CU4_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
-#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000
-#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
-#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU4_SP1_CTRL_REG__SP10_MASK 0x7f
-#define CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
-#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU4_SP1_CTRL_REG__SP11_MASK 0x7f0000
-#define CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
-#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU4_TD_TCP_CTRL_REG__TD_MASK 0x7f
-#define CGTS_CU4_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
-#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
-#define CGTS_CU4_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
-#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
-#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
-#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU5_SP0_CTRL_REG__SP00_MASK 0x7f
-#define CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
-#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x7f0000
-#define CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
-#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
-#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
-#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
-#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
-#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU5_TA_CTRL_REG__TA_MASK 0x7f
-#define CGTS_CU5_TA_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU5_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
-#define CGTS_CU5_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU5_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU5_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU5_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU5_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU5_SP1_CTRL_REG__SP10_MASK 0x7f
-#define CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
-#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU5_SP1_CTRL_REG__SP11_MASK 0x7f0000
-#define CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
-#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU5_TD_TCP_CTRL_REG__TD_MASK 0x7f
-#define CGTS_CU5_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
-#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
-#define CGTS_CU5_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
-#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
-#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
-#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU6_SP0_CTRL_REG__SP00_MASK 0x7f
-#define CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
-#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU6_SP0_CTRL_REG__SP01_MASK 0x7f0000
-#define CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
-#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
-#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
-#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
-#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
-#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU6_TA_CTRL_REG__TA_MASK 0x7f
-#define CGTS_CU6_TA_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU6_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
-#define CGTS_CU6_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU6_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU6_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU6_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU6_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU6_SP1_CTRL_REG__SP10_MASK 0x7f
-#define CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
-#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU6_SP1_CTRL_REG__SP11_MASK 0x7f0000
-#define CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
-#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU6_TD_TCP_CTRL_REG__TD_MASK 0x7f
-#define CGTS_CU6_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
-#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
-#define CGTS_CU6_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
-#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
-#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
-#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU7_SP0_CTRL_REG__SP00_MASK 0x7f
-#define CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
-#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU7_SP0_CTRL_REG__SP01_MASK 0x7f0000
-#define CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
-#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
-#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
-#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
-#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
-#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU7_TA_CTRL_REG__TA_MASK 0x7f
-#define CGTS_CU7_TA_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU7_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
-#define CGTS_CU7_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU7_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU7_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU7_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU7_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU7_SP1_CTRL_REG__SP10_MASK 0x7f
-#define CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
-#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU7_SP1_CTRL_REG__SP11_MASK 0x7f0000
-#define CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
-#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU7_TD_TCP_CTRL_REG__TD_MASK 0x7f
-#define CGTS_CU7_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
-#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
-#define CGTS_CU7_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
-#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
-#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
-#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU8_SP0_CTRL_REG__SP00_MASK 0x7f
-#define CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
-#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU8_SP0_CTRL_REG__SP01_MASK 0x7f0000
-#define CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
-#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
-#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
-#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
-#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
-#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK 0x7f
-#define CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80
-#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000
-#define CGTS_CU8_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
-#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000
-#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
-#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU8_SP1_CTRL_REG__SP10_MASK 0x7f
-#define CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
-#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU8_SP1_CTRL_REG__SP11_MASK 0x7f0000
-#define CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
-#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU8_TD_TCP_CTRL_REG__TD_MASK 0x7f
-#define CGTS_CU8_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
-#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
-#define CGTS_CU8_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
-#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
-#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
-#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU9_SP0_CTRL_REG__SP00_MASK 0x7f
-#define CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
-#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU9_SP0_CTRL_REG__SP01_MASK 0x7f0000
-#define CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
-#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
-#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
-#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
-#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
-#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU9_TA_CTRL_REG__TA_MASK 0x7f
-#define CGTS_CU9_TA_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU9_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
-#define CGTS_CU9_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU9_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU9_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU9_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU9_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU9_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU9_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU9_SP1_CTRL_REG__SP10_MASK 0x7f
-#define CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
-#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU9_SP1_CTRL_REG__SP11_MASK 0x7f0000
-#define CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
-#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU9_TD_TCP_CTRL_REG__TD_MASK 0x7f
-#define CGTS_CU9_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
-#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
-#define CGTS_CU9_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
-#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
-#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
-#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU10_SP0_CTRL_REG__SP00_MASK 0x7f
-#define CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
-#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU10_SP0_CTRL_REG__SP01_MASK 0x7f0000
-#define CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
-#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
-#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
-#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
-#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
-#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU10_TA_CTRL_REG__TA_MASK 0x7f
-#define CGTS_CU10_TA_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU10_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
-#define CGTS_CU10_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU10_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU10_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU10_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU10_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU10_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU10_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU10_SP1_CTRL_REG__SP10_MASK 0x7f
-#define CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
-#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU10_SP1_CTRL_REG__SP11_MASK 0x7f0000
-#define CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
-#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU10_TD_TCP_CTRL_REG__TD_MASK 0x7f
-#define CGTS_CU10_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
-#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
-#define CGTS_CU10_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
-#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
-#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
-#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU11_SP0_CTRL_REG__SP00_MASK 0x7f
-#define CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
-#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU11_SP0_CTRL_REG__SP01_MASK 0x7f0000
-#define CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
-#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
-#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
-#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
-#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
-#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU11_TA_CTRL_REG__TA_MASK 0x7f
-#define CGTS_CU11_TA_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU11_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
-#define CGTS_CU11_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU11_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU11_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU11_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU11_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU11_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU11_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU11_SP1_CTRL_REG__SP10_MASK 0x7f
-#define CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
-#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU11_SP1_CTRL_REG__SP11_MASK 0x7f0000
-#define CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
-#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU11_TD_TCP_CTRL_REG__TD_MASK 0x7f
-#define CGTS_CU11_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
-#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
-#define CGTS_CU11_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
-#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
-#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
-#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU12_SP0_CTRL_REG__SP00_MASK 0x7f
-#define CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
-#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU12_SP0_CTRL_REG__SP01_MASK 0x7f0000
-#define CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
-#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
-#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
-#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
-#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
-#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK 0x7f
-#define CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80
-#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000
-#define CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
-#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000
-#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
-#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU12_SP1_CTRL_REG__SP10_MASK 0x7f
-#define CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
-#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU12_SP1_CTRL_REG__SP11_MASK 0x7f0000
-#define CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
-#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU12_TD_TCP_CTRL_REG__TD_MASK 0x7f
-#define CGTS_CU12_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
-#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
-#define CGTS_CU12_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
-#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
-#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
-#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU13_SP0_CTRL_REG__SP00_MASK 0x7f
-#define CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
-#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU13_SP0_CTRL_REG__SP01_MASK 0x7f0000
-#define CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
-#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
-#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
-#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
-#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
-#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU13_TA_CTRL_REG__TA_MASK 0x7f
-#define CGTS_CU13_TA_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU13_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
-#define CGTS_CU13_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU13_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU13_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU13_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU13_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU13_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU13_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU13_SP1_CTRL_REG__SP10_MASK 0x7f
-#define CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
-#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU13_SP1_CTRL_REG__SP11_MASK 0x7f0000
-#define CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
-#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU13_TD_TCP_CTRL_REG__TD_MASK 0x7f
-#define CGTS_CU13_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
-#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
-#define CGTS_CU13_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
-#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
-#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
-#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU14_SP0_CTRL_REG__SP00_MASK 0x7f
-#define CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
-#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU14_SP0_CTRL_REG__SP01_MASK 0x7f0000
-#define CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
-#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
-#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
-#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
-#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
-#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU14_TA_CTRL_REG__TA_MASK 0x7f
-#define CGTS_CU14_TA_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU14_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
-#define CGTS_CU14_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU14_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU14_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU14_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU14_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU14_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU14_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU14_SP1_CTRL_REG__SP10_MASK 0x7f
-#define CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
-#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU14_SP1_CTRL_REG__SP11_MASK 0x7f0000
-#define CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
-#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU14_TD_TCP_CTRL_REG__TD_MASK 0x7f
-#define CGTS_CU14_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
-#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
-#define CGTS_CU14_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
-#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
-#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
-#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU15_SP0_CTRL_REG__SP00_MASK 0x7f
-#define CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT 0x0
-#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
-#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
-#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU15_SP0_CTRL_REG__SP01_MASK 0x7f0000
-#define CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT 0x10
-#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
-#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
-#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
-#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
-#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
-#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
-#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
-#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
-#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
-#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
-#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU15_TA_CTRL_REG__TA_MASK 0x7f
-#define CGTS_CU15_TA_CTRL_REG__TA__SHIFT 0x0
-#define CGTS_CU15_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
-#define CGTS_CU15_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
-#define CGTS_CU15_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU15_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU15_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU15_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU15_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU15_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU15_SP1_CTRL_REG__SP10_MASK 0x7f
-#define CGTS_CU15_SP1_CTRL_REG__SP10__SHIFT 0x0
-#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
-#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
-#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU15_SP1_CTRL_REG__SP11_MASK 0x7f0000
-#define CGTS_CU15_SP1_CTRL_REG__SP11__SHIFT 0x10
-#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
-#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
-#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTS_CU15_TD_TCP_CTRL_REG__TD_MASK 0x7f
-#define CGTS_CU15_TD_TCP_CTRL_REG__TD__SHIFT 0x0
-#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
-#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
-#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
-#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
-#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
-#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
-#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
-#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
-#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
-#define CGTS_CU15_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
-#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
-#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
-#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
-#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
-#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
-#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
-#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
-#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
-#define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0xf
-#define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
-#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0xfc0000
-#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12
-#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x1000000
-#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18
-#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x4000000
-#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x1a
-#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK 0x8000000
-#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b
-#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000
-#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c
-#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000
-#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d
-#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000
-#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e
-#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
-#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
-#define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0xf
-#define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
-#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0xfc0000
-#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12
-#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x1000000
-#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18
-#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE_MASK 0x2000000
-#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE__SHIFT 0x19
-#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE_MASK 0x4000000
-#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE__SHIFT 0x1a
-#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x8000000
-#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b
-#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000
-#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c
-#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000
-#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d
-#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000
-#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e
-#define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
-#define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
-#define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0xf
-#define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
-#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0xfff000
-#define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0xc
-#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x1000000
-#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x18
-#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x2000000
-#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x19
-#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x4000000
-#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x1a
-#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x8000000
-#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b
-#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000
-#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c
-#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000
-#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d
-#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000
-#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e
-#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
-#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
-#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0xf
-#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0
-#define SPI_WF_LIFETIME_CNTL__EN_MASK 0x10
-#define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4
-#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7fffffff
-#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000
-#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7fffffff
-#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000
-#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7fffffff
-#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000
-#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7fffffff
-#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000
-#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7fffffff
-#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000
-#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7fffffff
-#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000
-#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK 0x7fffffff
-#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK 0x80000000
-#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK 0x7fffffff
-#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK 0x80000000
-#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK 0x7fffffff
-#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK 0x80000000
-#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK 0x7fffffff
-#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK 0x80000000
-#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7fffffff
-#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000
-#define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7fffffff
-#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000
-#define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7fffffff
-#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000
-#define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK 0x7fffffff
-#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK 0x80000000
-#define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7fffffff
-#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000
-#define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK 0x7fffffff
-#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK 0x80000000
-#define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7fffffff
-#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000
-#define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7fffffff
-#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000
-#define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7fffffff
-#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000
-#define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7fffffff
-#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000
-#define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK 0x7fffffff
-#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK 0x80000000
-#define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7fffffff
-#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000
-#define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK 0x7fffffff
-#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK 0x80000000
-#define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7fffffff
-#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000
-#define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7fffffff
-#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000
-#define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7fffffff
-#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000
-#define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7fffffff
-#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000
-#define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7fffffff
-#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000
-#define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7fffffff
-#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000
-#define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7fffffff
-#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000
-#define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7fffffff
-#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0
-#define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000
-#define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f
-#define SPI_WF_LIFETIME_DEBUG__START_VALUE_MASK 0x7fffffff
-#define SPI_WF_LIFETIME_DEBUG__START_VALUE__SHIFT 0x0
-#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN_MASK 0x80000000
-#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN__SHIFT 0x1f
-#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY_MASK 0x1
-#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY__SHIFT 0x0
-#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY_MASK 0x2
-#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY__SHIFT 0x1
-#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY_MASK 0x4
-#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY__SHIFT 0x2
-#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY_MASK 0x8
-#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY__SHIFT 0x3
-#define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY_MASK 0x10
-#define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY__SHIFT 0x4
-#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY_MASK 0x20
-#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY__SHIFT 0x5
-#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY_MASK 0x40
-#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY__SHIFT 0x6
-#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY_MASK 0x80
-#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY__SHIFT 0x7
-#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY_MASK 0x100
-#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY__SHIFT 0x8
-#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY_MASK 0x200
-#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY__SHIFT 0x9
-#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY_MASK 0x400
-#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY__SHIFT 0xa
-#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY_MASK 0x800
-#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY__SHIFT 0xb
-#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY_MASK 0x1000
-#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY__SHIFT 0xc
-#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY_MASK 0x2000
-#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY__SHIFT 0xd
-#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY_MASK 0x4000
-#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY__SHIFT 0xe
-#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY_MASK 0x8000
-#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY__SHIFT 0xf
-#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY_MASK 0x10000
-#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY__SHIFT 0x10
-#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY_MASK 0x20000
-#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY__SHIFT 0x11
-#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY_MASK 0x40000
-#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY__SHIFT 0x12
-#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY_MASK 0x80000
-#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY__SHIFT 0x13
-#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY_MASK 0x100000
-#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY__SHIFT 0x14
-#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY_MASK 0x200000
-#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY__SHIFT 0x15
-#define SPI_SLAVE_DEBUG_BUSY__SAVE_CTX_BUSY_MASK 0x400000
-#define SPI_SLAVE_DEBUG_BUSY__SAVE_CTX_BUSY__SHIFT 0x16
-#define SPI_LB_CTR_CTRL__LOAD_MASK 0x1
-#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0
-#define SPI_LB_CU_MASK__CU_MASK_MASK 0xffff
-#define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x0
-#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xffffffff
-#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0
-#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0xffff
-#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x0
-#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0xff
-#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0
-#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0xff00
-#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8
-#define SPI_GDS_CREDITS__UNUSED_MASK 0xffff0000
-#define SPI_GDS_CREDITS__UNUSED__SHIFT 0x10
-#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0xffff
-#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0
-#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xffff0000
-#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10
-#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0xffff
-#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0
-#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xffff0000
-#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10
-#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xffffffff
-#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0
-#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x7ff
-#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0
-#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x7ff
-#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0
-#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x7ff
-#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0
-#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x7ff
-#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0
-#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x7ff
-#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0
-#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x7ff
-#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0
-#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x7ff
-#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0
-#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x7ff
-#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0
-#define BCI_DEBUG_READ__DATA_MASK 0xffffff
-#define BCI_DEBUG_READ__DATA__SHIFT 0x0
-#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xffffffff
-#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0
-#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xff
-#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0
-#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xffffffff
-#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0
-#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xff
-#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0
-#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x3f
-#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
-#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x3c0
-#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6
-#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xffffffff
-#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0
-#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xff
-#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0
-#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xffffffff
-#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0
-#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xff
-#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0
-#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x3f
-#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
-#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x3c0
-#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6
-#define SPI_SHADER_TBA_LO_PS__MEM_BASE_MASK 0xffffffff
-#define SPI_SHADER_TBA_LO_PS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_TBA_HI_PS__MEM_BASE_MASK 0xff
-#define SPI_SHADER_TBA_HI_PS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_TMA_LO_PS__MEM_BASE_MASK 0xffffffff
-#define SPI_SHADER_TMA_LO_PS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_TMA_HI_PS__MEM_BASE_MASK 0xff
-#define SPI_SHADER_TMA_HI_PS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xffffffff
-#define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0xff
-#define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x3f
-#define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x3c0
-#define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0xc00
-#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa
-#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0xff000
-#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0xc
-#define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x100000
-#define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14
-#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x200000
-#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x15
-#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE_MASK 0x400000
-#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE__SHIFT 0x16
-#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x800000
-#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x17
-#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x1000000
-#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x18
-#define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL_MASK 0xe000000
-#define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL__SHIFT 0x19
-#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER_MASK 0x10000000
-#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER__SHIFT 0x1c
-#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x1
-#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x3e
-#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x1
-#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x40
-#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x80
-#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x7
-#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0xff00
-#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x8
-#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x1ff0000
-#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x10
-#define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0xffff
-#define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK 0x3f0000
-#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT 0x10
-#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK 0x3c00000
-#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT 0x16
-#define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x0
-#define SPI_SHADER_TBA_LO_VS__MEM_BASE_MASK 0xffffffff
-#define SPI_SHADER_TBA_LO_VS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_TBA_HI_VS__MEM_BASE_MASK 0xff
-#define SPI_SHADER_TBA_HI_VS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_TMA_LO_VS__MEM_BASE_MASK 0xffffffff
-#define SPI_SHADER_TMA_LO_VS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_TMA_HI_VS__MEM_BASE_MASK 0xff
-#define SPI_SHADER_TMA_HI_VS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xffffffff
-#define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0xff
-#define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x3f
-#define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x3c0
-#define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0xc00
-#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0xa
-#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0xff000
-#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0xc
-#define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x100000
-#define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x14
-#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x200000
-#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x15
-#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE_MASK 0x400000
-#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE__SHIFT 0x16
-#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x800000
-#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x17
-#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x3000000
-#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x18
-#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x4000000
-#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x1a
-#define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL_MASK 0x38000000
-#define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL__SHIFT 0x1b
-#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER_MASK 0x40000000
-#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER__SHIFT 0x1e
-#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x1
-#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x3e
-#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x1
-#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x40
-#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x80
-#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x7
-#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x100
-#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x8
-#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x200
-#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x9
-#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x400
-#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0xa
-#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x800
-#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0xb
-#define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x1000
-#define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0xc
-#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x3fe000
-#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0xd
-#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN_MASK 0x1000000
-#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN__SHIFT 0x18
-#define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK 0xffff
-#define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK 0x3f0000
-#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT 0x10
-#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK 0x3c00000
-#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT 0x16
-#define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK 0x3f
-#define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN_MASK 0x1
-#define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR_MASK 0x3e
-#define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR__SHIFT 0x1
-#define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT_MASK 0x40
-#define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN_MASK 0x80
-#define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN__SHIFT 0x7
-#define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN_MASK 0x1ff00
-#define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN__SHIFT 0x8
-#define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE_MASK 0x1ff00000
-#define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE__SHIFT 0x14
-#define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN_MASK 0x1
-#define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR_MASK 0x3e
-#define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR__SHIFT 0x1
-#define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT_MASK 0x40
-#define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE_MASK 0xff80
-#define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE__SHIFT 0x7
-#define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN_MASK 0x1ff0000
-#define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN__SHIFT 0x10
-#define SPI_SHADER_TBA_LO_GS__MEM_BASE_MASK 0xffffffff
-#define SPI_SHADER_TBA_LO_GS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_TBA_HI_GS__MEM_BASE_MASK 0xff
-#define SPI_SHADER_TBA_HI_GS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_TMA_LO_GS__MEM_BASE_MASK 0xffffffff
-#define SPI_SHADER_TMA_LO_GS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_TMA_HI_GS__MEM_BASE_MASK 0xff
-#define SPI_SHADER_TMA_HI_GS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xffffffff
-#define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0xff
-#define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x3f
-#define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x3c0
-#define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0xc00
-#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa
-#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0xff000
-#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0xc
-#define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x100000
-#define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14
-#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x200000
-#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x15
-#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE_MASK 0x400000
-#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE__SHIFT 0x16
-#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x800000
-#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x17
-#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x1000000
-#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x18
-#define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL_MASK 0xe000000
-#define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL__SHIFT 0x19
-#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER_MASK 0x10000000
-#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER__SHIFT 0x1c
-#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x1
-#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x3e
-#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x1
-#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x40
-#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0xff80
-#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x7
-#define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0xffff
-#define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK 0x3f0000
-#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT 0x10
-#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK 0x3c00000
-#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT 0x16
-#define SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH_MASK 0xfc000000
-#define SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH__SHIFT 0x1a
-#define SPI_SHADER_USER_DATA_GS_0__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_GS_0__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_GS_1__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_GS_1__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_GS_2__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_GS_2__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_GS_3__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_GS_3__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_GS_4__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_GS_4__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_GS_5__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_GS_5__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_GS_6__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_GS_6__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_GS_7__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_GS_7__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_GS_8__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_GS_8__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_GS_9__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_GS_9__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_GS_10__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_GS_10__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_GS_11__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_GS_11__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_GS_12__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_GS_12__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_GS_13__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_GS_13__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_GS_14__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_GS_14__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_GS_15__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_GS_15__DATA__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN_MASK 0x1
-#define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR_MASK 0x3e
-#define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR__SHIFT 0x1
-#define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT_MASK 0x40
-#define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN_MASK 0x80
-#define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN__SHIFT 0x7
-#define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN_MASK 0x1ff00
-#define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN__SHIFT 0x8
-#define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE_MASK 0x1ff00000
-#define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE__SHIFT 0x14
-#define SPI_SHADER_TBA_LO_ES__MEM_BASE_MASK 0xffffffff
-#define SPI_SHADER_TBA_LO_ES__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_TBA_HI_ES__MEM_BASE_MASK 0xff
-#define SPI_SHADER_TBA_HI_ES__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_TMA_LO_ES__MEM_BASE_MASK 0xffffffff
-#define SPI_SHADER_TMA_LO_ES__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_TMA_HI_ES__MEM_BASE_MASK 0xff
-#define SPI_SHADER_TMA_HI_ES__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xffffffff
-#define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0xff
-#define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC1_ES__VGPRS_MASK 0x3f
-#define SPI_SHADER_PGM_RSRC1_ES__VGPRS__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC1_ES__SGPRS_MASK 0x3c0
-#define SPI_SHADER_PGM_RSRC1_ES__SGPRS__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC1_ES__PRIORITY_MASK 0xc00
-#define SPI_SHADER_PGM_RSRC1_ES__PRIORITY__SHIFT 0xa
-#define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE_MASK 0xff000
-#define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE__SHIFT 0xc
-#define SPI_SHADER_PGM_RSRC1_ES__PRIV_MASK 0x100000
-#define SPI_SHADER_PGM_RSRC1_ES__PRIV__SHIFT 0x14
-#define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP_MASK 0x200000
-#define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP__SHIFT 0x15
-#define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE_MASK 0x400000
-#define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE__SHIFT 0x16
-#define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE_MASK 0x800000
-#define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE__SHIFT 0x17
-#define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT_MASK 0x3000000
-#define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT__SHIFT 0x18
-#define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE_MASK 0x4000000
-#define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE__SHIFT 0x1a
-#define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL_MASK 0x38000000
-#define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL__SHIFT 0x1b
-#define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER_MASK 0x40000000
-#define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER__SHIFT 0x1e
-#define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN_MASK 0x1
-#define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR_MASK 0x3e
-#define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR__SHIFT 0x1
-#define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT_MASK 0x40
-#define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN_MASK 0x80
-#define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN__SHIFT 0x7
-#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN_MASK 0x1ff00
-#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN__SHIFT 0x8
-#define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE_MASK 0x1ff00000
-#define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE__SHIFT 0x14
-#define SPI_SHADER_PGM_RSRC3_ES__CU_EN_MASK 0xffff
-#define SPI_SHADER_PGM_RSRC3_ES__CU_EN__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT_MASK 0x3f0000
-#define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT__SHIFT 0x10
-#define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD_MASK 0x3c00000
-#define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD__SHIFT 0x16
-#define SPI_SHADER_PGM_RSRC3_ES__GROUP_FIFO_DEPTH_MASK 0xfc000000
-#define SPI_SHADER_PGM_RSRC3_ES__GROUP_FIFO_DEPTH__SHIFT 0x1a
-#define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN_MASK 0x1
-#define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR_MASK 0x3e
-#define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR__SHIFT 0x1
-#define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT_MASK 0x40
-#define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE_MASK 0xff80
-#define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE__SHIFT 0x7
-#define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN_MASK 0x1ff0000
-#define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN__SHIFT 0x10
-#define SPI_SHADER_TBA_LO_HS__MEM_BASE_MASK 0xffffffff
-#define SPI_SHADER_TBA_LO_HS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_TBA_HI_HS__MEM_BASE_MASK 0xff
-#define SPI_SHADER_TBA_HI_HS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_TMA_LO_HS__MEM_BASE_MASK 0xffffffff
-#define SPI_SHADER_TMA_LO_HS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_TMA_HI_HS__MEM_BASE_MASK 0xff
-#define SPI_SHADER_TMA_HI_HS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xffffffff
-#define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0xff
-#define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x3f
-#define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x3c0
-#define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0xc00
-#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa
-#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0xff000
-#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0xc
-#define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x100000
-#define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14
-#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x200000
-#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x15
-#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE_MASK 0x400000
-#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE__SHIFT 0x16
-#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x800000
-#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x17
-#define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL_MASK 0x7000000
-#define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL__SHIFT 0x18
-#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER_MASK 0x8000000
-#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER__SHIFT 0x1b
-#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x1
-#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x3e
-#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x1
-#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x40
-#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN_MASK 0x80
-#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN__SHIFT 0x7
-#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN_MASK 0x100
-#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN__SHIFT 0x8
-#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x3fe00
-#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x9
-#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK 0x3f
-#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK 0x3c0
-#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH_MASK 0xfc00
-#define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH__SHIFT 0xa
-#define SPI_SHADER_USER_DATA_HS_0__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_HS_0__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_HS_1__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_HS_1__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_HS_2__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_HS_2__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_HS_3__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_HS_3__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_HS_4__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_HS_4__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_HS_5__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_HS_5__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_HS_6__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_HS_6__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_HS_7__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_HS_7__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_HS_8__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_HS_8__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_HS_9__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_HS_9__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_HS_10__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_HS_10__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_HS_11__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_HS_11__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_HS_12__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_HS_12__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_HS_13__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_HS_13__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_HS_14__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_HS_14__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_HS_15__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_HS_15__DATA__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN_MASK 0x1
-#define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR_MASK 0x3e
-#define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR__SHIFT 0x1
-#define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT_MASK 0x40
-#define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE_MASK 0xff80
-#define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE__SHIFT 0x7
-#define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN_MASK 0x1ff0000
-#define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN__SHIFT 0x10
-#define SPI_SHADER_TBA_LO_LS__MEM_BASE_MASK 0xffffffff
-#define SPI_SHADER_TBA_LO_LS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_TBA_HI_LS__MEM_BASE_MASK 0xff
-#define SPI_SHADER_TBA_HI_LS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_TMA_LO_LS__MEM_BASE_MASK 0xffffffff
-#define SPI_SHADER_TMA_LO_LS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_TMA_HI_LS__MEM_BASE_MASK 0xff
-#define SPI_SHADER_TMA_HI_LS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xffffffff
-#define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0xff
-#define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC1_LS__VGPRS_MASK 0x3f
-#define SPI_SHADER_PGM_RSRC1_LS__VGPRS__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC1_LS__SGPRS_MASK 0x3c0
-#define SPI_SHADER_PGM_RSRC1_LS__SGPRS__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC1_LS__PRIORITY_MASK 0xc00
-#define SPI_SHADER_PGM_RSRC1_LS__PRIORITY__SHIFT 0xa
-#define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE_MASK 0xff000
-#define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE__SHIFT 0xc
-#define SPI_SHADER_PGM_RSRC1_LS__PRIV_MASK 0x100000
-#define SPI_SHADER_PGM_RSRC1_LS__PRIV__SHIFT 0x14
-#define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP_MASK 0x200000
-#define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP__SHIFT 0x15
-#define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE_MASK 0x400000
-#define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE__SHIFT 0x16
-#define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE_MASK 0x800000
-#define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE__SHIFT 0x17
-#define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT_MASK 0x3000000
-#define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT__SHIFT 0x18
-#define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL_MASK 0x1c000000
-#define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL__SHIFT 0x1a
-#define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER_MASK 0x20000000
-#define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER__SHIFT 0x1d
-#define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN_MASK 0x1
-#define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR_MASK 0x3e
-#define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR__SHIFT 0x1
-#define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT_MASK 0x40
-#define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT__SHIFT 0x6
-#define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE_MASK 0xff80
-#define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE__SHIFT 0x7
-#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN_MASK 0x1ff0000
-#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN__SHIFT 0x10
-#define SPI_SHADER_PGM_RSRC3_LS__CU_EN_MASK 0xffff
-#define SPI_SHADER_PGM_RSRC3_LS__CU_EN__SHIFT 0x0
-#define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT_MASK 0x3f0000
-#define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT__SHIFT 0x10
-#define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD_MASK 0x3c00000
-#define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD__SHIFT 0x16
-#define SPI_SHADER_PGM_RSRC3_LS__GROUP_FIFO_DEPTH_MASK 0xfc000000
-#define SPI_SHADER_PGM_RSRC3_LS__GROUP_FIFO_DEPTH__SHIFT 0x1a
-#define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x0
-#define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xffffffff
-#define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x0
-#define SQ_CONFIG__UNUSED_MASK 0xff
-#define SQ_CONFIG__UNUSED__SHIFT 0x0
-#define SQ_CONFIG__DEBUG_EN_MASK 0x100
-#define SQ_CONFIG__DEBUG_EN__SHIFT 0x8
-#define SQ_CONFIG__DEBUG_SINGLE_MEMOP_MASK 0x200
-#define SQ_CONFIG__DEBUG_SINGLE_MEMOP__SHIFT 0x9
-#define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE_MASK 0x400
-#define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE__SHIFT 0xa
-#define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x1000
-#define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0xc
-#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x2000
-#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0xd
-#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x4000
-#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0xe
-#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x8000
-#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0xf
-#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE_MASK 0x10000
-#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE__SHIFT 0x10
-#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE_MASK 0x20000
-#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE__SHIFT 0x11
-#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK 0x40000
-#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT 0x12
-#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK 0x180000
-#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT 0x13
-#define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK 0x1e00000
-#define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT 0x15
-#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x3
-#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0
-#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0xc
-#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2
-#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x30
-#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4
-#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x40
-#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6
-#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x80
-#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7
-#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x100
-#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8
-#define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x200
-#define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x9
-#define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x400
-#define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0xa
-#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x800
-#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb
-#define SQC_CONFIG__EVICT_LRU_MASK 0x3000
-#define SQC_CONFIG__EVICT_LRU__SHIFT 0xc
-#define SQC_CONFIG__FORCE_2_BANK_MASK 0x4000
-#define SQC_CONFIG__FORCE_2_BANK__SHIFT 0xe
-#define SQC_CONFIG__FORCE_1_BANK_MASK 0x8000
-#define SQC_CONFIG__FORCE_1_BANK__SHIFT 0xf
-#define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0xff0000
-#define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0x10
-#define SQC_CACHES__TARGET_INST_MASK 0x1
-#define SQC_CACHES__TARGET_INST__SHIFT 0x0
-#define SQC_CACHES__TARGET_DATA_MASK 0x2
-#define SQC_CACHES__TARGET_DATA__SHIFT 0x1
-#define SQC_CACHES__INVALIDATE_MASK 0x4
-#define SQC_CACHES__INVALIDATE__SHIFT 0x2
-#define SQC_CACHES__WRITEBACK_MASK 0x8
-#define SQC_CACHES__WRITEBACK__SHIFT 0x3
-#define SQC_CACHES__VOL_MASK 0x10
-#define SQC_CACHES__VOL__SHIFT 0x4
-#define SQC_CACHES__COMPLETE_MASK 0x10000
-#define SQC_CACHES__COMPLETE__SHIFT 0x10
-#define SQC_WRITEBACK__DWB_MASK 0x1
-#define SQC_WRITEBACK__DWB__SHIFT 0x0
-#define SQC_WRITEBACK__DIRTY_MASK 0x2
-#define SQC_WRITEBACK__DIRTY__SHIFT 0x1
-#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKA_MASK 0x3
-#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKA__SHIFT 0x0
-#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKA_MASK 0x4
-#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKA__SHIFT 0x2
-#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKB_MASK 0x18
-#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKB__SHIFT 0x3
-#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKB_MASK 0x20
-#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKB__SHIFT 0x5
-#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKC_MASK 0xc0
-#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKC__SHIFT 0x6
-#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKC_MASK 0x100
-#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKC__SHIFT 0x8
-#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKD_MASK 0x600
-#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKD__SHIFT 0x9
-#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKD_MASK 0x800
-#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKD__SHIFT 0xb
-#define SQC_DSM_CNTL__SEL_DATA_ICACHE_GATCL1_MASK 0x3000
-#define SQC_DSM_CNTL__SEL_DATA_ICACHE_GATCL1__SHIFT 0xc
-#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_GATCL1_MASK 0x4000
-#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_GATCL1__SHIFT 0xe
-#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKA_MASK 0x18000
-#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKA__SHIFT 0xf
-#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKA_MASK 0x20000
-#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKA__SHIFT 0x11
-#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKB_MASK 0xc0000
-#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKB__SHIFT 0x12
-#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKB_MASK 0x100000
-#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKB__SHIFT 0x14
-#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKC_MASK 0x600000
-#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKC__SHIFT 0x15
-#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKC_MASK 0x800000
-#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKC__SHIFT 0x17
-#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKD_MASK 0x3000000
-#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKD__SHIFT 0x18
-#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKD_MASK 0x4000000
-#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKD__SHIFT 0x1a
-#define SQC_DSM_CNTL__SEL_DATA_DCACHE_GATCL1_MASK 0x18000000
-#define SQC_DSM_CNTL__SEL_DATA_DCACHE_GATCL1__SHIFT 0x1b
-#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_GATCL1_MASK 0x20000000
-#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_GATCL1__SHIFT 0x1d
-#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x7f
-#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0
-#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x380
-#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7
-#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x1ffc00
-#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa
-#define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x3f
-#define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x0
-#define SQ_REG_CREDITS__CMD_CREDITS_MASK 0xf00
-#define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x8
-#define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000
-#define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x1c
-#define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000
-#define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x1d
-#define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000
-#define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x1e
-#define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000
-#define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x1f
-#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0xf
-#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0
-#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0xf00
-#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8
-#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x30000
-#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x10
-#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0xc0000
-#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12
-#define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x1
-#define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x0
-#define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x2
-#define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x1
-#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x4
-#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2
-#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x8
-#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x3
-#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x100
-#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x8
-#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x200
-#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x9
-#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x400
-#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa
-#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x10000
-#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x10
-#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x20000
-#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x11
-#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x40000
-#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x12
-#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x80000
-#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x13
-#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x100000
-#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14
-#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x200000
-#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x15
-#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x1000000
-#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x18
-#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x2000000
-#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x19
-#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x4000000
-#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x1a
-#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x6
-#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1
-#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x8
-#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3
-#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x10
-#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4
-#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x6
-#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1
-#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x8
-#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3
-#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x10
-#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4
-#define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0xffffff
-#define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0
-#define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x1
-#define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0
-#define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x1
-#define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0
-#define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x2
-#define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x1
-#define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x4
-#define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2
-#define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x8
-#define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x3
-#define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x10
-#define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4
-#define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x20
-#define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x5
-#define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x40
-#define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6
-#define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x1f00
-#define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x8
-#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x2000
-#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0xd
-#define SQ_PERFCOUNTER_MASK__SH0_MASK_MASK 0xffff
-#define SQ_PERFCOUNTER_MASK__SH0_MASK__SHIFT 0x0
-#define SQ_PERFCOUNTER_MASK__SH1_MASK_MASK 0xffff0000
-#define SQ_PERFCOUNTER_MASK__SH1_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x1
-#define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0
-#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0xf0000
-#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x10
-#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0xf00000
-#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x14
-#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0xf000000
-#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x18
-#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000
-#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x1c
-#define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0xf0000
-#define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x10
-#define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0xf00000
-#define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x14
-#define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0xf000000
-#define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x18
-#define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000
-#define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x1c
-#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x1ff
-#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK 0xf000
-#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
-#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0xf00000
-#define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK 0xf000000
-#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
-#define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x1ff
-#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK 0xf000
-#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
-#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0xf00000
-#define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK 0xf000000
-#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
-#define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x1ff
-#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK 0xf000
-#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
-#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0xf00000
-#define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK 0xf000000
-#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
-#define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x1ff
-#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK 0xf000
-#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
-#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0xf00000
-#define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK 0xf000000
-#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
-#define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x1ff
-#define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK 0xf000
-#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
-#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0xf00000
-#define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK 0xf000000
-#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xf0000000
-#define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x1ff
-#define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK 0xf000
-#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
-#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0xf00000
-#define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK 0xf000000
-#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xf0000000
-#define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x1ff
-#define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK 0xf000
-#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
-#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0xf00000
-#define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK 0xf000000
-#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xf0000000
-#define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x1ff
-#define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK 0xf000
-#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
-#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0xf00000
-#define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK 0xf000000
-#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xf0000000
-#define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0x1ff
-#define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK 0xf000
-#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
-#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0xf00000
-#define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK 0xf000000
-#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xf0000000
-#define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0x1ff
-#define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK 0xf000
-#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
-#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0xf00000
-#define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK 0xf000000
-#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xf0000000
-#define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0x1ff
-#define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK 0xf000
-#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
-#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0xf00000
-#define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK 0xf000000
-#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xf0000000
-#define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0x1ff
-#define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK 0xf000
-#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
-#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0xf00000
-#define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK 0xf000000
-#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xf0000000
-#define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0x1ff
-#define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK 0xf000
-#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
-#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0xf00000
-#define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK 0xf000000
-#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xf0000000
-#define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0x1ff
-#define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK 0xf000
-#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
-#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0xf00000
-#define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK 0xf000000
-#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xf0000000
-#define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0x1ff
-#define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK 0xf000
-#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
-#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0xf00000
-#define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK 0xf000000
-#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xf0000000
-#define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x1c
-#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0x1ff
-#define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x0
-#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK 0xf000
-#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT 0xc
-#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
-#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
-#define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0xf00000
-#define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14
-#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK 0xf000000
-#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT 0x18
-#define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xf0000000
-#define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x1c
-#define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0xf
-#define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
-#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000
-#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d
-#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000
-#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
-#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
-#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
-#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0xf
-#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
-#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK 0x10000000
-#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT 0x1c
-#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000
-#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d
-#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000
-#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
-#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
-#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
-#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff
-#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
-#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000
-#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
-#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff
-#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
-#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000
-#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
-#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff
-#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
-#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000
-#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
-#define SQ_POWER_THROTTLE__MIN_POWER_MASK 0x3fff
-#define SQ_POWER_THROTTLE__MIN_POWER__SHIFT 0x0
-#define SQ_POWER_THROTTLE__MAX_POWER_MASK 0x3fff0000
-#define SQ_POWER_THROTTLE__MAX_POWER__SHIFT 0x10
-#define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK 0xc0000000
-#define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT 0x1e
-#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK 0x3fff
-#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT 0x0
-#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
-#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
-#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
-#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
-#define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK 0x80000000
-#define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT 0x1f
-#define SQ_TIME_HI__TIME_MASK 0xffffffff
-#define SQ_TIME_HI__TIME__SHIFT 0x0
-#define SQ_TIME_LO__TIME_MASK 0xffffffff
-#define SQ_TIME_LO__TIME__SHIFT 0x0
-#define SQ_THREAD_TRACE_BASE__ADDR_MASK 0xffffffff
-#define SQ_THREAD_TRACE_BASE__ADDR__SHIFT 0x0
-#define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK 0xf
-#define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT 0x0
-#define SQ_THREAD_TRACE_SIZE__SIZE_MASK 0x3fffff
-#define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT 0x0
-#define SQ_THREAD_TRACE_MASK__CU_SEL_MASK 0x1f
-#define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT 0x0
-#define SQ_THREAD_TRACE_MASK__SH_SEL_MASK 0x20
-#define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT 0x5
-#define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK 0x80
-#define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT 0x7
-#define SQ_THREAD_TRACE_MASK__SIMD_EN_MASK 0xf00
-#define SQ_THREAD_TRACE_MASK__SIMD_EN__SHIFT 0x8
-#define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK 0x3000
-#define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT 0xc
-#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK 0x4000
-#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT 0xe
-#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK 0x8000
-#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT 0xf
-#define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xffffffff
-#define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x0
-#define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xffffffff
-#define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x0
-#define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xffffffff
-#define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x0
-#define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xffffffff
-#define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x0
-#define SQ_THREAD_TRACE_MODE__MASK_PS_MASK 0x7
-#define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT 0x0
-#define SQ_THREAD_TRACE_MODE__MASK_VS_MASK 0x38
-#define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT 0x3
-#define SQ_THREAD_TRACE_MODE__MASK_GS_MASK 0x1c0
-#define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT 0x6
-#define SQ_THREAD_TRACE_MODE__MASK_ES_MASK 0xe00
-#define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT 0x9
-#define SQ_THREAD_TRACE_MODE__MASK_HS_MASK 0x7000
-#define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT 0xc
-#define SQ_THREAD_TRACE_MODE__MASK_LS_MASK 0x38000
-#define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT 0xf
-#define SQ_THREAD_TRACE_MODE__MASK_CS_MASK 0x1c0000
-#define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT 0x12
-#define SQ_THREAD_TRACE_MODE__MODE_MASK 0x600000
-#define SQ_THREAD_TRACE_MODE__MODE__SHIFT 0x15
-#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK 0x1800000
-#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT 0x17
-#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK 0x2000000
-#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT 0x19
-#define SQ_THREAD_TRACE_MODE__PRIV_MASK 0x4000000
-#define SQ_THREAD_TRACE_MODE__PRIV__SHIFT 0x1a
-#define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK 0x18000000
-#define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT 0x1b
-#define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK 0x20000000
-#define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x1d
-#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK 0x40000000
-#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT 0x1e
-#define SQ_THREAD_TRACE_MODE__WRAP_MASK 0x80000000
-#define SQ_THREAD_TRACE_MODE__WRAP__SHIFT 0x1f
-#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK 0x80000000
-#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT 0x1f
-#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK 0xffff
-#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT 0x0
-#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK 0xff0000
-#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT 0x10
-#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK 0x1000000
-#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT 0x18
-#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK 0xffffffff
-#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT 0x0
-#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK 0xffff
-#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT 0x0
-#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK 0xffff0000
-#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT 0x10
-#define SQ_THREAD_TRACE_WPTR__WPTR_MASK 0x3fffffff
-#define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT 0x0
-#define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK 0xc0000000
-#define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT 0x1e
-#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x3ff
-#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0
-#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x3ff0000
-#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0x10
-#define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK 0x20000000
-#define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x1d
-#define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x40000000
-#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x1e
-#define SQ_THREAD_TRACE_STATUS__FULL_MASK 0x80000000
-#define SQ_THREAD_TRACE_STATUS__FULL__SHIFT 0x1f
-#define SQ_THREAD_TRACE_CNTR__CNTR_MASK 0xffffffff
-#define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT 0x0
-#define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK 0x7
-#define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT 0x0
-#define SQ_LB_CTR_CTRL__START_MASK 0x1
-#define SQ_LB_CTR_CTRL__START__SHIFT 0x0
-#define SQ_LB_CTR_CTRL__LOAD_MASK 0x2
-#define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1
-#define SQ_LB_CTR_CTRL__CLEAR_MASK 0x4
-#define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2
-#define SQ_LB_DATA_ALU_CYCLES__DATA_MASK 0xffffffff
-#define SQ_LB_DATA_ALU_CYCLES__DATA__SHIFT 0x0
-#define SQ_LB_DATA_TEX_CYCLES__DATA_MASK 0xffffffff
-#define SQ_LB_DATA_TEX_CYCLES__DATA__SHIFT 0x0
-#define SQ_LB_DATA_ALU_STALLS__DATA_MASK 0xffffffff
-#define SQ_LB_DATA_ALU_STALLS__DATA__SHIFT 0x0
-#define SQ_LB_DATA_TEX_STALLS__DATA_MASK 0xffffffff
-#define SQ_LB_DATA_TEX_STALLS__DATA__SHIFT 0x0
-#define SQC_EDC_CNT__INST_SEC_MASK 0xff
-#define SQC_EDC_CNT__INST_SEC__SHIFT 0x0
-#define SQC_EDC_CNT__INST_DED_MASK 0xff00
-#define SQC_EDC_CNT__INST_DED__SHIFT 0x8
-#define SQC_EDC_CNT__DATA_SEC_MASK 0xff0000
-#define SQC_EDC_CNT__DATA_SEC__SHIFT 0x10
-#define SQC_EDC_CNT__DATA_DED_MASK 0xff000000
-#define SQC_EDC_CNT__DATA_DED__SHIFT 0x18
-#define SQ_EDC_SEC_CNT__LDS_SEC_MASK 0xff
-#define SQ_EDC_SEC_CNT__LDS_SEC__SHIFT 0x0
-#define SQ_EDC_SEC_CNT__SGPR_SEC_MASK 0xff00
-#define SQ_EDC_SEC_CNT__SGPR_SEC__SHIFT 0x8
-#define SQ_EDC_SEC_CNT__VGPR_SEC_MASK 0xff0000
-#define SQ_EDC_SEC_CNT__VGPR_SEC__SHIFT 0x10
-#define SQ_EDC_DED_CNT__LDS_DED_MASK 0xff
-#define SQ_EDC_DED_CNT__LDS_DED__SHIFT 0x0
-#define SQ_EDC_DED_CNT__SGPR_DED_MASK 0xff00
-#define SQ_EDC_DED_CNT__SGPR_DED__SHIFT 0x8
-#define SQ_EDC_DED_CNT__VGPR_DED_MASK 0xff0000
-#define SQ_EDC_DED_CNT__VGPR_DED__SHIFT 0x10
-#define SQ_EDC_INFO__WAVE_ID_MASK 0xf
-#define SQ_EDC_INFO__WAVE_ID__SHIFT 0x0
-#define SQ_EDC_INFO__SIMD_ID_MASK 0x30
-#define SQ_EDC_INFO__SIMD_ID__SHIFT 0x4
-#define SQ_EDC_INFO__SOURCE_MASK 0x1c0
-#define SQ_EDC_INFO__SOURCE__SHIFT 0x6
-#define SQ_EDC_INFO__VM_ID_MASK 0x1e00
-#define SQ_EDC_INFO__VM_ID__SHIFT 0x9
-#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffff
-#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0
-#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0xffff
-#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0
-#define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3fff0000
-#define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x10
-#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000
-#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x1e
-#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000
-#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x1f
-#define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xffffffff
-#define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x0
-#define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x7
-#define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x0
-#define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x38
-#define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3
-#define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x1c0
-#define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6
-#define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0xe00
-#define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x9
-#define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x7000
-#define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0xc
-#define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x78000
-#define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0xf
-#define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE_MASK 0x180000
-#define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE__SHIFT 0x13
-#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x600000
-#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x15
-#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x800000
-#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x17
-#define SQ_BUF_RSRC_WORD3__ATC_MASK 0x1000000
-#define SQ_BUF_RSRC_WORD3__ATC__SHIFT 0x18
-#define SQ_BUF_RSRC_WORD3__HASH_ENABLE_MASK 0x2000000
-#define SQ_BUF_RSRC_WORD3__HASH_ENABLE__SHIFT 0x19
-#define SQ_BUF_RSRC_WORD3__HEAP_MASK 0x4000000
-#define SQ_BUF_RSRC_WORD3__HEAP__SHIFT 0x1a
-#define SQ_BUF_RSRC_WORD3__MTYPE_MASK 0x38000000
-#define SQ_BUF_RSRC_WORD3__MTYPE__SHIFT 0x1b
-#define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xc0000000
-#define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x1e
-#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffff
-#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0
-#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0xff
-#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0
-#define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0xfff00
-#define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x8
-#define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x3f00000
-#define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x14
-#define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3c000000
-#define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x1a
-#define SQ_IMG_RSRC_WORD1__MTYPE_MASK 0xc0000000
-#define SQ_IMG_RSRC_WORD1__MTYPE__SHIFT 0x1e
-#define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x3fff
-#define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x0
-#define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0xfffc000
-#define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0xe
-#define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000
-#define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x1c
-#define SQ_IMG_RSRC_WORD2__INTERLACED_MASK 0x80000000
-#define SQ_IMG_RSRC_WORD2__INTERLACED__SHIFT 0x1f
-#define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x7
-#define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x0
-#define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x38
-#define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3
-#define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x1c0
-#define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6
-#define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0xe00
-#define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x9
-#define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0xf000
-#define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0xc
-#define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0xf0000
-#define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x10
-#define SQ_IMG_RSRC_WORD3__TILING_INDEX_MASK 0x1f00000
-#define SQ_IMG_RSRC_WORD3__TILING_INDEX__SHIFT 0x14
-#define SQ_IMG_RSRC_WORD3__POW2_PAD_MASK 0x2000000
-#define SQ_IMG_RSRC_WORD3__POW2_PAD__SHIFT 0x19
-#define SQ_IMG_RSRC_WORD3__MTYPE_MASK 0x4000000
-#define SQ_IMG_RSRC_WORD3__MTYPE__SHIFT 0x1a
-#define SQ_IMG_RSRC_WORD3__ATC_MASK 0x8000000
-#define SQ_IMG_RSRC_WORD3__ATC__SHIFT 0x1b
-#define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xf0000000
-#define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x1c
-#define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x1fff
-#define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x0
-#define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x7ffe000
-#define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0xd
-#define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x1fff
-#define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x0
-#define SQ_IMG_RSRC_WORD5__LAST_ARRAY_MASK 0x3ffe000
-#define SQ_IMG_RSRC_WORD5__LAST_ARRAY__SHIFT 0xd
-#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0xfff
-#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x0
-#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0xff000
-#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0xc
-#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x100000
-#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x14
-#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN_MASK 0x200000
-#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN__SHIFT 0x15
-#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB_MASK 0x400000
-#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB__SHIFT 0x16
-#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM_MASK 0x800000
-#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM__SHIFT 0x17
-#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS_MASK 0xf000000
-#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS__SHIFT 0x18
-#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS_MASK 0xf0000000
-#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS__SHIFT 0x1c
-#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS_MASK 0xffffffff
-#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS__SHIFT 0x0
-#define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x7
-#define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x0
-#define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x38
-#define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x3
-#define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x1c0
-#define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x6
-#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0xe00
-#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x9
-#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x7000
-#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0xc
-#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x8000
-#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0xf
-#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x70000
-#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x10
-#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x80000
-#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x13
-#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x100000
-#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x14
-#define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x7e00000
-#define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x15
-#define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x8000000
-#define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x1b
-#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000
-#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x1c
-#define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000
-#define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x1d
-#define SQ_IMG_SAMP_WORD0__COMPAT_MODE_MASK 0x80000000
-#define SQ_IMG_SAMP_WORD0__COMPAT_MODE__SHIFT 0x1f
-#define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0xfff
-#define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x0
-#define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0xfff000
-#define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0xc
-#define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0xf000000
-#define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x18
-#define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xf0000000
-#define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x1c
-#define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x3fff
-#define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x0
-#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0xfc000
-#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0xe
-#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x300000
-#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x14
-#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0xc00000
-#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x16
-#define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x3000000
-#define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x18
-#define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0xc000000
-#define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x1a
-#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000
-#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x1c
-#define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL_MASK 0x20000000
-#define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL__SHIFT 0x1d
-#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000
-#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x1e
-#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE_MASK 0x80000000
-#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE__SHIFT 0x1f
-#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0xfff
-#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x0
-#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xc0000000
-#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x1e
-#define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK 0x7ffff
-#define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT 0x0
-#define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK 0xffffff
-#define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT 0x0
-#define SQ_M0_GPR_IDX_WORD__INDEX_MASK 0xff
-#define SQ_M0_GPR_IDX_WORD__INDEX__SHIFT 0x0
-#define SQ_M0_GPR_IDX_WORD__VSRC0_REL_MASK 0x1000
-#define SQ_M0_GPR_IDX_WORD__VSRC0_REL__SHIFT 0xc
-#define SQ_M0_GPR_IDX_WORD__VSRC1_REL_MASK 0x2000
-#define SQ_M0_GPR_IDX_WORD__VSRC1_REL__SHIFT 0xd
-#define SQ_M0_GPR_IDX_WORD__VSRC2_REL_MASK 0x4000
-#define SQ_M0_GPR_IDX_WORD__VSRC2_REL__SHIFT 0xe
-#define SQ_M0_GPR_IDX_WORD__VDST_REL_MASK 0x8000
-#define SQ_M0_GPR_IDX_WORD__VDST_REL__SHIFT 0xf
-#define SQ_IND_INDEX__WAVE_ID_MASK 0xf
-#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0
-#define SQ_IND_INDEX__SIMD_ID_MASK 0x30
-#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4
-#define SQ_IND_INDEX__THREAD_ID_MASK 0xfc0
-#define SQ_IND_INDEX__THREAD_ID__SHIFT 0x6
-#define SQ_IND_INDEX__AUTO_INCR_MASK 0x1000
-#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xc
-#define SQ_IND_INDEX__FORCE_READ_MASK 0x2000
-#define SQ_IND_INDEX__FORCE_READ__SHIFT 0xd
-#define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x4000
-#define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0xe
-#define SQ_IND_INDEX__UNINDEXED_MASK 0x8000
-#define SQ_IND_INDEX__UNINDEXED__SHIFT 0xf
-#define SQ_IND_INDEX__INDEX_MASK 0xffff0000
-#define SQ_IND_INDEX__INDEX__SHIFT 0x10
-#define SQ_CMD__CMD_MASK 0x7
-#define SQ_CMD__CMD__SHIFT 0x0
-#define SQ_CMD__MODE_MASK 0x70
-#define SQ_CMD__MODE__SHIFT 0x4
-#define SQ_CMD__CHECK_VMID_MASK 0x80
-#define SQ_CMD__CHECK_VMID__SHIFT 0x7
-#define SQ_CMD__DATA_MASK 0x700
-#define SQ_CMD__DATA__SHIFT 0x8
-#define SQ_CMD__WAVE_ID_MASK 0xf0000
-#define SQ_CMD__WAVE_ID__SHIFT 0x10
-#define SQ_CMD__SIMD_ID_MASK 0x300000
-#define SQ_CMD__SIMD_ID__SHIFT 0x14
-#define SQ_CMD__QUEUE_ID_MASK 0x7000000
-#define SQ_CMD__QUEUE_ID__SHIFT 0x18
-#define SQ_CMD__VM_ID_MASK 0xf0000000
-#define SQ_CMD__VM_ID__SHIFT 0x1c
-#define SQ_IND_DATA__DATA_MASK 0xffffffff
-#define SQ_IND_DATA__DATA__SHIFT 0x0
-#define SQ_REG_TIMESTAMP__TIMESTAMP_MASK 0xff
-#define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT 0x0
-#define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0xff
-#define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0
-#define SQ_HV_VMID_CTRL__DEFAULT_VMID_MASK 0xf
-#define SQ_HV_VMID_CTRL__DEFAULT_VMID__SHIFT 0x0
-#define SQ_HV_VMID_CTRL__ALLOWED_VMID_MASK_MASK 0xffff0
-#define SQ_HV_VMID_CTRL__ALLOWED_VMID_MASK__SHIFT 0x4
-#define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xffffffff
-#define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x0
-#define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xffffffff
-#define SQ_WAVE_INST_DW1__INST_DW1__SHIFT 0x0
-#define SQ_WAVE_PC_LO__PC_LO_MASK 0xffffffff
-#define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x0
-#define SQ_WAVE_PC_HI__PC_HI_MASK 0xffff
-#define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x0
-#define SQ_WAVE_IB_DBG0__IBUF_ST_MASK 0x7
-#define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x0
-#define SQ_WAVE_IB_DBG0__PC_INVALID_MASK 0x8
-#define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT 0x3
-#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK 0x10
-#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT 0x4
-#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK 0xe0
-#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT 0x5
-#define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK 0x300
-#define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT 0x8
-#define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK 0xc00
-#define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0xa
-#define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK 0xf0000
-#define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT 0x10
-#define SQ_WAVE_IB_DBG0__MISC_CNT_MASK 0xf00000
-#define SQ_WAVE_IB_DBG0__MISC_CNT__SHIFT 0x14
-#define SQ_WAVE_IB_DBG0__ECC_ST_MASK 0x3000000
-#define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT 0x18
-#define SQ_WAVE_IB_DBG0__IS_HYB_MASK 0x4000000
-#define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT 0x1a
-#define SQ_WAVE_IB_DBG0__HYB_CNT_MASK 0x18000000
-#define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT 0x1b
-#define SQ_WAVE_IB_DBG0__KILL_MASK 0x20000000
-#define SQ_WAVE_IB_DBG0__KILL__SHIFT 0x1d
-#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK 0x40000000
-#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT 0x1e
-#define SQ_WAVE_IB_DBG1__IXNACK_MASK 0x1
-#define SQ_WAVE_IB_DBG1__IXNACK__SHIFT 0x0
-#define SQ_WAVE_IB_DBG1__XNACK_MASK 0x2
-#define SQ_WAVE_IB_DBG1__XNACK__SHIFT 0x1
-#define SQ_WAVE_IB_DBG1__TA_NEED_RESET_MASK 0x4
-#define SQ_WAVE_IB_DBG1__TA_NEED_RESET__SHIFT 0x2
-#define SQ_WAVE_IB_DBG1__XCNT_MASK 0xf0
-#define SQ_WAVE_IB_DBG1__XCNT__SHIFT 0x4
-#define SQ_WAVE_IB_DBG1__QCNT_MASK 0xf00
-#define SQ_WAVE_IB_DBG1__QCNT__SHIFT 0x8
-#define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xffffffff
-#define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x0
-#define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xffffffff
-#define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x0
-#define SQ_WAVE_STATUS__SCC_MASK 0x1
-#define SQ_WAVE_STATUS__SCC__SHIFT 0x0
-#define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x6
-#define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x1
-#define SQ_WAVE_STATUS__USER_PRIO_MASK 0x18
-#define SQ_WAVE_STATUS__USER_PRIO__SHIFT 0x3
-#define SQ_WAVE_STATUS__PRIV_MASK 0x20
-#define SQ_WAVE_STATUS__PRIV__SHIFT 0x5
-#define SQ_WAVE_STATUS__TRAP_EN_MASK 0x40
-#define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x6
-#define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x80
-#define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x7
-#define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x100
-#define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x8
-#define SQ_WAVE_STATUS__EXECZ_MASK 0x200
-#define SQ_WAVE_STATUS__EXECZ__SHIFT 0x9
-#define SQ_WAVE_STATUS__VCCZ_MASK 0x400
-#define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa
-#define SQ_WAVE_STATUS__IN_TG_MASK 0x800
-#define SQ_WAVE_STATUS__IN_TG__SHIFT 0xb
-#define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x1000
-#define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0xc
-#define SQ_WAVE_STATUS__HALT_MASK 0x2000
-#define SQ_WAVE_STATUS__HALT__SHIFT 0xd
-#define SQ_WAVE_STATUS__TRAP_MASK 0x4000
-#define SQ_WAVE_STATUS__TRAP__SHIFT 0xe
-#define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK 0x8000
-#define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT 0xf
-#define SQ_WAVE_STATUS__VALID_MASK 0x10000
-#define SQ_WAVE_STATUS__VALID__SHIFT 0x10
-#define SQ_WAVE_STATUS__ECC_ERR_MASK 0x20000
-#define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x11
-#define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x40000
-#define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x12
-#define SQ_WAVE_STATUS__PERF_EN_MASK 0x80000
-#define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x13
-#define SQ_WAVE_STATUS__COND_DBG_USER_MASK 0x100000
-#define SQ_WAVE_STATUS__COND_DBG_USER__SHIFT 0x14
-#define SQ_WAVE_STATUS__COND_DBG_SYS_MASK 0x200000
-#define SQ_WAVE_STATUS__COND_DBG_SYS__SHIFT 0x15
-#define SQ_WAVE_STATUS__ALLOW_REPLAY_MASK 0x400000
-#define SQ_WAVE_STATUS__ALLOW_REPLAY__SHIFT 0x16
-#define SQ_WAVE_STATUS__INST_ATC_MASK 0x800000
-#define SQ_WAVE_STATUS__INST_ATC__SHIFT 0x17
-#define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x8000000
-#define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x1b
-#define SQ_WAVE_MODE__FP_ROUND_MASK 0xf
-#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0
-#define SQ_WAVE_MODE__FP_DENORM_MASK 0xf0
-#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4
-#define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x100
-#define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x8
-#define SQ_WAVE_MODE__IEEE_MASK 0x200
-#define SQ_WAVE_MODE__IEEE__SHIFT 0x9
-#define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x400
-#define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa
-#define SQ_WAVE_MODE__DEBUG_EN_MASK 0x800
-#define SQ_WAVE_MODE__DEBUG_EN__SHIFT 0xb
-#define SQ_WAVE_MODE__EXCP_EN_MASK 0x1ff000
-#define SQ_WAVE_MODE__EXCP_EN__SHIFT 0xc
-#define SQ_WAVE_MODE__GPR_IDX_EN_MASK 0x8000000
-#define SQ_WAVE_MODE__GPR_IDX_EN__SHIFT 0x1b
-#define SQ_WAVE_MODE__VSKIP_MASK 0x10000000
-#define SQ_WAVE_MODE__VSKIP__SHIFT 0x1c
-#define SQ_WAVE_MODE__CSP_MASK 0xe0000000
-#define SQ_WAVE_MODE__CSP__SHIFT 0x1d
-#define SQ_WAVE_TRAPSTS__EXCP_MASK 0x1ff
-#define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x0
-#define SQ_WAVE_TRAPSTS__SAVECTX_MASK 0x400
-#define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT 0xa
-#define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x3f0000
-#define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x10
-#define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xe0000000
-#define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x1d
-#define SQ_WAVE_HW_ID__WAVE_ID_MASK 0xf
-#define SQ_WAVE_HW_ID__WAVE_ID__SHIFT 0x0
-#define SQ_WAVE_HW_ID__SIMD_ID_MASK 0x30
-#define SQ_WAVE_HW_ID__SIMD_ID__SHIFT 0x4
-#define SQ_WAVE_HW_ID__PIPE_ID_MASK 0xc0
-#define SQ_WAVE_HW_ID__PIPE_ID__SHIFT 0x6
-#define SQ_WAVE_HW_ID__CU_ID_MASK 0xf00
-#define SQ_WAVE_HW_ID__CU_ID__SHIFT 0x8
-#define SQ_WAVE_HW_ID__SH_ID_MASK 0x1000
-#define SQ_WAVE_HW_ID__SH_ID__SHIFT 0xc
-#define SQ_WAVE_HW_ID__SE_ID_MASK 0x6000
-#define SQ_WAVE_HW_ID__SE_ID__SHIFT 0xd
-#define SQ_WAVE_HW_ID__TG_ID_MASK 0xf0000
-#define SQ_WAVE_HW_ID__TG_ID__SHIFT 0x10
-#define SQ_WAVE_HW_ID__VM_ID_MASK 0xf00000
-#define SQ_WAVE_HW_ID__VM_ID__SHIFT 0x14
-#define SQ_WAVE_HW_ID__QUEUE_ID_MASK 0x7000000
-#define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT 0x18
-#define SQ_WAVE_HW_ID__STATE_ID_MASK 0x38000000
-#define SQ_WAVE_HW_ID__STATE_ID__SHIFT 0x1b
-#define SQ_WAVE_HW_ID__ME_ID_MASK 0xc0000000
-#define SQ_WAVE_HW_ID__ME_ID__SHIFT 0x1e
-#define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x3f
-#define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x0
-#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x3f00
-#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x8
-#define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x3f0000
-#define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x10
-#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0xf000000
-#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x18
-#define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0xff
-#define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x0
-#define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x1ff000
-#define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0xc
-#define SQ_WAVE_IB_STS__VM_CNT_MASK 0xf
-#define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x0
-#define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x70
-#define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x4
-#define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0xf00
-#define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x8
-#define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x7000
-#define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0xc
-#define SQ_WAVE_IB_STS__FIRST_REPLAY_MASK 0x8000
-#define SQ_WAVE_IB_STS__FIRST_REPLAY__SHIFT 0xf
-#define SQ_WAVE_IB_STS__RCNT_MASK 0xf0000
-#define SQ_WAVE_IB_STS__RCNT__SHIFT 0x10
-#define SQ_WAVE_M0__M0_MASK 0xffffffff
-#define SQ_WAVE_M0__M0__SHIFT 0x0
-#define SQ_WAVE_TBA_LO__ADDR_LO_MASK 0xffffffff
-#define SQ_WAVE_TBA_LO__ADDR_LO__SHIFT 0x0
-#define SQ_WAVE_TBA_HI__ADDR_HI_MASK 0xff
-#define SQ_WAVE_TBA_HI__ADDR_HI__SHIFT 0x0
-#define SQ_WAVE_TMA_LO__ADDR_LO_MASK 0xffffffff
-#define SQ_WAVE_TMA_LO__ADDR_LO__SHIFT 0x0
-#define SQ_WAVE_TMA_HI__ADDR_HI_MASK 0xff
-#define SQ_WAVE_TMA_HI__ADDR_HI__SHIFT 0x0
-#define SQ_WAVE_TTMP0__DATA_MASK 0xffffffff
-#define SQ_WAVE_TTMP0__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP1__DATA_MASK 0xffffffff
-#define SQ_WAVE_TTMP1__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP2__DATA_MASK 0xffffffff
-#define SQ_WAVE_TTMP2__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP3__DATA_MASK 0xffffffff
-#define SQ_WAVE_TTMP3__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP4__DATA_MASK 0xffffffff
-#define SQ_WAVE_TTMP4__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP5__DATA_MASK 0xffffffff
-#define SQ_WAVE_TTMP5__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP6__DATA_MASK 0xffffffff
-#define SQ_WAVE_TTMP6__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP7__DATA_MASK 0xffffffff
-#define SQ_WAVE_TTMP7__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP8__DATA_MASK 0xffffffff
-#define SQ_WAVE_TTMP8__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP9__DATA_MASK 0xffffffff
-#define SQ_WAVE_TTMP9__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP10__DATA_MASK 0xffffffff
-#define SQ_WAVE_TTMP10__DATA__SHIFT 0x0
-#define SQ_WAVE_TTMP11__DATA_MASK 0xffffffff
-#define SQ_WAVE_TTMP11__DATA__SHIFT 0x0
-#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x1
-#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x0
-#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x2
-#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x1
-#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK 0xfff0
-#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT 0x4
-#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK 0xfff0000
-#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT 0x10
-#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0xff
-#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x0
-#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0xff00
-#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x8
-#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK 0xff0000
-#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT 0x10
-#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK 0xff000000
-#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT 0x18
-#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK 0xf
-#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT 0x0
-#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK 0x3f0
-#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT 0x4
-#define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x1
-#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x0
-#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x3f0
-#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x4
-#define SQ_DEBUG_CTRL_LOCAL__UNUSED_MASK 0xff
-#define SQ_DEBUG_CTRL_LOCAL__UNUSED__SHIFT 0x0
-#define SH_MEM_BASES__PRIVATE_BASE_MASK 0xffff
-#define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0
-#define SH_MEM_BASES__SHARED_BASE_MASK 0xffff0000
-#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10
-#define SH_MEM_APE1_BASE__BASE_MASK 0xffffffff
-#define SH_MEM_APE1_BASE__BASE__SHIFT 0x0
-#define SH_MEM_APE1_LIMIT__LIMIT_MASK 0xffffffff
-#define SH_MEM_APE1_LIMIT__LIMIT__SHIFT 0x0
-#define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x3
-#define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x0
-#define SH_MEM_CONFIG__PRIVATE_ATC_MASK 0x4
-#define SH_MEM_CONFIG__PRIVATE_ATC__SHIFT 0x2
-#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x18
-#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x3
-#define SH_MEM_CONFIG__DEFAULT_MTYPE_MASK 0xe0
-#define SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT 0x5
-#define SH_MEM_CONFIG__APE1_MTYPE_MASK 0x700
-#define SH_MEM_CONFIG__APE1_MTYPE__SHIFT 0x8
-#define SH_MEM_CONFIG__APE1_ATC_MASK 0x800
-#define SH_MEM_CONFIG__APE1_ATC__SHIFT 0xb
-#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0xf
-#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x10
-#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0xf
-#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x10
-#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x1e0
-#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x600
-#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x9
-#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0xf800
-#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0xb
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0xf
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x10
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x1e0
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x600
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x9
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xffff0000
-#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x10
-#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0xffffff
-#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0xf
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x10
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x20
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x3c0
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x6
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x3c00
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0xa
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0xc000
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0xe
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xffff0000
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x10
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0xffff
-#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0xf
-#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xffff0000
-#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x10
-#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xffffffff
-#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0xf
-#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x10
-#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x20
-#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x3c0
-#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x6
-#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x3c00
-#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0xa
-#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0xc000
-#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0xe
-#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0xf
-#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0xff0
-#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x1000
-#define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0xc
-#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0xe000
-#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0xd
-#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0xf
-#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x10
-#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x20
-#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x3c0
-#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x6
-#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x3c00
-#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0xa
-#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0xc000
-#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0xe
-#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x1f0000
-#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x10
-#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x200000
-#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x15
-#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1fc00000
-#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x16
-#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xe0000000
-#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x1d
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0xf
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x10
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x60
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x180
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x7
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x200
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x9
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x1c00
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0xa
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x4000
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0xe
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x8000
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0xf
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xffff0000
-#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x10
-#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xffffffff
-#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK 0xf
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK 0x10
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK 0x60
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK 0x180
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT 0x7
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK 0xfe00
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT 0x9
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK 0xffff0000
-#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT 0x10
-#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK 0xffff
-#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0xf
-#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x10
-#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x20
-#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x1c0
-#define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x6
-#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0xfc00
-#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0xa
-#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0xf
-#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x10
-#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x60
-#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x300
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x8
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0xc00
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0xa
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x3000
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0xc
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0xc000
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0xe
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x30000
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x10
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0xc0000
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x12
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x300000
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x14
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0xc00000
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x16
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x3000000
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x18
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0xc000000
-#define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x1a
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0xf
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x10
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x4
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x20
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x5
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x3c0
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x6
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0xc00
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0xa
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x1fff000
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0xc
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xfe000000
-#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x19
-#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x3f
-#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x0
-#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x7ffc0
-#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x6
-#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xfff80000
-#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x13
-#define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK 0xffffffff
-#define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT 0x0
-#define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK 0xffff
-#define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT 0x0
-#define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK 0x4000000
-#define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT 0x1a
-#define SQ_WREXEC_EXEC_HI__ATC_MASK 0x8000000
-#define SQ_WREXEC_EXEC_HI__ATC__SHIFT 0x1b
-#define SQ_WREXEC_EXEC_HI__MTYPE_MASK 0x70000000
-#define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT 0x1c
-#define SQ_WREXEC_EXEC_HI__MSB_MASK 0x80000000
-#define SQ_WREXEC_EXEC_HI__MSB__SHIFT 0x1f
-#define SQC_GATCL1_CNTL__RESERVED_MASK 0x3ffff
-#define SQC_GATCL1_CNTL__RESERVED__SHIFT 0x0
-#define SQC_GATCL1_CNTL__DCACHE_INVALIDATE_ALL_VMID_MASK 0x40000
-#define SQC_GATCL1_CNTL__DCACHE_INVALIDATE_ALL_VMID__SHIFT 0x12
-#define SQC_GATCL1_CNTL__DCACHE_FORCE_MISS_MASK 0x80000
-#define SQC_GATCL1_CNTL__DCACHE_FORCE_MISS__SHIFT 0x13
-#define SQC_GATCL1_CNTL__DCACHE_FORCE_IN_ORDER_MASK 0x100000
-#define SQC_GATCL1_CNTL__DCACHE_FORCE_IN_ORDER__SHIFT 0x14
-#define SQC_GATCL1_CNTL__DCACHE_REDUCE_FIFO_DEPTH_BY_2_MASK 0x600000
-#define SQC_GATCL1_CNTL__DCACHE_REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x15
-#define SQC_GATCL1_CNTL__DCACHE_REDUCE_CACHE_SIZE_BY_2_MASK 0x1800000
-#define SQC_GATCL1_CNTL__DCACHE_REDUCE_CACHE_SIZE_BY_2__SHIFT 0x17
-#define SQC_GATCL1_CNTL__ICACHE_INVALIDATE_ALL_VMID_MASK 0x2000000
-#define SQC_GATCL1_CNTL__ICACHE_INVALIDATE_ALL_VMID__SHIFT 0x19
-#define SQC_GATCL1_CNTL__ICACHE_FORCE_MISS_MASK 0x4000000
-#define SQC_GATCL1_CNTL__ICACHE_FORCE_MISS__SHIFT 0x1a
-#define SQC_GATCL1_CNTL__ICACHE_FORCE_IN_ORDER_MASK 0x8000000
-#define SQC_GATCL1_CNTL__ICACHE_FORCE_IN_ORDER__SHIFT 0x1b
-#define SQC_GATCL1_CNTL__ICACHE_REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000
-#define SQC_GATCL1_CNTL__ICACHE_REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
-#define SQC_GATCL1_CNTL__ICACHE_REDUCE_CACHE_SIZE_BY_2_MASK 0xc0000000
-#define SQC_GATCL1_CNTL__ICACHE_REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
-#define SQC_ATC_EDC_GATCL1_CNT__ICACHE_DATA_SEC_MASK 0xff
-#define SQC_ATC_EDC_GATCL1_CNT__ICACHE_DATA_SEC__SHIFT 0x0
-#define SQC_ATC_EDC_GATCL1_CNT__DCACHE_DATA_SEC_MASK 0xff0000
-#define SQC_ATC_EDC_GATCL1_CNT__DCACHE_DATA_SEC__SHIFT 0x10
-#define SQ_INTERRUPT_WORD_CMN__SE_ID_MASK 0x3000000
-#define SQ_INTERRUPT_WORD_CMN__SE_ID__SHIFT 0x18
-#define SQ_INTERRUPT_WORD_CMN__ENCODING_MASK 0xc000000
-#define SQ_INTERRUPT_WORD_CMN__ENCODING__SHIFT 0x1a
-#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_MASK 0x1
-#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE__SHIFT 0x0
-#define SQ_INTERRUPT_WORD_AUTO__WLT_MASK 0x2
-#define SQ_INTERRUPT_WORD_AUTO__WLT__SHIFT 0x1
-#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL_MASK 0x4
-#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL__SHIFT 0x2
-#define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP_MASK 0x8
-#define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP__SHIFT 0x3
-#define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP_MASK 0x10
-#define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP__SHIFT 0x4
-#define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW_MASK 0x20
-#define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW__SHIFT 0x5
-#define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW_MASK 0x40
-#define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW__SHIFT 0x6
-#define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW_MASK 0x80
-#define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW__SHIFT 0x7
-#define SQ_INTERRUPT_WORD_AUTO__SE_ID_MASK 0x3000000
-#define SQ_INTERRUPT_WORD_AUTO__SE_ID__SHIFT 0x18
-#define SQ_INTERRUPT_WORD_AUTO__ENCODING_MASK 0xc000000
-#define SQ_INTERRUPT_WORD_AUTO__ENCODING__SHIFT 0x1a
-#define SQ_INTERRUPT_WORD_WAVE__DATA_MASK 0xff
-#define SQ_INTERRUPT_WORD_WAVE__DATA__SHIFT 0x0
-#define SQ_INTERRUPT_WORD_WAVE__SH_ID_MASK 0x100
-#define SQ_INTERRUPT_WORD_WAVE__SH_ID__SHIFT 0x8
-#define SQ_INTERRUPT_WORD_WAVE__PRIV_MASK 0x200
-#define SQ_INTERRUPT_WORD_WAVE__PRIV__SHIFT 0x9
-#define SQ_INTERRUPT_WORD_WAVE__VM_ID_MASK 0x3c00
-#define SQ_INTERRUPT_WORD_WAVE__VM_ID__SHIFT 0xa
-#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID_MASK 0x3c000
-#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID__SHIFT 0xe
-#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID_MASK 0xc0000
-#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID__SHIFT 0x12
-#define SQ_INTERRUPT_WORD_WAVE__CU_ID_MASK 0xf00000
-#define SQ_INTERRUPT_WORD_WAVE__CU_ID__SHIFT 0x14
-#define SQ_INTERRUPT_WORD_WAVE__SE_ID_MASK 0x3000000
-#define SQ_INTERRUPT_WORD_WAVE__SE_ID__SHIFT 0x18
-#define SQ_INTERRUPT_WORD_WAVE__ENCODING_MASK 0xc000000
-#define SQ_INTERRUPT_WORD_WAVE__ENCODING__SHIFT 0x1a
-#define SQ_SOP2__SSRC0_MASK 0xff
-#define SQ_SOP2__SSRC0__SHIFT 0x0
-#define SQ_SOP2__SSRC1_MASK 0xff00
-#define SQ_SOP2__SSRC1__SHIFT 0x8
-#define SQ_SOP2__SDST_MASK 0x7f0000
-#define SQ_SOP2__SDST__SHIFT 0x10
-#define SQ_SOP2__OP_MASK 0x3f800000
-#define SQ_SOP2__OP__SHIFT 0x17
-#define SQ_SOP2__ENCODING_MASK 0xc0000000
-#define SQ_SOP2__ENCODING__SHIFT 0x1e
-#define SQ_VOP1__SRC0_MASK 0x1ff
-#define SQ_VOP1__SRC0__SHIFT 0x0
-#define SQ_VOP1__OP_MASK 0x1fe00
-#define SQ_VOP1__OP__SHIFT 0x9
-#define SQ_VOP1__VDST_MASK 0x1fe0000
-#define SQ_VOP1__VDST__SHIFT 0x11
-#define SQ_VOP1__ENCODING_MASK 0xfe000000
-#define SQ_VOP1__ENCODING__SHIFT 0x19
-#define SQ_MTBUF_1__VADDR_MASK 0xff
-#define SQ_MTBUF_1__VADDR__SHIFT 0x0
-#define SQ_MTBUF_1__VDATA_MASK 0xff00
-#define SQ_MTBUF_1__VDATA__SHIFT 0x8
-#define SQ_MTBUF_1__SRSRC_MASK 0x1f0000
-#define SQ_MTBUF_1__SRSRC__SHIFT 0x10
-#define SQ_MTBUF_1__SLC_MASK 0x400000
-#define SQ_MTBUF_1__SLC__SHIFT 0x16
-#define SQ_MTBUF_1__TFE_MASK 0x800000
-#define SQ_MTBUF_1__TFE__SHIFT 0x17
-#define SQ_MTBUF_1__SOFFSET_MASK 0xff000000
-#define SQ_MTBUF_1__SOFFSET__SHIFT 0x18
-#define SQ_EXP_1__VSRC0_MASK 0xff
-#define SQ_EXP_1__VSRC0__SHIFT 0x0
-#define SQ_EXP_1__VSRC1_MASK 0xff00
-#define SQ_EXP_1__VSRC1__SHIFT 0x8
-#define SQ_EXP_1__VSRC2_MASK 0xff0000
-#define SQ_EXP_1__VSRC2__SHIFT 0x10
-#define SQ_EXP_1__VSRC3_MASK 0xff000000
-#define SQ_EXP_1__VSRC3__SHIFT 0x18
-#define SQ_MUBUF_1__VADDR_MASK 0xff
-#define SQ_MUBUF_1__VADDR__SHIFT 0x0
-#define SQ_MUBUF_1__VDATA_MASK 0xff00
-#define SQ_MUBUF_1__VDATA__SHIFT 0x8
-#define SQ_MUBUF_1__SRSRC_MASK 0x1f0000
-#define SQ_MUBUF_1__SRSRC__SHIFT 0x10
-#define SQ_MUBUF_1__TFE_MASK 0x800000
-#define SQ_MUBUF_1__TFE__SHIFT 0x17
-#define SQ_MUBUF_1__SOFFSET_MASK 0xff000000
-#define SQ_MUBUF_1__SOFFSET__SHIFT 0x18
-#define SQ_SMEM_1__OFFSET_MASK 0xfffff
-#define SQ_SMEM_1__OFFSET__SHIFT 0x0
-#define SQ_INST__ENCODING_MASK 0xffffffff
-#define SQ_INST__ENCODING__SHIFT 0x0
-#define SQ_EXP_0__EN_MASK 0xf
-#define SQ_EXP_0__EN__SHIFT 0x0
-#define SQ_EXP_0__TGT_MASK 0x3f0
-#define SQ_EXP_0__TGT__SHIFT 0x4
-#define SQ_EXP_0__COMPR_MASK 0x400
-#define SQ_EXP_0__COMPR__SHIFT 0xa
-#define SQ_EXP_0__DONE_MASK 0x800
-#define SQ_EXP_0__DONE__SHIFT 0xb
-#define SQ_EXP_0__VM_MASK 0x1000
-#define SQ_EXP_0__VM__SHIFT 0xc
-#define SQ_EXP_0__ENCODING_MASK 0xfc000000
-#define SQ_EXP_0__ENCODING__SHIFT 0x1a
-#define SQ_MUBUF_0__OFFSET_MASK 0xfff
-#define SQ_MUBUF_0__OFFSET__SHIFT 0x0
-#define SQ_MUBUF_0__OFFEN_MASK 0x1000
-#define SQ_MUBUF_0__OFFEN__SHIFT 0xc
-#define SQ_MUBUF_0__IDXEN_MASK 0x2000
-#define SQ_MUBUF_0__IDXEN__SHIFT 0xd
-#define SQ_MUBUF_0__GLC_MASK 0x4000
-#define SQ_MUBUF_0__GLC__SHIFT 0xe
-#define SQ_MUBUF_0__LDS_MASK 0x10000
-#define SQ_MUBUF_0__LDS__SHIFT 0x10
-#define SQ_MUBUF_0__SLC_MASK 0x20000
-#define SQ_MUBUF_0__SLC__SHIFT 0x11
-#define SQ_MUBUF_0__OP_MASK 0x1fc0000
-#define SQ_MUBUF_0__OP__SHIFT 0x12
-#define SQ_MUBUF_0__ENCODING_MASK 0xfc000000
-#define SQ_MUBUF_0__ENCODING__SHIFT 0x1a
-#define SQ_VOP_SDWA__SRC0_MASK 0xff
-#define SQ_VOP_SDWA__SRC0__SHIFT 0x0
-#define SQ_VOP_SDWA__DST_SEL_MASK 0x700
-#define SQ_VOP_SDWA__DST_SEL__SHIFT 0x8
-#define SQ_VOP_SDWA__DST_UNUSED_MASK 0x1800
-#define SQ_VOP_SDWA__DST_UNUSED__SHIFT 0xb
-#define SQ_VOP_SDWA__CLAMP_MASK 0x2000
-#define SQ_VOP_SDWA__CLAMP__SHIFT 0xd
-#define SQ_VOP_SDWA__SRC0_SEL_MASK 0x70000
-#define SQ_VOP_SDWA__SRC0_SEL__SHIFT 0x10
-#define SQ_VOP_SDWA__SRC0_SEXT_MASK 0x80000
-#define SQ_VOP_SDWA__SRC0_SEXT__SHIFT 0x13
-#define SQ_VOP_SDWA__SRC0_NEG_MASK 0x100000
-#define SQ_VOP_SDWA__SRC0_NEG__SHIFT 0x14
-#define SQ_VOP_SDWA__SRC0_ABS_MASK 0x200000
-#define SQ_VOP_SDWA__SRC0_ABS__SHIFT 0x15
-#define SQ_VOP_SDWA__SRC1_SEL_MASK 0x7000000
-#define SQ_VOP_SDWA__SRC1_SEL__SHIFT 0x18
-#define SQ_VOP_SDWA__SRC1_SEXT_MASK 0x8000000
-#define SQ_VOP_SDWA__SRC1_SEXT__SHIFT 0x1b
-#define SQ_VOP_SDWA__SRC1_NEG_MASK 0x10000000
-#define SQ_VOP_SDWA__SRC1_NEG__SHIFT 0x1c
-#define SQ_VOP_SDWA__SRC1_ABS_MASK 0x20000000
-#define SQ_VOP_SDWA__SRC1_ABS__SHIFT 0x1d
-#define SQ_VOP3_0__VDST_MASK 0xff
-#define SQ_VOP3_0__VDST__SHIFT 0x0
-#define SQ_VOP3_0__ABS_MASK 0x700
-#define SQ_VOP3_0__ABS__SHIFT 0x8
-#define SQ_VOP3_0__CLAMP_MASK 0x8000
-#define SQ_VOP3_0__CLAMP__SHIFT 0xf
-#define SQ_VOP3_0__OP_MASK 0x3ff0000
-#define SQ_VOP3_0__OP__SHIFT 0x10
-#define SQ_VOP3_0__ENCODING_MASK 0xfc000000
-#define SQ_VOP3_0__ENCODING__SHIFT 0x1a
-#define SQ_VOP2__SRC0_MASK 0x1ff
-#define SQ_VOP2__SRC0__SHIFT 0x0
-#define SQ_VOP2__VSRC1_MASK 0x1fe00
-#define SQ_VOP2__VSRC1__SHIFT 0x9
-#define SQ_VOP2__VDST_MASK 0x1fe0000
-#define SQ_VOP2__VDST__SHIFT 0x11
-#define SQ_VOP2__OP_MASK 0x7e000000
-#define SQ_VOP2__OP__SHIFT 0x19
-#define SQ_VOP2__ENCODING_MASK 0x80000000
-#define SQ_VOP2__ENCODING__SHIFT 0x1f
-#define SQ_MTBUF_0__OFFSET_MASK 0xfff
-#define SQ_MTBUF_0__OFFSET__SHIFT 0x0
-#define SQ_MTBUF_0__OFFEN_MASK 0x1000
-#define SQ_MTBUF_0__OFFEN__SHIFT 0xc
-#define SQ_MTBUF_0__IDXEN_MASK 0x2000
-#define SQ_MTBUF_0__IDXEN__SHIFT 0xd
-#define SQ_MTBUF_0__GLC_MASK 0x4000
-#define SQ_MTBUF_0__GLC__SHIFT 0xe
-#define SQ_MTBUF_0__OP_MASK 0x78000
-#define SQ_MTBUF_0__OP__SHIFT 0xf
-#define SQ_MTBUF_0__DFMT_MASK 0x780000
-#define SQ_MTBUF_0__DFMT__SHIFT 0x13
-#define SQ_MTBUF_0__NFMT_MASK 0x3800000
-#define SQ_MTBUF_0__NFMT__SHIFT 0x17
-#define SQ_MTBUF_0__ENCODING_MASK 0xfc000000
-#define SQ_MTBUF_0__ENCODING__SHIFT 0x1a
-#define SQ_SOPP__SIMM16_MASK 0xffff
-#define SQ_SOPP__SIMM16__SHIFT 0x0
-#define SQ_SOPP__OP_MASK 0x7f0000
-#define SQ_SOPP__OP__SHIFT 0x10
-#define SQ_SOPP__ENCODING_MASK 0xff800000
-#define SQ_SOPP__ENCODING__SHIFT 0x17
-#define SQ_FLAT_0__GLC_MASK 0x10000
-#define SQ_FLAT_0__GLC__SHIFT 0x10
-#define SQ_FLAT_0__SLC_MASK 0x20000
-#define SQ_FLAT_0__SLC__SHIFT 0x11
-#define SQ_FLAT_0__OP_MASK 0x1fc0000
-#define SQ_FLAT_0__OP__SHIFT 0x12
-#define SQ_FLAT_0__ENCODING_MASK 0xfc000000
-#define SQ_FLAT_0__ENCODING__SHIFT 0x1a
-#define SQ_VOP3_0_SDST_ENC__VDST_MASK 0xff
-#define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x0
-#define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x7f00
-#define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x8
-#define SQ_VOP3_0_SDST_ENC__CLAMP_MASK 0x8000
-#define SQ_VOP3_0_SDST_ENC__CLAMP__SHIFT 0xf
-#define SQ_VOP3_0_SDST_ENC__OP_MASK 0x3ff0000
-#define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x10
-#define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xfc000000
-#define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x1a
-#define SQ_MIMG_1__VADDR_MASK 0xff
-#define SQ_MIMG_1__VADDR__SHIFT 0x0
-#define SQ_MIMG_1__VDATA_MASK 0xff00
-#define SQ_MIMG_1__VDATA__SHIFT 0x8
-#define SQ_MIMG_1__SRSRC_MASK 0x1f0000
-#define SQ_MIMG_1__SRSRC__SHIFT 0x10
-#define SQ_MIMG_1__SSAMP_MASK 0x3e00000
-#define SQ_MIMG_1__SSAMP__SHIFT 0x15
-#define SQ_MIMG_1__D16_MASK 0x80000000
-#define SQ_MIMG_1__D16__SHIFT 0x1f
-#define SQ_SOP1__SSRC0_MASK 0xff
-#define SQ_SOP1__SSRC0__SHIFT 0x0
-#define SQ_SOP1__OP_MASK 0xff00
-#define SQ_SOP1__OP__SHIFT 0x8
-#define SQ_SOP1__SDST_MASK 0x7f0000
-#define SQ_SOP1__SDST__SHIFT 0x10
-#define SQ_SOP1__ENCODING_MASK 0xff800000
-#define SQ_SOP1__ENCODING__SHIFT 0x17
-#define SQ_SOPC__SSRC0_MASK 0xff
-#define SQ_SOPC__SSRC0__SHIFT 0x0
-#define SQ_SOPC__SSRC1_MASK 0xff00
-#define SQ_SOPC__SSRC1__SHIFT 0x8
-#define SQ_SOPC__OP_MASK 0x7f0000
-#define SQ_SOPC__OP__SHIFT 0x10
-#define SQ_SOPC__ENCODING_MASK 0xff800000
-#define SQ_SOPC__ENCODING__SHIFT 0x17
-#define SQ_FLAT_1__ADDR_MASK 0xff
-#define SQ_FLAT_1__ADDR__SHIFT 0x0
-#define SQ_FLAT_1__DATA_MASK 0xff00
-#define SQ_FLAT_1__DATA__SHIFT 0x8
-#define SQ_FLAT_1__TFE_MASK 0x800000
-#define SQ_FLAT_1__TFE__SHIFT 0x17
-#define SQ_FLAT_1__VDST_MASK 0xff000000
-#define SQ_FLAT_1__VDST__SHIFT 0x18
-#define SQ_DS_1__ADDR_MASK 0xff
-#define SQ_DS_1__ADDR__SHIFT 0x0
-#define SQ_DS_1__DATA0_MASK 0xff00
-#define SQ_DS_1__DATA0__SHIFT 0x8
-#define SQ_DS_1__DATA1_MASK 0xff0000
-#define SQ_DS_1__DATA1__SHIFT 0x10
-#define SQ_DS_1__VDST_MASK 0xff000000
-#define SQ_DS_1__VDST__SHIFT 0x18
-#define SQ_VOP3_1__SRC0_MASK 0x1ff
-#define SQ_VOP3_1__SRC0__SHIFT 0x0
-#define SQ_VOP3_1__SRC1_MASK 0x3fe00
-#define SQ_VOP3_1__SRC1__SHIFT 0x9
-#define SQ_VOP3_1__SRC2_MASK 0x7fc0000
-#define SQ_VOP3_1__SRC2__SHIFT 0x12
-#define SQ_VOP3_1__OMOD_MASK 0x18000000
-#define SQ_VOP3_1__OMOD__SHIFT 0x1b
-#define SQ_VOP3_1__NEG_MASK 0xe0000000
-#define SQ_VOP3_1__NEG__SHIFT 0x1d
-#define SQ_SMEM_0__SBASE_MASK 0x3f
-#define SQ_SMEM_0__SBASE__SHIFT 0x0
-#define SQ_SMEM_0__SDATA_MASK 0x1fc0
-#define SQ_SMEM_0__SDATA__SHIFT 0x6
-#define SQ_SMEM_0__GLC_MASK 0x10000
-#define SQ_SMEM_0__GLC__SHIFT 0x10
-#define SQ_SMEM_0__IMM_MASK 0x20000
-#define SQ_SMEM_0__IMM__SHIFT 0x11
-#define SQ_SMEM_0__OP_MASK 0x3fc0000
-#define SQ_SMEM_0__OP__SHIFT 0x12
-#define SQ_SMEM_0__ENCODING_MASK 0xfc000000
-#define SQ_SMEM_0__ENCODING__SHIFT 0x1a
-#define SQ_MIMG_0__DMASK_MASK 0xf00
-#define SQ_MIMG_0__DMASK__SHIFT 0x8
-#define SQ_MIMG_0__UNORM_MASK 0x1000
-#define SQ_MIMG_0__UNORM__SHIFT 0xc
-#define SQ_MIMG_0__GLC_MASK 0x2000
-#define SQ_MIMG_0__GLC__SHIFT 0xd
-#define SQ_MIMG_0__DA_MASK 0x4000
-#define SQ_MIMG_0__DA__SHIFT 0xe
-#define SQ_MIMG_0__R128_MASK 0x8000
-#define SQ_MIMG_0__R128__SHIFT 0xf
-#define SQ_MIMG_0__TFE_MASK 0x10000
-#define SQ_MIMG_0__TFE__SHIFT 0x10
-#define SQ_MIMG_0__LWE_MASK 0x20000
-#define SQ_MIMG_0__LWE__SHIFT 0x11
-#define SQ_MIMG_0__OP_MASK 0x1fc0000
-#define SQ_MIMG_0__OP__SHIFT 0x12
-#define SQ_MIMG_0__SLC_MASK 0x2000000
-#define SQ_MIMG_0__SLC__SHIFT 0x19
-#define SQ_MIMG_0__ENCODING_MASK 0xfc000000
-#define SQ_MIMG_0__ENCODING__SHIFT 0x1a
-#define SQ_SOPK__SIMM16_MASK 0xffff
-#define SQ_SOPK__SIMM16__SHIFT 0x0
-#define SQ_SOPK__SDST_MASK 0x7f0000
-#define SQ_SOPK__SDST__SHIFT 0x10
-#define SQ_SOPK__OP_MASK 0xf800000
-#define SQ_SOPK__OP__SHIFT 0x17
-#define SQ_SOPK__ENCODING_MASK 0xf0000000
-#define SQ_SOPK__ENCODING__SHIFT 0x1c
-#define SQ_DS_0__OFFSET0_MASK 0xff
-#define SQ_DS_0__OFFSET0__SHIFT 0x0
-#define SQ_DS_0__OFFSET1_MASK 0xff00
-#define SQ_DS_0__OFFSET1__SHIFT 0x8
-#define SQ_DS_0__GDS_MASK 0x10000
-#define SQ_DS_0__GDS__SHIFT 0x10
-#define SQ_DS_0__OP_MASK 0x1fe0000
-#define SQ_DS_0__OP__SHIFT 0x11
-#define SQ_DS_0__ENCODING_MASK 0xfc000000
-#define SQ_DS_0__ENCODING__SHIFT 0x1a
-#define SQ_VOP_DPP__SRC0_MASK 0xff
-#define SQ_VOP_DPP__SRC0__SHIFT 0x0
-#define SQ_VOP_DPP__DPP_CTRL_MASK 0x1ff00
-#define SQ_VOP_DPP__DPP_CTRL__SHIFT 0x8
-#define SQ_VOP_DPP__BOUND_CTRL_MASK 0x80000
-#define SQ_VOP_DPP__BOUND_CTRL__SHIFT 0x13
-#define SQ_VOP_DPP__SRC0_NEG_MASK 0x100000
-#define SQ_VOP_DPP__SRC0_NEG__SHIFT 0x14
-#define SQ_VOP_DPP__SRC0_ABS_MASK 0x200000
-#define SQ_VOP_DPP__SRC0_ABS__SHIFT 0x15
-#define SQ_VOP_DPP__SRC1_NEG_MASK 0x400000
-#define SQ_VOP_DPP__SRC1_NEG__SHIFT 0x16
-#define SQ_VOP_DPP__SRC1_ABS_MASK 0x800000
-#define SQ_VOP_DPP__SRC1_ABS__SHIFT 0x17
-#define SQ_VOP_DPP__BANK_MASK_MASK 0xf000000
-#define SQ_VOP_DPP__BANK_MASK__SHIFT 0x18
-#define SQ_VOP_DPP__ROW_MASK_MASK 0xf0000000
-#define SQ_VOP_DPP__ROW_MASK__SHIFT 0x1c
-#define SQ_VOPC__SRC0_MASK 0x1ff
-#define SQ_VOPC__SRC0__SHIFT 0x0
-#define SQ_VOPC__VSRC1_MASK 0x1fe00
-#define SQ_VOPC__VSRC1__SHIFT 0x9
-#define SQ_VOPC__OP_MASK 0x1fe0000
-#define SQ_VOPC__OP__SHIFT 0x11
-#define SQ_VOPC__ENCODING_MASK 0xfe000000
-#define SQ_VOPC__ENCODING__SHIFT 0x19
-#define SQ_VINTRP__VSRC_MASK 0xff
-#define SQ_VINTRP__VSRC__SHIFT 0x0
-#define SQ_VINTRP__ATTRCHAN_MASK 0x300
-#define SQ_VINTRP__ATTRCHAN__SHIFT 0x8
-#define SQ_VINTRP__ATTR_MASK 0xfc00
-#define SQ_VINTRP__ATTR__SHIFT 0xa
-#define SQ_VINTRP__OP_MASK 0x30000
-#define SQ_VINTRP__OP__SHIFT 0x10
-#define SQ_VINTRP__VDST_MASK 0x3fc0000
-#define SQ_VINTRP__VDST__SHIFT 0x12
-#define SQ_VINTRP__ENCODING_MASK 0xfc000000
-#define SQ_VINTRP__ENCODING__SHIFT 0x1a
-#define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0xf
-#define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x0
-#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0xff0
-#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0xfff000
-#define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0xc
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x1000000
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x2000000
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x4000000
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x8000000
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000
-#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
-#define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0xf
-#define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x0
-#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0xff0
-#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0xfff000
-#define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0xc
-#define CGTT_SX_CLK_CTRL1__DBG_EN_MASK 0x1000000
-#define CGTT_SX_CLK_CTRL1__DBG_EN__SHIFT 0x18
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x2000000
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x4000000
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x8000000
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000
-#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x1f
-#define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0xf
-#define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x0
-#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0xff0
-#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0xfff000
-#define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0xc
-#define CGTT_SX_CLK_CTRL2__DBG_EN_MASK 0x1000000
-#define CGTT_SX_CLK_CTRL2__DBG_EN__SHIFT 0x18
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x2000000
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x4000000
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x8000000
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000
-#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x1f
-#define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0xf
-#define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x0
-#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0xff0
-#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0xfff000
-#define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0xc
-#define CGTT_SX_CLK_CTRL3__DBG_EN_MASK 0x1000000
-#define CGTT_SX_CLK_CTRL3__DBG_EN__SHIFT 0x18
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x2000000
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x4000000
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x8000000
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000
-#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x1f
-#define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0xf
-#define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x0
-#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0xff0
-#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0xfff000
-#define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0xc
-#define CGTT_SX_CLK_CTRL4__DBG_EN_MASK 0x1000000
-#define CGTT_SX_CLK_CTRL4__DBG_EN__SHIFT 0x18
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x2000000
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x19
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x4000000
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x1a
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x8000000
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x1d
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x1e
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000
-#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x1f
-#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS_MASK 0x1
-#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS__SHIFT 0x0
-#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY_MASK 0x2
-#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY__SHIFT 0x1
-#define SX_DEBUG_BUSY__PA_SX_BUSY_MASK 0x4
-#define SX_DEBUG_BUSY__PA_SX_BUSY__SHIFT 0x2
-#define SX_DEBUG_BUSY__POS_SCBD_BUSY_MASK 0x8
-#define SX_DEBUG_BUSY__POS_SCBD_BUSY__SHIFT 0x3
-#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY_MASK 0x10
-#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY__SHIFT 0x4
-#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY_MASK 0x20
-#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY__SHIFT 0x5
-#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY_MASK 0x40
-#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY__SHIFT 0x6
-#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY_MASK 0x80
-#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY__SHIFT 0x7
-#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY_MASK 0x100
-#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY__SHIFT 0x8
-#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY_MASK 0x200
-#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY__SHIFT 0x9
-#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY_MASK 0x400
-#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY__SHIFT 0xa
-#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY_MASK 0x800
-#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY__SHIFT 0xb
-#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY_MASK 0x1000
-#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY__SHIFT 0xc
-#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY_MASK 0x2000
-#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY__SHIFT 0xd
-#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY_MASK 0x4000
-#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY__SHIFT 0xe
-#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY_MASK 0x8000
-#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY__SHIFT 0xf
-#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY_MASK 0x10000
-#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY__SHIFT 0x10
-#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY_MASK 0x20000
-#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY__SHIFT 0x11
-#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY_MASK 0x40000
-#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY__SHIFT 0x12
-#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY_MASK 0x80000
-#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY__SHIFT 0x13
-#define SX_DEBUG_BUSY__POS_INMUX_VALID_MASK 0x100000
-#define SX_DEBUG_BUSY__POS_INMUX_VALID__SHIFT 0x14
-#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3_MASK 0x200000
-#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3__SHIFT 0x15
-#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2_MASK 0x400000
-#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2__SHIFT 0x16
-#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1_MASK 0x800000
-#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1__SHIFT 0x17
-#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3_MASK 0x1000000
-#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3__SHIFT 0x18
-#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2_MASK 0x2000000
-#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2__SHIFT 0x19
-#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1_MASK 0x4000000
-#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1__SHIFT 0x1a
-#define SX_DEBUG_BUSY__PCCMD_VALID_MASK 0x8000000
-#define SX_DEBUG_BUSY__PCCMD_VALID__SHIFT 0x1b
-#define SX_DEBUG_BUSY__VDATA1_VALID_MASK 0x10000000
-#define SX_DEBUG_BUSY__VDATA1_VALID__SHIFT 0x1c
-#define SX_DEBUG_BUSY__VDATA0_VALID_MASK 0x20000000
-#define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT 0x1d
-#define SX_DEBUG_BUSY__CMD_BUSYORVAL_MASK 0x40000000
-#define SX_DEBUG_BUSY__CMD_BUSYORVAL__SHIFT 0x1e
-#define SX_DEBUG_BUSY__ADDR_BUSYORVAL_MASK 0x80000000
-#define SX_DEBUG_BUSY__ADDR_BUSYORVAL__SHIFT 0x1f
-#define SX_DEBUG_BUSY_2__COL_SCBD_BUSY_MASK 0x1
-#define SX_DEBUG_BUSY_2__COL_SCBD_BUSY__SHIFT 0x0
-#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0_MASK 0x2
-#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0__SHIFT 0x1
-#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE_MASK 0x4
-#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE__SHIFT 0x2
-#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY_MASK 0x8
-#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY__SHIFT 0x3
-#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0_MASK 0x10
-#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0__SHIFT 0x4
-#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE_MASK 0x20
-#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE__SHIFT 0x5
-#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY_MASK 0x40
-#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY__SHIFT 0x6
-#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0_MASK 0x80
-#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0__SHIFT 0x7
-#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE_MASK 0x100
-#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE__SHIFT 0x8
-#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY_MASK 0x200
-#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY__SHIFT 0x9
-#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0_MASK 0x400
-#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0__SHIFT 0xa
-#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE_MASK 0x800
-#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE__SHIFT 0xb
-#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY_MASK 0x1000
-#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY__SHIFT 0xc
-#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY_MASK 0x2000
-#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY__SHIFT 0xd
-#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY_MASK 0x4000
-#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY__SHIFT 0xe
-#define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID_MASK 0x8000
-#define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID__SHIFT 0xf
-#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY_MASK 0x10000
-#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY__SHIFT 0x10
-#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY_MASK 0x20000
-#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY__SHIFT 0x11
-#define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID_MASK 0x40000
-#define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID__SHIFT 0x12
-#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY_MASK 0x80000
-#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY__SHIFT 0x13
-#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY_MASK 0x100000
-#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY__SHIFT 0x14
-#define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID_MASK 0x200000
-#define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID__SHIFT 0x15
-#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY_MASK 0x400000
-#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY__SHIFT 0x16
-#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY_MASK 0x800000
-#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY__SHIFT 0x17
-#define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID_MASK 0x1000000
-#define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID__SHIFT 0x18
-#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY_MASK 0x2000000
-#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY__SHIFT 0x19
-#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY_MASK 0x4000000
-#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY__SHIFT 0x1a
-#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY_MASK 0x8000000
-#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY__SHIFT 0x1b
-#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY_MASK 0x10000000
-#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY__SHIFT 0x1c
-#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY_MASK 0x20000000
-#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY__SHIFT 0x1d
-#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY_MASK 0x40000000
-#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY__SHIFT 0x1e
-#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY_MASK 0x80000000
-#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY__SHIFT 0x1f
-#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY_MASK 0x1
-#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY__SHIFT 0x0
-#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY_MASK 0x2
-#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY__SHIFT 0x1
-#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY_MASK 0x4
-#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY__SHIFT 0x2
-#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY_MASK 0x8
-#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY__SHIFT 0x3
-#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY_MASK 0x10
-#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY__SHIFT 0x4
-#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY_MASK 0x20
-#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY__SHIFT 0x5
-#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY_MASK 0x40
-#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY__SHIFT 0x6
-#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY_MASK 0x80
-#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY__SHIFT 0x7
-#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY_MASK 0x100
-#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY__SHIFT 0x8
-#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY_MASK 0x200
-#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY__SHIFT 0x9
-#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY_MASK 0x400
-#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY__SHIFT 0xa
-#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY_MASK 0x800
-#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY__SHIFT 0xb
-#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY_MASK 0x1000
-#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY__SHIFT 0xc
-#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY_MASK 0x2000
-#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY__SHIFT 0xd
-#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY_MASK 0x4000
-#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY__SHIFT 0xe
-#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY_MASK 0x8000
-#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY__SHIFT 0xf
-#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY_MASK 0x10000
-#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY__SHIFT 0x10
-#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY_MASK 0x20000
-#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY__SHIFT 0x11
-#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY_MASK 0x40000
-#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY__SHIFT 0x12
-#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY_MASK 0x80000
-#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY__SHIFT 0x13
-#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY_MASK 0x100000
-#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY__SHIFT 0x14
-#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY_MASK 0x200000
-#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY__SHIFT 0x15
-#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY_MASK 0x400000
-#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY__SHIFT 0x16
-#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY_MASK 0x800000
-#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY__SHIFT 0x17
-#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY_MASK 0x1000000
-#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY__SHIFT 0x18
-#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY_MASK 0x2000000
-#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY__SHIFT 0x19
-#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY_MASK 0x4000000
-#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY__SHIFT 0x1a
-#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY_MASK 0x8000000
-#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY__SHIFT 0x1b
-#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY_MASK 0x10000000
-#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY__SHIFT 0x1c
-#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY_MASK 0x20000000
-#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY__SHIFT 0x1d
-#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY_MASK 0x40000000
-#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY__SHIFT 0x1e
-#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY_MASK 0x80000000
-#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY__SHIFT 0x1f
-#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY_MASK 0x1
-#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY__SHIFT 0x0
-#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY_MASK 0x2
-#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY__SHIFT 0x1
-#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY_MASK 0x4
-#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY__SHIFT 0x2
-#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY_MASK 0x8
-#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY__SHIFT 0x3
-#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY_MASK 0x10
-#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY__SHIFT 0x4
-#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY_MASK 0x20
-#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY__SHIFT 0x5
-#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY_MASK 0x40
-#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY__SHIFT 0x6
-#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY_MASK 0x80
-#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY__SHIFT 0x7
-#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY_MASK 0x100
-#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY__SHIFT 0x8
-#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY_MASK 0x200
-#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY__SHIFT 0x9
-#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY_MASK 0x400
-#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY__SHIFT 0xa
-#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY_MASK 0x800
-#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY__SHIFT 0xb
-#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY_MASK 0x1000
-#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY__SHIFT 0xc
-#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY_MASK 0x2000
-#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY__SHIFT 0xd
-#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY_MASK 0x4000
-#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY__SHIFT 0xe
-#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY_MASK 0x8000
-#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY__SHIFT 0xf
-#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY_MASK 0x10000
-#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY__SHIFT 0x10
-#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY_MASK 0x20000
-#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY__SHIFT 0x11
-#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY_MASK 0x40000
-#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY__SHIFT 0x12
-#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY_MASK 0x80000
-#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY__SHIFT 0x13
-#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY_MASK 0x100000
-#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY__SHIFT 0x14
-#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY_MASK 0x200000
-#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY__SHIFT 0x15
-#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY_MASK 0x400000
-#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY__SHIFT 0x16
-#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY_MASK 0x800000
-#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY__SHIFT 0x17
-#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY_MASK 0x1000000
-#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY__SHIFT 0x18
-#define SX_DEBUG_BUSY_4__RESERVED_MASK 0xfe000000
-#define SX_DEBUG_BUSY_4__RESERVED__SHIFT 0x19
-#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x7f
-#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0
-#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x100
-#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x8
-#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS_MASK 0x200
-#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x9
-#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x400
-#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0xa
-#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT_MASK 0x800
-#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT__SHIFT 0xb
-#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT_MASK 0x1000
-#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT__SHIFT 0xc
-#define SX_DEBUG_1__DEBUG_DATA_MASK 0xffffe000
-#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0xd
-#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
-#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
-#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
-#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
-#define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
-#define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
-#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
-#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
-#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
-#define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
-#define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
-#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
-#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
-#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
-#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
-#define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
-#define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
-#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
-#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
-#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
-#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
-#define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
-#define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
-#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff
-#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
-#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00
-#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
-#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff
-#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
-#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00
-#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
-#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define SX_PS_DOWNCONVERT__MRT0_MASK 0xf
-#define SX_PS_DOWNCONVERT__MRT0__SHIFT 0x0
-#define SX_PS_DOWNCONVERT__MRT1_MASK 0xf0
-#define SX_PS_DOWNCONVERT__MRT1__SHIFT 0x4
-#define SX_PS_DOWNCONVERT__MRT2_MASK 0xf00
-#define SX_PS_DOWNCONVERT__MRT2__SHIFT 0x8
-#define SX_PS_DOWNCONVERT__MRT3_MASK 0xf000
-#define SX_PS_DOWNCONVERT__MRT3__SHIFT 0xc
-#define SX_PS_DOWNCONVERT__MRT4_MASK 0xf0000
-#define SX_PS_DOWNCONVERT__MRT4__SHIFT 0x10
-#define SX_PS_DOWNCONVERT__MRT5_MASK 0xf00000
-#define SX_PS_DOWNCONVERT__MRT5__SHIFT 0x14
-#define SX_PS_DOWNCONVERT__MRT6_MASK 0xf000000
-#define SX_PS_DOWNCONVERT__MRT6__SHIFT 0x18
-#define SX_PS_DOWNCONVERT__MRT7_MASK 0xf0000000
-#define SX_PS_DOWNCONVERT__MRT7__SHIFT 0x1c
-#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON_MASK 0xf
-#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON__SHIFT 0x0
-#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON_MASK 0xf0
-#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON__SHIFT 0x4
-#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON_MASK 0xf00
-#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON__SHIFT 0x8
-#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON_MASK 0xf000
-#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON__SHIFT 0xc
-#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON_MASK 0xf0000
-#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON__SHIFT 0x10
-#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON_MASK 0xf00000
-#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON__SHIFT 0x14
-#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON_MASK 0xf000000
-#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON__SHIFT 0x18
-#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON_MASK 0xf0000000
-#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON__SHIFT 0x1c
-#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE_MASK 0x1
-#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE__SHIFT 0x0
-#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE_MASK 0x2
-#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE__SHIFT 0x1
-#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE_MASK 0x10
-#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE__SHIFT 0x4
-#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE_MASK 0x20
-#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE__SHIFT 0x5
-#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE_MASK 0x100
-#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE__SHIFT 0x8
-#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE_MASK 0x200
-#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE__SHIFT 0x9
-#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE_MASK 0x1000
-#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE__SHIFT 0xc
-#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE_MASK 0x2000
-#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE__SHIFT 0xd
-#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE_MASK 0x10000
-#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE__SHIFT 0x10
-#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE_MASK 0x20000
-#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE__SHIFT 0x11
-#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE_MASK 0x100000
-#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE__SHIFT 0x14
-#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE_MASK 0x200000
-#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE__SHIFT 0x15
-#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE_MASK 0x1000000
-#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE__SHIFT 0x18
-#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE_MASK 0x2000000
-#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE__SHIFT 0x19
-#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE_MASK 0x10000000
-#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE__SHIFT 0x1c
-#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE_MASK 0x20000000
-#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE__SHIFT 0x1d
-#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE_MASK 0x80000000
-#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE__SHIFT 0x1f
-#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT_MASK 0x7
-#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
-#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT_MASK 0x70
-#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
-#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN_MASK 0x700
-#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
-#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x70000
-#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
-#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT_MASK 0x700000
-#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
-#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x7000000
-#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
-#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT_MASK 0x7
-#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
-#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT_MASK 0x70
-#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
-#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN_MASK 0x700
-#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
-#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x70000
-#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
-#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT_MASK 0x700000
-#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
-#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x7000000
-#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
-#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT_MASK 0x7
-#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
-#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT_MASK 0x70
-#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
-#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN_MASK 0x700
-#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
-#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x70000
-#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
-#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT_MASK 0x700000
-#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
-#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x7000000
-#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
-#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT_MASK 0x7
-#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
-#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT_MASK 0x70
-#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
-#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN_MASK 0x700
-#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
-#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x70000
-#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
-#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT_MASK 0x700000
-#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
-#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x7000000
-#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
-#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT_MASK 0x7
-#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
-#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT_MASK 0x70
-#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
-#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN_MASK 0x700
-#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
-#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x70000
-#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
-#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT_MASK 0x700000
-#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
-#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x7000000
-#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
-#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT_MASK 0x7
-#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
-#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT_MASK 0x70
-#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
-#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN_MASK 0x700
-#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
-#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x70000
-#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
-#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT_MASK 0x700000
-#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
-#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x7000000
-#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
-#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT_MASK 0x7
-#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
-#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT_MASK 0x70
-#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
-#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN_MASK 0x700
-#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
-#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x70000
-#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
-#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT_MASK 0x700000
-#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
-#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x7000000
-#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
-#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT_MASK 0x7
-#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
-#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT_MASK 0x70
-#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
-#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN_MASK 0x700
-#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
-#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x70000
-#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
-#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT_MASK 0x700000
-#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
-#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x7000000
-#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
-#define TCC_CTRL__CACHE_SIZE_MASK 0x3
-#define TCC_CTRL__CACHE_SIZE__SHIFT 0x0
-#define TCC_CTRL__RATE_MASK 0xc
-#define TCC_CTRL__RATE__SHIFT 0x2
-#define TCC_CTRL__WRITEBACK_MARGIN_MASK 0xf0
-#define TCC_CTRL__WRITEBACK_MARGIN__SHIFT 0x4
-#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK 0xf00
-#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE__SHIFT 0x8
-#define TCC_CTRL__SRC_FIFO_SIZE_MASK 0xf000
-#define TCC_CTRL__SRC_FIFO_SIZE__SHIFT 0xc
-#define TCC_CTRL__LATENCY_FIFO_SIZE_MASK 0xf0000
-#define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10
-#define TCC_CTRL__WB_OR_INV_ALL_VMIDS_MASK 0x100000
-#define TCC_CTRL__WB_OR_INV_ALL_VMIDS__SHIFT 0x14
-#define TCC_CTRL__MDC_SIZE_MASK 0x3000000
-#define TCC_CTRL__MDC_SIZE__SHIFT 0x18
-#define TCC_CTRL__MDC_SECTOR_SIZE_MASK 0xc000000
-#define TCC_CTRL__MDC_SECTOR_SIZE__SHIFT 0x1a
-#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE_MASK 0xf0000000
-#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE__SHIFT 0x1c
-#define TCC_EDC_CNT__SEC_COUNT_MASK 0xff
-#define TCC_EDC_CNT__SEC_COUNT__SHIFT 0x0
-#define TCC_EDC_CNT__DED_COUNT_MASK 0xff0000
-#define TCC_EDC_CNT__DED_COUNT__SHIFT 0x10
-#define TCC_REDUNDANCY__MC_SEL0_MASK 0x1
-#define TCC_REDUNDANCY__MC_SEL0__SHIFT 0x0
-#define TCC_REDUNDANCY__MC_SEL1_MASK 0x2
-#define TCC_REDUNDANCY__MC_SEL1__SHIFT 0x1
-#define TCC_EXE_DISABLE__EXE_DISABLE_MASK 0x2
-#define TCC_EXE_DISABLE__EXE_DISABLE__SHIFT 0x1
-#define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL_MASK 0x3
-#define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0
-#define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x4
-#define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2
-#define TCC_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf
-#define TCC_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
-#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
-#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
-#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
-#define TCA_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf
-#define TCA_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
-#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
-#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
-#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
-#define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
-#define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
-#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
-#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
-#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
-#define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
-#define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
-#define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
-#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
-#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
-#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
-#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
-#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
-#define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
-#define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
-#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
-#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf000000
-#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
-#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000
-#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
-#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
-#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
-#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
-#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
-#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf000000
-#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18
-#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000
-#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c
-#define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
-#define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
-#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
-#define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
-#define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
-#define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
-#define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
-#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
-#define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
-#define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
-#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TCA_CTRL__HOLE_TIMEOUT_MASK 0xf
-#define TCA_CTRL__HOLE_TIMEOUT__SHIFT 0x0
-#define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
-#define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
-#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
-#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
-#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
-#define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
-#define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
-#define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
-#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
-#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
-#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
-#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
-#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
-#define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
-#define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
-#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
-#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf000000
-#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
-#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000
-#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
-#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
-#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
-#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
-#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
-#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf000000
-#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18
-#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000
-#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c
-#define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
-#define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
-#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
-#define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
-#define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
-#define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
-#define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
-#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
-#define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
-#define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
-#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TA_BC_BASE_ADDR__ADDRESS_MASK 0xffffffff
-#define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x0
-#define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0xff
-#define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0
-#define TD_CNTL__SYNC_PHASE_SH_MASK 0x3
-#define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x0
-#define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x30
-#define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x4
-#define TD_CNTL__PAD_STALL_EN_MASK 0x100
-#define TD_CNTL__PAD_STALL_EN__SHIFT 0x8
-#define TD_CNTL__EXTEND_LDS_STALL_MASK 0x600
-#define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x9
-#define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x1800
-#define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0xb
-#define TD_CNTL__PRECISION_COMPATIBILITY_MASK 0x8000
-#define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT 0xf
-#define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x10000
-#define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x10
-#define TD_CNTL__LD_FLOAT_MODE_MASK 0x40000
-#define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x12
-#define TD_CNTL__GATHER4_DX9_MODE_MASK 0x80000
-#define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x13
-#define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x100000
-#define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x14
-#define TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK 0x200000
-#define TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT 0x15
-#define TD_CNTL__DISABLE_D16_PACKING_MASK 0x400000
-#define TD_CNTL__DISABLE_D16_PACKING__SHIFT 0x16
-#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT_MASK 0x800000
-#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT__SHIFT 0x17
-#define TD_STATUS__BUSY_MASK 0x80000000
-#define TD_STATUS__BUSY__SHIFT 0x1f
-#define TD_DEBUG_INDEX__INDEX_MASK 0x1f
-#define TD_DEBUG_INDEX__INDEX__SHIFT 0x0
-#define TD_DEBUG_DATA__DATA_MASK 0xffffffff
-#define TD_DEBUG_DATA__DATA__SHIFT 0x0
-#define TD_DSM_CNTL__FORCE_SEDB_0_MASK 0x1
-#define TD_DSM_CNTL__FORCE_SEDB_0__SHIFT 0x0
-#define TD_DSM_CNTL__FORCE_SEDB_1_MASK 0x2
-#define TD_DSM_CNTL__FORCE_SEDB_1__SHIFT 0x1
-#define TD_DSM_CNTL__EN_SINGLE_WR_SEDB_MASK 0x4
-#define TD_DSM_CNTL__EN_SINGLE_WR_SEDB__SHIFT 0x2
-#define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff
-#define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x3fc00
-#define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
-#define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
-#define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
-#define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
-#define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff
-#define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define TD_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x3fc00
-#define TD_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
-#define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
-#define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
-#define TD_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
-#define TD_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
-#define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
-#define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0xff
-#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x3fc00
-#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
-#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
-#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
-#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TD_SCRATCH__SCRATCH_MASK 0xffffffff
-#define TD_SCRATCH__SCRATCH__SHIFT 0x0
-#define TA_CNTL__FX_XNACK_CREDIT_MASK 0x7f
-#define TA_CNTL__FX_XNACK_CREDIT__SHIFT 0x0
-#define TA_CNTL__SQ_XNACK_CREDIT_MASK 0x1e00
-#define TA_CNTL__SQ_XNACK_CREDIT__SHIFT 0x9
-#define TA_CNTL__TC_DATA_CREDIT_MASK 0xe000
-#define TA_CNTL__TC_DATA_CREDIT__SHIFT 0xd
-#define TA_CNTL__ALIGNER_CREDIT_MASK 0x1f0000
-#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10
-#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xffc00000
-#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16
-#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x1
-#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0
-#define TA_CNTL_AUX__RESERVED_MASK 0xe
-#define TA_CNTL_AUX__RESERVED__SHIFT 0x1
-#define TA_CNTL_AUX__D16_PACK_DISABLE_MASK 0x10
-#define TA_CNTL_AUX__D16_PACK_DISABLE__SHIFT 0x4
-#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x10000
-#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10
-#define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK 0x20000
-#define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT 0x11
-#define TA_CNTL_AUX__ANISO_TAP_MASK 0x40000
-#define TA_CNTL_AUX__ANISO_TAP__SHIFT 0x12
-#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE_MASK 0x80000
-#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE__SHIFT 0x13
-#define TA_RESERVED_010C__Unused_MASK 0xffffffff
-#define TA_RESERVED_010C__Unused__SHIFT 0x0
-#define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xffffffff
-#define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x0
-#define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0xff
-#define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0
-#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x1000
-#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc
-#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x2000
-#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd
-#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x4000
-#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe
-#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x10000
-#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10
-#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x20000
-#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11
-#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x40000
-#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12
-#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x100000
-#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14
-#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x200000
-#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15
-#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x400000
-#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16
-#define TA_STATUS__IN_BUSY_MASK 0x1000000
-#define TA_STATUS__IN_BUSY__SHIFT 0x18
-#define TA_STATUS__FG_BUSY_MASK 0x2000000
-#define TA_STATUS__FG_BUSY__SHIFT 0x19
-#define TA_STATUS__LA_BUSY_MASK 0x4000000
-#define TA_STATUS__LA_BUSY__SHIFT 0x1a
-#define TA_STATUS__FL_BUSY_MASK 0x8000000
-#define TA_STATUS__FL_BUSY__SHIFT 0x1b
-#define TA_STATUS__TA_BUSY_MASK 0x10000000
-#define TA_STATUS__TA_BUSY__SHIFT 0x1c
-#define TA_STATUS__FA_BUSY_MASK 0x20000000
-#define TA_STATUS__FA_BUSY__SHIFT 0x1d
-#define TA_STATUS__AL_BUSY_MASK 0x40000000
-#define TA_STATUS__AL_BUSY__SHIFT 0x1e
-#define TA_STATUS__BUSY_MASK 0x80000000
-#define TA_STATUS__BUSY__SHIFT 0x1f
-#define TA_DEBUG_INDEX__INDEX_MASK 0x1f
-#define TA_DEBUG_INDEX__INDEX__SHIFT 0x0
-#define TA_DEBUG_DATA__DATA_MASK 0xffffffff
-#define TA_DEBUG_DATA__DATA__SHIFT 0x0
-#define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff
-#define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x3fc00
-#define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
-#define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
-#define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
-#define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
-#define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff
-#define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define TA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x3fc00
-#define TA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
-#define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
-#define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
-#define TA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
-#define TA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
-#define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
-#define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0xff
-#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x3fc00
-#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
-#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
-#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
-#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TA_SCRATCH__SCRATCH_MASK 0xffffffff
-#define TA_SCRATCH__SCRATCH__SHIFT 0x0
-#define SH_HIDDEN_PRIVATE_BASE_VMID__ADDRESS_MASK 0xffffffff
-#define SH_HIDDEN_PRIVATE_BASE_VMID__ADDRESS__SHIFT 0x0
-#define SH_STATIC_MEM_CONFIG__SWIZZLE_ENABLE_MASK 0x1
-#define SH_STATIC_MEM_CONFIG__SWIZZLE_ENABLE__SHIFT 0x0
-#define SH_STATIC_MEM_CONFIG__ELEMENT_SIZE_MASK 0x6
-#define SH_STATIC_MEM_CONFIG__ELEMENT_SIZE__SHIFT 0x1
-#define SH_STATIC_MEM_CONFIG__INDEX_STRIDE_MASK 0x18
-#define SH_STATIC_MEM_CONFIG__INDEX_STRIDE__SHIFT 0x3
-#define SH_STATIC_MEM_CONFIG__PRIVATE_MTYPE_MASK 0xe0
-#define SH_STATIC_MEM_CONFIG__PRIVATE_MTYPE__SHIFT 0x5
-#define SH_STATIC_MEM_CONFIG__READ_ONLY_CNTL_MASK 0xff00
-#define SH_STATIC_MEM_CONFIG__READ_ONLY_CNTL__SHIFT 0x8
-#define TCP_INVALIDATE__START_MASK 0x1
-#define TCP_INVALIDATE__START__SHIFT 0x0
-#define TCP_STATUS__TCP_BUSY_MASK 0x1
-#define TCP_STATUS__TCP_BUSY__SHIFT 0x0
-#define TCP_STATUS__INPUT_BUSY_MASK 0x2
-#define TCP_STATUS__INPUT_BUSY__SHIFT 0x1
-#define TCP_STATUS__ADRS_BUSY_MASK 0x4
-#define TCP_STATUS__ADRS_BUSY__SHIFT 0x2
-#define TCP_STATUS__TAGRAMS_BUSY_MASK 0x8
-#define TCP_STATUS__TAGRAMS_BUSY__SHIFT 0x3
-#define TCP_STATUS__CNTRL_BUSY_MASK 0x10
-#define TCP_STATUS__CNTRL_BUSY__SHIFT 0x4
-#define TCP_STATUS__LFIFO_BUSY_MASK 0x20
-#define TCP_STATUS__LFIFO_BUSY__SHIFT 0x5
-#define TCP_STATUS__READ_BUSY_MASK 0x40
-#define TCP_STATUS__READ_BUSY__SHIFT 0x6
-#define TCP_STATUS__FORMAT_BUSY_MASK 0x80
-#define TCP_STATUS__FORMAT_BUSY__SHIFT 0x7
-#define TCP_CNTL__FORCE_HIT_MASK 0x1
-#define TCP_CNTL__FORCE_HIT__SHIFT 0x0
-#define TCP_CNTL__FORCE_MISS_MASK 0x2
-#define TCP_CNTL__FORCE_MISS__SHIFT 0x1
-#define TCP_CNTL__L1_SIZE_MASK 0xc
-#define TCP_CNTL__L1_SIZE__SHIFT 0x2
-#define TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK 0x10
-#define TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT 0x4
-#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK 0x20
-#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT 0x5
-#define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x1f8000
-#define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0xf
-#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK 0xfc00000
-#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT 0x16
-#define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000
-#define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x1c
-#define TCP_CNTL__INV_ALL_VMIDS_MASK 0x20000000
-#define TCP_CNTL__INV_ALL_VMIDS__SHIFT 0x1d
-#define TCP_CHAN_STEER_LO__CHAN0_MASK 0xf
-#define TCP_CHAN_STEER_LO__CHAN0__SHIFT 0x0
-#define TCP_CHAN_STEER_LO__CHAN1_MASK 0xf0
-#define TCP_CHAN_STEER_LO__CHAN1__SHIFT 0x4
-#define TCP_CHAN_STEER_LO__CHAN2_MASK 0xf00
-#define TCP_CHAN_STEER_LO__CHAN2__SHIFT 0x8
-#define TCP_CHAN_STEER_LO__CHAN3_MASK 0xf000
-#define TCP_CHAN_STEER_LO__CHAN3__SHIFT 0xc
-#define TCP_CHAN_STEER_LO__CHAN4_MASK 0xf0000
-#define TCP_CHAN_STEER_LO__CHAN4__SHIFT 0x10
-#define TCP_CHAN_STEER_LO__CHAN5_MASK 0xf00000
-#define TCP_CHAN_STEER_LO__CHAN5__SHIFT 0x14
-#define TCP_CHAN_STEER_LO__CHAN6_MASK 0xf000000
-#define TCP_CHAN_STEER_LO__CHAN6__SHIFT 0x18
-#define TCP_CHAN_STEER_LO__CHAN7_MASK 0xf0000000
-#define TCP_CHAN_STEER_LO__CHAN7__SHIFT 0x1c
-#define TCP_CHAN_STEER_HI__CHAN8_MASK 0xf
-#define TCP_CHAN_STEER_HI__CHAN8__SHIFT 0x0
-#define TCP_CHAN_STEER_HI__CHAN9_MASK 0xf0
-#define TCP_CHAN_STEER_HI__CHAN9__SHIFT 0x4
-#define TCP_CHAN_STEER_HI__CHANA_MASK 0xf00
-#define TCP_CHAN_STEER_HI__CHANA__SHIFT 0x8
-#define TCP_CHAN_STEER_HI__CHANB_MASK 0xf000
-#define TCP_CHAN_STEER_HI__CHANB__SHIFT 0xc
-#define TCP_CHAN_STEER_HI__CHANC_MASK 0xf0000
-#define TCP_CHAN_STEER_HI__CHANC__SHIFT 0x10
-#define TCP_CHAN_STEER_HI__CHAND_MASK 0xf00000
-#define TCP_CHAN_STEER_HI__CHAND__SHIFT 0x14
-#define TCP_CHAN_STEER_HI__CHANE_MASK 0xf000000
-#define TCP_CHAN_STEER_HI__CHANE__SHIFT 0x18
-#define TCP_CHAN_STEER_HI__CHANF_MASK 0xf0000000
-#define TCP_CHAN_STEER_HI__CHANF__SHIFT 0x1c
-#define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0xf
-#define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT 0x0
-#define TCP_ADDR_CONFIG__NUM_BANKS_MASK 0x30
-#define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT 0x4
-#define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK 0x1c0
-#define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT 0x6
-#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK 0x200
-#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT 0x9
-#define TCP_CREDIT__LFIFO_CREDIT_MASK 0x3ff
-#define TCP_CREDIT__LFIFO_CREDIT__SHIFT 0x0
-#define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x7f0000
-#define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x10
-#define TCP_CREDIT__TD_CREDIT_MASK 0xe0000000
-#define TCP_CREDIT__TD_CREDIT__SHIFT 0x1d
-#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
-#define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
-#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
-#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
-#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
-#define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
-#define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
-#define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
-#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
-#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
-#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
-#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
-#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
-#define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
-#define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
-#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
-#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
-#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
-#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
-#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
-#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
-#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
-#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
-#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000
-#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
-#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000
-#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
-#define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
-#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
-#define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
-#define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
-#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
-#define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
-#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
-#define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
-#define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
-#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK 0x7
-#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT 0x0
-#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK 0x700
-#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT 0x8
-#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK 0x70000
-#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT 0x10
-#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK 0x7000000
-#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT 0x18
-#define TCP_EDC_CNT__SEC_COUNT_MASK 0xff
-#define TCP_EDC_CNT__SEC_COUNT__SHIFT 0x0
-#define TCP_EDC_CNT__LFIFO_SED_COUNT_MASK 0xff00
-#define TCP_EDC_CNT__LFIFO_SED_COUNT__SHIFT 0x8
-#define TCP_EDC_CNT__DED_COUNT_MASK 0xff0000
-#define TCP_EDC_CNT__DED_COUNT__SHIFT 0x10
-#define TCP_EDC_CNT__UNUSED_MASK 0xff000000
-#define TCP_EDC_CNT__UNUSED__SHIFT 0x18
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK 0x3
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT 0x0
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK 0xc
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT 0x2
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK 0x30
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT 0x4
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK 0xc0
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT 0x6
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK 0x300
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT 0x8
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK 0xc00
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT 0xa
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK 0x3000
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT 0xc
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK 0xc000
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT 0xe
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK 0x30000
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT 0x10
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK 0xc0000
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT 0x12
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK 0x300000
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT 0x14
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK 0xc00000
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT 0x16
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK 0x3000000
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT 0x18
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK 0xc000000
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT 0x1a
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK 0x30000000
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT 0x1c
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK 0xc0000000
-#define TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT 0x1e
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK 0x3
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT 0x0
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK 0xc
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT 0x2
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK 0x30
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT 0x4
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK 0xc0
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT 0x6
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK 0x300
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT 0x8
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK 0xc00
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT 0xa
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK 0x3000
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT 0xc
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK 0xc000
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT 0xe
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK 0x30000
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT 0x10
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK 0xc0000
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT 0x12
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK 0x300000
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT 0x14
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK 0xc00000
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT 0x16
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK 0x3000000
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT 0x18
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK 0xc000000
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT 0x1a
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK 0x30000000
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT 0x1c
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK 0xc0000000
-#define TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT 0x1e
-#define TC_CFG_L1_STORE_POLICY__POLICY_0_MASK 0x1
-#define TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT 0x0
-#define TC_CFG_L1_STORE_POLICY__POLICY_1_MASK 0x2
-#define TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT 0x1
-#define TC_CFG_L1_STORE_POLICY__POLICY_2_MASK 0x4
-#define TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT 0x2
-#define TC_CFG_L1_STORE_POLICY__POLICY_3_MASK 0x8
-#define TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT 0x3
-#define TC_CFG_L1_STORE_POLICY__POLICY_4_MASK 0x10
-#define TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT 0x4
-#define TC_CFG_L1_STORE_POLICY__POLICY_5_MASK 0x20
-#define TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT 0x5
-#define TC_CFG_L1_STORE_POLICY__POLICY_6_MASK 0x40
-#define TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT 0x6
-#define TC_CFG_L1_STORE_POLICY__POLICY_7_MASK 0x80
-#define TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT 0x7
-#define TC_CFG_L1_STORE_POLICY__POLICY_8_MASK 0x100
-#define TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT 0x8
-#define TC_CFG_L1_STORE_POLICY__POLICY_9_MASK 0x200
-#define TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT 0x9
-#define TC_CFG_L1_STORE_POLICY__POLICY_10_MASK 0x400
-#define TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT 0xa
-#define TC_CFG_L1_STORE_POLICY__POLICY_11_MASK 0x800
-#define TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT 0xb
-#define TC_CFG_L1_STORE_POLICY__POLICY_12_MASK 0x1000
-#define TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT 0xc
-#define TC_CFG_L1_STORE_POLICY__POLICY_13_MASK 0x2000
-#define TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT 0xd
-#define TC_CFG_L1_STORE_POLICY__POLICY_14_MASK 0x4000
-#define TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT 0xe
-#define TC_CFG_L1_STORE_POLICY__POLICY_15_MASK 0x8000
-#define TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT 0xf
-#define TC_CFG_L1_STORE_POLICY__POLICY_16_MASK 0x10000
-#define TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT 0x10
-#define TC_CFG_L1_STORE_POLICY__POLICY_17_MASK 0x20000
-#define TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT 0x11
-#define TC_CFG_L1_STORE_POLICY__POLICY_18_MASK 0x40000
-#define TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT 0x12
-#define TC_CFG_L1_STORE_POLICY__POLICY_19_MASK 0x80000
-#define TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT 0x13
-#define TC_CFG_L1_STORE_POLICY__POLICY_20_MASK 0x100000
-#define TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT 0x14
-#define TC_CFG_L1_STORE_POLICY__POLICY_21_MASK 0x200000
-#define TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT 0x15
-#define TC_CFG_L1_STORE_POLICY__POLICY_22_MASK 0x400000
-#define TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT 0x16
-#define TC_CFG_L1_STORE_POLICY__POLICY_23_MASK 0x800000
-#define TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT 0x17
-#define TC_CFG_L1_STORE_POLICY__POLICY_24_MASK 0x1000000
-#define TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT 0x18
-#define TC_CFG_L1_STORE_POLICY__POLICY_25_MASK 0x2000000
-#define TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT 0x19
-#define TC_CFG_L1_STORE_POLICY__POLICY_26_MASK 0x4000000
-#define TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT 0x1a
-#define TC_CFG_L1_STORE_POLICY__POLICY_27_MASK 0x8000000
-#define TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT 0x1b
-#define TC_CFG_L1_STORE_POLICY__POLICY_28_MASK 0x10000000
-#define TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT 0x1c
-#define TC_CFG_L1_STORE_POLICY__POLICY_29_MASK 0x20000000
-#define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT 0x1d
-#define TC_CFG_L1_STORE_POLICY__POLICY_30_MASK 0x40000000
-#define TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT 0x1e
-#define TC_CFG_L1_STORE_POLICY__POLICY_31_MASK 0x80000000
-#define TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT 0x1f
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK 0x3
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT 0x0
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK 0xc
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT 0x2
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK 0x30
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT 0x4
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK 0xc0
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT 0x6
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK 0x300
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT 0x8
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK 0xc00
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT 0xa
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK 0x3000
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT 0xc
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK 0xc000
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT 0xe
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK 0x30000
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT 0x10
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK 0xc0000
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT 0x12
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK 0x300000
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT 0x14
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK 0xc00000
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT 0x16
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK 0x3000000
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT 0x18
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK 0xc000000
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT 0x1a
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK 0x30000000
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT 0x1c
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK 0xc0000000
-#define TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT 0x1e
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK 0x3
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT 0x0
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK 0xc
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT 0x2
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK 0x30
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT 0x4
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK 0xc0
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT 0x6
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK 0x300
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT 0x8
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK 0xc00
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT 0xa
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK 0x3000
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT 0xc
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK 0xc000
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT 0xe
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK 0x30000
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT 0x10
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK 0xc0000
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT 0x12
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK 0x300000
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT 0x14
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK 0xc00000
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT 0x16
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK 0x3000000
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT 0x18
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK 0xc000000
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT 0x1a
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK 0x30000000
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT 0x1c
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK 0xc0000000
-#define TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT 0x1e
-#define TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK 0x3
-#define TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT 0x0
-#define TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK 0xc
-#define TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT 0x2
-#define TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK 0x30
-#define TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT 0x4
-#define TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK 0xc0
-#define TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT 0x6
-#define TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK 0x300
-#define TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT 0x8
-#define TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK 0xc00
-#define TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT 0xa
-#define TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK 0x3000
-#define TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT 0xc
-#define TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK 0xc000
-#define TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT 0xe
-#define TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK 0x30000
-#define TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT 0x10
-#define TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK 0xc0000
-#define TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT 0x12
-#define TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK 0x300000
-#define TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT 0x14
-#define TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK 0xc00000
-#define TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT 0x16
-#define TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK 0x3000000
-#define TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT 0x18
-#define TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK 0xc000000
-#define TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT 0x1a
-#define TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK 0x30000000
-#define TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT 0x1c
-#define TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK 0xc0000000
-#define TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT 0x1e
-#define TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK 0x3
-#define TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT 0x0
-#define TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK 0xc
-#define TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT 0x2
-#define TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK 0x30
-#define TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT 0x4
-#define TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK 0xc0
-#define TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT 0x6
-#define TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK 0x300
-#define TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT 0x8
-#define TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK 0xc00
-#define TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT 0xa
-#define TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK 0x3000
-#define TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT 0xc
-#define TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK 0xc000
-#define TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT 0xe
-#define TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK 0x30000
-#define TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT 0x10
-#define TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK 0xc0000
-#define TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT 0x12
-#define TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK 0x300000
-#define TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT 0x14
-#define TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK 0xc00000
-#define TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT 0x16
-#define TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK 0x3000000
-#define TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT 0x18
-#define TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK 0xc000000
-#define TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT 0x1a
-#define TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK 0x30000000
-#define TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT 0x1c
-#define TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK 0xc0000000
-#define TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT 0x1e
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK 0x3
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT 0x0
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK 0xc
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT 0x2
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK 0x30
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT 0x4
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK 0xc0
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT 0x6
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK 0x300
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT 0x8
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK 0xc00
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT 0xa
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK 0x3000
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT 0xc
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK 0xc000
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT 0xe
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK 0x30000
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT 0x10
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK 0xc0000
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT 0x12
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK 0x300000
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT 0x14
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK 0xc00000
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT 0x16
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK 0x3000000
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT 0x18
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK 0xc000000
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT 0x1a
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK 0x30000000
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT 0x1c
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK 0xc0000000
-#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT 0x1e
-#define TC_CFG_L1_VOLATILE__VOL_MASK 0xf
-#define TC_CFG_L1_VOLATILE__VOL__SHIFT 0x0
-#define TC_CFG_L2_VOLATILE__VOL_MASK 0xf
-#define TC_CFG_L2_VOLATILE__VOL__SHIFT 0x0
-#define TCP_WATCH0_ADDR_H__ADDR_MASK 0xffff
-#define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x0
-#define TCP_WATCH1_ADDR_H__ADDR_MASK 0xffff
-#define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x0
-#define TCP_WATCH2_ADDR_H__ADDR_MASK 0xffff
-#define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x0
-#define TCP_WATCH3_ADDR_H__ADDR_MASK 0xffff
-#define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x0
-#define TCP_WATCH0_ADDR_L__ADDR_MASK 0xffffffc0
-#define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x6
-#define TCP_WATCH1_ADDR_L__ADDR_MASK 0xffffffc0
-#define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x6
-#define TCP_WATCH2_ADDR_L__ADDR_MASK 0xffffffc0
-#define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x6
-#define TCP_WATCH3_ADDR_L__ADDR_MASK 0xffffffc0
-#define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x6
-#define TCP_WATCH0_CNTL__MASK_MASK 0xffffff
-#define TCP_WATCH0_CNTL__MASK__SHIFT 0x0
-#define TCP_WATCH0_CNTL__VMID_MASK 0xf000000
-#define TCP_WATCH0_CNTL__VMID__SHIFT 0x18
-#define TCP_WATCH0_CNTL__ATC_MASK 0x10000000
-#define TCP_WATCH0_CNTL__ATC__SHIFT 0x1c
-#define TCP_WATCH0_CNTL__MODE_MASK 0x60000000
-#define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d
-#define TCP_WATCH0_CNTL__VALID_MASK 0x80000000
-#define TCP_WATCH0_CNTL__VALID__SHIFT 0x1f
-#define TCP_WATCH1_CNTL__MASK_MASK 0xffffff
-#define TCP_WATCH1_CNTL__MASK__SHIFT 0x0
-#define TCP_WATCH1_CNTL__VMID_MASK 0xf000000
-#define TCP_WATCH1_CNTL__VMID__SHIFT 0x18
-#define TCP_WATCH1_CNTL__ATC_MASK 0x10000000
-#define TCP_WATCH1_CNTL__ATC__SHIFT 0x1c
-#define TCP_WATCH1_CNTL__MODE_MASK 0x60000000
-#define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d
-#define TCP_WATCH1_CNTL__VALID_MASK 0x80000000
-#define TCP_WATCH1_CNTL__VALID__SHIFT 0x1f
-#define TCP_WATCH2_CNTL__MASK_MASK 0xffffff
-#define TCP_WATCH2_CNTL__MASK__SHIFT 0x0
-#define TCP_WATCH2_CNTL__VMID_MASK 0xf000000
-#define TCP_WATCH2_CNTL__VMID__SHIFT 0x18
-#define TCP_WATCH2_CNTL__ATC_MASK 0x10000000
-#define TCP_WATCH2_CNTL__ATC__SHIFT 0x1c
-#define TCP_WATCH2_CNTL__MODE_MASK 0x60000000
-#define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d
-#define TCP_WATCH2_CNTL__VALID_MASK 0x80000000
-#define TCP_WATCH2_CNTL__VALID__SHIFT 0x1f
-#define TCP_WATCH3_CNTL__MASK_MASK 0xffffff
-#define TCP_WATCH3_CNTL__MASK__SHIFT 0x0
-#define TCP_WATCH3_CNTL__VMID_MASK 0xf000000
-#define TCP_WATCH3_CNTL__VMID__SHIFT 0x18
-#define TCP_WATCH3_CNTL__ATC_MASK 0x10000000
-#define TCP_WATCH3_CNTL__ATC__SHIFT 0x1c
-#define TCP_WATCH3_CNTL__MODE_MASK 0x60000000
-#define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d
-#define TCP_WATCH3_CNTL__VALID_MASK 0x80000000
-#define TCP_WATCH3_CNTL__VALID__SHIFT 0x1f
-#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID_MASK 0x2000000
-#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID__SHIFT 0x19
-#define TCP_GATCL1_CNTL__FORCE_MISS_MASK 0x4000000
-#define TCP_GATCL1_CNTL__FORCE_MISS__SHIFT 0x1a
-#define TCP_GATCL1_CNTL__FORCE_IN_ORDER_MASK 0x8000000
-#define TCP_GATCL1_CNTL__FORCE_IN_ORDER__SHIFT 0x1b
-#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000
-#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
-#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2_MASK 0xc0000000
-#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
-#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC_MASK 0xff
-#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC__SHIFT 0x0
-#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0_MASK 0x1
-#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0__SHIFT 0x0
-#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1_MASK 0x2
-#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1__SHIFT 0x1
-#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A_MASK 0x4
-#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A__SHIFT 0x2
-#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL_MASK 0x3
-#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0
-#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x4
-#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2
-#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL_MASK 0x18
-#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL__SHIFT 0x3
-#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x20
-#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x5
-#define TCP_CNTL2__LS_DISABLE_CLOCKS_MASK 0xff
-#define TCP_CNTL2__LS_DISABLE_CLOCKS__SHIFT 0x0
-#define TD_CGTT_CTRL__ON_DELAY_MASK 0xf
-#define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x0
-#define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0xff0
-#define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
-#define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
-#define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
-#define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
-#define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
-#define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
-#define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
-#define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
-#define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
-#define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
-#define TA_CGTT_CTRL__ON_DELAY_MASK 0xf
-#define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x0
-#define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0xff0
-#define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
-#define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
-#define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
-#define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
-#define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
-#define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
-#define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
-#define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
-#define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
-#define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
-#define CGTT_TCP_CLK_CTRL__ON_DELAY_MASK 0xf
-#define CGTT_TCP_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
-#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
-#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
-#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
-#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
-#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
-#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
-#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
-#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
-#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
-#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
-#define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0xf
-#define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
-#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
-#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
-#define TCI_STATUS__TCI_BUSY_MASK 0x1
-#define TCI_STATUS__TCI_BUSY__SHIFT 0x0
-#define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0xffff
-#define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x0
-#define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0xff0000
-#define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x10
-#define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xff000000
-#define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x18
-#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x1
-#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x0
-#define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x1fe
-#define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x1
-#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x6
-#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x1
-#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x18
-#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3
-#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x60
-#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5
-#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x180
-#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x7
-#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x1
-#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0
-#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x2
-#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1
-#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x4
-#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2
-#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x8
-#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x3
-#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x10
-#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x4
-#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x20
-#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5
-#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x40
-#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x6
-#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK 0x80
-#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT 0x7
-#define GDS_CNTL_STATUS__DS_BUSY_MASK 0x100
-#define GDS_CNTL_STATUS__DS_BUSY__SHIFT 0x8
-#define GDS_CNTL_STATUS__GWS_BUSY_MASK 0x200
-#define GDS_CNTL_STATUS__GWS_BUSY__SHIFT 0x9
-#define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK 0x400
-#define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0xa
-#define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK 0x800
-#define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT 0xb
-#define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK 0x1000
-#define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT 0xc
-#define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK 0x2000
-#define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT 0xd
-#define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK 0x4000
-#define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT 0xe
-#define GDS_ENHANCE2__MISC_MASK 0xffff
-#define GDS_ENHANCE2__MISC__SHIFT 0x0
-#define GDS_ENHANCE2__UNUSED_MASK 0xffff0000
-#define GDS_ENHANCE2__UNUSED__SHIFT 0x10
-#define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x1
-#define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0
-#define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x2
-#define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1
-#define GDS_PROTECTION_FAULT__GRBM_MASK 0x4
-#define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2
-#define GDS_PROTECTION_FAULT__SH_ID_MASK 0x38
-#define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x3
-#define GDS_PROTECTION_FAULT__CU_ID_MASK 0x3c0
-#define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x6
-#define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0xc00
-#define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa
-#define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0xf000
-#define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xc
-#define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xffff0000
-#define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x10
-#define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x1
-#define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0
-#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x2
-#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1
-#define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x4
-#define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2
-#define GDS_VM_PROTECTION_FAULT__OA_MASK 0x8
-#define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3
-#define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x10
-#define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4
-#define GDS_VM_PROTECTION_FAULT__VMID_MASK 0xf00
-#define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8
-#define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xffff0000
-#define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10
-#define GDS_EDC_CNT__DED_MASK 0xff
-#define GDS_EDC_CNT__DED__SHIFT 0x0
-#define GDS_EDC_CNT__SED_MASK 0xff00
-#define GDS_EDC_CNT__SED__SHIFT 0x8
-#define GDS_EDC_CNT__SEC_MASK 0xff0000
-#define GDS_EDC_CNT__SEC__SHIFT 0x10
-#define GDS_EDC_GRBM_CNT__DED_MASK 0xff
-#define GDS_EDC_GRBM_CNT__DED__SHIFT 0x0
-#define GDS_EDC_GRBM_CNT__SEC_MASK 0xff0000
-#define GDS_EDC_GRBM_CNT__SEC__SHIFT 0x10
-#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x1
-#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0
-#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x2
-#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1
-#define GDS_EDC_OA_DED__ME0_CS_DED_MASK 0x4
-#define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT 0x2
-#define GDS_EDC_OA_DED__UNUSED0_MASK 0x8
-#define GDS_EDC_OA_DED__UNUSED0__SHIFT 0x3
-#define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK 0x10
-#define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT 0x4
-#define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK 0x20
-#define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT 0x5
-#define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK 0x40
-#define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT 0x6
-#define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK 0x80
-#define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT 0x7
-#define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK 0x100
-#define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT 0x8
-#define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK 0x200
-#define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT 0x9
-#define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK 0x400
-#define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT 0xa
-#define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK 0x800
-#define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT 0xb
-#define GDS_EDC_OA_DED__UNUSED1_MASK 0xfffff000
-#define GDS_EDC_OA_DED__UNUSED1__SHIFT 0xc
-#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX_MASK 0x1f
-#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX__SHIFT 0x0
-#define GDS_DEBUG_CNTL__UNUSED_MASK 0xffffffe0
-#define GDS_DEBUG_CNTL__UNUSED__SHIFT 0x5
-#define GDS_DEBUG_DATA__DATA_MASK 0xffffffff
-#define GDS_DEBUG_DATA__DATA__SHIFT 0x0
-#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_0_MASK 0x1
-#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_0__SHIFT 0x0
-#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_1_MASK 0x2
-#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_1__SHIFT 0x1
-#define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_A_MASK 0x4
-#define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_A__SHIFT 0x2
-#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_0_MASK 0x8
-#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_0__SHIFT 0x3
-#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_1_MASK 0x10
-#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_1__SHIFT 0x4
-#define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_B_MASK 0x20
-#define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_B__SHIFT 0x5
-#define GDS_DSM_CNTL__UNUSED_MASK 0xffffffc0
-#define GDS_DSM_CNTL__UNUSED__SHIFT 0x6
-#define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0xf
-#define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
-#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
-#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
-#define GDS_RD_ADDR__READ_ADDR_MASK 0xffffffff
-#define GDS_RD_ADDR__READ_ADDR__SHIFT 0x0
-#define GDS_RD_DATA__READ_DATA_MASK 0xffffffff
-#define GDS_RD_DATA__READ_DATA__SHIFT 0x0
-#define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xffffffff
-#define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x0
-#define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xffffffff
-#define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x0
-#define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xffffffff
-#define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x0
-#define GDS_WR_ADDR__WRITE_ADDR_MASK 0xffffffff
-#define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x0
-#define GDS_WR_DATA__WRITE_DATA_MASK 0xffffffff
-#define GDS_WR_DATA__WRITE_DATA__SHIFT 0x0
-#define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xffffffff
-#define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x0
-#define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xffffffff
-#define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x0
-#define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xffffffff
-#define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x0
-#define GDS_ATOM_CNTL__AINC_MASK 0x3f
-#define GDS_ATOM_CNTL__AINC__SHIFT 0x0
-#define GDS_ATOM_CNTL__UNUSED1_MASK 0xc0
-#define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x6
-#define GDS_ATOM_CNTL__DMODE_MASK 0x300
-#define GDS_ATOM_CNTL__DMODE__SHIFT 0x8
-#define GDS_ATOM_CNTL__UNUSED2_MASK 0xfffffc00
-#define GDS_ATOM_CNTL__UNUSED2__SHIFT 0xa
-#define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x1
-#define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x0
-#define GDS_ATOM_COMPLETE__UNUSED_MASK 0xfffffffe
-#define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x1
-#define GDS_ATOM_BASE__BASE_MASK 0xffff
-#define GDS_ATOM_BASE__BASE__SHIFT 0x0
-#define GDS_ATOM_BASE__UNUSED_MASK 0xffff0000
-#define GDS_ATOM_BASE__UNUSED__SHIFT 0x10
-#define GDS_ATOM_SIZE__SIZE_MASK 0xffff
-#define GDS_ATOM_SIZE__SIZE__SHIFT 0x0
-#define GDS_ATOM_SIZE__UNUSED_MASK 0xffff0000
-#define GDS_ATOM_SIZE__UNUSED__SHIFT 0x10
-#define GDS_ATOM_OFFSET0__OFFSET0_MASK 0xff
-#define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x0
-#define GDS_ATOM_OFFSET0__UNUSED_MASK 0xffffff00
-#define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x8
-#define GDS_ATOM_OFFSET1__OFFSET1_MASK 0xff
-#define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x0
-#define GDS_ATOM_OFFSET1__UNUSED_MASK 0xffffff00
-#define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x8
-#define GDS_ATOM_DST__DST_MASK 0xffffffff
-#define GDS_ATOM_DST__DST__SHIFT 0x0
-#define GDS_ATOM_OP__OP_MASK 0xff
-#define GDS_ATOM_OP__OP__SHIFT 0x0
-#define GDS_ATOM_OP__UNUSED_MASK 0xffffff00
-#define GDS_ATOM_OP__UNUSED__SHIFT 0x8
-#define GDS_ATOM_SRC0__DATA_MASK 0xffffffff
-#define GDS_ATOM_SRC0__DATA__SHIFT 0x0
-#define GDS_ATOM_SRC0_U__DATA_MASK 0xffffffff
-#define GDS_ATOM_SRC0_U__DATA__SHIFT 0x0
-#define GDS_ATOM_SRC1__DATA_MASK 0xffffffff
-#define GDS_ATOM_SRC1__DATA__SHIFT 0x0
-#define GDS_ATOM_SRC1_U__DATA_MASK 0xffffffff
-#define GDS_ATOM_SRC1_U__DATA__SHIFT 0x0
-#define GDS_ATOM_READ0__DATA_MASK 0xffffffff
-#define GDS_ATOM_READ0__DATA__SHIFT 0x0
-#define GDS_ATOM_READ0_U__DATA_MASK 0xffffffff
-#define GDS_ATOM_READ0_U__DATA__SHIFT 0x0
-#define GDS_ATOM_READ1__DATA_MASK 0xffffffff
-#define GDS_ATOM_READ1__DATA__SHIFT 0x0
-#define GDS_ATOM_READ1_U__DATA_MASK 0xffffffff
-#define GDS_ATOM_READ1_U__DATA__SHIFT 0x0
-#define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x3f
-#define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x0
-#define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xffffffc0
-#define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x6
-#define GDS_GWS_RESOURCE__FLAG_MASK 0x1
-#define GDS_GWS_RESOURCE__FLAG__SHIFT 0x0
-#define GDS_GWS_RESOURCE__COUNTER_MASK 0x1ffe
-#define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x1
-#define GDS_GWS_RESOURCE__TYPE_MASK 0x2000
-#define GDS_GWS_RESOURCE__TYPE__SHIFT 0xd
-#define GDS_GWS_RESOURCE__DED_MASK 0x4000
-#define GDS_GWS_RESOURCE__DED__SHIFT 0xe
-#define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x8000
-#define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0xf
-#define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0xfff0000
-#define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x10
-#define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x10000000
-#define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x1c
-#define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x20000000
-#define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x1d
-#define GDS_GWS_RESOURCE__UNUSED1_MASK 0xc0000000
-#define GDS_GWS_RESOURCE__UNUSED1__SHIFT 0x1e
-#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0xffff
-#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x0
-#define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xffff0000
-#define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x10
-#define GDS_OA_CNTL__INDEX_MASK 0xf
-#define GDS_OA_CNTL__INDEX__SHIFT 0x0
-#define GDS_OA_CNTL__UNUSED_MASK 0xfffffff0
-#define GDS_OA_CNTL__UNUSED__SHIFT 0x4
-#define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK 0xffffffff
-#define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT 0x0
-#define GDS_OA_ADDRESS__DS_ADDRESS_MASK 0xffff
-#define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT 0x0
-#define GDS_OA_ADDRESS__CRAWLER_MASK 0xf0000
-#define GDS_OA_ADDRESS__CRAWLER__SHIFT 0x10
-#define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK 0x300000
-#define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT 0x14
-#define GDS_OA_ADDRESS__UNUSED_MASK 0x3fc00000
-#define GDS_OA_ADDRESS__UNUSED__SHIFT 0x16
-#define GDS_OA_ADDRESS__NO_ALLOC_MASK 0x40000000
-#define GDS_OA_ADDRESS__NO_ALLOC__SHIFT 0x1e
-#define GDS_OA_ADDRESS__ENABLE_MASK 0x80000000
-#define GDS_OA_ADDRESS__ENABLE__SHIFT 0x1f
-#define GDS_OA_INCDEC__VALUE_MASK 0x7fffffff
-#define GDS_OA_INCDEC__VALUE__SHIFT 0x0
-#define GDS_OA_INCDEC__INCDEC_MASK 0x80000000
-#define GDS_OA_INCDEC__INCDEC__SHIFT 0x1f
-#define GDS_OA_RING_SIZE__RING_SIZE_MASK 0xffffffff
-#define GDS_OA_RING_SIZE__RING_SIZE__SHIFT 0x0
-#define GDS_DEBUG_REG0__spare1_MASK 0x3f
-#define GDS_DEBUG_REG0__spare1__SHIFT 0x0
-#define GDS_DEBUG_REG0__write_buff_valid_MASK 0x40
-#define GDS_DEBUG_REG0__write_buff_valid__SHIFT 0x6
-#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr_MASK 0xf80
-#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr__SHIFT 0x7
-#define GDS_DEBUG_REG0__last_pixel_ptr_MASK 0x1000
-#define GDS_DEBUG_REG0__last_pixel_ptr__SHIFT 0xc
-#define GDS_DEBUG_REG0__cstate_MASK 0x1e000
-#define GDS_DEBUG_REG0__cstate__SHIFT 0xd
-#define GDS_DEBUG_REG0__buff_write_MASK 0x20000
-#define GDS_DEBUG_REG0__buff_write__SHIFT 0x11
-#define GDS_DEBUG_REG0__flush_request_MASK 0x40000
-#define GDS_DEBUG_REG0__flush_request__SHIFT 0x12
-#define GDS_DEBUG_REG0__wr_buffer_wr_complete_MASK 0x80000
-#define GDS_DEBUG_REG0__wr_buffer_wr_complete__SHIFT 0x13
-#define GDS_DEBUG_REG0__wbuf_fifo_empty_MASK 0x100000
-#define GDS_DEBUG_REG0__wbuf_fifo_empty__SHIFT 0x14
-#define GDS_DEBUG_REG0__wbuf_fifo_full_MASK 0x200000
-#define GDS_DEBUG_REG0__wbuf_fifo_full__SHIFT 0x15
-#define GDS_DEBUG_REG0__spare_MASK 0xffc00000
-#define GDS_DEBUG_REG0__spare__SHIFT 0x16
-#define GDS_DEBUG_REG1__tag_hit_MASK 0x1
-#define GDS_DEBUG_REG1__tag_hit__SHIFT 0x0
-#define GDS_DEBUG_REG1__tag_miss_MASK 0x2
-#define GDS_DEBUG_REG1__tag_miss__SHIFT 0x1
-#define GDS_DEBUG_REG1__pixel_addr_MASK 0x1fffc
-#define GDS_DEBUG_REG1__pixel_addr__SHIFT 0x2
-#define GDS_DEBUG_REG1__pixel_vld_MASK 0x20000
-#define GDS_DEBUG_REG1__pixel_vld__SHIFT 0x11
-#define GDS_DEBUG_REG1__data_ready_MASK 0x40000
-#define GDS_DEBUG_REG1__data_ready__SHIFT 0x12
-#define GDS_DEBUG_REG1__awaiting_data_MASK 0x80000
-#define GDS_DEBUG_REG1__awaiting_data__SHIFT 0x13
-#define GDS_DEBUG_REG1__addr_fifo_full_MASK 0x100000
-#define GDS_DEBUG_REG1__addr_fifo_full__SHIFT 0x14
-#define GDS_DEBUG_REG1__addr_fifo_empty_MASK 0x200000
-#define GDS_DEBUG_REG1__addr_fifo_empty__SHIFT 0x15
-#define GDS_DEBUG_REG1__buffer_loaded_MASK 0x400000
-#define GDS_DEBUG_REG1__buffer_loaded__SHIFT 0x16
-#define GDS_DEBUG_REG1__buffer_invalid_MASK 0x800000
-#define GDS_DEBUG_REG1__buffer_invalid__SHIFT 0x17
-#define GDS_DEBUG_REG1__spare_MASK 0xff000000
-#define GDS_DEBUG_REG1__spare__SHIFT 0x18
-#define GDS_DEBUG_REG2__ds_full_MASK 0x1
-#define GDS_DEBUG_REG2__ds_full__SHIFT 0x0
-#define GDS_DEBUG_REG2__ds_credit_avail_MASK 0x2
-#define GDS_DEBUG_REG2__ds_credit_avail__SHIFT 0x1
-#define GDS_DEBUG_REG2__ord_idx_free_MASK 0x4
-#define GDS_DEBUG_REG2__ord_idx_free__SHIFT 0x2
-#define GDS_DEBUG_REG2__cmd_write_MASK 0x8
-#define GDS_DEBUG_REG2__cmd_write__SHIFT 0x3
-#define GDS_DEBUG_REG2__app_sel_MASK 0xf0
-#define GDS_DEBUG_REG2__app_sel__SHIFT 0x4
-#define GDS_DEBUG_REG2__req_MASK 0x7fff00
-#define GDS_DEBUG_REG2__req__SHIFT 0x8
-#define GDS_DEBUG_REG2__spare_MASK 0xff800000
-#define GDS_DEBUG_REG2__spare__SHIFT 0x17
-#define GDS_DEBUG_REG3__pipe_num_busy_MASK 0x7ff
-#define GDS_DEBUG_REG3__pipe_num_busy__SHIFT 0x0
-#define GDS_DEBUG_REG3__pipe0_busy_num_MASK 0x7800
-#define GDS_DEBUG_REG3__pipe0_busy_num__SHIFT 0xb
-#define GDS_DEBUG_REG3__spare_MASK 0xffff8000
-#define GDS_DEBUG_REG3__spare__SHIFT 0xf
-#define GDS_DEBUG_REG4__gws_busy_MASK 0x1
-#define GDS_DEBUG_REG4__gws_busy__SHIFT 0x0
-#define GDS_DEBUG_REG4__gws_req_MASK 0x2
-#define GDS_DEBUG_REG4__gws_req__SHIFT 0x1
-#define GDS_DEBUG_REG4__gws_out_stall_MASK 0x4
-#define GDS_DEBUG_REG4__gws_out_stall__SHIFT 0x2
-#define GDS_DEBUG_REG4__cur_reso_MASK 0x1f8
-#define GDS_DEBUG_REG4__cur_reso__SHIFT 0x3
-#define GDS_DEBUG_REG4__cur_reso_head_valid_MASK 0x200
-#define GDS_DEBUG_REG4__cur_reso_head_valid__SHIFT 0x9
-#define GDS_DEBUG_REG4__cur_reso_head_dirty_MASK 0x400
-#define GDS_DEBUG_REG4__cur_reso_head_dirty__SHIFT 0xa
-#define GDS_DEBUG_REG4__cur_reso_head_flag_MASK 0x800
-#define GDS_DEBUG_REG4__cur_reso_head_flag__SHIFT 0xb
-#define GDS_DEBUG_REG4__cur_reso_fed_MASK 0x1000
-#define GDS_DEBUG_REG4__cur_reso_fed__SHIFT 0xc
-#define GDS_DEBUG_REG4__cur_reso_barrier_MASK 0x2000
-#define GDS_DEBUG_REG4__cur_reso_barrier__SHIFT 0xd
-#define GDS_DEBUG_REG4__cur_reso_flag_MASK 0x4000
-#define GDS_DEBUG_REG4__cur_reso_flag__SHIFT 0xe
-#define GDS_DEBUG_REG4__cur_reso_cnt_gt0_MASK 0x8000
-#define GDS_DEBUG_REG4__cur_reso_cnt_gt0__SHIFT 0xf
-#define GDS_DEBUG_REG4__credit_cnt_gt0_MASK 0x10000
-#define GDS_DEBUG_REG4__credit_cnt_gt0__SHIFT 0x10
-#define GDS_DEBUG_REG4__cmd_write_MASK 0x20000
-#define GDS_DEBUG_REG4__cmd_write__SHIFT 0x11
-#define GDS_DEBUG_REG4__grbm_gws_reso_wr_MASK 0x40000
-#define GDS_DEBUG_REG4__grbm_gws_reso_wr__SHIFT 0x12
-#define GDS_DEBUG_REG4__grbm_gws_reso_rd_MASK 0x80000
-#define GDS_DEBUG_REG4__grbm_gws_reso_rd__SHIFT 0x13
-#define GDS_DEBUG_REG4__ram_read_busy_MASK 0x100000
-#define GDS_DEBUG_REG4__ram_read_busy__SHIFT 0x14
-#define GDS_DEBUG_REG4__gws_bulkfree_MASK 0x200000
-#define GDS_DEBUG_REG4__gws_bulkfree__SHIFT 0x15
-#define GDS_DEBUG_REG4__ram_gws_re_MASK 0x400000
-#define GDS_DEBUG_REG4__ram_gws_re__SHIFT 0x16
-#define GDS_DEBUG_REG4__ram_gws_we_MASK 0x800000
-#define GDS_DEBUG_REG4__ram_gws_we__SHIFT 0x17
-#define GDS_DEBUG_REG4__spare_MASK 0xff000000
-#define GDS_DEBUG_REG4__spare__SHIFT 0x18
-#define GDS_DEBUG_REG5__write_dis_MASK 0x1
-#define GDS_DEBUG_REG5__write_dis__SHIFT 0x0
-#define GDS_DEBUG_REG5__dec_error_MASK 0x2
-#define GDS_DEBUG_REG5__dec_error__SHIFT 0x1
-#define GDS_DEBUG_REG5__alloc_opco_error_MASK 0x4
-#define GDS_DEBUG_REG5__alloc_opco_error__SHIFT 0x2
-#define GDS_DEBUG_REG5__dealloc_opco_error_MASK 0x8
-#define GDS_DEBUG_REG5__dealloc_opco_error__SHIFT 0x3
-#define GDS_DEBUG_REG5__wrap_opco_error_MASK 0x10
-#define GDS_DEBUG_REG5__wrap_opco_error__SHIFT 0x4
-#define GDS_DEBUG_REG5__spare_MASK 0xe0
-#define GDS_DEBUG_REG5__spare__SHIFT 0x5
-#define GDS_DEBUG_REG5__error_ds_address_MASK 0x3fff00
-#define GDS_DEBUG_REG5__error_ds_address__SHIFT 0x8
-#define GDS_DEBUG_REG5__spare1_MASK 0xffc00000
-#define GDS_DEBUG_REG5__spare1__SHIFT 0x16
-#define GDS_DEBUG_REG6__oa_busy_MASK 0x1
-#define GDS_DEBUG_REG6__oa_busy__SHIFT 0x0
-#define GDS_DEBUG_REG6__counters_enabled_MASK 0x1e
-#define GDS_DEBUG_REG6__counters_enabled__SHIFT 0x1
-#define GDS_DEBUG_REG6__counters_busy_MASK 0x1fffe0
-#define GDS_DEBUG_REG6__counters_busy__SHIFT 0x5
-#define GDS_DEBUG_REG6__spare_MASK 0xffe00000
-#define GDS_DEBUG_REG6__spare__SHIFT 0x15
-#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
-#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
-#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
-#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
-#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
-#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
-#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
-#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
-#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
-#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
-#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
-#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
-#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
-#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
-#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
-#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
-#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
-#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
-#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
-#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
-#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
-#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
-#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
-#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff
-#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
-#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00
-#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
-#define GDS_VMID0_BASE__BASE_MASK 0xffff
-#define GDS_VMID0_BASE__BASE__SHIFT 0x0
-#define GDS_VMID1_BASE__BASE_MASK 0xffff
-#define GDS_VMID1_BASE__BASE__SHIFT 0x0
-#define GDS_VMID2_BASE__BASE_MASK 0xffff
-#define GDS_VMID2_BASE__BASE__SHIFT 0x0
-#define GDS_VMID3_BASE__BASE_MASK 0xffff
-#define GDS_VMID3_BASE__BASE__SHIFT 0x0
-#define GDS_VMID4_BASE__BASE_MASK 0xffff
-#define GDS_VMID4_BASE__BASE__SHIFT 0x0
-#define GDS_VMID5_BASE__BASE_MASK 0xffff
-#define GDS_VMID5_BASE__BASE__SHIFT 0x0
-#define GDS_VMID6_BASE__BASE_MASK 0xffff
-#define GDS_VMID6_BASE__BASE__SHIFT 0x0
-#define GDS_VMID7_BASE__BASE_MASK 0xffff
-#define GDS_VMID7_BASE__BASE__SHIFT 0x0
-#define GDS_VMID8_BASE__BASE_MASK 0xffff
-#define GDS_VMID8_BASE__BASE__SHIFT 0x0
-#define GDS_VMID9_BASE__BASE_MASK 0xffff
-#define GDS_VMID9_BASE__BASE__SHIFT 0x0
-#define GDS_VMID10_BASE__BASE_MASK 0xffff
-#define GDS_VMID10_BASE__BASE__SHIFT 0x0
-#define GDS_VMID11_BASE__BASE_MASK 0xffff
-#define GDS_VMID11_BASE__BASE__SHIFT 0x0
-#define GDS_VMID12_BASE__BASE_MASK 0xffff
-#define GDS_VMID12_BASE__BASE__SHIFT 0x0
-#define GDS_VMID13_BASE__BASE_MASK 0xffff
-#define GDS_VMID13_BASE__BASE__SHIFT 0x0
-#define GDS_VMID14_BASE__BASE_MASK 0xffff
-#define GDS_VMID14_BASE__BASE__SHIFT 0x0
-#define GDS_VMID15_BASE__BASE_MASK 0xffff
-#define GDS_VMID15_BASE__BASE__SHIFT 0x0
-#define GDS_VMID0_SIZE__SIZE_MASK 0x1ffff
-#define GDS_VMID0_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID1_SIZE__SIZE_MASK 0x1ffff
-#define GDS_VMID1_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID2_SIZE__SIZE_MASK 0x1ffff
-#define GDS_VMID2_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID3_SIZE__SIZE_MASK 0x1ffff
-#define GDS_VMID3_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID4_SIZE__SIZE_MASK 0x1ffff
-#define GDS_VMID4_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID5_SIZE__SIZE_MASK 0x1ffff
-#define GDS_VMID5_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID6_SIZE__SIZE_MASK 0x1ffff
-#define GDS_VMID6_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID7_SIZE__SIZE_MASK 0x1ffff
-#define GDS_VMID7_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID8_SIZE__SIZE_MASK 0x1ffff
-#define GDS_VMID8_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID9_SIZE__SIZE_MASK 0x1ffff
-#define GDS_VMID9_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID10_SIZE__SIZE_MASK 0x1ffff
-#define GDS_VMID10_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID11_SIZE__SIZE_MASK 0x1ffff
-#define GDS_VMID11_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID12_SIZE__SIZE_MASK 0x1ffff
-#define GDS_VMID12_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID13_SIZE__SIZE_MASK 0x1ffff
-#define GDS_VMID13_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID14_SIZE__SIZE_MASK 0x1ffff
-#define GDS_VMID14_SIZE__SIZE__SHIFT 0x0
-#define GDS_VMID15_SIZE__SIZE_MASK 0x1ffff
-#define GDS_VMID15_SIZE__SIZE__SHIFT 0x0
-#define GDS_GWS_VMID0__BASE_MASK 0x3f
-#define GDS_GWS_VMID0__BASE__SHIFT 0x0
-#define GDS_GWS_VMID0__SIZE_MASK 0x7f0000
-#define GDS_GWS_VMID0__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID1__BASE_MASK 0x3f
-#define GDS_GWS_VMID1__BASE__SHIFT 0x0
-#define GDS_GWS_VMID1__SIZE_MASK 0x7f0000
-#define GDS_GWS_VMID1__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID2__BASE_MASK 0x3f
-#define GDS_GWS_VMID2__BASE__SHIFT 0x0
-#define GDS_GWS_VMID2__SIZE_MASK 0x7f0000
-#define GDS_GWS_VMID2__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID3__BASE_MASK 0x3f
-#define GDS_GWS_VMID3__BASE__SHIFT 0x0
-#define GDS_GWS_VMID3__SIZE_MASK 0x7f0000
-#define GDS_GWS_VMID3__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID4__BASE_MASK 0x3f
-#define GDS_GWS_VMID4__BASE__SHIFT 0x0
-#define GDS_GWS_VMID4__SIZE_MASK 0x7f0000
-#define GDS_GWS_VMID4__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID5__BASE_MASK 0x3f
-#define GDS_GWS_VMID5__BASE__SHIFT 0x0
-#define GDS_GWS_VMID5__SIZE_MASK 0x7f0000
-#define GDS_GWS_VMID5__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID6__BASE_MASK 0x3f
-#define GDS_GWS_VMID6__BASE__SHIFT 0x0
-#define GDS_GWS_VMID6__SIZE_MASK 0x7f0000
-#define GDS_GWS_VMID6__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID7__BASE_MASK 0x3f
-#define GDS_GWS_VMID7__BASE__SHIFT 0x0
-#define GDS_GWS_VMID7__SIZE_MASK 0x7f0000
-#define GDS_GWS_VMID7__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID8__BASE_MASK 0x3f
-#define GDS_GWS_VMID8__BASE__SHIFT 0x0
-#define GDS_GWS_VMID8__SIZE_MASK 0x7f0000
-#define GDS_GWS_VMID8__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID9__BASE_MASK 0x3f
-#define GDS_GWS_VMID9__BASE__SHIFT 0x0
-#define GDS_GWS_VMID9__SIZE_MASK 0x7f0000
-#define GDS_GWS_VMID9__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID10__BASE_MASK 0x3f
-#define GDS_GWS_VMID10__BASE__SHIFT 0x0
-#define GDS_GWS_VMID10__SIZE_MASK 0x7f0000
-#define GDS_GWS_VMID10__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID11__BASE_MASK 0x3f
-#define GDS_GWS_VMID11__BASE__SHIFT 0x0
-#define GDS_GWS_VMID11__SIZE_MASK 0x7f0000
-#define GDS_GWS_VMID11__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID12__BASE_MASK 0x3f
-#define GDS_GWS_VMID12__BASE__SHIFT 0x0
-#define GDS_GWS_VMID12__SIZE_MASK 0x7f0000
-#define GDS_GWS_VMID12__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID13__BASE_MASK 0x3f
-#define GDS_GWS_VMID13__BASE__SHIFT 0x0
-#define GDS_GWS_VMID13__SIZE_MASK 0x7f0000
-#define GDS_GWS_VMID13__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID14__BASE_MASK 0x3f
-#define GDS_GWS_VMID14__BASE__SHIFT 0x0
-#define GDS_GWS_VMID14__SIZE_MASK 0x7f0000
-#define GDS_GWS_VMID14__SIZE__SHIFT 0x10
-#define GDS_GWS_VMID15__BASE_MASK 0x3f
-#define GDS_GWS_VMID15__BASE__SHIFT 0x0
-#define GDS_GWS_VMID15__SIZE_MASK 0x7f0000
-#define GDS_GWS_VMID15__SIZE__SHIFT 0x10
-#define GDS_OA_VMID0__MASK_MASK 0xffff
-#define GDS_OA_VMID0__MASK__SHIFT 0x0
-#define GDS_OA_VMID0__UNUSED_MASK 0xffff0000
-#define GDS_OA_VMID0__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID1__MASK_MASK 0xffff
-#define GDS_OA_VMID1__MASK__SHIFT 0x0
-#define GDS_OA_VMID1__UNUSED_MASK 0xffff0000
-#define GDS_OA_VMID1__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID2__MASK_MASK 0xffff
-#define GDS_OA_VMID2__MASK__SHIFT 0x0
-#define GDS_OA_VMID2__UNUSED_MASK 0xffff0000
-#define GDS_OA_VMID2__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID3__MASK_MASK 0xffff
-#define GDS_OA_VMID3__MASK__SHIFT 0x0
-#define GDS_OA_VMID3__UNUSED_MASK 0xffff0000
-#define GDS_OA_VMID3__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID4__MASK_MASK 0xffff
-#define GDS_OA_VMID4__MASK__SHIFT 0x0
-#define GDS_OA_VMID4__UNUSED_MASK 0xffff0000
-#define GDS_OA_VMID4__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID5__MASK_MASK 0xffff
-#define GDS_OA_VMID5__MASK__SHIFT 0x0
-#define GDS_OA_VMID5__UNUSED_MASK 0xffff0000
-#define GDS_OA_VMID5__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID6__MASK_MASK 0xffff
-#define GDS_OA_VMID6__MASK__SHIFT 0x0
-#define GDS_OA_VMID6__UNUSED_MASK 0xffff0000
-#define GDS_OA_VMID6__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID7__MASK_MASK 0xffff
-#define GDS_OA_VMID7__MASK__SHIFT 0x0
-#define GDS_OA_VMID7__UNUSED_MASK 0xffff0000
-#define GDS_OA_VMID7__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID8__MASK_MASK 0xffff
-#define GDS_OA_VMID8__MASK__SHIFT 0x0
-#define GDS_OA_VMID8__UNUSED_MASK 0xffff0000
-#define GDS_OA_VMID8__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID9__MASK_MASK 0xffff
-#define GDS_OA_VMID9__MASK__SHIFT 0x0
-#define GDS_OA_VMID9__UNUSED_MASK 0xffff0000
-#define GDS_OA_VMID9__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID10__MASK_MASK 0xffff
-#define GDS_OA_VMID10__MASK__SHIFT 0x0
-#define GDS_OA_VMID10__UNUSED_MASK 0xffff0000
-#define GDS_OA_VMID10__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID11__MASK_MASK 0xffff
-#define GDS_OA_VMID11__MASK__SHIFT 0x0
-#define GDS_OA_VMID11__UNUSED_MASK 0xffff0000
-#define GDS_OA_VMID11__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID12__MASK_MASK 0xffff
-#define GDS_OA_VMID12__MASK__SHIFT 0x0
-#define GDS_OA_VMID12__UNUSED_MASK 0xffff0000
-#define GDS_OA_VMID12__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID13__MASK_MASK 0xffff
-#define GDS_OA_VMID13__MASK__SHIFT 0x0
-#define GDS_OA_VMID13__UNUSED_MASK 0xffff0000
-#define GDS_OA_VMID13__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID14__MASK_MASK 0xffff
-#define GDS_OA_VMID14__MASK__SHIFT 0x0
-#define GDS_OA_VMID14__UNUSED_MASK 0xffff0000
-#define GDS_OA_VMID14__UNUSED__SHIFT 0x10
-#define GDS_OA_VMID15__MASK_MASK 0xffff
-#define GDS_OA_VMID15__MASK__SHIFT 0x0
-#define GDS_OA_VMID15__UNUSED_MASK 0xffff0000
-#define GDS_OA_VMID15__UNUSED__SHIFT 0x10
-#define GDS_GWS_RESET0__RESOURCE0_RESET_MASK 0x1
-#define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT 0x0
-#define GDS_GWS_RESET0__RESOURCE1_RESET_MASK 0x2
-#define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT 0x1
-#define GDS_GWS_RESET0__RESOURCE2_RESET_MASK 0x4
-#define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT 0x2
-#define GDS_GWS_RESET0__RESOURCE3_RESET_MASK 0x8
-#define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT 0x3
-#define GDS_GWS_RESET0__RESOURCE4_RESET_MASK 0x10
-#define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT 0x4
-#define GDS_GWS_RESET0__RESOURCE5_RESET_MASK 0x20
-#define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT 0x5
-#define GDS_GWS_RESET0__RESOURCE6_RESET_MASK 0x40
-#define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT 0x6
-#define GDS_GWS_RESET0__RESOURCE7_RESET_MASK 0x80
-#define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT 0x7
-#define GDS_GWS_RESET0__RESOURCE8_RESET_MASK 0x100
-#define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT 0x8
-#define GDS_GWS_RESET0__RESOURCE9_RESET_MASK 0x200
-#define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT 0x9
-#define GDS_GWS_RESET0__RESOURCE10_RESET_MASK 0x400
-#define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa
-#define GDS_GWS_RESET0__RESOURCE11_RESET_MASK 0x800
-#define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT 0xb
-#define GDS_GWS_RESET0__RESOURCE12_RESET_MASK 0x1000
-#define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT 0xc
-#define GDS_GWS_RESET0__RESOURCE13_RESET_MASK 0x2000
-#define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT 0xd
-#define GDS_GWS_RESET0__RESOURCE14_RESET_MASK 0x4000
-#define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT 0xe
-#define GDS_GWS_RESET0__RESOURCE15_RESET_MASK 0x8000
-#define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT 0xf
-#define GDS_GWS_RESET0__RESOURCE16_RESET_MASK 0x10000
-#define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT 0x10
-#define GDS_GWS_RESET0__RESOURCE17_RESET_MASK 0x20000
-#define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT 0x11
-#define GDS_GWS_RESET0__RESOURCE18_RESET_MASK 0x40000
-#define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT 0x12
-#define GDS_GWS_RESET0__RESOURCE19_RESET_MASK 0x80000
-#define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT 0x13
-#define GDS_GWS_RESET0__RESOURCE20_RESET_MASK 0x100000
-#define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT 0x14
-#define GDS_GWS_RESET0__RESOURCE21_RESET_MASK 0x200000
-#define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT 0x15
-#define GDS_GWS_RESET0__RESOURCE22_RESET_MASK 0x400000
-#define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT 0x16
-#define GDS_GWS_RESET0__RESOURCE23_RESET_MASK 0x800000
-#define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT 0x17
-#define GDS_GWS_RESET0__RESOURCE24_RESET_MASK 0x1000000
-#define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT 0x18
-#define GDS_GWS_RESET0__RESOURCE25_RESET_MASK 0x2000000
-#define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT 0x19
-#define GDS_GWS_RESET0__RESOURCE26_RESET_MASK 0x4000000
-#define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT 0x1a
-#define GDS_GWS_RESET0__RESOURCE27_RESET_MASK 0x8000000
-#define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT 0x1b
-#define GDS_GWS_RESET0__RESOURCE28_RESET_MASK 0x10000000
-#define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT 0x1c
-#define GDS_GWS_RESET0__RESOURCE29_RESET_MASK 0x20000000
-#define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d
-#define GDS_GWS_RESET0__RESOURCE30_RESET_MASK 0x40000000
-#define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT 0x1e
-#define GDS_GWS_RESET0__RESOURCE31_RESET_MASK 0x80000000
-#define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT 0x1f
-#define GDS_GWS_RESET1__RESOURCE32_RESET_MASK 0x1
-#define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT 0x0
-#define GDS_GWS_RESET1__RESOURCE33_RESET_MASK 0x2
-#define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT 0x1
-#define GDS_GWS_RESET1__RESOURCE34_RESET_MASK 0x4
-#define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT 0x2
-#define GDS_GWS_RESET1__RESOURCE35_RESET_MASK 0x8
-#define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT 0x3
-#define GDS_GWS_RESET1__RESOURCE36_RESET_MASK 0x10
-#define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT 0x4
-#define GDS_GWS_RESET1__RESOURCE37_RESET_MASK 0x20
-#define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT 0x5
-#define GDS_GWS_RESET1__RESOURCE38_RESET_MASK 0x40
-#define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT 0x6
-#define GDS_GWS_RESET1__RESOURCE39_RESET_MASK 0x80
-#define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT 0x7
-#define GDS_GWS_RESET1__RESOURCE40_RESET_MASK 0x100
-#define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT 0x8
-#define GDS_GWS_RESET1__RESOURCE41_RESET_MASK 0x200
-#define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT 0x9
-#define GDS_GWS_RESET1__RESOURCE42_RESET_MASK 0x400
-#define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa
-#define GDS_GWS_RESET1__RESOURCE43_RESET_MASK 0x800
-#define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT 0xb
-#define GDS_GWS_RESET1__RESOURCE44_RESET_MASK 0x1000
-#define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT 0xc
-#define GDS_GWS_RESET1__RESOURCE45_RESET_MASK 0x2000
-#define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT 0xd
-#define GDS_GWS_RESET1__RESOURCE46_RESET_MASK 0x4000
-#define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT 0xe
-#define GDS_GWS_RESET1__RESOURCE47_RESET_MASK 0x8000
-#define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT 0xf
-#define GDS_GWS_RESET1__RESOURCE48_RESET_MASK 0x10000
-#define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT 0x10
-#define GDS_GWS_RESET1__RESOURCE49_RESET_MASK 0x20000
-#define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT 0x11
-#define GDS_GWS_RESET1__RESOURCE50_RESET_MASK 0x40000
-#define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT 0x12
-#define GDS_GWS_RESET1__RESOURCE51_RESET_MASK 0x80000
-#define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT 0x13
-#define GDS_GWS_RESET1__RESOURCE52_RESET_MASK 0x100000
-#define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT 0x14
-#define GDS_GWS_RESET1__RESOURCE53_RESET_MASK 0x200000
-#define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT 0x15
-#define GDS_GWS_RESET1__RESOURCE54_RESET_MASK 0x400000
-#define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT 0x16
-#define GDS_GWS_RESET1__RESOURCE55_RESET_MASK 0x800000
-#define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT 0x17
-#define GDS_GWS_RESET1__RESOURCE56_RESET_MASK 0x1000000
-#define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT 0x18
-#define GDS_GWS_RESET1__RESOURCE57_RESET_MASK 0x2000000
-#define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT 0x19
-#define GDS_GWS_RESET1__RESOURCE58_RESET_MASK 0x4000000
-#define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT 0x1a
-#define GDS_GWS_RESET1__RESOURCE59_RESET_MASK 0x8000000
-#define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT 0x1b
-#define GDS_GWS_RESET1__RESOURCE60_RESET_MASK 0x10000000
-#define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT 0x1c
-#define GDS_GWS_RESET1__RESOURCE61_RESET_MASK 0x20000000
-#define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d
-#define GDS_GWS_RESET1__RESOURCE62_RESET_MASK 0x40000000
-#define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT 0x1e
-#define GDS_GWS_RESET1__RESOURCE63_RESET_MASK 0x80000000
-#define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT 0x1f
-#define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x1
-#define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x0
-#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0xff00
-#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x8
-#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff
-#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
-#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK 0x1
-#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT 0x0
-#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK 0x2
-#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT 0x1
-#define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK 0x4
-#define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT 0x2
-#define GDS_OA_RESET_MASK__UNUSED0_MASK 0x8
-#define GDS_OA_RESET_MASK__UNUSED0__SHIFT 0x3
-#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK 0x10
-#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT 0x4
-#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK 0x20
-#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT 0x5
-#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK 0x40
-#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT 0x6
-#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK 0x80
-#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT 0x7
-#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK 0x100
-#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT 0x8
-#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK 0x200
-#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT 0x9
-#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK 0x400
-#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa
-#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK 0x800
-#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT 0xb
-#define GDS_OA_RESET_MASK__UNUSED1_MASK 0xfffff000
-#define GDS_OA_RESET_MASK__UNUSED1__SHIFT 0xc
-#define GDS_OA_RESET__RESET_MASK 0x1
-#define GDS_OA_RESET__RESET__SHIFT 0x0
-#define GDS_OA_RESET__PIPE_ID_MASK 0xff00
-#define GDS_OA_RESET__PIPE_ID__SHIFT 0x8
-#define GDS_ENHANCE__MISC_MASK 0xffff
-#define GDS_ENHANCE__MISC__SHIFT 0x0
-#define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x10000
-#define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x10
-#define GDS_ENHANCE__CGPG_RESTORE_MASK 0x20000
-#define GDS_ENHANCE__CGPG_RESTORE__SHIFT 0x11
-#define GDS_ENHANCE__UNUSED_MASK 0xfffc0000
-#define GDS_ENHANCE__UNUSED__SHIFT 0x12
-#define GDS_OA_CGPG_RESTORE__VMID_MASK 0xff
-#define GDS_OA_CGPG_RESTORE__VMID__SHIFT 0x0
-#define GDS_OA_CGPG_RESTORE__MEID_MASK 0xf00
-#define GDS_OA_CGPG_RESTORE__MEID__SHIFT 0x8
-#define GDS_OA_CGPG_RESTORE__PIPEID_MASK 0xf000
-#define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT 0xc
-#define GDS_OA_CGPG_RESTORE__QUEUEID_MASK 0xf0000
-#define GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT 0x10
-#define GDS_OA_CGPG_RESTORE__UNUSED_MASK 0xfff00000
-#define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT 0x14
-#define GDS_CS_CTXSW_STATUS__R_MASK 0x1
-#define GDS_CS_CTXSW_STATUS__R__SHIFT 0x0
-#define GDS_CS_CTXSW_STATUS__W_MASK 0x2
-#define GDS_CS_CTXSW_STATUS__W__SHIFT 0x1
-#define GDS_CS_CTXSW_STATUS__UNUSED_MASK 0xfffffffc
-#define GDS_CS_CTXSW_STATUS__UNUSED__SHIFT 0x2
-#define GDS_CS_CTXSW_CNT0__UPDN_MASK 0xffff
-#define GDS_CS_CTXSW_CNT0__UPDN__SHIFT 0x0
-#define GDS_CS_CTXSW_CNT0__PTR_MASK 0xffff0000
-#define GDS_CS_CTXSW_CNT0__PTR__SHIFT 0x10
-#define GDS_CS_CTXSW_CNT1__UPDN_MASK 0xffff
-#define GDS_CS_CTXSW_CNT1__UPDN__SHIFT 0x0
-#define GDS_CS_CTXSW_CNT1__PTR_MASK 0xffff0000
-#define GDS_CS_CTXSW_CNT1__PTR__SHIFT 0x10
-#define GDS_CS_CTXSW_CNT2__UPDN_MASK 0xffff
-#define GDS_CS_CTXSW_CNT2__UPDN__SHIFT 0x0
-#define GDS_CS_CTXSW_CNT2__PTR_MASK 0xffff0000
-#define GDS_CS_CTXSW_CNT2__PTR__SHIFT 0x10
-#define GDS_CS_CTXSW_CNT3__UPDN_MASK 0xffff
-#define GDS_CS_CTXSW_CNT3__UPDN__SHIFT 0x0
-#define GDS_CS_CTXSW_CNT3__PTR_MASK 0xffff0000
-#define GDS_CS_CTXSW_CNT3__PTR__SHIFT 0x10
-#define GDS_GFX_CTXSW_STATUS__R_MASK 0x1
-#define GDS_GFX_CTXSW_STATUS__R__SHIFT 0x0
-#define GDS_GFX_CTXSW_STATUS__W_MASK 0x2
-#define GDS_GFX_CTXSW_STATUS__W__SHIFT 0x1
-#define GDS_GFX_CTXSW_STATUS__UNUSED_MASK 0xfffffffc
-#define GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT 0x2
-#define GDS_VS_CTXSW_CNT0__UPDN_MASK 0xffff
-#define GDS_VS_CTXSW_CNT0__UPDN__SHIFT 0x0
-#define GDS_VS_CTXSW_CNT0__PTR_MASK 0xffff0000
-#define GDS_VS_CTXSW_CNT0__PTR__SHIFT 0x10
-#define GDS_VS_CTXSW_CNT1__UPDN_MASK 0xffff
-#define GDS_VS_CTXSW_CNT1__UPDN__SHIFT 0x0
-#define GDS_VS_CTXSW_CNT1__PTR_MASK 0xffff0000
-#define GDS_VS_CTXSW_CNT1__PTR__SHIFT 0x10
-#define GDS_VS_CTXSW_CNT2__UPDN_MASK 0xffff
-#define GDS_VS_CTXSW_CNT2__UPDN__SHIFT 0x0
-#define GDS_VS_CTXSW_CNT2__PTR_MASK 0xffff0000
-#define GDS_VS_CTXSW_CNT2__PTR__SHIFT 0x10
-#define GDS_VS_CTXSW_CNT3__UPDN_MASK 0xffff
-#define GDS_VS_CTXSW_CNT3__UPDN__SHIFT 0x0
-#define GDS_VS_CTXSW_CNT3__PTR_MASK 0xffff0000
-#define GDS_VS_CTXSW_CNT3__PTR__SHIFT 0x10
-#define GDS_PS0_CTXSW_CNT0__UPDN_MASK 0xffff
-#define GDS_PS0_CTXSW_CNT0__UPDN__SHIFT 0x0
-#define GDS_PS0_CTXSW_CNT0__PTR_MASK 0xffff0000
-#define GDS_PS0_CTXSW_CNT0__PTR__SHIFT 0x10
-#define GDS_PS1_CTXSW_CNT0__UPDN_MASK 0xffff
-#define GDS_PS1_CTXSW_CNT0__UPDN__SHIFT 0x0
-#define GDS_PS1_CTXSW_CNT0__PTR_MASK 0xffff0000
-#define GDS_PS1_CTXSW_CNT0__PTR__SHIFT 0x10
-#define GDS_PS2_CTXSW_CNT0__UPDN_MASK 0xffff
-#define GDS_PS2_CTXSW_CNT0__UPDN__SHIFT 0x0
-#define GDS_PS2_CTXSW_CNT0__PTR_MASK 0xffff0000
-#define GDS_PS2_CTXSW_CNT0__PTR__SHIFT 0x10
-#define GDS_PS3_CTXSW_CNT0__UPDN_MASK 0xffff
-#define GDS_PS3_CTXSW_CNT0__UPDN__SHIFT 0x0
-#define GDS_PS3_CTXSW_CNT0__PTR_MASK 0xffff0000
-#define GDS_PS3_CTXSW_CNT0__PTR__SHIFT 0x10
-#define GDS_PS4_CTXSW_CNT0__UPDN_MASK 0xffff
-#define GDS_PS4_CTXSW_CNT0__UPDN__SHIFT 0x0
-#define GDS_PS4_CTXSW_CNT0__PTR_MASK 0xffff0000
-#define GDS_PS4_CTXSW_CNT0__PTR__SHIFT 0x10
-#define GDS_PS5_CTXSW_CNT0__UPDN_MASK 0xffff
-#define GDS_PS5_CTXSW_CNT0__UPDN__SHIFT 0x0
-#define GDS_PS5_CTXSW_CNT0__PTR_MASK 0xffff0000
-#define GDS_PS5_CTXSW_CNT0__PTR__SHIFT 0x10
-#define GDS_PS6_CTXSW_CNT0__UPDN_MASK 0xffff
-#define GDS_PS6_CTXSW_CNT0__UPDN__SHIFT 0x0
-#define GDS_PS6_CTXSW_CNT0__PTR_MASK 0xffff0000
-#define GDS_PS6_CTXSW_CNT0__PTR__SHIFT 0x10
-#define GDS_PS7_CTXSW_CNT0__UPDN_MASK 0xffff
-#define GDS_PS7_CTXSW_CNT0__UPDN__SHIFT 0x0
-#define GDS_PS7_CTXSW_CNT0__PTR_MASK 0xffff0000
-#define GDS_PS7_CTXSW_CNT0__PTR__SHIFT 0x10
-#define GDS_PS0_CTXSW_CNT1__UPDN_MASK 0xffff
-#define GDS_PS0_CTXSW_CNT1__UPDN__SHIFT 0x0
-#define GDS_PS0_CTXSW_CNT1__PTR_MASK 0xffff0000
-#define GDS_PS0_CTXSW_CNT1__PTR__SHIFT 0x10
-#define GDS_PS1_CTXSW_CNT1__UPDN_MASK 0xffff
-#define GDS_PS1_CTXSW_CNT1__UPDN__SHIFT 0x0
-#define GDS_PS1_CTXSW_CNT1__PTR_MASK 0xffff0000
-#define GDS_PS1_CTXSW_CNT1__PTR__SHIFT 0x10
-#define GDS_PS2_CTXSW_CNT1__UPDN_MASK 0xffff
-#define GDS_PS2_CTXSW_CNT1__UPDN__SHIFT 0x0
-#define GDS_PS2_CTXSW_CNT1__PTR_MASK 0xffff0000
-#define GDS_PS2_CTXSW_CNT1__PTR__SHIFT 0x10
-#define GDS_PS3_CTXSW_CNT1__UPDN_MASK 0xffff
-#define GDS_PS3_CTXSW_CNT1__UPDN__SHIFT 0x0
-#define GDS_PS3_CTXSW_CNT1__PTR_MASK 0xffff0000
-#define GDS_PS3_CTXSW_CNT1__PTR__SHIFT 0x10
-#define GDS_PS4_CTXSW_CNT1__UPDN_MASK 0xffff
-#define GDS_PS4_CTXSW_CNT1__UPDN__SHIFT 0x0
-#define GDS_PS4_CTXSW_CNT1__PTR_MASK 0xffff0000
-#define GDS_PS4_CTXSW_CNT1__PTR__SHIFT 0x10
-#define GDS_PS5_CTXSW_CNT1__UPDN_MASK 0xffff
-#define GDS_PS5_CTXSW_CNT1__UPDN__SHIFT 0x0
-#define GDS_PS5_CTXSW_CNT1__PTR_MASK 0xffff0000
-#define GDS_PS5_CTXSW_CNT1__PTR__SHIFT 0x10
-#define GDS_PS6_CTXSW_CNT1__UPDN_MASK 0xffff
-#define GDS_PS6_CTXSW_CNT1__UPDN__SHIFT 0x0
-#define GDS_PS6_CTXSW_CNT1__PTR_MASK 0xffff0000
-#define GDS_PS6_CTXSW_CNT1__PTR__SHIFT 0x10
-#define GDS_PS7_CTXSW_CNT1__UPDN_MASK 0xffff
-#define GDS_PS7_CTXSW_CNT1__UPDN__SHIFT 0x0
-#define GDS_PS7_CTXSW_CNT1__PTR_MASK 0xffff0000
-#define GDS_PS7_CTXSW_CNT1__PTR__SHIFT 0x10
-#define GDS_PS0_CTXSW_CNT2__UPDN_MASK 0xffff
-#define GDS_PS0_CTXSW_CNT2__UPDN__SHIFT 0x0
-#define GDS_PS0_CTXSW_CNT2__PTR_MASK 0xffff0000
-#define GDS_PS0_CTXSW_CNT2__PTR__SHIFT 0x10
-#define GDS_PS1_CTXSW_CNT2__UPDN_MASK 0xffff
-#define GDS_PS1_CTXSW_CNT2__UPDN__SHIFT 0x0
-#define GDS_PS1_CTXSW_CNT2__PTR_MASK 0xffff0000
-#define GDS_PS1_CTXSW_CNT2__PTR__SHIFT 0x10
-#define GDS_PS2_CTXSW_CNT2__UPDN_MASK 0xffff
-#define GDS_PS2_CTXSW_CNT2__UPDN__SHIFT 0x0
-#define GDS_PS2_CTXSW_CNT2__PTR_MASK 0xffff0000
-#define GDS_PS2_CTXSW_CNT2__PTR__SHIFT 0x10
-#define GDS_PS3_CTXSW_CNT2__UPDN_MASK 0xffff
-#define GDS_PS3_CTXSW_CNT2__UPDN__SHIFT 0x0
-#define GDS_PS3_CTXSW_CNT2__PTR_MASK 0xffff0000
-#define GDS_PS3_CTXSW_CNT2__PTR__SHIFT 0x10
-#define GDS_PS4_CTXSW_CNT2__UPDN_MASK 0xffff
-#define GDS_PS4_CTXSW_CNT2__UPDN__SHIFT 0x0
-#define GDS_PS4_CTXSW_CNT2__PTR_MASK 0xffff0000
-#define GDS_PS4_CTXSW_CNT2__PTR__SHIFT 0x10
-#define GDS_PS5_CTXSW_CNT2__UPDN_MASK 0xffff
-#define GDS_PS5_CTXSW_CNT2__UPDN__SHIFT 0x0
-#define GDS_PS5_CTXSW_CNT2__PTR_MASK 0xffff0000
-#define GDS_PS5_CTXSW_CNT2__PTR__SHIFT 0x10
-#define GDS_PS6_CTXSW_CNT2__UPDN_MASK 0xffff
-#define GDS_PS6_CTXSW_CNT2__UPDN__SHIFT 0x0
-#define GDS_PS6_CTXSW_CNT2__PTR_MASK 0xffff0000
-#define GDS_PS6_CTXSW_CNT2__PTR__SHIFT 0x10
-#define GDS_PS7_CTXSW_CNT2__UPDN_MASK 0xffff
-#define GDS_PS7_CTXSW_CNT2__UPDN__SHIFT 0x0
-#define GDS_PS7_CTXSW_CNT2__PTR_MASK 0xffff0000
-#define GDS_PS7_CTXSW_CNT2__PTR__SHIFT 0x10
-#define GDS_PS0_CTXSW_CNT3__UPDN_MASK 0xffff
-#define GDS_PS0_CTXSW_CNT3__UPDN__SHIFT 0x0
-#define GDS_PS0_CTXSW_CNT3__PTR_MASK 0xffff0000
-#define GDS_PS0_CTXSW_CNT3__PTR__SHIFT 0x10
-#define GDS_PS1_CTXSW_CNT3__UPDN_MASK 0xffff
-#define GDS_PS1_CTXSW_CNT3__UPDN__SHIFT 0x0
-#define GDS_PS1_CTXSW_CNT3__PTR_MASK 0xffff0000
-#define GDS_PS1_CTXSW_CNT3__PTR__SHIFT 0x10
-#define GDS_PS2_CTXSW_CNT3__UPDN_MASK 0xffff
-#define GDS_PS2_CTXSW_CNT3__UPDN__SHIFT 0x0
-#define GDS_PS2_CTXSW_CNT3__PTR_MASK 0xffff0000
-#define GDS_PS2_CTXSW_CNT3__PTR__SHIFT 0x10
-#define GDS_PS3_CTXSW_CNT3__UPDN_MASK 0xffff
-#define GDS_PS3_CTXSW_CNT3__UPDN__SHIFT 0x0
-#define GDS_PS3_CTXSW_CNT3__PTR_MASK 0xffff0000
-#define GDS_PS3_CTXSW_CNT3__PTR__SHIFT 0x10
-#define GDS_PS4_CTXSW_CNT3__UPDN_MASK 0xffff
-#define GDS_PS4_CTXSW_CNT3__UPDN__SHIFT 0x0
-#define GDS_PS4_CTXSW_CNT3__PTR_MASK 0xffff0000
-#define GDS_PS4_CTXSW_CNT3__PTR__SHIFT 0x10
-#define GDS_PS5_CTXSW_CNT3__UPDN_MASK 0xffff
-#define GDS_PS5_CTXSW_CNT3__UPDN__SHIFT 0x0
-#define GDS_PS5_CTXSW_CNT3__PTR_MASK 0xffff0000
-#define GDS_PS5_CTXSW_CNT3__PTR__SHIFT 0x10
-#define GDS_PS6_CTXSW_CNT3__UPDN_MASK 0xffff
-#define GDS_PS6_CTXSW_CNT3__UPDN__SHIFT 0x0
-#define GDS_PS6_CTXSW_CNT3__PTR_MASK 0xffff0000
-#define GDS_PS6_CTXSW_CNT3__PTR__SHIFT 0x10
-#define GDS_PS7_CTXSW_CNT3__UPDN_MASK 0xffff
-#define GDS_PS7_CTXSW_CNT3__UPDN__SHIFT 0x0
-#define GDS_PS7_CTXSW_CNT3__PTR_MASK 0xffff0000
-#define GDS_PS7_CTXSW_CNT3__PTR__SHIFT 0x10
-#define CS_COPY_STATE__SRC_STATE_ID_MASK 0x7
-#define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
-#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x7
-#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
-#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x3
-#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x0
-#define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0xc
-#define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x2
-#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x10
-#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x4
-#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x20
-#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x5
-#define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x40
-#define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x6
-#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x3f
-#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0
-#define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x7fc0000
-#define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0x12
-#define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x8000000
-#define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b
-#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0xfffffff
-#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x0
-#define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0xff
-#define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x0
-#define VGT_DMA_BASE__BASE_ADDR_MASK 0xffffffff
-#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x0
-#define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x3
-#define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
-#define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0xc
-#define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x2
-#define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x30
-#define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x4
-#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0x40
-#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x6
-#define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x200
-#define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x9
-#define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x400
-#define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa
-#define VGT_DMA_INDEX_TYPE__MTYPE_MASK 0x1800
-#define VGT_DMA_INDEX_TYPE__MTYPE__SHIFT 0xb
-#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffff
-#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0
-#define IA_ENHANCE__MISC_MASK 0xffffffff
-#define IA_ENHANCE__MISC__SHIFT 0x0
-#define VGT_DMA_SIZE__NUM_INDICES_MASK 0xffffffff
-#define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x0
-#define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xffffffff
-#define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x0
-#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x3f
-#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0
-#define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0xffff
-#define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0
-#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x20000
-#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11
-#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x100000
-#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14
-#define VGT_IMMED_DATA__DATA_MASK 0xffffffff
-#define VGT_IMMED_DATA__DATA__SHIFT 0x0
-#define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x3
-#define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
-#define VGT_NUM_INDICES__NUM_INDICES_MASK 0xffffffff
-#define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x0
-#define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffff
-#define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0
-#define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x3f
-#define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0
-#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x1
-#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x0
-#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x2
-#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x1
-#define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xffffffff
-#define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x0
-#define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x1
-#define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x0
-#define VGT_REUSE_OFF__REUSE_OFF_MASK 0x1
-#define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x0
-#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xffffffff
-#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0
-#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xffffffff
-#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x0
-#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xffffffff
-#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0
-#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xffffffff
-#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0
-#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xffffffff
-#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0
-#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0xff
-#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x0
-#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x7f
-#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x0
-#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xffffffff
-#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0
-#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x1
-#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0
-#define VGT_ENHANCE__MISC_MASK 0xffffffff
-#define VGT_ENHANCE__MISC__SHIFT 0x0
-#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x7
-#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x0
-#define VGT_HOS_CNTL__TESS_MODE_MASK 0x3
-#define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x0
-#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xffffffff
-#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x0
-#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xffffffff
-#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x0
-#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0xff
-#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x0
-#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x1f
-#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x0
-#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x4000
-#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0xe
-#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x8000
-#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0xf
-#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x70000
-#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x10
-#define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0xf
-#define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x0
-#define VGT_GROUP_DECR__DECR_MASK 0xf
-#define VGT_GROUP_DECR__DECR__SHIFT 0x0
-#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x1
-#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x0
-#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x2
-#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x1
-#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x4
-#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x2
-#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x8
-#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x3
-#define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0xff00
-#define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x8
-#define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0xff0000
-#define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x10
-#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x1
-#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x0
-#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x2
-#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x1
-#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x4
-#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x2
-#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x8
-#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x3
-#define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0xff00
-#define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x8
-#define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0xff0000
-#define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x10
-#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0xf
-#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x0
-#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0xf0
-#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x4
-#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0xf00
-#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x8
-#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0xf000
-#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0xc
-#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0xf0000
-#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x10
-#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0xf00000
-#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x14
-#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0xf000000
-#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x18
-#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xf0000000
-#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x1c
-#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0xf
-#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x0
-#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0xf0
-#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x4
-#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0xf00
-#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x8
-#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0xf000
-#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0xc
-#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0xf0000
-#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x10
-#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0xf00000
-#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x14
-#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0xf000000
-#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x18
-#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xf0000000
-#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x1c
-#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x3ff
-#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0
-#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x1ff
-#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0
-#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH_MASK 0x7fe00
-#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH__SHIFT 0x9
-#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x3f
-#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0
-#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x3f
-#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0
-#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x7
-#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
-#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x70000
-#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10
-#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000
-#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10
-#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000
-#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10
-#define VGT_GS_MODE__MODE_MASK 0x7
-#define VGT_GS_MODE__MODE__SHIFT 0x0
-#define VGT_GS_MODE__RESERVED_0_MASK 0x8
-#define VGT_GS_MODE__RESERVED_0__SHIFT 0x3
-#define VGT_GS_MODE__CUT_MODE_MASK 0x30
-#define VGT_GS_MODE__CUT_MODE__SHIFT 0x4
-#define VGT_GS_MODE__RESERVED_1_MASK 0x7c0
-#define VGT_GS_MODE__RESERVED_1__SHIFT 0x6
-#define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x800
-#define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0xb
-#define VGT_GS_MODE__RESERVED_2_MASK 0x1000
-#define VGT_GS_MODE__RESERVED_2__SHIFT 0xc
-#define VGT_GS_MODE__ES_PASSTHRU_MASK 0x2000
-#define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0xd
-#define VGT_GS_MODE__RESERVED_3_MASK 0x4000
-#define VGT_GS_MODE__RESERVED_3__SHIFT 0xe
-#define VGT_GS_MODE__RESERVED_4_MASK 0x8000
-#define VGT_GS_MODE__RESERVED_4__SHIFT 0xf
-#define VGT_GS_MODE__RESERVED_5_MASK 0x10000
-#define VGT_GS_MODE__RESERVED_5__SHIFT 0x10
-#define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x20000
-#define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x11
-#define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x40000
-#define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x12
-#define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x80000
-#define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x13
-#define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x100000
-#define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x14
-#define VGT_GS_MODE__ONCHIP_MASK 0x600000
-#define VGT_GS_MODE__ONCHIP__SHIFT 0x15
-#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK 0x7ff
-#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT 0x0
-#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK 0x3ff800
-#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT 0xb
-#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x3f
-#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x0
-#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x3f00
-#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x8
-#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x3f0000
-#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x10
-#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0xfc00000
-#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x16
-#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000
-#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x1f
-#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x3
-#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0
-#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK 0x10
-#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT 0x4
-#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x20
-#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x5
-#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0xc0
-#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6
-#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x200
-#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9
-#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x800
-#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb
-#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x1000
-#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc
-#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x2000
-#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd
-#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x1f0000
-#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10
-#define VGT_RESET_DEBUG__GS_DISABLE_MASK 0x1
-#define VGT_RESET_DEBUG__GS_DISABLE__SHIFT 0x0
-#define VGT_RESET_DEBUG__TESS_DISABLE_MASK 0x2
-#define VGT_RESET_DEBUG__TESS_DISABLE__SHIFT 0x1
-#define VGT_RESET_DEBUG__WD_DISABLE_MASK 0x4
-#define VGT_RESET_DEBUG__WD_DISABLE__SHIFT 0x2
-#define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0xff
-#define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0
-#define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x700
-#define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8
-#define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x3800
-#define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb
-#define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x1c000
-#define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe
-#define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0xe0000
-#define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11
-#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x7f
-#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0
-#define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x80
-#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7
-#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x3fff00
-#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8
-#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK 0xfc00000
-#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT 0x16
-#define VGT_GS_PER_ES__GS_PER_ES_MASK 0x7ff
-#define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x0
-#define VGT_ES_PER_GS__ES_PER_GS_MASK 0x7ff
-#define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x0
-#define VGT_GS_PER_VS__GS_PER_VS_MASK 0xf
-#define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x0
-#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x1f
-#define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0
-#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x3
-#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0
-#define IA_CNTL_STATUS__IA_BUSY_MASK 0x1
-#define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x0
-#define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x2
-#define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x1
-#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x4
-#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x2
-#define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x8
-#define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x3
-#define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x10
-#define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x4
-#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x1
-#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x0
-#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x2
-#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x1
-#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x4
-#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x2
-#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x8
-#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x3
-#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x70
-#define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x4
-#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0xf00
-#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x8
-#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000
-#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x1f
-#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xffffffff
-#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xffffffff
-#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xffffffff
-#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xffffffff
-#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xffffffff
-#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xffffffff
-#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xffffffff
-#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xffffffff
-#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x0
-#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x3ff
-#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x0
-#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x3ff
-#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x0
-#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x3ff
-#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x0
-#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x3ff
-#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0xf
-#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0xf0
-#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x4
-#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0xf00
-#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x8
-#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0xf000
-#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0xc
-#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xffffffff
-#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xffffffff
-#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xffffffff
-#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x0
-#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xffffffff
-#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x0
-#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xffffffff
-#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x0
-#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xffffffff
-#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x0
-#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x1ff
-#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x0
-#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x7ff
-#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x0
-#define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x3
-#define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x0
-#define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x4
-#define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x2
-#define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x18
-#define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x3
-#define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x20
-#define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x5
-#define VGT_SHADER_STAGES_EN__VS_EN_MASK 0xc0
-#define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x6
-#define VGT_SHADER_STAGES_EN__DYNAMIC_HS_MASK 0x100
-#define VGT_SHADER_STAGES_EN__DYNAMIC_HS__SHIFT 0x8
-#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK 0x200
-#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT 0x9
-#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK 0x400
-#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT 0xa
-#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK 0x800
-#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT 0xb
-#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK 0x1000
-#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT 0xc
-#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK 0xffffffff
-#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT 0x0
-#define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0xff
-#define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x0
-#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x3f00
-#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8
-#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0xfc000
-#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0xe
-#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x3f00
-#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8
-#define VGT_TF_PARAM__TYPE_MASK 0x3
-#define VGT_TF_PARAM__TYPE__SHIFT 0x0
-#define VGT_TF_PARAM__PARTITIONING_MASK 0x1c
-#define VGT_TF_PARAM__PARTITIONING__SHIFT 0x2
-#define VGT_TF_PARAM__TOPOLOGY_MASK 0xe0
-#define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x5
-#define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK 0x100
-#define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT 0x8
-#define VGT_TF_PARAM__DEPRECATED_MASK 0x200
-#define VGT_TF_PARAM__DEPRECATED__SHIFT 0x9
-#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD_MASK 0x3c00
-#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD__SHIFT 0xa
-#define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x4000
-#define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0xe
-#define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x8000
-#define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0xf
-#define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK 0x60000
-#define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT 0x11
-#define VGT_TF_PARAM__MTYPE_MASK 0x180000
-#define VGT_TF_PARAM__MTYPE__SHIFT 0x13
-#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK 0xff
-#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT 0x0
-#define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK 0xff00
-#define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT 0x8
-#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0xff0000
-#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT 0x10
-#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK 0xff000000
-#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT 0x18
-#define VGT_TF_RING_SIZE__SIZE_MASK 0xffff
-#define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0
-#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x1
-#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0
-#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x7e
-#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1
-#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x80
-#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7
-#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x1ff
-#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0
-#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x600
-#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x9
-#define VGT_TF_MEMORY_BASE__BASE_MASK 0xffffffff
-#define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0
-#define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x1
-#define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x0
-#define VGT_GS_INSTANCE_CNT__CNT_MASK 0x1fc
-#define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x2
-#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0xffff
-#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x0
-#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x10000
-#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x10
-#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x20000
-#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x11
-#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x40000
-#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x12
-#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x80000
-#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x13
-#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x100000
-#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x14
-#define IA_MULTI_VGT_PARAM__MAX_PRIMGRP_IN_WAVE_MASK 0xf0000000
-#define IA_MULTI_VGT_PARAM__MAX_PRIMGRP_IN_WAVE__SHIFT 0x1c
-#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff
-#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
-#define VGT_ESGS_RING_SIZE__MEM_SIZE_MASK 0xffffffff
-#define VGT_ESGS_RING_SIZE__MEM_SIZE__SHIFT 0x0
-#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xffffffff
-#define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x0
-#define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x7fff
-#define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x0
-#define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x7fff
-#define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x0
-#define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x7fff
-#define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x0
-#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x7fff
-#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0
-#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x7fff
-#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0
-#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x7fff
-#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x0
-#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x7fff
-#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x0
-#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x7fff
-#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x0
-#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x7fff
-#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x0
-#define WD_CNTL_STATUS__WD_BUSY_MASK 0x1
-#define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x0
-#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x2
-#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x1
-#define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x4
-#define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x2
-#define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x8
-#define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x3
-#define WD_ENHANCE__MISC_MASK 0xffffffff
-#define WD_ENHANCE__MISC__SHIFT 0x0
-#define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x1fff
-#define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0
-#define GFX_PIPE_CONTROL__RESERVED_MASK 0xe000
-#define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd
-#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x10000
-#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10
-#define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0xf
-#define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
-#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
-#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x2000000
-#define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0x19
-#define CGTT_VGT_CLK_CTRL__DBG_ENABLE_MASK 0x4000000
-#define CGTT_VGT_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a
-#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
-#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000
-#define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x1c
-#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK 0x20000000
-#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x1d
-#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000
-#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
-#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
-#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
-#define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0xf
-#define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
-#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
-#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x2000000
-#define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x19
-#define CGTT_IA_CLK_CTRL__DBG_ENABLE_MASK 0x4000000
-#define CGTT_IA_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a
-#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
-#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
-#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
-#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000
-#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
-#define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
-#define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
-#define CGTT_WD_CLK_CTRL__ON_DELAY_MASK 0xf
-#define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
-#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
-#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK 0x2000000
-#define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT 0x19
-#define CGTT_WD_CLK_CTRL__DBG_ENABLE_MASK 0x4000000
-#define CGTT_WD_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a
-#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
-#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define CGTT_WD_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000
-#define CGTT_WD_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x1c
-#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000
-#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d
-#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000
-#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x1e
-#define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
-#define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
-#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK 0x3f
-#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT 0x0
-#define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B_MASK 0x40
-#define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B__SHIFT 0x6
-#define VGT_DEBUG_DATA__DATA_MASK 0xffffffff
-#define VGT_DEBUG_DATA__DATA__SHIFT 0x0
-#define IA_DEBUG_CNTL__IA_DEBUG_INDX_MASK 0x3f
-#define IA_DEBUG_CNTL__IA_DEBUG_INDX__SHIFT 0x0
-#define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B_MASK 0x40
-#define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B__SHIFT 0x6
-#define IA_DEBUG_DATA__DATA_MASK 0xffffffff
-#define IA_DEBUG_DATA__DATA__SHIFT 0x0
-#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x1
-#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x0
-#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x2
-#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x1
-#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x4
-#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x2
-#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x8
-#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x3
-#define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x10
-#define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x4
-#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x20
-#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x5
-#define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x40
-#define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x6
-#define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x80
-#define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x7
-#define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x100
-#define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x8
-#define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x200
-#define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x9
-#define WD_DEBUG_CNTL__WD_DEBUG_INDX_MASK 0x3f
-#define WD_DEBUG_CNTL__WD_DEBUG_INDX__SHIFT 0x0
-#define WD_DEBUG_CNTL__WD_DEBUG_SEL_BUS_B_MASK 0x40
-#define WD_DEBUG_CNTL__WD_DEBUG_SEL_BUS_B__SHIFT 0x6
-#define WD_DEBUG_DATA__DATA_MASK 0xffffffff
-#define WD_DEBUG_DATA__DATA__SHIFT 0x0
-#define WD_QOS__DRAW_STALL_MASK 0x1
-#define WD_QOS__DRAW_STALL__SHIFT 0x0
-#define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x30000
-#define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10
-#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0xf000000
-#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18
-#define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x30000
-#define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10
-#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0xf000000
-#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18
-#define WD_DEBUG_REG0__wd_busy_extended_MASK 0x1
-#define WD_DEBUG_REG0__wd_busy_extended__SHIFT 0x0
-#define WD_DEBUG_REG0__wd_nodma_busy_extended_MASK 0x2
-#define WD_DEBUG_REG0__wd_nodma_busy_extended__SHIFT 0x1
-#define WD_DEBUG_REG0__wd_busy_MASK 0x4
-#define WD_DEBUG_REG0__wd_busy__SHIFT 0x2
-#define WD_DEBUG_REG0__wd_nodma_busy_MASK 0x8
-#define WD_DEBUG_REG0__wd_nodma_busy__SHIFT 0x3
-#define WD_DEBUG_REG0__rbiu_busy_MASK 0x10
-#define WD_DEBUG_REG0__rbiu_busy__SHIFT 0x4
-#define WD_DEBUG_REG0__spl_dma_busy_MASK 0x20
-#define WD_DEBUG_REG0__spl_dma_busy__SHIFT 0x5
-#define WD_DEBUG_REG0__spl_di_busy_MASK 0x40
-#define WD_DEBUG_REG0__spl_di_busy__SHIFT 0x6
-#define WD_DEBUG_REG0__vgt0_active_q_MASK 0x80
-#define WD_DEBUG_REG0__vgt0_active_q__SHIFT 0x7
-#define WD_DEBUG_REG0__vgt1_active_q_MASK 0x100
-#define WD_DEBUG_REG0__vgt1_active_q__SHIFT 0x8
-#define WD_DEBUG_REG0__spl_dma_p1_busy_MASK 0x200
-#define WD_DEBUG_REG0__spl_dma_p1_busy__SHIFT 0x9
-#define WD_DEBUG_REG0__rbiu_dr_p1_fifo_busy_MASK 0x400
-#define WD_DEBUG_REG0__rbiu_dr_p1_fifo_busy__SHIFT 0xa
-#define WD_DEBUG_REG0__rbiu_di_p1_fifo_busy_MASK 0x800
-#define WD_DEBUG_REG0__rbiu_di_p1_fifo_busy__SHIFT 0xb
-#define WD_DEBUG_REG0__SPARE2_MASK 0x1000
-#define WD_DEBUG_REG0__SPARE2__SHIFT 0xc
-#define WD_DEBUG_REG0__rbiu_dr_fifo_busy_MASK 0x2000
-#define WD_DEBUG_REG0__rbiu_dr_fifo_busy__SHIFT 0xd
-#define WD_DEBUG_REG0__rbiu_spl_dr_valid_MASK 0x4000
-#define WD_DEBUG_REG0__rbiu_spl_dr_valid__SHIFT 0xe
-#define WD_DEBUG_REG0__spl_rbiu_dr_read_MASK 0x8000
-#define WD_DEBUG_REG0__spl_rbiu_dr_read__SHIFT 0xf
-#define WD_DEBUG_REG0__SPARE3_MASK 0x10000
-#define WD_DEBUG_REG0__SPARE3__SHIFT 0x10
-#define WD_DEBUG_REG0__rbiu_di_fifo_busy_MASK 0x20000
-#define WD_DEBUG_REG0__rbiu_di_fifo_busy__SHIFT 0x11
-#define WD_DEBUG_REG0__rbiu_spl_di_valid_MASK 0x40000
-#define WD_DEBUG_REG0__rbiu_spl_di_valid__SHIFT 0x12
-#define WD_DEBUG_REG0__spl_rbiu_di_read_MASK 0x80000
-#define WD_DEBUG_REG0__spl_rbiu_di_read__SHIFT 0x13
-#define WD_DEBUG_REG0__se0_synced_q_MASK 0x100000
-#define WD_DEBUG_REG0__se0_synced_q__SHIFT 0x14
-#define WD_DEBUG_REG0__se1_synced_q_MASK 0x200000
-#define WD_DEBUG_REG0__se1_synced_q__SHIFT 0x15
-#define WD_DEBUG_REG0__se2_synced_q_MASK 0x400000
-#define WD_DEBUG_REG0__se2_synced_q__SHIFT 0x16
-#define WD_DEBUG_REG0__se3_synced_q_MASK 0x800000
-#define WD_DEBUG_REG0__se3_synced_q__SHIFT 0x17
-#define WD_DEBUG_REG0__reg_clk_busy_MASK 0x1000000
-#define WD_DEBUG_REG0__reg_clk_busy__SHIFT 0x18
-#define WD_DEBUG_REG0__input_clk_busy_MASK 0x2000000
-#define WD_DEBUG_REG0__input_clk_busy__SHIFT 0x19
-#define WD_DEBUG_REG0__core_clk_busy_MASK 0x4000000
-#define WD_DEBUG_REG0__core_clk_busy__SHIFT 0x1a
-#define WD_DEBUG_REG0__vgt2_active_q_MASK 0x8000000
-#define WD_DEBUG_REG0__vgt2_active_q__SHIFT 0x1b
-#define WD_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000
-#define WD_DEBUG_REG0__sclk_reg_vld__SHIFT 0x1c
-#define WD_DEBUG_REG0__sclk_input_vld_MASK 0x20000000
-#define WD_DEBUG_REG0__sclk_input_vld__SHIFT 0x1d
-#define WD_DEBUG_REG0__sclk_core_vld_MASK 0x40000000
-#define WD_DEBUG_REG0__sclk_core_vld__SHIFT 0x1e
-#define WD_DEBUG_REG0__vgt3_active_q_MASK 0x80000000
-#define WD_DEBUG_REG0__vgt3_active_q__SHIFT 0x1f
-#define WD_DEBUG_REG1__grbm_fifo_empty_MASK 0x1
-#define WD_DEBUG_REG1__grbm_fifo_empty__SHIFT 0x0
-#define WD_DEBUG_REG1__grbm_fifo_full_MASK 0x2
-#define WD_DEBUG_REG1__grbm_fifo_full__SHIFT 0x1
-#define WD_DEBUG_REG1__grbm_fifo_we_MASK 0x4
-#define WD_DEBUG_REG1__grbm_fifo_we__SHIFT 0x2
-#define WD_DEBUG_REG1__grbm_fifo_re_MASK 0x8
-#define WD_DEBUG_REG1__grbm_fifo_re__SHIFT 0x3
-#define WD_DEBUG_REG1__draw_initiator_valid_q_MASK 0x10
-#define WD_DEBUG_REG1__draw_initiator_valid_q__SHIFT 0x4
-#define WD_DEBUG_REG1__event_initiator_valid_q_MASK 0x20
-#define WD_DEBUG_REG1__event_initiator_valid_q__SHIFT 0x5
-#define WD_DEBUG_REG1__event_addr_valid_q_MASK 0x40
-#define WD_DEBUG_REG1__event_addr_valid_q__SHIFT 0x6
-#define WD_DEBUG_REG1__dma_request_valid_q_MASK 0x80
-#define WD_DEBUG_REG1__dma_request_valid_q__SHIFT 0x7
-#define WD_DEBUG_REG1__SPARE0_MASK 0x100
-#define WD_DEBUG_REG1__SPARE0__SHIFT 0x8
-#define WD_DEBUG_REG1__min_indx_valid_q_MASK 0x200
-#define WD_DEBUG_REG1__min_indx_valid_q__SHIFT 0x9
-#define WD_DEBUG_REG1__max_indx_valid_q_MASK 0x400
-#define WD_DEBUG_REG1__max_indx_valid_q__SHIFT 0xa
-#define WD_DEBUG_REG1__indx_offset_valid_q_MASK 0x800
-#define WD_DEBUG_REG1__indx_offset_valid_q__SHIFT 0xb
-#define WD_DEBUG_REG1__grbm_fifo_rdata_reg_id_MASK 0x1f000
-#define WD_DEBUG_REG1__grbm_fifo_rdata_reg_id__SHIFT 0xc
-#define WD_DEBUG_REG1__grbm_fifo_rdata_state_MASK 0xe0000
-#define WD_DEBUG_REG1__grbm_fifo_rdata_state__SHIFT 0x11
-#define WD_DEBUG_REG1__free_cnt_q_MASK 0x3f00000
-#define WD_DEBUG_REG1__free_cnt_q__SHIFT 0x14
-#define WD_DEBUG_REG1__rbiu_di_fifo_we_MASK 0x4000000
-#define WD_DEBUG_REG1__rbiu_di_fifo_we__SHIFT 0x1a
-#define WD_DEBUG_REG1__rbiu_dr_fifo_we_MASK 0x8000000
-#define WD_DEBUG_REG1__rbiu_dr_fifo_we__SHIFT 0x1b
-#define WD_DEBUG_REG1__rbiu_di_fifo_empty_MASK 0x10000000
-#define WD_DEBUG_REG1__rbiu_di_fifo_empty__SHIFT 0x1c
-#define WD_DEBUG_REG1__rbiu_di_fifo_full_MASK 0x20000000
-#define WD_DEBUG_REG1__rbiu_di_fifo_full__SHIFT 0x1d
-#define WD_DEBUG_REG1__rbiu_dr_fifo_empty_MASK 0x40000000
-#define WD_DEBUG_REG1__rbiu_dr_fifo_empty__SHIFT 0x1e
-#define WD_DEBUG_REG1__rbiu_dr_fifo_full_MASK 0x80000000
-#define WD_DEBUG_REG1__rbiu_dr_fifo_full__SHIFT 0x1f
-#define WD_DEBUG_REG2__p1_grbm_fifo_empty_MASK 0x1
-#define WD_DEBUG_REG2__p1_grbm_fifo_empty__SHIFT 0x0
-#define WD_DEBUG_REG2__p1_grbm_fifo_full_MASK 0x2
-#define WD_DEBUG_REG2__p1_grbm_fifo_full__SHIFT 0x1
-#define WD_DEBUG_REG2__p1_grbm_fifo_we_MASK 0x4
-#define WD_DEBUG_REG2__p1_grbm_fifo_we__SHIFT 0x2
-#define WD_DEBUG_REG2__p1_grbm_fifo_re_MASK 0x8
-#define WD_DEBUG_REG2__p1_grbm_fifo_re__SHIFT 0x3
-#define WD_DEBUG_REG2__p1_draw_initiator_valid_q_MASK 0x10
-#define WD_DEBUG_REG2__p1_draw_initiator_valid_q__SHIFT 0x4
-#define WD_DEBUG_REG2__p1_event_initiator_valid_q_MASK 0x20
-#define WD_DEBUG_REG2__p1_event_initiator_valid_q__SHIFT 0x5
-#define WD_DEBUG_REG2__p1_event_addr_valid_q_MASK 0x40
-#define WD_DEBUG_REG2__p1_event_addr_valid_q__SHIFT 0x6
-#define WD_DEBUG_REG2__p1_dma_request_valid_q_MASK 0x80
-#define WD_DEBUG_REG2__p1_dma_request_valid_q__SHIFT 0x7
-#define WD_DEBUG_REG2__SPARE0_MASK 0x100
-#define WD_DEBUG_REG2__SPARE0__SHIFT 0x8
-#define WD_DEBUG_REG2__p1_min_indx_valid_q_MASK 0x200
-#define WD_DEBUG_REG2__p1_min_indx_valid_q__SHIFT 0x9
-#define WD_DEBUG_REG2__p1_max_indx_valid_q_MASK 0x400
-#define WD_DEBUG_REG2__p1_max_indx_valid_q__SHIFT 0xa
-#define WD_DEBUG_REG2__p1_indx_offset_valid_q_MASK 0x800
-#define WD_DEBUG_REG2__p1_indx_offset_valid_q__SHIFT 0xb
-#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_reg_id_MASK 0x1f000
-#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_reg_id__SHIFT 0xc
-#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_state_MASK 0xe0000
-#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_state__SHIFT 0x11
-#define WD_DEBUG_REG2__p1_free_cnt_q_MASK 0x3f00000
-#define WD_DEBUG_REG2__p1_free_cnt_q__SHIFT 0x14
-#define WD_DEBUG_REG2__p1_rbiu_di_fifo_we_MASK 0x4000000
-#define WD_DEBUG_REG2__p1_rbiu_di_fifo_we__SHIFT 0x1a
-#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_we_MASK 0x8000000
-#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_we__SHIFT 0x1b
-#define WD_DEBUG_REG2__p1_rbiu_di_fifo_empty_MASK 0x10000000
-#define WD_DEBUG_REG2__p1_rbiu_di_fifo_empty__SHIFT 0x1c
-#define WD_DEBUG_REG2__p1_rbiu_di_fifo_full_MASK 0x20000000
-#define WD_DEBUG_REG2__p1_rbiu_di_fifo_full__SHIFT 0x1d
-#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_empty_MASK 0x40000000
-#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_empty__SHIFT 0x1e
-#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_full_MASK 0x80000000
-#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_full__SHIFT 0x1f
-#define WD_DEBUG_REG3__rbiu_spl_dr_valid_MASK 0x1
-#define WD_DEBUG_REG3__rbiu_spl_dr_valid__SHIFT 0x0
-#define WD_DEBUG_REG3__SPARE0_MASK 0x2
-#define WD_DEBUG_REG3__SPARE0__SHIFT 0x1
-#define WD_DEBUG_REG3__pipe0_dr_MASK 0x4
-#define WD_DEBUG_REG3__pipe0_dr__SHIFT 0x2
-#define WD_DEBUG_REG3__pipe0_rtr_MASK 0x8
-#define WD_DEBUG_REG3__pipe0_rtr__SHIFT 0x3
-#define WD_DEBUG_REG3__pipe1_dr_MASK 0x10
-#define WD_DEBUG_REG3__pipe1_dr__SHIFT 0x4
-#define WD_DEBUG_REG3__pipe1_rtr_MASK 0x20
-#define WD_DEBUG_REG3__pipe1_rtr__SHIFT 0x5
-#define WD_DEBUG_REG3__wd_subdma_fifo_empty_MASK 0x40
-#define WD_DEBUG_REG3__wd_subdma_fifo_empty__SHIFT 0x6
-#define WD_DEBUG_REG3__wd_subdma_fifo_full_MASK 0x80
-#define WD_DEBUG_REG3__wd_subdma_fifo_full__SHIFT 0x7
-#define WD_DEBUG_REG3__dma_buf_type_p0_q_MASK 0x300
-#define WD_DEBUG_REG3__dma_buf_type_p0_q__SHIFT 0x8
-#define WD_DEBUG_REG3__dma_zero_indices_p0_q_MASK 0x400
-#define WD_DEBUG_REG3__dma_zero_indices_p0_q__SHIFT 0xa
-#define WD_DEBUG_REG3__dma_req_path_p3_q_MASK 0x800
-#define WD_DEBUG_REG3__dma_req_path_p3_q__SHIFT 0xb
-#define WD_DEBUG_REG3__dma_not_eop_p1_q_MASK 0x1000
-#define WD_DEBUG_REG3__dma_not_eop_p1_q__SHIFT 0xc
-#define WD_DEBUG_REG3__out_of_range_p4_MASK 0x2000
-#define WD_DEBUG_REG3__out_of_range_p4__SHIFT 0xd
-#define WD_DEBUG_REG3__last_sub_dma_p3_q_MASK 0x4000
-#define WD_DEBUG_REG3__last_sub_dma_p3_q__SHIFT 0xe
-#define WD_DEBUG_REG3__last_rdreq_of_sub_dma_p4_MASK 0x8000
-#define WD_DEBUG_REG3__last_rdreq_of_sub_dma_p4__SHIFT 0xf
-#define WD_DEBUG_REG3__WD_IA_dma_send_d_MASK 0x10000
-#define WD_DEBUG_REG3__WD_IA_dma_send_d__SHIFT 0x10
-#define WD_DEBUG_REG3__WD_IA_dma_rtr_MASK 0x20000
-#define WD_DEBUG_REG3__WD_IA_dma_rtr__SHIFT 0x11
-#define WD_DEBUG_REG3__WD_IA1_dma_send_d_MASK 0x40000
-#define WD_DEBUG_REG3__WD_IA1_dma_send_d__SHIFT 0x12
-#define WD_DEBUG_REG3__WD_IA1_dma_rtr_MASK 0x80000
-#define WD_DEBUG_REG3__WD_IA1_dma_rtr__SHIFT 0x13
-#define WD_DEBUG_REG3__last_inst_of_dma_p2_MASK 0x100000
-#define WD_DEBUG_REG3__last_inst_of_dma_p2__SHIFT 0x14
-#define WD_DEBUG_REG3__last_sd_of_inst_p2_MASK 0x200000
-#define WD_DEBUG_REG3__last_sd_of_inst_p2__SHIFT 0x15
-#define WD_DEBUG_REG3__last_sd_of_dma_p2_MASK 0x400000
-#define WD_DEBUG_REG3__last_sd_of_dma_p2__SHIFT 0x16
-#define WD_DEBUG_REG3__SPARE1_MASK 0x800000
-#define WD_DEBUG_REG3__SPARE1__SHIFT 0x17
-#define WD_DEBUG_REG3__WD_IA_dma_busy_MASK 0x1000000
-#define WD_DEBUG_REG3__WD_IA_dma_busy__SHIFT 0x18
-#define WD_DEBUG_REG3__WD_IA1_dma_busy_MASK 0x2000000
-#define WD_DEBUG_REG3__WD_IA1_dma_busy__SHIFT 0x19
-#define WD_DEBUG_REG3__send_to_ia1_p3_q_MASK 0x4000000
-#define WD_DEBUG_REG3__send_to_ia1_p3_q__SHIFT 0x1a
-#define WD_DEBUG_REG3__dma_wd_switch_on_eop_p3_q_MASK 0x8000000
-#define WD_DEBUG_REG3__dma_wd_switch_on_eop_p3_q__SHIFT 0x1b
-#define WD_DEBUG_REG3__pipe3_dr_MASK 0x10000000
-#define WD_DEBUG_REG3__pipe3_dr__SHIFT 0x1c
-#define WD_DEBUG_REG3__pipe3_rtr_MASK 0x20000000
-#define WD_DEBUG_REG3__pipe3_rtr__SHIFT 0x1d
-#define WD_DEBUG_REG3__wd_dma2draw_fifo_empty_MASK 0x40000000
-#define WD_DEBUG_REG3__wd_dma2draw_fifo_empty__SHIFT 0x1e
-#define WD_DEBUG_REG3__wd_dma2draw_fifo_full_MASK 0x80000000
-#define WD_DEBUG_REG3__wd_dma2draw_fifo_full__SHIFT 0x1f
-#define WD_DEBUG_REG4__rbiu_spl_di_valid_MASK 0x1
-#define WD_DEBUG_REG4__rbiu_spl_di_valid__SHIFT 0x0
-#define WD_DEBUG_REG4__spl_rbiu_di_read_MASK 0x2
-#define WD_DEBUG_REG4__spl_rbiu_di_read__SHIFT 0x1
-#define WD_DEBUG_REG4__rbiu_spl_p1_di_valid_MASK 0x4
-#define WD_DEBUG_REG4__rbiu_spl_p1_di_valid__SHIFT 0x2
-#define WD_DEBUG_REG4__spl_rbiu_p1_di_read_MASK 0x8
-#define WD_DEBUG_REG4__spl_rbiu_p1_di_read__SHIFT 0x3
-#define WD_DEBUG_REG4__pipe0_dr_MASK 0x10
-#define WD_DEBUG_REG4__pipe0_dr__SHIFT 0x4
-#define WD_DEBUG_REG4__pipe0_rtr_MASK 0x20
-#define WD_DEBUG_REG4__pipe0_rtr__SHIFT 0x5
-#define WD_DEBUG_REG4__pipe1_dr_MASK 0x40
-#define WD_DEBUG_REG4__pipe1_dr__SHIFT 0x6
-#define WD_DEBUG_REG4__pipe1_rtr_MASK 0x80
-#define WD_DEBUG_REG4__pipe1_rtr__SHIFT 0x7
-#define WD_DEBUG_REG4__pipe2_dr_MASK 0x100
-#define WD_DEBUG_REG4__pipe2_dr__SHIFT 0x8
-#define WD_DEBUG_REG4__pipe2_rtr_MASK 0x200
-#define WD_DEBUG_REG4__pipe2_rtr__SHIFT 0x9
-#define WD_DEBUG_REG4__pipe3_ld_MASK 0x400
-#define WD_DEBUG_REG4__pipe3_ld__SHIFT 0xa
-#define WD_DEBUG_REG4__pipe3_rtr_MASK 0x800
-#define WD_DEBUG_REG4__pipe3_rtr__SHIFT 0xb
-#define WD_DEBUG_REG4__WD_IA_draw_send_d_MASK 0x1000
-#define WD_DEBUG_REG4__WD_IA_draw_send_d__SHIFT 0xc
-#define WD_DEBUG_REG4__WD_IA_draw_rtr_MASK 0x2000
-#define WD_DEBUG_REG4__WD_IA_draw_rtr__SHIFT 0xd
-#define WD_DEBUG_REG4__di_type_p0_MASK 0xc000
-#define WD_DEBUG_REG4__di_type_p0__SHIFT 0xe
-#define WD_DEBUG_REG4__di_state_sel_p1_q_MASK 0x70000
-#define WD_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x10
-#define WD_DEBUG_REG4__di_wd_switch_on_eop_p1_q_MASK 0x80000
-#define WD_DEBUG_REG4__di_wd_switch_on_eop_p1_q__SHIFT 0x13
-#define WD_DEBUG_REG4__rbiu_spl_pipe0_lockout_MASK 0x100000
-#define WD_DEBUG_REG4__rbiu_spl_pipe0_lockout__SHIFT 0x14
-#define WD_DEBUG_REG4__last_inst_of_di_p2_MASK 0x200000
-#define WD_DEBUG_REG4__last_inst_of_di_p2__SHIFT 0x15
-#define WD_DEBUG_REG4__last_sd_of_inst_p2_MASK 0x400000
-#define WD_DEBUG_REG4__last_sd_of_inst_p2__SHIFT 0x16
-#define WD_DEBUG_REG4__last_sd_of_di_p2_MASK 0x800000
-#define WD_DEBUG_REG4__last_sd_of_di_p2__SHIFT 0x17
-#define WD_DEBUG_REG4__not_eop_wait_p1_q_MASK 0x1000000
-#define WD_DEBUG_REG4__not_eop_wait_p1_q__SHIFT 0x18
-#define WD_DEBUG_REG4__not_eop_wait_q_MASK 0x2000000
-#define WD_DEBUG_REG4__not_eop_wait_q__SHIFT 0x19
-#define WD_DEBUG_REG4__ext_event_wait_p1_q_MASK 0x4000000
-#define WD_DEBUG_REG4__ext_event_wait_p1_q__SHIFT 0x1a
-#define WD_DEBUG_REG4__ext_event_wait_q_MASK 0x8000000
-#define WD_DEBUG_REG4__ext_event_wait_q__SHIFT 0x1b
-#define WD_DEBUG_REG4__WD_IA1_draw_send_d_MASK 0x10000000
-#define WD_DEBUG_REG4__WD_IA1_draw_send_d__SHIFT 0x1c
-#define WD_DEBUG_REG4__WD_IA1_draw_rtr_MASK 0x20000000
-#define WD_DEBUG_REG4__WD_IA1_draw_rtr__SHIFT 0x1d
-#define WD_DEBUG_REG4__send_to_ia1_q_MASK 0x40000000
-#define WD_DEBUG_REG4__send_to_ia1_q__SHIFT 0x1e
-#define WD_DEBUG_REG4__dual_ia_mode_MASK 0x80000000
-#define WD_DEBUG_REG4__dual_ia_mode__SHIFT 0x1f
-#define WD_DEBUG_REG5__p1_rbiu_spl_dr_valid_MASK 0x1
-#define WD_DEBUG_REG5__p1_rbiu_spl_dr_valid__SHIFT 0x0
-#define WD_DEBUG_REG5__SPARE0_MASK 0x2
-#define WD_DEBUG_REG5__SPARE0__SHIFT 0x1
-#define WD_DEBUG_REG5__p1_pipe0_dr_MASK 0x4
-#define WD_DEBUG_REG5__p1_pipe0_dr__SHIFT 0x2
-#define WD_DEBUG_REG5__p1_pipe0_rtr_MASK 0x8
-#define WD_DEBUG_REG5__p1_pipe0_rtr__SHIFT 0x3
-#define WD_DEBUG_REG5__p1_pipe1_dr_MASK 0x10
-#define WD_DEBUG_REG5__p1_pipe1_dr__SHIFT 0x4
-#define WD_DEBUG_REG5__p1_pipe1_rtr_MASK 0x20
-#define WD_DEBUG_REG5__p1_pipe1_rtr__SHIFT 0x5
-#define WD_DEBUG_REG5__p1_wd_subdma_fifo_empty_MASK 0x40
-#define WD_DEBUG_REG5__p1_wd_subdma_fifo_empty__SHIFT 0x6
-#define WD_DEBUG_REG5__p1_wd_subdma_fifo_full_MASK 0x80
-#define WD_DEBUG_REG5__p1_wd_subdma_fifo_full__SHIFT 0x7
-#define WD_DEBUG_REG5__p1_dma_buf_type_p0_q_MASK 0x300
-#define WD_DEBUG_REG5__p1_dma_buf_type_p0_q__SHIFT 0x8
-#define WD_DEBUG_REG5__p1_dma_zero_indices_p0_q_MASK 0x400
-#define WD_DEBUG_REG5__p1_dma_zero_indices_p0_q__SHIFT 0xa
-#define WD_DEBUG_REG5__p1_dma_req_path_p3_q_MASK 0x800
-#define WD_DEBUG_REG5__p1_dma_req_path_p3_q__SHIFT 0xb
-#define WD_DEBUG_REG5__p1_dma_not_eop_p1_q_MASK 0x1000
-#define WD_DEBUG_REG5__p1_dma_not_eop_p1_q__SHIFT 0xc
-#define WD_DEBUG_REG5__p1_out_of_range_p4_MASK 0x2000
-#define WD_DEBUG_REG5__p1_out_of_range_p4__SHIFT 0xd
-#define WD_DEBUG_REG5__p1_last_sub_dma_p3_q_MASK 0x4000
-#define WD_DEBUG_REG5__p1_last_sub_dma_p3_q__SHIFT 0xe
-#define WD_DEBUG_REG5__p1_last_rdreq_of_sub_dma_p4_MASK 0x8000
-#define WD_DEBUG_REG5__p1_last_rdreq_of_sub_dma_p4__SHIFT 0xf
-#define WD_DEBUG_REG5__p1_WD_IA_dma_send_d_MASK 0x10000
-#define WD_DEBUG_REG5__p1_WD_IA_dma_send_d__SHIFT 0x10
-#define WD_DEBUG_REG5__p1_WD_IA_dma_rtr_MASK 0x20000
-#define WD_DEBUG_REG5__p1_WD_IA_dma_rtr__SHIFT 0x11
-#define WD_DEBUG_REG5__p1_WD_IA1_dma_send_d_MASK 0x40000
-#define WD_DEBUG_REG5__p1_WD_IA1_dma_send_d__SHIFT 0x12
-#define WD_DEBUG_REG5__p1_WD_IA1_dma_rtr_MASK 0x80000
-#define WD_DEBUG_REG5__p1_WD_IA1_dma_rtr__SHIFT 0x13
-#define WD_DEBUG_REG5__p1_last_inst_of_dma_p2_MASK 0x100000
-#define WD_DEBUG_REG5__p1_last_inst_of_dma_p2__SHIFT 0x14
-#define WD_DEBUG_REG5__p1_last_sd_of_inst_p2_MASK 0x200000
-#define WD_DEBUG_REG5__p1_last_sd_of_inst_p2__SHIFT 0x15
-#define WD_DEBUG_REG5__p1_last_sd_of_dma_p2_MASK 0x400000
-#define WD_DEBUG_REG5__p1_last_sd_of_dma_p2__SHIFT 0x16
-#define WD_DEBUG_REG5__SPARE1_MASK 0x800000
-#define WD_DEBUG_REG5__SPARE1__SHIFT 0x17
-#define WD_DEBUG_REG5__p1_WD_IA_dma_busy_MASK 0x1000000
-#define WD_DEBUG_REG5__p1_WD_IA_dma_busy__SHIFT 0x18
-#define WD_DEBUG_REG5__p1_WD_IA1_dma_busy_MASK 0x2000000
-#define WD_DEBUG_REG5__p1_WD_IA1_dma_busy__SHIFT 0x19
-#define WD_DEBUG_REG5__p1_send_to_ia1_p3_q_MASK 0x4000000
-#define WD_DEBUG_REG5__p1_send_to_ia1_p3_q__SHIFT 0x1a
-#define WD_DEBUG_REG5__p1_dma_wd_switch_on_eop_p3_q_MASK 0x8000000
-#define WD_DEBUG_REG5__p1_dma_wd_switch_on_eop_p3_q__SHIFT 0x1b
-#define WD_DEBUG_REG5__p1_pipe3_dr_MASK 0x10000000
-#define WD_DEBUG_REG5__p1_pipe3_dr__SHIFT 0x1c
-#define WD_DEBUG_REG5__p1_pipe3_rtr_MASK 0x20000000
-#define WD_DEBUG_REG5__p1_pipe3_rtr__SHIFT 0x1d
-#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_empty_MASK 0x40000000
-#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_empty__SHIFT 0x1e
-#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_full_MASK 0x80000000
-#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_full__SHIFT 0x1f
-#define WD_DEBUG_REG6__WD_IA_draw_eop_MASK 0xffffffff
-#define WD_DEBUG_REG6__WD_IA_draw_eop__SHIFT 0x0
-#define WD_DEBUG_REG7__SE0VGT_WD_thdgrp_send_in_MASK 0x1
-#define WD_DEBUG_REG7__SE0VGT_WD_thdgrp_send_in__SHIFT 0x0
-#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_re_MASK 0x2
-#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_re__SHIFT 0x1
-#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_empty_MASK 0x4
-#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_empty__SHIFT 0x2
-#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_full_MASK 0x8
-#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_full__SHIFT 0x3
-#define WD_DEBUG_REG7__SE1VGT_WD_thdgrp_send_in_MASK 0x10
-#define WD_DEBUG_REG7__SE1VGT_WD_thdgrp_send_in__SHIFT 0x4
-#define WD_DEBUG_REG7__wd_arb_se1_input_fifo_re_MASK 0x20
-#define WD_DEBUG_REG7__wd_arb_se1_input_fifo_re__SHIFT 0x5
-#define WD_DEBUG_REG7__wd_arb_se1_input_fifo_empty_MASK 0x40
-#define WD_DEBUG_REG7__wd_arb_se1_input_fifo_empty__SHIFT 0x6
-#define WD_DEBUG_REG7__wd_arb_se1_input_fifo_full_MASK 0x80
-#define WD_DEBUG_REG7__wd_arb_se1_input_fifo_full__SHIFT 0x7
-#define WD_DEBUG_REG7__SPARE1_MASK 0xf00
-#define WD_DEBUG_REG7__SPARE1__SHIFT 0x8
-#define WD_DEBUG_REG7__SPARE2_MASK 0xf000
-#define WD_DEBUG_REG7__SPARE2__SHIFT 0xc
-#define WD_DEBUG_REG7__te11_arb_state_q_MASK 0x70000
-#define WD_DEBUG_REG7__te11_arb_state_q__SHIFT 0x10
-#define WD_DEBUG_REG7__SPARE5_MASK 0x80000
-#define WD_DEBUG_REG7__SPARE5__SHIFT 0x13
-#define WD_DEBUG_REG7__se0_thdgrp_is_event_MASK 0x100000
-#define WD_DEBUG_REG7__se0_thdgrp_is_event__SHIFT 0x14
-#define WD_DEBUG_REG7__se0_thdgrp_eop_MASK 0x200000
-#define WD_DEBUG_REG7__se0_thdgrp_eop__SHIFT 0x15
-#define WD_DEBUG_REG7__se1_thdgrp_is_event_MASK 0x400000
-#define WD_DEBUG_REG7__se1_thdgrp_is_event__SHIFT 0x16
-#define WD_DEBUG_REG7__se1_thdgrp_eop_MASK 0x800000
-#define WD_DEBUG_REG7__se1_thdgrp_eop__SHIFT 0x17
-#define WD_DEBUG_REG7__SPARE6_MASK 0xf000000
-#define WD_DEBUG_REG7__SPARE6__SHIFT 0x18
-#define WD_DEBUG_REG7__tfreq_arb_tgroup_rtr_MASK 0x10000000
-#define WD_DEBUG_REG7__tfreq_arb_tgroup_rtr__SHIFT 0x1c
-#define WD_DEBUG_REG7__arb_tfreq_tgroup_rts_MASK 0x20000000
-#define WD_DEBUG_REG7__arb_tfreq_tgroup_rts__SHIFT 0x1d
-#define WD_DEBUG_REG7__arb_tfreq_tgroup_event_MASK 0x40000000
-#define WD_DEBUG_REG7__arb_tfreq_tgroup_event__SHIFT 0x1e
-#define WD_DEBUG_REG7__te11_arb_busy_MASK 0x80000000
-#define WD_DEBUG_REG7__te11_arb_busy__SHIFT 0x1f
-#define WD_DEBUG_REG8__pipe0_dr_MASK 0x1
-#define WD_DEBUG_REG8__pipe0_dr__SHIFT 0x0
-#define WD_DEBUG_REG8__pipe1_dr_MASK 0x2
-#define WD_DEBUG_REG8__pipe1_dr__SHIFT 0x1
-#define WD_DEBUG_REG8__pipe0_rtr_MASK 0x4
-#define WD_DEBUG_REG8__pipe0_rtr__SHIFT 0x2
-#define WD_DEBUG_REG8__pipe1_rtr_MASK 0x8
-#define WD_DEBUG_REG8__pipe1_rtr__SHIFT 0x3
-#define WD_DEBUG_REG8__tfreq_tg_fifo_empty_MASK 0x10
-#define WD_DEBUG_REG8__tfreq_tg_fifo_empty__SHIFT 0x4
-#define WD_DEBUG_REG8__tfreq_tg_fifo_full_MASK 0x20
-#define WD_DEBUG_REG8__tfreq_tg_fifo_full__SHIFT 0x5
-#define WD_DEBUG_REG8__tf_data_fifo_busy_q_MASK 0x40
-#define WD_DEBUG_REG8__tf_data_fifo_busy_q__SHIFT 0x6
-#define WD_DEBUG_REG8__tf_data_fifo_rtr_q_MASK 0x80
-#define WD_DEBUG_REG8__tf_data_fifo_rtr_q__SHIFT 0x7
-#define WD_DEBUG_REG8__tf_skid_fifo_empty_MASK 0x100
-#define WD_DEBUG_REG8__tf_skid_fifo_empty__SHIFT 0x8
-#define WD_DEBUG_REG8__tf_skid_fifo_full_MASK 0x200
-#define WD_DEBUG_REG8__tf_skid_fifo_full__SHIFT 0x9
-#define WD_DEBUG_REG8__wd_tc_rdreq_rtr_q_MASK 0x400
-#define WD_DEBUG_REG8__wd_tc_rdreq_rtr_q__SHIFT 0xa
-#define WD_DEBUG_REG8__last_req_of_tg_p2_MASK 0x800
-#define WD_DEBUG_REG8__last_req_of_tg_p2__SHIFT 0xb
-#define WD_DEBUG_REG8__se0spi_wd_hs_done_cnt_q_MASK 0x3f000
-#define WD_DEBUG_REG8__se0spi_wd_hs_done_cnt_q__SHIFT 0xc
-#define WD_DEBUG_REG8__event_flag_p1_q_MASK 0x40000
-#define WD_DEBUG_REG8__event_flag_p1_q__SHIFT 0x12
-#define WD_DEBUG_REG8__null_flag_p1_q_MASK 0x80000
-#define WD_DEBUG_REG8__null_flag_p1_q__SHIFT 0x13
-#define WD_DEBUG_REG8__tf_data_fifo_cnt_q_MASK 0x7f00000
-#define WD_DEBUG_REG8__tf_data_fifo_cnt_q__SHIFT 0x14
-#define WD_DEBUG_REG8__second_tf_ret_data_q_MASK 0x8000000
-#define WD_DEBUG_REG8__second_tf_ret_data_q__SHIFT 0x1b
-#define WD_DEBUG_REG8__first_req_of_tg_p1_q_MASK 0x10000000
-#define WD_DEBUG_REG8__first_req_of_tg_p1_q__SHIFT 0x1c
-#define WD_DEBUG_REG8__WD_TC_rdreq_send_out_MASK 0x20000000
-#define WD_DEBUG_REG8__WD_TC_rdreq_send_out__SHIFT 0x1d
-#define WD_DEBUG_REG8__WD_TC_rdnfo_stall_out_MASK 0x40000000
-#define WD_DEBUG_REG8__WD_TC_rdnfo_stall_out__SHIFT 0x1e
-#define WD_DEBUG_REG8__TC_WD_rdret_valid_in_MASK 0x80000000
-#define WD_DEBUG_REG8__TC_WD_rdret_valid_in__SHIFT 0x1f
-#define WD_DEBUG_REG9__pipe0_dr_MASK 0x1
-#define WD_DEBUG_REG9__pipe0_dr__SHIFT 0x0
-#define WD_DEBUG_REG9__pipec_tf_dr_MASK 0x2
-#define WD_DEBUG_REG9__pipec_tf_dr__SHIFT 0x1
-#define WD_DEBUG_REG9__pipe2_dr_MASK 0x4
-#define WD_DEBUG_REG9__pipe2_dr__SHIFT 0x2
-#define WD_DEBUG_REG9__event_or_null_flags_p0_q_MASK 0x8
-#define WD_DEBUG_REG9__event_or_null_flags_p0_q__SHIFT 0x3
-#define WD_DEBUG_REG9__pipe0_rtr_MASK 0x10
-#define WD_DEBUG_REG9__pipe0_rtr__SHIFT 0x4
-#define WD_DEBUG_REG9__pipe1_rtr_MASK 0x20
-#define WD_DEBUG_REG9__pipe1_rtr__SHIFT 0x5
-#define WD_DEBUG_REG9__pipec_tf_rtr_MASK 0x40
-#define WD_DEBUG_REG9__pipec_tf_rtr__SHIFT 0x6
-#define WD_DEBUG_REG9__pipe2_rtr_MASK 0x80
-#define WD_DEBUG_REG9__pipe2_rtr__SHIFT 0x7
-#define WD_DEBUG_REG9__ttp_patch_fifo_full_MASK 0x100
-#define WD_DEBUG_REG9__ttp_patch_fifo_full__SHIFT 0x8
-#define WD_DEBUG_REG9__ttp_patch_fifo_empty_MASK 0x200
-#define WD_DEBUG_REG9__ttp_patch_fifo_empty__SHIFT 0x9
-#define WD_DEBUG_REG9__ttp_tf_fifo_empty_MASK 0x400
-#define WD_DEBUG_REG9__ttp_tf_fifo_empty__SHIFT 0xa
-#define WD_DEBUG_REG9__SPARE0_MASK 0xf800
-#define WD_DEBUG_REG9__SPARE0__SHIFT 0xb
-#define WD_DEBUG_REG9__tf_fetch_state_q_MASK 0x70000
-#define WD_DEBUG_REG9__tf_fetch_state_q__SHIFT 0x10
-#define WD_DEBUG_REG9__last_patch_of_tg_MASK 0x80000
-#define WD_DEBUG_REG9__last_patch_of_tg__SHIFT 0x13
-#define WD_DEBUG_REG9__tf_pointer_p0_q_MASK 0xf00000
-#define WD_DEBUG_REG9__tf_pointer_p0_q__SHIFT 0x14
-#define WD_DEBUG_REG9__dynamic_hs_p0_q_MASK 0x1000000
-#define WD_DEBUG_REG9__dynamic_hs_p0_q__SHIFT 0x18
-#define WD_DEBUG_REG9__first_fetch_of_tg_p0_q_MASK 0x2000000
-#define WD_DEBUG_REG9__first_fetch_of_tg_p0_q__SHIFT 0x19
-#define WD_DEBUG_REG9__mem_is_even_MASK 0x4000000
-#define WD_DEBUG_REG9__mem_is_even__SHIFT 0x1a
-#define WD_DEBUG_REG9__SPARE1_MASK 0x8000000
-#define WD_DEBUG_REG9__SPARE1__SHIFT 0x1b
-#define WD_DEBUG_REG9__SPARE2_MASK 0x30000000
-#define WD_DEBUG_REG9__SPARE2__SHIFT 0x1c
-#define WD_DEBUG_REG9__pipe4_dr_MASK 0x40000000
-#define WD_DEBUG_REG9__pipe4_dr__SHIFT 0x1e
-#define WD_DEBUG_REG9__pipe4_rtr_MASK 0x80000000
-#define WD_DEBUG_REG9__pipe4_rtr__SHIFT 0x1f
-#define WD_DEBUG_REG10__ttp_pd_patch_rts_MASK 0x1
-#define WD_DEBUG_REG10__ttp_pd_patch_rts__SHIFT 0x0
-#define WD_DEBUG_REG10__ttp_pd_is_event_MASK 0x2
-#define WD_DEBUG_REG10__ttp_pd_is_event__SHIFT 0x1
-#define WD_DEBUG_REG10__ttp_pd_eopg_MASK 0x4
-#define WD_DEBUG_REG10__ttp_pd_eopg__SHIFT 0x2
-#define WD_DEBUG_REG10__ttp_pd_eop_MASK 0x8
-#define WD_DEBUG_REG10__ttp_pd_eop__SHIFT 0x3
-#define WD_DEBUG_REG10__pipe0_dr_MASK 0x10
-#define WD_DEBUG_REG10__pipe0_dr__SHIFT 0x4
-#define WD_DEBUG_REG10__pipe1_dr_MASK 0x20
-#define WD_DEBUG_REG10__pipe1_dr__SHIFT 0x5
-#define WD_DEBUG_REG10__pipe0_rtr_MASK 0x40
-#define WD_DEBUG_REG10__pipe0_rtr__SHIFT 0x6
-#define WD_DEBUG_REG10__pipe1_rtr_MASK 0x80
-#define WD_DEBUG_REG10__pipe1_rtr__SHIFT 0x7
-#define WD_DEBUG_REG10__donut_en_p1_q_MASK 0x100
-#define WD_DEBUG_REG10__donut_en_p1_q__SHIFT 0x8
-#define WD_DEBUG_REG10__donut_se_switch_p2_MASK 0x200
-#define WD_DEBUG_REG10__donut_se_switch_p2__SHIFT 0x9
-#define WD_DEBUG_REG10__patch_se_switch_p2_MASK 0x400
-#define WD_DEBUG_REG10__patch_se_switch_p2__SHIFT 0xa
-#define WD_DEBUG_REG10__last_donut_switch_p2_MASK 0x800
-#define WD_DEBUG_REG10__last_donut_switch_p2__SHIFT 0xb
-#define WD_DEBUG_REG10__last_donut_of_patch_p2_MASK 0x1000
-#define WD_DEBUG_REG10__last_donut_of_patch_p2__SHIFT 0xc
-#define WD_DEBUG_REG10__is_event_p1_q_MASK 0x2000
-#define WD_DEBUG_REG10__is_event_p1_q__SHIFT 0xd
-#define WD_DEBUG_REG10__eopg_p1_q_MASK 0x4000
-#define WD_DEBUG_REG10__eopg_p1_q__SHIFT 0xe
-#define WD_DEBUG_REG10__eop_p1_q_MASK 0x8000
-#define WD_DEBUG_REG10__eop_p1_q__SHIFT 0xf
-#define WD_DEBUG_REG10__patch_accum_q_MASK 0xff0000
-#define WD_DEBUG_REG10__patch_accum_q__SHIFT 0x10
-#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_full_MASK 0x1000000
-#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_full__SHIFT 0x18
-#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_empty_MASK 0x2000000
-#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_empty__SHIFT 0x19
-#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_full_MASK 0x4000000
-#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_full__SHIFT 0x1a
-#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_empty_MASK 0x8000000
-#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_empty__SHIFT 0x1b
-#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_full_MASK 0x10000000
-#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_full__SHIFT 0x1c
-#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_empty_MASK 0x20000000
-#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_empty__SHIFT 0x1d
-#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_full_MASK 0x40000000
-#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_full__SHIFT 0x1e
-#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_empty_MASK 0x80000000
-#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_empty__SHIFT 0x1f
-#define IA_DEBUG_REG0__ia_busy_extended_MASK 0x1
-#define IA_DEBUG_REG0__ia_busy_extended__SHIFT 0x0
-#define IA_DEBUG_REG0__ia_nodma_busy_extended_MASK 0x2
-#define IA_DEBUG_REG0__ia_nodma_busy_extended__SHIFT 0x1
-#define IA_DEBUG_REG0__ia_busy_MASK 0x4
-#define IA_DEBUG_REG0__ia_busy__SHIFT 0x2
-#define IA_DEBUG_REG0__ia_nodma_busy_MASK 0x8
-#define IA_DEBUG_REG0__ia_nodma_busy__SHIFT 0x3
-#define IA_DEBUG_REG0__SPARE0_MASK 0x10
-#define IA_DEBUG_REG0__SPARE0__SHIFT 0x4
-#define IA_DEBUG_REG0__dma_req_busy_MASK 0x20
-#define IA_DEBUG_REG0__dma_req_busy__SHIFT 0x5
-#define IA_DEBUG_REG0__dma_busy_MASK 0x40
-#define IA_DEBUG_REG0__dma_busy__SHIFT 0x6
-#define IA_DEBUG_REG0__mc_xl8r_busy_MASK 0x80
-#define IA_DEBUG_REG0__mc_xl8r_busy__SHIFT 0x7
-#define IA_DEBUG_REG0__grp_busy_MASK 0x100
-#define IA_DEBUG_REG0__grp_busy__SHIFT 0x8
-#define IA_DEBUG_REG0__SPARE1_MASK 0x200
-#define IA_DEBUG_REG0__SPARE1__SHIFT 0x9
-#define IA_DEBUG_REG0__dma_grp_valid_MASK 0x400
-#define IA_DEBUG_REG0__dma_grp_valid__SHIFT 0xa
-#define IA_DEBUG_REG0__grp_dma_read_MASK 0x800
-#define IA_DEBUG_REG0__grp_dma_read__SHIFT 0xb
-#define IA_DEBUG_REG0__dma_grp_hp_valid_MASK 0x1000
-#define IA_DEBUG_REG0__dma_grp_hp_valid__SHIFT 0xc
-#define IA_DEBUG_REG0__grp_dma_hp_read_MASK 0x2000
-#define IA_DEBUG_REG0__grp_dma_hp_read__SHIFT 0xd
-#define IA_DEBUG_REG0__SPARE2_MASK 0xffc000
-#define IA_DEBUG_REG0__SPARE2__SHIFT 0xe
-#define IA_DEBUG_REG0__reg_clk_busy_MASK 0x1000000
-#define IA_DEBUG_REG0__reg_clk_busy__SHIFT 0x18
-#define IA_DEBUG_REG0__core_clk_busy_MASK 0x2000000
-#define IA_DEBUG_REG0__core_clk_busy__SHIFT 0x19
-#define IA_DEBUG_REG0__SPARE3_MASK 0x4000000
-#define IA_DEBUG_REG0__SPARE3__SHIFT 0x1a
-#define IA_DEBUG_REG0__SPARE4_MASK 0x8000000
-#define IA_DEBUG_REG0__SPARE4__SHIFT 0x1b
-#define IA_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000
-#define IA_DEBUG_REG0__sclk_reg_vld__SHIFT 0x1c
-#define IA_DEBUG_REG0__sclk_core_vld_MASK 0x20000000
-#define IA_DEBUG_REG0__sclk_core_vld__SHIFT 0x1d
-#define IA_DEBUG_REG0__SPARE5_MASK 0x40000000
-#define IA_DEBUG_REG0__SPARE5__SHIFT 0x1e
-#define IA_DEBUG_REG0__SPARE6_MASK 0x80000000
-#define IA_DEBUG_REG0__SPARE6__SHIFT 0x1f
-#define IA_DEBUG_REG1__dma_input_fifo_empty_MASK 0x1
-#define IA_DEBUG_REG1__dma_input_fifo_empty__SHIFT 0x0
-#define IA_DEBUG_REG1__dma_input_fifo_full_MASK 0x2
-#define IA_DEBUG_REG1__dma_input_fifo_full__SHIFT 0x1
-#define IA_DEBUG_REG1__start_new_packet_MASK 0x4
-#define IA_DEBUG_REG1__start_new_packet__SHIFT 0x2
-#define IA_DEBUG_REG1__dma_rdreq_dr_q_MASK 0x8
-#define IA_DEBUG_REG1__dma_rdreq_dr_q__SHIFT 0x3
-#define IA_DEBUG_REG1__dma_zero_indices_q_MASK 0x10
-#define IA_DEBUG_REG1__dma_zero_indices_q__SHIFT 0x4
-#define IA_DEBUG_REG1__dma_buf_type_q_MASK 0x60
-#define IA_DEBUG_REG1__dma_buf_type_q__SHIFT 0x5
-#define IA_DEBUG_REG1__dma_req_path_q_MASK 0x80
-#define IA_DEBUG_REG1__dma_req_path_q__SHIFT 0x7
-#define IA_DEBUG_REG1__discard_1st_chunk_MASK 0x100
-#define IA_DEBUG_REG1__discard_1st_chunk__SHIFT 0x8
-#define IA_DEBUG_REG1__discard_2nd_chunk_MASK 0x200
-#define IA_DEBUG_REG1__discard_2nd_chunk__SHIFT 0x9
-#define IA_DEBUG_REG1__second_tc_ret_data_q_MASK 0x400
-#define IA_DEBUG_REG1__second_tc_ret_data_q__SHIFT 0xa
-#define IA_DEBUG_REG1__dma_tc_ret_sel_q_MASK 0x800
-#define IA_DEBUG_REG1__dma_tc_ret_sel_q__SHIFT 0xb
-#define IA_DEBUG_REG1__last_rdreq_in_dma_op_MASK 0x1000
-#define IA_DEBUG_REG1__last_rdreq_in_dma_op__SHIFT 0xc
-#define IA_DEBUG_REG1__dma_mask_fifo_empty_MASK 0x2000
-#define IA_DEBUG_REG1__dma_mask_fifo_empty__SHIFT 0xd
-#define IA_DEBUG_REG1__dma_data_fifo_empty_q_MASK 0x4000
-#define IA_DEBUG_REG1__dma_data_fifo_empty_q__SHIFT 0xe
-#define IA_DEBUG_REG1__dma_data_fifo_full_MASK 0x8000
-#define IA_DEBUG_REG1__dma_data_fifo_full__SHIFT 0xf
-#define IA_DEBUG_REG1__dma_req_fifo_empty_MASK 0x10000
-#define IA_DEBUG_REG1__dma_req_fifo_empty__SHIFT 0x10
-#define IA_DEBUG_REG1__dma_req_fifo_full_MASK 0x20000
-#define IA_DEBUG_REG1__dma_req_fifo_full__SHIFT 0x11
-#define IA_DEBUG_REG1__stage2_dr_MASK 0x40000
-#define IA_DEBUG_REG1__stage2_dr__SHIFT 0x12
-#define IA_DEBUG_REG1__stage2_rtr_MASK 0x80000
-#define IA_DEBUG_REG1__stage2_rtr__SHIFT 0x13
-#define IA_DEBUG_REG1__stage3_dr_MASK 0x100000
-#define IA_DEBUG_REG1__stage3_dr__SHIFT 0x14
-#define IA_DEBUG_REG1__stage3_rtr_MASK 0x200000
-#define IA_DEBUG_REG1__stage3_rtr__SHIFT 0x15
-#define IA_DEBUG_REG1__stage4_dr_MASK 0x400000
-#define IA_DEBUG_REG1__stage4_dr__SHIFT 0x16
-#define IA_DEBUG_REG1__stage4_rtr_MASK 0x800000
-#define IA_DEBUG_REG1__stage4_rtr__SHIFT 0x17
-#define IA_DEBUG_REG1__dma_skid_fifo_empty_MASK 0x1000000
-#define IA_DEBUG_REG1__dma_skid_fifo_empty__SHIFT 0x18
-#define IA_DEBUG_REG1__dma_skid_fifo_full_MASK 0x2000000
-#define IA_DEBUG_REG1__dma_skid_fifo_full__SHIFT 0x19
-#define IA_DEBUG_REG1__dma_grp_valid_MASK 0x4000000
-#define IA_DEBUG_REG1__dma_grp_valid__SHIFT 0x1a
-#define IA_DEBUG_REG1__grp_dma_read_MASK 0x8000000
-#define IA_DEBUG_REG1__grp_dma_read__SHIFT 0x1b
-#define IA_DEBUG_REG1__current_data_valid_MASK 0x10000000
-#define IA_DEBUG_REG1__current_data_valid__SHIFT 0x1c
-#define IA_DEBUG_REG1__out_of_range_r2_q_MASK 0x20000000
-#define IA_DEBUG_REG1__out_of_range_r2_q__SHIFT 0x1d
-#define IA_DEBUG_REG1__dma_mask_fifo_we_MASK 0x40000000
-#define IA_DEBUG_REG1__dma_mask_fifo_we__SHIFT 0x1e
-#define IA_DEBUG_REG1__dma_ret_data_we_q_MASK 0x80000000
-#define IA_DEBUG_REG1__dma_ret_data_we_q__SHIFT 0x1f
-#define IA_DEBUG_REG2__hp_dma_input_fifo_empty_MASK 0x1
-#define IA_DEBUG_REG2__hp_dma_input_fifo_empty__SHIFT 0x0
-#define IA_DEBUG_REG2__hp_dma_input_fifo_full_MASK 0x2
-#define IA_DEBUG_REG2__hp_dma_input_fifo_full__SHIFT 0x1
-#define IA_DEBUG_REG2__hp_start_new_packet_MASK 0x4
-#define IA_DEBUG_REG2__hp_start_new_packet__SHIFT 0x2
-#define IA_DEBUG_REG2__hp_dma_rdreq_dr_q_MASK 0x8
-#define IA_DEBUG_REG2__hp_dma_rdreq_dr_q__SHIFT 0x3
-#define IA_DEBUG_REG2__hp_dma_zero_indices_q_MASK 0x10
-#define IA_DEBUG_REG2__hp_dma_zero_indices_q__SHIFT 0x4
-#define IA_DEBUG_REG2__hp_dma_buf_type_q_MASK 0x60
-#define IA_DEBUG_REG2__hp_dma_buf_type_q__SHIFT 0x5
-#define IA_DEBUG_REG2__hp_dma_req_path_q_MASK 0x80
-#define IA_DEBUG_REG2__hp_dma_req_path_q__SHIFT 0x7
-#define IA_DEBUG_REG2__hp_discard_1st_chunk_MASK 0x100
-#define IA_DEBUG_REG2__hp_discard_1st_chunk__SHIFT 0x8
-#define IA_DEBUG_REG2__hp_discard_2nd_chunk_MASK 0x200
-#define IA_DEBUG_REG2__hp_discard_2nd_chunk__SHIFT 0x9
-#define IA_DEBUG_REG2__hp_second_tc_ret_data_q_MASK 0x400
-#define IA_DEBUG_REG2__hp_second_tc_ret_data_q__SHIFT 0xa
-#define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q_MASK 0x800
-#define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q__SHIFT 0xb
-#define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op_MASK 0x1000
-#define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op__SHIFT 0xc
-#define IA_DEBUG_REG2__hp_dma_mask_fifo_empty_MASK 0x2000
-#define IA_DEBUG_REG2__hp_dma_mask_fifo_empty__SHIFT 0xd
-#define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q_MASK 0x4000
-#define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q__SHIFT 0xe
-#define IA_DEBUG_REG2__hp_dma_data_fifo_full_MASK 0x8000
-#define IA_DEBUG_REG2__hp_dma_data_fifo_full__SHIFT 0xf
-#define IA_DEBUG_REG2__hp_dma_req_fifo_empty_MASK 0x10000
-#define IA_DEBUG_REG2__hp_dma_req_fifo_empty__SHIFT 0x10
-#define IA_DEBUG_REG2__hp_dma_req_fifo_full_MASK 0x20000
-#define IA_DEBUG_REG2__hp_dma_req_fifo_full__SHIFT 0x11
-#define IA_DEBUG_REG2__hp_stage2_dr_MASK 0x40000
-#define IA_DEBUG_REG2__hp_stage2_dr__SHIFT 0x12
-#define IA_DEBUG_REG2__hp_stage2_rtr_MASK 0x80000
-#define IA_DEBUG_REG2__hp_stage2_rtr__SHIFT 0x13
-#define IA_DEBUG_REG2__hp_stage3_dr_MASK 0x100000
-#define IA_DEBUG_REG2__hp_stage3_dr__SHIFT 0x14
-#define IA_DEBUG_REG2__hp_stage3_rtr_MASK 0x200000
-#define IA_DEBUG_REG2__hp_stage3_rtr__SHIFT 0x15
-#define IA_DEBUG_REG2__hp_stage4_dr_MASK 0x400000
-#define IA_DEBUG_REG2__hp_stage4_dr__SHIFT 0x16
-#define IA_DEBUG_REG2__hp_stage4_rtr_MASK 0x800000
-#define IA_DEBUG_REG2__hp_stage4_rtr__SHIFT 0x17
-#define IA_DEBUG_REG2__hp_dma_skid_fifo_empty_MASK 0x1000000
-#define IA_DEBUG_REG2__hp_dma_skid_fifo_empty__SHIFT 0x18
-#define IA_DEBUG_REG2__hp_dma_skid_fifo_full_MASK 0x2000000
-#define IA_DEBUG_REG2__hp_dma_skid_fifo_full__SHIFT 0x19
-#define IA_DEBUG_REG2__hp_dma_grp_valid_MASK 0x4000000
-#define IA_DEBUG_REG2__hp_dma_grp_valid__SHIFT 0x1a
-#define IA_DEBUG_REG2__hp_grp_dma_read_MASK 0x8000000
-#define IA_DEBUG_REG2__hp_grp_dma_read__SHIFT 0x1b
-#define IA_DEBUG_REG2__hp_current_data_valid_MASK 0x10000000
-#define IA_DEBUG_REG2__hp_current_data_valid__SHIFT 0x1c
-#define IA_DEBUG_REG2__hp_out_of_range_r2_q_MASK 0x20000000
-#define IA_DEBUG_REG2__hp_out_of_range_r2_q__SHIFT 0x1d
-#define IA_DEBUG_REG2__hp_dma_mask_fifo_we_MASK 0x40000000
-#define IA_DEBUG_REG2__hp_dma_mask_fifo_we__SHIFT 0x1e
-#define IA_DEBUG_REG2__hp_dma_ret_data_we_q_MASK 0x80000000
-#define IA_DEBUG_REG2__hp_dma_ret_data_we_q__SHIFT 0x1f
-#define IA_DEBUG_REG3__dma_pipe0_rdreq_valid_MASK 0x1
-#define IA_DEBUG_REG3__dma_pipe0_rdreq_valid__SHIFT 0x0
-#define IA_DEBUG_REG3__dma_pipe0_rdreq_read_MASK 0x2
-#define IA_DEBUG_REG3__dma_pipe0_rdreq_read__SHIFT 0x1
-#define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out_MASK 0x4
-#define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out__SHIFT 0x2
-#define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out_MASK 0x8
-#define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out__SHIFT 0x3
-#define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out_MASK 0x10
-#define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out__SHIFT 0x4
-#define IA_DEBUG_REG3__grp_dma_draw_is_pipe0_MASK 0x20
-#define IA_DEBUG_REG3__grp_dma_draw_is_pipe0__SHIFT 0x5
-#define IA_DEBUG_REG3__must_service_pipe0_req_MASK 0x40
-#define IA_DEBUG_REG3__must_service_pipe0_req__SHIFT 0x6
-#define IA_DEBUG_REG3__send_pipe1_req_MASK 0x80
-#define IA_DEBUG_REG3__send_pipe1_req__SHIFT 0x7
-#define IA_DEBUG_REG3__dma_pipe1_rdreq_valid_MASK 0x100
-#define IA_DEBUG_REG3__dma_pipe1_rdreq_valid__SHIFT 0x8
-#define IA_DEBUG_REG3__dma_pipe1_rdreq_read_MASK 0x200
-#define IA_DEBUG_REG3__dma_pipe1_rdreq_read__SHIFT 0x9
-#define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out_MASK 0x400
-#define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out__SHIFT 0xa
-#define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out_MASK 0x800
-#define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out__SHIFT 0xb
-#define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out_MASK 0x1000
-#define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out__SHIFT 0xc
-#define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q_MASK 0x2000
-#define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q__SHIFT 0xd
-#define IA_DEBUG_REG3__mc_out_rtr_MASK 0x4000
-#define IA_DEBUG_REG3__mc_out_rtr__SHIFT 0xe
-#define IA_DEBUG_REG3__dma_rdreq_send_out_MASK 0x8000
-#define IA_DEBUG_REG3__dma_rdreq_send_out__SHIFT 0xf
-#define IA_DEBUG_REG3__pipe0_dr_MASK 0x10000
-#define IA_DEBUG_REG3__pipe0_dr__SHIFT 0x10
-#define IA_DEBUG_REG3__pipe0_rtr_MASK 0x20000
-#define IA_DEBUG_REG3__pipe0_rtr__SHIFT 0x11
-#define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q_MASK 0x40000
-#define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q__SHIFT 0x12
-#define IA_DEBUG_REG3__tc_out_rtr_MASK 0x80000
-#define IA_DEBUG_REG3__tc_out_rtr__SHIFT 0x13
-#define IA_DEBUG_REG3__pair0_valid_p1_MASK 0x100000
-#define IA_DEBUG_REG3__pair0_valid_p1__SHIFT 0x14
-#define IA_DEBUG_REG3__pair1_valid_p1_MASK 0x200000
-#define IA_DEBUG_REG3__pair1_valid_p1__SHIFT 0x15
-#define IA_DEBUG_REG3__pair2_valid_p1_MASK 0x400000
-#define IA_DEBUG_REG3__pair2_valid_p1__SHIFT 0x16
-#define IA_DEBUG_REG3__pair3_valid_p1_MASK 0x800000
-#define IA_DEBUG_REG3__pair3_valid_p1__SHIFT 0x17
-#define IA_DEBUG_REG3__tc_req_count_q_MASK 0x3000000
-#define IA_DEBUG_REG3__tc_req_count_q__SHIFT 0x18
-#define IA_DEBUG_REG3__discard_1st_chunk_MASK 0x4000000
-#define IA_DEBUG_REG3__discard_1st_chunk__SHIFT 0x1a
-#define IA_DEBUG_REG3__discard_2nd_chunk_MASK 0x8000000
-#define IA_DEBUG_REG3__discard_2nd_chunk__SHIFT 0x1b
-#define IA_DEBUG_REG3__last_tc_req_p1_MASK 0x10000000
-#define IA_DEBUG_REG3__last_tc_req_p1__SHIFT 0x1c
-#define IA_DEBUG_REG3__IA_TC_rdreq_send_out_MASK 0x20000000
-#define IA_DEBUG_REG3__IA_TC_rdreq_send_out__SHIFT 0x1d
-#define IA_DEBUG_REG3__TC_IA_rdret_valid_in_MASK 0x40000000
-#define IA_DEBUG_REG3__TC_IA_rdret_valid_in__SHIFT 0x1e
-#define IA_DEBUG_REG3__TAP_IA_rdret_vld_in_MASK 0x80000000
-#define IA_DEBUG_REG3__TAP_IA_rdret_vld_in__SHIFT 0x1f
-#define IA_DEBUG_REG4__pipe0_dr_MASK 0x1
-#define IA_DEBUG_REG4__pipe0_dr__SHIFT 0x0
-#define IA_DEBUG_REG4__pipe1_dr_MASK 0x2
-#define IA_DEBUG_REG4__pipe1_dr__SHIFT 0x1
-#define IA_DEBUG_REG4__pipe2_dr_MASK 0x4
-#define IA_DEBUG_REG4__pipe2_dr__SHIFT 0x2
-#define IA_DEBUG_REG4__pipe3_dr_MASK 0x8
-#define IA_DEBUG_REG4__pipe3_dr__SHIFT 0x3
-#define IA_DEBUG_REG4__pipe4_dr_MASK 0x10
-#define IA_DEBUG_REG4__pipe4_dr__SHIFT 0x4
-#define IA_DEBUG_REG4__pipe5_dr_MASK 0x20
-#define IA_DEBUG_REG4__pipe5_dr__SHIFT 0x5
-#define IA_DEBUG_REG4__grp_se0_fifo_empty_MASK 0x40
-#define IA_DEBUG_REG4__grp_se0_fifo_empty__SHIFT 0x6
-#define IA_DEBUG_REG4__grp_se0_fifo_full_MASK 0x80
-#define IA_DEBUG_REG4__grp_se0_fifo_full__SHIFT 0x7
-#define IA_DEBUG_REG4__pipe0_rtr_MASK 0x100
-#define IA_DEBUG_REG4__pipe0_rtr__SHIFT 0x8
-#define IA_DEBUG_REG4__pipe1_rtr_MASK 0x200
-#define IA_DEBUG_REG4__pipe1_rtr__SHIFT 0x9
-#define IA_DEBUG_REG4__pipe2_rtr_MASK 0x400
-#define IA_DEBUG_REG4__pipe2_rtr__SHIFT 0xa
-#define IA_DEBUG_REG4__pipe3_rtr_MASK 0x800
-#define IA_DEBUG_REG4__pipe3_rtr__SHIFT 0xb
-#define IA_DEBUG_REG4__pipe4_rtr_MASK 0x1000
-#define IA_DEBUG_REG4__pipe4_rtr__SHIFT 0xc
-#define IA_DEBUG_REG4__pipe5_rtr_MASK 0x2000
-#define IA_DEBUG_REG4__pipe5_rtr__SHIFT 0xd
-#define IA_DEBUG_REG4__ia_vgt_prim_rtr_q_MASK 0x4000
-#define IA_DEBUG_REG4__ia_vgt_prim_rtr_q__SHIFT 0xe
-#define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q_MASK 0x8000
-#define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q__SHIFT 0xf
-#define IA_DEBUG_REG4__di_major_mode_p1_q_MASK 0x10000
-#define IA_DEBUG_REG4__di_major_mode_p1_q__SHIFT 0x10
-#define IA_DEBUG_REG4__gs_mode_p1_q_MASK 0xe0000
-#define IA_DEBUG_REG4__gs_mode_p1_q__SHIFT 0x11
-#define IA_DEBUG_REG4__di_event_flag_p1_q_MASK 0x100000
-#define IA_DEBUG_REG4__di_event_flag_p1_q__SHIFT 0x14
-#define IA_DEBUG_REG4__di_state_sel_p1_q_MASK 0xe00000
-#define IA_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x15
-#define IA_DEBUG_REG4__draw_opaq_en_p1_q_MASK 0x1000000
-#define IA_DEBUG_REG4__draw_opaq_en_p1_q__SHIFT 0x18
-#define IA_DEBUG_REG4__draw_opaq_active_q_MASK 0x2000000
-#define IA_DEBUG_REG4__draw_opaq_active_q__SHIFT 0x19
-#define IA_DEBUG_REG4__di_source_select_p1_q_MASK 0xc000000
-#define IA_DEBUG_REG4__di_source_select_p1_q__SHIFT 0x1a
-#define IA_DEBUG_REG4__ready_to_read_di_MASK 0x10000000
-#define IA_DEBUG_REG4__ready_to_read_di__SHIFT 0x1c
-#define IA_DEBUG_REG4__di_first_group_of_draw_q_MASK 0x20000000
-#define IA_DEBUG_REG4__di_first_group_of_draw_q__SHIFT 0x1d
-#define IA_DEBUG_REG4__last_shift_of_draw_MASK 0x40000000
-#define IA_DEBUG_REG4__last_shift_of_draw__SHIFT 0x1e
-#define IA_DEBUG_REG4__current_shift_is_vect1_q_MASK 0x80000000
-#define IA_DEBUG_REG4__current_shift_is_vect1_q__SHIFT 0x1f
-#define IA_DEBUG_REG5__di_index_counter_q_15_0_MASK 0xffff
-#define IA_DEBUG_REG5__di_index_counter_q_15_0__SHIFT 0x0
-#define IA_DEBUG_REG5__instanceid_13_0_MASK 0x3fff0000
-#define IA_DEBUG_REG5__instanceid_13_0__SHIFT 0x10
-#define IA_DEBUG_REG5__draw_input_fifo_full_MASK 0x40000000
-#define IA_DEBUG_REG5__draw_input_fifo_full__SHIFT 0x1e
-#define IA_DEBUG_REG5__draw_input_fifo_empty_MASK 0x80000000
-#define IA_DEBUG_REG5__draw_input_fifo_empty__SHIFT 0x1f
-#define IA_DEBUG_REG6__current_shift_q_MASK 0xf
-#define IA_DEBUG_REG6__current_shift_q__SHIFT 0x0
-#define IA_DEBUG_REG6__current_stride_pre_MASK 0xf0
-#define IA_DEBUG_REG6__current_stride_pre__SHIFT 0x4
-#define IA_DEBUG_REG6__current_stride_q_MASK 0x1f00
-#define IA_DEBUG_REG6__current_stride_q__SHIFT 0x8
-#define IA_DEBUG_REG6__first_group_partial_MASK 0x2000
-#define IA_DEBUG_REG6__first_group_partial__SHIFT 0xd
-#define IA_DEBUG_REG6__second_group_partial_MASK 0x4000
-#define IA_DEBUG_REG6__second_group_partial__SHIFT 0xe
-#define IA_DEBUG_REG6__curr_prim_partial_MASK 0x8000
-#define IA_DEBUG_REG6__curr_prim_partial__SHIFT 0xf
-#define IA_DEBUG_REG6__next_stride_q_MASK 0x1f0000
-#define IA_DEBUG_REG6__next_stride_q__SHIFT 0x10
-#define IA_DEBUG_REG6__next_group_partial_MASK 0x200000
-#define IA_DEBUG_REG6__next_group_partial__SHIFT 0x15
-#define IA_DEBUG_REG6__after_group_partial_MASK 0x400000
-#define IA_DEBUG_REG6__after_group_partial__SHIFT 0x16
-#define IA_DEBUG_REG6__extract_group_MASK 0x800000
-#define IA_DEBUG_REG6__extract_group__SHIFT 0x17
-#define IA_DEBUG_REG6__grp_shift_debug_data_MASK 0xff000000
-#define IA_DEBUG_REG6__grp_shift_debug_data__SHIFT 0x18
-#define IA_DEBUG_REG7__reset_indx_state_q_MASK 0xf
-#define IA_DEBUG_REG7__reset_indx_state_q__SHIFT 0x0
-#define IA_DEBUG_REG7__shift_vect_valid_p2_q_MASK 0xf0
-#define IA_DEBUG_REG7__shift_vect_valid_p2_q__SHIFT 0x4
-#define IA_DEBUG_REG7__shift_vect1_valid_p2_q_MASK 0xf00
-#define IA_DEBUG_REG7__shift_vect1_valid_p2_q__SHIFT 0x8
-#define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q_MASK 0xf000
-#define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q__SHIFT 0xc
-#define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q_MASK 0xf0000
-#define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q__SHIFT 0x10
-#define IA_DEBUG_REG7__num_indx_in_group_p2_q_MASK 0x700000
-#define IA_DEBUG_REG7__num_indx_in_group_p2_q__SHIFT 0x14
-#define IA_DEBUG_REG7__last_group_of_draw_p2_q_MASK 0x800000
-#define IA_DEBUG_REG7__last_group_of_draw_p2_q__SHIFT 0x17
-#define IA_DEBUG_REG7__shift_event_flag_p2_q_MASK 0x1000000
-#define IA_DEBUG_REG7__shift_event_flag_p2_q__SHIFT 0x18
-#define IA_DEBUG_REG7__indx_shift_is_one_p2_q_MASK 0x2000000
-#define IA_DEBUG_REG7__indx_shift_is_one_p2_q__SHIFT 0x19
-#define IA_DEBUG_REG7__indx_shift_is_two_p2_q_MASK 0x4000000
-#define IA_DEBUG_REG7__indx_shift_is_two_p2_q__SHIFT 0x1a
-#define IA_DEBUG_REG7__indx_stride_is_four_p2_q_MASK 0x8000000
-#define IA_DEBUG_REG7__indx_stride_is_four_p2_q__SHIFT 0x1b
-#define IA_DEBUG_REG7__shift_prim1_reset_p3_q_MASK 0x10000000
-#define IA_DEBUG_REG7__shift_prim1_reset_p3_q__SHIFT 0x1c
-#define IA_DEBUG_REG7__shift_prim1_partial_p3_q_MASK 0x20000000
-#define IA_DEBUG_REG7__shift_prim1_partial_p3_q__SHIFT 0x1d
-#define IA_DEBUG_REG7__shift_prim0_reset_p3_q_MASK 0x40000000
-#define IA_DEBUG_REG7__shift_prim0_reset_p3_q__SHIFT 0x1e
-#define IA_DEBUG_REG7__shift_prim0_partial_p3_q_MASK 0x80000000
-#define IA_DEBUG_REG7__shift_prim0_partial_p3_q__SHIFT 0x1f
-#define IA_DEBUG_REG8__di_prim_type_p1_q_MASK 0x1f
-#define IA_DEBUG_REG8__di_prim_type_p1_q__SHIFT 0x0
-#define IA_DEBUG_REG8__two_cycle_xfer_p1_q_MASK 0x20
-#define IA_DEBUG_REG8__two_cycle_xfer_p1_q__SHIFT 0x5
-#define IA_DEBUG_REG8__two_prim_input_p1_q_MASK 0x40
-#define IA_DEBUG_REG8__two_prim_input_p1_q__SHIFT 0x6
-#define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q_MASK 0x80
-#define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q__SHIFT 0x7
-#define IA_DEBUG_REG8__last_group_of_inst_p5_q_MASK 0x100
-#define IA_DEBUG_REG8__last_group_of_inst_p5_q__SHIFT 0x8
-#define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q_MASK 0x200
-#define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q__SHIFT 0x9
-#define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q_MASK 0x400
-#define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q__SHIFT 0xa
-#define IA_DEBUG_REG8__grp_continued_MASK 0x800
-#define IA_DEBUG_REG8__grp_continued__SHIFT 0xb
-#define IA_DEBUG_REG8__grp_state_sel_MASK 0x7000
-#define IA_DEBUG_REG8__grp_state_sel__SHIFT 0xc
-#define IA_DEBUG_REG8__grp_sub_prim_type_MASK 0x1f8000
-#define IA_DEBUG_REG8__grp_sub_prim_type__SHIFT 0xf
-#define IA_DEBUG_REG8__grp_output_path_MASK 0xe00000
-#define IA_DEBUG_REG8__grp_output_path__SHIFT 0x15
-#define IA_DEBUG_REG8__grp_null_primitive_MASK 0x1000000
-#define IA_DEBUG_REG8__grp_null_primitive__SHIFT 0x18
-#define IA_DEBUG_REG8__grp_eop_MASK 0x2000000
-#define IA_DEBUG_REG8__grp_eop__SHIFT 0x19
-#define IA_DEBUG_REG8__grp_eopg_MASK 0x4000000
-#define IA_DEBUG_REG8__grp_eopg__SHIFT 0x1a
-#define IA_DEBUG_REG8__grp_event_flag_MASK 0x8000000
-#define IA_DEBUG_REG8__grp_event_flag__SHIFT 0x1b
-#define IA_DEBUG_REG8__grp_components_valid_MASK 0xf0000000
-#define IA_DEBUG_REG8__grp_components_valid__SHIFT 0x1c
-#define IA_DEBUG_REG9__send_to_se1_p6_MASK 0x1
-#define IA_DEBUG_REG9__send_to_se1_p6__SHIFT 0x0
-#define IA_DEBUG_REG9__gfx_se_switch_p6_MASK 0x2
-#define IA_DEBUG_REG9__gfx_se_switch_p6__SHIFT 0x1
-#define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6_MASK 0x4
-#define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6__SHIFT 0x2
-#define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6_MASK 0x8
-#define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6__SHIFT 0x3
-#define IA_DEBUG_REG9__prim1_eoi_p6_MASK 0x10
-#define IA_DEBUG_REG9__prim1_eoi_p6__SHIFT 0x4
-#define IA_DEBUG_REG9__prim0_eoi_p6_MASK 0x20
-#define IA_DEBUG_REG9__prim0_eoi_p6__SHIFT 0x5
-#define IA_DEBUG_REG9__prim1_valid_eopg_p6_MASK 0x40
-#define IA_DEBUG_REG9__prim1_valid_eopg_p6__SHIFT 0x6
-#define IA_DEBUG_REG9__prim0_valid_eopg_p6_MASK 0x80
-#define IA_DEBUG_REG9__prim0_valid_eopg_p6__SHIFT 0x7
-#define IA_DEBUG_REG9__prim1_to_other_se_p6_MASK 0x100
-#define IA_DEBUG_REG9__prim1_to_other_se_p6__SHIFT 0x8
-#define IA_DEBUG_REG9__eopg_on_last_prim_p6_MASK 0x200
-#define IA_DEBUG_REG9__eopg_on_last_prim_p6__SHIFT 0x9
-#define IA_DEBUG_REG9__eopg_between_prims_p6_MASK 0x400
-#define IA_DEBUG_REG9__eopg_between_prims_p6__SHIFT 0xa
-#define IA_DEBUG_REG9__prim_count_eq_group_size_p6_MASK 0x800
-#define IA_DEBUG_REG9__prim_count_eq_group_size_p6__SHIFT 0xb
-#define IA_DEBUG_REG9__prim_count_gt_group_size_p6_MASK 0x1000
-#define IA_DEBUG_REG9__prim_count_gt_group_size_p6__SHIFT 0xc
-#define IA_DEBUG_REG9__two_prim_output_p5_q_MASK 0x2000
-#define IA_DEBUG_REG9__two_prim_output_p5_q__SHIFT 0xd
-#define IA_DEBUG_REG9__SPARE0_MASK 0x4000
-#define IA_DEBUG_REG9__SPARE0__SHIFT 0xe
-#define IA_DEBUG_REG9__SPARE1_MASK 0x8000
-#define IA_DEBUG_REG9__SPARE1__SHIFT 0xf
-#define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q_MASK 0x10000
-#define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q__SHIFT 0x10
-#define IA_DEBUG_REG9__prim1_xfer_p6_MASK 0x20000
-#define IA_DEBUG_REG9__prim1_xfer_p6__SHIFT 0x11
-#define IA_DEBUG_REG9__grp_se1_fifo_empty_MASK 0x40000
-#define IA_DEBUG_REG9__grp_se1_fifo_empty__SHIFT 0x12
-#define IA_DEBUG_REG9__grp_se1_fifo_full_MASK 0x80000
-#define IA_DEBUG_REG9__grp_se1_fifo_full__SHIFT 0x13
-#define IA_DEBUG_REG9__prim_counter_q_MASK 0xfff00000
-#define IA_DEBUG_REG9__prim_counter_q__SHIFT 0x14
-#define VGT_DEBUG_REG0__vgt_busy_extended_MASK 0x1
-#define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT 0x0
-#define VGT_DEBUG_REG0__SPARE9_MASK 0x2
-#define VGT_DEBUG_REG0__SPARE9__SHIFT 0x1
-#define VGT_DEBUG_REG0__vgt_busy_MASK 0x4
-#define VGT_DEBUG_REG0__vgt_busy__SHIFT 0x2
-#define VGT_DEBUG_REG0__SPARE8_MASK 0x8
-#define VGT_DEBUG_REG0__SPARE8__SHIFT 0x3
-#define VGT_DEBUG_REG0__SPARE7_MASK 0x10
-#define VGT_DEBUG_REG0__SPARE7__SHIFT 0x4
-#define VGT_DEBUG_REG0__SPARE6_MASK 0x20
-#define VGT_DEBUG_REG0__SPARE6__SHIFT 0x5
-#define VGT_DEBUG_REG0__SPARE5_MASK 0x40
-#define VGT_DEBUG_REG0__SPARE5__SHIFT 0x6
-#define VGT_DEBUG_REG0__SPARE4_MASK 0x80
-#define VGT_DEBUG_REG0__SPARE4__SHIFT 0x7
-#define VGT_DEBUG_REG0__pi_busy_MASK 0x100
-#define VGT_DEBUG_REG0__pi_busy__SHIFT 0x8
-#define VGT_DEBUG_REG0__vr_pi_busy_MASK 0x200
-#define VGT_DEBUG_REG0__vr_pi_busy__SHIFT 0x9
-#define VGT_DEBUG_REG0__pt_pi_busy_MASK 0x400
-#define VGT_DEBUG_REG0__pt_pi_busy__SHIFT 0xa
-#define VGT_DEBUG_REG0__te_pi_busy_MASK 0x800
-#define VGT_DEBUG_REG0__te_pi_busy__SHIFT 0xb
-#define VGT_DEBUG_REG0__gs_busy_MASK 0x1000
-#define VGT_DEBUG_REG0__gs_busy__SHIFT 0xc
-#define VGT_DEBUG_REG0__rcm_busy_MASK 0x2000
-#define VGT_DEBUG_REG0__rcm_busy__SHIFT 0xd
-#define VGT_DEBUG_REG0__tm_busy_MASK 0x4000
-#define VGT_DEBUG_REG0__tm_busy__SHIFT 0xe
-#define VGT_DEBUG_REG0__cm_busy_MASK 0x8000
-#define VGT_DEBUG_REG0__cm_busy__SHIFT 0xf
-#define VGT_DEBUG_REG0__gog_busy_MASK 0x10000
-#define VGT_DEBUG_REG0__gog_busy__SHIFT 0x10
-#define VGT_DEBUG_REG0__frmt_busy_MASK 0x20000
-#define VGT_DEBUG_REG0__frmt_busy__SHIFT 0x11
-#define VGT_DEBUG_REG0__SPARE10_MASK 0x40000
-#define VGT_DEBUG_REG0__SPARE10__SHIFT 0x12
-#define VGT_DEBUG_REG0__te11_pi_busy_MASK 0x80000
-#define VGT_DEBUG_REG0__te11_pi_busy__SHIFT 0x13
-#define VGT_DEBUG_REG0__SPARE3_MASK 0x100000
-#define VGT_DEBUG_REG0__SPARE3__SHIFT 0x14
-#define VGT_DEBUG_REG0__combined_out_busy_MASK 0x200000
-#define VGT_DEBUG_REG0__combined_out_busy__SHIFT 0x15
-#define VGT_DEBUG_REG0__spi_vs_interfaces_busy_MASK 0x400000
-#define VGT_DEBUG_REG0__spi_vs_interfaces_busy__SHIFT 0x16
-#define VGT_DEBUG_REG0__pa_interfaces_busy_MASK 0x800000
-#define VGT_DEBUG_REG0__pa_interfaces_busy__SHIFT 0x17
-#define VGT_DEBUG_REG0__reg_clk_busy_MASK 0x1000000
-#define VGT_DEBUG_REG0__reg_clk_busy__SHIFT 0x18
-#define VGT_DEBUG_REG0__SPARE2_MASK 0x2000000
-#define VGT_DEBUG_REG0__SPARE2__SHIFT 0x19
-#define VGT_DEBUG_REG0__core_clk_busy_MASK 0x4000000
-#define VGT_DEBUG_REG0__core_clk_busy__SHIFT 0x1a
-#define VGT_DEBUG_REG0__gs_clk_busy_MASK 0x8000000
-#define VGT_DEBUG_REG0__gs_clk_busy__SHIFT 0x1b
-#define VGT_DEBUG_REG0__SPARE1_MASK 0x10000000
-#define VGT_DEBUG_REG0__SPARE1__SHIFT 0x1c
-#define VGT_DEBUG_REG0__sclk_core_vld_MASK 0x20000000
-#define VGT_DEBUG_REG0__sclk_core_vld__SHIFT 0x1d
-#define VGT_DEBUG_REG0__sclk_gs_vld_MASK 0x40000000
-#define VGT_DEBUG_REG0__sclk_gs_vld__SHIFT 0x1e
-#define VGT_DEBUG_REG0__SPARE0_MASK 0x80000000
-#define VGT_DEBUG_REG0__SPARE0__SHIFT 0x1f
-#define VGT_DEBUG_REG1__SPARE9_MASK 0x1
-#define VGT_DEBUG_REG1__SPARE9__SHIFT 0x0
-#define VGT_DEBUG_REG1__SPARE8_MASK 0x2
-#define VGT_DEBUG_REG1__SPARE8__SHIFT 0x1
-#define VGT_DEBUG_REG1__SPARE7_MASK 0x4
-#define VGT_DEBUG_REG1__SPARE7__SHIFT 0x2
-#define VGT_DEBUG_REG1__SPARE6_MASK 0x8
-#define VGT_DEBUG_REG1__SPARE6__SHIFT 0x3
-#define VGT_DEBUG_REG1__SPARE5_MASK 0x10
-#define VGT_DEBUG_REG1__SPARE5__SHIFT 0x4
-#define VGT_DEBUG_REG1__SPARE4_MASK 0x20
-#define VGT_DEBUG_REG1__SPARE4__SHIFT 0x5
-#define VGT_DEBUG_REG1__SPARE3_MASK 0x40
-#define VGT_DEBUG_REG1__SPARE3__SHIFT 0x6
-#define VGT_DEBUG_REG1__SPARE2_MASK 0x80
-#define VGT_DEBUG_REG1__SPARE2__SHIFT 0x7
-#define VGT_DEBUG_REG1__SPARE1_MASK 0x100
-#define VGT_DEBUG_REG1__SPARE1__SHIFT 0x8
-#define VGT_DEBUG_REG1__SPARE0_MASK 0x200
-#define VGT_DEBUG_REG1__SPARE0__SHIFT 0x9
-#define VGT_DEBUG_REG1__pi_vr_valid_MASK 0x400
-#define VGT_DEBUG_REG1__pi_vr_valid__SHIFT 0xa
-#define VGT_DEBUG_REG1__vr_pi_read_MASK 0x800
-#define VGT_DEBUG_REG1__vr_pi_read__SHIFT 0xb
-#define VGT_DEBUG_REG1__pi_pt_valid_MASK 0x1000
-#define VGT_DEBUG_REG1__pi_pt_valid__SHIFT 0xc
-#define VGT_DEBUG_REG1__pt_pi_read_MASK 0x2000
-#define VGT_DEBUG_REG1__pt_pi_read__SHIFT 0xd
-#define VGT_DEBUG_REG1__pi_te_valid_MASK 0x4000
-#define VGT_DEBUG_REG1__pi_te_valid__SHIFT 0xe
-#define VGT_DEBUG_REG1__te_grp_read_MASK 0x8000
-#define VGT_DEBUG_REG1__te_grp_read__SHIFT 0xf
-#define VGT_DEBUG_REG1__vr_out_indx_valid_MASK 0x10000
-#define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT 0x10
-#define VGT_DEBUG_REG1__SPARE12_MASK 0x20000
-#define VGT_DEBUG_REG1__SPARE12__SHIFT 0x11
-#define VGT_DEBUG_REG1__vr_out_prim_valid_MASK 0x40000
-#define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT 0x12
-#define VGT_DEBUG_REG1__SPARE11_MASK 0x80000
-#define VGT_DEBUG_REG1__SPARE11__SHIFT 0x13
-#define VGT_DEBUG_REG1__pt_out_indx_valid_MASK 0x100000
-#define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT 0x14
-#define VGT_DEBUG_REG1__SPARE10_MASK 0x200000
-#define VGT_DEBUG_REG1__SPARE10__SHIFT 0x15
-#define VGT_DEBUG_REG1__pt_out_prim_valid_MASK 0x400000
-#define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT 0x16
-#define VGT_DEBUG_REG1__SPARE23_MASK 0x800000
-#define VGT_DEBUG_REG1__SPARE23__SHIFT 0x17
-#define VGT_DEBUG_REG1__te_out_data_valid_MASK 0x1000000
-#define VGT_DEBUG_REG1__te_out_data_valid__SHIFT 0x18
-#define VGT_DEBUG_REG1__SPARE25_MASK 0x2000000
-#define VGT_DEBUG_REG1__SPARE25__SHIFT 0x19
-#define VGT_DEBUG_REG1__pi_gs_valid_MASK 0x4000000
-#define VGT_DEBUG_REG1__pi_gs_valid__SHIFT 0x1a
-#define VGT_DEBUG_REG1__gs_pi_read_MASK 0x8000000
-#define VGT_DEBUG_REG1__gs_pi_read__SHIFT 0x1b
-#define VGT_DEBUG_REG1__gog_out_indx_valid_MASK 0x10000000
-#define VGT_DEBUG_REG1__gog_out_indx_valid__SHIFT 0x1c
-#define VGT_DEBUG_REG1__out_indx_read_MASK 0x20000000
-#define VGT_DEBUG_REG1__out_indx_read__SHIFT 0x1d
-#define VGT_DEBUG_REG1__gog_out_prim_valid_MASK 0x40000000
-#define VGT_DEBUG_REG1__gog_out_prim_valid__SHIFT 0x1e
-#define VGT_DEBUG_REG1__out_prim_read_MASK 0x80000000
-#define VGT_DEBUG_REG1__out_prim_read__SHIFT 0x1f
-#define VGT_DEBUG_REG2__hs_grp_busy_MASK 0x1
-#define VGT_DEBUG_REG2__hs_grp_busy__SHIFT 0x0
-#define VGT_DEBUG_REG2__hs_noif_busy_MASK 0x2
-#define VGT_DEBUG_REG2__hs_noif_busy__SHIFT 0x1
-#define VGT_DEBUG_REG2__tfmmIsBusy_MASK 0x4
-#define VGT_DEBUG_REG2__tfmmIsBusy__SHIFT 0x2
-#define VGT_DEBUG_REG2__lsVertIfBusy_0_MASK 0x8
-#define VGT_DEBUG_REG2__lsVertIfBusy_0__SHIFT 0x3
-#define VGT_DEBUG_REG2__te11_hs_tess_input_rtr_MASK 0x10
-#define VGT_DEBUG_REG2__te11_hs_tess_input_rtr__SHIFT 0x4
-#define VGT_DEBUG_REG2__lsWaveIfBusy_0_MASK 0x20
-#define VGT_DEBUG_REG2__lsWaveIfBusy_0__SHIFT 0x5
-#define VGT_DEBUG_REG2__hs_te11_tess_input_rts_MASK 0x40
-#define VGT_DEBUG_REG2__hs_te11_tess_input_rts__SHIFT 0x6
-#define VGT_DEBUG_REG2__grpModBusy_MASK 0x80
-#define VGT_DEBUG_REG2__grpModBusy__SHIFT 0x7
-#define VGT_DEBUG_REG2__lsVertFifoEmpty_MASK 0x100
-#define VGT_DEBUG_REG2__lsVertFifoEmpty__SHIFT 0x8
-#define VGT_DEBUG_REG2__lsWaveFifoEmpty_MASK 0x200
-#define VGT_DEBUG_REG2__lsWaveFifoEmpty__SHIFT 0x9
-#define VGT_DEBUG_REG2__hsVertFifoEmpty_MASK 0x400
-#define VGT_DEBUG_REG2__hsVertFifoEmpty__SHIFT 0xa
-#define VGT_DEBUG_REG2__hsWaveFifoEmpty_MASK 0x800
-#define VGT_DEBUG_REG2__hsWaveFifoEmpty__SHIFT 0xb
-#define VGT_DEBUG_REG2__hsInputFifoEmpty_MASK 0x1000
-#define VGT_DEBUG_REG2__hsInputFifoEmpty__SHIFT 0xc
-#define VGT_DEBUG_REG2__hsTifFifoEmpty_MASK 0x2000
-#define VGT_DEBUG_REG2__hsTifFifoEmpty__SHIFT 0xd
-#define VGT_DEBUG_REG2__lsVertFifoFull_MASK 0x4000
-#define VGT_DEBUG_REG2__lsVertFifoFull__SHIFT 0xe
-#define VGT_DEBUG_REG2__lsWaveFifoFull_MASK 0x8000
-#define VGT_DEBUG_REG2__lsWaveFifoFull__SHIFT 0xf
-#define VGT_DEBUG_REG2__hsVertFifoFull_MASK 0x10000
-#define VGT_DEBUG_REG2__hsVertFifoFull__SHIFT 0x10
-#define VGT_DEBUG_REG2__hsWaveFifoFull_MASK 0x20000
-#define VGT_DEBUG_REG2__hsWaveFifoFull__SHIFT 0x11
-#define VGT_DEBUG_REG2__hsInputFifoFull_MASK 0x40000
-#define VGT_DEBUG_REG2__hsInputFifoFull__SHIFT 0x12
-#define VGT_DEBUG_REG2__hsTifFifoFull_MASK 0x80000
-#define VGT_DEBUG_REG2__hsTifFifoFull__SHIFT 0x13
-#define VGT_DEBUG_REG2__p0_rtr_MASK 0x100000
-#define VGT_DEBUG_REG2__p0_rtr__SHIFT 0x14
-#define VGT_DEBUG_REG2__p1_rtr_MASK 0x200000
-#define VGT_DEBUG_REG2__p1_rtr__SHIFT 0x15
-#define VGT_DEBUG_REG2__p0_dr_MASK 0x400000
-#define VGT_DEBUG_REG2__p0_dr__SHIFT 0x16
-#define VGT_DEBUG_REG2__p1_dr_MASK 0x800000
-#define VGT_DEBUG_REG2__p1_dr__SHIFT 0x17
-#define VGT_DEBUG_REG2__p0_rts_MASK 0x1000000
-#define VGT_DEBUG_REG2__p0_rts__SHIFT 0x18
-#define VGT_DEBUG_REG2__p1_rts_MASK 0x2000000
-#define VGT_DEBUG_REG2__p1_rts__SHIFT 0x19
-#define VGT_DEBUG_REG2__ls_sh_id_MASK 0x4000000
-#define VGT_DEBUG_REG2__ls_sh_id__SHIFT 0x1a
-#define VGT_DEBUG_REG2__lsFwaveFlag_MASK 0x8000000
-#define VGT_DEBUG_REG2__lsFwaveFlag__SHIFT 0x1b
-#define VGT_DEBUG_REG2__lsWaveSendFlush_MASK 0x10000000
-#define VGT_DEBUG_REG2__lsWaveSendFlush__SHIFT 0x1c
-#define VGT_DEBUG_REG2__SPARE_MASK 0xe0000000
-#define VGT_DEBUG_REG2__SPARE__SHIFT 0x1d
-#define VGT_DEBUG_REG3__lsTgRelInd_MASK 0xfff
-#define VGT_DEBUG_REG3__lsTgRelInd__SHIFT 0x0
-#define VGT_DEBUG_REG3__lsWaveRelInd_MASK 0x3f000
-#define VGT_DEBUG_REG3__lsWaveRelInd__SHIFT 0xc
-#define VGT_DEBUG_REG3__lsPatchCnt_MASK 0x3fc0000
-#define VGT_DEBUG_REG3__lsPatchCnt__SHIFT 0x12
-#define VGT_DEBUG_REG3__hsWaveRelInd_MASK 0xfc000000
-#define VGT_DEBUG_REG3__hsWaveRelInd__SHIFT 0x1a
-#define VGT_DEBUG_REG4__hsPatchCnt_MASK 0xff
-#define VGT_DEBUG_REG4__hsPatchCnt__SHIFT 0x0
-#define VGT_DEBUG_REG4__hsPrimId_15_0_MASK 0xffff00
-#define VGT_DEBUG_REG4__hsPrimId_15_0__SHIFT 0x8
-#define VGT_DEBUG_REG4__hsCpCnt_MASK 0x1f000000
-#define VGT_DEBUG_REG4__hsCpCnt__SHIFT 0x18
-#define VGT_DEBUG_REG4__hsWaveSendFlush_MASK 0x20000000
-#define VGT_DEBUG_REG4__hsWaveSendFlush__SHIFT 0x1d
-#define VGT_DEBUG_REG4__hsFwaveFlag_MASK 0x40000000
-#define VGT_DEBUG_REG4__hsFwaveFlag__SHIFT 0x1e
-#define VGT_DEBUG_REG4__SPARE_MASK 0x80000000
-#define VGT_DEBUG_REG4__SPARE__SHIFT 0x1f
-#define VGT_DEBUG_REG5__SPARE4_MASK 0x7
-#define VGT_DEBUG_REG5__SPARE4__SHIFT 0x0
-#define VGT_DEBUG_REG5__hsWaveCreditCnt_0_MASK 0xf8
-#define VGT_DEBUG_REG5__hsWaveCreditCnt_0__SHIFT 0x3
-#define VGT_DEBUG_REG5__SPARE3_MASK 0x700
-#define VGT_DEBUG_REG5__SPARE3__SHIFT 0x8
-#define VGT_DEBUG_REG5__hsVertCreditCnt_0_MASK 0xf800
-#define VGT_DEBUG_REG5__hsVertCreditCnt_0__SHIFT 0xb
-#define VGT_DEBUG_REG5__SPARE2_MASK 0x70000
-#define VGT_DEBUG_REG5__SPARE2__SHIFT 0x10
-#define VGT_DEBUG_REG5__lsWaveCreditCnt_0_MASK 0xf80000
-#define VGT_DEBUG_REG5__lsWaveCreditCnt_0__SHIFT 0x13
-#define VGT_DEBUG_REG5__SPARE1_MASK 0x7000000
-#define VGT_DEBUG_REG5__SPARE1__SHIFT 0x18
-#define VGT_DEBUG_REG5__lsVertCreditCnt_0_MASK 0xf8000000
-#define VGT_DEBUG_REG5__lsVertCreditCnt_0__SHIFT 0x1b
-#define VGT_DEBUG_REG6__debug_BASE_MASK 0xffff
-#define VGT_DEBUG_REG6__debug_BASE__SHIFT 0x0
-#define VGT_DEBUG_REG6__debug_SIZE_MASK 0xffff0000
-#define VGT_DEBUG_REG6__debug_SIZE__SHIFT 0x10
-#define VGT_DEBUG_REG7__debug_tfmmFifoEmpty_MASK 0x1
-#define VGT_DEBUG_REG7__debug_tfmmFifoEmpty__SHIFT 0x0
-#define VGT_DEBUG_REG7__debug_tfmmFifoFull_MASK 0x2
-#define VGT_DEBUG_REG7__debug_tfmmFifoFull__SHIFT 0x1
-#define VGT_DEBUG_REG7__hs_pipe0_dr_MASK 0x4
-#define VGT_DEBUG_REG7__hs_pipe0_dr__SHIFT 0x2
-#define VGT_DEBUG_REG7__hs_pipe0_rtr_MASK 0x8
-#define VGT_DEBUG_REG7__hs_pipe0_rtr__SHIFT 0x3
-#define VGT_DEBUG_REG7__hs_pipe1_rtr_MASK 0x10
-#define VGT_DEBUG_REG7__hs_pipe1_rtr__SHIFT 0x4
-#define VGT_DEBUG_REG7__SPARE_MASK 0xffe0
-#define VGT_DEBUG_REG7__SPARE__SHIFT 0x5
-#define VGT_DEBUG_REG7__TF_addr_MASK 0xffff0000
-#define VGT_DEBUG_REG7__TF_addr__SHIFT 0x10
-#define VGT_DEBUG_REG8__rcm_busy_q_MASK 0x1
-#define VGT_DEBUG_REG8__rcm_busy_q__SHIFT 0x0
-#define VGT_DEBUG_REG8__rcm_noif_busy_q_MASK 0x2
-#define VGT_DEBUG_REG8__rcm_noif_busy_q__SHIFT 0x1
-#define VGT_DEBUG_REG8__r1_inst_rtr_MASK 0x4
-#define VGT_DEBUG_REG8__r1_inst_rtr__SHIFT 0x2
-#define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q_MASK 0x8
-#define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q__SHIFT 0x3
-#define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q_MASK 0x10
-#define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q__SHIFT 0x4
-#define VGT_DEBUG_REG8__gs_tbl_valid_r3_q_MASK 0x20
-#define VGT_DEBUG_REG8__gs_tbl_valid_r3_q__SHIFT 0x5
-#define VGT_DEBUG_REG8__valid_r0_q_MASK 0x40
-#define VGT_DEBUG_REG8__valid_r0_q__SHIFT 0x6
-#define VGT_DEBUG_REG8__valid_r1_q_MASK 0x80
-#define VGT_DEBUG_REG8__valid_r1_q__SHIFT 0x7
-#define VGT_DEBUG_REG8__valid_r2_MASK 0x100
-#define VGT_DEBUG_REG8__valid_r2__SHIFT 0x8
-#define VGT_DEBUG_REG8__valid_r2_q_MASK 0x200
-#define VGT_DEBUG_REG8__valid_r2_q__SHIFT 0x9
-#define VGT_DEBUG_REG8__r0_rtr_MASK 0x400
-#define VGT_DEBUG_REG8__r0_rtr__SHIFT 0xa
-#define VGT_DEBUG_REG8__r1_rtr_MASK 0x800
-#define VGT_DEBUG_REG8__r1_rtr__SHIFT 0xb
-#define VGT_DEBUG_REG8__r2_indx_rtr_MASK 0x1000
-#define VGT_DEBUG_REG8__r2_indx_rtr__SHIFT 0xc
-#define VGT_DEBUG_REG8__r2_rtr_MASK 0x2000
-#define VGT_DEBUG_REG8__r2_rtr__SHIFT 0xd
-#define VGT_DEBUG_REG8__es_gs_rtr_MASK 0x4000
-#define VGT_DEBUG_REG8__es_gs_rtr__SHIFT 0xe
-#define VGT_DEBUG_REG8__gs_event_fifo_rtr_MASK 0x8000
-#define VGT_DEBUG_REG8__gs_event_fifo_rtr__SHIFT 0xf
-#define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr_MASK 0x10000
-#define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr__SHIFT 0x10
-#define VGT_DEBUG_REG8__gs_tbl_r3_rtr_MASK 0x20000
-#define VGT_DEBUG_REG8__gs_tbl_r3_rtr__SHIFT 0x11
-#define VGT_DEBUG_REG8__prim_skid_fifo_empty_MASK 0x40000
-#define VGT_DEBUG_REG8__prim_skid_fifo_empty__SHIFT 0x12
-#define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q_MASK 0x80000
-#define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q__SHIFT 0x13
-#define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr_MASK 0x100000
-#define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr__SHIFT 0x14
-#define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr_MASK 0x200000
-#define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr__SHIFT 0x15
-#define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q_MASK 0x400000
-#define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q__SHIFT 0x16
-#define VGT_DEBUG_REG8__r2_no_bp_rtr_MASK 0x800000
-#define VGT_DEBUG_REG8__r2_no_bp_rtr__SHIFT 0x17
-#define VGT_DEBUG_REG8__hold_for_es_flush_MASK 0x1000000
-#define VGT_DEBUG_REG8__hold_for_es_flush__SHIFT 0x18
-#define VGT_DEBUG_REG8__gs_event_fifo_empty_MASK 0x2000000
-#define VGT_DEBUG_REG8__gs_event_fifo_empty__SHIFT 0x19
-#define VGT_DEBUG_REG8__gsprim_buff_empty_q_MASK 0x4000000
-#define VGT_DEBUG_REG8__gsprim_buff_empty_q__SHIFT 0x1a
-#define VGT_DEBUG_REG8__gsprim_buff_full_q_MASK 0x8000000
-#define VGT_DEBUG_REG8__gsprim_buff_full_q__SHIFT 0x1b
-#define VGT_DEBUG_REG8__te_prim_fifo_empty_MASK 0x10000000
-#define VGT_DEBUG_REG8__te_prim_fifo_empty__SHIFT 0x1c
-#define VGT_DEBUG_REG8__te_prim_fifo_full_MASK 0x20000000
-#define VGT_DEBUG_REG8__te_prim_fifo_full__SHIFT 0x1d
-#define VGT_DEBUG_REG8__te_vert_fifo_empty_MASK 0x40000000
-#define VGT_DEBUG_REG8__te_vert_fifo_empty__SHIFT 0x1e
-#define VGT_DEBUG_REG8__te_vert_fifo_full_MASK 0x80000000
-#define VGT_DEBUG_REG8__te_vert_fifo_full__SHIFT 0x1f
-#define VGT_DEBUG_REG9__indices_to_send_r2_q_MASK 0x3
-#define VGT_DEBUG_REG9__indices_to_send_r2_q__SHIFT 0x0
-#define VGT_DEBUG_REG9__valid_indices_r3_MASK 0x4
-#define VGT_DEBUG_REG9__valid_indices_r3__SHIFT 0x2
-#define VGT_DEBUG_REG9__gs_eov_r3_MASK 0x8
-#define VGT_DEBUG_REG9__gs_eov_r3__SHIFT 0x3
-#define VGT_DEBUG_REG9__eop_indx_r3_MASK 0x10
-#define VGT_DEBUG_REG9__eop_indx_r3__SHIFT 0x4
-#define VGT_DEBUG_REG9__eop_prim_r3_MASK 0x20
-#define VGT_DEBUG_REG9__eop_prim_r3__SHIFT 0x5
-#define VGT_DEBUG_REG9__es_eov_r3_MASK 0x40
-#define VGT_DEBUG_REG9__es_eov_r3__SHIFT 0x6
-#define VGT_DEBUG_REG9__es_tbl_state_r3_q_0_MASK 0x80
-#define VGT_DEBUG_REG9__es_tbl_state_r3_q_0__SHIFT 0x7
-#define VGT_DEBUG_REG9__pending_es_send_r3_q_MASK 0x100
-#define VGT_DEBUG_REG9__pending_es_send_r3_q__SHIFT 0x8
-#define VGT_DEBUG_REG9__pending_es_flush_r3_MASK 0x200
-#define VGT_DEBUG_REG9__pending_es_flush_r3__SHIFT 0x9
-#define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0_MASK 0x400
-#define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0__SHIFT 0xa
-#define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q_MASK 0x3f800
-#define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q__SHIFT 0xb
-#define VGT_DEBUG_REG9__gs_tbl_eop_r3_q_MASK 0x40000
-#define VGT_DEBUG_REG9__gs_tbl_eop_r3_q__SHIFT 0x12
-#define VGT_DEBUG_REG9__gs_tbl_state_r3_q_MASK 0x380000
-#define VGT_DEBUG_REG9__gs_tbl_state_r3_q__SHIFT 0x13
-#define VGT_DEBUG_REG9__gs_pending_state_r3_q_MASK 0x400000
-#define VGT_DEBUG_REG9__gs_pending_state_r3_q__SHIFT 0x16
-#define VGT_DEBUG_REG9__invalidate_rb_roll_over_q_MASK 0x800000
-#define VGT_DEBUG_REG9__invalidate_rb_roll_over_q__SHIFT 0x17
-#define VGT_DEBUG_REG9__gs_instancing_state_q_MASK 0x1000000
-#define VGT_DEBUG_REG9__gs_instancing_state_q__SHIFT 0x18
-#define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0_MASK 0x2000000
-#define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0__SHIFT 0x19
-#define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0_MASK 0x4000000
-#define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0__SHIFT 0x1a
-#define VGT_DEBUG_REG9__pre_r0_rtr_MASK 0x8000000
-#define VGT_DEBUG_REG9__pre_r0_rtr__SHIFT 0x1b
-#define VGT_DEBUG_REG9__valid_r3_q_MASK 0x10000000
-#define VGT_DEBUG_REG9__valid_r3_q__SHIFT 0x1c
-#define VGT_DEBUG_REG9__valid_pre_r0_q_MASK 0x20000000
-#define VGT_DEBUG_REG9__valid_pre_r0_q__SHIFT 0x1d
-#define VGT_DEBUG_REG9__SPARE0_MASK 0x40000000
-#define VGT_DEBUG_REG9__SPARE0__SHIFT 0x1e
-#define VGT_DEBUG_REG9__off_chip_hs_r2_q_MASK 0x80000000
-#define VGT_DEBUG_REG9__off_chip_hs_r2_q__SHIFT 0x1f
-#define VGT_DEBUG_REG10__index_buffer_depth_r1_q_MASK 0x1f
-#define VGT_DEBUG_REG10__index_buffer_depth_r1_q__SHIFT 0x0
-#define VGT_DEBUG_REG10__eopg_r2_q_MASK 0x20
-#define VGT_DEBUG_REG10__eopg_r2_q__SHIFT 0x5
-#define VGT_DEBUG_REG10__eotg_r2_q_MASK 0x40
-#define VGT_DEBUG_REG10__eotg_r2_q__SHIFT 0x6
-#define VGT_DEBUG_REG10__onchip_gs_en_r0_q_MASK 0x180
-#define VGT_DEBUG_REG10__onchip_gs_en_r0_q__SHIFT 0x7
-#define VGT_DEBUG_REG10__SPARE2_MASK 0x600
-#define VGT_DEBUG_REG10__SPARE2__SHIFT 0x9
-#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq_MASK 0x800
-#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq__SHIFT 0xb
-#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q_MASK 0x1000
-#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q__SHIFT 0xc
-#define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0_MASK 0x7fe000
-#define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0__SHIFT 0xd
-#define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0_MASK 0xff800000
-#define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0__SHIFT 0x17
-#define VGT_DEBUG_REG11__tm_busy_q_MASK 0x1
-#define VGT_DEBUG_REG11__tm_busy_q__SHIFT 0x0
-#define VGT_DEBUG_REG11__tm_noif_busy_q_MASK 0x2
-#define VGT_DEBUG_REG11__tm_noif_busy_q__SHIFT 0x1
-#define VGT_DEBUG_REG11__tm_out_busy_q_MASK 0x4
-#define VGT_DEBUG_REG11__tm_out_busy_q__SHIFT 0x2
-#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy_MASK 0x8
-#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy__SHIFT 0x3
-#define VGT_DEBUG_REG11__vs_dealloc_tbl_busy_MASK 0x10
-#define VGT_DEBUG_REG11__vs_dealloc_tbl_busy__SHIFT 0x4
-#define VGT_DEBUG_REG11__SPARE1_MASK 0x20
-#define VGT_DEBUG_REG11__SPARE1__SHIFT 0x5
-#define VGT_DEBUG_REG11__spi_gsthread_fifo_busy_MASK 0x40
-#define VGT_DEBUG_REG11__spi_gsthread_fifo_busy__SHIFT 0x6
-#define VGT_DEBUG_REG11__spi_esthread_fifo_busy_MASK 0x80
-#define VGT_DEBUG_REG11__spi_esthread_fifo_busy__SHIFT 0x7
-#define VGT_DEBUG_REG11__hold_eswave_MASK 0x100
-#define VGT_DEBUG_REG11__hold_eswave__SHIFT 0x8
-#define VGT_DEBUG_REG11__es_rb_roll_over_r3_MASK 0x200
-#define VGT_DEBUG_REG11__es_rb_roll_over_r3__SHIFT 0x9
-#define VGT_DEBUG_REG11__counters_busy_r0_MASK 0x400
-#define VGT_DEBUG_REG11__counters_busy_r0__SHIFT 0xa
-#define VGT_DEBUG_REG11__counters_avail_r0_MASK 0x800
-#define VGT_DEBUG_REG11__counters_avail_r0__SHIFT 0xb
-#define VGT_DEBUG_REG11__counters_available_r0_MASK 0x1000
-#define VGT_DEBUG_REG11__counters_available_r0__SHIFT 0xc
-#define VGT_DEBUG_REG11__vs_event_fifo_rtr_MASK 0x2000
-#define VGT_DEBUG_REG11__vs_event_fifo_rtr__SHIFT 0xd
-#define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q_MASK 0x4000
-#define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q__SHIFT 0xe
-#define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q_MASK 0x8000
-#define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q__SHIFT 0xf
-#define VGT_DEBUG_REG11__gs_issue_rtr_MASK 0x10000
-#define VGT_DEBUG_REG11__gs_issue_rtr__SHIFT 0x10
-#define VGT_DEBUG_REG11__tm_pt_event_rtr_MASK 0x20000
-#define VGT_DEBUG_REG11__tm_pt_event_rtr__SHIFT 0x11
-#define VGT_DEBUG_REG11__SPARE0_MASK 0x40000
-#define VGT_DEBUG_REG11__SPARE0__SHIFT 0x12
-#define VGT_DEBUG_REG11__gs_r0_rtr_MASK 0x80000
-#define VGT_DEBUG_REG11__gs_r0_rtr__SHIFT 0x13
-#define VGT_DEBUG_REG11__es_r0_rtr_MASK 0x100000
-#define VGT_DEBUG_REG11__es_r0_rtr__SHIFT 0x14
-#define VGT_DEBUG_REG11__gog_tm_vs_event_rtr_MASK 0x200000
-#define VGT_DEBUG_REG11__gog_tm_vs_event_rtr__SHIFT 0x15
-#define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr_MASK 0x400000
-#define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr__SHIFT 0x16
-#define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr_MASK 0x800000
-#define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr__SHIFT 0x17
-#define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr_MASK 0x1000000
-#define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr__SHIFT 0x18
-#define VGT_DEBUG_REG11__vs_event_fifo_empty_MASK 0x2000000
-#define VGT_DEBUG_REG11__vs_event_fifo_empty__SHIFT 0x19
-#define VGT_DEBUG_REG11__vs_event_fifo_full_MASK 0x4000000
-#define VGT_DEBUG_REG11__vs_event_fifo_full__SHIFT 0x1a
-#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full_MASK 0x8000000
-#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full__SHIFT 0x1b
-#define VGT_DEBUG_REG11__vs_dealloc_tbl_full_MASK 0x10000000
-#define VGT_DEBUG_REG11__vs_dealloc_tbl_full__SHIFT 0x1c
-#define VGT_DEBUG_REG11__send_event_q_MASK 0x20000000
-#define VGT_DEBUG_REG11__send_event_q__SHIFT 0x1d
-#define VGT_DEBUG_REG11__es_tbl_empty_MASK 0x40000000
-#define VGT_DEBUG_REG11__es_tbl_empty__SHIFT 0x1e
-#define VGT_DEBUG_REG11__no_active_states_r0_MASK 0x80000000
-#define VGT_DEBUG_REG11__no_active_states_r0__SHIFT 0x1f
-#define VGT_DEBUG_REG12__gs_state0_r0_q_MASK 0x7
-#define VGT_DEBUG_REG12__gs_state0_r0_q__SHIFT 0x0
-#define VGT_DEBUG_REG12__gs_state1_r0_q_MASK 0x38
-#define VGT_DEBUG_REG12__gs_state1_r0_q__SHIFT 0x3
-#define VGT_DEBUG_REG12__gs_state2_r0_q_MASK 0x1c0
-#define VGT_DEBUG_REG12__gs_state2_r0_q__SHIFT 0x6
-#define VGT_DEBUG_REG12__gs_state3_r0_q_MASK 0xe00
-#define VGT_DEBUG_REG12__gs_state3_r0_q__SHIFT 0x9
-#define VGT_DEBUG_REG12__gs_state4_r0_q_MASK 0x7000
-#define VGT_DEBUG_REG12__gs_state4_r0_q__SHIFT 0xc
-#define VGT_DEBUG_REG12__gs_state5_r0_q_MASK 0x38000
-#define VGT_DEBUG_REG12__gs_state5_r0_q__SHIFT 0xf
-#define VGT_DEBUG_REG12__gs_state6_r0_q_MASK 0x1c0000
-#define VGT_DEBUG_REG12__gs_state6_r0_q__SHIFT 0x12
-#define VGT_DEBUG_REG12__gs_state7_r0_q_MASK 0xe00000
-#define VGT_DEBUG_REG12__gs_state7_r0_q__SHIFT 0x15
-#define VGT_DEBUG_REG12__gs_state8_r0_q_MASK 0x7000000
-#define VGT_DEBUG_REG12__gs_state8_r0_q__SHIFT 0x18
-#define VGT_DEBUG_REG12__gs_state9_r0_q_MASK 0x38000000
-#define VGT_DEBUG_REG12__gs_state9_r0_q__SHIFT 0x1b
-#define VGT_DEBUG_REG12__hold_eswave_eop_MASK 0x40000000
-#define VGT_DEBUG_REG12__hold_eswave_eop__SHIFT 0x1e
-#define VGT_DEBUG_REG12__SPARE0_MASK 0x80000000
-#define VGT_DEBUG_REG12__SPARE0__SHIFT 0x1f
-#define VGT_DEBUG_REG13__gs_state10_r0_q_MASK 0x7
-#define VGT_DEBUG_REG13__gs_state10_r0_q__SHIFT 0x0
-#define VGT_DEBUG_REG13__gs_state11_r0_q_MASK 0x38
-#define VGT_DEBUG_REG13__gs_state11_r0_q__SHIFT 0x3
-#define VGT_DEBUG_REG13__gs_state12_r0_q_MASK 0x1c0
-#define VGT_DEBUG_REG13__gs_state12_r0_q__SHIFT 0x6
-#define VGT_DEBUG_REG13__gs_state13_r0_q_MASK 0xe00
-#define VGT_DEBUG_REG13__gs_state13_r0_q__SHIFT 0x9
-#define VGT_DEBUG_REG13__gs_state14_r0_q_MASK 0x7000
-#define VGT_DEBUG_REG13__gs_state14_r0_q__SHIFT 0xc
-#define VGT_DEBUG_REG13__gs_state15_r0_q_MASK 0x38000
-#define VGT_DEBUG_REG13__gs_state15_r0_q__SHIFT 0xf
-#define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0_MASK 0x3c0000
-#define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0__SHIFT 0x12
-#define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0_MASK 0x400000
-#define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0__SHIFT 0x16
-#define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0_MASK 0x800000
-#define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0__SHIFT 0x17
-#define VGT_DEBUG_REG13__es_tbl_full_MASK 0x1000000
-#define VGT_DEBUG_REG13__es_tbl_full__SHIFT 0x18
-#define VGT_DEBUG_REG13__SPARE1_MASK 0x2000000
-#define VGT_DEBUG_REG13__SPARE1__SHIFT 0x19
-#define VGT_DEBUG_REG13__SPARE0_MASK 0x4000000
-#define VGT_DEBUG_REG13__SPARE0__SHIFT 0x1a
-#define VGT_DEBUG_REG13__active_cm_sm_r0_q_MASK 0xf8000000
-#define VGT_DEBUG_REG13__active_cm_sm_r0_q__SHIFT 0x1b
-#define VGT_DEBUG_REG14__SPARE3_MASK 0xf
-#define VGT_DEBUG_REG14__SPARE3__SHIFT 0x0
-#define VGT_DEBUG_REG14__gsfetch_done_fifo_full_MASK 0x10
-#define VGT_DEBUG_REG14__gsfetch_done_fifo_full__SHIFT 0x4
-#define VGT_DEBUG_REG14__gs_rb_space_avail_r0_MASK 0x20
-#define VGT_DEBUG_REG14__gs_rb_space_avail_r0__SHIFT 0x5
-#define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0_MASK 0x40
-#define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0__SHIFT 0x6
-#define VGT_DEBUG_REG14__SPARE8_MASK 0x180
-#define VGT_DEBUG_REG14__SPARE8__SHIFT 0x7
-#define VGT_DEBUG_REG14__vs_done_cnt_q_not_0_MASK 0x200
-#define VGT_DEBUG_REG14__vs_done_cnt_q_not_0__SHIFT 0x9
-#define VGT_DEBUG_REG14__es_flush_cnt_busy_q_MASK 0x400
-#define VGT_DEBUG_REG14__es_flush_cnt_busy_q__SHIFT 0xa
-#define VGT_DEBUG_REG14__gs_tbl_full_r0_MASK 0x800
-#define VGT_DEBUG_REG14__gs_tbl_full_r0__SHIFT 0xb
-#define VGT_DEBUG_REG14__SPARE2_MASK 0x1ff000
-#define VGT_DEBUG_REG14__SPARE2__SHIFT 0xc
-#define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy_MASK 0x200000
-#define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy__SHIFT 0x15
-#define VGT_DEBUG_REG14__SPARE_MASK 0x1c00000
-#define VGT_DEBUG_REG14__SPARE__SHIFT 0x16
-#define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q_MASK 0x2000000
-#define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q__SHIFT 0x19
-#define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0_MASK 0x4000000
-#define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0__SHIFT 0x1a
-#define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy_MASK 0x8000000
-#define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy__SHIFT 0x1b
-#define VGT_DEBUG_REG14__SPARE1_MASK 0x10000000
-#define VGT_DEBUG_REG14__SPARE1__SHIFT 0x1c
-#define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0_MASK 0x20000000
-#define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0__SHIFT 0x1d
-#define VGT_DEBUG_REG14__SPARE0_MASK 0x40000000
-#define VGT_DEBUG_REG14__SPARE0__SHIFT 0x1e
-#define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q_MASK 0x80000000
-#define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q__SHIFT 0x1f
-#define VGT_DEBUG_REG15__cm_busy_q_MASK 0x1
-#define VGT_DEBUG_REG15__cm_busy_q__SHIFT 0x0
-#define VGT_DEBUG_REG15__counters_busy_q_MASK 0x2
-#define VGT_DEBUG_REG15__counters_busy_q__SHIFT 0x1
-#define VGT_DEBUG_REG15__output_fifo_empty_MASK 0x4
-#define VGT_DEBUG_REG15__output_fifo_empty__SHIFT 0x2
-#define VGT_DEBUG_REG15__output_fifo_full_MASK 0x8
-#define VGT_DEBUG_REG15__output_fifo_full__SHIFT 0x3
-#define VGT_DEBUG_REG15__counters_full_MASK 0x10
-#define VGT_DEBUG_REG15__counters_full__SHIFT 0x4
-#define VGT_DEBUG_REG15__active_sm_q_MASK 0x3e0
-#define VGT_DEBUG_REG15__active_sm_q__SHIFT 0x5
-#define VGT_DEBUG_REG15__entry_rdptr_q_MASK 0x7c00
-#define VGT_DEBUG_REG15__entry_rdptr_q__SHIFT 0xa
-#define VGT_DEBUG_REG15__cntr_tbl_wrptr_q_MASK 0xf8000
-#define VGT_DEBUG_REG15__cntr_tbl_wrptr_q__SHIFT 0xf
-#define VGT_DEBUG_REG15__SPARE25_MASK 0x3f00000
-#define VGT_DEBUG_REG15__SPARE25__SHIFT 0x14
-#define VGT_DEBUG_REG15__st_cut_mode_q_MASK 0xc000000
-#define VGT_DEBUG_REG15__st_cut_mode_q__SHIFT 0x1a
-#define VGT_DEBUG_REG15__gs_done_array_q_not_0_MASK 0x10000000
-#define VGT_DEBUG_REG15__gs_done_array_q_not_0__SHIFT 0x1c
-#define VGT_DEBUG_REG15__SPARE31_MASK 0xe0000000
-#define VGT_DEBUG_REG15__SPARE31__SHIFT 0x1d
-#define VGT_DEBUG_REG16__gog_busy_MASK 0x1
-#define VGT_DEBUG_REG16__gog_busy__SHIFT 0x0
-#define VGT_DEBUG_REG16__gog_state_q_MASK 0xe
-#define VGT_DEBUG_REG16__gog_state_q__SHIFT 0x1
-#define VGT_DEBUG_REG16__r0_rtr_MASK 0x10
-#define VGT_DEBUG_REG16__r0_rtr__SHIFT 0x4
-#define VGT_DEBUG_REG16__r1_rtr_MASK 0x20
-#define VGT_DEBUG_REG16__r1_rtr__SHIFT 0x5
-#define VGT_DEBUG_REG16__r1_upstream_rtr_MASK 0x40
-#define VGT_DEBUG_REG16__r1_upstream_rtr__SHIFT 0x6
-#define VGT_DEBUG_REG16__r2_vs_tbl_rtr_MASK 0x80
-#define VGT_DEBUG_REG16__r2_vs_tbl_rtr__SHIFT 0x7
-#define VGT_DEBUG_REG16__r2_prim_rtr_MASK 0x100
-#define VGT_DEBUG_REG16__r2_prim_rtr__SHIFT 0x8
-#define VGT_DEBUG_REG16__r2_indx_rtr_MASK 0x200
-#define VGT_DEBUG_REG16__r2_indx_rtr__SHIFT 0x9
-#define VGT_DEBUG_REG16__r2_rtr_MASK 0x400
-#define VGT_DEBUG_REG16__r2_rtr__SHIFT 0xa
-#define VGT_DEBUG_REG16__gog_tm_vs_event_rtr_MASK 0x800
-#define VGT_DEBUG_REG16__gog_tm_vs_event_rtr__SHIFT 0xb
-#define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr_MASK 0x1000
-#define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr__SHIFT 0xc
-#define VGT_DEBUG_REG16__indx_valid_r2_q_MASK 0x2000
-#define VGT_DEBUG_REG16__indx_valid_r2_q__SHIFT 0xd
-#define VGT_DEBUG_REG16__prim_valid_r2_q_MASK 0x4000
-#define VGT_DEBUG_REG16__prim_valid_r2_q__SHIFT 0xe
-#define VGT_DEBUG_REG16__valid_r2_q_MASK 0x8000
-#define VGT_DEBUG_REG16__valid_r2_q__SHIFT 0xf
-#define VGT_DEBUG_REG16__prim_valid_r1_q_MASK 0x10000
-#define VGT_DEBUG_REG16__prim_valid_r1_q__SHIFT 0x10
-#define VGT_DEBUG_REG16__indx_valid_r1_q_MASK 0x20000
-#define VGT_DEBUG_REG16__indx_valid_r1_q__SHIFT 0x11
-#define VGT_DEBUG_REG16__valid_r1_q_MASK 0x40000
-#define VGT_DEBUG_REG16__valid_r1_q__SHIFT 0x12
-#define VGT_DEBUG_REG16__indx_valid_r0_q_MASK 0x80000
-#define VGT_DEBUG_REG16__indx_valid_r0_q__SHIFT 0x13
-#define VGT_DEBUG_REG16__prim_valid_r0_q_MASK 0x100000
-#define VGT_DEBUG_REG16__prim_valid_r0_q__SHIFT 0x14
-#define VGT_DEBUG_REG16__valid_r0_q_MASK 0x200000
-#define VGT_DEBUG_REG16__valid_r0_q__SHIFT 0x15
-#define VGT_DEBUG_REG16__send_event_q_MASK 0x400000
-#define VGT_DEBUG_REG16__send_event_q__SHIFT 0x16
-#define VGT_DEBUG_REG16__SPARE24_MASK 0x800000
-#define VGT_DEBUG_REG16__SPARE24__SHIFT 0x17
-#define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q_MASK 0x1000000
-#define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q__SHIFT 0x18
-#define VGT_DEBUG_REG16__gog_out_prim_state_sel_MASK 0xe000000
-#define VGT_DEBUG_REG16__gog_out_prim_state_sel__SHIFT 0x19
-#define VGT_DEBUG_REG16__multiple_streams_en_r1_q_MASK 0x10000000
-#define VGT_DEBUG_REG16__multiple_streams_en_r1_q__SHIFT 0x1c
-#define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0_MASK 0x20000000
-#define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0__SHIFT 0x1d
-#define VGT_DEBUG_REG16__num_gs_r2_q_not_0_MASK 0x40000000
-#define VGT_DEBUG_REG16__num_gs_r2_q_not_0__SHIFT 0x1e
-#define VGT_DEBUG_REG16__new_vs_thread_r2_MASK 0x80000000
-#define VGT_DEBUG_REG16__new_vs_thread_r2__SHIFT 0x1f
-#define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0_MASK 0x3f
-#define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0__SHIFT 0x0
-#define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0_MASK 0xfc0
-#define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0__SHIFT 0x6
-#define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0_MASK 0x3f000
-#define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0__SHIFT 0xc
-#define VGT_DEBUG_REG17__gog_out_indx_13_0_MASK 0xfffc0000
-#define VGT_DEBUG_REG17__gog_out_indx_13_0__SHIFT 0x12
-#define VGT_DEBUG_REG18__grp_vr_valid_MASK 0x1
-#define VGT_DEBUG_REG18__grp_vr_valid__SHIFT 0x0
-#define VGT_DEBUG_REG18__pipe0_dr_MASK 0x2
-#define VGT_DEBUG_REG18__pipe0_dr__SHIFT 0x1
-#define VGT_DEBUG_REG18__pipe1_dr_MASK 0x4
-#define VGT_DEBUG_REG18__pipe1_dr__SHIFT 0x2
-#define VGT_DEBUG_REG18__vr_grp_read_MASK 0x8
-#define VGT_DEBUG_REG18__vr_grp_read__SHIFT 0x3
-#define VGT_DEBUG_REG18__pipe0_rtr_MASK 0x10
-#define VGT_DEBUG_REG18__pipe0_rtr__SHIFT 0x4
-#define VGT_DEBUG_REG18__pipe1_rtr_MASK 0x20
-#define VGT_DEBUG_REG18__pipe1_rtr__SHIFT 0x5
-#define VGT_DEBUG_REG18__out_vr_indx_read_MASK 0x40
-#define VGT_DEBUG_REG18__out_vr_indx_read__SHIFT 0x6
-#define VGT_DEBUG_REG18__out_vr_prim_read_MASK 0x80
-#define VGT_DEBUG_REG18__out_vr_prim_read__SHIFT 0x7
-#define VGT_DEBUG_REG18__indices_to_send_q_MASK 0x700
-#define VGT_DEBUG_REG18__indices_to_send_q__SHIFT 0x8
-#define VGT_DEBUG_REG18__valid_indices_MASK 0x800
-#define VGT_DEBUG_REG18__valid_indices__SHIFT 0xb
-#define VGT_DEBUG_REG18__last_indx_of_prim_MASK 0x1000
-#define VGT_DEBUG_REG18__last_indx_of_prim__SHIFT 0xc
-#define VGT_DEBUG_REG18__indx0_new_d_MASK 0x2000
-#define VGT_DEBUG_REG18__indx0_new_d__SHIFT 0xd
-#define VGT_DEBUG_REG18__indx1_new_d_MASK 0x4000
-#define VGT_DEBUG_REG18__indx1_new_d__SHIFT 0xe
-#define VGT_DEBUG_REG18__indx2_new_d_MASK 0x8000
-#define VGT_DEBUG_REG18__indx2_new_d__SHIFT 0xf
-#define VGT_DEBUG_REG18__indx2_hit_d_MASK 0x10000
-#define VGT_DEBUG_REG18__indx2_hit_d__SHIFT 0x10
-#define VGT_DEBUG_REG18__indx1_hit_d_MASK 0x20000
-#define VGT_DEBUG_REG18__indx1_hit_d__SHIFT 0x11
-#define VGT_DEBUG_REG18__indx0_hit_d_MASK 0x40000
-#define VGT_DEBUG_REG18__indx0_hit_d__SHIFT 0x12
-#define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q_MASK 0x80000
-#define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q__SHIFT 0x13
-#define VGT_DEBUG_REG18__last_group_of_instance_r0_q_MASK 0x100000
-#define VGT_DEBUG_REG18__last_group_of_instance_r0_q__SHIFT 0x14
-#define VGT_DEBUG_REG18__null_primitive_r0_q_MASK 0x200000
-#define VGT_DEBUG_REG18__null_primitive_r0_q__SHIFT 0x15
-#define VGT_DEBUG_REG18__eop_r0_q_MASK 0x400000
-#define VGT_DEBUG_REG18__eop_r0_q__SHIFT 0x16
-#define VGT_DEBUG_REG18__eject_vtx_vect_r1_d_MASK 0x800000
-#define VGT_DEBUG_REG18__eject_vtx_vect_r1_d__SHIFT 0x17
-#define VGT_DEBUG_REG18__sub_prim_type_r0_q_MASK 0x7000000
-#define VGT_DEBUG_REG18__sub_prim_type_r0_q__SHIFT 0x18
-#define VGT_DEBUG_REG18__gs_scenario_a_r0_q_MASK 0x8000000
-#define VGT_DEBUG_REG18__gs_scenario_a_r0_q__SHIFT 0x1b
-#define VGT_DEBUG_REG18__gs_scenario_b_r0_q_MASK 0x10000000
-#define VGT_DEBUG_REG18__gs_scenario_b_r0_q__SHIFT 0x1c
-#define VGT_DEBUG_REG18__components_valid_r0_q_MASK 0xe0000000
-#define VGT_DEBUG_REG18__components_valid_r0_q__SHIFT 0x1d
-#define VGT_DEBUG_REG19__separate_out_busy_q_MASK 0x1
-#define VGT_DEBUG_REG19__separate_out_busy_q__SHIFT 0x0
-#define VGT_DEBUG_REG19__separate_out_indx_busy_q_MASK 0x2
-#define VGT_DEBUG_REG19__separate_out_indx_busy_q__SHIFT 0x1
-#define VGT_DEBUG_REG19__prim_buffer_empty_MASK 0x4
-#define VGT_DEBUG_REG19__prim_buffer_empty__SHIFT 0x2
-#define VGT_DEBUG_REG19__prim_buffer_full_MASK 0x8
-#define VGT_DEBUG_REG19__prim_buffer_full__SHIFT 0x3
-#define VGT_DEBUG_REG19__pa_clips_fifo_busy_q_MASK 0x10
-#define VGT_DEBUG_REG19__pa_clips_fifo_busy_q__SHIFT 0x4
-#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q_MASK 0x20
-#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q__SHIFT 0x5
-#define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q_MASK 0x40
-#define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q__SHIFT 0x6
-#define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q_MASK 0x80
-#define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q__SHIFT 0x7
-#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q_MASK 0x100
-#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q__SHIFT 0x8
-#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q_MASK 0x200
-#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q__SHIFT 0x9
-#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q_MASK 0x400
-#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q__SHIFT 0xa
-#define VGT_DEBUG_REG19__hold_prim_MASK 0x800
-#define VGT_DEBUG_REG19__hold_prim__SHIFT 0xb
-#define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q_MASK 0x1000
-#define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q__SHIFT 0xc
-#define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q_MASK 0x2000
-#define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q__SHIFT 0xd
-#define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q_MASK 0x4000
-#define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q__SHIFT 0xe
-#define VGT_DEBUG_REG19__new_packet_q_MASK 0x8000
-#define VGT_DEBUG_REG19__new_packet_q__SHIFT 0xf
-#define VGT_DEBUG_REG19__buffered_prim_event_MASK 0x10000
-#define VGT_DEBUG_REG19__buffered_prim_event__SHIFT 0x10
-#define VGT_DEBUG_REG19__buffered_prim_null_primitive_MASK 0x20000
-#define VGT_DEBUG_REG19__buffered_prim_null_primitive__SHIFT 0x11
-#define VGT_DEBUG_REG19__buffered_prim_eop_MASK 0x40000
-#define VGT_DEBUG_REG19__buffered_prim_eop__SHIFT 0x12
-#define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect_MASK 0x80000
-#define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect__SHIFT 0x13
-#define VGT_DEBUG_REG19__buffered_prim_type_event_MASK 0x3f00000
-#define VGT_DEBUG_REG19__buffered_prim_type_event__SHIFT 0x14
-#define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q_MASK 0x4000000
-#define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q__SHIFT 0x1a
-#define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q_MASK 0x8000000
-#define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q__SHIFT 0x1b
-#define VGT_DEBUG_REG19__num_new_unique_rel_indx_MASK 0x30000000
-#define VGT_DEBUG_REG19__num_new_unique_rel_indx__SHIFT 0x1c
-#define VGT_DEBUG_REG19__null_terminate_vtx_vector_MASK 0x40000000
-#define VGT_DEBUG_REG19__null_terminate_vtx_vector__SHIFT 0x1e
-#define VGT_DEBUG_REG19__filter_event_MASK 0x80000000
-#define VGT_DEBUG_REG19__filter_event__SHIFT 0x1f
-#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex_MASK 0xffff
-#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex__SHIFT 0x0
-#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0_MASK 0x10000
-#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0__SHIFT 0x10
-#define VGT_DEBUG_REG20__SPARE17_MASK 0x20000
-#define VGT_DEBUG_REG20__SPARE17__SHIFT 0x11
-#define VGT_DEBUG_REG20__alloc_counter_q_MASK 0x3c0000
-#define VGT_DEBUG_REG20__alloc_counter_q__SHIFT 0x12
-#define VGT_DEBUG_REG20__curr_dealloc_distance_q_MASK 0x1fc00000
-#define VGT_DEBUG_REG20__curr_dealloc_distance_q__SHIFT 0x16
-#define VGT_DEBUG_REG20__new_allocate_q_MASK 0x20000000
-#define VGT_DEBUG_REG20__new_allocate_q__SHIFT 0x1d
-#define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0_MASK 0x40000000
-#define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0__SHIFT 0x1e
-#define VGT_DEBUG_REG20__int_vtx_counter_q_not_0_MASK 0x80000000
-#define VGT_DEBUG_REG20__int_vtx_counter_q_not_0__SHIFT 0x1f
-#define VGT_DEBUG_REG21__out_indx_fifo_empty_MASK 0x1
-#define VGT_DEBUG_REG21__out_indx_fifo_empty__SHIFT 0x0
-#define VGT_DEBUG_REG21__indx_side_fifo_empty_MASK 0x2
-#define VGT_DEBUG_REG21__indx_side_fifo_empty__SHIFT 0x1
-#define VGT_DEBUG_REG21__pipe0_dr_MASK 0x4
-#define VGT_DEBUG_REG21__pipe0_dr__SHIFT 0x2
-#define VGT_DEBUG_REG21__pipe1_dr_MASK 0x8
-#define VGT_DEBUG_REG21__pipe1_dr__SHIFT 0x3
-#define VGT_DEBUG_REG21__pipe2_dr_MASK 0x10
-#define VGT_DEBUG_REG21__pipe2_dr__SHIFT 0x4
-#define VGT_DEBUG_REG21__vsthread_buff_empty_MASK 0x20
-#define VGT_DEBUG_REG21__vsthread_buff_empty__SHIFT 0x5
-#define VGT_DEBUG_REG21__out_indx_fifo_full_MASK 0x40
-#define VGT_DEBUG_REG21__out_indx_fifo_full__SHIFT 0x6
-#define VGT_DEBUG_REG21__indx_side_fifo_full_MASK 0x80
-#define VGT_DEBUG_REG21__indx_side_fifo_full__SHIFT 0x7
-#define VGT_DEBUG_REG21__pipe0_rtr_MASK 0x100
-#define VGT_DEBUG_REG21__pipe0_rtr__SHIFT 0x8
-#define VGT_DEBUG_REG21__pipe1_rtr_MASK 0x200
-#define VGT_DEBUG_REG21__pipe1_rtr__SHIFT 0x9
-#define VGT_DEBUG_REG21__pipe2_rtr_MASK 0x400
-#define VGT_DEBUG_REG21__pipe2_rtr__SHIFT 0xa
-#define VGT_DEBUG_REG21__vsthread_buff_full_MASK 0x800
-#define VGT_DEBUG_REG21__vsthread_buff_full__SHIFT 0xb
-#define VGT_DEBUG_REG21__interfaces_rtr_MASK 0x1000
-#define VGT_DEBUG_REG21__interfaces_rtr__SHIFT 0xc
-#define VGT_DEBUG_REG21__indx_count_q_not_0_MASK 0x2000
-#define VGT_DEBUG_REG21__indx_count_q_not_0__SHIFT 0xd
-#define VGT_DEBUG_REG21__wait_for_external_eopg_q_MASK 0x4000
-#define VGT_DEBUG_REG21__wait_for_external_eopg_q__SHIFT 0xe
-#define VGT_DEBUG_REG21__full_state_p1_q_MASK 0x8000
-#define VGT_DEBUG_REG21__full_state_p1_q__SHIFT 0xf
-#define VGT_DEBUG_REG21__indx_side_indx_valid_MASK 0x10000
-#define VGT_DEBUG_REG21__indx_side_indx_valid__SHIFT 0x10
-#define VGT_DEBUG_REG21__stateid_p0_q_MASK 0xe0000
-#define VGT_DEBUG_REG21__stateid_p0_q__SHIFT 0x11
-#define VGT_DEBUG_REG21__is_event_p0_q_MASK 0x100000
-#define VGT_DEBUG_REG21__is_event_p0_q__SHIFT 0x14
-#define VGT_DEBUG_REG21__lshs_dealloc_p1_MASK 0x200000
-#define VGT_DEBUG_REG21__lshs_dealloc_p1__SHIFT 0x15
-#define VGT_DEBUG_REG21__stream_id_r2_q_MASK 0x400000
-#define VGT_DEBUG_REG21__stream_id_r2_q__SHIFT 0x16
-#define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0_MASK 0x800000
-#define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0__SHIFT 0x17
-#define VGT_DEBUG_REG21__buff_full_p1_MASK 0x1000000
-#define VGT_DEBUG_REG21__buff_full_p1__SHIFT 0x18
-#define VGT_DEBUG_REG21__strmout_valid_p1_MASK 0x2000000
-#define VGT_DEBUG_REG21__strmout_valid_p1__SHIFT 0x19
-#define VGT_DEBUG_REG21__eotg_r2_q_MASK 0x4000000
-#define VGT_DEBUG_REG21__eotg_r2_q__SHIFT 0x1a
-#define VGT_DEBUG_REG21__null_r2_q_MASK 0x8000000
-#define VGT_DEBUG_REG21__null_r2_q__SHIFT 0x1b
-#define VGT_DEBUG_REG21__p0_dr_MASK 0x10000000
-#define VGT_DEBUG_REG21__p0_dr__SHIFT 0x1c
-#define VGT_DEBUG_REG21__p0_rtr_MASK 0x20000000
-#define VGT_DEBUG_REG21__p0_rtr__SHIFT 0x1d
-#define VGT_DEBUG_REG21__eopg_p0_q_MASK 0x40000000
-#define VGT_DEBUG_REG21__eopg_p0_q__SHIFT 0x1e
-#define VGT_DEBUG_REG21__p0_nobp_MASK 0x80000000
-#define VGT_DEBUG_REG21__p0_nobp__SHIFT 0x1f
-#define VGT_DEBUG_REG22__cm_state16_MASK 0x3
-#define VGT_DEBUG_REG22__cm_state16__SHIFT 0x0
-#define VGT_DEBUG_REG22__cm_state17_MASK 0xc
-#define VGT_DEBUG_REG22__cm_state17__SHIFT 0x2
-#define VGT_DEBUG_REG22__cm_state18_MASK 0x30
-#define VGT_DEBUG_REG22__cm_state18__SHIFT 0x4
-#define VGT_DEBUG_REG22__cm_state19_MASK 0xc0
-#define VGT_DEBUG_REG22__cm_state19__SHIFT 0x6
-#define VGT_DEBUG_REG22__cm_state20_MASK 0x300
-#define VGT_DEBUG_REG22__cm_state20__SHIFT 0x8
-#define VGT_DEBUG_REG22__cm_state21_MASK 0xc00
-#define VGT_DEBUG_REG22__cm_state21__SHIFT 0xa
-#define VGT_DEBUG_REG22__cm_state22_MASK 0x3000
-#define VGT_DEBUG_REG22__cm_state22__SHIFT 0xc
-#define VGT_DEBUG_REG22__cm_state23_MASK 0xc000
-#define VGT_DEBUG_REG22__cm_state23__SHIFT 0xe
-#define VGT_DEBUG_REG22__cm_state24_MASK 0x30000
-#define VGT_DEBUG_REG22__cm_state24__SHIFT 0x10
-#define VGT_DEBUG_REG22__cm_state25_MASK 0xc0000
-#define VGT_DEBUG_REG22__cm_state25__SHIFT 0x12
-#define VGT_DEBUG_REG22__cm_state26_MASK 0x300000
-#define VGT_DEBUG_REG22__cm_state26__SHIFT 0x14
-#define VGT_DEBUG_REG22__cm_state27_MASK 0xc00000
-#define VGT_DEBUG_REG22__cm_state27__SHIFT 0x16
-#define VGT_DEBUG_REG22__cm_state28_MASK 0x3000000
-#define VGT_DEBUG_REG22__cm_state28__SHIFT 0x18
-#define VGT_DEBUG_REG22__cm_state29_MASK 0xc000000
-#define VGT_DEBUG_REG22__cm_state29__SHIFT 0x1a
-#define VGT_DEBUG_REG22__cm_state30_MASK 0x30000000
-#define VGT_DEBUG_REG22__cm_state30__SHIFT 0x1c
-#define VGT_DEBUG_REG22__cm_state31_MASK 0xc0000000
-#define VGT_DEBUG_REG22__cm_state31__SHIFT 0x1e
-#define VGT_DEBUG_REG23__frmt_busy_MASK 0x1
-#define VGT_DEBUG_REG23__frmt_busy__SHIFT 0x0
-#define VGT_DEBUG_REG23__rcm_frmt_vert_rtr_MASK 0x2
-#define VGT_DEBUG_REG23__rcm_frmt_vert_rtr__SHIFT 0x1
-#define VGT_DEBUG_REG23__rcm_frmt_prim_rtr_MASK 0x4
-#define VGT_DEBUG_REG23__rcm_frmt_prim_rtr__SHIFT 0x2
-#define VGT_DEBUG_REG23__prim_r3_rtr_MASK 0x8
-#define VGT_DEBUG_REG23__prim_r3_rtr__SHIFT 0x3
-#define VGT_DEBUG_REG23__prim_r2_rtr_MASK 0x10
-#define VGT_DEBUG_REG23__prim_r2_rtr__SHIFT 0x4
-#define VGT_DEBUG_REG23__vert_r3_rtr_MASK 0x20
-#define VGT_DEBUG_REG23__vert_r3_rtr__SHIFT 0x5
-#define VGT_DEBUG_REG23__vert_r2_rtr_MASK 0x40
-#define VGT_DEBUG_REG23__vert_r2_rtr__SHIFT 0x6
-#define VGT_DEBUG_REG23__vert_r1_rtr_MASK 0x80
-#define VGT_DEBUG_REG23__vert_r1_rtr__SHIFT 0x7
-#define VGT_DEBUG_REG23__vert_r0_rtr_MASK 0x100
-#define VGT_DEBUG_REG23__vert_r0_rtr__SHIFT 0x8
-#define VGT_DEBUG_REG23__prim_fifo_empty_MASK 0x200
-#define VGT_DEBUG_REG23__prim_fifo_empty__SHIFT 0x9
-#define VGT_DEBUG_REG23__prim_fifo_full_MASK 0x400
-#define VGT_DEBUG_REG23__prim_fifo_full__SHIFT 0xa
-#define VGT_DEBUG_REG23__vert_dr_r2_q_MASK 0x800
-#define VGT_DEBUG_REG23__vert_dr_r2_q__SHIFT 0xb
-#define VGT_DEBUG_REG23__prim_dr_r2_q_MASK 0x1000
-#define VGT_DEBUG_REG23__prim_dr_r2_q__SHIFT 0xc
-#define VGT_DEBUG_REG23__vert_dr_r1_q_MASK 0x2000
-#define VGT_DEBUG_REG23__vert_dr_r1_q__SHIFT 0xd
-#define VGT_DEBUG_REG23__vert_dr_r0_q_MASK 0x4000
-#define VGT_DEBUG_REG23__vert_dr_r0_q__SHIFT 0xe
-#define VGT_DEBUG_REG23__new_verts_r2_q_MASK 0x18000
-#define VGT_DEBUG_REG23__new_verts_r2_q__SHIFT 0xf
-#define VGT_DEBUG_REG23__verts_sent_r2_q_MASK 0x1e0000
-#define VGT_DEBUG_REG23__verts_sent_r2_q__SHIFT 0x11
-#define VGT_DEBUG_REG23__prim_state_sel_r2_q_MASK 0xe00000
-#define VGT_DEBUG_REG23__prim_state_sel_r2_q__SHIFT 0x15
-#define VGT_DEBUG_REG23__SPARE_MASK 0xff000000
-#define VGT_DEBUG_REG23__SPARE__SHIFT 0x18
-#define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0_MASK 0xffffff
-#define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0__SHIFT 0x0
-#define VGT_DEBUG_REG24__dependent_st_cut_mode_q_MASK 0x3000000
-#define VGT_DEBUG_REG24__dependent_st_cut_mode_q__SHIFT 0x18
-#define VGT_DEBUG_REG24__SPARE31_MASK 0xfc000000
-#define VGT_DEBUG_REG24__SPARE31__SHIFT 0x1a
-#define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0_MASK 0x3ffffff
-#define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0__SHIFT 0x0
-#define VGT_DEBUG_REG25__active_sm_r0_q_MASK 0x3c000000
-#define VGT_DEBUG_REG25__active_sm_r0_q__SHIFT 0x1a
-#define VGT_DEBUG_REG25__add_gs_rb_space_r1_q_MASK 0x40000000
-#define VGT_DEBUG_REG25__add_gs_rb_space_r1_q__SHIFT 0x1e
-#define VGT_DEBUG_REG25__add_gs_rb_space_r0_q_MASK 0x80000000
-#define VGT_DEBUG_REG25__add_gs_rb_space_r0_q__SHIFT 0x1f
-#define VGT_DEBUG_REG26__cm_state0_MASK 0x3
-#define VGT_DEBUG_REG26__cm_state0__SHIFT 0x0
-#define VGT_DEBUG_REG26__cm_state1_MASK 0xc
-#define VGT_DEBUG_REG26__cm_state1__SHIFT 0x2
-#define VGT_DEBUG_REG26__cm_state2_MASK 0x30
-#define VGT_DEBUG_REG26__cm_state2__SHIFT 0x4
-#define VGT_DEBUG_REG26__cm_state3_MASK 0xc0
-#define VGT_DEBUG_REG26__cm_state3__SHIFT 0x6
-#define VGT_DEBUG_REG26__cm_state4_MASK 0x300
-#define VGT_DEBUG_REG26__cm_state4__SHIFT 0x8
-#define VGT_DEBUG_REG26__cm_state5_MASK 0xc00
-#define VGT_DEBUG_REG26__cm_state5__SHIFT 0xa
-#define VGT_DEBUG_REG26__cm_state6_MASK 0x3000
-#define VGT_DEBUG_REG26__cm_state6__SHIFT 0xc
-#define VGT_DEBUG_REG26__cm_state7_MASK 0xc000
-#define VGT_DEBUG_REG26__cm_state7__SHIFT 0xe
-#define VGT_DEBUG_REG26__cm_state8_MASK 0x30000
-#define VGT_DEBUG_REG26__cm_state8__SHIFT 0x10
-#define VGT_DEBUG_REG26__cm_state9_MASK 0xc0000
-#define VGT_DEBUG_REG26__cm_state9__SHIFT 0x12
-#define VGT_DEBUG_REG26__cm_state10_MASK 0x300000
-#define VGT_DEBUG_REG26__cm_state10__SHIFT 0x14
-#define VGT_DEBUG_REG26__cm_state11_MASK 0xc00000
-#define VGT_DEBUG_REG26__cm_state11__SHIFT 0x16
-#define VGT_DEBUG_REG26__cm_state12_MASK 0x3000000
-#define VGT_DEBUG_REG26__cm_state12__SHIFT 0x18
-#define VGT_DEBUG_REG26__cm_state13_MASK 0xc000000
-#define VGT_DEBUG_REG26__cm_state13__SHIFT 0x1a
-#define VGT_DEBUG_REG26__cm_state14_MASK 0x30000000
-#define VGT_DEBUG_REG26__cm_state14__SHIFT 0x1c
-#define VGT_DEBUG_REG26__cm_state15_MASK 0xc0000000
-#define VGT_DEBUG_REG26__cm_state15__SHIFT 0x1e
-#define VGT_DEBUG_REG27__pipe0_dr_MASK 0x1
-#define VGT_DEBUG_REG27__pipe0_dr__SHIFT 0x0
-#define VGT_DEBUG_REG27__gsc0_dr_MASK 0x2
-#define VGT_DEBUG_REG27__gsc0_dr__SHIFT 0x1
-#define VGT_DEBUG_REG27__pipe1_dr_MASK 0x4
-#define VGT_DEBUG_REG27__pipe1_dr__SHIFT 0x2
-#define VGT_DEBUG_REG27__tm_pt_event_rtr_MASK 0x8
-#define VGT_DEBUG_REG27__tm_pt_event_rtr__SHIFT 0x3
-#define VGT_DEBUG_REG27__pipe0_rtr_MASK 0x10
-#define VGT_DEBUG_REG27__pipe0_rtr__SHIFT 0x4
-#define VGT_DEBUG_REG27__gsc0_rtr_MASK 0x20
-#define VGT_DEBUG_REG27__gsc0_rtr__SHIFT 0x5
-#define VGT_DEBUG_REG27__pipe1_rtr_MASK 0x40
-#define VGT_DEBUG_REG27__pipe1_rtr__SHIFT 0x6
-#define VGT_DEBUG_REG27__last_indx_of_prim_p1_q_MASK 0x80
-#define VGT_DEBUG_REG27__last_indx_of_prim_p1_q__SHIFT 0x7
-#define VGT_DEBUG_REG27__indices_to_send_p0_q_MASK 0x300
-#define VGT_DEBUG_REG27__indices_to_send_p0_q__SHIFT 0x8
-#define VGT_DEBUG_REG27__event_flag_p1_q_MASK 0x400
-#define VGT_DEBUG_REG27__event_flag_p1_q__SHIFT 0xa
-#define VGT_DEBUG_REG27__eop_p1_q_MASK 0x800
-#define VGT_DEBUG_REG27__eop_p1_q__SHIFT 0xb
-#define VGT_DEBUG_REG27__gs_out_prim_type_p0_q_MASK 0x3000
-#define VGT_DEBUG_REG27__gs_out_prim_type_p0_q__SHIFT 0xc
-#define VGT_DEBUG_REG27__gsc_null_primitive_p0_q_MASK 0x4000
-#define VGT_DEBUG_REG27__gsc_null_primitive_p0_q__SHIFT 0xe
-#define VGT_DEBUG_REG27__gsc_eop_p0_q_MASK 0x8000
-#define VGT_DEBUG_REG27__gsc_eop_p0_q__SHIFT 0xf
-#define VGT_DEBUG_REG27__gsc_2cycle_output_MASK 0x10000
-#define VGT_DEBUG_REG27__gsc_2cycle_output__SHIFT 0x10
-#define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q_MASK 0x20000
-#define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q__SHIFT 0x11
-#define VGT_DEBUG_REG27__last_indx_of_vsprim_MASK 0x40000
-#define VGT_DEBUG_REG27__last_indx_of_vsprim__SHIFT 0x12
-#define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q_MASK 0x80000
-#define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q__SHIFT 0x13
-#define VGT_DEBUG_REG27__gsc_indx_count_p0_q_MASK 0x7ff00000
-#define VGT_DEBUG_REG27__gsc_indx_count_p0_q__SHIFT 0x14
-#define VGT_DEBUG_REG27__last_vsprim_of_gsprim_MASK 0x80000000
-#define VGT_DEBUG_REG27__last_vsprim_of_gsprim__SHIFT 0x1f
-#define VGT_DEBUG_REG28__con_state_q_MASK 0xf
-#define VGT_DEBUG_REG28__con_state_q__SHIFT 0x0
-#define VGT_DEBUG_REG28__second_cycle_q_MASK 0x10
-#define VGT_DEBUG_REG28__second_cycle_q__SHIFT 0x4
-#define VGT_DEBUG_REG28__process_tri_middle_p0_q_MASK 0x20
-#define VGT_DEBUG_REG28__process_tri_middle_p0_q__SHIFT 0x5
-#define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q_MASK 0x40
-#define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q__SHIFT 0x6
-#define VGT_DEBUG_REG28__process_tri_center_poly_p0_q_MASK 0x80
-#define VGT_DEBUG_REG28__process_tri_center_poly_p0_q__SHIFT 0x7
-#define VGT_DEBUG_REG28__pipe0_patch_dr_MASK 0x100
-#define VGT_DEBUG_REG28__pipe0_patch_dr__SHIFT 0x8
-#define VGT_DEBUG_REG28__pipe0_edge_dr_MASK 0x200
-#define VGT_DEBUG_REG28__pipe0_edge_dr__SHIFT 0x9
-#define VGT_DEBUG_REG28__pipe1_dr_MASK 0x400
-#define VGT_DEBUG_REG28__pipe1_dr__SHIFT 0xa
-#define VGT_DEBUG_REG28__pipe0_patch_rtr_MASK 0x800
-#define VGT_DEBUG_REG28__pipe0_patch_rtr__SHIFT 0xb
-#define VGT_DEBUG_REG28__pipe0_edge_rtr_MASK 0x1000
-#define VGT_DEBUG_REG28__pipe0_edge_rtr__SHIFT 0xc
-#define VGT_DEBUG_REG28__pipe1_rtr_MASK 0x2000
-#define VGT_DEBUG_REG28__pipe1_rtr__SHIFT 0xd
-#define VGT_DEBUG_REG28__outer_parity_p0_q_MASK 0x4000
-#define VGT_DEBUG_REG28__outer_parity_p0_q__SHIFT 0xe
-#define VGT_DEBUG_REG28__parallel_parity_p0_q_MASK 0x8000
-#define VGT_DEBUG_REG28__parallel_parity_p0_q__SHIFT 0xf
-#define VGT_DEBUG_REG28__first_ring_of_patch_p0_q_MASK 0x10000
-#define VGT_DEBUG_REG28__first_ring_of_patch_p0_q__SHIFT 0x10
-#define VGT_DEBUG_REG28__last_ring_of_patch_p0_q_MASK 0x20000
-#define VGT_DEBUG_REG28__last_ring_of_patch_p0_q__SHIFT 0x11
-#define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q_MASK 0x40000
-#define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q__SHIFT 0x12
-#define VGT_DEBUG_REG28__last_point_of_outer_ring_p1_MASK 0x80000
-#define VGT_DEBUG_REG28__last_point_of_outer_ring_p1__SHIFT 0x13
-#define VGT_DEBUG_REG28__last_point_of_inner_ring_p1_MASK 0x100000
-#define VGT_DEBUG_REG28__last_point_of_inner_ring_p1__SHIFT 0x14
-#define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q_MASK 0x200000
-#define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q__SHIFT 0x15
-#define VGT_DEBUG_REG28__advance_outer_point_p1_MASK 0x400000
-#define VGT_DEBUG_REG28__advance_outer_point_p1__SHIFT 0x16
-#define VGT_DEBUG_REG28__advance_inner_point_p1_MASK 0x800000
-#define VGT_DEBUG_REG28__advance_inner_point_p1__SHIFT 0x17
-#define VGT_DEBUG_REG28__next_ring_is_rect_p0_q_MASK 0x1000000
-#define VGT_DEBUG_REG28__next_ring_is_rect_p0_q__SHIFT 0x18
-#define VGT_DEBUG_REG28__pipe1_outer1_rtr_MASK 0x2000000
-#define VGT_DEBUG_REG28__pipe1_outer1_rtr__SHIFT 0x19
-#define VGT_DEBUG_REG28__pipe1_outer2_rtr_MASK 0x4000000
-#define VGT_DEBUG_REG28__pipe1_outer2_rtr__SHIFT 0x1a
-#define VGT_DEBUG_REG28__pipe1_inner1_rtr_MASK 0x8000000
-#define VGT_DEBUG_REG28__pipe1_inner1_rtr__SHIFT 0x1b
-#define VGT_DEBUG_REG28__pipe1_inner2_rtr_MASK 0x10000000
-#define VGT_DEBUG_REG28__pipe1_inner2_rtr__SHIFT 0x1c
-#define VGT_DEBUG_REG28__pipe1_patch_rtr_MASK 0x20000000
-#define VGT_DEBUG_REG28__pipe1_patch_rtr__SHIFT 0x1d
-#define VGT_DEBUG_REG28__pipe1_edge_rtr_MASK 0x40000000
-#define VGT_DEBUG_REG28__pipe1_edge_rtr__SHIFT 0x1e
-#define VGT_DEBUG_REG28__use_stored_inner_q_ring2_MASK 0x80000000
-#define VGT_DEBUG_REG28__use_stored_inner_q_ring2__SHIFT 0x1f
-#define VGT_DEBUG_REG29__con_state_q_MASK 0xf
-#define VGT_DEBUG_REG29__con_state_q__SHIFT 0x0
-#define VGT_DEBUG_REG29__second_cycle_q_MASK 0x10
-#define VGT_DEBUG_REG29__second_cycle_q__SHIFT 0x4
-#define VGT_DEBUG_REG29__process_tri_middle_p0_q_MASK 0x20
-#define VGT_DEBUG_REG29__process_tri_middle_p0_q__SHIFT 0x5
-#define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q_MASK 0x40
-#define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q__SHIFT 0x6
-#define VGT_DEBUG_REG29__process_tri_center_poly_p0_q_MASK 0x80
-#define VGT_DEBUG_REG29__process_tri_center_poly_p0_q__SHIFT 0x7
-#define VGT_DEBUG_REG29__pipe0_patch_dr_MASK 0x100
-#define VGT_DEBUG_REG29__pipe0_patch_dr__SHIFT 0x8
-#define VGT_DEBUG_REG29__pipe0_edge_dr_MASK 0x200
-#define VGT_DEBUG_REG29__pipe0_edge_dr__SHIFT 0x9
-#define VGT_DEBUG_REG29__pipe1_dr_MASK 0x400
-#define VGT_DEBUG_REG29__pipe1_dr__SHIFT 0xa
-#define VGT_DEBUG_REG29__pipe0_patch_rtr_MASK 0x800
-#define VGT_DEBUG_REG29__pipe0_patch_rtr__SHIFT 0xb
-#define VGT_DEBUG_REG29__pipe0_edge_rtr_MASK 0x1000
-#define VGT_DEBUG_REG29__pipe0_edge_rtr__SHIFT 0xc
-#define VGT_DEBUG_REG29__pipe1_rtr_MASK 0x2000
-#define VGT_DEBUG_REG29__pipe1_rtr__SHIFT 0xd
-#define VGT_DEBUG_REG29__outer_parity_p0_q_MASK 0x4000
-#define VGT_DEBUG_REG29__outer_parity_p0_q__SHIFT 0xe
-#define VGT_DEBUG_REG29__parallel_parity_p0_q_MASK 0x8000
-#define VGT_DEBUG_REG29__parallel_parity_p0_q__SHIFT 0xf
-#define VGT_DEBUG_REG29__first_ring_of_patch_p0_q_MASK 0x10000
-#define VGT_DEBUG_REG29__first_ring_of_patch_p0_q__SHIFT 0x10
-#define VGT_DEBUG_REG29__last_ring_of_patch_p0_q_MASK 0x20000
-#define VGT_DEBUG_REG29__last_ring_of_patch_p0_q__SHIFT 0x11
-#define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q_MASK 0x40000
-#define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q__SHIFT 0x12
-#define VGT_DEBUG_REG29__last_point_of_outer_ring_p1_MASK 0x80000
-#define VGT_DEBUG_REG29__last_point_of_outer_ring_p1__SHIFT 0x13
-#define VGT_DEBUG_REG29__last_point_of_inner_ring_p1_MASK 0x100000
-#define VGT_DEBUG_REG29__last_point_of_inner_ring_p1__SHIFT 0x14
-#define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q_MASK 0x200000
-#define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q__SHIFT 0x15
-#define VGT_DEBUG_REG29__advance_outer_point_p1_MASK 0x400000
-#define VGT_DEBUG_REG29__advance_outer_point_p1__SHIFT 0x16
-#define VGT_DEBUG_REG29__advance_inner_point_p1_MASK 0x800000
-#define VGT_DEBUG_REG29__advance_inner_point_p1__SHIFT 0x17
-#define VGT_DEBUG_REG29__next_ring_is_rect_p0_q_MASK 0x1000000
-#define VGT_DEBUG_REG29__next_ring_is_rect_p0_q__SHIFT 0x18
-#define VGT_DEBUG_REG29__pipe1_outer1_rtr_MASK 0x2000000
-#define VGT_DEBUG_REG29__pipe1_outer1_rtr__SHIFT 0x19
-#define VGT_DEBUG_REG29__pipe1_outer2_rtr_MASK 0x4000000
-#define VGT_DEBUG_REG29__pipe1_outer2_rtr__SHIFT 0x1a
-#define VGT_DEBUG_REG29__pipe1_inner1_rtr_MASK 0x8000000
-#define VGT_DEBUG_REG29__pipe1_inner1_rtr__SHIFT 0x1b
-#define VGT_DEBUG_REG29__pipe1_inner2_rtr_MASK 0x10000000
-#define VGT_DEBUG_REG29__pipe1_inner2_rtr__SHIFT 0x1c
-#define VGT_DEBUG_REG29__pipe1_patch_rtr_MASK 0x20000000
-#define VGT_DEBUG_REG29__pipe1_patch_rtr__SHIFT 0x1d
-#define VGT_DEBUG_REG29__pipe1_edge_rtr_MASK 0x40000000
-#define VGT_DEBUG_REG29__pipe1_edge_rtr__SHIFT 0x1e
-#define VGT_DEBUG_REG29__use_stored_inner_q_ring3_MASK 0x80000000
-#define VGT_DEBUG_REG29__use_stored_inner_q_ring3__SHIFT 0x1f
-#define VGT_DEBUG_REG31__pipe0_dr_MASK 0x1
-#define VGT_DEBUG_REG31__pipe0_dr__SHIFT 0x0
-#define VGT_DEBUG_REG31__pipe0_rtr_MASK 0x2
-#define VGT_DEBUG_REG31__pipe0_rtr__SHIFT 0x1
-#define VGT_DEBUG_REG31__pipe1_outer_dr_MASK 0x4
-#define VGT_DEBUG_REG31__pipe1_outer_dr__SHIFT 0x2
-#define VGT_DEBUG_REG31__pipe1_inner_dr_MASK 0x8
-#define VGT_DEBUG_REG31__pipe1_inner_dr__SHIFT 0x3
-#define VGT_DEBUG_REG31__pipe2_outer_dr_MASK 0x10
-#define VGT_DEBUG_REG31__pipe2_outer_dr__SHIFT 0x4
-#define VGT_DEBUG_REG31__pipe2_inner_dr_MASK 0x20
-#define VGT_DEBUG_REG31__pipe2_inner_dr__SHIFT 0x5
-#define VGT_DEBUG_REG31__pipe3_outer_dr_MASK 0x40
-#define VGT_DEBUG_REG31__pipe3_outer_dr__SHIFT 0x6
-#define VGT_DEBUG_REG31__pipe3_inner_dr_MASK 0x80
-#define VGT_DEBUG_REG31__pipe3_inner_dr__SHIFT 0x7
-#define VGT_DEBUG_REG31__pipe4_outer_dr_MASK 0x100
-#define VGT_DEBUG_REG31__pipe4_outer_dr__SHIFT 0x8
-#define VGT_DEBUG_REG31__pipe4_inner_dr_MASK 0x200
-#define VGT_DEBUG_REG31__pipe4_inner_dr__SHIFT 0x9
-#define VGT_DEBUG_REG31__pipe5_outer_dr_MASK 0x400
-#define VGT_DEBUG_REG31__pipe5_outer_dr__SHIFT 0xa
-#define VGT_DEBUG_REG31__pipe5_inner_dr_MASK 0x800
-#define VGT_DEBUG_REG31__pipe5_inner_dr__SHIFT 0xb
-#define VGT_DEBUG_REG31__pipe2_outer_rtr_MASK 0x1000
-#define VGT_DEBUG_REG31__pipe2_outer_rtr__SHIFT 0xc
-#define VGT_DEBUG_REG31__pipe2_inner_rtr_MASK 0x2000
-#define VGT_DEBUG_REG31__pipe2_inner_rtr__SHIFT 0xd
-#define VGT_DEBUG_REG31__pipe3_outer_rtr_MASK 0x4000
-#define VGT_DEBUG_REG31__pipe3_outer_rtr__SHIFT 0xe
-#define VGT_DEBUG_REG31__pipe3_inner_rtr_MASK 0x8000
-#define VGT_DEBUG_REG31__pipe3_inner_rtr__SHIFT 0xf
-#define VGT_DEBUG_REG31__pipe4_outer_rtr_MASK 0x10000
-#define VGT_DEBUG_REG31__pipe4_outer_rtr__SHIFT 0x10
-#define VGT_DEBUG_REG31__pipe4_inner_rtr_MASK 0x20000
-#define VGT_DEBUG_REG31__pipe4_inner_rtr__SHIFT 0x11
-#define VGT_DEBUG_REG31__pipe5_outer_rtr_MASK 0x40000
-#define VGT_DEBUG_REG31__pipe5_outer_rtr__SHIFT 0x12
-#define VGT_DEBUG_REG31__pipe5_inner_rtr_MASK 0x80000
-#define VGT_DEBUG_REG31__pipe5_inner_rtr__SHIFT 0x13
-#define VGT_DEBUG_REG31__pg_con_outer_point1_rts_MASK 0x100000
-#define VGT_DEBUG_REG31__pg_con_outer_point1_rts__SHIFT 0x14
-#define VGT_DEBUG_REG31__pg_con_outer_point2_rts_MASK 0x200000
-#define VGT_DEBUG_REG31__pg_con_outer_point2_rts__SHIFT 0x15
-#define VGT_DEBUG_REG31__pg_con_inner_point1_rts_MASK 0x400000
-#define VGT_DEBUG_REG31__pg_con_inner_point1_rts__SHIFT 0x16
-#define VGT_DEBUG_REG31__pg_con_inner_point2_rts_MASK 0x800000
-#define VGT_DEBUG_REG31__pg_con_inner_point2_rts__SHIFT 0x17
-#define VGT_DEBUG_REG31__pg_patch_fifo_empty_MASK 0x1000000
-#define VGT_DEBUG_REG31__pg_patch_fifo_empty__SHIFT 0x18
-#define VGT_DEBUG_REG31__pg_edge_fifo_empty_MASK 0x2000000
-#define VGT_DEBUG_REG31__pg_edge_fifo_empty__SHIFT 0x19
-#define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty_MASK 0x4000000
-#define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty__SHIFT 0x1a
-#define VGT_DEBUG_REG31__pg_patch_fifo_full_MASK 0x8000000
-#define VGT_DEBUG_REG31__pg_patch_fifo_full__SHIFT 0x1b
-#define VGT_DEBUG_REG31__pg_edge_fifo_full_MASK 0x10000000
-#define VGT_DEBUG_REG31__pg_edge_fifo_full__SHIFT 0x1c
-#define VGT_DEBUG_REG31__pg_inner_perp_fifo_full_MASK 0x20000000
-#define VGT_DEBUG_REG31__pg_inner_perp_fifo_full__SHIFT 0x1d
-#define VGT_DEBUG_REG31__outer_ring_done_q_MASK 0x40000000
-#define VGT_DEBUG_REG31__outer_ring_done_q__SHIFT 0x1e
-#define VGT_DEBUG_REG31__inner_ring_done_q_MASK 0x80000000
-#define VGT_DEBUG_REG31__inner_ring_done_q__SHIFT 0x1f
-#define VGT_DEBUG_REG32__first_ring_of_patch_MASK 0x1
-#define VGT_DEBUG_REG32__first_ring_of_patch__SHIFT 0x0
-#define VGT_DEBUG_REG32__last_ring_of_patch_MASK 0x2
-#define VGT_DEBUG_REG32__last_ring_of_patch__SHIFT 0x1
-#define VGT_DEBUG_REG32__last_edge_of_outer_ring_MASK 0x4
-#define VGT_DEBUG_REG32__last_edge_of_outer_ring__SHIFT 0x2
-#define VGT_DEBUG_REG32__last_point_of_outer_edge_MASK 0x8
-#define VGT_DEBUG_REG32__last_point_of_outer_edge__SHIFT 0x3
-#define VGT_DEBUG_REG32__last_edge_of_inner_ring_MASK 0x10
-#define VGT_DEBUG_REG32__last_edge_of_inner_ring__SHIFT 0x4
-#define VGT_DEBUG_REG32__last_point_of_inner_edge_MASK 0x20
-#define VGT_DEBUG_REG32__last_point_of_inner_edge__SHIFT 0x5
-#define VGT_DEBUG_REG32__last_patch_of_tg_p0_q_MASK 0x40
-#define VGT_DEBUG_REG32__last_patch_of_tg_p0_q__SHIFT 0x6
-#define VGT_DEBUG_REG32__event_null_special_p0_q_MASK 0x80
-#define VGT_DEBUG_REG32__event_null_special_p0_q__SHIFT 0x7
-#define VGT_DEBUG_REG32__event_flag_p5_q_MASK 0x100
-#define VGT_DEBUG_REG32__event_flag_p5_q__SHIFT 0x8
-#define VGT_DEBUG_REG32__first_point_of_patch_p5_q_MASK 0x200
-#define VGT_DEBUG_REG32__first_point_of_patch_p5_q__SHIFT 0x9
-#define VGT_DEBUG_REG32__first_point_of_edge_p5_q_MASK 0x400
-#define VGT_DEBUG_REG32__first_point_of_edge_p5_q__SHIFT 0xa
-#define VGT_DEBUG_REG32__last_patch_of_tg_p5_q_MASK 0x800
-#define VGT_DEBUG_REG32__last_patch_of_tg_p5_q__SHIFT 0xb
-#define VGT_DEBUG_REG32__tess_topology_p5_q_MASK 0x3000
-#define VGT_DEBUG_REG32__tess_topology_p5_q__SHIFT 0xc
-#define VGT_DEBUG_REG32__pipe5_inner3_rtr_MASK 0x4000
-#define VGT_DEBUG_REG32__pipe5_inner3_rtr__SHIFT 0xe
-#define VGT_DEBUG_REG32__pipe5_inner2_rtr_MASK 0x8000
-#define VGT_DEBUG_REG32__pipe5_inner2_rtr__SHIFT 0xf
-#define VGT_DEBUG_REG32__pg_edge_fifo3_full_MASK 0x10000
-#define VGT_DEBUG_REG32__pg_edge_fifo3_full__SHIFT 0x10
-#define VGT_DEBUG_REG32__pg_edge_fifo2_full_MASK 0x20000
-#define VGT_DEBUG_REG32__pg_edge_fifo2_full__SHIFT 0x11
-#define VGT_DEBUG_REG32__pg_inner3_point_fifo_full_MASK 0x40000
-#define VGT_DEBUG_REG32__pg_inner3_point_fifo_full__SHIFT 0x12
-#define VGT_DEBUG_REG32__pg_outer3_point_fifo_full_MASK 0x80000
-#define VGT_DEBUG_REG32__pg_outer3_point_fifo_full__SHIFT 0x13
-#define VGT_DEBUG_REG32__pg_inner2_point_fifo_full_MASK 0x100000
-#define VGT_DEBUG_REG32__pg_inner2_point_fifo_full__SHIFT 0x14
-#define VGT_DEBUG_REG32__pg_outer2_point_fifo_full_MASK 0x200000
-#define VGT_DEBUG_REG32__pg_outer2_point_fifo_full__SHIFT 0x15
-#define VGT_DEBUG_REG32__pg_inner_point_fifo_full_MASK 0x400000
-#define VGT_DEBUG_REG32__pg_inner_point_fifo_full__SHIFT 0x16
-#define VGT_DEBUG_REG32__pg_outer_point_fifo_full_MASK 0x800000
-#define VGT_DEBUG_REG32__pg_outer_point_fifo_full__SHIFT 0x17
-#define VGT_DEBUG_REG32__inner2_fifos_rtr_MASK 0x1000000
-#define VGT_DEBUG_REG32__inner2_fifos_rtr__SHIFT 0x18
-#define VGT_DEBUG_REG32__inner_fifos_rtr_MASK 0x2000000
-#define VGT_DEBUG_REG32__inner_fifos_rtr__SHIFT 0x19
-#define VGT_DEBUG_REG32__outer_fifos_rtr_MASK 0x4000000
-#define VGT_DEBUG_REG32__outer_fifos_rtr__SHIFT 0x1a
-#define VGT_DEBUG_REG32__fifos_rtr_MASK 0x8000000
-#define VGT_DEBUG_REG32__fifos_rtr__SHIFT 0x1b
-#define VGT_DEBUG_REG32__SPARE_MASK 0xf0000000
-#define VGT_DEBUG_REG32__SPARE__SHIFT 0x1c
-#define VGT_DEBUG_REG33__pipe0_patch_dr_MASK 0x1
-#define VGT_DEBUG_REG33__pipe0_patch_dr__SHIFT 0x0
-#define VGT_DEBUG_REG33__ring3_pipe1_dr_MASK 0x2
-#define VGT_DEBUG_REG33__ring3_pipe1_dr__SHIFT 0x1
-#define VGT_DEBUG_REG33__pipe1_dr_MASK 0x4
-#define VGT_DEBUG_REG33__pipe1_dr__SHIFT 0x2
-#define VGT_DEBUG_REG33__pipe2_dr_MASK 0x8
-#define VGT_DEBUG_REG33__pipe2_dr__SHIFT 0x3
-#define VGT_DEBUG_REG33__pipe0_patch_rtr_MASK 0x10
-#define VGT_DEBUG_REG33__pipe0_patch_rtr__SHIFT 0x4
-#define VGT_DEBUG_REG33__ring2_pipe1_dr_MASK 0x20
-#define VGT_DEBUG_REG33__ring2_pipe1_dr__SHIFT 0x5
-#define VGT_DEBUG_REG33__ring1_pipe1_dr_MASK 0x40
-#define VGT_DEBUG_REG33__ring1_pipe1_dr__SHIFT 0x6
-#define VGT_DEBUG_REG33__pipe2_rtr_MASK 0x80
-#define VGT_DEBUG_REG33__pipe2_rtr__SHIFT 0x7
-#define VGT_DEBUG_REG33__pipe3_dr_MASK 0x100
-#define VGT_DEBUG_REG33__pipe3_dr__SHIFT 0x8
-#define VGT_DEBUG_REG33__pipe3_rtr_MASK 0x200
-#define VGT_DEBUG_REG33__pipe3_rtr__SHIFT 0x9
-#define VGT_DEBUG_REG33__ring2_in_sync_q_MASK 0x400
-#define VGT_DEBUG_REG33__ring2_in_sync_q__SHIFT 0xa
-#define VGT_DEBUG_REG33__ring1_in_sync_q_MASK 0x800
-#define VGT_DEBUG_REG33__ring1_in_sync_q__SHIFT 0xb
-#define VGT_DEBUG_REG33__pipe1_patch_rtr_MASK 0x1000
-#define VGT_DEBUG_REG33__pipe1_patch_rtr__SHIFT 0xc
-#define VGT_DEBUG_REG33__ring3_in_sync_q_MASK 0x2000
-#define VGT_DEBUG_REG33__ring3_in_sync_q__SHIFT 0xd
-#define VGT_DEBUG_REG33__tm_te11_event_rtr_MASK 0x4000
-#define VGT_DEBUG_REG33__tm_te11_event_rtr__SHIFT 0xe
-#define VGT_DEBUG_REG33__first_prim_of_patch_q_MASK 0x8000
-#define VGT_DEBUG_REG33__first_prim_of_patch_q__SHIFT 0xf
-#define VGT_DEBUG_REG33__con_prim_fifo_full_MASK 0x10000
-#define VGT_DEBUG_REG33__con_prim_fifo_full__SHIFT 0x10
-#define VGT_DEBUG_REG33__con_vert_fifo_full_MASK 0x20000
-#define VGT_DEBUG_REG33__con_vert_fifo_full__SHIFT 0x11
-#define VGT_DEBUG_REG33__con_prim_fifo_empty_MASK 0x40000
-#define VGT_DEBUG_REG33__con_prim_fifo_empty__SHIFT 0x12
-#define VGT_DEBUG_REG33__con_vert_fifo_empty_MASK 0x80000
-#define VGT_DEBUG_REG33__con_vert_fifo_empty__SHIFT 0x13
-#define VGT_DEBUG_REG33__last_patch_of_tg_p0_q_MASK 0x100000
-#define VGT_DEBUG_REG33__last_patch_of_tg_p0_q__SHIFT 0x14
-#define VGT_DEBUG_REG33__ring3_valid_p2_MASK 0x200000
-#define VGT_DEBUG_REG33__ring3_valid_p2__SHIFT 0x15
-#define VGT_DEBUG_REG33__ring2_valid_p2_MASK 0x400000
-#define VGT_DEBUG_REG33__ring2_valid_p2__SHIFT 0x16
-#define VGT_DEBUG_REG33__ring1_valid_p2_MASK 0x800000
-#define VGT_DEBUG_REG33__ring1_valid_p2__SHIFT 0x17
-#define VGT_DEBUG_REG33__tess_type_p0_q_MASK 0x3000000
-#define VGT_DEBUG_REG33__tess_type_p0_q__SHIFT 0x18
-#define VGT_DEBUG_REG33__tess_topology_p0_q_MASK 0xc000000
-#define VGT_DEBUG_REG33__tess_topology_p0_q__SHIFT 0x1a
-#define VGT_DEBUG_REG33__te11_out_vert_gs_en_MASK 0x10000000
-#define VGT_DEBUG_REG33__te11_out_vert_gs_en__SHIFT 0x1c
-#define VGT_DEBUG_REG33__con_ring3_busy_MASK 0x20000000
-#define VGT_DEBUG_REG33__con_ring3_busy__SHIFT 0x1d
-#define VGT_DEBUG_REG33__con_ring2_busy_MASK 0x40000000
-#define VGT_DEBUG_REG33__con_ring2_busy__SHIFT 0x1e
-#define VGT_DEBUG_REG33__con_ring1_busy_MASK 0x80000000
-#define VGT_DEBUG_REG33__con_ring1_busy__SHIFT 0x1f
-#define VGT_DEBUG_REG34__con_state_q_MASK 0xf
-#define VGT_DEBUG_REG34__con_state_q__SHIFT 0x0
-#define VGT_DEBUG_REG34__second_cycle_q_MASK 0x10
-#define VGT_DEBUG_REG34__second_cycle_q__SHIFT 0x4
-#define VGT_DEBUG_REG34__process_tri_middle_p0_q_MASK 0x20
-#define VGT_DEBUG_REG34__process_tri_middle_p0_q__SHIFT 0x5
-#define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q_MASK 0x40
-#define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q__SHIFT 0x6
-#define VGT_DEBUG_REG34__process_tri_center_poly_p0_q_MASK 0x80
-#define VGT_DEBUG_REG34__process_tri_center_poly_p0_q__SHIFT 0x7
-#define VGT_DEBUG_REG34__pipe0_patch_dr_MASK 0x100
-#define VGT_DEBUG_REG34__pipe0_patch_dr__SHIFT 0x8
-#define VGT_DEBUG_REG34__pipe0_edge_dr_MASK 0x200
-#define VGT_DEBUG_REG34__pipe0_edge_dr__SHIFT 0x9
-#define VGT_DEBUG_REG34__pipe1_dr_MASK 0x400
-#define VGT_DEBUG_REG34__pipe1_dr__SHIFT 0xa
-#define VGT_DEBUG_REG34__pipe0_patch_rtr_MASK 0x800
-#define VGT_DEBUG_REG34__pipe0_patch_rtr__SHIFT 0xb
-#define VGT_DEBUG_REG34__pipe0_edge_rtr_MASK 0x1000
-#define VGT_DEBUG_REG34__pipe0_edge_rtr__SHIFT 0xc
-#define VGT_DEBUG_REG34__pipe1_rtr_MASK 0x2000
-#define VGT_DEBUG_REG34__pipe1_rtr__SHIFT 0xd
-#define VGT_DEBUG_REG34__outer_parity_p0_q_MASK 0x4000
-#define VGT_DEBUG_REG34__outer_parity_p0_q__SHIFT 0xe
-#define VGT_DEBUG_REG34__parallel_parity_p0_q_MASK 0x8000
-#define VGT_DEBUG_REG34__parallel_parity_p0_q__SHIFT 0xf
-#define VGT_DEBUG_REG34__first_ring_of_patch_p0_q_MASK 0x10000
-#define VGT_DEBUG_REG34__first_ring_of_patch_p0_q__SHIFT 0x10
-#define VGT_DEBUG_REG34__last_ring_of_patch_p0_q_MASK 0x20000
-#define VGT_DEBUG_REG34__last_ring_of_patch_p0_q__SHIFT 0x11
-#define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q_MASK 0x40000
-#define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q__SHIFT 0x12
-#define VGT_DEBUG_REG34__last_point_of_outer_ring_p1_MASK 0x80000
-#define VGT_DEBUG_REG34__last_point_of_outer_ring_p1__SHIFT 0x13
-#define VGT_DEBUG_REG34__last_point_of_inner_ring_p1_MASK 0x100000
-#define VGT_DEBUG_REG34__last_point_of_inner_ring_p1__SHIFT 0x14
-#define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q_MASK 0x200000
-#define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q__SHIFT 0x15
-#define VGT_DEBUG_REG34__advance_outer_point_p1_MASK 0x400000
-#define VGT_DEBUG_REG34__advance_outer_point_p1__SHIFT 0x16
-#define VGT_DEBUG_REG34__advance_inner_point_p1_MASK 0x800000
-#define VGT_DEBUG_REG34__advance_inner_point_p1__SHIFT 0x17
-#define VGT_DEBUG_REG34__next_ring_is_rect_p0_q_MASK 0x1000000
-#define VGT_DEBUG_REG34__next_ring_is_rect_p0_q__SHIFT 0x18
-#define VGT_DEBUG_REG34__pipe1_outer1_rtr_MASK 0x2000000
-#define VGT_DEBUG_REG34__pipe1_outer1_rtr__SHIFT 0x19
-#define VGT_DEBUG_REG34__pipe1_outer2_rtr_MASK 0x4000000
-#define VGT_DEBUG_REG34__pipe1_outer2_rtr__SHIFT 0x1a
-#define VGT_DEBUG_REG34__pipe1_inner1_rtr_MASK 0x8000000
-#define VGT_DEBUG_REG34__pipe1_inner1_rtr__SHIFT 0x1b
-#define VGT_DEBUG_REG34__pipe1_inner2_rtr_MASK 0x10000000
-#define VGT_DEBUG_REG34__pipe1_inner2_rtr__SHIFT 0x1c
-#define VGT_DEBUG_REG34__pipe1_patch_rtr_MASK 0x20000000
-#define VGT_DEBUG_REG34__pipe1_patch_rtr__SHIFT 0x1d
-#define VGT_DEBUG_REG34__pipe1_edge_rtr_MASK 0x40000000
-#define VGT_DEBUG_REG34__pipe1_edge_rtr__SHIFT 0x1e
-#define VGT_DEBUG_REG34__use_stored_inner_q_ring1_MASK 0x80000000
-#define VGT_DEBUG_REG34__use_stored_inner_q_ring1__SHIFT 0x1f
-#define VGT_DEBUG_REG36__VGT_PA_clipp_eop_MASK 0xffffffff
-#define VGT_DEBUG_REG36__VGT_PA_clipp_eop__SHIFT 0x0
-#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK 0xff
-#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT 0x0
-#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
-#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
-#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
-#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
-#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
-#define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
-#define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
-#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
-#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
-#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
-#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
-#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
-#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
-#define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
-#define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff
-#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
-#define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
-#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff
-#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
-#define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
-#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
-#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
-#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
-#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
-#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
-#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
-#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
-#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
-#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
-#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000
-#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
-#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000
-#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
-#define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
-#define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
-#define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
-#define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
-#define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
-#define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
-#define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
-#define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff
-#define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
-#define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff
-#define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
-#define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
-#define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff
-#define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
-#define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
-#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
-#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
-#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
-#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
-#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
-#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
-#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
-#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
-#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define WD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff
-#define WD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
-#define WD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
-#define WD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
-#define WD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff
-#define WD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
-#define WD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
-#define WD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
-#define WD_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff
-#define WD_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
-#define WD_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
-#define WD_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
-#define WD_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff
-#define WD_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
-#define WD_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
-#define WD_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
-#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
-#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
-#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
-#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
-#define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK 0xffffffff
-#define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT 0x0
-#define DIDT_IND_DATA__DIDT_IND_DATA_MASK 0xffffffff
-#define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT 0x0
-#define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK 0x1
-#define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
-#define DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK 0x2
-#define DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT 0x1
-#define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0xc
-#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x2
-#define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK 0x10
-#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
-#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
-#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
-#define DIDT_SQ_CTRL0__UNUSED_0_MASK 0xffffffc0
-#define DIDT_SQ_CTRL0__UNUSED_0__SHIFT 0x6
-#define DIDT_SQ_CTRL1__MIN_POWER_MASK 0xffff
-#define DIDT_SQ_CTRL1__MIN_POWER__SHIFT 0x0
-#define DIDT_SQ_CTRL1__MAX_POWER_MASK 0xffff0000
-#define DIDT_SQ_CTRL1__MAX_POWER__SHIFT 0x10
-#define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
-#define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
-#define DIDT_SQ_CTRL2__UNUSED_0_MASK 0xc000
-#define DIDT_SQ_CTRL2__UNUSED_0__SHIFT 0xe
-#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
-#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
-#define DIDT_SQ_CTRL2__UNUSED_1_MASK 0x4000000
-#define DIDT_SQ_CTRL2__UNUSED_1__SHIFT 0x1a
-#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
-#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
-#define DIDT_SQ_CTRL2__UNUSED_2_MASK 0x80000000
-#define DIDT_SQ_CTRL2__UNUSED_2__SHIFT 0x1f
-#define DIDT_SQ_CTRL_OCP__UNUSED_0_MASK 0xffff
-#define DIDT_SQ_CTRL_OCP__UNUSED_0__SHIFT 0x0
-#define DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000
-#define DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10
-#define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK 0xff
-#define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT 0x0
-#define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK 0xff00
-#define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT 0x8
-#define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK 0xff0000
-#define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT 0x10
-#define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK 0xff000000
-#define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT 0x18
-#define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK 0xff
-#define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT 0x0
-#define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK 0xff00
-#define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT 0x8
-#define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK 0xff0000
-#define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT 0x10
-#define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK 0xff000000
-#define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT 0x18
-#define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK 0xff
-#define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT 0x0
-#define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK 0xff00
-#define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT 0x8
-#define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK 0xff0000
-#define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT 0x10
-#define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK 0xff000000
-#define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT 0x18
-#define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK 0x1
-#define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
-#define DIDT_DB_CTRL0__USE_REF_CLOCK_MASK 0x2
-#define DIDT_DB_CTRL0__USE_REF_CLOCK__SHIFT 0x1
-#define DIDT_DB_CTRL0__PHASE_OFFSET_MASK 0xc
-#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x2
-#define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK 0x10
-#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
-#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
-#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
-#define DIDT_DB_CTRL0__UNUSED_0_MASK 0xffffffc0
-#define DIDT_DB_CTRL0__UNUSED_0__SHIFT 0x6
-#define DIDT_DB_CTRL1__MIN_POWER_MASK 0xffff
-#define DIDT_DB_CTRL1__MIN_POWER__SHIFT 0x0
-#define DIDT_DB_CTRL1__MAX_POWER_MASK 0xffff0000
-#define DIDT_DB_CTRL1__MAX_POWER__SHIFT 0x10
-#define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
-#define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
-#define DIDT_DB_CTRL2__UNUSED_0_MASK 0xc000
-#define DIDT_DB_CTRL2__UNUSED_0__SHIFT 0xe
-#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
-#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
-#define DIDT_DB_CTRL2__UNUSED_1_MASK 0x4000000
-#define DIDT_DB_CTRL2__UNUSED_1__SHIFT 0x1a
-#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
-#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
-#define DIDT_DB_CTRL2__UNUSED_2_MASK 0x80000000
-#define DIDT_DB_CTRL2__UNUSED_2__SHIFT 0x1f
-#define DIDT_DB_CTRL_OCP__UNUSED_0_MASK 0xffff
-#define DIDT_DB_CTRL_OCP__UNUSED_0__SHIFT 0x0
-#define DIDT_DB_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000
-#define DIDT_DB_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10
-#define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK 0xff
-#define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT 0x0
-#define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK 0xff00
-#define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT 0x8
-#define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK 0xff0000
-#define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT 0x10
-#define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK 0xff000000
-#define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT 0x18
-#define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK 0xff
-#define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT 0x0
-#define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK 0xff00
-#define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT 0x8
-#define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK 0xff0000
-#define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT 0x10
-#define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK 0xff000000
-#define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT 0x18
-#define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK 0xff
-#define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT 0x0
-#define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK 0xff00
-#define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT 0x8
-#define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK 0xff0000
-#define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT 0x10
-#define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK 0xff000000
-#define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT 0x18
-#define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK 0x1
-#define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
-#define DIDT_TD_CTRL0__USE_REF_CLOCK_MASK 0x2
-#define DIDT_TD_CTRL0__USE_REF_CLOCK__SHIFT 0x1
-#define DIDT_TD_CTRL0__PHASE_OFFSET_MASK 0xc
-#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x2
-#define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK 0x10
-#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
-#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
-#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
-#define DIDT_TD_CTRL0__UNUSED_0_MASK 0xffffffc0
-#define DIDT_TD_CTRL0__UNUSED_0__SHIFT 0x6
-#define DIDT_TD_CTRL1__MIN_POWER_MASK 0xffff
-#define DIDT_TD_CTRL1__MIN_POWER__SHIFT 0x0
-#define DIDT_TD_CTRL1__MAX_POWER_MASK 0xffff0000
-#define DIDT_TD_CTRL1__MAX_POWER__SHIFT 0x10
-#define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
-#define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
-#define DIDT_TD_CTRL2__UNUSED_0_MASK 0xc000
-#define DIDT_TD_CTRL2__UNUSED_0__SHIFT 0xe
-#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
-#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
-#define DIDT_TD_CTRL2__UNUSED_1_MASK 0x4000000
-#define DIDT_TD_CTRL2__UNUSED_1__SHIFT 0x1a
-#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
-#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
-#define DIDT_TD_CTRL2__UNUSED_2_MASK 0x80000000
-#define DIDT_TD_CTRL2__UNUSED_2__SHIFT 0x1f
-#define DIDT_TD_CTRL_OCP__UNUSED_0_MASK 0xffff
-#define DIDT_TD_CTRL_OCP__UNUSED_0__SHIFT 0x0
-#define DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000
-#define DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10
-#define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK 0xff
-#define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT 0x0
-#define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK 0xff00
-#define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT 0x8
-#define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK 0xff0000
-#define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT 0x10
-#define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK 0xff000000
-#define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT 0x18
-#define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK 0xff
-#define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT 0x0
-#define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK 0xff00
-#define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT 0x8
-#define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK 0xff0000
-#define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT 0x10
-#define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK 0xff000000
-#define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT 0x18
-#define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK 0xff
-#define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT 0x0
-#define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK 0xff00
-#define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT 0x8
-#define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK 0xff0000
-#define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT 0x10
-#define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK 0xff000000
-#define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT 0x18
-#define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK 0x1
-#define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
-#define DIDT_TCP_CTRL0__USE_REF_CLOCK_MASK 0x2
-#define DIDT_TCP_CTRL0__USE_REF_CLOCK__SHIFT 0x1
-#define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK 0xc
-#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x2
-#define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK 0x10
-#define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
-#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
-#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
-#define DIDT_TCP_CTRL0__UNUSED_0_MASK 0xffffffc0
-#define DIDT_TCP_CTRL0__UNUSED_0__SHIFT 0x6
-#define DIDT_TCP_CTRL1__MIN_POWER_MASK 0xffff
-#define DIDT_TCP_CTRL1__MIN_POWER__SHIFT 0x0
-#define DIDT_TCP_CTRL1__MAX_POWER_MASK 0xffff0000
-#define DIDT_TCP_CTRL1__MAX_POWER__SHIFT 0x10
-#define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
-#define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
-#define DIDT_TCP_CTRL2__UNUSED_0_MASK 0xc000
-#define DIDT_TCP_CTRL2__UNUSED_0__SHIFT 0xe
-#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
-#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
-#define DIDT_TCP_CTRL2__UNUSED_1_MASK 0x4000000
-#define DIDT_TCP_CTRL2__UNUSED_1__SHIFT 0x1a
-#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
-#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
-#define DIDT_TCP_CTRL2__UNUSED_2_MASK 0x80000000
-#define DIDT_TCP_CTRL2__UNUSED_2__SHIFT 0x1f
-#define DIDT_TCP_CTRL_OCP__UNUSED_0_MASK 0xffff
-#define DIDT_TCP_CTRL_OCP__UNUSED_0__SHIFT 0x0
-#define DIDT_TCP_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000
-#define DIDT_TCP_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10
-#define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK 0xff
-#define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT 0x0
-#define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK 0xff00
-#define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT 0x8
-#define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK 0xff0000
-#define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT 0x10
-#define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK 0xff000000
-#define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT 0x18
-#define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK 0xff
-#define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT 0x0
-#define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK 0xff00
-#define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT 0x8
-#define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK 0xff0000
-#define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT 0x10
-#define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK 0xff000000
-#define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT 0x18
-#define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK 0xff
-#define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT 0x0
-#define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK 0xff00
-#define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT 0x8
-#define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK 0xff0000
-#define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT 0x10
-#define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK 0xff000000
-#define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT 0x18
-#define DIDT_DBR_CTRL0__DIDT_CTRL_EN_MASK 0x1
-#define DIDT_DBR_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
-#define DIDT_DBR_CTRL0__USE_REF_CLOCK_MASK 0x2
-#define DIDT_DBR_CTRL0__USE_REF_CLOCK__SHIFT 0x1
-#define DIDT_DBR_CTRL0__PHASE_OFFSET_MASK 0xc
-#define DIDT_DBR_CTRL0__PHASE_OFFSET__SHIFT 0x2
-#define DIDT_DBR_CTRL0__DIDT_CTRL_RST_MASK 0x10
-#define DIDT_DBR_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
-#define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
-#define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
-#define DIDT_DBR_CTRL0__UNUSED_0_MASK 0xffffffc0
-#define DIDT_DBR_CTRL0__UNUSED_0__SHIFT 0x6
-#define DIDT_DBR_CTRL1__MIN_POWER_MASK 0xffff
-#define DIDT_DBR_CTRL1__MIN_POWER__SHIFT 0x0
-#define DIDT_DBR_CTRL1__MAX_POWER_MASK 0xffff0000
-#define DIDT_DBR_CTRL1__MAX_POWER__SHIFT 0x10
-#define DIDT_DBR_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
-#define DIDT_DBR_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
-#define DIDT_DBR_CTRL2__UNUSED_0_MASK 0xc000
-#define DIDT_DBR_CTRL2__UNUSED_0__SHIFT 0xe
-#define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
-#define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
-#define DIDT_DBR_CTRL2__UNUSED_1_MASK 0x4000000
-#define DIDT_DBR_CTRL2__UNUSED_1__SHIFT 0x1a
-#define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
-#define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
-#define DIDT_DBR_CTRL2__UNUSED_2_MASK 0x80000000
-#define DIDT_DBR_CTRL2__UNUSED_2__SHIFT 0x1f
-#define DIDT_DBR_CTRL_OCP__UNUSED_0_MASK 0xffff
-#define DIDT_DBR_CTRL_OCP__UNUSED_0__SHIFT 0x0
-#define DIDT_DBR_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000
-#define DIDT_DBR_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10
-#define DIDT_DBR_WEIGHT0_3__WEIGHT0_MASK 0xff
-#define DIDT_DBR_WEIGHT0_3__WEIGHT0__SHIFT 0x0
-#define DIDT_DBR_WEIGHT0_3__WEIGHT1_MASK 0xff00
-#define DIDT_DBR_WEIGHT0_3__WEIGHT1__SHIFT 0x8
-#define DIDT_DBR_WEIGHT0_3__WEIGHT2_MASK 0xff0000
-#define DIDT_DBR_WEIGHT0_3__WEIGHT2__SHIFT 0x10
-#define DIDT_DBR_WEIGHT0_3__WEIGHT3_MASK 0xff000000
-#define DIDT_DBR_WEIGHT0_3__WEIGHT3__SHIFT 0x18
-#define DIDT_DBR_WEIGHT4_7__WEIGHT4_MASK 0xff
-#define DIDT_DBR_WEIGHT4_7__WEIGHT4__SHIFT 0x0
-#define DIDT_DBR_WEIGHT4_7__WEIGHT5_MASK 0xff00
-#define DIDT_DBR_WEIGHT4_7__WEIGHT5__SHIFT 0x8
-#define DIDT_DBR_WEIGHT4_7__WEIGHT6_MASK 0xff0000
-#define DIDT_DBR_WEIGHT4_7__WEIGHT6__SHIFT 0x10
-#define DIDT_DBR_WEIGHT4_7__WEIGHT7_MASK 0xff000000
-#define DIDT_DBR_WEIGHT4_7__WEIGHT7__SHIFT 0x18
-#define DIDT_DBR_WEIGHT8_11__WEIGHT8_MASK 0xff
-#define DIDT_DBR_WEIGHT8_11__WEIGHT8__SHIFT 0x0
-#define DIDT_DBR_WEIGHT8_11__WEIGHT9_MASK 0xff00
-#define DIDT_DBR_WEIGHT8_11__WEIGHT9__SHIFT 0x8
-#define DIDT_DBR_WEIGHT8_11__WEIGHT10_MASK 0xff0000
-#define DIDT_DBR_WEIGHT8_11__WEIGHT10__SHIFT 0x10
-#define DIDT_DBR_WEIGHT8_11__WEIGHT11_MASK 0xff000000
-#define DIDT_DBR_WEIGHT8_11__WEIGHT11__SHIFT 0x18
-
-#endif /* GFX_8_1_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_enum.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_enum.h
deleted file mode 100644
index 05b80f2bb..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_enum.h
+++ /dev/null
@@ -1,1198 +0,0 @@
-/*
- * GMC_8_1 Register documentation
- *
- * Copyright (C) 2014 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef GMC_8_1_ENUM_H
-#define GMC_8_1_ENUM_H
-
-typedef enum SurfaceEndian {
- ENDIAN_NONE = 0x0,
- ENDIAN_8IN16 = 0x1,
- ENDIAN_8IN32 = 0x2,
- ENDIAN_8IN64 = 0x3,
-} SurfaceEndian;
-typedef enum ArrayMode {
- ARRAY_LINEAR_GENERAL = 0x0,
- ARRAY_LINEAR_ALIGNED = 0x1,
- ARRAY_1D_TILED_THIN1 = 0x2,
- ARRAY_1D_TILED_THICK = 0x3,
- ARRAY_2D_TILED_THIN1 = 0x4,
- ARRAY_PRT_TILED_THIN1 = 0x5,
- ARRAY_PRT_2D_TILED_THIN1 = 0x6,
- ARRAY_2D_TILED_THICK = 0x7,
- ARRAY_2D_TILED_XTHICK = 0x8,
- ARRAY_PRT_TILED_THICK = 0x9,
- ARRAY_PRT_2D_TILED_THICK = 0xa,
- ARRAY_PRT_3D_TILED_THIN1 = 0xb,
- ARRAY_3D_TILED_THIN1 = 0xc,
- ARRAY_3D_TILED_THICK = 0xd,
- ARRAY_3D_TILED_XTHICK = 0xe,
- ARRAY_PRT_3D_TILED_THICK = 0xf,
-} ArrayMode;
-typedef enum PipeTiling {
- CONFIG_1_PIPE = 0x0,
- CONFIG_2_PIPE = 0x1,
- CONFIG_4_PIPE = 0x2,
- CONFIG_8_PIPE = 0x3,
-} PipeTiling;
-typedef enum BankTiling {
- CONFIG_4_BANK = 0x0,
- CONFIG_8_BANK = 0x1,
-} BankTiling;
-typedef enum GroupInterleave {
- CONFIG_256B_GROUP = 0x0,
- CONFIG_512B_GROUP = 0x1,
-} GroupInterleave;
-typedef enum RowTiling {
- CONFIG_1KB_ROW = 0x0,
- CONFIG_2KB_ROW = 0x1,
- CONFIG_4KB_ROW = 0x2,
- CONFIG_8KB_ROW = 0x3,
- CONFIG_1KB_ROW_OPT = 0x4,
- CONFIG_2KB_ROW_OPT = 0x5,
- CONFIG_4KB_ROW_OPT = 0x6,
- CONFIG_8KB_ROW_OPT = 0x7,
-} RowTiling;
-typedef enum BankSwapBytes {
- CONFIG_128B_SWAPS = 0x0,
- CONFIG_256B_SWAPS = 0x1,
- CONFIG_512B_SWAPS = 0x2,
- CONFIG_1KB_SWAPS = 0x3,
-} BankSwapBytes;
-typedef enum SampleSplitBytes {
- CONFIG_1KB_SPLIT = 0x0,
- CONFIG_2KB_SPLIT = 0x1,
- CONFIG_4KB_SPLIT = 0x2,
- CONFIG_8KB_SPLIT = 0x3,
-} SampleSplitBytes;
-typedef enum NumPipes {
- ADDR_CONFIG_1_PIPE = 0x0,
- ADDR_CONFIG_2_PIPE = 0x1,
- ADDR_CONFIG_4_PIPE = 0x2,
- ADDR_CONFIG_8_PIPE = 0x3,
-} NumPipes;
-typedef enum PipeInterleaveSize {
- ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
- ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
-} PipeInterleaveSize;
-typedef enum BankInterleaveSize {
- ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
- ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
- ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
- ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
-} BankInterleaveSize;
-typedef enum NumShaderEngines {
- ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
- ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
-} NumShaderEngines;
-typedef enum ShaderEngineTileSize {
- ADDR_CONFIG_SE_TILE_16 = 0x0,
- ADDR_CONFIG_SE_TILE_32 = 0x1,
-} ShaderEngineTileSize;
-typedef enum NumGPUs {
- ADDR_CONFIG_1_GPU = 0x0,
- ADDR_CONFIG_2_GPU = 0x1,
- ADDR_CONFIG_4_GPU = 0x2,
-} NumGPUs;
-typedef enum MultiGPUTileSize {
- ADDR_CONFIG_GPU_TILE_16 = 0x0,
- ADDR_CONFIG_GPU_TILE_32 = 0x1,
- ADDR_CONFIG_GPU_TILE_64 = 0x2,
- ADDR_CONFIG_GPU_TILE_128 = 0x3,
-} MultiGPUTileSize;
-typedef enum RowSize {
- ADDR_CONFIG_1KB_ROW = 0x0,
- ADDR_CONFIG_2KB_ROW = 0x1,
- ADDR_CONFIG_4KB_ROW = 0x2,
-} RowSize;
-typedef enum NumLowerPipes {
- ADDR_CONFIG_1_LOWER_PIPES = 0x0,
- ADDR_CONFIG_2_LOWER_PIPES = 0x1,
-} NumLowerPipes;
-typedef enum DebugBlockId {
- DBG_CLIENT_BLKID_RESERVED = 0x0,
- DBG_CLIENT_BLKID_dbg = 0x1,
- DBG_CLIENT_BLKID_scf2 = 0x2,
- DBG_CLIENT_BLKID_mcd5 = 0x3,
- DBG_CLIENT_BLKID_vmc = 0x4,
- DBG_CLIENT_BLKID_sx30 = 0x5,
- DBG_CLIENT_BLKID_mcd2 = 0x6,
- DBG_CLIENT_BLKID_bci1 = 0x7,
- DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0x8,
- DBG_CLIENT_BLKID_mcc0 = 0x9,
- DBG_CLIENT_BLKID_uvdf_0 = 0xa,
- DBG_CLIENT_BLKID_uvdf_1 = 0xb,
- DBG_CLIENT_BLKID_uvdf_2 = 0xc,
- DBG_CLIENT_BLKID_uvdi_0 = 0xd,
- DBG_CLIENT_BLKID_bci0 = 0xe,
- DBG_CLIENT_BLKID_vcec0_0 = 0xf,
- DBG_CLIENT_BLKID_cb100 = 0x10,
- DBG_CLIENT_BLKID_cb001 = 0x11,
- DBG_CLIENT_BLKID_mcd4 = 0x12,
- DBG_CLIENT_BLKID_tmonw00 = 0x13,
- DBG_CLIENT_BLKID_cb101 = 0x14,
- DBG_CLIENT_BLKID_sx10 = 0x15,
- DBG_CLIENT_BLKID_cb301 = 0x16,
- DBG_CLIENT_BLKID_tmonw01 = 0x17,
- DBG_CLIENT_BLKID_vcea0_0 = 0x18,
- DBG_CLIENT_BLKID_vcea0_1 = 0x19,
- DBG_CLIENT_BLKID_vcea0_2 = 0x1a,
- DBG_CLIENT_BLKID_vcea0_3 = 0x1b,
- DBG_CLIENT_BLKID_scf1 = 0x1c,
- DBG_CLIENT_BLKID_sx20 = 0x1d,
- DBG_CLIENT_BLKID_spim1 = 0x1e,
- DBG_CLIENT_BLKID_pa10 = 0x1f,
- DBG_CLIENT_BLKID_pa00 = 0x20,
- DBG_CLIENT_BLKID_gmcon = 0x21,
- DBG_CLIENT_BLKID_mcb = 0x22,
- DBG_CLIENT_BLKID_vgt0 = 0x23,
- DBG_CLIENT_BLKID_pc0 = 0x24,
- DBG_CLIENT_BLKID_bci2 = 0x25,
- DBG_CLIENT_BLKID_uvdb_0 = 0x26,
- DBG_CLIENT_BLKID_spim3 = 0x27,
- DBG_CLIENT_BLKID_cpc_0 = 0x28,
- DBG_CLIENT_BLKID_cpc_1 = 0x29,
- DBG_CLIENT_BLKID_uvdm_0 = 0x2a,
- DBG_CLIENT_BLKID_uvdm_1 = 0x2b,
- DBG_CLIENT_BLKID_uvdm_2 = 0x2c,
- DBG_CLIENT_BLKID_uvdm_3 = 0x2d,
- DBG_CLIENT_BLKID_cb000 = 0x2e,
- DBG_CLIENT_BLKID_spim0 = 0x2f,
- DBG_CLIENT_BLKID_mcc2 = 0x30,
- DBG_CLIENT_BLKID_ds0 = 0x31,
- DBG_CLIENT_BLKID_srbm = 0x32,
- DBG_CLIENT_BLKID_ih = 0x33,
- DBG_CLIENT_BLKID_sem = 0x34,
- DBG_CLIENT_BLKID_sdma_0 = 0x35,
- DBG_CLIENT_BLKID_sdma_1 = 0x36,
- DBG_CLIENT_BLKID_hdp = 0x37,
- DBG_CLIENT_BLKID_acp_0 = 0x38,
- DBG_CLIENT_BLKID_acp_1 = 0x39,
- DBG_CLIENT_BLKID_cb200 = 0x3a,
- DBG_CLIENT_BLKID_scf3 = 0x3b,
- DBG_CLIENT_BLKID_vceb1_0 = 0x3c,
- DBG_CLIENT_BLKID_vcea1_0 = 0x3d,
- DBG_CLIENT_BLKID_vcea1_1 = 0x3e,
- DBG_CLIENT_BLKID_vcea1_2 = 0x3f,
- DBG_CLIENT_BLKID_vcea1_3 = 0x40,
- DBG_CLIENT_BLKID_bci3 = 0x41,
- DBG_CLIENT_BLKID_mcd0 = 0x42,
- DBG_CLIENT_BLKID_pa11 = 0x43,
- DBG_CLIENT_BLKID_pa01 = 0x44,
- DBG_CLIENT_BLKID_cb201 = 0x45,
- DBG_CLIENT_BLKID_spim2 = 0x46,
- DBG_CLIENT_BLKID_vgt2 = 0x47,
- DBG_CLIENT_BLKID_pc2 = 0x48,
- DBG_CLIENT_BLKID_smu_0 = 0x49,
- DBG_CLIENT_BLKID_smu_1 = 0x4a,
- DBG_CLIENT_BLKID_smu_2 = 0x4b,
- DBG_CLIENT_BLKID_cb1 = 0x4c,
- DBG_CLIENT_BLKID_ia0 = 0x4d,
- DBG_CLIENT_BLKID_wd = 0x4e,
- DBG_CLIENT_BLKID_ia1 = 0x4f,
- DBG_CLIENT_BLKID_vcec1_0 = 0x50,
- DBG_CLIENT_BLKID_scf0 = 0x51,
- DBG_CLIENT_BLKID_vgt1 = 0x52,
- DBG_CLIENT_BLKID_pc1 = 0x53,
- DBG_CLIENT_BLKID_cb0 = 0x54,
- DBG_CLIENT_BLKID_gdc_one_0 = 0x55,
- DBG_CLIENT_BLKID_gdc_one_1 = 0x56,
- DBG_CLIENT_BLKID_gdc_one_2 = 0x57,
- DBG_CLIENT_BLKID_gdc_one_3 = 0x58,
- DBG_CLIENT_BLKID_gdc_one_4 = 0x59,
- DBG_CLIENT_BLKID_gdc_one_5 = 0x5a,
- DBG_CLIENT_BLKID_gdc_one_6 = 0x5b,
- DBG_CLIENT_BLKID_gdc_one_7 = 0x5c,
- DBG_CLIENT_BLKID_gdc_one_8 = 0x5d,
- DBG_CLIENT_BLKID_gdc_one_9 = 0x5e,
- DBG_CLIENT_BLKID_gdc_one_10 = 0x5f,
- DBG_CLIENT_BLKID_gdc_one_11 = 0x60,
- DBG_CLIENT_BLKID_gdc_one_12 = 0x61,
- DBG_CLIENT_BLKID_gdc_one_13 = 0x62,
- DBG_CLIENT_BLKID_gdc_one_14 = 0x63,
- DBG_CLIENT_BLKID_gdc_one_15 = 0x64,
- DBG_CLIENT_BLKID_gdc_one_16 = 0x65,
- DBG_CLIENT_BLKID_gdc_one_17 = 0x66,
- DBG_CLIENT_BLKID_gdc_one_18 = 0x67,
- DBG_CLIENT_BLKID_gdc_one_19 = 0x68,
- DBG_CLIENT_BLKID_gdc_one_20 = 0x69,
- DBG_CLIENT_BLKID_gdc_one_21 = 0x6a,
- DBG_CLIENT_BLKID_gdc_one_22 = 0x6b,
- DBG_CLIENT_BLKID_gdc_one_23 = 0x6c,
- DBG_CLIENT_BLKID_gdc_one_24 = 0x6d,
- DBG_CLIENT_BLKID_gdc_one_25 = 0x6e,
- DBG_CLIENT_BLKID_gdc_one_26 = 0x6f,
- DBG_CLIENT_BLKID_gdc_one_27 = 0x70,
- DBG_CLIENT_BLKID_gdc_one_28 = 0x71,
- DBG_CLIENT_BLKID_gdc_one_29 = 0x72,
- DBG_CLIENT_BLKID_gdc_one_30 = 0x73,
- DBG_CLIENT_BLKID_gdc_one_31 = 0x74,
- DBG_CLIENT_BLKID_gdc_one_32 = 0x75,
- DBG_CLIENT_BLKID_gdc_one_33 = 0x76,
- DBG_CLIENT_BLKID_gdc_one_34 = 0x77,
- DBG_CLIENT_BLKID_gdc_one_35 = 0x78,
- DBG_CLIENT_BLKID_vceb0_0 = 0x79,
- DBG_CLIENT_BLKID_vgt3 = 0x7a,
- DBG_CLIENT_BLKID_pc3 = 0x7b,
- DBG_CLIENT_BLKID_mcd3 = 0x7c,
- DBG_CLIENT_BLKID_uvdu_0 = 0x7d,
- DBG_CLIENT_BLKID_uvdu_1 = 0x7e,
- DBG_CLIENT_BLKID_uvdu_2 = 0x7f,
- DBG_CLIENT_BLKID_uvdu_3 = 0x80,
- DBG_CLIENT_BLKID_uvdu_4 = 0x81,
- DBG_CLIENT_BLKID_uvdu_5 = 0x82,
- DBG_CLIENT_BLKID_uvdu_6 = 0x83,
- DBG_CLIENT_BLKID_cb300 = 0x84,
- DBG_CLIENT_BLKID_mcd1 = 0x85,
- DBG_CLIENT_BLKID_sx00 = 0x86,
- DBG_CLIENT_BLKID_uvdc_0 = 0x87,
- DBG_CLIENT_BLKID_uvdc_1 = 0x88,
- DBG_CLIENT_BLKID_mcc3 = 0x89,
- DBG_CLIENT_BLKID_cpg_0 = 0x8a,
- DBG_CLIENT_BLKID_cpg_1 = 0x8b,
- DBG_CLIENT_BLKID_gck = 0x8c,
- DBG_CLIENT_BLKID_mcc1 = 0x8d,
- DBG_CLIENT_BLKID_cpf_0 = 0x8e,
- DBG_CLIENT_BLKID_cpf_1 = 0x8f,
- DBG_CLIENT_BLKID_rlc = 0x90,
- DBG_CLIENT_BLKID_grbm = 0x91,
- DBG_CLIENT_BLKID_sammsp = 0x92,
- DBG_CLIENT_BLKID_dci_pg = 0x93,
- DBG_CLIENT_BLKID_dci_0 = 0x94,
- DBG_CLIENT_BLKID_dccg0_0 = 0x95,
- DBG_CLIENT_BLKID_dccg0_1 = 0x96,
- DBG_CLIENT_BLKID_dcfe01_0 = 0x97,
- DBG_CLIENT_BLKID_dcfe02_0 = 0x98,
- DBG_CLIENT_BLKID_dcfe03_0 = 0x99,
- DBG_CLIENT_BLKID_dcfe04_0 = 0x9a,
- DBG_CLIENT_BLKID_dcfe05_0 = 0x9b,
- DBG_CLIENT_BLKID_dcfe06_0 = 0x9c,
- DBG_CLIENT_BLKID_RESERVED_LAST = 0x9d,
-} DebugBlockId;
-typedef enum DebugBlockId_OLD {
- DBG_BLOCK_ID_RESERVED = 0x0,
- DBG_BLOCK_ID_DBG = 0x1,
- DBG_BLOCK_ID_VMC = 0x2,
- DBG_BLOCK_ID_PDMA = 0x3,
- DBG_BLOCK_ID_CG = 0x4,
- DBG_BLOCK_ID_SRBM = 0x5,
- DBG_BLOCK_ID_GRBM = 0x6,
- DBG_BLOCK_ID_RLC = 0x7,
- DBG_BLOCK_ID_CSC = 0x8,
- DBG_BLOCK_ID_SEM = 0x9,
- DBG_BLOCK_ID_IH = 0xa,
- DBG_BLOCK_ID_SC = 0xb,
- DBG_BLOCK_ID_SQ = 0xc,
- DBG_BLOCK_ID_AVP = 0xd,
- DBG_BLOCK_ID_GMCON = 0xe,
- DBG_BLOCK_ID_SMU = 0xf,
- DBG_BLOCK_ID_DMA0 = 0x10,
- DBG_BLOCK_ID_DMA1 = 0x11,
- DBG_BLOCK_ID_SPIM = 0x12,
- DBG_BLOCK_ID_GDS = 0x13,
- DBG_BLOCK_ID_SPIS = 0x14,
- DBG_BLOCK_ID_UNUSED0 = 0x15,
- DBG_BLOCK_ID_PA0 = 0x16,
- DBG_BLOCK_ID_PA1 = 0x17,
- DBG_BLOCK_ID_CP0 = 0x18,
- DBG_BLOCK_ID_CP1 = 0x19,
- DBG_BLOCK_ID_CP2 = 0x1a,
- DBG_BLOCK_ID_UNUSED1 = 0x1b,
- DBG_BLOCK_ID_UVDU = 0x1c,
- DBG_BLOCK_ID_UVDM = 0x1d,
- DBG_BLOCK_ID_VCE = 0x1e,
- DBG_BLOCK_ID_UNUSED2 = 0x1f,
- DBG_BLOCK_ID_VGT0 = 0x20,
- DBG_BLOCK_ID_VGT1 = 0x21,
- DBG_BLOCK_ID_IA = 0x22,
- DBG_BLOCK_ID_UNUSED3 = 0x23,
- DBG_BLOCK_ID_SCT0 = 0x24,
- DBG_BLOCK_ID_SCT1 = 0x25,
- DBG_BLOCK_ID_SPM0 = 0x26,
- DBG_BLOCK_ID_SPM1 = 0x27,
- DBG_BLOCK_ID_TCAA = 0x28,
- DBG_BLOCK_ID_TCAB = 0x29,
- DBG_BLOCK_ID_TCCA = 0x2a,
- DBG_BLOCK_ID_TCCB = 0x2b,
- DBG_BLOCK_ID_MCC0 = 0x2c,
- DBG_BLOCK_ID_MCC1 = 0x2d,
- DBG_BLOCK_ID_MCC2 = 0x2e,
- DBG_BLOCK_ID_MCC3 = 0x2f,
- DBG_BLOCK_ID_SX0 = 0x30,
- DBG_BLOCK_ID_SX1 = 0x31,
- DBG_BLOCK_ID_SX2 = 0x32,
- DBG_BLOCK_ID_SX3 = 0x33,
- DBG_BLOCK_ID_UNUSED4 = 0x34,
- DBG_BLOCK_ID_UNUSED5 = 0x35,
- DBG_BLOCK_ID_UNUSED6 = 0x36,
- DBG_BLOCK_ID_UNUSED7 = 0x37,
- DBG_BLOCK_ID_PC0 = 0x38,
- DBG_BLOCK_ID_PC1 = 0x39,
- DBG_BLOCK_ID_UNUSED8 = 0x3a,
- DBG_BLOCK_ID_UNUSED9 = 0x3b,
- DBG_BLOCK_ID_UNUSED10 = 0x3c,
- DBG_BLOCK_ID_UNUSED11 = 0x3d,
- DBG_BLOCK_ID_MCB = 0x3e,
- DBG_BLOCK_ID_UNUSED12 = 0x3f,
- DBG_BLOCK_ID_SCB0 = 0x40,
- DBG_BLOCK_ID_SCB1 = 0x41,
- DBG_BLOCK_ID_UNUSED13 = 0x42,
- DBG_BLOCK_ID_UNUSED14 = 0x43,
- DBG_BLOCK_ID_SCF0 = 0x44,
- DBG_BLOCK_ID_SCF1 = 0x45,
- DBG_BLOCK_ID_UNUSED15 = 0x46,
- DBG_BLOCK_ID_UNUSED16 = 0x47,
- DBG_BLOCK_ID_BCI0 = 0x48,
- DBG_BLOCK_ID_BCI1 = 0x49,
- DBG_BLOCK_ID_BCI2 = 0x4a,
- DBG_BLOCK_ID_BCI3 = 0x4b,
- DBG_BLOCK_ID_UNUSED17 = 0x4c,
- DBG_BLOCK_ID_UNUSED18 = 0x4d,
- DBG_BLOCK_ID_UNUSED19 = 0x4e,
- DBG_BLOCK_ID_UNUSED20 = 0x4f,
- DBG_BLOCK_ID_CB00 = 0x50,
- DBG_BLOCK_ID_CB01 = 0x51,
- DBG_BLOCK_ID_CB02 = 0x52,
- DBG_BLOCK_ID_CB03 = 0x53,
- DBG_BLOCK_ID_CB04 = 0x54,
- DBG_BLOCK_ID_UNUSED21 = 0x55,
- DBG_BLOCK_ID_UNUSED22 = 0x56,
- DBG_BLOCK_ID_UNUSED23 = 0x57,
- DBG_BLOCK_ID_CB10 = 0x58,
- DBG_BLOCK_ID_CB11 = 0x59,
- DBG_BLOCK_ID_CB12 = 0x5a,
- DBG_BLOCK_ID_CB13 = 0x5b,
- DBG_BLOCK_ID_CB14 = 0x5c,
- DBG_BLOCK_ID_UNUSED24 = 0x5d,
- DBG_BLOCK_ID_UNUSED25 = 0x5e,
- DBG_BLOCK_ID_UNUSED26 = 0x5f,
- DBG_BLOCK_ID_TCP0 = 0x60,
- DBG_BLOCK_ID_TCP1 = 0x61,
- DBG_BLOCK_ID_TCP2 = 0x62,
- DBG_BLOCK_ID_TCP3 = 0x63,
- DBG_BLOCK_ID_TCP4 = 0x64,
- DBG_BLOCK_ID_TCP5 = 0x65,
- DBG_BLOCK_ID_TCP6 = 0x66,
- DBG_BLOCK_ID_TCP7 = 0x67,
- DBG_BLOCK_ID_TCP8 = 0x68,
- DBG_BLOCK_ID_TCP9 = 0x69,
- DBG_BLOCK_ID_TCP10 = 0x6a,
- DBG_BLOCK_ID_TCP11 = 0x6b,
- DBG_BLOCK_ID_TCP12 = 0x6c,
- DBG_BLOCK_ID_TCP13 = 0x6d,
- DBG_BLOCK_ID_TCP14 = 0x6e,
- DBG_BLOCK_ID_TCP15 = 0x6f,
- DBG_BLOCK_ID_TCP16 = 0x70,
- DBG_BLOCK_ID_TCP17 = 0x71,
- DBG_BLOCK_ID_TCP18 = 0x72,
- DBG_BLOCK_ID_TCP19 = 0x73,
- DBG_BLOCK_ID_TCP20 = 0x74,
- DBG_BLOCK_ID_TCP21 = 0x75,
- DBG_BLOCK_ID_TCP22 = 0x76,
- DBG_BLOCK_ID_TCP23 = 0x77,
- DBG_BLOCK_ID_TCP_RESERVED0 = 0x78,
- DBG_BLOCK_ID_TCP_RESERVED1 = 0x79,
- DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a,
- DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b,
- DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c,
- DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d,
- DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e,
- DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f,
- DBG_BLOCK_ID_DB00 = 0x80,
- DBG_BLOCK_ID_DB01 = 0x81,
- DBG_BLOCK_ID_DB02 = 0x82,
- DBG_BLOCK_ID_DB03 = 0x83,
- DBG_BLOCK_ID_DB04 = 0x84,
- DBG_BLOCK_ID_UNUSED27 = 0x85,
- DBG_BLOCK_ID_UNUSED28 = 0x86,
- DBG_BLOCK_ID_UNUSED29 = 0x87,
- DBG_BLOCK_ID_DB10 = 0x88,
- DBG_BLOCK_ID_DB11 = 0x89,
- DBG_BLOCK_ID_DB12 = 0x8a,
- DBG_BLOCK_ID_DB13 = 0x8b,
- DBG_BLOCK_ID_DB14 = 0x8c,
- DBG_BLOCK_ID_UNUSED30 = 0x8d,
- DBG_BLOCK_ID_UNUSED31 = 0x8e,
- DBG_BLOCK_ID_UNUSED32 = 0x8f,
- DBG_BLOCK_ID_TCC0 = 0x90,
- DBG_BLOCK_ID_TCC1 = 0x91,
- DBG_BLOCK_ID_TCC2 = 0x92,
- DBG_BLOCK_ID_TCC3 = 0x93,
- DBG_BLOCK_ID_TCC4 = 0x94,
- DBG_BLOCK_ID_TCC5 = 0x95,
- DBG_BLOCK_ID_TCC6 = 0x96,
- DBG_BLOCK_ID_TCC7 = 0x97,
- DBG_BLOCK_ID_SPS00 = 0x98,
- DBG_BLOCK_ID_SPS01 = 0x99,
- DBG_BLOCK_ID_SPS02 = 0x9a,
- DBG_BLOCK_ID_SPS10 = 0x9b,
- DBG_BLOCK_ID_SPS11 = 0x9c,
- DBG_BLOCK_ID_SPS12 = 0x9d,
- DBG_BLOCK_ID_UNUSED33 = 0x9e,
- DBG_BLOCK_ID_UNUSED34 = 0x9f,
- DBG_BLOCK_ID_TA00 = 0xa0,
- DBG_BLOCK_ID_TA01 = 0xa1,
- DBG_BLOCK_ID_TA02 = 0xa2,
- DBG_BLOCK_ID_TA03 = 0xa3,
- DBG_BLOCK_ID_TA04 = 0xa4,
- DBG_BLOCK_ID_TA05 = 0xa5,
- DBG_BLOCK_ID_TA06 = 0xa6,
- DBG_BLOCK_ID_TA07 = 0xa7,
- DBG_BLOCK_ID_TA08 = 0xa8,
- DBG_BLOCK_ID_TA09 = 0xa9,
- DBG_BLOCK_ID_TA0A = 0xaa,
- DBG_BLOCK_ID_TA0B = 0xab,
- DBG_BLOCK_ID_UNUSED35 = 0xac,
- DBG_BLOCK_ID_UNUSED36 = 0xad,
- DBG_BLOCK_ID_UNUSED37 = 0xae,
- DBG_BLOCK_ID_UNUSED38 = 0xaf,
- DBG_BLOCK_ID_TA10 = 0xb0,
- DBG_BLOCK_ID_TA11 = 0xb1,
- DBG_BLOCK_ID_TA12 = 0xb2,
- DBG_BLOCK_ID_TA13 = 0xb3,
- DBG_BLOCK_ID_TA14 = 0xb4,
- DBG_BLOCK_ID_TA15 = 0xb5,
- DBG_BLOCK_ID_TA16 = 0xb6,
- DBG_BLOCK_ID_TA17 = 0xb7,
- DBG_BLOCK_ID_TA18 = 0xb8,
- DBG_BLOCK_ID_TA19 = 0xb9,
- DBG_BLOCK_ID_TA1A = 0xba,
- DBG_BLOCK_ID_TA1B = 0xbb,
- DBG_BLOCK_ID_UNUSED39 = 0xbc,
- DBG_BLOCK_ID_UNUSED40 = 0xbd,
- DBG_BLOCK_ID_UNUSED41 = 0xbe,
- DBG_BLOCK_ID_UNUSED42 = 0xbf,
- DBG_BLOCK_ID_TD00 = 0xc0,
- DBG_BLOCK_ID_TD01 = 0xc1,
- DBG_BLOCK_ID_TD02 = 0xc2,
- DBG_BLOCK_ID_TD03 = 0xc3,
- DBG_BLOCK_ID_TD04 = 0xc4,
- DBG_BLOCK_ID_TD05 = 0xc5,
- DBG_BLOCK_ID_TD06 = 0xc6,
- DBG_BLOCK_ID_TD07 = 0xc7,
- DBG_BLOCK_ID_TD08 = 0xc8,
- DBG_BLOCK_ID_TD09 = 0xc9,
- DBG_BLOCK_ID_TD0A = 0xca,
- DBG_BLOCK_ID_TD0B = 0xcb,
- DBG_BLOCK_ID_UNUSED43 = 0xcc,
- DBG_BLOCK_ID_UNUSED44 = 0xcd,
- DBG_BLOCK_ID_UNUSED45 = 0xce,
- DBG_BLOCK_ID_UNUSED46 = 0xcf,
- DBG_BLOCK_ID_TD10 = 0xd0,
- DBG_BLOCK_ID_TD11 = 0xd1,
- DBG_BLOCK_ID_TD12 = 0xd2,
- DBG_BLOCK_ID_TD13 = 0xd3,
- DBG_BLOCK_ID_TD14 = 0xd4,
- DBG_BLOCK_ID_TD15 = 0xd5,
- DBG_BLOCK_ID_TD16 = 0xd6,
- DBG_BLOCK_ID_TD17 = 0xd7,
- DBG_BLOCK_ID_TD18 = 0xd8,
- DBG_BLOCK_ID_TD19 = 0xd9,
- DBG_BLOCK_ID_TD1A = 0xda,
- DBG_BLOCK_ID_TD1B = 0xdb,
- DBG_BLOCK_ID_UNUSED47 = 0xdc,
- DBG_BLOCK_ID_UNUSED48 = 0xdd,
- DBG_BLOCK_ID_UNUSED49 = 0xde,
- DBG_BLOCK_ID_UNUSED50 = 0xdf,
- DBG_BLOCK_ID_MCD0 = 0xe0,
- DBG_BLOCK_ID_MCD1 = 0xe1,
- DBG_BLOCK_ID_MCD2 = 0xe2,
- DBG_BLOCK_ID_MCD3 = 0xe3,
- DBG_BLOCK_ID_MCD4 = 0xe4,
- DBG_BLOCK_ID_MCD5 = 0xe5,
- DBG_BLOCK_ID_UNUSED51 = 0xe6,
- DBG_BLOCK_ID_UNUSED52 = 0xe7,
-} DebugBlockId_OLD;
-typedef enum DebugBlockId_BY2 {
- DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
- DBG_BLOCK_ID_VMC_BY2 = 0x1,
- DBG_BLOCK_ID_CG_BY2 = 0x2,
- DBG_BLOCK_ID_GRBM_BY2 = 0x3,
- DBG_BLOCK_ID_CSC_BY2 = 0x4,
- DBG_BLOCK_ID_IH_BY2 = 0x5,
- DBG_BLOCK_ID_SQ_BY2 = 0x6,
- DBG_BLOCK_ID_GMCON_BY2 = 0x7,
- DBG_BLOCK_ID_DMA0_BY2 = 0x8,
- DBG_BLOCK_ID_SPIM_BY2 = 0x9,
- DBG_BLOCK_ID_SPIS_BY2 = 0xa,
- DBG_BLOCK_ID_PA0_BY2 = 0xb,
- DBG_BLOCK_ID_CP0_BY2 = 0xc,
- DBG_BLOCK_ID_CP2_BY2 = 0xd,
- DBG_BLOCK_ID_UVDU_BY2 = 0xe,
- DBG_BLOCK_ID_VCE_BY2 = 0xf,
- DBG_BLOCK_ID_VGT0_BY2 = 0x10,
- DBG_BLOCK_ID_IA_BY2 = 0x11,
- DBG_BLOCK_ID_SCT0_BY2 = 0x12,
- DBG_BLOCK_ID_SPM0_BY2 = 0x13,
- DBG_BLOCK_ID_TCAA_BY2 = 0x14,
- DBG_BLOCK_ID_TCCA_BY2 = 0x15,
- DBG_BLOCK_ID_MCC0_BY2 = 0x16,
- DBG_BLOCK_ID_MCC2_BY2 = 0x17,
- DBG_BLOCK_ID_SX0_BY2 = 0x18,
- DBG_BLOCK_ID_SX2_BY2 = 0x19,
- DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a,
- DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b,
- DBG_BLOCK_ID_PC0_BY2 = 0x1c,
- DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d,
- DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e,
- DBG_BLOCK_ID_MCB_BY2 = 0x1f,
- DBG_BLOCK_ID_SCB0_BY2 = 0x20,
- DBG_BLOCK_ID_UNUSED13_BY2 = 0x21,
- DBG_BLOCK_ID_SCF0_BY2 = 0x22,
- DBG_BLOCK_ID_UNUSED15_BY2 = 0x23,
- DBG_BLOCK_ID_BCI0_BY2 = 0x24,
- DBG_BLOCK_ID_BCI2_BY2 = 0x25,
- DBG_BLOCK_ID_UNUSED17_BY2 = 0x26,
- DBG_BLOCK_ID_UNUSED19_BY2 = 0x27,
- DBG_BLOCK_ID_CB00_BY2 = 0x28,
- DBG_BLOCK_ID_CB02_BY2 = 0x29,
- DBG_BLOCK_ID_CB04_BY2 = 0x2a,
- DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b,
- DBG_BLOCK_ID_CB10_BY2 = 0x2c,
- DBG_BLOCK_ID_CB12_BY2 = 0x2d,
- DBG_BLOCK_ID_CB14_BY2 = 0x2e,
- DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f,
- DBG_BLOCK_ID_TCP0_BY2 = 0x30,
- DBG_BLOCK_ID_TCP2_BY2 = 0x31,
- DBG_BLOCK_ID_TCP4_BY2 = 0x32,
- DBG_BLOCK_ID_TCP6_BY2 = 0x33,
- DBG_BLOCK_ID_TCP8_BY2 = 0x34,
- DBG_BLOCK_ID_TCP10_BY2 = 0x35,
- DBG_BLOCK_ID_TCP12_BY2 = 0x36,
- DBG_BLOCK_ID_TCP14_BY2 = 0x37,
- DBG_BLOCK_ID_TCP16_BY2 = 0x38,
- DBG_BLOCK_ID_TCP18_BY2 = 0x39,
- DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
- DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
- DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
- DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
- DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
- DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
- DBG_BLOCK_ID_DB00_BY2 = 0x40,
- DBG_BLOCK_ID_DB02_BY2 = 0x41,
- DBG_BLOCK_ID_DB04_BY2 = 0x42,
- DBG_BLOCK_ID_UNUSED28_BY2 = 0x43,
- DBG_BLOCK_ID_DB10_BY2 = 0x44,
- DBG_BLOCK_ID_DB12_BY2 = 0x45,
- DBG_BLOCK_ID_DB14_BY2 = 0x46,
- DBG_BLOCK_ID_UNUSED31_BY2 = 0x47,
- DBG_BLOCK_ID_TCC0_BY2 = 0x48,
- DBG_BLOCK_ID_TCC2_BY2 = 0x49,
- DBG_BLOCK_ID_TCC4_BY2 = 0x4a,
- DBG_BLOCK_ID_TCC6_BY2 = 0x4b,
- DBG_BLOCK_ID_SPS00_BY2 = 0x4c,
- DBG_BLOCK_ID_SPS02_BY2 = 0x4d,
- DBG_BLOCK_ID_SPS11_BY2 = 0x4e,
- DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f,
- DBG_BLOCK_ID_TA00_BY2 = 0x50,
- DBG_BLOCK_ID_TA02_BY2 = 0x51,
- DBG_BLOCK_ID_TA04_BY2 = 0x52,
- DBG_BLOCK_ID_TA06_BY2 = 0x53,
- DBG_BLOCK_ID_TA08_BY2 = 0x54,
- DBG_BLOCK_ID_TA0A_BY2 = 0x55,
- DBG_BLOCK_ID_UNUSED35_BY2 = 0x56,
- DBG_BLOCK_ID_UNUSED37_BY2 = 0x57,
- DBG_BLOCK_ID_TA10_BY2 = 0x58,
- DBG_BLOCK_ID_TA12_BY2 = 0x59,
- DBG_BLOCK_ID_TA14_BY2 = 0x5a,
- DBG_BLOCK_ID_TA16_BY2 = 0x5b,
- DBG_BLOCK_ID_TA18_BY2 = 0x5c,
- DBG_BLOCK_ID_TA1A_BY2 = 0x5d,
- DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e,
- DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f,
- DBG_BLOCK_ID_TD00_BY2 = 0x60,
- DBG_BLOCK_ID_TD02_BY2 = 0x61,
- DBG_BLOCK_ID_TD04_BY2 = 0x62,
- DBG_BLOCK_ID_TD06_BY2 = 0x63,
- DBG_BLOCK_ID_TD08_BY2 = 0x64,
- DBG_BLOCK_ID_TD0A_BY2 = 0x65,
- DBG_BLOCK_ID_UNUSED43_BY2 = 0x66,
- DBG_BLOCK_ID_UNUSED45_BY2 = 0x67,
- DBG_BLOCK_ID_TD10_BY2 = 0x68,
- DBG_BLOCK_ID_TD12_BY2 = 0x69,
- DBG_BLOCK_ID_TD14_BY2 = 0x6a,
- DBG_BLOCK_ID_TD16_BY2 = 0x6b,
- DBG_BLOCK_ID_TD18_BY2 = 0x6c,
- DBG_BLOCK_ID_TD1A_BY2 = 0x6d,
- DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e,
- DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f,
- DBG_BLOCK_ID_MCD0_BY2 = 0x70,
- DBG_BLOCK_ID_MCD2_BY2 = 0x71,
- DBG_BLOCK_ID_MCD4_BY2 = 0x72,
- DBG_BLOCK_ID_UNUSED51_BY2 = 0x73,
-} DebugBlockId_BY2;
-typedef enum DebugBlockId_BY4 {
- DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
- DBG_BLOCK_ID_CG_BY4 = 0x1,
- DBG_BLOCK_ID_CSC_BY4 = 0x2,
- DBG_BLOCK_ID_SQ_BY4 = 0x3,
- DBG_BLOCK_ID_DMA0_BY4 = 0x4,
- DBG_BLOCK_ID_SPIS_BY4 = 0x5,
- DBG_BLOCK_ID_CP0_BY4 = 0x6,
- DBG_BLOCK_ID_UVDU_BY4 = 0x7,
- DBG_BLOCK_ID_VGT0_BY4 = 0x8,
- DBG_BLOCK_ID_SCT0_BY4 = 0x9,
- DBG_BLOCK_ID_TCAA_BY4 = 0xa,
- DBG_BLOCK_ID_MCC0_BY4 = 0xb,
- DBG_BLOCK_ID_SX0_BY4 = 0xc,
- DBG_BLOCK_ID_UNUSED4_BY4 = 0xd,
- DBG_BLOCK_ID_PC0_BY4 = 0xe,
- DBG_BLOCK_ID_UNUSED10_BY4 = 0xf,
- DBG_BLOCK_ID_SCB0_BY4 = 0x10,
- DBG_BLOCK_ID_SCF0_BY4 = 0x11,
- DBG_BLOCK_ID_BCI0_BY4 = 0x12,
- DBG_BLOCK_ID_UNUSED17_BY4 = 0x13,
- DBG_BLOCK_ID_CB00_BY4 = 0x14,
- DBG_BLOCK_ID_CB04_BY4 = 0x15,
- DBG_BLOCK_ID_CB10_BY4 = 0x16,
- DBG_BLOCK_ID_CB14_BY4 = 0x17,
- DBG_BLOCK_ID_TCP0_BY4 = 0x18,
- DBG_BLOCK_ID_TCP4_BY4 = 0x19,
- DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
- DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
- DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
- DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
- DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
- DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
- DBG_BLOCK_ID_DB_BY4 = 0x20,
- DBG_BLOCK_ID_DB04_BY4 = 0x21,
- DBG_BLOCK_ID_DB10_BY4 = 0x22,
- DBG_BLOCK_ID_DB14_BY4 = 0x23,
- DBG_BLOCK_ID_TCC0_BY4 = 0x24,
- DBG_BLOCK_ID_TCC4_BY4 = 0x25,
- DBG_BLOCK_ID_SPS00_BY4 = 0x26,
- DBG_BLOCK_ID_SPS11_BY4 = 0x27,
- DBG_BLOCK_ID_TA00_BY4 = 0x28,
- DBG_BLOCK_ID_TA04_BY4 = 0x29,
- DBG_BLOCK_ID_TA08_BY4 = 0x2a,
- DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b,
- DBG_BLOCK_ID_TA10_BY4 = 0x2c,
- DBG_BLOCK_ID_TA14_BY4 = 0x2d,
- DBG_BLOCK_ID_TA18_BY4 = 0x2e,
- DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f,
- DBG_BLOCK_ID_TD00_BY4 = 0x30,
- DBG_BLOCK_ID_TD04_BY4 = 0x31,
- DBG_BLOCK_ID_TD08_BY4 = 0x32,
- DBG_BLOCK_ID_UNUSED43_BY4 = 0x33,
- DBG_BLOCK_ID_TD10_BY4 = 0x34,
- DBG_BLOCK_ID_TD14_BY4 = 0x35,
- DBG_BLOCK_ID_TD18_BY4 = 0x36,
- DBG_BLOCK_ID_UNUSED47_BY4 = 0x37,
- DBG_BLOCK_ID_MCD0_BY4 = 0x38,
- DBG_BLOCK_ID_MCD4_BY4 = 0x39,
-} DebugBlockId_BY4;
-typedef enum DebugBlockId_BY8 {
- DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
- DBG_BLOCK_ID_CSC_BY8 = 0x1,
- DBG_BLOCK_ID_DMA0_BY8 = 0x2,
- DBG_BLOCK_ID_CP0_BY8 = 0x3,
- DBG_BLOCK_ID_VGT0_BY8 = 0x4,
- DBG_BLOCK_ID_TCAA_BY8 = 0x5,
- DBG_BLOCK_ID_SX0_BY8 = 0x6,
- DBG_BLOCK_ID_PC0_BY8 = 0x7,
- DBG_BLOCK_ID_SCB0_BY8 = 0x8,
- DBG_BLOCK_ID_BCI0_BY8 = 0x9,
- DBG_BLOCK_ID_CB00_BY8 = 0xa,
- DBG_BLOCK_ID_CB10_BY8 = 0xb,
- DBG_BLOCK_ID_TCP0_BY8 = 0xc,
- DBG_BLOCK_ID_TCP8_BY8 = 0xd,
- DBG_BLOCK_ID_TCP16_BY8 = 0xe,
- DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
- DBG_BLOCK_ID_DB00_BY8 = 0x10,
- DBG_BLOCK_ID_DB10_BY8 = 0x11,
- DBG_BLOCK_ID_TCC0_BY8 = 0x12,
- DBG_BLOCK_ID_SPS00_BY8 = 0x13,
- DBG_BLOCK_ID_TA00_BY8 = 0x14,
- DBG_BLOCK_ID_TA08_BY8 = 0x15,
- DBG_BLOCK_ID_TA10_BY8 = 0x16,
- DBG_BLOCK_ID_TA18_BY8 = 0x17,
- DBG_BLOCK_ID_TD00_BY8 = 0x18,
- DBG_BLOCK_ID_TD08_BY8 = 0x19,
- DBG_BLOCK_ID_TD10_BY8 = 0x1a,
- DBG_BLOCK_ID_TD18_BY8 = 0x1b,
- DBG_BLOCK_ID_MCD0_BY8 = 0x1c,
-} DebugBlockId_BY8;
-typedef enum DebugBlockId_BY16 {
- DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
- DBG_BLOCK_ID_DMA0_BY16 = 0x1,
- DBG_BLOCK_ID_VGT0_BY16 = 0x2,
- DBG_BLOCK_ID_SX0_BY16 = 0x3,
- DBG_BLOCK_ID_SCB0_BY16 = 0x4,
- DBG_BLOCK_ID_CB00_BY16 = 0x5,
- DBG_BLOCK_ID_TCP0_BY16 = 0x6,
- DBG_BLOCK_ID_TCP16_BY16 = 0x7,
- DBG_BLOCK_ID_DB00_BY16 = 0x8,
- DBG_BLOCK_ID_TCC0_BY16 = 0x9,
- DBG_BLOCK_ID_TA00_BY16 = 0xa,
- DBG_BLOCK_ID_TA10_BY16 = 0xb,
- DBG_BLOCK_ID_TD00_BY16 = 0xc,
- DBG_BLOCK_ID_TD10_BY16 = 0xd,
- DBG_BLOCK_ID_MCD0_BY16 = 0xe,
-} DebugBlockId_BY16;
-typedef enum ColorTransform {
- DCC_CT_AUTO = 0x0,
- DCC_CT_NONE = 0x1,
- ABGR_TO_A_BG_G_RB = 0x2,
- BGRA_TO_BG_G_RB_A = 0x3,
-} ColorTransform;
-typedef enum CompareRef {
- REF_NEVER = 0x0,
- REF_LESS = 0x1,
- REF_EQUAL = 0x2,
- REF_LEQUAL = 0x3,
- REF_GREATER = 0x4,
- REF_NOTEQUAL = 0x5,
- REF_GEQUAL = 0x6,
- REF_ALWAYS = 0x7,
-} CompareRef;
-typedef enum ReadSize {
- READ_256_BITS = 0x0,
- READ_512_BITS = 0x1,
-} ReadSize;
-typedef enum DepthFormat {
- DEPTH_INVALID = 0x0,
- DEPTH_16 = 0x1,
- DEPTH_X8_24 = 0x2,
- DEPTH_8_24 = 0x3,
- DEPTH_X8_24_FLOAT = 0x4,
- DEPTH_8_24_FLOAT = 0x5,
- DEPTH_32_FLOAT = 0x6,
- DEPTH_X24_8_32_FLOAT = 0x7,
-} DepthFormat;
-typedef enum ZFormat {
- Z_INVALID = 0x0,
- Z_16 = 0x1,
- Z_24 = 0x2,
- Z_32_FLOAT = 0x3,
-} ZFormat;
-typedef enum StencilFormat {
- STENCIL_INVALID = 0x0,
- STENCIL_8 = 0x1,
-} StencilFormat;
-typedef enum CmaskMode {
- CMASK_CLEAR_NONE = 0x0,
- CMASK_CLEAR_ONE = 0x1,
- CMASK_CLEAR_ALL = 0x2,
- CMASK_ANY_EXPANDED = 0x3,
- CMASK_ALPHA0_FRAG1 = 0x4,
- CMASK_ALPHA0_FRAG2 = 0x5,
- CMASK_ALPHA0_FRAG4 = 0x6,
- CMASK_ALPHA0_FRAGS = 0x7,
- CMASK_ALPHA1_FRAG1 = 0x8,
- CMASK_ALPHA1_FRAG2 = 0x9,
- CMASK_ALPHA1_FRAG4 = 0xa,
- CMASK_ALPHA1_FRAGS = 0xb,
- CMASK_ALPHAX_FRAG1 = 0xc,
- CMASK_ALPHAX_FRAG2 = 0xd,
- CMASK_ALPHAX_FRAG4 = 0xe,
- CMASK_ALPHAX_FRAGS = 0xf,
-} CmaskMode;
-typedef enum QuadExportFormat {
- EXPORT_UNUSED = 0x0,
- EXPORT_32_R = 0x1,
- EXPORT_32_GR = 0x2,
- EXPORT_32_AR = 0x3,
- EXPORT_FP16_ABGR = 0x4,
- EXPORT_UNSIGNED16_ABGR = 0x5,
- EXPORT_SIGNED16_ABGR = 0x6,
- EXPORT_32_ABGR = 0x7,
-} QuadExportFormat;
-typedef enum QuadExportFormatOld {
- EXPORT_4P_32BPC_ABGR = 0x0,
- EXPORT_4P_16BPC_ABGR = 0x1,
- EXPORT_4P_32BPC_GR = 0x2,
- EXPORT_4P_32BPC_AR = 0x3,
- EXPORT_2P_32BPC_ABGR = 0x4,
- EXPORT_8P_32BPC_R = 0x5,
-} QuadExportFormatOld;
-typedef enum ColorFormat {
- COLOR_INVALID = 0x0,
- COLOR_8 = 0x1,
- COLOR_16 = 0x2,
- COLOR_8_8 = 0x3,
- COLOR_32 = 0x4,
- COLOR_16_16 = 0x5,
- COLOR_10_11_11 = 0x6,
- COLOR_11_11_10 = 0x7,
- COLOR_10_10_10_2 = 0x8,
- COLOR_2_10_10_10 = 0x9,
- COLOR_8_8_8_8 = 0xa,
- COLOR_32_32 = 0xb,
- COLOR_16_16_16_16 = 0xc,
- COLOR_RESERVED_13 = 0xd,
- COLOR_32_32_32_32 = 0xe,
- COLOR_RESERVED_15 = 0xf,
- COLOR_5_6_5 = 0x10,
- COLOR_1_5_5_5 = 0x11,
- COLOR_5_5_5_1 = 0x12,
- COLOR_4_4_4_4 = 0x13,
- COLOR_8_24 = 0x14,
- COLOR_24_8 = 0x15,
- COLOR_X24_8_32_FLOAT = 0x16,
- COLOR_RESERVED_23 = 0x17,
-} ColorFormat;
-typedef enum SurfaceFormat {
- FMT_INVALID = 0x0,
- FMT_8 = 0x1,
- FMT_16 = 0x2,
- FMT_8_8 = 0x3,
- FMT_32 = 0x4,
- FMT_16_16 = 0x5,
- FMT_10_11_11 = 0x6,
- FMT_11_11_10 = 0x7,
- FMT_10_10_10_2 = 0x8,
- FMT_2_10_10_10 = 0x9,
- FMT_8_8_8_8 = 0xa,
- FMT_32_32 = 0xb,
- FMT_16_16_16_16 = 0xc,
- FMT_32_32_32 = 0xd,
- FMT_32_32_32_32 = 0xe,
- FMT_RESERVED_4 = 0xf,
- FMT_5_6_5 = 0x10,
- FMT_1_5_5_5 = 0x11,
- FMT_5_5_5_1 = 0x12,
- FMT_4_4_4_4 = 0x13,
- FMT_8_24 = 0x14,
- FMT_24_8 = 0x15,
- FMT_X24_8_32_FLOAT = 0x16,
- FMT_RESERVED_33 = 0x17,
- FMT_11_11_10_FLOAT = 0x18,
- FMT_16_FLOAT = 0x19,
- FMT_32_FLOAT = 0x1a,
- FMT_16_16_FLOAT = 0x1b,
- FMT_8_24_FLOAT = 0x1c,
- FMT_24_8_FLOAT = 0x1d,
- FMT_32_32_FLOAT = 0x1e,
- FMT_10_11_11_FLOAT = 0x1f,
- FMT_16_16_16_16_FLOAT = 0x20,
- FMT_3_3_2 = 0x21,
- FMT_6_5_5 = 0x22,
- FMT_32_32_32_32_FLOAT = 0x23,
- FMT_RESERVED_36 = 0x24,
- FMT_1 = 0x25,
- FMT_1_REVERSED = 0x26,
- FMT_GB_GR = 0x27,
- FMT_BG_RG = 0x28,
- FMT_32_AS_8 = 0x29,
- FMT_32_AS_8_8 = 0x2a,
- FMT_5_9_9_9_SHAREDEXP = 0x2b,
- FMT_8_8_8 = 0x2c,
- FMT_16_16_16 = 0x2d,
- FMT_16_16_16_FLOAT = 0x2e,
- FMT_4_4 = 0x2f,
- FMT_32_32_32_FLOAT = 0x30,
- FMT_BC1 = 0x31,
- FMT_BC2 = 0x32,
- FMT_BC3 = 0x33,
- FMT_BC4 = 0x34,
- FMT_BC5 = 0x35,
- FMT_BC6 = 0x36,
- FMT_BC7 = 0x37,
- FMT_32_AS_32_32_32_32 = 0x38,
- FMT_APC3 = 0x39,
- FMT_APC4 = 0x3a,
- FMT_APC5 = 0x3b,
- FMT_APC6 = 0x3c,
- FMT_APC7 = 0x3d,
- FMT_CTX1 = 0x3e,
- FMT_RESERVED_63 = 0x3f,
-} SurfaceFormat;
-typedef enum BUF_DATA_FORMAT {
- BUF_DATA_FORMAT_INVALID = 0x0,
- BUF_DATA_FORMAT_8 = 0x1,
- BUF_DATA_FORMAT_16 = 0x2,
- BUF_DATA_FORMAT_8_8 = 0x3,
- BUF_DATA_FORMAT_32 = 0x4,
- BUF_DATA_FORMAT_16_16 = 0x5,
- BUF_DATA_FORMAT_10_11_11 = 0x6,
- BUF_DATA_FORMAT_11_11_10 = 0x7,
- BUF_DATA_FORMAT_10_10_10_2 = 0x8,
- BUF_DATA_FORMAT_2_10_10_10 = 0x9,
- BUF_DATA_FORMAT_8_8_8_8 = 0xa,
- BUF_DATA_FORMAT_32_32 = 0xb,
- BUF_DATA_FORMAT_16_16_16_16 = 0xc,
- BUF_DATA_FORMAT_32_32_32 = 0xd,
- BUF_DATA_FORMAT_32_32_32_32 = 0xe,
- BUF_DATA_FORMAT_RESERVED_15 = 0xf,
-} BUF_DATA_FORMAT;
-typedef enum IMG_DATA_FORMAT {
- IMG_DATA_FORMAT_INVALID = 0x0,
- IMG_DATA_FORMAT_8 = 0x1,
- IMG_DATA_FORMAT_16 = 0x2,
- IMG_DATA_FORMAT_8_8 = 0x3,
- IMG_DATA_FORMAT_32 = 0x4,
- IMG_DATA_FORMAT_16_16 = 0x5,
- IMG_DATA_FORMAT_10_11_11 = 0x6,
- IMG_DATA_FORMAT_11_11_10 = 0x7,
- IMG_DATA_FORMAT_10_10_10_2 = 0x8,
- IMG_DATA_FORMAT_2_10_10_10 = 0x9,
- IMG_DATA_FORMAT_8_8_8_8 = 0xa,
- IMG_DATA_FORMAT_32_32 = 0xb,
- IMG_DATA_FORMAT_16_16_16_16 = 0xc,
- IMG_DATA_FORMAT_32_32_32 = 0xd,
- IMG_DATA_FORMAT_32_32_32_32 = 0xe,
- IMG_DATA_FORMAT_RESERVED_15 = 0xf,
- IMG_DATA_FORMAT_5_6_5 = 0x10,
- IMG_DATA_FORMAT_1_5_5_5 = 0x11,
- IMG_DATA_FORMAT_5_5_5_1 = 0x12,
- IMG_DATA_FORMAT_4_4_4_4 = 0x13,
- IMG_DATA_FORMAT_8_24 = 0x14,
- IMG_DATA_FORMAT_24_8 = 0x15,
- IMG_DATA_FORMAT_X24_8_32 = 0x16,
- IMG_DATA_FORMAT_RESERVED_23 = 0x17,
- IMG_DATA_FORMAT_RESERVED_24 = 0x18,
- IMG_DATA_FORMAT_RESERVED_25 = 0x19,
- IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
- IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
- IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
- IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
- IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
- IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
- IMG_DATA_FORMAT_GB_GR = 0x20,
- IMG_DATA_FORMAT_BG_RG = 0x21,
- IMG_DATA_FORMAT_5_9_9_9 = 0x22,
- IMG_DATA_FORMAT_BC1 = 0x23,
- IMG_DATA_FORMAT_BC2 = 0x24,
- IMG_DATA_FORMAT_BC3 = 0x25,
- IMG_DATA_FORMAT_BC4 = 0x26,
- IMG_DATA_FORMAT_BC5 = 0x27,
- IMG_DATA_FORMAT_BC6 = 0x28,
- IMG_DATA_FORMAT_BC7 = 0x29,
- IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
- IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
- IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
- IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
- IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
- IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
- IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
- IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
- IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
- IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
- IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
- IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
- IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
- IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
- IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
- IMG_DATA_FORMAT_4_4 = 0x39,
- IMG_DATA_FORMAT_6_5_5 = 0x3a,
- IMG_DATA_FORMAT_1 = 0x3b,
- IMG_DATA_FORMAT_1_REVERSED = 0x3c,
- IMG_DATA_FORMAT_32_AS_8 = 0x3d,
- IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
- IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
-} IMG_DATA_FORMAT;
-typedef enum BUF_NUM_FORMAT {
- BUF_NUM_FORMAT_UNORM = 0x0,
- BUF_NUM_FORMAT_SNORM = 0x1,
- BUF_NUM_FORMAT_USCALED = 0x2,
- BUF_NUM_FORMAT_SSCALED = 0x3,
- BUF_NUM_FORMAT_UINT = 0x4,
- BUF_NUM_FORMAT_SINT = 0x5,
- BUF_NUM_FORMAT_RESERVED_6 = 0x6,
- BUF_NUM_FORMAT_FLOAT = 0x7,
-} BUF_NUM_FORMAT;
-typedef enum IMG_NUM_FORMAT {
- IMG_NUM_FORMAT_UNORM = 0x0,
- IMG_NUM_FORMAT_SNORM = 0x1,
- IMG_NUM_FORMAT_USCALED = 0x2,
- IMG_NUM_FORMAT_SSCALED = 0x3,
- IMG_NUM_FORMAT_UINT = 0x4,
- IMG_NUM_FORMAT_SINT = 0x5,
- IMG_NUM_FORMAT_RESERVED_6 = 0x6,
- IMG_NUM_FORMAT_FLOAT = 0x7,
- IMG_NUM_FORMAT_RESERVED_8 = 0x8,
- IMG_NUM_FORMAT_SRGB = 0x9,
- IMG_NUM_FORMAT_RESERVED_10 = 0xa,
- IMG_NUM_FORMAT_RESERVED_11 = 0xb,
- IMG_NUM_FORMAT_RESERVED_12 = 0xc,
- IMG_NUM_FORMAT_RESERVED_13 = 0xd,
- IMG_NUM_FORMAT_RESERVED_14 = 0xe,
- IMG_NUM_FORMAT_RESERVED_15 = 0xf,
-} IMG_NUM_FORMAT;
-typedef enum TileType {
- ARRAY_COLOR_TILE = 0x0,
- ARRAY_DEPTH_TILE = 0x1,
-} TileType;
-typedef enum NonDispTilingOrder {
- ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
- ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
-} NonDispTilingOrder;
-typedef enum MicroTileMode {
- ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
- ADDR_SURF_THIN_MICRO_TILING = 0x1,
- ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
- ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
- ADDR_SURF_THICK_MICRO_TILING = 0x4,
-} MicroTileMode;
-typedef enum TileSplit {
- ADDR_SURF_TILE_SPLIT_64B = 0x0,
- ADDR_SURF_TILE_SPLIT_128B = 0x1,
- ADDR_SURF_TILE_SPLIT_256B = 0x2,
- ADDR_SURF_TILE_SPLIT_512B = 0x3,
- ADDR_SURF_TILE_SPLIT_1KB = 0x4,
- ADDR_SURF_TILE_SPLIT_2KB = 0x5,
- ADDR_SURF_TILE_SPLIT_4KB = 0x6,
-} TileSplit;
-typedef enum SampleSplit {
- ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
- ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
- ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
- ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
-} SampleSplit;
-typedef enum PipeConfig {
- ADDR_SURF_P2 = 0x0,
- ADDR_SURF_P2_RESERVED0 = 0x1,
- ADDR_SURF_P2_RESERVED1 = 0x2,
- ADDR_SURF_P2_RESERVED2 = 0x3,
- ADDR_SURF_P4_8x16 = 0x4,
- ADDR_SURF_P4_16x16 = 0x5,
- ADDR_SURF_P4_16x32 = 0x6,
- ADDR_SURF_P4_32x32 = 0x7,
- ADDR_SURF_P8_16x16_8x16 = 0x8,
- ADDR_SURF_P8_16x32_8x16 = 0x9,
- ADDR_SURF_P8_32x32_8x16 = 0xa,
- ADDR_SURF_P8_16x32_16x16 = 0xb,
- ADDR_SURF_P8_32x32_16x16 = 0xc,
- ADDR_SURF_P8_32x32_16x32 = 0xd,
- ADDR_SURF_P8_32x64_32x32 = 0xe,
- ADDR_SURF_P8_RESERVED0 = 0xf,
- ADDR_SURF_P16_32x32_8x16 = 0x10,
- ADDR_SURF_P16_32x32_16x16 = 0x11,
-} PipeConfig;
-typedef enum NumBanks {
- ADDR_SURF_2_BANK = 0x0,
- ADDR_SURF_4_BANK = 0x1,
- ADDR_SURF_8_BANK = 0x2,
- ADDR_SURF_16_BANK = 0x3,
-} NumBanks;
-typedef enum BankWidth {
- ADDR_SURF_BANK_WIDTH_1 = 0x0,
- ADDR_SURF_BANK_WIDTH_2 = 0x1,
- ADDR_SURF_BANK_WIDTH_4 = 0x2,
- ADDR_SURF_BANK_WIDTH_8 = 0x3,
-} BankWidth;
-typedef enum BankHeight {
- ADDR_SURF_BANK_HEIGHT_1 = 0x0,
- ADDR_SURF_BANK_HEIGHT_2 = 0x1,
- ADDR_SURF_BANK_HEIGHT_4 = 0x2,
- ADDR_SURF_BANK_HEIGHT_8 = 0x3,
-} BankHeight;
-typedef enum BankWidthHeight {
- ADDR_SURF_BANK_WH_1 = 0x0,
- ADDR_SURF_BANK_WH_2 = 0x1,
- ADDR_SURF_BANK_WH_4 = 0x2,
- ADDR_SURF_BANK_WH_8 = 0x3,
-} BankWidthHeight;
-typedef enum MacroTileAspect {
- ADDR_SURF_MACRO_ASPECT_1 = 0x0,
- ADDR_SURF_MACRO_ASPECT_2 = 0x1,
- ADDR_SURF_MACRO_ASPECT_4 = 0x2,
- ADDR_SURF_MACRO_ASPECT_8 = 0x3,
-} MacroTileAspect;
-typedef enum GATCL1RequestType {
- GATCL1_TYPE_NORMAL = 0x0,
- GATCL1_TYPE_SHOOTDOWN = 0x1,
- GATCL1_TYPE_BYPASS = 0x2,
-} GATCL1RequestType;
-typedef enum TCC_CACHE_POLICIES {
- TCC_CACHE_POLICY_LRU = 0x0,
- TCC_CACHE_POLICY_STREAM = 0x1,
-} TCC_CACHE_POLICIES;
-typedef enum MTYPE {
- MTYPE_NC_NV = 0x0,
- MTYPE_NC = 0x1,
- MTYPE_CC = 0x2,
- MTYPE_UC = 0x3,
-} MTYPE;
-typedef enum PERFMON_COUNTER_MODE {
- PERFMON_COUNTER_MODE_ACCUM = 0x0,
- PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
- PERFMON_COUNTER_MODE_MAX = 0x2,
- PERFMON_COUNTER_MODE_DIRTY = 0x3,
- PERFMON_COUNTER_MODE_SAMPLE = 0x4,
- PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
- PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
- PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
- PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
- PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
- PERFMON_COUNTER_MODE_RESERVED = 0xf,
-} PERFMON_COUNTER_MODE;
-typedef enum PERFMON_SPM_MODE {
- PERFMON_SPM_MODE_OFF = 0x0,
- PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
- PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
- PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
- PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
- PERFMON_SPM_MODE_RESERVED_5 = 0x5,
- PERFMON_SPM_MODE_RESERVED_6 = 0x6,
- PERFMON_SPM_MODE_RESERVED_7 = 0x7,
- PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
- PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
- PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
-} PERFMON_SPM_MODE;
-typedef enum SurfaceTiling {
- ARRAY_LINEAR = 0x0,
- ARRAY_TILED = 0x1,
-} SurfaceTiling;
-typedef enum SurfaceArray {
- ARRAY_1D = 0x0,
- ARRAY_2D = 0x1,
- ARRAY_3D = 0x2,
- ARRAY_3D_SLICE = 0x3,
-} SurfaceArray;
-typedef enum ColorArray {
- ARRAY_2D_ALT_COLOR = 0x0,
- ARRAY_2D_COLOR = 0x1,
- ARRAY_3D_SLICE_COLOR = 0x3,
-} ColorArray;
-typedef enum DepthArray {
- ARRAY_2D_ALT_DEPTH = 0x0,
- ARRAY_2D_DEPTH = 0x1,
-} DepthArray;
-typedef enum ENUM_NUM_SIMD_PER_CU {
- NUM_SIMD_PER_CU = 0x4,
-} ENUM_NUM_SIMD_PER_CU;
-typedef enum MEM_PWR_FORCE_CTRL {
- NO_FORCE_REQUEST = 0x0,
- FORCE_LIGHT_SLEEP_REQUEST = 0x1,
- FORCE_DEEP_SLEEP_REQUEST = 0x2,
- FORCE_SHUT_DOWN_REQUEST = 0x3,
-} MEM_PWR_FORCE_CTRL;
-typedef enum MEM_PWR_FORCE_CTRL2 {
- NO_FORCE_REQ = 0x0,
- FORCE_LIGHT_SLEEP_REQ = 0x1,
-} MEM_PWR_FORCE_CTRL2;
-typedef enum MEM_PWR_DIS_CTRL {
- ENABLE_MEM_PWR_CTRL = 0x0,
- DISABLE_MEM_PWR_CTRL = 0x1,
-} MEM_PWR_DIS_CTRL;
-typedef enum MEM_PWR_SEL_CTRL {
- DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
- DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
- DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
-} MEM_PWR_SEL_CTRL;
-typedef enum MEM_PWR_SEL_CTRL2 {
- DYNAMIC_DEEP_SLEEP_EN = 0x0,
- DYNAMIC_LIGHT_SLEEP_EN = 0x1,
-} MEM_PWR_SEL_CTRL2;
-
-#endif /* GMC_8_1_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_enum.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_enum.h
deleted file mode 100644
index bc18e4d1f..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_enum.h
+++ /dev/null
@@ -1,1068 +0,0 @@
-/*
- * GMC_8_2 Register documentation
- *
- * Copyright (C) 2014 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef GMC_8_2_ENUM_H
-#define GMC_8_2_ENUM_H
-
-typedef enum DebugBlockId {
- DBG_BLOCK_ID_RESERVED = 0x0,
- DBG_BLOCK_ID_DBG = 0x1,
- DBG_BLOCK_ID_VMC = 0x2,
- DBG_BLOCK_ID_PDMA = 0x3,
- DBG_BLOCK_ID_CG = 0x4,
- DBG_BLOCK_ID_SRBM = 0x5,
- DBG_BLOCK_ID_GRBM = 0x6,
- DBG_BLOCK_ID_RLC = 0x7,
- DBG_BLOCK_ID_CSC = 0x8,
- DBG_BLOCK_ID_SEM = 0x9,
- DBG_BLOCK_ID_IH = 0xa,
- DBG_BLOCK_ID_SC = 0xb,
- DBG_BLOCK_ID_SQ = 0xc,
- DBG_BLOCK_ID_UVDU = 0xd,
- DBG_BLOCK_ID_SQA = 0xe,
- DBG_BLOCK_ID_SDMA0 = 0xf,
- DBG_BLOCK_ID_SDMA1 = 0x10,
- DBG_BLOCK_ID_SPIM = 0x11,
- DBG_BLOCK_ID_GDS = 0x12,
- DBG_BLOCK_ID_VC0 = 0x13,
- DBG_BLOCK_ID_VC1 = 0x14,
- DBG_BLOCK_ID_PA0 = 0x15,
- DBG_BLOCK_ID_PA1 = 0x16,
- DBG_BLOCK_ID_CP0 = 0x17,
- DBG_BLOCK_ID_CP1 = 0x18,
- DBG_BLOCK_ID_CP2 = 0x19,
- DBG_BLOCK_ID_XBR = 0x1a,
- DBG_BLOCK_ID_UVDM = 0x1b,
- DBG_BLOCK_ID_VGT0 = 0x1c,
- DBG_BLOCK_ID_VGT1 = 0x1d,
- DBG_BLOCK_ID_IA = 0x1e,
- DBG_BLOCK_ID_SXM0 = 0x1f,
- DBG_BLOCK_ID_SXM1 = 0x20,
- DBG_BLOCK_ID_SCT0 = 0x21,
- DBG_BLOCK_ID_SCT1 = 0x22,
- DBG_BLOCK_ID_SPM0 = 0x23,
- DBG_BLOCK_ID_SPM1 = 0x24,
- DBG_BLOCK_ID_UNUSED0 = 0x25,
- DBG_BLOCK_ID_UNUSED1 = 0x26,
- DBG_BLOCK_ID_TCAA = 0x27,
- DBG_BLOCK_ID_TCAB = 0x28,
- DBG_BLOCK_ID_TCCA = 0x29,
- DBG_BLOCK_ID_TCCB = 0x2a,
- DBG_BLOCK_ID_MCC0 = 0x2b,
- DBG_BLOCK_ID_MCC1 = 0x2c,
- DBG_BLOCK_ID_MCC2 = 0x2d,
- DBG_BLOCK_ID_MCC3 = 0x2e,
- DBG_BLOCK_ID_SXS0 = 0x2f,
- DBG_BLOCK_ID_SXS1 = 0x30,
- DBG_BLOCK_ID_SXS2 = 0x31,
- DBG_BLOCK_ID_SXS3 = 0x32,
- DBG_BLOCK_ID_SXS4 = 0x33,
- DBG_BLOCK_ID_SXS5 = 0x34,
- DBG_BLOCK_ID_SXS6 = 0x35,
- DBG_BLOCK_ID_SXS7 = 0x36,
- DBG_BLOCK_ID_SXS8 = 0x37,
- DBG_BLOCK_ID_SXS9 = 0x38,
- DBG_BLOCK_ID_BCI0 = 0x39,
- DBG_BLOCK_ID_BCI1 = 0x3a,
- DBG_BLOCK_ID_BCI2 = 0x3b,
- DBG_BLOCK_ID_BCI3 = 0x3c,
- DBG_BLOCK_ID_MCB = 0x3d,
- DBG_BLOCK_ID_UNUSED6 = 0x3e,
- DBG_BLOCK_ID_SQA00 = 0x3f,
- DBG_BLOCK_ID_SQA01 = 0x40,
- DBG_BLOCK_ID_SQA02 = 0x41,
- DBG_BLOCK_ID_SQA10 = 0x42,
- DBG_BLOCK_ID_SQA11 = 0x43,
- DBG_BLOCK_ID_SQA12 = 0x44,
- DBG_BLOCK_ID_UNUSED7 = 0x45,
- DBG_BLOCK_ID_UNUSED8 = 0x46,
- DBG_BLOCK_ID_SQB00 = 0x47,
- DBG_BLOCK_ID_SQB01 = 0x48,
- DBG_BLOCK_ID_SQB10 = 0x49,
- DBG_BLOCK_ID_SQB11 = 0x4a,
- DBG_BLOCK_ID_SQ00 = 0x4b,
- DBG_BLOCK_ID_SQ01 = 0x4c,
- DBG_BLOCK_ID_SQ10 = 0x4d,
- DBG_BLOCK_ID_SQ11 = 0x4e,
- DBG_BLOCK_ID_CB00 = 0x4f,
- DBG_BLOCK_ID_CB01 = 0x50,
- DBG_BLOCK_ID_CB02 = 0x51,
- DBG_BLOCK_ID_CB03 = 0x52,
- DBG_BLOCK_ID_CB04 = 0x53,
- DBG_BLOCK_ID_UNUSED9 = 0x54,
- DBG_BLOCK_ID_UNUSED10 = 0x55,
- DBG_BLOCK_ID_UNUSED11 = 0x56,
- DBG_BLOCK_ID_CB10 = 0x57,
- DBG_BLOCK_ID_CB11 = 0x58,
- DBG_BLOCK_ID_CB12 = 0x59,
- DBG_BLOCK_ID_CB13 = 0x5a,
- DBG_BLOCK_ID_CB14 = 0x5b,
- DBG_BLOCK_ID_UNUSED12 = 0x5c,
- DBG_BLOCK_ID_UNUSED13 = 0x5d,
- DBG_BLOCK_ID_UNUSED14 = 0x5e,
- DBG_BLOCK_ID_TCP0 = 0x5f,
- DBG_BLOCK_ID_TCP1 = 0x60,
- DBG_BLOCK_ID_TCP2 = 0x61,
- DBG_BLOCK_ID_TCP3 = 0x62,
- DBG_BLOCK_ID_TCP4 = 0x63,
- DBG_BLOCK_ID_TCP5 = 0x64,
- DBG_BLOCK_ID_TCP6 = 0x65,
- DBG_BLOCK_ID_TCP7 = 0x66,
- DBG_BLOCK_ID_TCP8 = 0x67,
- DBG_BLOCK_ID_TCP9 = 0x68,
- DBG_BLOCK_ID_TCP10 = 0x69,
- DBG_BLOCK_ID_TCP11 = 0x6a,
- DBG_BLOCK_ID_TCP12 = 0x6b,
- DBG_BLOCK_ID_TCP13 = 0x6c,
- DBG_BLOCK_ID_TCP14 = 0x6d,
- DBG_BLOCK_ID_TCP15 = 0x6e,
- DBG_BLOCK_ID_TCP16 = 0x6f,
- DBG_BLOCK_ID_TCP17 = 0x70,
- DBG_BLOCK_ID_TCP18 = 0x71,
- DBG_BLOCK_ID_TCP19 = 0x72,
- DBG_BLOCK_ID_TCP20 = 0x73,
- DBG_BLOCK_ID_TCP21 = 0x74,
- DBG_BLOCK_ID_TCP22 = 0x75,
- DBG_BLOCK_ID_TCP23 = 0x76,
- DBG_BLOCK_ID_TCP_RESERVED0 = 0x77,
- DBG_BLOCK_ID_TCP_RESERVED1 = 0x78,
- DBG_BLOCK_ID_TCP_RESERVED2 = 0x79,
- DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a,
- DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b,
- DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c,
- DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d,
- DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e,
- DBG_BLOCK_ID_DB00 = 0x7f,
- DBG_BLOCK_ID_DB01 = 0x80,
- DBG_BLOCK_ID_DB02 = 0x81,
- DBG_BLOCK_ID_DB03 = 0x82,
- DBG_BLOCK_ID_DB04 = 0x83,
- DBG_BLOCK_ID_UNUSED15 = 0x84,
- DBG_BLOCK_ID_UNUSED16 = 0x85,
- DBG_BLOCK_ID_UNUSED17 = 0x86,
- DBG_BLOCK_ID_DB10 = 0x87,
- DBG_BLOCK_ID_DB11 = 0x88,
- DBG_BLOCK_ID_DB12 = 0x89,
- DBG_BLOCK_ID_DB13 = 0x8a,
- DBG_BLOCK_ID_DB14 = 0x8b,
- DBG_BLOCK_ID_UNUSED18 = 0x8c,
- DBG_BLOCK_ID_UNUSED19 = 0x8d,
- DBG_BLOCK_ID_UNUSED20 = 0x8e,
- DBG_BLOCK_ID_TCC0 = 0x8f,
- DBG_BLOCK_ID_TCC1 = 0x90,
- DBG_BLOCK_ID_TCC2 = 0x91,
- DBG_BLOCK_ID_TCC3 = 0x92,
- DBG_BLOCK_ID_TCC4 = 0x93,
- DBG_BLOCK_ID_TCC5 = 0x94,
- DBG_BLOCK_ID_TCC6 = 0x95,
- DBG_BLOCK_ID_TCC7 = 0x96,
- DBG_BLOCK_ID_SPS00 = 0x97,
- DBG_BLOCK_ID_SPS01 = 0x98,
- DBG_BLOCK_ID_SPS02 = 0x99,
- DBG_BLOCK_ID_SPS10 = 0x9a,
- DBG_BLOCK_ID_SPS11 = 0x9b,
- DBG_BLOCK_ID_SPS12 = 0x9c,
- DBG_BLOCK_ID_UNUSED21 = 0x9d,
- DBG_BLOCK_ID_UNUSED22 = 0x9e,
- DBG_BLOCK_ID_TA00 = 0x9f,
- DBG_BLOCK_ID_TA01 = 0xa0,
- DBG_BLOCK_ID_TA02 = 0xa1,
- DBG_BLOCK_ID_TA03 = 0xa2,
- DBG_BLOCK_ID_TA04 = 0xa3,
- DBG_BLOCK_ID_TA05 = 0xa4,
- DBG_BLOCK_ID_TA06 = 0xa5,
- DBG_BLOCK_ID_TA07 = 0xa6,
- DBG_BLOCK_ID_TA08 = 0xa7,
- DBG_BLOCK_ID_TA09 = 0xa8,
- DBG_BLOCK_ID_TA0A = 0xa9,
- DBG_BLOCK_ID_TA0B = 0xaa,
- DBG_BLOCK_ID_UNUSED23 = 0xab,
- DBG_BLOCK_ID_UNUSED24 = 0xac,
- DBG_BLOCK_ID_UNUSED25 = 0xad,
- DBG_BLOCK_ID_UNUSED26 = 0xae,
- DBG_BLOCK_ID_TA10 = 0xaf,
- DBG_BLOCK_ID_TA11 = 0xb0,
- DBG_BLOCK_ID_TA12 = 0xb1,
- DBG_BLOCK_ID_TA13 = 0xb2,
- DBG_BLOCK_ID_TA14 = 0xb3,
- DBG_BLOCK_ID_TA15 = 0xb4,
- DBG_BLOCK_ID_TA16 = 0xb5,
- DBG_BLOCK_ID_TA17 = 0xb6,
- DBG_BLOCK_ID_TA18 = 0xb7,
- DBG_BLOCK_ID_TA19 = 0xb8,
- DBG_BLOCK_ID_TA1A = 0xb9,
- DBG_BLOCK_ID_TA1B = 0xba,
- DBG_BLOCK_ID_UNUSED27 = 0xbb,
- DBG_BLOCK_ID_UNUSED28 = 0xbc,
- DBG_BLOCK_ID_UNUSED29 = 0xbd,
- DBG_BLOCK_ID_UNUSED30 = 0xbe,
- DBG_BLOCK_ID_TD00 = 0xbf,
- DBG_BLOCK_ID_TD01 = 0xc0,
- DBG_BLOCK_ID_TD02 = 0xc1,
- DBG_BLOCK_ID_TD03 = 0xc2,
- DBG_BLOCK_ID_TD04 = 0xc3,
- DBG_BLOCK_ID_TD05 = 0xc4,
- DBG_BLOCK_ID_TD06 = 0xc5,
- DBG_BLOCK_ID_TD07 = 0xc6,
- DBG_BLOCK_ID_TD08 = 0xc7,
- DBG_BLOCK_ID_TD09 = 0xc8,
- DBG_BLOCK_ID_TD0A = 0xc9,
- DBG_BLOCK_ID_TD0B = 0xca,
- DBG_BLOCK_ID_UNUSED31 = 0xcb,
- DBG_BLOCK_ID_UNUSED32 = 0xcc,
- DBG_BLOCK_ID_UNUSED33 = 0xcd,
- DBG_BLOCK_ID_UNUSED34 = 0xce,
- DBG_BLOCK_ID_TD10 = 0xcf,
- DBG_BLOCK_ID_TD11 = 0xd0,
- DBG_BLOCK_ID_TD12 = 0xd1,
- DBG_BLOCK_ID_TD13 = 0xd2,
- DBG_BLOCK_ID_TD14 = 0xd3,
- DBG_BLOCK_ID_TD15 = 0xd4,
- DBG_BLOCK_ID_TD16 = 0xd5,
- DBG_BLOCK_ID_TD17 = 0xd6,
- DBG_BLOCK_ID_TD18 = 0xd7,
- DBG_BLOCK_ID_TD19 = 0xd8,
- DBG_BLOCK_ID_TD1A = 0xd9,
- DBG_BLOCK_ID_TD1B = 0xda,
- DBG_BLOCK_ID_UNUSED35 = 0xdb,
- DBG_BLOCK_ID_UNUSED36 = 0xdc,
- DBG_BLOCK_ID_UNUSED37 = 0xdd,
- DBG_BLOCK_ID_UNUSED38 = 0xde,
- DBG_BLOCK_ID_LDS00 = 0xdf,
- DBG_BLOCK_ID_LDS01 = 0xe0,
- DBG_BLOCK_ID_LDS02 = 0xe1,
- DBG_BLOCK_ID_LDS03 = 0xe2,
- DBG_BLOCK_ID_LDS04 = 0xe3,
- DBG_BLOCK_ID_LDS05 = 0xe4,
- DBG_BLOCK_ID_LDS06 = 0xe5,
- DBG_BLOCK_ID_LDS07 = 0xe6,
- DBG_BLOCK_ID_LDS08 = 0xe7,
- DBG_BLOCK_ID_LDS09 = 0xe8,
- DBG_BLOCK_ID_LDS0A = 0xe9,
- DBG_BLOCK_ID_LDS0B = 0xea,
- DBG_BLOCK_ID_UNUSED39 = 0xeb,
- DBG_BLOCK_ID_UNUSED40 = 0xec,
- DBG_BLOCK_ID_UNUSED41 = 0xed,
- DBG_BLOCK_ID_UNUSED42 = 0xee,
- DBG_BLOCK_ID_LDS10 = 0xef,
- DBG_BLOCK_ID_LDS11 = 0xf0,
- DBG_BLOCK_ID_LDS12 = 0xf1,
- DBG_BLOCK_ID_LDS13 = 0xf2,
- DBG_BLOCK_ID_LDS14 = 0xf3,
- DBG_BLOCK_ID_LDS15 = 0xf4,
- DBG_BLOCK_ID_LDS16 = 0xf5,
- DBG_BLOCK_ID_LDS17 = 0xf6,
- DBG_BLOCK_ID_LDS18 = 0xf7,
- DBG_BLOCK_ID_LDS19 = 0xf8,
- DBG_BLOCK_ID_LDS1A = 0xf9,
- DBG_BLOCK_ID_LDS1B = 0xfa,
- DBG_BLOCK_ID_UNUSED43 = 0xfb,
- DBG_BLOCK_ID_UNUSED44 = 0xfc,
- DBG_BLOCK_ID_UNUSED45 = 0xfd,
- DBG_BLOCK_ID_UNUSED46 = 0xfe,
-} DebugBlockId;
-typedef enum DebugBlockId_BY2 {
- DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
- DBG_BLOCK_ID_VMC_BY2 = 0x1,
- DBG_BLOCK_ID_UNUSED0_BY2 = 0x2,
- DBG_BLOCK_ID_GRBM_BY2 = 0x3,
- DBG_BLOCK_ID_CSC_BY2 = 0x4,
- DBG_BLOCK_ID_IH_BY2 = 0x5,
- DBG_BLOCK_ID_SQ_BY2 = 0x6,
- DBG_BLOCK_ID_UVD_BY2 = 0x7,
- DBG_BLOCK_ID_SDMA0_BY2 = 0x8,
- DBG_BLOCK_ID_SPIM_BY2 = 0x9,
- DBG_BLOCK_ID_VC0_BY2 = 0xa,
- DBG_BLOCK_ID_PA_BY2 = 0xb,
- DBG_BLOCK_ID_CP0_BY2 = 0xc,
- DBG_BLOCK_ID_CP2_BY2 = 0xd,
- DBG_BLOCK_ID_PC0_BY2 = 0xe,
- DBG_BLOCK_ID_BCI0_BY2 = 0xf,
- DBG_BLOCK_ID_SXM0_BY2 = 0x10,
- DBG_BLOCK_ID_SCT0_BY2 = 0x11,
- DBG_BLOCK_ID_SPM0_BY2 = 0x12,
- DBG_BLOCK_ID_BCI2_BY2 = 0x13,
- DBG_BLOCK_ID_TCA_BY2 = 0x14,
- DBG_BLOCK_ID_TCCA_BY2 = 0x15,
- DBG_BLOCK_ID_MCC_BY2 = 0x16,
- DBG_BLOCK_ID_MCC2_BY2 = 0x17,
- DBG_BLOCK_ID_MCD_BY2 = 0x18,
- DBG_BLOCK_ID_MCD2_BY2 = 0x19,
- DBG_BLOCK_ID_MCD4_BY2 = 0x1a,
- DBG_BLOCK_ID_MCB_BY2 = 0x1b,
- DBG_BLOCK_ID_SQA_BY2 = 0x1c,
- DBG_BLOCK_ID_SQA02_BY2 = 0x1d,
- DBG_BLOCK_ID_SQA11_BY2 = 0x1e,
- DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f,
- DBG_BLOCK_ID_SQB_BY2 = 0x20,
- DBG_BLOCK_ID_SQB10_BY2 = 0x21,
- DBG_BLOCK_ID_UNUSED10_BY2 = 0x22,
- DBG_BLOCK_ID_UNUSED12_BY2 = 0x23,
- DBG_BLOCK_ID_CB_BY2 = 0x24,
- DBG_BLOCK_ID_CB02_BY2 = 0x25,
- DBG_BLOCK_ID_CB10_BY2 = 0x26,
- DBG_BLOCK_ID_CB12_BY2 = 0x27,
- DBG_BLOCK_ID_SXS_BY2 = 0x28,
- DBG_BLOCK_ID_SXS2_BY2 = 0x29,
- DBG_BLOCK_ID_SXS4_BY2 = 0x2a,
- DBG_BLOCK_ID_SXS6_BY2 = 0x2b,
- DBG_BLOCK_ID_DB_BY2 = 0x2c,
- DBG_BLOCK_ID_DB02_BY2 = 0x2d,
- DBG_BLOCK_ID_DB10_BY2 = 0x2e,
- DBG_BLOCK_ID_DB12_BY2 = 0x2f,
- DBG_BLOCK_ID_TCP_BY2 = 0x30,
- DBG_BLOCK_ID_TCP2_BY2 = 0x31,
- DBG_BLOCK_ID_TCP4_BY2 = 0x32,
- DBG_BLOCK_ID_TCP6_BY2 = 0x33,
- DBG_BLOCK_ID_TCP8_BY2 = 0x34,
- DBG_BLOCK_ID_TCP10_BY2 = 0x35,
- DBG_BLOCK_ID_TCP12_BY2 = 0x36,
- DBG_BLOCK_ID_TCP14_BY2 = 0x37,
- DBG_BLOCK_ID_TCP16_BY2 = 0x38,
- DBG_BLOCK_ID_TCP18_BY2 = 0x39,
- DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
- DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
- DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
- DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
- DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
- DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
- DBG_BLOCK_ID_TCC_BY2 = 0x40,
- DBG_BLOCK_ID_TCC2_BY2 = 0x41,
- DBG_BLOCK_ID_TCC4_BY2 = 0x42,
- DBG_BLOCK_ID_TCC6_BY2 = 0x43,
- DBG_BLOCK_ID_SPS_BY2 = 0x44,
- DBG_BLOCK_ID_SPS02_BY2 = 0x45,
- DBG_BLOCK_ID_SPS11_BY2 = 0x46,
- DBG_BLOCK_ID_UNUSED14_BY2 = 0x47,
- DBG_BLOCK_ID_TA_BY2 = 0x48,
- DBG_BLOCK_ID_TA02_BY2 = 0x49,
- DBG_BLOCK_ID_TA04_BY2 = 0x4a,
- DBG_BLOCK_ID_TA06_BY2 = 0x4b,
- DBG_BLOCK_ID_TA08_BY2 = 0x4c,
- DBG_BLOCK_ID_TA0A_BY2 = 0x4d,
- DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e,
- DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f,
- DBG_BLOCK_ID_TA10_BY2 = 0x50,
- DBG_BLOCK_ID_TA12_BY2 = 0x51,
- DBG_BLOCK_ID_TA14_BY2 = 0x52,
- DBG_BLOCK_ID_TA16_BY2 = 0x53,
- DBG_BLOCK_ID_TA18_BY2 = 0x54,
- DBG_BLOCK_ID_TA1A_BY2 = 0x55,
- DBG_BLOCK_ID_UNUSED24_BY2 = 0x56,
- DBG_BLOCK_ID_UNUSED26_BY2 = 0x57,
- DBG_BLOCK_ID_TD_BY2 = 0x58,
- DBG_BLOCK_ID_TD02_BY2 = 0x59,
- DBG_BLOCK_ID_TD04_BY2 = 0x5a,
- DBG_BLOCK_ID_TD06_BY2 = 0x5b,
- DBG_BLOCK_ID_TD08_BY2 = 0x5c,
- DBG_BLOCK_ID_TD0A_BY2 = 0x5d,
- DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e,
- DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f,
- DBG_BLOCK_ID_TD10_BY2 = 0x60,
- DBG_BLOCK_ID_TD12_BY2 = 0x61,
- DBG_BLOCK_ID_TD14_BY2 = 0x62,
- DBG_BLOCK_ID_TD16_BY2 = 0x63,
- DBG_BLOCK_ID_TD18_BY2 = 0x64,
- DBG_BLOCK_ID_TD1A_BY2 = 0x65,
- DBG_BLOCK_ID_UNUSED32_BY2 = 0x66,
- DBG_BLOCK_ID_UNUSED34_BY2 = 0x67,
- DBG_BLOCK_ID_LDS_BY2 = 0x68,
- DBG_BLOCK_ID_LDS02_BY2 = 0x69,
- DBG_BLOCK_ID_LDS04_BY2 = 0x6a,
- DBG_BLOCK_ID_LDS06_BY2 = 0x6b,
- DBG_BLOCK_ID_LDS08_BY2 = 0x6c,
- DBG_BLOCK_ID_LDS0A_BY2 = 0x6d,
- DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e,
- DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f,
- DBG_BLOCK_ID_LDS10_BY2 = 0x70,
- DBG_BLOCK_ID_LDS12_BY2 = 0x71,
- DBG_BLOCK_ID_LDS14_BY2 = 0x72,
- DBG_BLOCK_ID_LDS16_BY2 = 0x73,
- DBG_BLOCK_ID_LDS18_BY2 = 0x74,
- DBG_BLOCK_ID_LDS1A_BY2 = 0x75,
- DBG_BLOCK_ID_UNUSED40_BY2 = 0x76,
- DBG_BLOCK_ID_UNUSED42_BY2 = 0x77,
-} DebugBlockId_BY2;
-typedef enum DebugBlockId_BY4 {
- DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
- DBG_BLOCK_ID_UNUSED0_BY4 = 0x1,
- DBG_BLOCK_ID_CSC_BY4 = 0x2,
- DBG_BLOCK_ID_SQ_BY4 = 0x3,
- DBG_BLOCK_ID_SDMA0_BY4 = 0x4,
- DBG_BLOCK_ID_VC0_BY4 = 0x5,
- DBG_BLOCK_ID_CP0_BY4 = 0x6,
- DBG_BLOCK_ID_UNUSED1_BY4 = 0x7,
- DBG_BLOCK_ID_SXM0_BY4 = 0x8,
- DBG_BLOCK_ID_SPM0_BY4 = 0x9,
- DBG_BLOCK_ID_TCAA_BY4 = 0xa,
- DBG_BLOCK_ID_MCC_BY4 = 0xb,
- DBG_BLOCK_ID_MCD_BY4 = 0xc,
- DBG_BLOCK_ID_MCD4_BY4 = 0xd,
- DBG_BLOCK_ID_SQA_BY4 = 0xe,
- DBG_BLOCK_ID_SQA11_BY4 = 0xf,
- DBG_BLOCK_ID_SQB_BY4 = 0x10,
- DBG_BLOCK_ID_UNUSED10_BY4 = 0x11,
- DBG_BLOCK_ID_CB_BY4 = 0x12,
- DBG_BLOCK_ID_CB10_BY4 = 0x13,
- DBG_BLOCK_ID_SXS_BY4 = 0x14,
- DBG_BLOCK_ID_SXS4_BY4 = 0x15,
- DBG_BLOCK_ID_DB_BY4 = 0x16,
- DBG_BLOCK_ID_DB10_BY4 = 0x17,
- DBG_BLOCK_ID_TCP_BY4 = 0x18,
- DBG_BLOCK_ID_TCP4_BY4 = 0x19,
- DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
- DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
- DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
- DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
- DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
- DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
- DBG_BLOCK_ID_TCC_BY4 = 0x20,
- DBG_BLOCK_ID_TCC4_BY4 = 0x21,
- DBG_BLOCK_ID_SPS_BY4 = 0x22,
- DBG_BLOCK_ID_SPS11_BY4 = 0x23,
- DBG_BLOCK_ID_TA_BY4 = 0x24,
- DBG_BLOCK_ID_TA04_BY4 = 0x25,
- DBG_BLOCK_ID_TA08_BY4 = 0x26,
- DBG_BLOCK_ID_UNUSED20_BY4 = 0x27,
- DBG_BLOCK_ID_TA10_BY4 = 0x28,
- DBG_BLOCK_ID_TA14_BY4 = 0x29,
- DBG_BLOCK_ID_TA18_BY4 = 0x2a,
- DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b,
- DBG_BLOCK_ID_TD_BY4 = 0x2c,
- DBG_BLOCK_ID_TD04_BY4 = 0x2d,
- DBG_BLOCK_ID_TD08_BY4 = 0x2e,
- DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f,
- DBG_BLOCK_ID_TD10_BY4 = 0x30,
- DBG_BLOCK_ID_TD14_BY4 = 0x31,
- DBG_BLOCK_ID_TD18_BY4 = 0x32,
- DBG_BLOCK_ID_UNUSED32_BY4 = 0x33,
- DBG_BLOCK_ID_LDS_BY4 = 0x34,
- DBG_BLOCK_ID_LDS04_BY4 = 0x35,
- DBG_BLOCK_ID_LDS08_BY4 = 0x36,
- DBG_BLOCK_ID_UNUSED36_BY4 = 0x37,
- DBG_BLOCK_ID_LDS10_BY4 = 0x38,
- DBG_BLOCK_ID_LDS14_BY4 = 0x39,
- DBG_BLOCK_ID_LDS18_BY4 = 0x3a,
- DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b,
-} DebugBlockId_BY4;
-typedef enum DebugBlockId_BY8 {
- DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
- DBG_BLOCK_ID_CSC_BY8 = 0x1,
- DBG_BLOCK_ID_SDMA0_BY8 = 0x2,
- DBG_BLOCK_ID_CP0_BY8 = 0x3,
- DBG_BLOCK_ID_SXM0_BY8 = 0x4,
- DBG_BLOCK_ID_TCA_BY8 = 0x5,
- DBG_BLOCK_ID_MCD_BY8 = 0x6,
- DBG_BLOCK_ID_SQA_BY8 = 0x7,
- DBG_BLOCK_ID_SQB_BY8 = 0x8,
- DBG_BLOCK_ID_CB_BY8 = 0x9,
- DBG_BLOCK_ID_SXS_BY8 = 0xa,
- DBG_BLOCK_ID_DB_BY8 = 0xb,
- DBG_BLOCK_ID_TCP_BY8 = 0xc,
- DBG_BLOCK_ID_TCP8_BY8 = 0xd,
- DBG_BLOCK_ID_TCP16_BY8 = 0xe,
- DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
- DBG_BLOCK_ID_TCC_BY8 = 0x10,
- DBG_BLOCK_ID_SPS_BY8 = 0x11,
- DBG_BLOCK_ID_TA_BY8 = 0x12,
- DBG_BLOCK_ID_TA08_BY8 = 0x13,
- DBG_BLOCK_ID_TA10_BY8 = 0x14,
- DBG_BLOCK_ID_TA18_BY8 = 0x15,
- DBG_BLOCK_ID_TD_BY8 = 0x16,
- DBG_BLOCK_ID_TD08_BY8 = 0x17,
- DBG_BLOCK_ID_TD10_BY8 = 0x18,
- DBG_BLOCK_ID_TD18_BY8 = 0x19,
- DBG_BLOCK_ID_LDS_BY8 = 0x1a,
- DBG_BLOCK_ID_LDS08_BY8 = 0x1b,
- DBG_BLOCK_ID_LDS10_BY8 = 0x1c,
- DBG_BLOCK_ID_LDS18_BY8 = 0x1d,
-} DebugBlockId_BY8;
-typedef enum DebugBlockId_BY16 {
- DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
- DBG_BLOCK_ID_SDMA0_BY16 = 0x1,
- DBG_BLOCK_ID_SXM_BY16 = 0x2,
- DBG_BLOCK_ID_MCD_BY16 = 0x3,
- DBG_BLOCK_ID_SQB_BY16 = 0x4,
- DBG_BLOCK_ID_SXS_BY16 = 0x5,
- DBG_BLOCK_ID_TCP_BY16 = 0x6,
- DBG_BLOCK_ID_TCP16_BY16 = 0x7,
- DBG_BLOCK_ID_TCC_BY16 = 0x8,
- DBG_BLOCK_ID_TA_BY16 = 0x9,
- DBG_BLOCK_ID_TA10_BY16 = 0xa,
- DBG_BLOCK_ID_TD_BY16 = 0xb,
- DBG_BLOCK_ID_TD10_BY16 = 0xc,
- DBG_BLOCK_ID_LDS_BY16 = 0xd,
- DBG_BLOCK_ID_LDS10_BY16 = 0xe,
-} DebugBlockId_BY16;
-typedef enum SurfaceEndian {
- ENDIAN_NONE = 0x0,
- ENDIAN_8IN16 = 0x1,
- ENDIAN_8IN32 = 0x2,
- ENDIAN_8IN64 = 0x3,
-} SurfaceEndian;
-typedef enum ArrayMode {
- ARRAY_LINEAR_GENERAL = 0x0,
- ARRAY_LINEAR_ALIGNED = 0x1,
- ARRAY_1D_TILED_THIN1 = 0x2,
- ARRAY_1D_TILED_THICK = 0x3,
- ARRAY_2D_TILED_THIN1 = 0x4,
- ARRAY_PRT_TILED_THIN1 = 0x5,
- ARRAY_PRT_2D_TILED_THIN1 = 0x6,
- ARRAY_2D_TILED_THICK = 0x7,
- ARRAY_2D_TILED_XTHICK = 0x8,
- ARRAY_PRT_TILED_THICK = 0x9,
- ARRAY_PRT_2D_TILED_THICK = 0xa,
- ARRAY_PRT_3D_TILED_THIN1 = 0xb,
- ARRAY_3D_TILED_THIN1 = 0xc,
- ARRAY_3D_TILED_THICK = 0xd,
- ARRAY_3D_TILED_XTHICK = 0xe,
- ARRAY_PRT_3D_TILED_THICK = 0xf,
-} ArrayMode;
-typedef enum PipeTiling {
- CONFIG_1_PIPE = 0x0,
- CONFIG_2_PIPE = 0x1,
- CONFIG_4_PIPE = 0x2,
- CONFIG_8_PIPE = 0x3,
-} PipeTiling;
-typedef enum BankTiling {
- CONFIG_4_BANK = 0x0,
- CONFIG_8_BANK = 0x1,
-} BankTiling;
-typedef enum GroupInterleave {
- CONFIG_256B_GROUP = 0x0,
- CONFIG_512B_GROUP = 0x1,
-} GroupInterleave;
-typedef enum RowTiling {
- CONFIG_1KB_ROW = 0x0,
- CONFIG_2KB_ROW = 0x1,
- CONFIG_4KB_ROW = 0x2,
- CONFIG_8KB_ROW = 0x3,
- CONFIG_1KB_ROW_OPT = 0x4,
- CONFIG_2KB_ROW_OPT = 0x5,
- CONFIG_4KB_ROW_OPT = 0x6,
- CONFIG_8KB_ROW_OPT = 0x7,
-} RowTiling;
-typedef enum BankSwapBytes {
- CONFIG_128B_SWAPS = 0x0,
- CONFIG_256B_SWAPS = 0x1,
- CONFIG_512B_SWAPS = 0x2,
- CONFIG_1KB_SWAPS = 0x3,
-} BankSwapBytes;
-typedef enum SampleSplitBytes {
- CONFIG_1KB_SPLIT = 0x0,
- CONFIG_2KB_SPLIT = 0x1,
- CONFIG_4KB_SPLIT = 0x2,
- CONFIG_8KB_SPLIT = 0x3,
-} SampleSplitBytes;
-typedef enum NumPipes {
- ADDR_CONFIG_1_PIPE = 0x0,
- ADDR_CONFIG_2_PIPE = 0x1,
- ADDR_CONFIG_4_PIPE = 0x2,
- ADDR_CONFIG_8_PIPE = 0x3,
-} NumPipes;
-typedef enum PipeInterleaveSize {
- ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
- ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
-} PipeInterleaveSize;
-typedef enum BankInterleaveSize {
- ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
- ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
- ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
- ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
-} BankInterleaveSize;
-typedef enum NumShaderEngines {
- ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
- ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
-} NumShaderEngines;
-typedef enum ShaderEngineTileSize {
- ADDR_CONFIG_SE_TILE_16 = 0x0,
- ADDR_CONFIG_SE_TILE_32 = 0x1,
-} ShaderEngineTileSize;
-typedef enum NumGPUs {
- ADDR_CONFIG_1_GPU = 0x0,
- ADDR_CONFIG_2_GPU = 0x1,
- ADDR_CONFIG_4_GPU = 0x2,
-} NumGPUs;
-typedef enum MultiGPUTileSize {
- ADDR_CONFIG_GPU_TILE_16 = 0x0,
- ADDR_CONFIG_GPU_TILE_32 = 0x1,
- ADDR_CONFIG_GPU_TILE_64 = 0x2,
- ADDR_CONFIG_GPU_TILE_128 = 0x3,
-} MultiGPUTileSize;
-typedef enum RowSize {
- ADDR_CONFIG_1KB_ROW = 0x0,
- ADDR_CONFIG_2KB_ROW = 0x1,
- ADDR_CONFIG_4KB_ROW = 0x2,
-} RowSize;
-typedef enum NumLowerPipes {
- ADDR_CONFIG_1_LOWER_PIPES = 0x0,
- ADDR_CONFIG_2_LOWER_PIPES = 0x1,
-} NumLowerPipes;
-typedef enum ColorTransform {
- DCC_CT_AUTO = 0x0,
- DCC_CT_NONE = 0x1,
- ABGR_TO_A_BG_G_RB = 0x2,
- BGRA_TO_BG_G_RB_A = 0x3,
-} ColorTransform;
-typedef enum CompareRef {
- REF_NEVER = 0x0,
- REF_LESS = 0x1,
- REF_EQUAL = 0x2,
- REF_LEQUAL = 0x3,
- REF_GREATER = 0x4,
- REF_NOTEQUAL = 0x5,
- REF_GEQUAL = 0x6,
- REF_ALWAYS = 0x7,
-} CompareRef;
-typedef enum ReadSize {
- READ_256_BITS = 0x0,
- READ_512_BITS = 0x1,
-} ReadSize;
-typedef enum DepthFormat {
- DEPTH_INVALID = 0x0,
- DEPTH_16 = 0x1,
- DEPTH_X8_24 = 0x2,
- DEPTH_8_24 = 0x3,
- DEPTH_X8_24_FLOAT = 0x4,
- DEPTH_8_24_FLOAT = 0x5,
- DEPTH_32_FLOAT = 0x6,
- DEPTH_X24_8_32_FLOAT = 0x7,
-} DepthFormat;
-typedef enum ZFormat {
- Z_INVALID = 0x0,
- Z_16 = 0x1,
- Z_24 = 0x2,
- Z_32_FLOAT = 0x3,
-} ZFormat;
-typedef enum StencilFormat {
- STENCIL_INVALID = 0x0,
- STENCIL_8 = 0x1,
-} StencilFormat;
-typedef enum CmaskMode {
- CMASK_CLEAR_NONE = 0x0,
- CMASK_CLEAR_ONE = 0x1,
- CMASK_CLEAR_ALL = 0x2,
- CMASK_ANY_EXPANDED = 0x3,
- CMASK_ALPHA0_FRAG1 = 0x4,
- CMASK_ALPHA0_FRAG2 = 0x5,
- CMASK_ALPHA0_FRAG4 = 0x6,
- CMASK_ALPHA0_FRAGS = 0x7,
- CMASK_ALPHA1_FRAG1 = 0x8,
- CMASK_ALPHA1_FRAG2 = 0x9,
- CMASK_ALPHA1_FRAG4 = 0xa,
- CMASK_ALPHA1_FRAGS = 0xb,
- CMASK_ALPHAX_FRAG1 = 0xc,
- CMASK_ALPHAX_FRAG2 = 0xd,
- CMASK_ALPHAX_FRAG4 = 0xe,
- CMASK_ALPHAX_FRAGS = 0xf,
-} CmaskMode;
-typedef enum QuadExportFormat {
- EXPORT_UNUSED = 0x0,
- EXPORT_32_R = 0x1,
- EXPORT_32_GR = 0x2,
- EXPORT_32_AR = 0x3,
- EXPORT_FP16_ABGR = 0x4,
- EXPORT_UNSIGNED16_ABGR = 0x5,
- EXPORT_SIGNED16_ABGR = 0x6,
- EXPORT_32_ABGR = 0x7,
-} QuadExportFormat;
-typedef enum QuadExportFormatOld {
- EXPORT_4P_32BPC_ABGR = 0x0,
- EXPORT_4P_16BPC_ABGR = 0x1,
- EXPORT_4P_32BPC_GR = 0x2,
- EXPORT_4P_32BPC_AR = 0x3,
- EXPORT_2P_32BPC_ABGR = 0x4,
- EXPORT_8P_32BPC_R = 0x5,
-} QuadExportFormatOld;
-typedef enum ColorFormat {
- COLOR_INVALID = 0x0,
- COLOR_8 = 0x1,
- COLOR_16 = 0x2,
- COLOR_8_8 = 0x3,
- COLOR_32 = 0x4,
- COLOR_16_16 = 0x5,
- COLOR_10_11_11 = 0x6,
- COLOR_11_11_10 = 0x7,
- COLOR_10_10_10_2 = 0x8,
- COLOR_2_10_10_10 = 0x9,
- COLOR_8_8_8_8 = 0xa,
- COLOR_32_32 = 0xb,
- COLOR_16_16_16_16 = 0xc,
- COLOR_RESERVED_13 = 0xd,
- COLOR_32_32_32_32 = 0xe,
- COLOR_RESERVED_15 = 0xf,
- COLOR_5_6_5 = 0x10,
- COLOR_1_5_5_5 = 0x11,
- COLOR_5_5_5_1 = 0x12,
- COLOR_4_4_4_4 = 0x13,
- COLOR_8_24 = 0x14,
- COLOR_24_8 = 0x15,
- COLOR_X24_8_32_FLOAT = 0x16,
- COLOR_RESERVED_23 = 0x17,
-} ColorFormat;
-typedef enum SurfaceFormat {
- FMT_INVALID = 0x0,
- FMT_8 = 0x1,
- FMT_16 = 0x2,
- FMT_8_8 = 0x3,
- FMT_32 = 0x4,
- FMT_16_16 = 0x5,
- FMT_10_11_11 = 0x6,
- FMT_11_11_10 = 0x7,
- FMT_10_10_10_2 = 0x8,
- FMT_2_10_10_10 = 0x9,
- FMT_8_8_8_8 = 0xa,
- FMT_32_32 = 0xb,
- FMT_16_16_16_16 = 0xc,
- FMT_32_32_32 = 0xd,
- FMT_32_32_32_32 = 0xe,
- FMT_RESERVED_4 = 0xf,
- FMT_5_6_5 = 0x10,
- FMT_1_5_5_5 = 0x11,
- FMT_5_5_5_1 = 0x12,
- FMT_4_4_4_4 = 0x13,
- FMT_8_24 = 0x14,
- FMT_24_8 = 0x15,
- FMT_X24_8_32_FLOAT = 0x16,
- FMT_RESERVED_33 = 0x17,
- FMT_11_11_10_FLOAT = 0x18,
- FMT_16_FLOAT = 0x19,
- FMT_32_FLOAT = 0x1a,
- FMT_16_16_FLOAT = 0x1b,
- FMT_8_24_FLOAT = 0x1c,
- FMT_24_8_FLOAT = 0x1d,
- FMT_32_32_FLOAT = 0x1e,
- FMT_10_11_11_FLOAT = 0x1f,
- FMT_16_16_16_16_FLOAT = 0x20,
- FMT_3_3_2 = 0x21,
- FMT_6_5_5 = 0x22,
- FMT_32_32_32_32_FLOAT = 0x23,
- FMT_RESERVED_36 = 0x24,
- FMT_1 = 0x25,
- FMT_1_REVERSED = 0x26,
- FMT_GB_GR = 0x27,
- FMT_BG_RG = 0x28,
- FMT_32_AS_8 = 0x29,
- FMT_32_AS_8_8 = 0x2a,
- FMT_5_9_9_9_SHAREDEXP = 0x2b,
- FMT_8_8_8 = 0x2c,
- FMT_16_16_16 = 0x2d,
- FMT_16_16_16_FLOAT = 0x2e,
- FMT_4_4 = 0x2f,
- FMT_32_32_32_FLOAT = 0x30,
- FMT_BC1 = 0x31,
- FMT_BC2 = 0x32,
- FMT_BC3 = 0x33,
- FMT_BC4 = 0x34,
- FMT_BC5 = 0x35,
- FMT_BC6 = 0x36,
- FMT_BC7 = 0x37,
- FMT_32_AS_32_32_32_32 = 0x38,
- FMT_APC3 = 0x39,
- FMT_APC4 = 0x3a,
- FMT_APC5 = 0x3b,
- FMT_APC6 = 0x3c,
- FMT_APC7 = 0x3d,
- FMT_CTX1 = 0x3e,
- FMT_RESERVED_63 = 0x3f,
-} SurfaceFormat;
-typedef enum BUF_DATA_FORMAT {
- BUF_DATA_FORMAT_INVALID = 0x0,
- BUF_DATA_FORMAT_8 = 0x1,
- BUF_DATA_FORMAT_16 = 0x2,
- BUF_DATA_FORMAT_8_8 = 0x3,
- BUF_DATA_FORMAT_32 = 0x4,
- BUF_DATA_FORMAT_16_16 = 0x5,
- BUF_DATA_FORMAT_10_11_11 = 0x6,
- BUF_DATA_FORMAT_11_11_10 = 0x7,
- BUF_DATA_FORMAT_10_10_10_2 = 0x8,
- BUF_DATA_FORMAT_2_10_10_10 = 0x9,
- BUF_DATA_FORMAT_8_8_8_8 = 0xa,
- BUF_DATA_FORMAT_32_32 = 0xb,
- BUF_DATA_FORMAT_16_16_16_16 = 0xc,
- BUF_DATA_FORMAT_32_32_32 = 0xd,
- BUF_DATA_FORMAT_32_32_32_32 = 0xe,
- BUF_DATA_FORMAT_RESERVED_15 = 0xf,
-} BUF_DATA_FORMAT;
-typedef enum IMG_DATA_FORMAT {
- IMG_DATA_FORMAT_INVALID = 0x0,
- IMG_DATA_FORMAT_8 = 0x1,
- IMG_DATA_FORMAT_16 = 0x2,
- IMG_DATA_FORMAT_8_8 = 0x3,
- IMG_DATA_FORMAT_32 = 0x4,
- IMG_DATA_FORMAT_16_16 = 0x5,
- IMG_DATA_FORMAT_10_11_11 = 0x6,
- IMG_DATA_FORMAT_11_11_10 = 0x7,
- IMG_DATA_FORMAT_10_10_10_2 = 0x8,
- IMG_DATA_FORMAT_2_10_10_10 = 0x9,
- IMG_DATA_FORMAT_8_8_8_8 = 0xa,
- IMG_DATA_FORMAT_32_32 = 0xb,
- IMG_DATA_FORMAT_16_16_16_16 = 0xc,
- IMG_DATA_FORMAT_32_32_32 = 0xd,
- IMG_DATA_FORMAT_32_32_32_32 = 0xe,
- IMG_DATA_FORMAT_RESERVED_15 = 0xf,
- IMG_DATA_FORMAT_5_6_5 = 0x10,
- IMG_DATA_FORMAT_1_5_5_5 = 0x11,
- IMG_DATA_FORMAT_5_5_5_1 = 0x12,
- IMG_DATA_FORMAT_4_4_4_4 = 0x13,
- IMG_DATA_FORMAT_8_24 = 0x14,
- IMG_DATA_FORMAT_24_8 = 0x15,
- IMG_DATA_FORMAT_X24_8_32 = 0x16,
- IMG_DATA_FORMAT_RESERVED_23 = 0x17,
- IMG_DATA_FORMAT_RESERVED_24 = 0x18,
- IMG_DATA_FORMAT_RESERVED_25 = 0x19,
- IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
- IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
- IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
- IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
- IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
- IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
- IMG_DATA_FORMAT_GB_GR = 0x20,
- IMG_DATA_FORMAT_BG_RG = 0x21,
- IMG_DATA_FORMAT_5_9_9_9 = 0x22,
- IMG_DATA_FORMAT_BC1 = 0x23,
- IMG_DATA_FORMAT_BC2 = 0x24,
- IMG_DATA_FORMAT_BC3 = 0x25,
- IMG_DATA_FORMAT_BC4 = 0x26,
- IMG_DATA_FORMAT_BC5 = 0x27,
- IMG_DATA_FORMAT_BC6 = 0x28,
- IMG_DATA_FORMAT_BC7 = 0x29,
- IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
- IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
- IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
- IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
- IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
- IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
- IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
- IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
- IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
- IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
- IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
- IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
- IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
- IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
- IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
- IMG_DATA_FORMAT_4_4 = 0x39,
- IMG_DATA_FORMAT_6_5_5 = 0x3a,
- IMG_DATA_FORMAT_1 = 0x3b,
- IMG_DATA_FORMAT_1_REVERSED = 0x3c,
- IMG_DATA_FORMAT_32_AS_8 = 0x3d,
- IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
- IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
-} IMG_DATA_FORMAT;
-typedef enum BUF_NUM_FORMAT {
- BUF_NUM_FORMAT_UNORM = 0x0,
- BUF_NUM_FORMAT_SNORM = 0x1,
- BUF_NUM_FORMAT_USCALED = 0x2,
- BUF_NUM_FORMAT_SSCALED = 0x3,
- BUF_NUM_FORMAT_UINT = 0x4,
- BUF_NUM_FORMAT_SINT = 0x5,
- BUF_NUM_FORMAT_RESERVED_6 = 0x6,
- BUF_NUM_FORMAT_FLOAT = 0x7,
-} BUF_NUM_FORMAT;
-typedef enum IMG_NUM_FORMAT {
- IMG_NUM_FORMAT_UNORM = 0x0,
- IMG_NUM_FORMAT_SNORM = 0x1,
- IMG_NUM_FORMAT_USCALED = 0x2,
- IMG_NUM_FORMAT_SSCALED = 0x3,
- IMG_NUM_FORMAT_UINT = 0x4,
- IMG_NUM_FORMAT_SINT = 0x5,
- IMG_NUM_FORMAT_RESERVED_6 = 0x6,
- IMG_NUM_FORMAT_FLOAT = 0x7,
- IMG_NUM_FORMAT_RESERVED_8 = 0x8,
- IMG_NUM_FORMAT_SRGB = 0x9,
- IMG_NUM_FORMAT_RESERVED_10 = 0xa,
- IMG_NUM_FORMAT_RESERVED_11 = 0xb,
- IMG_NUM_FORMAT_RESERVED_12 = 0xc,
- IMG_NUM_FORMAT_RESERVED_13 = 0xd,
- IMG_NUM_FORMAT_RESERVED_14 = 0xe,
- IMG_NUM_FORMAT_RESERVED_15 = 0xf,
-} IMG_NUM_FORMAT;
-typedef enum TileType {
- ARRAY_COLOR_TILE = 0x0,
- ARRAY_DEPTH_TILE = 0x1,
-} TileType;
-typedef enum NonDispTilingOrder {
- ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
- ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
-} NonDispTilingOrder;
-typedef enum MicroTileMode {
- ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
- ADDR_SURF_THIN_MICRO_TILING = 0x1,
- ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
- ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
- ADDR_SURF_THICK_MICRO_TILING = 0x4,
-} MicroTileMode;
-typedef enum TileSplit {
- ADDR_SURF_TILE_SPLIT_64B = 0x0,
- ADDR_SURF_TILE_SPLIT_128B = 0x1,
- ADDR_SURF_TILE_SPLIT_256B = 0x2,
- ADDR_SURF_TILE_SPLIT_512B = 0x3,
- ADDR_SURF_TILE_SPLIT_1KB = 0x4,
- ADDR_SURF_TILE_SPLIT_2KB = 0x5,
- ADDR_SURF_TILE_SPLIT_4KB = 0x6,
-} TileSplit;
-typedef enum SampleSplit {
- ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
- ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
- ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
- ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
-} SampleSplit;
-typedef enum PipeConfig {
- ADDR_SURF_P2 = 0x0,
- ADDR_SURF_P2_RESERVED0 = 0x1,
- ADDR_SURF_P2_RESERVED1 = 0x2,
- ADDR_SURF_P2_RESERVED2 = 0x3,
- ADDR_SURF_P4_8x16 = 0x4,
- ADDR_SURF_P4_16x16 = 0x5,
- ADDR_SURF_P4_16x32 = 0x6,
- ADDR_SURF_P4_32x32 = 0x7,
- ADDR_SURF_P8_16x16_8x16 = 0x8,
- ADDR_SURF_P8_16x32_8x16 = 0x9,
- ADDR_SURF_P8_32x32_8x16 = 0xa,
- ADDR_SURF_P8_16x32_16x16 = 0xb,
- ADDR_SURF_P8_32x32_16x16 = 0xc,
- ADDR_SURF_P8_32x32_16x32 = 0xd,
- ADDR_SURF_P8_32x64_32x32 = 0xe,
- ADDR_SURF_P8_RESERVED0 = 0xf,
- ADDR_SURF_P16_32x32_8x16 = 0x10,
- ADDR_SURF_P16_32x32_16x16 = 0x11,
-} PipeConfig;
-typedef enum NumBanks {
- ADDR_SURF_2_BANK = 0x0,
- ADDR_SURF_4_BANK = 0x1,
- ADDR_SURF_8_BANK = 0x2,
- ADDR_SURF_16_BANK = 0x3,
-} NumBanks;
-typedef enum BankWidth {
- ADDR_SURF_BANK_WIDTH_1 = 0x0,
- ADDR_SURF_BANK_WIDTH_2 = 0x1,
- ADDR_SURF_BANK_WIDTH_4 = 0x2,
- ADDR_SURF_BANK_WIDTH_8 = 0x3,
-} BankWidth;
-typedef enum BankHeight {
- ADDR_SURF_BANK_HEIGHT_1 = 0x0,
- ADDR_SURF_BANK_HEIGHT_2 = 0x1,
- ADDR_SURF_BANK_HEIGHT_4 = 0x2,
- ADDR_SURF_BANK_HEIGHT_8 = 0x3,
-} BankHeight;
-typedef enum BankWidthHeight {
- ADDR_SURF_BANK_WH_1 = 0x0,
- ADDR_SURF_BANK_WH_2 = 0x1,
- ADDR_SURF_BANK_WH_4 = 0x2,
- ADDR_SURF_BANK_WH_8 = 0x3,
-} BankWidthHeight;
-typedef enum MacroTileAspect {
- ADDR_SURF_MACRO_ASPECT_1 = 0x0,
- ADDR_SURF_MACRO_ASPECT_2 = 0x1,
- ADDR_SURF_MACRO_ASPECT_4 = 0x2,
- ADDR_SURF_MACRO_ASPECT_8 = 0x3,
-} MacroTileAspect;
-typedef enum GATCL1RequestType {
- GATCL1_TYPE_NORMAL = 0x0,
- GATCL1_TYPE_SHOOTDOWN = 0x1,
- GATCL1_TYPE_BYPASS = 0x2,
-} GATCL1RequestType;
-typedef enum TCC_CACHE_POLICIES {
- TCC_CACHE_POLICY_LRU = 0x0,
- TCC_CACHE_POLICY_STREAM = 0x1,
-} TCC_CACHE_POLICIES;
-typedef enum MTYPE {
- MTYPE_NC_NV = 0x0,
- MTYPE_NC = 0x1,
- MTYPE_CC = 0x2,
- MTYPE_UC = 0x3,
-} MTYPE;
-typedef enum PERFMON_COUNTER_MODE {
- PERFMON_COUNTER_MODE_ACCUM = 0x0,
- PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
- PERFMON_COUNTER_MODE_MAX = 0x2,
- PERFMON_COUNTER_MODE_DIRTY = 0x3,
- PERFMON_COUNTER_MODE_SAMPLE = 0x4,
- PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
- PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
- PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
- PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
- PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
- PERFMON_COUNTER_MODE_RESERVED = 0xf,
-} PERFMON_COUNTER_MODE;
-typedef enum PERFMON_SPM_MODE {
- PERFMON_SPM_MODE_OFF = 0x0,
- PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
- PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
- PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
- PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
- PERFMON_SPM_MODE_RESERVED_5 = 0x5,
- PERFMON_SPM_MODE_RESERVED_6 = 0x6,
- PERFMON_SPM_MODE_RESERVED_7 = 0x7,
- PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
- PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
- PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
-} PERFMON_SPM_MODE;
-typedef enum SurfaceTiling {
- ARRAY_LINEAR = 0x0,
- ARRAY_TILED = 0x1,
-} SurfaceTiling;
-typedef enum SurfaceArray {
- ARRAY_1D = 0x0,
- ARRAY_2D = 0x1,
- ARRAY_3D = 0x2,
- ARRAY_3D_SLICE = 0x3,
-} SurfaceArray;
-typedef enum ColorArray {
- ARRAY_2D_ALT_COLOR = 0x0,
- ARRAY_2D_COLOR = 0x1,
- ARRAY_3D_SLICE_COLOR = 0x3,
-} ColorArray;
-typedef enum DepthArray {
- ARRAY_2D_ALT_DEPTH = 0x0,
- ARRAY_2D_DEPTH = 0x1,
-} DepthArray;
-typedef enum ENUM_NUM_SIMD_PER_CU {
- NUM_SIMD_PER_CU = 0x4,
-} ENUM_NUM_SIMD_PER_CU;
-typedef enum MEM_PWR_FORCE_CTRL {
- NO_FORCE_REQUEST = 0x0,
- FORCE_LIGHT_SLEEP_REQUEST = 0x1,
- FORCE_DEEP_SLEEP_REQUEST = 0x2,
- FORCE_SHUT_DOWN_REQUEST = 0x3,
-} MEM_PWR_FORCE_CTRL;
-typedef enum MEM_PWR_FORCE_CTRL2 {
- NO_FORCE_REQ = 0x0,
- FORCE_LIGHT_SLEEP_REQ = 0x1,
-} MEM_PWR_FORCE_CTRL2;
-typedef enum MEM_PWR_DIS_CTRL {
- ENABLE_MEM_PWR_CTRL = 0x0,
- DISABLE_MEM_PWR_CTRL = 0x1,
-} MEM_PWR_DIS_CTRL;
-typedef enum MEM_PWR_SEL_CTRL {
- DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
- DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
- DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
-} MEM_PWR_SEL_CTRL;
-typedef enum MEM_PWR_SEL_CTRL2 {
- DYNAMIC_DEEP_SLEEP_EN = 0x0,
- DYNAMIC_LIGHT_SLEEP_EN = 0x1,
-} MEM_PWR_SEL_CTRL2;
-
-#endif /* GMC_8_2_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_4_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_4_2_offset.h
deleted file mode 100644
index 546b043cc..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_4_2_offset.h
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * Copyright 2022 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef _hdp_4_4_2_OFFSET_HEADER
-#define _hdp_4_4_2_OFFSET_HEADER
-
-
-
-// addressBlock: aid_hdp_hdpdec
-// base address: 0x3c80
-#define regHDP_MMHUB_TLVL 0x0000
-#define regHDP_MMHUB_TLVL_BASE_IDX 0
-#define regHDP_MMHUB_UNITID 0x0001
-#define regHDP_MMHUB_UNITID_BASE_IDX 0
-#define regHDP_NONSURFACE_BASE 0x0040
-#define regHDP_NONSURFACE_BASE_BASE_IDX 0
-#define regHDP_NONSURFACE_INFO 0x0041
-#define regHDP_NONSURFACE_INFO_BASE_IDX 0
-#define regHDP_NONSURFACE_BASE_HI 0x0042
-#define regHDP_NONSURFACE_BASE_HI_BASE_IDX 0
-#define regHDP_SURFACE_WRITE_FLAGS 0x00c4
-#define regHDP_SURFACE_WRITE_FLAGS_BASE_IDX 0
-#define regHDP_SURFACE_READ_FLAGS 0x00c5
-#define regHDP_SURFACE_READ_FLAGS_BASE_IDX 0
-#define regHDP_SURFACE_WRITE_FLAGS_CLR 0x00c6
-#define regHDP_SURFACE_WRITE_FLAGS_CLR_BASE_IDX 0
-#define regHDP_SURFACE_READ_FLAGS_CLR 0x00c7
-#define regHDP_SURFACE_READ_FLAGS_CLR_BASE_IDX 0
-#define regHDP_NONSURF_FLAGS 0x00c8
-#define regHDP_NONSURF_FLAGS_BASE_IDX 0
-#define regHDP_NONSURF_FLAGS_CLR 0x00c9
-#define regHDP_NONSURF_FLAGS_CLR_BASE_IDX 0
-#define regHDP_HOST_PATH_CNTL 0x00cc
-#define regHDP_HOST_PATH_CNTL_BASE_IDX 0
-#define regHDP_SW_SEMAPHORE 0x00cd
-#define regHDP_SW_SEMAPHORE_BASE_IDX 0
-#define regHDP_DEBUG0 0x00ce
-#define regHDP_DEBUG0_BASE_IDX 0
-#define regHDP_LAST_SURFACE_HIT 0x00d0
-#define regHDP_LAST_SURFACE_HIT_BASE_IDX 0
-#define regHDP_OUTSTANDING_REQ 0x00d2
-#define regHDP_OUTSTANDING_REQ_BASE_IDX 0
-#define regHDP_MISC_CNTL 0x00d3
-#define regHDP_MISC_CNTL_BASE_IDX 0
-#define regHDP_MEM_POWER_CTRL 0x00d4
-#define regHDP_MEM_POWER_CTRL_BASE_IDX 0
-#define regHDP_MMHUB_CNTL 0x00d5
-#define regHDP_MMHUB_CNTL_BASE_IDX 0
-#define regHDP_EDC_CNT 0x00d6
-#define regHDP_EDC_CNT_BASE_IDX 0
-#define regHDP_VERSION 0x00d7
-#define regHDP_VERSION_BASE_IDX 0
-#define regHDP_CLK_CNTL 0x00d8
-#define regHDP_CLK_CNTL_BASE_IDX 0
-#define regHDP_MEMIO_CNTL 0x00f6
-#define regHDP_MEMIO_CNTL_BASE_IDX 0
-#define regHDP_MEMIO_ADDR 0x00f7
-#define regHDP_MEMIO_ADDR_BASE_IDX 0
-#define regHDP_MEMIO_STATUS 0x00f8
-#define regHDP_MEMIO_STATUS_BASE_IDX 0
-#define regHDP_MEMIO_WR_DATA 0x00f9
-#define regHDP_MEMIO_WR_DATA_BASE_IDX 0
-#define regHDP_MEMIO_RD_DATA 0x00fa
-#define regHDP_MEMIO_RD_DATA_BASE_IDX 0
-#define regHDP_XDP_DIRECT2HDP_FIRST 0x0100
-#define regHDP_XDP_DIRECT2HDP_FIRST_BASE_IDX 0
-#define regHDP_XDP_D2H_FLUSH 0x0101
-#define regHDP_XDP_D2H_FLUSH_BASE_IDX 0
-#define regHDP_XDP_D2H_BAR_UPDATE 0x0102
-#define regHDP_XDP_D2H_BAR_UPDATE_BASE_IDX 0
-#define regHDP_XDP_D2H_RSVD_3 0x0103
-#define regHDP_XDP_D2H_RSVD_3_BASE_IDX 0
-#define regHDP_XDP_D2H_RSVD_4 0x0104
-#define regHDP_XDP_D2H_RSVD_4_BASE_IDX 0
-#define regHDP_XDP_D2H_RSVD_5 0x0105
-#define regHDP_XDP_D2H_RSVD_5_BASE_IDX 0
-#define regHDP_XDP_D2H_RSVD_6 0x0106
-#define regHDP_XDP_D2H_RSVD_6_BASE_IDX 0
-#define regHDP_XDP_D2H_RSVD_7 0x0107
-#define regHDP_XDP_D2H_RSVD_7_BASE_IDX 0
-#define regHDP_XDP_D2H_RSVD_8 0x0108
-#define regHDP_XDP_D2H_RSVD_8_BASE_IDX 0
-#define regHDP_XDP_D2H_RSVD_9 0x0109
-#define regHDP_XDP_D2H_RSVD_9_BASE_IDX 0
-#define regHDP_XDP_D2H_RSVD_10 0x010a
-#define regHDP_XDP_D2H_RSVD_10_BASE_IDX 0
-#define regHDP_XDP_D2H_RSVD_11 0x010b
-#define regHDP_XDP_D2H_RSVD_11_BASE_IDX 0
-#define regHDP_XDP_D2H_RSVD_12 0x010c
-#define regHDP_XDP_D2H_RSVD_12_BASE_IDX 0
-#define regHDP_XDP_D2H_RSVD_13 0x010d
-#define regHDP_XDP_D2H_RSVD_13_BASE_IDX 0
-#define regHDP_XDP_D2H_RSVD_14 0x010e
-#define regHDP_XDP_D2H_RSVD_14_BASE_IDX 0
-#define regHDP_XDP_D2H_RSVD_15 0x010f
-#define regHDP_XDP_D2H_RSVD_15_BASE_IDX 0
-#define regHDP_XDP_D2H_RSVD_16 0x0110
-#define regHDP_XDP_D2H_RSVD_16_BASE_IDX 0
-#define regHDP_XDP_D2H_RSVD_17 0x0111
-#define regHDP_XDP_D2H_RSVD_17_BASE_IDX 0
-#define regHDP_XDP_D2H_RSVD_18 0x0112
-#define regHDP_XDP_D2H_RSVD_18_BASE_IDX 0
-#define regHDP_XDP_D2H_RSVD_19 0x0113
-#define regHDP_XDP_D2H_RSVD_19_BASE_IDX 0
-#define regHDP_XDP_D2H_RSVD_20 0x0114
-#define regHDP_XDP_D2H_RSVD_20_BASE_IDX 0
-#define regHDP_XDP_D2H_RSVD_21 0x0115
-#define regHDP_XDP_D2H_RSVD_21_BASE_IDX 0
-#define regHDP_XDP_D2H_RSVD_22 0x0116
-#define regHDP_XDP_D2H_RSVD_22_BASE_IDX 0
-#define regHDP_XDP_D2H_RSVD_23 0x0117
-#define regHDP_XDP_D2H_RSVD_23_BASE_IDX 0
-#define regHDP_XDP_D2H_RSVD_24 0x0118
-#define regHDP_XDP_D2H_RSVD_24_BASE_IDX 0
-#define regHDP_XDP_D2H_RSVD_25 0x0119
-#define regHDP_XDP_D2H_RSVD_25_BASE_IDX 0
-#define regHDP_XDP_D2H_RSVD_26 0x011a
-#define regHDP_XDP_D2H_RSVD_26_BASE_IDX 0
-#define regHDP_XDP_D2H_RSVD_27 0x011b
-#define regHDP_XDP_D2H_RSVD_27_BASE_IDX 0
-#define regHDP_XDP_D2H_RSVD_28 0x011c
-#define regHDP_XDP_D2H_RSVD_28_BASE_IDX 0
-#define regHDP_XDP_D2H_RSVD_29 0x011d
-#define regHDP_XDP_D2H_RSVD_29_BASE_IDX 0
-#define regHDP_XDP_D2H_RSVD_30 0x011e
-#define regHDP_XDP_D2H_RSVD_30_BASE_IDX 0
-#define regHDP_XDP_D2H_RSVD_31 0x011f
-#define regHDP_XDP_D2H_RSVD_31_BASE_IDX 0
-#define regHDP_XDP_D2H_RSVD_32 0x0120
-#define regHDP_XDP_D2H_RSVD_32_BASE_IDX 0
-#define regHDP_XDP_D2H_RSVD_33 0x0121
-#define regHDP_XDP_D2H_RSVD_33_BASE_IDX 0
-#define regHDP_XDP_D2H_RSVD_34 0x0122
-#define regHDP_XDP_D2H_RSVD_34_BASE_IDX 0
-#define regHDP_XDP_DIRECT2HDP_LAST 0x0123
-#define regHDP_XDP_DIRECT2HDP_LAST_BASE_IDX 0
-#define regHDP_XDP_P2P_BAR_CFG 0x0124
-#define regHDP_XDP_P2P_BAR_CFG_BASE_IDX 0
-#define regHDP_XDP_P2P_MBX_OFFSET 0x0125
-#define regHDP_XDP_P2P_MBX_OFFSET_BASE_IDX 0
-#define regHDP_XDP_P2P_MBX_ADDR0 0x0126
-#define regHDP_XDP_P2P_MBX_ADDR0_BASE_IDX 0
-#define regHDP_XDP_P2P_MBX_ADDR1 0x0127
-#define regHDP_XDP_P2P_MBX_ADDR1_BASE_IDX 0
-#define regHDP_XDP_P2P_MBX_ADDR2 0x0128
-#define regHDP_XDP_P2P_MBX_ADDR2_BASE_IDX 0
-#define regHDP_XDP_P2P_MBX_ADDR3 0x0129
-#define regHDP_XDP_P2P_MBX_ADDR3_BASE_IDX 0
-#define regHDP_XDP_P2P_MBX_ADDR4 0x012a
-#define regHDP_XDP_P2P_MBX_ADDR4_BASE_IDX 0
-#define regHDP_XDP_P2P_MBX_ADDR5 0x012b
-#define regHDP_XDP_P2P_MBX_ADDR5_BASE_IDX 0
-#define regHDP_XDP_P2P_MBX_ADDR6 0x012c
-#define regHDP_XDP_P2P_MBX_ADDR6_BASE_IDX 0
-#define regHDP_XDP_HDP_MBX_MC_CFG 0x012d
-#define regHDP_XDP_HDP_MBX_MC_CFG_BASE_IDX 0
-#define regHDP_XDP_HDP_MC_CFG 0x012e
-#define regHDP_XDP_HDP_MC_CFG_BASE_IDX 0
-#define regHDP_XDP_HST_CFG 0x012f
-#define regHDP_XDP_HST_CFG_BASE_IDX 0
-#define regHDP_XDP_HDP_IPH_CFG 0x0131
-#define regHDP_XDP_HDP_IPH_CFG_BASE_IDX 0
-#define regHDP_XDP_P2P_BAR0 0x0134
-#define regHDP_XDP_P2P_BAR0_BASE_IDX 0
-#define regHDP_XDP_P2P_BAR1 0x0135
-#define regHDP_XDP_P2P_BAR1_BASE_IDX 0
-#define regHDP_XDP_P2P_BAR2 0x0136
-#define regHDP_XDP_P2P_BAR2_BASE_IDX 0
-#define regHDP_XDP_P2P_BAR3 0x0137
-#define regHDP_XDP_P2P_BAR3_BASE_IDX 0
-#define regHDP_XDP_P2P_BAR4 0x0138
-#define regHDP_XDP_P2P_BAR4_BASE_IDX 0
-#define regHDP_XDP_P2P_BAR5 0x0139
-#define regHDP_XDP_P2P_BAR5_BASE_IDX 0
-#define regHDP_XDP_P2P_BAR6 0x013a
-#define regHDP_XDP_P2P_BAR6_BASE_IDX 0
-#define regHDP_XDP_P2P_BAR7 0x013b
-#define regHDP_XDP_P2P_BAR7_BASE_IDX 0
-#define regHDP_XDP_FLUSH_ARMED_STS 0x013c
-#define regHDP_XDP_FLUSH_ARMED_STS_BASE_IDX 0
-#define regHDP_XDP_FLUSH_CNTR0_STS 0x013d
-#define regHDP_XDP_FLUSH_CNTR0_STS_BASE_IDX 0
-#define regHDP_XDP_BUSY_STS 0x013e
-#define regHDP_XDP_BUSY_STS_BASE_IDX 0
-#define regHDP_XDP_STICKY 0x013f
-#define regHDP_XDP_STICKY_BASE_IDX 0
-#define regHDP_XDP_CHKN 0x0140
-#define regHDP_XDP_CHKN_BASE_IDX 0
-#define regHDP_XDP_BARS_ADDR_39_36 0x0144
-#define regHDP_XDP_BARS_ADDR_39_36_BASE_IDX 0
-#define regHDP_XDP_MC_VM_FB_LOCATION_BASE 0x0145
-#define regHDP_XDP_MC_VM_FB_LOCATION_BASE_BASE_IDX 0
-#define regHDP_XDP_GPU_IOV_VIOLATION_LOG 0x0148
-#define regHDP_XDP_GPU_IOV_VIOLATION_LOG_BASE_IDX 0
-#define regHDP_XDP_GPU_IOV_VIOLATION_LOG2 0x0149
-#define regHDP_XDP_GPU_IOV_VIOLATION_LOG2_BASE_IDX 0
-#define regHDP_XDP_MMHUB_ERROR 0x014a
-#define regHDP_XDP_MMHUB_ERROR_BASE_IDX 0
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_4_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_4_2_sh_mask.h
deleted file mode 100644
index 3ccd27979..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_4_2_sh_mask.h
+++ /dev/null
@@ -1,663 +0,0 @@
-/*
- * Copyright 2022 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef _hdp_4_4_2_SH_MASK_HEADER
-#define _hdp_4_4_2_SH_MASK_HEADER
-
-
-// addressBlock: aid_hdp_hdpdec
-//HDP_MMHUB_TLVL
-#define HDP_MMHUB_TLVL__HDP_WR_TLVL__SHIFT 0x0
-#define HDP_MMHUB_TLVL__HDP_RD_TLVL__SHIFT 0x4
-#define HDP_MMHUB_TLVL__XDP_WR_TLVL__SHIFT 0x8
-#define HDP_MMHUB_TLVL__XDP_RD_TLVL__SHIFT 0xc
-#define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL__SHIFT 0x10
-#define HDP_MMHUB_TLVL__HDP_WR_TLVL_MASK 0x0000000FL
-#define HDP_MMHUB_TLVL__HDP_RD_TLVL_MASK 0x000000F0L
-#define HDP_MMHUB_TLVL__XDP_WR_TLVL_MASK 0x00000F00L
-#define HDP_MMHUB_TLVL__XDP_RD_TLVL_MASK 0x0000F000L
-#define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL_MASK 0x000F0000L
-//HDP_MMHUB_UNITID
-#define HDP_MMHUB_UNITID__HDP_UNITID__SHIFT 0x0
-#define HDP_MMHUB_UNITID__XDP_UNITID__SHIFT 0x8
-#define HDP_MMHUB_UNITID__XDP_MBX_UNITID__SHIFT 0x10
-#define HDP_MMHUB_UNITID__HDP_UNITID_MASK 0x0000003FL
-#define HDP_MMHUB_UNITID__XDP_UNITID_MASK 0x00003F00L
-#define HDP_MMHUB_UNITID__XDP_MBX_UNITID_MASK 0x003F0000L
-//HDP_NONSURFACE_BASE
-#define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8__SHIFT 0x0
-#define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8_MASK 0xFFFFFFFFL
-//HDP_NONSURFACE_INFO
-#define HDP_NONSURFACE_INFO__NONSURF_SWAP__SHIFT 0x4
-#define HDP_NONSURFACE_INFO__NONSURF_VMID__SHIFT 0x8
-#define HDP_NONSURFACE_INFO__NONSURF_SWAP_MASK 0x00000030L
-#define HDP_NONSURFACE_INFO__NONSURF_VMID_MASK 0x00000F00L
-//HDP_NONSURFACE_BASE_HI
-#define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40__SHIFT 0x0
-#define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40_MASK 0x000000FFL
-//HDP_SURFACE_WRITE_FLAGS
-#define HDP_SURFACE_WRITE_FLAGS__SURF0_WRITE_FLAG__SHIFT 0x0
-#define HDP_SURFACE_WRITE_FLAGS__SURF1_WRITE_FLAG__SHIFT 0x1
-#define HDP_SURFACE_WRITE_FLAGS__SURF0_WRITE_FLAG_MASK 0x00000001L
-#define HDP_SURFACE_WRITE_FLAGS__SURF1_WRITE_FLAG_MASK 0x00000002L
-//HDP_SURFACE_READ_FLAGS
-#define HDP_SURFACE_READ_FLAGS__SURF0_READ_FLAG__SHIFT 0x0
-#define HDP_SURFACE_READ_FLAGS__SURF1_READ_FLAG__SHIFT 0x1
-#define HDP_SURFACE_READ_FLAGS__SURF0_READ_FLAG_MASK 0x00000001L
-#define HDP_SURFACE_READ_FLAGS__SURF1_READ_FLAG_MASK 0x00000002L
-//HDP_SURFACE_WRITE_FLAGS_CLR
-#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF0_WRITE_FLAG_CLR__SHIFT 0x0
-#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF1_WRITE_FLAG_CLR__SHIFT 0x1
-#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF0_WRITE_FLAG_CLR_MASK 0x00000001L
-#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF1_WRITE_FLAG_CLR_MASK 0x00000002L
-//HDP_SURFACE_READ_FLAGS_CLR
-#define HDP_SURFACE_READ_FLAGS_CLR__SURF0_READ_FLAG_CLR__SHIFT 0x0
-#define HDP_SURFACE_READ_FLAGS_CLR__SURF1_READ_FLAG_CLR__SHIFT 0x1
-#define HDP_SURFACE_READ_FLAGS_CLR__SURF0_READ_FLAG_CLR_MASK 0x00000001L
-#define HDP_SURFACE_READ_FLAGS_CLR__SURF1_READ_FLAG_CLR_MASK 0x00000002L
-//HDP_NONSURF_FLAGS
-#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0
-#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1
-#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x00000001L
-#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x00000002L
-//HDP_NONSURF_FLAGS_CLR
-#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0
-#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1
-#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x00000001L
-#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x00000002L
-//HDP_HOST_PATH_CNTL
-#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9
-#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb
-#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG__SHIFT 0x12
-#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13
-#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15
-#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN__SHIFT 0x16
-#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d
-#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x00000600L
-#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x00001800L
-#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG_MASK 0x00040000L
-#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x00180000L
-#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x00200000L
-#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN_MASK 0x00400000L
-#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000L
-//HDP_SW_SEMAPHORE
-#define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0
-#define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xFFFFFFFFL
-//HDP_DEBUG0
-#define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x0
-#define HDP_DEBUG0__HDP_DEBUG_MASK 0xFFFFFFFFL
-//HDP_LAST_SURFACE_HIT
-#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0
-#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x00000003L
-//HDP_OUTSTANDING_REQ
-#define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0
-#define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8
-#define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0x000000FFL
-#define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0x0000FF00L
-//HDP_MISC_CNTL
-#define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL__SHIFT 0x2
-#define HDP_MISC_CNTL__ATOMIC_BUFFER_PROTECT_ENABLE__SHIFT 0x4
-#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5
-#define HDP_MISC_CNTL__RAW_ADDR_CAM_ENABLE__SHIFT 0x7
-#define HDP_MISC_CNTL__MMHUB_EARLY_WRACK_ENABLE__SHIFT 0x8
-#define HDP_MISC_CNTL__EARLY_WRACK_MISSING_PROTECT_ENABLE__SHIFT 0x9
-#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb
-#define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY__SHIFT 0xc
-#define HDP_MISC_CNTL__READ_BUFFER_WATERMARK__SHIFT 0xe
-#define HDP_MISC_CNTL__SRAM_ECC_ENABLE__SHIFT 0x14
-#define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15
-#define HDP_MISC_CNTL__ATOMIC_FED_ENABLE__SHIFT 0x16
-#define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE__SHIFT 0x18
-#define HDP_MISC_CNTL__HDP_MMHUB_PENDING_WR_TAG_CHECK__SHIFT 0x1a
-#define HDP_MISC_CNTL__XDP_MMHUB_PENDING_WR_TAG_CHECK__SHIFT 0x1b
-#define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE__SHIFT 0x1e
-#define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL_MASK 0x0000000CL
-#define HDP_MISC_CNTL__ATOMIC_BUFFER_PROTECT_ENABLE_MASK 0x00000010L
-#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x00000020L
-#define HDP_MISC_CNTL__RAW_ADDR_CAM_ENABLE_MASK 0x00000080L
-#define HDP_MISC_CNTL__MMHUB_EARLY_WRACK_ENABLE_MASK 0x00000100L
-#define HDP_MISC_CNTL__EARLY_WRACK_MISSING_PROTECT_ENABLE_MASK 0x00000200L
-#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x00000800L
-#define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY_MASK 0x00003000L
-#define HDP_MISC_CNTL__READ_BUFFER_WATERMARK_MASK 0x0000C000L
-#define HDP_MISC_CNTL__SRAM_ECC_ENABLE_MASK 0x00100000L
-#define HDP_MISC_CNTL__FED_ENABLE_MASK 0x00200000L
-#define HDP_MISC_CNTL__ATOMIC_FED_ENABLE_MASK 0x00400000L
-#define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE_MASK 0x01000000L
-#define HDP_MISC_CNTL__HDP_MMHUB_PENDING_WR_TAG_CHECK_MASK 0x04000000L
-#define HDP_MISC_CNTL__XDP_MMHUB_PENDING_WR_TAG_CHECK_MASK 0x08000000L
-#define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE_MASK 0x40000000L
-//HDP_MEM_POWER_CTRL
-#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN__SHIFT 0x0
-#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN__SHIFT 0x1
-#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN__SHIFT 0x2
-#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN__SHIFT 0x3
-#define HDP_MEM_POWER_CTRL__IPH_MEM_IDLE_HYSTERESIS__SHIFT 0x4
-#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x8
-#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DOWN_LS_ENTER_DELAY__SHIFT 0xe
-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN__SHIFT 0x10
-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN__SHIFT 0x11
-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DS_EN__SHIFT 0x12
-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_SD_EN__SHIFT 0x13
-#define HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS__SHIFT 0x14
-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x18
-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DOWN_LS_ENTER_DELAY__SHIFT 0x1e
-#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L
-#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L
-#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK 0x00000004L
-#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK 0x00000008L
-#define HDP_MEM_POWER_CTRL__IPH_MEM_IDLE_HYSTERESIS_MASK 0x00000070L
-#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_UP_RECOVER_DELAY_MASK 0x00003F00L
-#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DOWN_LS_ENTER_DELAY_MASK 0x0000C000L
-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L
-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DS_EN_MASK 0x00040000L
-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_SD_EN_MASK 0x00080000L
-#define HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS_MASK 0x00700000L
-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_UP_RECOVER_DELAY_MASK 0x3F000000L
-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DOWN_LS_ENTER_DELAY_MASK 0xC0000000L
-//HDP_MMHUB_CNTL
-#define HDP_MMHUB_CNTL__HDP_MMHUB_RO__SHIFT 0x0
-#define HDP_MMHUB_CNTL__HDP_MMHUB_GCC__SHIFT 0x1
-#define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP__SHIFT 0x2
-#define HDP_MMHUB_CNTL__HDP_MMHUB_RO_OVERRIDE__SHIFT 0x4
-#define HDP_MMHUB_CNTL__HDP_MMHUB_GCC_OVERRIDE__SHIFT 0x5
-#define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP_OVERRIDE__SHIFT 0x6
-#define HDP_MMHUB_CNTL__HDP_MMHUB_RO_MASK 0x00000001L
-#define HDP_MMHUB_CNTL__HDP_MMHUB_GCC_MASK 0x00000002L
-#define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP_MASK 0x00000004L
-#define HDP_MMHUB_CNTL__HDP_MMHUB_RO_OVERRIDE_MASK 0x00000010L
-#define HDP_MMHUB_CNTL__HDP_MMHUB_GCC_OVERRIDE_MASK 0x00000020L
-#define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP_OVERRIDE_MASK 0x00000040L
-//HDP_EDC_CNT
-#define HDP_EDC_CNT__MEM0_SED_COUNT__SHIFT 0x0
-#define HDP_EDC_CNT__MEM0_SED_COUNT_MASK 0x00000003L
-//HDP_VERSION
-#define HDP_VERSION__MINVER__SHIFT 0x0
-#define HDP_VERSION__MAJVER__SHIFT 0x8
-#define HDP_VERSION__REV__SHIFT 0x10
-#define HDP_VERSION__MINVER_MASK 0x000000FFL
-#define HDP_VERSION__MAJVER_MASK 0x0000FF00L
-#define HDP_VERSION__REV_MASK 0x00FF0000L
-//HDP_CLK_CNTL
-#define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x0
-#define HDP_CLK_CNTL__REG_WAKE_DYN_CLK__SHIFT 0x4
-#define HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x1a
-#define HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x1b
-#define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE__SHIFT 0x1c
-#define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1d
-#define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE__SHIFT 0x1e
-#define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE__SHIFT 0x1f
-#define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT_MASK 0x0000000FL
-#define HDP_CLK_CNTL__REG_WAKE_DYN_CLK_MASK 0x00000010L
-#define HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK 0x04000000L
-#define HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK 0x08000000L
-#define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK 0x10000000L
-#define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK 0x20000000L
-#define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK 0x40000000L
-#define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK 0x80000000L
-//HDP_MEMIO_CNTL
-#define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0
-#define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1
-#define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2
-#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6
-#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7
-#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8
-#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe
-#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf
-#define HDP_MEMIO_CNTL__MEMIO_VF__SHIFT 0x10
-#define HDP_MEMIO_CNTL__MEMIO_VFID__SHIFT 0x11
-#define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x00000001L
-#define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x00000002L
-#define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x0000003CL
-#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x00000040L
-#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x00000080L
-#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x00003F00L
-#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x00004000L
-#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x00008000L
-#define HDP_MEMIO_CNTL__MEMIO_VF_MASK 0x00010000L
-#define HDP_MEMIO_CNTL__MEMIO_VFID_MASK 0x003E0000L
-//HDP_MEMIO_ADDR
-#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0
-#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xFFFFFFFFL
-//HDP_MEMIO_STATUS
-#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0
-#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1
-#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2
-#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3
-#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x00000001L
-#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x00000002L
-#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x00000004L
-#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x00000008L
-//HDP_MEMIO_WR_DATA
-#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0
-#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xFFFFFFFFL
-//HDP_MEMIO_RD_DATA
-#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0
-#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xFFFFFFFFL
-//HDP_XDP_DIRECT2HDP_FIRST
-#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0
-#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_FLUSH
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0x0000000FL
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0x000000F0L
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x00000700L
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0x0000F800L
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x00010000L
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x00040000L
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x00080000L
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x00100000L
-//HDP_XDP_D2H_BAR_UPDATE
-#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0
-#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10
-#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14
-#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0x0000FFFFL
-#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0x000F0000L
-#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x00700000L
-//HDP_XDP_D2H_RSVD_3
-#define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_4
-#define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_5
-#define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_6
-#define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_7
-#define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_8
-#define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_9
-#define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_10
-#define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_11
-#define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_12
-#define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_13
-#define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_14
-#define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_15
-#define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_16
-#define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_17
-#define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_18
-#define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_19
-#define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_20
-#define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_21
-#define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_22
-#define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_23
-#define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_24
-#define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_25
-#define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_26
-#define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_27
-#define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_28
-#define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_29
-#define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_30
-#define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_31
-#define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_32
-#define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_33
-#define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_34
-#define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0
-#define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_DIRECT2HDP_LAST
-#define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0
-#define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xFFFFFFFFL
-//HDP_XDP_P2P_BAR_CFG
-#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0
-#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4
-#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0x0000000FL
-#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x00000030L
-//HDP_XDP_P2P_MBX_OFFSET
-#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0
-#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x0001FFFFL
-//HDP_XDP_P2P_MBX_ADDR0
-#define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0
-#define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19__SHIFT 0x3
-#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x14
-#define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40__SHIFT 0x18
-#define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x00000001L
-#define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19_MASK 0x000FFFF8L
-#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x00F00000L
-#define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40_MASK 0xFF000000L
-//HDP_XDP_P2P_MBX_ADDR1
-#define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0
-#define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19__SHIFT 0x3
-#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x14
-#define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40__SHIFT 0x18
-#define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x00000001L
-#define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19_MASK 0x000FFFF8L
-#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x00F00000L
-#define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40_MASK 0xFF000000L
-//HDP_XDP_P2P_MBX_ADDR2
-#define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0
-#define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19__SHIFT 0x3
-#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x14
-#define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40__SHIFT 0x18
-#define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x00000001L
-#define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19_MASK 0x000FFFF8L
-#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x00F00000L
-#define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40_MASK 0xFF000000L
-//HDP_XDP_P2P_MBX_ADDR3
-#define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0
-#define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19__SHIFT 0x3
-#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x14
-#define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40__SHIFT 0x18
-#define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x00000001L
-#define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19_MASK 0x000FFFF8L
-#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x00F00000L
-#define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40_MASK 0xFF000000L
-//HDP_XDP_P2P_MBX_ADDR4
-#define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0
-#define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19__SHIFT 0x3
-#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x14
-#define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40__SHIFT 0x18
-#define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x00000001L
-#define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19_MASK 0x000FFFF8L
-#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x00F00000L
-#define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40_MASK 0xFF000000L
-//HDP_XDP_P2P_MBX_ADDR5
-#define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0
-#define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19__SHIFT 0x3
-#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x14
-#define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40__SHIFT 0x18
-#define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x00000001L
-#define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19_MASK 0x000FFFF8L
-#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x00F00000L
-#define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40_MASK 0xFF000000L
-//HDP_XDP_P2P_MBX_ADDR6
-#define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0
-#define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19__SHIFT 0x3
-#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x14
-#define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40__SHIFT 0x18
-#define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x00000001L
-#define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19_MASK 0x000FFFF8L
-#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x00F00000L
-#define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40_MASK 0xFF000000L
-//HDP_XDP_HDP_MBX_MC_CFG
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS__SHIFT 0x0
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x4
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x8
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO__SHIFT 0xc
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC__SHIFT 0xd
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP__SHIFT 0xe
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS_MASK 0x0000000FL
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x00000030L
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0x00000F00L
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO_MASK 0x00001000L
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC_MASK 0x00002000L
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP_MASK 0x00004000L
-//HDP_XDP_HDP_MC_CFG
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP_OVERRIDE__SHIFT 0x0
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC_OVERRIDE__SHIFT 0x1
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO_OVERRIDE__SHIFT 0x2
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP__SHIFT 0x3
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP__SHIFT 0x4
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID__SHIFT 0x8
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO__SHIFT 0xc
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC__SHIFT 0xd
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP_OVERRIDE_MASK 0x00000001L
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC_OVERRIDE_MASK 0x00000002L
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO_OVERRIDE_MASK 0x00000004L
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP_MASK 0x00000008L
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP_MASK 0x00000030L
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID_MASK 0x00000F00L
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO_MASK 0x00001000L
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC_MASK 0x00002000L
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0x000FC000L
-//HDP_XDP_HST_CFG
-#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0
-#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1
-#define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN__SHIFT 0x3
-#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN__SHIFT 0x4
-#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG__SHIFT 0x5
-#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x00000001L
-#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x00000006L
-#define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN_MASK 0x00000008L
-#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN_MASK 0x00000010L
-#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG_MASK 0x00000020L
-//HDP_XDP_HDP_IPH_CFG
-#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x0
-#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x6
-#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc
-#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd
-#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x0000003FL
-#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0x00000FC0L
-#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x00001000L
-#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x00002000L
-//HDP_XDP_P2P_BAR0
-#define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0
-#define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10
-#define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14
-#define HDP_XDP_P2P_BAR0__ADDR_MASK 0x0000FFFFL
-#define HDP_XDP_P2P_BAR0__FLUSH_MASK 0x000F0000L
-#define HDP_XDP_P2P_BAR0__VALID_MASK 0x00100000L
-//HDP_XDP_P2P_BAR1
-#define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0
-#define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10
-#define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14
-#define HDP_XDP_P2P_BAR1__ADDR_MASK 0x0000FFFFL
-#define HDP_XDP_P2P_BAR1__FLUSH_MASK 0x000F0000L
-#define HDP_XDP_P2P_BAR1__VALID_MASK 0x00100000L
-//HDP_XDP_P2P_BAR2
-#define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0
-#define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10
-#define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14
-#define HDP_XDP_P2P_BAR2__ADDR_MASK 0x0000FFFFL
-#define HDP_XDP_P2P_BAR2__FLUSH_MASK 0x000F0000L
-#define HDP_XDP_P2P_BAR2__VALID_MASK 0x00100000L
-//HDP_XDP_P2P_BAR3
-#define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0
-#define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10
-#define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14
-#define HDP_XDP_P2P_BAR3__ADDR_MASK 0x0000FFFFL
-#define HDP_XDP_P2P_BAR3__FLUSH_MASK 0x000F0000L
-#define HDP_XDP_P2P_BAR3__VALID_MASK 0x00100000L
-//HDP_XDP_P2P_BAR4
-#define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0
-#define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10
-#define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14
-#define HDP_XDP_P2P_BAR4__ADDR_MASK 0x0000FFFFL
-#define HDP_XDP_P2P_BAR4__FLUSH_MASK 0x000F0000L
-#define HDP_XDP_P2P_BAR4__VALID_MASK 0x00100000L
-//HDP_XDP_P2P_BAR5
-#define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0
-#define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10
-#define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14
-#define HDP_XDP_P2P_BAR5__ADDR_MASK 0x0000FFFFL
-#define HDP_XDP_P2P_BAR5__FLUSH_MASK 0x000F0000L
-#define HDP_XDP_P2P_BAR5__VALID_MASK 0x00100000L
-//HDP_XDP_P2P_BAR6
-#define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0
-#define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10
-#define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14
-#define HDP_XDP_P2P_BAR6__ADDR_MASK 0x0000FFFFL
-#define HDP_XDP_P2P_BAR6__FLUSH_MASK 0x000F0000L
-#define HDP_XDP_P2P_BAR6__VALID_MASK 0x00100000L
-//HDP_XDP_P2P_BAR7
-#define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0
-#define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10
-#define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14
-#define HDP_XDP_P2P_BAR7__ADDR_MASK 0x0000FFFFL
-#define HDP_XDP_P2P_BAR7__FLUSH_MASK 0x000F0000L
-#define HDP_XDP_P2P_BAR7__VALID_MASK 0x00100000L
-//HDP_XDP_FLUSH_ARMED_STS
-#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0
-#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xFFFFFFFFL
-//HDP_XDP_FLUSH_CNTR0_STS
-#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0
-#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x03FFFFFFL
-//HDP_XDP_BUSY_STS
-#define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x0
-#define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x00FFFFFFL
-//HDP_XDP_STICKY
-#define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0
-#define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10
-#define HDP_XDP_STICKY__STICKY_STS_MASK 0x0000FFFFL
-#define HDP_XDP_STICKY__STICKY_W1C_MASK 0xFFFF0000L
-//HDP_XDP_CHKN
-#define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0
-#define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8
-#define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10
-#define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18
-#define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0x000000FFL
-#define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0x0000FF00L
-#define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0x00FF0000L
-#define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xFF000000L
-//HDP_XDP_BARS_ADDR_39_36
-#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0
-#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4
-#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8
-#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc
-#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10
-#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14
-#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18
-#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c
-#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0x0000000FL
-#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0x000000F0L
-#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0x00000F00L
-#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0x0000F000L
-#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0x000F0000L
-#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0x00F00000L
-#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0x0F000000L
-#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xF0000000L
-//HDP_XDP_MC_VM_FB_LOCATION_BASE
-#define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0
-#define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x03FFFFFFL
-//HDP_XDP_GPU_IOV_VIOLATION_LOG
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x12
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00040000L
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L
-//HDP_XDP_GPU_IOV_VIOLATION_LOG2
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000003FFL
-//HDP_XDP_MMHUB_ERROR
-#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01__SHIFT 0x1
-#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10__SHIFT 0x2
-#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11__SHIFT 0x3
-#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_FED__SHIFT 0x4
-#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01__SHIFT 0x5
-#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10__SHIFT 0x6
-#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11__SHIFT 0x7
-#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01__SHIFT 0x9
-#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10__SHIFT 0xa
-#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11__SHIFT 0xb
-#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_FED__SHIFT 0xc
-#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01__SHIFT 0xd
-#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10__SHIFT 0xe
-#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11__SHIFT 0xf
-#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01__SHIFT 0x11
-#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10__SHIFT 0x12
-#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11__SHIFT 0x13
-#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01__SHIFT 0x15
-#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10__SHIFT 0x16
-#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11__SHIFT 0x17
-#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01_MASK 0x00000002L
-#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10_MASK 0x00000004L
-#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11_MASK 0x00000008L
-#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_FED_MASK 0x00000010L
-#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01_MASK 0x00000020L
-#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10_MASK 0x00000040L
-#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11_MASK 0x00000080L
-#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01_MASK 0x00000200L
-#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10_MASK 0x00000400L
-#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11_MASK 0x00000800L
-#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_FED_MASK 0x00001000L
-#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01_MASK 0x00002000L
-#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10_MASK 0x00004000L
-#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11_MASK 0x00008000L
-#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01_MASK 0x00020000L
-#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10_MASK 0x00040000L
-#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11_MASK 0x00080000L
-#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01_MASK 0x00200000L
-#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10_MASK 0x00400000L
-#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11_MASK 0x00800000L
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_offset.h
deleted file mode 100644
index 904ae530a..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_offset.h
+++ /dev/null
@@ -1,1991 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _mmhub_9_3_0_OFFSET_HEADER
-#define _mmhub_9_3_0_OFFSET_HEADER
-
-
-
-// addressBlock: mmhub_dagbdec
-// base address: 0x68000
-#define mmDAGB0_RDCLI0 0x0000
-#define mmDAGB0_RDCLI0_BASE_IDX 0
-#define mmDAGB0_RDCLI1 0x0001
-#define mmDAGB0_RDCLI1_BASE_IDX 0
-#define mmDAGB0_RDCLI2 0x0002
-#define mmDAGB0_RDCLI2_BASE_IDX 0
-#define mmDAGB0_RDCLI3 0x0003
-#define mmDAGB0_RDCLI3_BASE_IDX 0
-#define mmDAGB0_RDCLI4 0x0004
-#define mmDAGB0_RDCLI4_BASE_IDX 0
-#define mmDAGB0_RDCLI5 0x0005
-#define mmDAGB0_RDCLI5_BASE_IDX 0
-#define mmDAGB0_RDCLI6 0x0006
-#define mmDAGB0_RDCLI6_BASE_IDX 0
-#define mmDAGB0_RDCLI7 0x0007
-#define mmDAGB0_RDCLI7_BASE_IDX 0
-#define mmDAGB0_RDCLI8 0x0008
-#define mmDAGB0_RDCLI8_BASE_IDX 0
-#define mmDAGB0_RDCLI9 0x0009
-#define mmDAGB0_RDCLI9_BASE_IDX 0
-#define mmDAGB0_RDCLI10 0x000a
-#define mmDAGB0_RDCLI10_BASE_IDX 0
-#define mmDAGB0_RDCLI11 0x000b
-#define mmDAGB0_RDCLI11_BASE_IDX 0
-#define mmDAGB0_RDCLI12 0x000c
-#define mmDAGB0_RDCLI12_BASE_IDX 0
-#define mmDAGB0_RDCLI13 0x000d
-#define mmDAGB0_RDCLI13_BASE_IDX 0
-#define mmDAGB0_RDCLI14 0x000e
-#define mmDAGB0_RDCLI14_BASE_IDX 0
-#define mmDAGB0_RDCLI15 0x000f
-#define mmDAGB0_RDCLI15_BASE_IDX 0
-#define mmDAGB0_RD_CNTL 0x0010
-#define mmDAGB0_RD_CNTL_BASE_IDX 0
-#define mmDAGB0_RD_GMI_CNTL 0x0011
-#define mmDAGB0_RD_GMI_CNTL_BASE_IDX 0
-#define mmDAGB0_RD_ADDR_DAGB 0x0012
-#define mmDAGB0_RD_ADDR_DAGB_BASE_IDX 0
-#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST 0x0013
-#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
-#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 0x0014
-#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
-#define mmDAGB0_RD_CGTT_CLK_CTRL 0x0015
-#define mmDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 0
-#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x0016
-#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0
-#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL 0x0017
-#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0
-#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x0018
-#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
-#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x0019
-#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
-#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x001a
-#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
-#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x001b
-#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
-#define mmDAGB0_RD_VC0_CNTL 0x001c
-#define mmDAGB0_RD_VC0_CNTL_BASE_IDX 0
-#define mmDAGB0_RD_VC1_CNTL 0x001d
-#define mmDAGB0_RD_VC1_CNTL_BASE_IDX 0
-#define mmDAGB0_RD_VC2_CNTL 0x001e
-#define mmDAGB0_RD_VC2_CNTL_BASE_IDX 0
-#define mmDAGB0_RD_VC3_CNTL 0x001f
-#define mmDAGB0_RD_VC3_CNTL_BASE_IDX 0
-#define mmDAGB0_RD_VC4_CNTL 0x0020
-#define mmDAGB0_RD_VC4_CNTL_BASE_IDX 0
-#define mmDAGB0_RD_VC5_CNTL 0x0021
-#define mmDAGB0_RD_VC5_CNTL_BASE_IDX 0
-#define mmDAGB0_RD_VC6_CNTL 0x0022
-#define mmDAGB0_RD_VC6_CNTL_BASE_IDX 0
-#define mmDAGB0_RD_VC7_CNTL 0x0023
-#define mmDAGB0_RD_VC7_CNTL_BASE_IDX 0
-#define mmDAGB0_RD_CNTL_MISC 0x0024
-#define mmDAGB0_RD_CNTL_MISC_BASE_IDX 0
-#define mmDAGB0_RD_TLB_CREDIT 0x0025
-#define mmDAGB0_RD_TLB_CREDIT_BASE_IDX 0
-#define mmDAGB0_RDCLI_ASK_PENDING 0x0026
-#define mmDAGB0_RDCLI_ASK_PENDING_BASE_IDX 0
-#define mmDAGB0_RDCLI_GO_PENDING 0x0027
-#define mmDAGB0_RDCLI_GO_PENDING_BASE_IDX 0
-#define mmDAGB0_RDCLI_GBLSEND_PENDING 0x0028
-#define mmDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX 0
-#define mmDAGB0_RDCLI_TLB_PENDING 0x0029
-#define mmDAGB0_RDCLI_TLB_PENDING_BASE_IDX 0
-#define mmDAGB0_RDCLI_OARB_PENDING 0x002a
-#define mmDAGB0_RDCLI_OARB_PENDING_BASE_IDX 0
-#define mmDAGB0_RDCLI_OSD_PENDING 0x002b
-#define mmDAGB0_RDCLI_OSD_PENDING_BASE_IDX 0
-#define mmDAGB0_WRCLI0 0x002c
-#define mmDAGB0_WRCLI0_BASE_IDX 0
-#define mmDAGB0_WRCLI1 0x002d
-#define mmDAGB0_WRCLI1_BASE_IDX 0
-#define mmDAGB0_WRCLI2 0x002e
-#define mmDAGB0_WRCLI2_BASE_IDX 0
-#define mmDAGB0_WRCLI3 0x002f
-#define mmDAGB0_WRCLI3_BASE_IDX 0
-#define mmDAGB0_WRCLI4 0x0030
-#define mmDAGB0_WRCLI4_BASE_IDX 0
-#define mmDAGB0_WRCLI5 0x0031
-#define mmDAGB0_WRCLI5_BASE_IDX 0
-#define mmDAGB0_WRCLI6 0x0032
-#define mmDAGB0_WRCLI6_BASE_IDX 0
-#define mmDAGB0_WRCLI7 0x0033
-#define mmDAGB0_WRCLI7_BASE_IDX 0
-#define mmDAGB0_WRCLI8 0x0034
-#define mmDAGB0_WRCLI8_BASE_IDX 0
-#define mmDAGB0_WRCLI9 0x0035
-#define mmDAGB0_WRCLI9_BASE_IDX 0
-#define mmDAGB0_WRCLI10 0x0036
-#define mmDAGB0_WRCLI10_BASE_IDX 0
-#define mmDAGB0_WRCLI11 0x0037
-#define mmDAGB0_WRCLI11_BASE_IDX 0
-#define mmDAGB0_WRCLI12 0x0038
-#define mmDAGB0_WRCLI12_BASE_IDX 0
-#define mmDAGB0_WRCLI13 0x0039
-#define mmDAGB0_WRCLI13_BASE_IDX 0
-#define mmDAGB0_WRCLI14 0x003a
-#define mmDAGB0_WRCLI14_BASE_IDX 0
-#define mmDAGB0_WRCLI15 0x003b
-#define mmDAGB0_WRCLI15_BASE_IDX 0
-#define mmDAGB0_WR_CNTL 0x003c
-#define mmDAGB0_WR_CNTL_BASE_IDX 0
-#define mmDAGB0_WR_GMI_CNTL 0x003d
-#define mmDAGB0_WR_GMI_CNTL_BASE_IDX 0
-#define mmDAGB0_WR_ADDR_DAGB 0x003e
-#define mmDAGB0_WR_ADDR_DAGB_BASE_IDX 0
-#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST 0x003f
-#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
-#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 0x0040
-#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
-#define mmDAGB0_WR_CGTT_CLK_CTRL 0x0041
-#define mmDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX 0
-#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0x0042
-#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0
-#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL 0x0043
-#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0
-#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0 0x0044
-#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
-#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0x0045
-#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
-#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1 0x0046
-#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
-#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0x0047
-#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
-#define mmDAGB0_WR_DATA_DAGB 0x0048
-#define mmDAGB0_WR_DATA_DAGB_BASE_IDX 0
-#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0 0x0049
-#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0
-#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0x004a
-#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0
-#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1 0x004b
-#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0
-#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0x004c
-#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0
-#define mmDAGB0_WR_VC0_CNTL 0x004d
-#define mmDAGB0_WR_VC0_CNTL_BASE_IDX 0
-#define mmDAGB0_WR_VC1_CNTL 0x004e
-#define mmDAGB0_WR_VC1_CNTL_BASE_IDX 0
-#define mmDAGB0_WR_VC2_CNTL 0x004f
-#define mmDAGB0_WR_VC2_CNTL_BASE_IDX 0
-#define mmDAGB0_WR_VC3_CNTL 0x0050
-#define mmDAGB0_WR_VC3_CNTL_BASE_IDX 0
-#define mmDAGB0_WR_VC4_CNTL 0x0051
-#define mmDAGB0_WR_VC4_CNTL_BASE_IDX 0
-#define mmDAGB0_WR_VC5_CNTL 0x0052
-#define mmDAGB0_WR_VC5_CNTL_BASE_IDX 0
-#define mmDAGB0_WR_VC6_CNTL 0x0053
-#define mmDAGB0_WR_VC6_CNTL_BASE_IDX 0
-#define mmDAGB0_WR_VC7_CNTL 0x0054
-#define mmDAGB0_WR_VC7_CNTL_BASE_IDX 0
-#define mmDAGB0_WR_CNTL_MISC 0x0055
-#define mmDAGB0_WR_CNTL_MISC_BASE_IDX 0
-#define mmDAGB0_WR_TLB_CREDIT 0x0056
-#define mmDAGB0_WR_TLB_CREDIT_BASE_IDX 0
-#define mmDAGB0_WR_DATA_CREDIT 0x0057
-#define mmDAGB0_WR_DATA_CREDIT_BASE_IDX 0
-#define mmDAGB0_WR_MISC_CREDIT 0x0058
-#define mmDAGB0_WR_MISC_CREDIT_BASE_IDX 0
-#define mmDAGB0_WRCLI_ASK_PENDING 0x0059
-#define mmDAGB0_WRCLI_ASK_PENDING_BASE_IDX 0
-#define mmDAGB0_WRCLI_GO_PENDING 0x005a
-#define mmDAGB0_WRCLI_GO_PENDING_BASE_IDX 0
-#define mmDAGB0_WRCLI_GBLSEND_PENDING 0x005b
-#define mmDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX 0
-#define mmDAGB0_WRCLI_TLB_PENDING 0x005c
-#define mmDAGB0_WRCLI_TLB_PENDING_BASE_IDX 0
-#define mmDAGB0_WRCLI_OARB_PENDING 0x005d
-#define mmDAGB0_WRCLI_OARB_PENDING_BASE_IDX 0
-#define mmDAGB0_WRCLI_OSD_PENDING 0x005e
-#define mmDAGB0_WRCLI_OSD_PENDING_BASE_IDX 0
-#define mmDAGB0_WRCLI_DBUS_ASK_PENDING 0x005f
-#define mmDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0
-#define mmDAGB0_WRCLI_DBUS_GO_PENDING 0x0060
-#define mmDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX 0
-#define mmDAGB0_DAGB_DLY 0x0061
-#define mmDAGB0_DAGB_DLY_BASE_IDX 0
-#define mmDAGB0_CNTL_MISC 0x0062
-#define mmDAGB0_CNTL_MISC_BASE_IDX 0
-#define mmDAGB0_CNTL_MISC2 0x0063
-#define mmDAGB0_CNTL_MISC2_BASE_IDX 0
-#define mmDAGB0_FIFO_EMPTY 0x0064
-#define mmDAGB0_FIFO_EMPTY_BASE_IDX 0
-#define mmDAGB0_FIFO_FULL 0x0065
-#define mmDAGB0_FIFO_FULL_BASE_IDX 0
-#define mmDAGB0_WR_CREDITS_FULL 0x0066
-#define mmDAGB0_WR_CREDITS_FULL_BASE_IDX 0
-#define mmDAGB0_RD_CREDITS_FULL 0x0067
-#define mmDAGB0_RD_CREDITS_FULL_BASE_IDX 0
-#define mmDAGB0_PERFCOUNTER_LO 0x0068
-#define mmDAGB0_PERFCOUNTER_LO_BASE_IDX 0
-#define mmDAGB0_PERFCOUNTER_HI 0x0069
-#define mmDAGB0_PERFCOUNTER_HI_BASE_IDX 0
-#define mmDAGB0_PERFCOUNTER0_CFG 0x006a
-#define mmDAGB0_PERFCOUNTER0_CFG_BASE_IDX 0
-#define mmDAGB0_PERFCOUNTER1_CFG 0x006b
-#define mmDAGB0_PERFCOUNTER1_CFG_BASE_IDX 0
-#define mmDAGB0_PERFCOUNTER2_CFG 0x006c
-#define mmDAGB0_PERFCOUNTER2_CFG_BASE_IDX 0
-#define mmDAGB0_PERFCOUNTER_RSLT_CNTL 0x006d
-#define mmDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
-#define mmDAGB0_RESERVE0 0x006e
-#define mmDAGB0_RESERVE0_BASE_IDX 0
-#define mmDAGB0_RESERVE1 0x006f
-#define mmDAGB0_RESERVE1_BASE_IDX 0
-#define mmDAGB0_RESERVE2 0x0070
-#define mmDAGB0_RESERVE2_BASE_IDX 0
-#define mmDAGB0_RESERVE3 0x0071
-#define mmDAGB0_RESERVE3_BASE_IDX 0
-#define mmDAGB0_RESERVE4 0x0072
-#define mmDAGB0_RESERVE4_BASE_IDX 0
-#define mmDAGB0_RESERVE5 0x0073
-#define mmDAGB0_RESERVE5_BASE_IDX 0
-#define mmDAGB0_RESERVE6 0x0074
-#define mmDAGB0_RESERVE6_BASE_IDX 0
-#define mmDAGB0_RESERVE7 0x0075
-#define mmDAGB0_RESERVE7_BASE_IDX 0
-#define mmDAGB0_RESERVE8 0x0076
-#define mmDAGB0_RESERVE8_BASE_IDX 0
-#define mmDAGB0_RESERVE9 0x0077
-#define mmDAGB0_RESERVE9_BASE_IDX 0
-#define mmDAGB0_RESERVE10 0x0078
-#define mmDAGB0_RESERVE10_BASE_IDX 0
-#define mmDAGB0_RESERVE11 0x0079
-#define mmDAGB0_RESERVE11_BASE_IDX 0
-#define mmDAGB0_RESERVE12 0x007a
-#define mmDAGB0_RESERVE12_BASE_IDX 0
-#define mmDAGB0_RESERVE13 0x007b
-#define mmDAGB0_RESERVE13_BASE_IDX 0
-#define mmDAGB0_RESERVE14 0x007c
-#define mmDAGB0_RESERVE14_BASE_IDX 0
-#define mmDAGB0_RESERVE15 0x007d
-#define mmDAGB0_RESERVE15_BASE_IDX 0
-#define mmDAGB0_RESERVE16 0x007e
-#define mmDAGB0_RESERVE16_BASE_IDX 0
-#define mmDAGB0_RESERVE17 0x007f
-#define mmDAGB0_RESERVE17_BASE_IDX 0
-#define mmDAGB1_RDCLI0 0x0080
-#define mmDAGB1_RDCLI0_BASE_IDX 0
-#define mmDAGB1_RDCLI1 0x0081
-#define mmDAGB1_RDCLI1_BASE_IDX 0
-#define mmDAGB1_RDCLI2 0x0082
-#define mmDAGB1_RDCLI2_BASE_IDX 0
-#define mmDAGB1_RDCLI3 0x0083
-#define mmDAGB1_RDCLI3_BASE_IDX 0
-#define mmDAGB1_RDCLI4 0x0084
-#define mmDAGB1_RDCLI4_BASE_IDX 0
-#define mmDAGB1_RDCLI5 0x0085
-#define mmDAGB1_RDCLI5_BASE_IDX 0
-#define mmDAGB1_RDCLI6 0x0086
-#define mmDAGB1_RDCLI6_BASE_IDX 0
-#define mmDAGB1_RDCLI7 0x0087
-#define mmDAGB1_RDCLI7_BASE_IDX 0
-#define mmDAGB1_RDCLI8 0x0088
-#define mmDAGB1_RDCLI8_BASE_IDX 0
-#define mmDAGB1_RDCLI9 0x0089
-#define mmDAGB1_RDCLI9_BASE_IDX 0
-#define mmDAGB1_RDCLI10 0x008a
-#define mmDAGB1_RDCLI10_BASE_IDX 0
-#define mmDAGB1_RDCLI11 0x008b
-#define mmDAGB1_RDCLI11_BASE_IDX 0
-#define mmDAGB1_RDCLI12 0x008c
-#define mmDAGB1_RDCLI12_BASE_IDX 0
-#define mmDAGB1_RDCLI13 0x008d
-#define mmDAGB1_RDCLI13_BASE_IDX 0
-#define mmDAGB1_RDCLI14 0x008e
-#define mmDAGB1_RDCLI14_BASE_IDX 0
-#define mmDAGB1_RDCLI15 0x008f
-#define mmDAGB1_RDCLI15_BASE_IDX 0
-#define mmDAGB1_RD_CNTL 0x0090
-#define mmDAGB1_RD_CNTL_BASE_IDX 0
-#define mmDAGB1_RD_GMI_CNTL 0x0091
-#define mmDAGB1_RD_GMI_CNTL_BASE_IDX 0
-#define mmDAGB1_RD_ADDR_DAGB 0x0092
-#define mmDAGB1_RD_ADDR_DAGB_BASE_IDX 0
-#define mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST 0x0093
-#define mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
-#define mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER 0x0094
-#define mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
-#define mmDAGB1_RD_CGTT_CLK_CTRL 0x0095
-#define mmDAGB1_RD_CGTT_CLK_CTRL_BASE_IDX 0
-#define mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL 0x0096
-#define mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0
-#define mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL 0x0097
-#define mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0
-#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST0 0x0098
-#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
-#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0 0x0099
-#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
-#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST1 0x009a
-#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
-#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1 0x009b
-#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
-#define mmDAGB1_RD_VC0_CNTL 0x009c
-#define mmDAGB1_RD_VC0_CNTL_BASE_IDX 0
-#define mmDAGB1_RD_VC1_CNTL 0x009d
-#define mmDAGB1_RD_VC1_CNTL_BASE_IDX 0
-#define mmDAGB1_RD_VC2_CNTL 0x009e
-#define mmDAGB1_RD_VC2_CNTL_BASE_IDX 0
-#define mmDAGB1_RD_VC3_CNTL 0x009f
-#define mmDAGB1_RD_VC3_CNTL_BASE_IDX 0
-#define mmDAGB1_RD_VC4_CNTL 0x00a0
-#define mmDAGB1_RD_VC4_CNTL_BASE_IDX 0
-#define mmDAGB1_RD_VC5_CNTL 0x00a1
-#define mmDAGB1_RD_VC5_CNTL_BASE_IDX 0
-#define mmDAGB1_RD_VC6_CNTL 0x00a2
-#define mmDAGB1_RD_VC6_CNTL_BASE_IDX 0
-#define mmDAGB1_RD_VC7_CNTL 0x00a3
-#define mmDAGB1_RD_VC7_CNTL_BASE_IDX 0
-#define mmDAGB1_RD_CNTL_MISC 0x00a4
-#define mmDAGB1_RD_CNTL_MISC_BASE_IDX 0
-#define mmDAGB1_RD_TLB_CREDIT 0x00a5
-#define mmDAGB1_RD_TLB_CREDIT_BASE_IDX 0
-#define mmDAGB1_RDCLI_ASK_PENDING 0x00a6
-#define mmDAGB1_RDCLI_ASK_PENDING_BASE_IDX 0
-#define mmDAGB1_RDCLI_GO_PENDING 0x00a7
-#define mmDAGB1_RDCLI_GO_PENDING_BASE_IDX 0
-#define mmDAGB1_RDCLI_GBLSEND_PENDING 0x00a8
-#define mmDAGB1_RDCLI_GBLSEND_PENDING_BASE_IDX 0
-#define mmDAGB1_RDCLI_TLB_PENDING 0x00a9
-#define mmDAGB1_RDCLI_TLB_PENDING_BASE_IDX 0
-#define mmDAGB1_RDCLI_OARB_PENDING 0x00aa
-#define mmDAGB1_RDCLI_OARB_PENDING_BASE_IDX 0
-#define mmDAGB1_RDCLI_OSD_PENDING 0x00ab
-#define mmDAGB1_RDCLI_OSD_PENDING_BASE_IDX 0
-#define mmDAGB1_WRCLI0 0x00ac
-#define mmDAGB1_WRCLI0_BASE_IDX 0
-#define mmDAGB1_WRCLI1 0x00ad
-#define mmDAGB1_WRCLI1_BASE_IDX 0
-#define mmDAGB1_WRCLI2 0x00ae
-#define mmDAGB1_WRCLI2_BASE_IDX 0
-#define mmDAGB1_WRCLI3 0x00af
-#define mmDAGB1_WRCLI3_BASE_IDX 0
-#define mmDAGB1_WRCLI4 0x00b0
-#define mmDAGB1_WRCLI4_BASE_IDX 0
-#define mmDAGB1_WRCLI5 0x00b1
-#define mmDAGB1_WRCLI5_BASE_IDX 0
-#define mmDAGB1_WRCLI6 0x00b2
-#define mmDAGB1_WRCLI6_BASE_IDX 0
-#define mmDAGB1_WRCLI7 0x00b3
-#define mmDAGB1_WRCLI7_BASE_IDX 0
-#define mmDAGB1_WRCLI8 0x00b4
-#define mmDAGB1_WRCLI8_BASE_IDX 0
-#define mmDAGB1_WRCLI9 0x00b5
-#define mmDAGB1_WRCLI9_BASE_IDX 0
-#define mmDAGB1_WRCLI10 0x00b6
-#define mmDAGB1_WRCLI10_BASE_IDX 0
-#define mmDAGB1_WRCLI11 0x00b7
-#define mmDAGB1_WRCLI11_BASE_IDX 0
-#define mmDAGB1_WRCLI12 0x00b8
-#define mmDAGB1_WRCLI12_BASE_IDX 0
-#define mmDAGB1_WRCLI13 0x00b9
-#define mmDAGB1_WRCLI13_BASE_IDX 0
-#define mmDAGB1_WRCLI14 0x00ba
-#define mmDAGB1_WRCLI14_BASE_IDX 0
-#define mmDAGB1_WRCLI15 0x00bb
-#define mmDAGB1_WRCLI15_BASE_IDX 0
-#define mmDAGB1_WR_CNTL 0x00bc
-#define mmDAGB1_WR_CNTL_BASE_IDX 0
-#define mmDAGB1_WR_GMI_CNTL 0x00bd
-#define mmDAGB1_WR_GMI_CNTL_BASE_IDX 0
-#define mmDAGB1_WR_ADDR_DAGB 0x00be
-#define mmDAGB1_WR_ADDR_DAGB_BASE_IDX 0
-#define mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST 0x00bf
-#define mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
-#define mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER 0x00c0
-#define mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
-#define mmDAGB1_WR_CGTT_CLK_CTRL 0x00c1
-#define mmDAGB1_WR_CGTT_CLK_CTRL_BASE_IDX 0
-#define mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL 0x00c2
-#define mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0
-#define mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL 0x00c3
-#define mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0
-#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST0 0x00c4
-#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
-#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0 0x00c5
-#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
-#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST1 0x00c6
-#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
-#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1 0x00c7
-#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
-#define mmDAGB1_WR_DATA_DAGB 0x00c8
-#define mmDAGB1_WR_DATA_DAGB_BASE_IDX 0
-#define mmDAGB1_WR_DATA_DAGB_MAX_BURST0 0x00c9
-#define mmDAGB1_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0
-#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0 0x00ca
-#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0
-#define mmDAGB1_WR_DATA_DAGB_MAX_BURST1 0x00cb
-#define mmDAGB1_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0
-#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1 0x00cc
-#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0
-#define mmDAGB1_WR_VC0_CNTL 0x00cd
-#define mmDAGB1_WR_VC0_CNTL_BASE_IDX 0
-#define mmDAGB1_WR_VC1_CNTL 0x00ce
-#define mmDAGB1_WR_VC1_CNTL_BASE_IDX 0
-#define mmDAGB1_WR_VC2_CNTL 0x00cf
-#define mmDAGB1_WR_VC2_CNTL_BASE_IDX 0
-#define mmDAGB1_WR_VC3_CNTL 0x00d0
-#define mmDAGB1_WR_VC3_CNTL_BASE_IDX 0
-#define mmDAGB1_WR_VC4_CNTL 0x00d1
-#define mmDAGB1_WR_VC4_CNTL_BASE_IDX 0
-#define mmDAGB1_WR_VC5_CNTL 0x00d2
-#define mmDAGB1_WR_VC5_CNTL_BASE_IDX 0
-#define mmDAGB1_WR_VC6_CNTL 0x00d3
-#define mmDAGB1_WR_VC6_CNTL_BASE_IDX 0
-#define mmDAGB1_WR_VC7_CNTL 0x00d4
-#define mmDAGB1_WR_VC7_CNTL_BASE_IDX 0
-#define mmDAGB1_WR_CNTL_MISC 0x00d5
-#define mmDAGB1_WR_CNTL_MISC_BASE_IDX 0
-#define mmDAGB1_WR_TLB_CREDIT 0x00d6
-#define mmDAGB1_WR_TLB_CREDIT_BASE_IDX 0
-#define mmDAGB1_WR_DATA_CREDIT 0x00d7
-#define mmDAGB1_WR_DATA_CREDIT_BASE_IDX 0
-#define mmDAGB1_WR_MISC_CREDIT 0x00d8
-#define mmDAGB1_WR_MISC_CREDIT_BASE_IDX 0
-#define mmDAGB1_WRCLI_ASK_PENDING 0x00d9
-#define mmDAGB1_WRCLI_ASK_PENDING_BASE_IDX 0
-#define mmDAGB1_WRCLI_GO_PENDING 0x00da
-#define mmDAGB1_WRCLI_GO_PENDING_BASE_IDX 0
-#define mmDAGB1_WRCLI_GBLSEND_PENDING 0x00db
-#define mmDAGB1_WRCLI_GBLSEND_PENDING_BASE_IDX 0
-#define mmDAGB1_WRCLI_TLB_PENDING 0x00dc
-#define mmDAGB1_WRCLI_TLB_PENDING_BASE_IDX 0
-#define mmDAGB1_WRCLI_OARB_PENDING 0x00dd
-#define mmDAGB1_WRCLI_OARB_PENDING_BASE_IDX 0
-#define mmDAGB1_WRCLI_OSD_PENDING 0x00de
-#define mmDAGB1_WRCLI_OSD_PENDING_BASE_IDX 0
-#define mmDAGB1_WRCLI_DBUS_ASK_PENDING 0x00df
-#define mmDAGB1_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0
-#define mmDAGB1_WRCLI_DBUS_GO_PENDING 0x00e0
-#define mmDAGB1_WRCLI_DBUS_GO_PENDING_BASE_IDX 0
-#define mmDAGB1_DAGB_DLY 0x00e1
-#define mmDAGB1_DAGB_DLY_BASE_IDX 0
-#define mmDAGB1_CNTL_MISC 0x00e2
-#define mmDAGB1_CNTL_MISC_BASE_IDX 0
-#define mmDAGB1_CNTL_MISC2 0x00e3
-#define mmDAGB1_CNTL_MISC2_BASE_IDX 0
-#define mmDAGB1_FIFO_EMPTY 0x00e4
-#define mmDAGB1_FIFO_EMPTY_BASE_IDX 0
-#define mmDAGB1_FIFO_FULL 0x00e5
-#define mmDAGB1_FIFO_FULL_BASE_IDX 0
-#define mmDAGB1_WR_CREDITS_FULL 0x00e6
-#define mmDAGB1_WR_CREDITS_FULL_BASE_IDX 0
-#define mmDAGB1_RD_CREDITS_FULL 0x00e7
-#define mmDAGB1_RD_CREDITS_FULL_BASE_IDX 0
-#define mmDAGB1_PERFCOUNTER_LO 0x00e8
-#define mmDAGB1_PERFCOUNTER_LO_BASE_IDX 0
-#define mmDAGB1_PERFCOUNTER_HI 0x00e9
-#define mmDAGB1_PERFCOUNTER_HI_BASE_IDX 0
-#define mmDAGB1_PERFCOUNTER0_CFG 0x00ea
-#define mmDAGB1_PERFCOUNTER0_CFG_BASE_IDX 0
-#define mmDAGB1_PERFCOUNTER1_CFG 0x00eb
-#define mmDAGB1_PERFCOUNTER1_CFG_BASE_IDX 0
-#define mmDAGB1_PERFCOUNTER2_CFG 0x00ec
-#define mmDAGB1_PERFCOUNTER2_CFG_BASE_IDX 0
-#define mmDAGB1_PERFCOUNTER_RSLT_CNTL 0x00ed
-#define mmDAGB1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
-#define mmDAGB1_RESERVE0 0x00ee
-#define mmDAGB1_RESERVE0_BASE_IDX 0
-#define mmDAGB1_RESERVE1 0x00ef
-#define mmDAGB1_RESERVE1_BASE_IDX 0
-#define mmDAGB1_RESERVE2 0x00f0
-#define mmDAGB1_RESERVE2_BASE_IDX 0
-#define mmDAGB1_RESERVE3 0x00f1
-#define mmDAGB1_RESERVE3_BASE_IDX 0
-#define mmDAGB1_RESERVE4 0x00f2
-#define mmDAGB1_RESERVE4_BASE_IDX 0
-#define mmDAGB1_RESERVE5 0x00f3
-#define mmDAGB1_RESERVE5_BASE_IDX 0
-#define mmDAGB1_RESERVE6 0x00f4
-#define mmDAGB1_RESERVE6_BASE_IDX 0
-#define mmDAGB1_RESERVE7 0x00f5
-#define mmDAGB1_RESERVE7_BASE_IDX 0
-#define mmDAGB1_RESERVE8 0x00f6
-#define mmDAGB1_RESERVE8_BASE_IDX 0
-#define mmDAGB1_RESERVE9 0x00f7
-#define mmDAGB1_RESERVE9_BASE_IDX 0
-#define mmDAGB1_RESERVE10 0x00f8
-#define mmDAGB1_RESERVE10_BASE_IDX 0
-#define mmDAGB1_RESERVE11 0x00f9
-#define mmDAGB1_RESERVE11_BASE_IDX 0
-#define mmDAGB1_RESERVE12 0x00fa
-#define mmDAGB1_RESERVE12_BASE_IDX 0
-#define mmDAGB1_RESERVE13 0x00fb
-#define mmDAGB1_RESERVE13_BASE_IDX 0
-#define mmDAGB1_RESERVE14 0x00fc
-#define mmDAGB1_RESERVE14_BASE_IDX 0
-#define mmDAGB1_RESERVE15 0x00fd
-#define mmDAGB1_RESERVE15_BASE_IDX 0
-#define mmDAGB1_RESERVE16 0x00fe
-#define mmDAGB1_RESERVE16_BASE_IDX 0
-#define mmDAGB1_RESERVE17 0x00ff
-#define mmDAGB1_RESERVE17_BASE_IDX 0
-
-
-// addressBlock: mmhub_ea_mmeadec
-// base address: 0x68400
-#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0 0x0100
-#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0
-#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1 0x0101
-#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0
-#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0 0x0102
-#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0
-#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1 0x0103
-#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0
-#define mmMMEA0_DRAM_RD_GRP2VC_MAP 0x0104
-#define mmMMEA0_DRAM_RD_GRP2VC_MAP_BASE_IDX 0
-#define mmMMEA0_DRAM_WR_GRP2VC_MAP 0x0105
-#define mmMMEA0_DRAM_WR_GRP2VC_MAP_BASE_IDX 0
-#define mmMMEA0_DRAM_RD_LAZY 0x0106
-#define mmMMEA0_DRAM_RD_LAZY_BASE_IDX 0
-#define mmMMEA0_DRAM_WR_LAZY 0x0107
-#define mmMMEA0_DRAM_WR_LAZY_BASE_IDX 0
-#define mmMMEA0_DRAM_RD_CAM_CNTL 0x0108
-#define mmMMEA0_DRAM_RD_CAM_CNTL_BASE_IDX 0
-#define mmMMEA0_DRAM_WR_CAM_CNTL 0x0109
-#define mmMMEA0_DRAM_WR_CAM_CNTL_BASE_IDX 0
-#define mmMMEA0_DRAM_PAGE_BURST 0x010a
-#define mmMMEA0_DRAM_PAGE_BURST_BASE_IDX 0
-#define mmMMEA0_DRAM_RD_PRI_AGE 0x010b
-#define mmMMEA0_DRAM_RD_PRI_AGE_BASE_IDX 0
-#define mmMMEA0_DRAM_WR_PRI_AGE 0x010c
-#define mmMMEA0_DRAM_WR_PRI_AGE_BASE_IDX 0
-#define mmMMEA0_DRAM_RD_PRI_QUEUING 0x010d
-#define mmMMEA0_DRAM_RD_PRI_QUEUING_BASE_IDX 0
-#define mmMMEA0_DRAM_WR_PRI_QUEUING 0x010e
-#define mmMMEA0_DRAM_WR_PRI_QUEUING_BASE_IDX 0
-#define mmMMEA0_DRAM_RD_PRI_FIXED 0x010f
-#define mmMMEA0_DRAM_RD_PRI_FIXED_BASE_IDX 0
-#define mmMMEA0_DRAM_WR_PRI_FIXED 0x0110
-#define mmMMEA0_DRAM_WR_PRI_FIXED_BASE_IDX 0
-#define mmMMEA0_DRAM_RD_PRI_URGENCY 0x0111
-#define mmMMEA0_DRAM_RD_PRI_URGENCY_BASE_IDX 0
-#define mmMMEA0_DRAM_WR_PRI_URGENCY 0x0112
-#define mmMMEA0_DRAM_WR_PRI_URGENCY_BASE_IDX 0
-#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1 0x0113
-#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0
-#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2 0x0114
-#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0
-#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3 0x0115
-#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0
-#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1 0x0116
-#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0
-#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2 0x0117
-#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0
-#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3 0x0118
-#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0
-#define mmMMEA0_ADDRNORM_BASE_ADDR0 0x0134
-#define mmMMEA0_ADDRNORM_BASE_ADDR0_BASE_IDX 0
-#define mmMMEA0_ADDRNORM_LIMIT_ADDR0 0x0135
-#define mmMMEA0_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0
-#define mmMMEA0_ADDRNORM_BASE_ADDR1 0x0136
-#define mmMMEA0_ADDRNORM_BASE_ADDR1_BASE_IDX 0
-#define mmMMEA0_ADDRNORM_LIMIT_ADDR1 0x0137
-#define mmMMEA0_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0
-#define mmMMEA0_ADDRNORM_OFFSET_ADDR1 0x0138
-#define mmMMEA0_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0
-#define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL 0x0143
-#define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0
-#define mmMMEA0_ADDRNORMDRAM_TRICHANNEL_CFG 0x0145
-#define mmMMEA0_ADDRNORMDRAM_TRICHANNEL_CFG_BASE_IDX 0
-#define mmMMEA0_ADDRDEC_BANK_CFG 0x0147
-#define mmMMEA0_ADDRDEC_BANK_CFG_BASE_IDX 0
-#define mmMMEA0_ADDRDEC_MISC_CFG 0x0148
-#define mmMMEA0_ADDRDEC_MISC_CFG_BASE_IDX 0
-#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 0x0149
-#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 0
-#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 0x014a
-#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 0
-#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 0x014b
-#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 0
-#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 0x014c
-#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 0
-#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 0x014d
-#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 0
-#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC 0x014e
-#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 0
-#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2 0x014f
-#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 0
-#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0 0x0150
-#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 0
-#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1 0x0151
-#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 0
-#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE 0x0152
-#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0
-#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0 0x015d
-#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0
-#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1 0x015e
-#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0
-#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2 0x015f
-#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0
-#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3 0x0160
-#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0
-#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0 0x0161
-#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0
-#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1 0x0162
-#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0
-#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2 0x0163
-#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0
-#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3 0x0164
-#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0
-#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01 0x0165
-#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0
-#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23 0x0166
-#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0
-#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01 0x0167
-#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0
-#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23 0x0168
-#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0
-#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01 0x0169
-#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0
-#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23 0x016a
-#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0
-#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01 0x016b
-#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0
-#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23 0x016c
-#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0
-#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01 0x016d
-#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0
-#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23 0x016e
-#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0
-#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01 0x016f
-#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0
-#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23 0x0170
-#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0
-#define mmMMEA0_ADDRDEC0_RM_SEL_CS01 0x0171
-#define mmMMEA0_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0
-#define mmMMEA0_ADDRDEC0_RM_SEL_CS23 0x0172
-#define mmMMEA0_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0
-#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01 0x0173
-#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0
-#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23 0x0174
-#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0
-#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0 0x0175
-#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0
-#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1 0x0176
-#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0
-#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2 0x0177
-#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0
-#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3 0x0178
-#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0
-#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0 0x0179
-#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0
-#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1 0x017a
-#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0
-#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2 0x017b
-#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0
-#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3 0x017c
-#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0
-#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01 0x017d
-#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0
-#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23 0x017e
-#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0
-#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01 0x017f
-#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0
-#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23 0x0180
-#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0
-#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01 0x0181
-#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0
-#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23 0x0182
-#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0
-#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01 0x0183
-#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0
-#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23 0x0184
-#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0
-#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01 0x0185
-#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0
-#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23 0x0186
-#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0
-#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01 0x0187
-#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0
-#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23 0x0188
-#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0
-#define mmMMEA0_ADDRDEC1_RM_SEL_CS01 0x0189
-#define mmMMEA0_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0
-#define mmMMEA0_ADDRDEC1_RM_SEL_CS23 0x018a
-#define mmMMEA0_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0
-#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01 0x018b
-#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0
-#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23 0x018c
-#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0
-#define mmMMEA0_IO_RD_CLI2GRP_MAP0 0x01d5
-#define mmMMEA0_IO_RD_CLI2GRP_MAP0_BASE_IDX 0
-#define mmMMEA0_IO_RD_CLI2GRP_MAP1 0x01d6
-#define mmMMEA0_IO_RD_CLI2GRP_MAP1_BASE_IDX 0
-#define mmMMEA0_IO_WR_CLI2GRP_MAP0 0x01d7
-#define mmMMEA0_IO_WR_CLI2GRP_MAP0_BASE_IDX 0
-#define mmMMEA0_IO_WR_CLI2GRP_MAP1 0x01d8
-#define mmMMEA0_IO_WR_CLI2GRP_MAP1_BASE_IDX 0
-#define mmMMEA0_IO_RD_COMBINE_FLUSH 0x01d9
-#define mmMMEA0_IO_RD_COMBINE_FLUSH_BASE_IDX 0
-#define mmMMEA0_IO_WR_COMBINE_FLUSH 0x01da
-#define mmMMEA0_IO_WR_COMBINE_FLUSH_BASE_IDX 0
-#define mmMMEA0_IO_GROUP_BURST 0x01db
-#define mmMMEA0_IO_GROUP_BURST_BASE_IDX 0
-#define mmMMEA0_IO_RD_PRI_AGE 0x01dc
-#define mmMMEA0_IO_RD_PRI_AGE_BASE_IDX 0
-#define mmMMEA0_IO_WR_PRI_AGE 0x01dd
-#define mmMMEA0_IO_WR_PRI_AGE_BASE_IDX 0
-#define mmMMEA0_IO_RD_PRI_QUEUING 0x01de
-#define mmMMEA0_IO_RD_PRI_QUEUING_BASE_IDX 0
-#define mmMMEA0_IO_WR_PRI_QUEUING 0x01df
-#define mmMMEA0_IO_WR_PRI_QUEUING_BASE_IDX 0
-#define mmMMEA0_IO_RD_PRI_FIXED 0x01e0
-#define mmMMEA0_IO_RD_PRI_FIXED_BASE_IDX 0
-#define mmMMEA0_IO_WR_PRI_FIXED 0x01e1
-#define mmMMEA0_IO_WR_PRI_FIXED_BASE_IDX 0
-#define mmMMEA0_IO_RD_PRI_URGENCY 0x01e2
-#define mmMMEA0_IO_RD_PRI_URGENCY_BASE_IDX 0
-#define mmMMEA0_IO_WR_PRI_URGENCY 0x01e3
-#define mmMMEA0_IO_WR_PRI_URGENCY_BASE_IDX 0
-#define mmMMEA0_IO_RD_PRI_URGENCY_MASK 0x01e4
-#define mmMMEA0_IO_RD_PRI_URGENCY_MASK_BASE_IDX 0
-#define mmMMEA0_IO_WR_PRI_URGENCY_MASK 0x01e5
-#define mmMMEA0_IO_WR_PRI_URGENCY_MASK_BASE_IDX 0
-#define mmMMEA0_IO_RD_PRI_QUANT_PRI1 0x01e6
-#define mmMMEA0_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0
-#define mmMMEA0_IO_RD_PRI_QUANT_PRI2 0x01e7
-#define mmMMEA0_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0
-#define mmMMEA0_IO_RD_PRI_QUANT_PRI3 0x01e8
-#define mmMMEA0_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0
-#define mmMMEA0_IO_WR_PRI_QUANT_PRI1 0x01e9
-#define mmMMEA0_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0
-#define mmMMEA0_IO_WR_PRI_QUANT_PRI2 0x01ea
-#define mmMMEA0_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0
-#define mmMMEA0_IO_WR_PRI_QUANT_PRI3 0x01eb
-#define mmMMEA0_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0
-#define mmMMEA0_SDP_ARB_DRAM 0x01ec
-#define mmMMEA0_SDP_ARB_DRAM_BASE_IDX 0
-#define mmMMEA0_SDP_ARB_FINAL 0x01ee
-#define mmMMEA0_SDP_ARB_FINAL_BASE_IDX 0
-#define mmMMEA0_SDP_DRAM_PRIORITY 0x01ef
-#define mmMMEA0_SDP_DRAM_PRIORITY_BASE_IDX 0
-#define mmMMEA0_SDP_IO_PRIORITY 0x01f1
-#define mmMMEA0_SDP_IO_PRIORITY_BASE_IDX 0
-#define mmMMEA0_SDP_CREDITS 0x01f2
-#define mmMMEA0_SDP_CREDITS_BASE_IDX 0
-#define mmMMEA0_SDP_TAG_RESERVE0 0x01f3
-#define mmMMEA0_SDP_TAG_RESERVE0_BASE_IDX 0
-#define mmMMEA0_SDP_TAG_RESERVE1 0x01f4
-#define mmMMEA0_SDP_TAG_RESERVE1_BASE_IDX 0
-#define mmMMEA0_SDP_VCC_RESERVE0 0x01f5
-#define mmMMEA0_SDP_VCC_RESERVE0_BASE_IDX 0
-#define mmMMEA0_SDP_VCC_RESERVE1 0x01f6
-#define mmMMEA0_SDP_VCC_RESERVE1_BASE_IDX 0
-#define mmMMEA0_SDP_VCD_RESERVE0 0x01f7
-#define mmMMEA0_SDP_VCD_RESERVE0_BASE_IDX 0
-#define mmMMEA0_SDP_VCD_RESERVE1 0x01f8
-#define mmMMEA0_SDP_VCD_RESERVE1_BASE_IDX 0
-#define mmMMEA0_SDP_REQ_CNTL 0x01f9
-#define mmMMEA0_SDP_REQ_CNTL_BASE_IDX 0
-#define mmMMEA0_MISC 0x01fa
-#define mmMMEA0_MISC_BASE_IDX 0
-#define mmMMEA0_LATENCY_SAMPLING 0x01fb
-#define mmMMEA0_LATENCY_SAMPLING_BASE_IDX 0
-#define mmMMEA0_PERFCOUNTER_LO 0x01fc
-#define mmMMEA0_PERFCOUNTER_LO_BASE_IDX 0
-#define mmMMEA0_PERFCOUNTER_HI 0x01fd
-#define mmMMEA0_PERFCOUNTER_HI_BASE_IDX 0
-#define mmMMEA0_PERFCOUNTER0_CFG 0x01fe
-#define mmMMEA0_PERFCOUNTER0_CFG_BASE_IDX 0
-#define mmMMEA0_PERFCOUNTER1_CFG 0x01ff
-#define mmMMEA0_PERFCOUNTER1_CFG_BASE_IDX 0
-#define mmMMEA0_PERFCOUNTER_RSLT_CNTL 0x0200
-#define mmMMEA0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
-#define mmMMEA0_EDC_CNT 0x0206
-#define mmMMEA0_EDC_CNT_BASE_IDX 0
-#define mmMMEA0_EDC_CNT2 0x0207
-#define mmMMEA0_EDC_CNT2_BASE_IDX 0
-#define mmMMEA0_DSM_CNTL 0x0208
-#define mmMMEA0_DSM_CNTL_BASE_IDX 0
-#define mmMMEA0_DSM_CNTLA 0x0209
-#define mmMMEA0_DSM_CNTLA_BASE_IDX 0
-#define mmMMEA0_DSM_CNTLB 0x020a
-#define mmMMEA0_DSM_CNTLB_BASE_IDX 0
-#define mmMMEA0_DSM_CNTL2 0x020b
-#define mmMMEA0_DSM_CNTL2_BASE_IDX 0
-#define mmMMEA0_DSM_CNTL2A 0x020c
-#define mmMMEA0_DSM_CNTL2A_BASE_IDX 0
-#define mmMMEA0_DSM_CNTL2B 0x020d
-#define mmMMEA0_DSM_CNTL2B_BASE_IDX 0
-#define mmMMEA0_CGTT_CLK_CTRL 0x020f
-#define mmMMEA0_CGTT_CLK_CTRL_BASE_IDX 0
-#define mmMMEA0_EDC_MODE 0x0210
-#define mmMMEA0_EDC_MODE_BASE_IDX 0
-#define mmMMEA0_ERR_STATUS 0x0211
-#define mmMMEA0_ERR_STATUS_BASE_IDX 0
-#define mmMMEA0_MISC2 0x0212
-#define mmMMEA0_MISC2_BASE_IDX 0
-#define mmMMEA1_DRAM_RD_CLI2GRP_MAP0 0x0240
-#define mmMMEA1_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0
-#define mmMMEA1_DRAM_RD_CLI2GRP_MAP1 0x0241
-#define mmMMEA1_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0
-#define mmMMEA1_DRAM_WR_CLI2GRP_MAP0 0x0242
-#define mmMMEA1_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0
-#define mmMMEA1_DRAM_WR_CLI2GRP_MAP1 0x0243
-#define mmMMEA1_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0
-#define mmMMEA1_DRAM_RD_GRP2VC_MAP 0x0244
-#define mmMMEA1_DRAM_RD_GRP2VC_MAP_BASE_IDX 0
-#define mmMMEA1_DRAM_WR_GRP2VC_MAP 0x0245
-#define mmMMEA1_DRAM_WR_GRP2VC_MAP_BASE_IDX 0
-#define mmMMEA1_DRAM_RD_LAZY 0x0246
-#define mmMMEA1_DRAM_RD_LAZY_BASE_IDX 0
-#define mmMMEA1_DRAM_WR_LAZY 0x0247
-#define mmMMEA1_DRAM_WR_LAZY_BASE_IDX 0
-#define mmMMEA1_DRAM_RD_CAM_CNTL 0x0248
-#define mmMMEA1_DRAM_RD_CAM_CNTL_BASE_IDX 0
-#define mmMMEA1_DRAM_WR_CAM_CNTL 0x0249
-#define mmMMEA1_DRAM_WR_CAM_CNTL_BASE_IDX 0
-#define mmMMEA1_DRAM_PAGE_BURST 0x024a
-#define mmMMEA1_DRAM_PAGE_BURST_BASE_IDX 0
-#define mmMMEA1_DRAM_RD_PRI_AGE 0x024b
-#define mmMMEA1_DRAM_RD_PRI_AGE_BASE_IDX 0
-#define mmMMEA1_DRAM_WR_PRI_AGE 0x024c
-#define mmMMEA1_DRAM_WR_PRI_AGE_BASE_IDX 0
-#define mmMMEA1_DRAM_RD_PRI_QUEUING 0x024d
-#define mmMMEA1_DRAM_RD_PRI_QUEUING_BASE_IDX 0
-#define mmMMEA1_DRAM_WR_PRI_QUEUING 0x024e
-#define mmMMEA1_DRAM_WR_PRI_QUEUING_BASE_IDX 0
-#define mmMMEA1_DRAM_RD_PRI_FIXED 0x024f
-#define mmMMEA1_DRAM_RD_PRI_FIXED_BASE_IDX 0
-#define mmMMEA1_DRAM_WR_PRI_FIXED 0x0250
-#define mmMMEA1_DRAM_WR_PRI_FIXED_BASE_IDX 0
-#define mmMMEA1_DRAM_RD_PRI_URGENCY 0x0251
-#define mmMMEA1_DRAM_RD_PRI_URGENCY_BASE_IDX 0
-#define mmMMEA1_DRAM_WR_PRI_URGENCY 0x0252
-#define mmMMEA1_DRAM_WR_PRI_URGENCY_BASE_IDX 0
-#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1 0x0253
-#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0
-#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2 0x0254
-#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0
-#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3 0x0255
-#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0
-#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1 0x0256
-#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0
-#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2 0x0257
-#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0
-#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3 0x0258
-#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0
-#define mmMMEA1_ADDRNORM_BASE_ADDR0 0x0274
-#define mmMMEA1_ADDRNORM_BASE_ADDR0_BASE_IDX 0
-#define mmMMEA1_ADDRNORM_LIMIT_ADDR0 0x0275
-#define mmMMEA1_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0
-#define mmMMEA1_ADDRNORM_BASE_ADDR1 0x0276
-#define mmMMEA1_ADDRNORM_BASE_ADDR1_BASE_IDX 0
-#define mmMMEA1_ADDRNORM_LIMIT_ADDR1 0x0277
-#define mmMMEA1_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0
-#define mmMMEA1_ADDRNORM_OFFSET_ADDR1 0x0278
-#define mmMMEA1_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0
-#define mmMMEA1_ADDRNORMDRAM_HOLE_CNTL 0x0283
-#define mmMMEA1_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0
-#define mmMMEA1_ADDRNORMDRAM_TRICHANNEL_CFG 0x0285
-#define mmMMEA1_ADDRNORMDRAM_TRICHANNEL_CFG_BASE_IDX 0
-#define mmMMEA1_ADDRDEC_BANK_CFG 0x0287
-#define mmMMEA1_ADDRDEC_BANK_CFG_BASE_IDX 0
-#define mmMMEA1_ADDRDEC_MISC_CFG 0x0288
-#define mmMMEA1_ADDRDEC_MISC_CFG_BASE_IDX 0
-#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0 0x0289
-#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 0
-#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1 0x028a
-#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 0
-#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2 0x028b
-#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 0
-#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3 0x028c
-#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 0
-#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4 0x028d
-#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 0
-#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC 0x028e
-#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 0
-#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2 0x028f
-#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 0
-#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0 0x0290
-#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 0
-#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1 0x0291
-#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 0
-#define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE 0x0292
-#define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0
-#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0 0x029d
-#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0
-#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1 0x029e
-#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0
-#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2 0x029f
-#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0
-#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3 0x02a0
-#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0
-#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0 0x02a1
-#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0
-#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1 0x02a2
-#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0
-#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2 0x02a3
-#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0
-#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3 0x02a4
-#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0
-#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01 0x02a5
-#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0
-#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23 0x02a6
-#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0
-#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01 0x02a7
-#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0
-#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23 0x02a8
-#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0
-#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01 0x02a9
-#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0
-#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23 0x02aa
-#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0
-#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01 0x02ab
-#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0
-#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23 0x02ac
-#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0
-#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01 0x02ad
-#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0
-#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23 0x02ae
-#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0
-#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01 0x02af
-#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0
-#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23 0x02b0
-#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0
-#define mmMMEA1_ADDRDEC0_RM_SEL_CS01 0x02b1
-#define mmMMEA1_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0
-#define mmMMEA1_ADDRDEC0_RM_SEL_CS23 0x02b2
-#define mmMMEA1_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0
-#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01 0x02b3
-#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0
-#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23 0x02b4
-#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0
-#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0 0x02b5
-#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0
-#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1 0x02b6
-#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0
-#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2 0x02b7
-#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0
-#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3 0x02b8
-#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0
-#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0 0x02b9
-#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0
-#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1 0x02ba
-#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0
-#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2 0x02bb
-#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0
-#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3 0x02bc
-#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0
-#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01 0x02bd
-#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0
-#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23 0x02be
-#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0
-#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01 0x02bf
-#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0
-#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23 0x02c0
-#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0
-#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01 0x02c1
-#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0
-#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23 0x02c2
-#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0
-#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01 0x02c3
-#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0
-#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23 0x02c4
-#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0
-#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01 0x02c5
-#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0
-#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23 0x02c6
-#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0
-#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01 0x02c7
-#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0
-#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23 0x02c8
-#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0
-#define mmMMEA1_ADDRDEC1_RM_SEL_CS01 0x02c9
-#define mmMMEA1_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0
-#define mmMMEA1_ADDRDEC1_RM_SEL_CS23 0x02ca
-#define mmMMEA1_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0
-#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01 0x02cb
-#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0
-#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23 0x02cc
-#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0
-#define mmMMEA1_IO_RD_CLI2GRP_MAP0 0x0315
-#define mmMMEA1_IO_RD_CLI2GRP_MAP0_BASE_IDX 0
-#define mmMMEA1_IO_RD_CLI2GRP_MAP1 0x0316
-#define mmMMEA1_IO_RD_CLI2GRP_MAP1_BASE_IDX 0
-#define mmMMEA1_IO_WR_CLI2GRP_MAP0 0x0317
-#define mmMMEA1_IO_WR_CLI2GRP_MAP0_BASE_IDX 0
-#define mmMMEA1_IO_WR_CLI2GRP_MAP1 0x0318
-#define mmMMEA1_IO_WR_CLI2GRP_MAP1_BASE_IDX 0
-#define mmMMEA1_IO_RD_COMBINE_FLUSH 0x0319
-#define mmMMEA1_IO_RD_COMBINE_FLUSH_BASE_IDX 0
-#define mmMMEA1_IO_WR_COMBINE_FLUSH 0x031a
-#define mmMMEA1_IO_WR_COMBINE_FLUSH_BASE_IDX 0
-#define mmMMEA1_IO_GROUP_BURST 0x031b
-#define mmMMEA1_IO_GROUP_BURST_BASE_IDX 0
-#define mmMMEA1_IO_RD_PRI_AGE 0x031c
-#define mmMMEA1_IO_RD_PRI_AGE_BASE_IDX 0
-#define mmMMEA1_IO_WR_PRI_AGE 0x031d
-#define mmMMEA1_IO_WR_PRI_AGE_BASE_IDX 0
-#define mmMMEA1_IO_RD_PRI_QUEUING 0x031e
-#define mmMMEA1_IO_RD_PRI_QUEUING_BASE_IDX 0
-#define mmMMEA1_IO_WR_PRI_QUEUING 0x031f
-#define mmMMEA1_IO_WR_PRI_QUEUING_BASE_IDX 0
-#define mmMMEA1_IO_RD_PRI_FIXED 0x0320
-#define mmMMEA1_IO_RD_PRI_FIXED_BASE_IDX 0
-#define mmMMEA1_IO_WR_PRI_FIXED 0x0321
-#define mmMMEA1_IO_WR_PRI_FIXED_BASE_IDX 0
-#define mmMMEA1_IO_RD_PRI_URGENCY 0x0322
-#define mmMMEA1_IO_RD_PRI_URGENCY_BASE_IDX 0
-#define mmMMEA1_IO_WR_PRI_URGENCY 0x0323
-#define mmMMEA1_IO_WR_PRI_URGENCY_BASE_IDX 0
-#define mmMMEA1_IO_RD_PRI_URGENCY_MASK 0x0324
-#define mmMMEA1_IO_RD_PRI_URGENCY_MASK_BASE_IDX 0
-#define mmMMEA1_IO_WR_PRI_URGENCY_MASK 0x0325
-#define mmMMEA1_IO_WR_PRI_URGENCY_MASK_BASE_IDX 0
-#define mmMMEA1_IO_RD_PRI_QUANT_PRI1 0x0326
-#define mmMMEA1_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0
-#define mmMMEA1_IO_RD_PRI_QUANT_PRI2 0x0327
-#define mmMMEA1_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0
-#define mmMMEA1_IO_RD_PRI_QUANT_PRI3 0x0328
-#define mmMMEA1_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0
-#define mmMMEA1_IO_WR_PRI_QUANT_PRI1 0x0329
-#define mmMMEA1_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0
-#define mmMMEA1_IO_WR_PRI_QUANT_PRI2 0x032a
-#define mmMMEA1_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0
-#define mmMMEA1_IO_WR_PRI_QUANT_PRI3 0x032b
-#define mmMMEA1_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0
-#define mmMMEA1_SDP_ARB_DRAM 0x032c
-#define mmMMEA1_SDP_ARB_DRAM_BASE_IDX 0
-#define mmMMEA1_SDP_ARB_FINAL 0x032e
-#define mmMMEA1_SDP_ARB_FINAL_BASE_IDX 0
-#define mmMMEA1_SDP_DRAM_PRIORITY 0x032f
-#define mmMMEA1_SDP_DRAM_PRIORITY_BASE_IDX 0
-#define mmMMEA1_SDP_IO_PRIORITY 0x0331
-#define mmMMEA1_SDP_IO_PRIORITY_BASE_IDX 0
-#define mmMMEA1_SDP_CREDITS 0x0332
-#define mmMMEA1_SDP_CREDITS_BASE_IDX 0
-#define mmMMEA1_SDP_TAG_RESERVE0 0x0333
-#define mmMMEA1_SDP_TAG_RESERVE0_BASE_IDX 0
-#define mmMMEA1_SDP_TAG_RESERVE1 0x0334
-#define mmMMEA1_SDP_TAG_RESERVE1_BASE_IDX 0
-#define mmMMEA1_SDP_VCC_RESERVE0 0x0335
-#define mmMMEA1_SDP_VCC_RESERVE0_BASE_IDX 0
-#define mmMMEA1_SDP_VCC_RESERVE1 0x0336
-#define mmMMEA1_SDP_VCC_RESERVE1_BASE_IDX 0
-#define mmMMEA1_SDP_VCD_RESERVE0 0x0337
-#define mmMMEA1_SDP_VCD_RESERVE0_BASE_IDX 0
-#define mmMMEA1_SDP_VCD_RESERVE1 0x0338
-#define mmMMEA1_SDP_VCD_RESERVE1_BASE_IDX 0
-#define mmMMEA1_SDP_REQ_CNTL 0x0339
-#define mmMMEA1_SDP_REQ_CNTL_BASE_IDX 0
-#define mmMMEA1_MISC 0x033a
-#define mmMMEA1_MISC_BASE_IDX 0
-#define mmMMEA1_LATENCY_SAMPLING 0x033b
-#define mmMMEA1_LATENCY_SAMPLING_BASE_IDX 0
-#define mmMMEA1_PERFCOUNTER_LO 0x033c
-#define mmMMEA1_PERFCOUNTER_LO_BASE_IDX 0
-#define mmMMEA1_PERFCOUNTER_HI 0x033d
-#define mmMMEA1_PERFCOUNTER_HI_BASE_IDX 0
-#define mmMMEA1_PERFCOUNTER0_CFG 0x033e
-#define mmMMEA1_PERFCOUNTER0_CFG_BASE_IDX 0
-#define mmMMEA1_PERFCOUNTER1_CFG 0x033f
-#define mmMMEA1_PERFCOUNTER1_CFG_BASE_IDX 0
-#define mmMMEA1_PERFCOUNTER_RSLT_CNTL 0x0340
-#define mmMMEA1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
-#define mmMMEA1_EDC_CNT 0x0346
-#define mmMMEA1_EDC_CNT_BASE_IDX 0
-#define mmMMEA1_EDC_CNT2 0x0347
-#define mmMMEA1_EDC_CNT2_BASE_IDX 0
-#define mmMMEA1_DSM_CNTL 0x0348
-#define mmMMEA1_DSM_CNTL_BASE_IDX 0
-#define mmMMEA1_DSM_CNTLA 0x0349
-#define mmMMEA1_DSM_CNTLA_BASE_IDX 0
-#define mmMMEA1_DSM_CNTLB 0x034a
-#define mmMMEA1_DSM_CNTLB_BASE_IDX 0
-#define mmMMEA1_DSM_CNTL2 0x034b
-#define mmMMEA1_DSM_CNTL2_BASE_IDX 0
-#define mmMMEA1_DSM_CNTL2A 0x034c
-#define mmMMEA1_DSM_CNTL2A_BASE_IDX 0
-#define mmMMEA1_DSM_CNTL2B 0x034d
-#define mmMMEA1_DSM_CNTL2B_BASE_IDX 0
-#define mmMMEA1_CGTT_CLK_CTRL 0x034f
-#define mmMMEA1_CGTT_CLK_CTRL_BASE_IDX 0
-#define mmMMEA1_EDC_MODE 0x0350
-#define mmMMEA1_EDC_MODE_BASE_IDX 0
-#define mmMMEA1_ERR_STATUS 0x0351
-#define mmMMEA1_ERR_STATUS_BASE_IDX 0
-#define mmMMEA1_MISC2 0x0352
-#define mmMMEA1_MISC2_BASE_IDX 0
-
-
-// addressBlock: mmhub_pctldec
-// base address: 0x68e00
-#define mmPCTL_MISC 0x0380
-#define mmPCTL_MISC_BASE_IDX 0
-#define mmPCTL_MMHUB_DEEPSLEEP 0x0381
-#define mmPCTL_MMHUB_DEEPSLEEP_BASE_IDX 0
-#define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE 0x0382
-#define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 0
-#define mmPCTL_PG_IGNORE_DEEPSLEEP 0x0383
-#define mmPCTL_PG_IGNORE_DEEPSLEEP_BASE_IDX 0
-#define mmPCTL_PG_DAGB 0x0384
-#define mmPCTL_PG_DAGB_BASE_IDX 0
-#define mmPCTL0_RENG_RAM_INDEX 0x0385
-#define mmPCTL0_RENG_RAM_INDEX_BASE_IDX 0
-#define mmPCTL0_RENG_RAM_DATA 0x0386
-#define mmPCTL0_RENG_RAM_DATA_BASE_IDX 0
-#define mmPCTL0_RENG_EXECUTE 0x0387
-#define mmPCTL0_RENG_EXECUTE_BASE_IDX 0
-#define mmPCTL0_MISC 0x0388
-#define mmPCTL0_MISC_BASE_IDX 0
-#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0 0x0389
-#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0
-#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1 0x038a
-#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0
-#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2 0x038b
-#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0
-#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE3 0x038c
-#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 0
-#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE4 0x038d
-#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 0
-#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET 0x038e
-#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET_BASE_IDX 0
-#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1 0x038f
-#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0
-#define mmPCTL1_RENG_RAM_INDEX 0x0390
-#define mmPCTL1_RENG_RAM_INDEX_BASE_IDX 0
-#define mmPCTL1_RENG_RAM_DATA 0x0391
-#define mmPCTL1_RENG_RAM_DATA_BASE_IDX 0
-#define mmPCTL1_RENG_EXECUTE 0x0392
-#define mmPCTL1_RENG_EXECUTE_BASE_IDX 0
-#define mmPCTL1_MISC 0x0393
-#define mmPCTL1_MISC_BASE_IDX 0
-#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0 0x0394
-#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0
-#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1 0x0395
-#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0
-#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2 0x0396
-#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0
-#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE3 0x0397
-#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 0
-#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE4 0x0398
-#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 0
-#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET 0x0399
-#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET_BASE_IDX 0
-#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1 0x039a
-#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0
-#define mmPCTL2_RENG_RAM_INDEX 0x039b
-#define mmPCTL2_RENG_RAM_INDEX_BASE_IDX 0
-#define mmPCTL2_RENG_RAM_DATA 0x039c
-#define mmPCTL2_RENG_RAM_DATA_BASE_IDX 0
-#define mmPCTL2_RENG_EXECUTE 0x039d
-#define mmPCTL2_RENG_EXECUTE_BASE_IDX 0
-#define mmPCTL2_MISC 0x039e
-#define mmPCTL2_MISC_BASE_IDX 0
-#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0 0x039f
-#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0
-#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1 0x03a0
-#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0
-#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2 0x03a1
-#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0
-#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE3 0x03a2
-#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 0
-#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE4 0x03a3
-#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 0
-#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET 0x03a4
-#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET_BASE_IDX 0
-#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x03a5
-#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0
-
-
-// addressBlock: mmhub_l1tlb_vml1dec
-// base address: 0x69600
-#define mmMC_VM_MX_L1_TLB0_STATUS 0x0588
-#define mmMC_VM_MX_L1_TLB0_STATUS_BASE_IDX 0
-#define mmMC_VM_MX_L1_TLB1_STATUS 0x0589
-#define mmMC_VM_MX_L1_TLB1_STATUS_BASE_IDX 0
-#define mmMC_VM_MX_L1_TLB2_STATUS 0x058a
-#define mmMC_VM_MX_L1_TLB2_STATUS_BASE_IDX 0
-#define mmMC_VM_MX_L1_TLB3_STATUS 0x058b
-#define mmMC_VM_MX_L1_TLB3_STATUS_BASE_IDX 0
-#define mmMC_VM_MX_L1_TLB4_STATUS 0x058c
-#define mmMC_VM_MX_L1_TLB4_STATUS_BASE_IDX 0
-#define mmMC_VM_MX_L1_TLB5_STATUS 0x058d
-#define mmMC_VM_MX_L1_TLB5_STATUS_BASE_IDX 0
-#define mmMC_VM_MX_L1_TLB6_STATUS 0x058e
-#define mmMC_VM_MX_L1_TLB6_STATUS_BASE_IDX 0
-#define mmMC_VM_MX_L1_TLB7_STATUS 0x058f
-#define mmMC_VM_MX_L1_TLB7_STATUS_BASE_IDX 0
-
-
-// addressBlock: mmhub_l1tlb_vml1pldec
-// base address: 0x69650
-#define mmMC_VM_MX_L1_PERFCOUNTER0_CFG 0x0594
-#define mmMC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX 0
-#define mmMC_VM_MX_L1_PERFCOUNTER1_CFG 0x0595
-#define mmMC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX 0
-#define mmMC_VM_MX_L1_PERFCOUNTER2_CFG 0x0596
-#define mmMC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX 0
-#define mmMC_VM_MX_L1_PERFCOUNTER3_CFG 0x0597
-#define mmMC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX 0
-#define mmMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0x0598
-#define mmMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
-
-
-// addressBlock: mmhub_l1tlb_vml1prdec
-// base address: 0x69670
-#define mmMC_VM_MX_L1_PERFCOUNTER_LO 0x059c
-#define mmMC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX 0
-#define mmMC_VM_MX_L1_PERFCOUNTER_HI 0x059d
-#define mmMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX 0
-
-
-// addressBlock: mmhub_utcl2_atcl2dec
-// base address: 0x69900
-#define mmATC_L2_CNTL 0x0640
-#define mmATC_L2_CNTL_BASE_IDX 0
-#define mmATC_L2_CNTL2 0x0641
-#define mmATC_L2_CNTL2_BASE_IDX 0
-#define mmATC_L2_CACHE_DATA0 0x0644
-#define mmATC_L2_CACHE_DATA0_BASE_IDX 0
-#define mmATC_L2_CACHE_DATA1 0x0645
-#define mmATC_L2_CACHE_DATA1_BASE_IDX 0
-#define mmATC_L2_CACHE_DATA2 0x0646
-#define mmATC_L2_CACHE_DATA2_BASE_IDX 0
-#define mmATC_L2_CNTL3 0x0647
-#define mmATC_L2_CNTL3_BASE_IDX 0
-#define mmATC_L2_STATUS 0x0648
-#define mmATC_L2_STATUS_BASE_IDX 0
-#define mmATC_L2_STATUS2 0x0649
-#define mmATC_L2_STATUS2_BASE_IDX 0
-#define mmATC_L2_MISC_CG 0x064a
-#define mmATC_L2_MISC_CG_BASE_IDX 0
-#define mmATC_L2_MEM_POWER_LS 0x064b
-#define mmATC_L2_MEM_POWER_LS_BASE_IDX 0
-#define mmATC_L2_CGTT_CLK_CTRL 0x064c
-#define mmATC_L2_CGTT_CLK_CTRL_BASE_IDX 0
-
-
-// addressBlock: mmhub_utcl2_vml2pfdec
-// base address: 0x69a00
-#define mmVM_L2_CNTL 0x0680
-#define mmVM_L2_CNTL_BASE_IDX 0
-#define mmVM_L2_CNTL2 0x0681
-#define mmVM_L2_CNTL2_BASE_IDX 0
-#define mmVM_L2_CNTL3 0x0682
-#define mmVM_L2_CNTL3_BASE_IDX 0
-#define mmVM_L2_STATUS 0x0683
-#define mmVM_L2_STATUS_BASE_IDX 0
-#define mmVM_DUMMY_PAGE_FAULT_CNTL 0x0684
-#define mmVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0
-#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0685
-#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0
-#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0686
-#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0
-#define mmVM_L2_PROTECTION_FAULT_CNTL 0x0687
-#define mmVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0
-#define mmVM_L2_PROTECTION_FAULT_CNTL2 0x0688
-#define mmVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0
-#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3 0x0689
-#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0
-#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4 0x068a
-#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0
-#define mmVM_L2_PROTECTION_FAULT_STATUS 0x068b
-#define mmVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0
-#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32 0x068c
-#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0
-#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32 0x068d
-#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0
-#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x068e
-#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0
-#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x068f
-#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0
-#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0691
-#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0
-#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0692
-#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0
-#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0693
-#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0
-#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0694
-#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0
-#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0695
-#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0
-#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0696
-#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0
-#define mmVM_L2_CNTL4 0x0697
-#define mmVM_L2_CNTL4_BASE_IDX 0
-#define mmVM_L2_MM_GROUP_RT_CLASSES 0x0698
-#define mmVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0
-#define mmVM_L2_BANK_SELECT_RESERVED_CID 0x0699
-#define mmVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0
-#define mmVM_L2_BANK_SELECT_RESERVED_CID2 0x069a
-#define mmVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0
-#define mmVM_L2_CACHE_PARITY_CNTL 0x069b
-#define mmVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0
-#define mmVM_L2_CGTT_CLK_CTRL 0x069e
-#define mmVM_L2_CGTT_CLK_CTRL_BASE_IDX 0
-
-
-// addressBlock: mmhub_utcl2_vml2vcdec
-// base address: 0x69b00
-#define mmVM_CONTEXT0_CNTL 0x06c0
-#define mmVM_CONTEXT0_CNTL_BASE_IDX 0
-#define mmVM_CONTEXT1_CNTL 0x06c1
-#define mmVM_CONTEXT1_CNTL_BASE_IDX 0
-#define mmVM_CONTEXT2_CNTL 0x06c2
-#define mmVM_CONTEXT2_CNTL_BASE_IDX 0
-#define mmVM_CONTEXT3_CNTL 0x06c3
-#define mmVM_CONTEXT3_CNTL_BASE_IDX 0
-#define mmVM_CONTEXT4_CNTL 0x06c4
-#define mmVM_CONTEXT4_CNTL_BASE_IDX 0
-#define mmVM_CONTEXT5_CNTL 0x06c5
-#define mmVM_CONTEXT5_CNTL_BASE_IDX 0
-#define mmVM_CONTEXT6_CNTL 0x06c6
-#define mmVM_CONTEXT6_CNTL_BASE_IDX 0
-#define mmVM_CONTEXT7_CNTL 0x06c7
-#define mmVM_CONTEXT7_CNTL_BASE_IDX 0
-#define mmVM_CONTEXT8_CNTL 0x06c8
-#define mmVM_CONTEXT8_CNTL_BASE_IDX 0
-#define mmVM_CONTEXT9_CNTL 0x06c9
-#define mmVM_CONTEXT9_CNTL_BASE_IDX 0
-#define mmVM_CONTEXT10_CNTL 0x06ca
-#define mmVM_CONTEXT10_CNTL_BASE_IDX 0
-#define mmVM_CONTEXT11_CNTL 0x06cb
-#define mmVM_CONTEXT11_CNTL_BASE_IDX 0
-#define mmVM_CONTEXT12_CNTL 0x06cc
-#define mmVM_CONTEXT12_CNTL_BASE_IDX 0
-#define mmVM_CONTEXT13_CNTL 0x06cd
-#define mmVM_CONTEXT13_CNTL_BASE_IDX 0
-#define mmVM_CONTEXT14_CNTL 0x06ce
-#define mmVM_CONTEXT14_CNTL_BASE_IDX 0
-#define mmVM_CONTEXT15_CNTL 0x06cf
-#define mmVM_CONTEXT15_CNTL_BASE_IDX 0
-#define mmVM_CONTEXTS_DISABLE 0x06d0
-#define mmVM_CONTEXTS_DISABLE_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG0_SEM 0x06d1
-#define mmVM_INVALIDATE_ENG0_SEM_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG1_SEM 0x06d2
-#define mmVM_INVALIDATE_ENG1_SEM_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG2_SEM 0x06d3
-#define mmVM_INVALIDATE_ENG2_SEM_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG3_SEM 0x06d4
-#define mmVM_INVALIDATE_ENG3_SEM_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG4_SEM 0x06d5
-#define mmVM_INVALIDATE_ENG4_SEM_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG5_SEM 0x06d6
-#define mmVM_INVALIDATE_ENG5_SEM_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG6_SEM 0x06d7
-#define mmVM_INVALIDATE_ENG6_SEM_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG7_SEM 0x06d8
-#define mmVM_INVALIDATE_ENG7_SEM_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG8_SEM 0x06d9
-#define mmVM_INVALIDATE_ENG8_SEM_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG9_SEM 0x06da
-#define mmVM_INVALIDATE_ENG9_SEM_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG10_SEM 0x06db
-#define mmVM_INVALIDATE_ENG10_SEM_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG11_SEM 0x06dc
-#define mmVM_INVALIDATE_ENG11_SEM_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG12_SEM 0x06dd
-#define mmVM_INVALIDATE_ENG12_SEM_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG13_SEM 0x06de
-#define mmVM_INVALIDATE_ENG13_SEM_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG14_SEM 0x06df
-#define mmVM_INVALIDATE_ENG14_SEM_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG15_SEM 0x06e0
-#define mmVM_INVALIDATE_ENG15_SEM_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG16_SEM 0x06e1
-#define mmVM_INVALIDATE_ENG16_SEM_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG17_SEM 0x06e2
-#define mmVM_INVALIDATE_ENG17_SEM_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG0_REQ 0x06e3
-#define mmVM_INVALIDATE_ENG0_REQ_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG1_REQ 0x06e4
-#define mmVM_INVALIDATE_ENG1_REQ_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG2_REQ 0x06e5
-#define mmVM_INVALIDATE_ENG2_REQ_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG3_REQ 0x06e6
-#define mmVM_INVALIDATE_ENG3_REQ_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG4_REQ 0x06e7
-#define mmVM_INVALIDATE_ENG4_REQ_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG5_REQ 0x06e8
-#define mmVM_INVALIDATE_ENG5_REQ_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG6_REQ 0x06e9
-#define mmVM_INVALIDATE_ENG6_REQ_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG7_REQ 0x06ea
-#define mmVM_INVALIDATE_ENG7_REQ_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG8_REQ 0x06eb
-#define mmVM_INVALIDATE_ENG8_REQ_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG9_REQ 0x06ec
-#define mmVM_INVALIDATE_ENG9_REQ_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG10_REQ 0x06ed
-#define mmVM_INVALIDATE_ENG10_REQ_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG11_REQ 0x06ee
-#define mmVM_INVALIDATE_ENG11_REQ_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG12_REQ 0x06ef
-#define mmVM_INVALIDATE_ENG12_REQ_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG13_REQ 0x06f0
-#define mmVM_INVALIDATE_ENG13_REQ_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG14_REQ 0x06f1
-#define mmVM_INVALIDATE_ENG14_REQ_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG15_REQ 0x06f2
-#define mmVM_INVALIDATE_ENG15_REQ_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG16_REQ 0x06f3
-#define mmVM_INVALIDATE_ENG16_REQ_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG17_REQ 0x06f4
-#define mmVM_INVALIDATE_ENG17_REQ_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG0_ACK 0x06f5
-#define mmVM_INVALIDATE_ENG0_ACK_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG1_ACK 0x06f6
-#define mmVM_INVALIDATE_ENG1_ACK_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG2_ACK 0x06f7
-#define mmVM_INVALIDATE_ENG2_ACK_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG3_ACK 0x06f8
-#define mmVM_INVALIDATE_ENG3_ACK_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG4_ACK 0x06f9
-#define mmVM_INVALIDATE_ENG4_ACK_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG5_ACK 0x06fa
-#define mmVM_INVALIDATE_ENG5_ACK_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG6_ACK 0x06fb
-#define mmVM_INVALIDATE_ENG6_ACK_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG7_ACK 0x06fc
-#define mmVM_INVALIDATE_ENG7_ACK_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG8_ACK 0x06fd
-#define mmVM_INVALIDATE_ENG8_ACK_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG9_ACK 0x06fe
-#define mmVM_INVALIDATE_ENG9_ACK_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG10_ACK 0x06ff
-#define mmVM_INVALIDATE_ENG10_ACK_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG11_ACK 0x0700
-#define mmVM_INVALIDATE_ENG11_ACK_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG12_ACK 0x0701
-#define mmVM_INVALIDATE_ENG12_ACK_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG13_ACK 0x0702
-#define mmVM_INVALIDATE_ENG13_ACK_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG14_ACK 0x0703
-#define mmVM_INVALIDATE_ENG14_ACK_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG15_ACK 0x0704
-#define mmVM_INVALIDATE_ENG15_ACK_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG16_ACK 0x0705
-#define mmVM_INVALIDATE_ENG16_ACK_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG17_ACK 0x0706
-#define mmVM_INVALIDATE_ENG17_ACK_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x0707
-#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x0708
-#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x0709
-#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x070a
-#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x070b
-#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x070c
-#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x070d
-#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x070e
-#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x070f
-#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x0710
-#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x0711
-#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x0712
-#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x0713
-#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x0714
-#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x0715
-#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x0716
-#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x0717
-#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x0718
-#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x0719
-#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x071a
-#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x071b
-#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x071c
-#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x071d
-#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x071e
-#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x071f
-#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x0720
-#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x0721
-#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x0722
-#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x0723
-#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x0724
-#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x0725
-#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x0726
-#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x0727
-#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x0728
-#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x0729
-#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0
-#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x072a
-#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0
-#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x072b
-#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x072c
-#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x072d
-#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x072e
-#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x072f
-#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0730
-#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0731
-#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x0732
-#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0733
-#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0734
-#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x0735
-#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x0736
-#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0737
-#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0738
-#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x0739
-#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x073a
-#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x073b
-#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x073c
-#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x073d
-#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x073e
-#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x073f
-#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0740
-#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0741
-#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0742
-#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x0743
-#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x0744
-#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x0745
-#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x0746
-#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x0747
-#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x0748
-#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x0749
-#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x074a
-#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x074b
-#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x074c
-#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x074d
-#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x074e
-#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x074f
-#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x0750
-#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0751
-#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0752
-#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0753
-#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0754
-#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0755
-#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x0756
-#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0757
-#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0758
-#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x0759
-#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x075a
-#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x075b
-#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x075c
-#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x075d
-#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x075e
-#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x075f
-#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0760
-#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0761
-#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0762
-#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0763
-#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x0764
-#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x0765
-#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x0766
-#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x0767
-#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x0768
-#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x0769
-#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x076a
-#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x076b
-#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x076c
-#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x076d
-#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x076e
-#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x076f
-#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0770
-#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0771
-#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0772
-#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0773
-#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0774
-#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0775
-#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0776
-#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0777
-#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0778
-#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0779
-#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x077a
-#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x077b
-#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x077c
-#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x077d
-#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x077e
-#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x077f
-#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0780
-#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0781
-#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0782
-#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0783
-#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0784
-#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0785
-#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0786
-#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0787
-#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0788
-#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
-#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0789
-#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
-#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x078a
-#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
-
-
-// addressBlock: mmhub_utcl2_vml2pldec
-// base address: 0x69e90
-#define mmMC_VM_L2_PERFCOUNTER0_CFG 0x07a4
-#define mmMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 0
-#define mmMC_VM_L2_PERFCOUNTER1_CFG 0x07a5
-#define mmMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 0
-#define mmMC_VM_L2_PERFCOUNTER2_CFG 0x07a6
-#define mmMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 0
-#define mmMC_VM_L2_PERFCOUNTER3_CFG 0x07a7
-#define mmMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 0
-#define mmMC_VM_L2_PERFCOUNTER4_CFG 0x07a8
-#define mmMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 0
-#define mmMC_VM_L2_PERFCOUNTER5_CFG 0x07a9
-#define mmMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 0
-#define mmMC_VM_L2_PERFCOUNTER6_CFG 0x07aa
-#define mmMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 0
-#define mmMC_VM_L2_PERFCOUNTER7_CFG 0x07ab
-#define mmMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 0
-#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x07ac
-#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
-
-
-// addressBlock: mmhub_utcl2_vml2prdec
-// base address: 0x69ee0
-#define mmMC_VM_L2_PERFCOUNTER_LO 0x07b8
-#define mmMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 0
-#define mmMC_VM_L2_PERFCOUNTER_HI 0x07b9
-#define mmMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 0
-
-
-// addressBlock: mmhub_utcl2_vmsharedhvdec
-// base address: 0x69f30
-#define mmMC_VM_FB_SIZE_OFFSET_VF0 0x07cc
-#define mmMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 0
-#define mmMC_VM_FB_SIZE_OFFSET_VF1 0x07cd
-#define mmMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 0
-#define mmMC_VM_FB_SIZE_OFFSET_VF2 0x07ce
-#define mmMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 0
-#define mmMC_VM_FB_SIZE_OFFSET_VF3 0x07cf
-#define mmMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 0
-#define mmMC_VM_FB_SIZE_OFFSET_VF4 0x07d0
-#define mmMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 0
-#define mmMC_VM_FB_SIZE_OFFSET_VF5 0x07d1
-#define mmMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 0
-#define mmMC_VM_FB_SIZE_OFFSET_VF6 0x07d2
-#define mmMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 0
-#define mmMC_VM_FB_SIZE_OFFSET_VF7 0x07d3
-#define mmMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 0
-#define mmMC_VM_FB_SIZE_OFFSET_VF8 0x07d4
-#define mmMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 0
-#define mmMC_VM_FB_SIZE_OFFSET_VF9 0x07d5
-#define mmMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 0
-#define mmMC_VM_FB_SIZE_OFFSET_VF10 0x07d6
-#define mmMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 0
-#define mmMC_VM_FB_SIZE_OFFSET_VF11 0x07d7
-#define mmMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 0
-#define mmMC_VM_FB_SIZE_OFFSET_VF12 0x07d8
-#define mmMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 0
-#define mmMC_VM_FB_SIZE_OFFSET_VF13 0x07d9
-#define mmMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 0
-#define mmMC_VM_FB_SIZE_OFFSET_VF14 0x07da
-#define mmMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 0
-#define mmMC_VM_FB_SIZE_OFFSET_VF15 0x07db
-#define mmMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 0
-#define mmVM_IOMMU_MMIO_CNTRL_1 0x07dc
-#define mmVM_IOMMU_MMIO_CNTRL_1_BASE_IDX 0
-#define mmMC_VM_MARC_BASE_LO_0 0x07dd
-#define mmMC_VM_MARC_BASE_LO_0_BASE_IDX 0
-#define mmMC_VM_MARC_BASE_LO_1 0x07de
-#define mmMC_VM_MARC_BASE_LO_1_BASE_IDX 0
-#define mmMC_VM_MARC_BASE_LO_2 0x07df
-#define mmMC_VM_MARC_BASE_LO_2_BASE_IDX 0
-#define mmMC_VM_MARC_BASE_LO_3 0x07e0
-#define mmMC_VM_MARC_BASE_LO_3_BASE_IDX 0
-#define mmMC_VM_MARC_BASE_HI_0 0x07e1
-#define mmMC_VM_MARC_BASE_HI_0_BASE_IDX 0
-#define mmMC_VM_MARC_BASE_HI_1 0x07e2
-#define mmMC_VM_MARC_BASE_HI_1_BASE_IDX 0
-#define mmMC_VM_MARC_BASE_HI_2 0x07e3
-#define mmMC_VM_MARC_BASE_HI_2_BASE_IDX 0
-#define mmMC_VM_MARC_BASE_HI_3 0x07e4
-#define mmMC_VM_MARC_BASE_HI_3_BASE_IDX 0
-#define mmMC_VM_MARC_RELOC_LO_0 0x07e5
-#define mmMC_VM_MARC_RELOC_LO_0_BASE_IDX 0
-#define mmMC_VM_MARC_RELOC_LO_1 0x07e6
-#define mmMC_VM_MARC_RELOC_LO_1_BASE_IDX 0
-#define mmMC_VM_MARC_RELOC_LO_2 0x07e7
-#define mmMC_VM_MARC_RELOC_LO_2_BASE_IDX 0
-#define mmMC_VM_MARC_RELOC_LO_3 0x07e8
-#define mmMC_VM_MARC_RELOC_LO_3_BASE_IDX 0
-#define mmMC_VM_MARC_RELOC_HI_0 0x07e9
-#define mmMC_VM_MARC_RELOC_HI_0_BASE_IDX 0
-#define mmMC_VM_MARC_RELOC_HI_1 0x07ea
-#define mmMC_VM_MARC_RELOC_HI_1_BASE_IDX 0
-#define mmMC_VM_MARC_RELOC_HI_2 0x07eb
-#define mmMC_VM_MARC_RELOC_HI_2_BASE_IDX 0
-#define mmMC_VM_MARC_RELOC_HI_3 0x07ec
-#define mmMC_VM_MARC_RELOC_HI_3_BASE_IDX 0
-#define mmMC_VM_MARC_LEN_LO_0 0x07ed
-#define mmMC_VM_MARC_LEN_LO_0_BASE_IDX 0
-#define mmMC_VM_MARC_LEN_LO_1 0x07ee
-#define mmMC_VM_MARC_LEN_LO_1_BASE_IDX 0
-#define mmMC_VM_MARC_LEN_LO_2 0x07ef
-#define mmMC_VM_MARC_LEN_LO_2_BASE_IDX 0
-#define mmMC_VM_MARC_LEN_LO_3 0x07f0
-#define mmMC_VM_MARC_LEN_LO_3_BASE_IDX 0
-#define mmMC_VM_MARC_LEN_HI_0 0x07f1
-#define mmMC_VM_MARC_LEN_HI_0_BASE_IDX 0
-#define mmMC_VM_MARC_LEN_HI_1 0x07f2
-#define mmMC_VM_MARC_LEN_HI_1_BASE_IDX 0
-#define mmMC_VM_MARC_LEN_HI_2 0x07f3
-#define mmMC_VM_MARC_LEN_HI_2_BASE_IDX 0
-#define mmMC_VM_MARC_LEN_HI_3 0x07f4
-#define mmMC_VM_MARC_LEN_HI_3_BASE_IDX 0
-#define mmVM_IOMMU_CONTROL_REGISTER 0x07f5
-#define mmVM_IOMMU_CONTROL_REGISTER_BASE_IDX 0
-#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x07f6
-#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 0
-#define mmVM_PCIE_ATS_CNTL 0x07f7
-#define mmVM_PCIE_ATS_CNTL_BASE_IDX 0
-#define mmVM_PCIE_ATS_CNTL_VF_0 0x07f8
-#define mmVM_PCIE_ATS_CNTL_VF_0_BASE_IDX 0
-#define mmVM_PCIE_ATS_CNTL_VF_1 0x07f9
-#define mmVM_PCIE_ATS_CNTL_VF_1_BASE_IDX 0
-#define mmVM_PCIE_ATS_CNTL_VF_2 0x07fa
-#define mmVM_PCIE_ATS_CNTL_VF_2_BASE_IDX 0
-#define mmVM_PCIE_ATS_CNTL_VF_3 0x07fb
-#define mmVM_PCIE_ATS_CNTL_VF_3_BASE_IDX 0
-#define mmVM_PCIE_ATS_CNTL_VF_4 0x07fc
-#define mmVM_PCIE_ATS_CNTL_VF_4_BASE_IDX 0
-#define mmVM_PCIE_ATS_CNTL_VF_5 0x07fd
-#define mmVM_PCIE_ATS_CNTL_VF_5_BASE_IDX 0
-#define mmVM_PCIE_ATS_CNTL_VF_6 0x07fe
-#define mmVM_PCIE_ATS_CNTL_VF_6_BASE_IDX 0
-#define mmVM_PCIE_ATS_CNTL_VF_7 0x07ff
-#define mmVM_PCIE_ATS_CNTL_VF_7_BASE_IDX 0
-#define mmVM_PCIE_ATS_CNTL_VF_8 0x0800
-#define mmVM_PCIE_ATS_CNTL_VF_8_BASE_IDX 0
-#define mmVM_PCIE_ATS_CNTL_VF_9 0x0801
-#define mmVM_PCIE_ATS_CNTL_VF_9_BASE_IDX 0
-#define mmVM_PCIE_ATS_CNTL_VF_10 0x0802
-#define mmVM_PCIE_ATS_CNTL_VF_10_BASE_IDX 0
-#define mmVM_PCIE_ATS_CNTL_VF_11 0x0803
-#define mmVM_PCIE_ATS_CNTL_VF_11_BASE_IDX 0
-#define mmVM_PCIE_ATS_CNTL_VF_12 0x0804
-#define mmVM_PCIE_ATS_CNTL_VF_12_BASE_IDX 0
-#define mmVM_PCIE_ATS_CNTL_VF_13 0x0805
-#define mmVM_PCIE_ATS_CNTL_VF_13_BASE_IDX 0
-#define mmVM_PCIE_ATS_CNTL_VF_14 0x0806
-#define mmVM_PCIE_ATS_CNTL_VF_14_BASE_IDX 0
-#define mmVM_PCIE_ATS_CNTL_VF_15 0x0807
-#define mmVM_PCIE_ATS_CNTL_VF_15_BASE_IDX 0
-#define mmUTCL2_CGTT_CLK_CTRL 0x0808
-#define mmUTCL2_CGTT_CLK_CTRL_BASE_IDX 0
-#define mmMC_SHARED_ACTIVE_FCN_ID 0x0809
-#define mmMC_SHARED_ACTIVE_FCN_ID_BASE_IDX 0
-#define mmMC_VM_XGMI_GPUIOV_ENABLE 0x080a
-#define mmMC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX 0
-
-
-// addressBlock: mmhub_utcl2_vmsharedpfdec
-// base address: 0x6a040
-#define mmMC_VM_NB_MMIOBASE 0x0810
-#define mmMC_VM_NB_MMIOBASE_BASE_IDX 0
-#define mmMC_VM_NB_MMIOLIMIT 0x0811
-#define mmMC_VM_NB_MMIOLIMIT_BASE_IDX 0
-#define mmMC_VM_NB_PCI_CTRL 0x0812
-#define mmMC_VM_NB_PCI_CTRL_BASE_IDX 0
-#define mmMC_VM_NB_PCI_ARB 0x0813
-#define mmMC_VM_NB_PCI_ARB_BASE_IDX 0
-#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1 0x0814
-#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 0
-#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2 0x0815
-#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 0
-#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2 0x0816
-#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 0
-#define mmMC_VM_FB_OFFSET 0x0817
-#define mmMC_VM_FB_OFFSET_BASE_IDX 0
-#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0818
-#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0
-#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0819
-#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0
-#define mmMC_VM_STEERING 0x081a
-#define mmMC_VM_STEERING_BASE_IDX 0
-#define mmMC_SHARED_VIRT_RESET_REQ 0x081b
-#define mmMC_SHARED_VIRT_RESET_REQ_BASE_IDX 0
-#define mmMC_MEM_POWER_LS 0x081c
-#define mmMC_MEM_POWER_LS_BASE_IDX 0
-#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x081d
-#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0
-#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x081e
-#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0
-#define mmMC_VM_APT_CNTL 0x081f
-#define mmMC_VM_APT_CNTL_BASE_IDX 0
-#define mmMC_VM_LOCAL_HBM_ADDRESS_START 0x0820
-#define mmMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 0
-#define mmMC_VM_LOCAL_HBM_ADDRESS_END 0x0821
-#define mmMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 0
-#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x0822
-#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 0
-#define mmMC_VM_XGMI_LFB_CNTL 0x0823
-#define mmMC_VM_XGMI_LFB_CNTL_BASE_IDX 0
-#define mmMC_VM_XGMI_LFB_SIZE 0x0824
-#define mmMC_VM_XGMI_LFB_SIZE_BASE_IDX 0
-
-
-// addressBlock: mmhub_utcl2_vmsharedvcdec
-// base address: 0x6a0b0
-#define mmMC_VM_FB_LOCATION_BASE 0x082c
-#define mmMC_VM_FB_LOCATION_BASE_BASE_IDX 0
-#define mmMC_VM_FB_LOCATION_TOP 0x082d
-#define mmMC_VM_FB_LOCATION_TOP_BASE_IDX 0
-#define mmMC_VM_AGP_TOP 0x082e
-#define mmMC_VM_AGP_TOP_BASE_IDX 0
-#define mmMC_VM_AGP_BOT 0x082f
-#define mmMC_VM_AGP_BOT_BASE_IDX 0
-#define mmMC_VM_AGP_BASE 0x0830
-#define mmMC_VM_AGP_BASE_BASE_IDX 0
-#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0831
-#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0
-#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0832
-#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0
-#define mmMC_VM_MX_L1_TLB_CNTL 0x0833
-#define mmMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0
-
-
-// addressBlock: mmhub_utcl2_atcl2pfcntrdec
-// base address: 0x6a100
-#define mmATC_L2_PERFCOUNTER_LO 0x0840
-#define mmATC_L2_PERFCOUNTER_LO_BASE_IDX 0
-#define mmATC_L2_PERFCOUNTER_HI 0x0841
-#define mmATC_L2_PERFCOUNTER_HI_BASE_IDX 0
-
-
-// addressBlock: mmhub_utcl2_atcl2pfcntldec
-// base address: 0x6a120
-#define mmATC_L2_PERFCOUNTER0_CFG 0x0848
-#define mmATC_L2_PERFCOUNTER0_CFG_BASE_IDX 0
-#define mmATC_L2_PERFCOUNTER1_CFG 0x0849
-#define mmATC_L2_PERFCOUNTER1_CFG_BASE_IDX 0
-#define mmATC_L2_PERFCOUNTER_RSLT_CNTL 0x084a
-#define mmATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_sh_mask.h
deleted file mode 100644
index 3936c1d8a..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_sh_mask.h
+++ /dev/null
@@ -1,10265 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _mmhub_9_3_0_SH_MASK_HEADER
-#define _mmhub_9_3_0_SH_MASK_HEADER
-
-
-// addressBlock: mmhub_dagbdec
-//DAGB0_RDCLI0
-#define DAGB0_RDCLI0__VIRT_CHAN__SHIFT 0x0
-#define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB0_RDCLI0__URG_HIGH__SHIFT 0x4
-#define DAGB0_RDCLI0__URG_LOW__SHIFT 0x8
-#define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB0_RDCLI0__MAX_BW__SHIFT 0xd
-#define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB0_RDCLI0__MIN_BW__SHIFT 0x16
-#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB0_RDCLI0__MAX_OSD__SHIFT 0x1a
-#define DAGB0_RDCLI0__VIRT_CHAN_MASK 0x00000007L
-#define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB0_RDCLI0__URG_HIGH_MASK 0x000000F0L
-#define DAGB0_RDCLI0__URG_LOW_MASK 0x00000F00L
-#define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB0_RDCLI0__MAX_BW_MASK 0x001FE000L
-#define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB0_RDCLI0__MIN_BW_MASK 0x01C00000L
-#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB0_RDCLI0__MAX_OSD_MASK 0xFC000000L
-//DAGB0_RDCLI1
-#define DAGB0_RDCLI1__VIRT_CHAN__SHIFT 0x0
-#define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB0_RDCLI1__URG_HIGH__SHIFT 0x4
-#define DAGB0_RDCLI1__URG_LOW__SHIFT 0x8
-#define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB0_RDCLI1__MAX_BW__SHIFT 0xd
-#define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB0_RDCLI1__MIN_BW__SHIFT 0x16
-#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB0_RDCLI1__MAX_OSD__SHIFT 0x1a
-#define DAGB0_RDCLI1__VIRT_CHAN_MASK 0x00000007L
-#define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB0_RDCLI1__URG_HIGH_MASK 0x000000F0L
-#define DAGB0_RDCLI1__URG_LOW_MASK 0x00000F00L
-#define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB0_RDCLI1__MAX_BW_MASK 0x001FE000L
-#define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB0_RDCLI1__MIN_BW_MASK 0x01C00000L
-#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB0_RDCLI1__MAX_OSD_MASK 0xFC000000L
-//DAGB0_RDCLI2
-#define DAGB0_RDCLI2__VIRT_CHAN__SHIFT 0x0
-#define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB0_RDCLI2__URG_HIGH__SHIFT 0x4
-#define DAGB0_RDCLI2__URG_LOW__SHIFT 0x8
-#define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB0_RDCLI2__MAX_BW__SHIFT 0xd
-#define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB0_RDCLI2__MIN_BW__SHIFT 0x16
-#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB0_RDCLI2__MAX_OSD__SHIFT 0x1a
-#define DAGB0_RDCLI2__VIRT_CHAN_MASK 0x00000007L
-#define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB0_RDCLI2__URG_HIGH_MASK 0x000000F0L
-#define DAGB0_RDCLI2__URG_LOW_MASK 0x00000F00L
-#define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB0_RDCLI2__MAX_BW_MASK 0x001FE000L
-#define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB0_RDCLI2__MIN_BW_MASK 0x01C00000L
-#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB0_RDCLI2__MAX_OSD_MASK 0xFC000000L
-//DAGB0_RDCLI3
-#define DAGB0_RDCLI3__VIRT_CHAN__SHIFT 0x0
-#define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB0_RDCLI3__URG_HIGH__SHIFT 0x4
-#define DAGB0_RDCLI3__URG_LOW__SHIFT 0x8
-#define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB0_RDCLI3__MAX_BW__SHIFT 0xd
-#define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB0_RDCLI3__MIN_BW__SHIFT 0x16
-#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB0_RDCLI3__MAX_OSD__SHIFT 0x1a
-#define DAGB0_RDCLI3__VIRT_CHAN_MASK 0x00000007L
-#define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB0_RDCLI3__URG_HIGH_MASK 0x000000F0L
-#define DAGB0_RDCLI3__URG_LOW_MASK 0x00000F00L
-#define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB0_RDCLI3__MAX_BW_MASK 0x001FE000L
-#define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB0_RDCLI3__MIN_BW_MASK 0x01C00000L
-#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB0_RDCLI3__MAX_OSD_MASK 0xFC000000L
-//DAGB0_RDCLI4
-#define DAGB0_RDCLI4__VIRT_CHAN__SHIFT 0x0
-#define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB0_RDCLI4__URG_HIGH__SHIFT 0x4
-#define DAGB0_RDCLI4__URG_LOW__SHIFT 0x8
-#define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB0_RDCLI4__MAX_BW__SHIFT 0xd
-#define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB0_RDCLI4__MIN_BW__SHIFT 0x16
-#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB0_RDCLI4__MAX_OSD__SHIFT 0x1a
-#define DAGB0_RDCLI4__VIRT_CHAN_MASK 0x00000007L
-#define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB0_RDCLI4__URG_HIGH_MASK 0x000000F0L
-#define DAGB0_RDCLI4__URG_LOW_MASK 0x00000F00L
-#define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB0_RDCLI4__MAX_BW_MASK 0x001FE000L
-#define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB0_RDCLI4__MIN_BW_MASK 0x01C00000L
-#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB0_RDCLI4__MAX_OSD_MASK 0xFC000000L
-//DAGB0_RDCLI5
-#define DAGB0_RDCLI5__VIRT_CHAN__SHIFT 0x0
-#define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB0_RDCLI5__URG_HIGH__SHIFT 0x4
-#define DAGB0_RDCLI5__URG_LOW__SHIFT 0x8
-#define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB0_RDCLI5__MAX_BW__SHIFT 0xd
-#define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB0_RDCLI5__MIN_BW__SHIFT 0x16
-#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB0_RDCLI5__MAX_OSD__SHIFT 0x1a
-#define DAGB0_RDCLI5__VIRT_CHAN_MASK 0x00000007L
-#define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB0_RDCLI5__URG_HIGH_MASK 0x000000F0L
-#define DAGB0_RDCLI5__URG_LOW_MASK 0x00000F00L
-#define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB0_RDCLI5__MAX_BW_MASK 0x001FE000L
-#define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB0_RDCLI5__MIN_BW_MASK 0x01C00000L
-#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB0_RDCLI5__MAX_OSD_MASK 0xFC000000L
-//DAGB0_RDCLI6
-#define DAGB0_RDCLI6__VIRT_CHAN__SHIFT 0x0
-#define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB0_RDCLI6__URG_HIGH__SHIFT 0x4
-#define DAGB0_RDCLI6__URG_LOW__SHIFT 0x8
-#define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB0_RDCLI6__MAX_BW__SHIFT 0xd
-#define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB0_RDCLI6__MIN_BW__SHIFT 0x16
-#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB0_RDCLI6__MAX_OSD__SHIFT 0x1a
-#define DAGB0_RDCLI6__VIRT_CHAN_MASK 0x00000007L
-#define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB0_RDCLI6__URG_HIGH_MASK 0x000000F0L
-#define DAGB0_RDCLI6__URG_LOW_MASK 0x00000F00L
-#define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB0_RDCLI6__MAX_BW_MASK 0x001FE000L
-#define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB0_RDCLI6__MIN_BW_MASK 0x01C00000L
-#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB0_RDCLI6__MAX_OSD_MASK 0xFC000000L
-//DAGB0_RDCLI7
-#define DAGB0_RDCLI7__VIRT_CHAN__SHIFT 0x0
-#define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB0_RDCLI7__URG_HIGH__SHIFT 0x4
-#define DAGB0_RDCLI7__URG_LOW__SHIFT 0x8
-#define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB0_RDCLI7__MAX_BW__SHIFT 0xd
-#define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB0_RDCLI7__MIN_BW__SHIFT 0x16
-#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB0_RDCLI7__MAX_OSD__SHIFT 0x1a
-#define DAGB0_RDCLI7__VIRT_CHAN_MASK 0x00000007L
-#define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB0_RDCLI7__URG_HIGH_MASK 0x000000F0L
-#define DAGB0_RDCLI7__URG_LOW_MASK 0x00000F00L
-#define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB0_RDCLI7__MAX_BW_MASK 0x001FE000L
-#define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB0_RDCLI7__MIN_BW_MASK 0x01C00000L
-#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB0_RDCLI7__MAX_OSD_MASK 0xFC000000L
-//DAGB0_RDCLI8
-#define DAGB0_RDCLI8__VIRT_CHAN__SHIFT 0x0
-#define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB0_RDCLI8__URG_HIGH__SHIFT 0x4
-#define DAGB0_RDCLI8__URG_LOW__SHIFT 0x8
-#define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB0_RDCLI8__MAX_BW__SHIFT 0xd
-#define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB0_RDCLI8__MIN_BW__SHIFT 0x16
-#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB0_RDCLI8__MAX_OSD__SHIFT 0x1a
-#define DAGB0_RDCLI8__VIRT_CHAN_MASK 0x00000007L
-#define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB0_RDCLI8__URG_HIGH_MASK 0x000000F0L
-#define DAGB0_RDCLI8__URG_LOW_MASK 0x00000F00L
-#define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB0_RDCLI8__MAX_BW_MASK 0x001FE000L
-#define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB0_RDCLI8__MIN_BW_MASK 0x01C00000L
-#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB0_RDCLI8__MAX_OSD_MASK 0xFC000000L
-//DAGB0_RDCLI9
-#define DAGB0_RDCLI9__VIRT_CHAN__SHIFT 0x0
-#define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB0_RDCLI9__URG_HIGH__SHIFT 0x4
-#define DAGB0_RDCLI9__URG_LOW__SHIFT 0x8
-#define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB0_RDCLI9__MAX_BW__SHIFT 0xd
-#define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB0_RDCLI9__MIN_BW__SHIFT 0x16
-#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB0_RDCLI9__MAX_OSD__SHIFT 0x1a
-#define DAGB0_RDCLI9__VIRT_CHAN_MASK 0x00000007L
-#define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB0_RDCLI9__URG_HIGH_MASK 0x000000F0L
-#define DAGB0_RDCLI9__URG_LOW_MASK 0x00000F00L
-#define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB0_RDCLI9__MAX_BW_MASK 0x001FE000L
-#define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB0_RDCLI9__MIN_BW_MASK 0x01C00000L
-#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB0_RDCLI9__MAX_OSD_MASK 0xFC000000L
-//DAGB0_RDCLI10
-#define DAGB0_RDCLI10__VIRT_CHAN__SHIFT 0x0
-#define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB0_RDCLI10__URG_HIGH__SHIFT 0x4
-#define DAGB0_RDCLI10__URG_LOW__SHIFT 0x8
-#define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB0_RDCLI10__MAX_BW__SHIFT 0xd
-#define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB0_RDCLI10__MIN_BW__SHIFT 0x16
-#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB0_RDCLI10__MAX_OSD__SHIFT 0x1a
-#define DAGB0_RDCLI10__VIRT_CHAN_MASK 0x00000007L
-#define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB0_RDCLI10__URG_HIGH_MASK 0x000000F0L
-#define DAGB0_RDCLI10__URG_LOW_MASK 0x00000F00L
-#define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB0_RDCLI10__MAX_BW_MASK 0x001FE000L
-#define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB0_RDCLI10__MIN_BW_MASK 0x01C00000L
-#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB0_RDCLI10__MAX_OSD_MASK 0xFC000000L
-//DAGB0_RDCLI11
-#define DAGB0_RDCLI11__VIRT_CHAN__SHIFT 0x0
-#define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB0_RDCLI11__URG_HIGH__SHIFT 0x4
-#define DAGB0_RDCLI11__URG_LOW__SHIFT 0x8
-#define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB0_RDCLI11__MAX_BW__SHIFT 0xd
-#define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB0_RDCLI11__MIN_BW__SHIFT 0x16
-#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB0_RDCLI11__MAX_OSD__SHIFT 0x1a
-#define DAGB0_RDCLI11__VIRT_CHAN_MASK 0x00000007L
-#define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB0_RDCLI11__URG_HIGH_MASK 0x000000F0L
-#define DAGB0_RDCLI11__URG_LOW_MASK 0x00000F00L
-#define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB0_RDCLI11__MAX_BW_MASK 0x001FE000L
-#define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB0_RDCLI11__MIN_BW_MASK 0x01C00000L
-#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB0_RDCLI11__MAX_OSD_MASK 0xFC000000L
-//DAGB0_RDCLI12
-#define DAGB0_RDCLI12__VIRT_CHAN__SHIFT 0x0
-#define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB0_RDCLI12__URG_HIGH__SHIFT 0x4
-#define DAGB0_RDCLI12__URG_LOW__SHIFT 0x8
-#define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB0_RDCLI12__MAX_BW__SHIFT 0xd
-#define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB0_RDCLI12__MIN_BW__SHIFT 0x16
-#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB0_RDCLI12__MAX_OSD__SHIFT 0x1a
-#define DAGB0_RDCLI12__VIRT_CHAN_MASK 0x00000007L
-#define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB0_RDCLI12__URG_HIGH_MASK 0x000000F0L
-#define DAGB0_RDCLI12__URG_LOW_MASK 0x00000F00L
-#define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB0_RDCLI12__MAX_BW_MASK 0x001FE000L
-#define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB0_RDCLI12__MIN_BW_MASK 0x01C00000L
-#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB0_RDCLI12__MAX_OSD_MASK 0xFC000000L
-//DAGB0_RDCLI13
-#define DAGB0_RDCLI13__VIRT_CHAN__SHIFT 0x0
-#define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB0_RDCLI13__URG_HIGH__SHIFT 0x4
-#define DAGB0_RDCLI13__URG_LOW__SHIFT 0x8
-#define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB0_RDCLI13__MAX_BW__SHIFT 0xd
-#define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB0_RDCLI13__MIN_BW__SHIFT 0x16
-#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB0_RDCLI13__MAX_OSD__SHIFT 0x1a
-#define DAGB0_RDCLI13__VIRT_CHAN_MASK 0x00000007L
-#define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB0_RDCLI13__URG_HIGH_MASK 0x000000F0L
-#define DAGB0_RDCLI13__URG_LOW_MASK 0x00000F00L
-#define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB0_RDCLI13__MAX_BW_MASK 0x001FE000L
-#define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB0_RDCLI13__MIN_BW_MASK 0x01C00000L
-#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB0_RDCLI13__MAX_OSD_MASK 0xFC000000L
-//DAGB0_RDCLI14
-#define DAGB0_RDCLI14__VIRT_CHAN__SHIFT 0x0
-#define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB0_RDCLI14__URG_HIGH__SHIFT 0x4
-#define DAGB0_RDCLI14__URG_LOW__SHIFT 0x8
-#define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB0_RDCLI14__MAX_BW__SHIFT 0xd
-#define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB0_RDCLI14__MIN_BW__SHIFT 0x16
-#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB0_RDCLI14__MAX_OSD__SHIFT 0x1a
-#define DAGB0_RDCLI14__VIRT_CHAN_MASK 0x00000007L
-#define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB0_RDCLI14__URG_HIGH_MASK 0x000000F0L
-#define DAGB0_RDCLI14__URG_LOW_MASK 0x00000F00L
-#define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB0_RDCLI14__MAX_BW_MASK 0x001FE000L
-#define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB0_RDCLI14__MIN_BW_MASK 0x01C00000L
-#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB0_RDCLI14__MAX_OSD_MASK 0xFC000000L
-//DAGB0_RDCLI15
-#define DAGB0_RDCLI15__VIRT_CHAN__SHIFT 0x0
-#define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB0_RDCLI15__URG_HIGH__SHIFT 0x4
-#define DAGB0_RDCLI15__URG_LOW__SHIFT 0x8
-#define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB0_RDCLI15__MAX_BW__SHIFT 0xd
-#define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB0_RDCLI15__MIN_BW__SHIFT 0x16
-#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB0_RDCLI15__MAX_OSD__SHIFT 0x1a
-#define DAGB0_RDCLI15__VIRT_CHAN_MASK 0x00000007L
-#define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB0_RDCLI15__URG_HIGH_MASK 0x000000F0L
-#define DAGB0_RDCLI15__URG_LOW_MASK 0x00000F00L
-#define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB0_RDCLI15__MAX_BW_MASK 0x001FE000L
-#define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB0_RDCLI15__MIN_BW_MASK 0x01C00000L
-#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB0_RDCLI15__MAX_OSD_MASK 0xFC000000L
-//DAGB0_RD_CNTL
-#define DAGB0_RD_CNTL__SCLK_FREQ__SHIFT 0x0
-#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4
-#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
-#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
-#define DAGB0_RD_CNTL__IO_LEVEL__SHIFT 0x11
-#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14
-#define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17
-#define DAGB0_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL
-#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L
-#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L
-#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L
-#define DAGB0_RD_CNTL__IO_LEVEL_MASK 0x000E0000L
-#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L
-#define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L
-//DAGB0_RD_GMI_CNTL
-#define DAGB0_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0
-#define DAGB0_RD_GMI_CNTL__LEVEL__SHIFT 0x6
-#define DAGB0_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9
-#define DAGB0_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd
-#define DAGB0_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL
-#define DAGB0_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L
-#define DAGB0_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L
-#define DAGB0_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L
-//DAGB0_RD_ADDR_DAGB
-#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0
-#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
-#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
-#define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7
-#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L
-#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
-#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
-#define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L
-//DAGB0_RD_OUTPUT_DAGB_MAX_BURST
-#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0
-#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4
-#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8
-#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc
-#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10
-#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14
-#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18
-#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c
-#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL
-#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L
-#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L
-#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L
-#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L
-#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L
-#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L
-#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L
-//DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER
-#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0
-#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4
-#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8
-#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc
-#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10
-#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14
-#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18
-#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c
-#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL
-#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L
-#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L
-#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L
-#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L
-#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L
-#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L
-#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L
-//DAGB0_RD_CGTT_CLK_CTRL
-#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
-#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
-#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
-#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
-#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
-#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
-#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
-#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
-#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
-#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
-#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
-#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
-//DAGB0_L1TLB_RD_CGTT_CLK_CTRL
-#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
-#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
-#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
-#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
-#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
-#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
-#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
-#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
-#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
-#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
-#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
-#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
-//DAGB0_ATCVM_RD_CGTT_CLK_CTRL
-#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
-#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
-#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
-#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
-#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
-#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
-#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
-#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
-#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
-#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
-#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
-#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
-//DAGB0_RD_ADDR_DAGB_MAX_BURST0
-#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
-#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
-#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
-#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
-#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
-#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
-#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
-#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
-#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
-#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
-#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
-#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
-#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
-#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
-#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
-#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
-//DAGB0_RD_ADDR_DAGB_LAZY_TIMER0
-#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
-#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
-#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
-#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
-#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
-#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
-#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
-#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
-#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
-#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
-#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
-#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
-#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
-#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
-#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
-#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
-//DAGB0_RD_ADDR_DAGB_MAX_BURST1
-#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
-#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
-#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
-#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
-#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
-#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
-#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
-#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
-#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
-#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
-#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
-#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
-#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
-#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
-#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
-#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
-//DAGB0_RD_ADDR_DAGB_LAZY_TIMER1
-#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
-#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
-#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
-#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
-#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
-#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
-#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
-#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
-#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
-#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
-#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
-#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
-#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
-#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
-#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
-#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
-//DAGB0_RD_VC0_CNTL
-#define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0
-#define DAGB0_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5
-#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb
-#define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT 0xc
-#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14
-#define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT 0x15
-#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
-#define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19
-#define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL
-#define DAGB0_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L
-#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
-#define DAGB0_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L
-#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
-#define DAGB0_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L
-#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
-#define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L
-//DAGB0_RD_VC1_CNTL
-#define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0
-#define DAGB0_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5
-#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb
-#define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT 0xc
-#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14
-#define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT 0x15
-#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
-#define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19
-#define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL
-#define DAGB0_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L
-#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
-#define DAGB0_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L
-#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
-#define DAGB0_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L
-#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
-#define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L
-//DAGB0_RD_VC2_CNTL
-#define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0
-#define DAGB0_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5
-#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb
-#define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT 0xc
-#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14
-#define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT 0x15
-#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
-#define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19
-#define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL
-#define DAGB0_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L
-#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
-#define DAGB0_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L
-#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
-#define DAGB0_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L
-#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
-#define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L
-//DAGB0_RD_VC3_CNTL
-#define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0
-#define DAGB0_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5
-#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb
-#define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT 0xc
-#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14
-#define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT 0x15
-#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
-#define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19
-#define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL
-#define DAGB0_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L
-#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
-#define DAGB0_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L
-#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
-#define DAGB0_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L
-#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
-#define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L
-//DAGB0_RD_VC4_CNTL
-#define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0
-#define DAGB0_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5
-#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb
-#define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT 0xc
-#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14
-#define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT 0x15
-#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
-#define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19
-#define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL
-#define DAGB0_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L
-#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
-#define DAGB0_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L
-#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
-#define DAGB0_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L
-#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
-#define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L
-//DAGB0_RD_VC5_CNTL
-#define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0
-#define DAGB0_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5
-#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb
-#define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT 0xc
-#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14
-#define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT 0x15
-#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
-#define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19
-#define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL
-#define DAGB0_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L
-#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
-#define DAGB0_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L
-#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
-#define DAGB0_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L
-#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
-#define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L
-//DAGB0_RD_VC6_CNTL
-#define DAGB0_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0
-#define DAGB0_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5
-#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb
-#define DAGB0_RD_VC6_CNTL__MAX_BW__SHIFT 0xc
-#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14
-#define DAGB0_RD_VC6_CNTL__MIN_BW__SHIFT 0x15
-#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
-#define DAGB0_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19
-#define DAGB0_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL
-#define DAGB0_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L
-#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
-#define DAGB0_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L
-#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
-#define DAGB0_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L
-#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
-#define DAGB0_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L
-//DAGB0_RD_VC7_CNTL
-#define DAGB0_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0
-#define DAGB0_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5
-#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb
-#define DAGB0_RD_VC7_CNTL__MAX_BW__SHIFT 0xc
-#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14
-#define DAGB0_RD_VC7_CNTL__MIN_BW__SHIFT 0x15
-#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
-#define DAGB0_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19
-#define DAGB0_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL
-#define DAGB0_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L
-#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
-#define DAGB0_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L
-#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
-#define DAGB0_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L
-#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
-#define DAGB0_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L
-//DAGB0_RD_CNTL_MISC
-#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0
-#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6
-#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd
-#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13
-#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14
-#define DAGB0_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15
-#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL
-#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L
-#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L
-#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L
-#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L
-#define DAGB0_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L
-//DAGB0_RD_TLB_CREDIT
-#define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT 0x0
-#define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT 0x5
-#define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa
-#define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT 0xf
-#define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT 0x14
-#define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT 0x19
-#define DAGB0_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL
-#define DAGB0_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L
-#define DAGB0_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L
-#define DAGB0_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L
-#define DAGB0_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L
-#define DAGB0_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L
-//DAGB0_RDCLI_ASK_PENDING
-#define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0
-#define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
-//DAGB0_RDCLI_GO_PENDING
-#define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT 0x0
-#define DAGB0_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
-//DAGB0_RDCLI_GBLSEND_PENDING
-#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0
-#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL
-//DAGB0_RDCLI_TLB_PENDING
-#define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0
-#define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL
-//DAGB0_RDCLI_OARB_PENDING
-#define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0
-#define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL
-//DAGB0_RDCLI_OSD_PENDING
-#define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0
-#define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
-//DAGB0_WRCLI0
-#define DAGB0_WRCLI0__VIRT_CHAN__SHIFT 0x0
-#define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB0_WRCLI0__URG_HIGH__SHIFT 0x4
-#define DAGB0_WRCLI0__URG_LOW__SHIFT 0x8
-#define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB0_WRCLI0__MAX_BW__SHIFT 0xd
-#define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB0_WRCLI0__MIN_BW__SHIFT 0x16
-#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB0_WRCLI0__MAX_OSD__SHIFT 0x1a
-#define DAGB0_WRCLI0__VIRT_CHAN_MASK 0x00000007L
-#define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB0_WRCLI0__URG_HIGH_MASK 0x000000F0L
-#define DAGB0_WRCLI0__URG_LOW_MASK 0x00000F00L
-#define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB0_WRCLI0__MAX_BW_MASK 0x001FE000L
-#define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB0_WRCLI0__MIN_BW_MASK 0x01C00000L
-#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB0_WRCLI0__MAX_OSD_MASK 0xFC000000L
-//DAGB0_WRCLI1
-#define DAGB0_WRCLI1__VIRT_CHAN__SHIFT 0x0
-#define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB0_WRCLI1__URG_HIGH__SHIFT 0x4
-#define DAGB0_WRCLI1__URG_LOW__SHIFT 0x8
-#define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB0_WRCLI1__MAX_BW__SHIFT 0xd
-#define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB0_WRCLI1__MIN_BW__SHIFT 0x16
-#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB0_WRCLI1__MAX_OSD__SHIFT 0x1a
-#define DAGB0_WRCLI1__VIRT_CHAN_MASK 0x00000007L
-#define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB0_WRCLI1__URG_HIGH_MASK 0x000000F0L
-#define DAGB0_WRCLI1__URG_LOW_MASK 0x00000F00L
-#define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB0_WRCLI1__MAX_BW_MASK 0x001FE000L
-#define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB0_WRCLI1__MIN_BW_MASK 0x01C00000L
-#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB0_WRCLI1__MAX_OSD_MASK 0xFC000000L
-//DAGB0_WRCLI2
-#define DAGB0_WRCLI2__VIRT_CHAN__SHIFT 0x0
-#define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB0_WRCLI2__URG_HIGH__SHIFT 0x4
-#define DAGB0_WRCLI2__URG_LOW__SHIFT 0x8
-#define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB0_WRCLI2__MAX_BW__SHIFT 0xd
-#define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB0_WRCLI2__MIN_BW__SHIFT 0x16
-#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB0_WRCLI2__MAX_OSD__SHIFT 0x1a
-#define DAGB0_WRCLI2__VIRT_CHAN_MASK 0x00000007L
-#define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB0_WRCLI2__URG_HIGH_MASK 0x000000F0L
-#define DAGB0_WRCLI2__URG_LOW_MASK 0x00000F00L
-#define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB0_WRCLI2__MAX_BW_MASK 0x001FE000L
-#define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB0_WRCLI2__MIN_BW_MASK 0x01C00000L
-#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB0_WRCLI2__MAX_OSD_MASK 0xFC000000L
-//DAGB0_WRCLI3
-#define DAGB0_WRCLI3__VIRT_CHAN__SHIFT 0x0
-#define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB0_WRCLI3__URG_HIGH__SHIFT 0x4
-#define DAGB0_WRCLI3__URG_LOW__SHIFT 0x8
-#define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB0_WRCLI3__MAX_BW__SHIFT 0xd
-#define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB0_WRCLI3__MIN_BW__SHIFT 0x16
-#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB0_WRCLI3__MAX_OSD__SHIFT 0x1a
-#define DAGB0_WRCLI3__VIRT_CHAN_MASK 0x00000007L
-#define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB0_WRCLI3__URG_HIGH_MASK 0x000000F0L
-#define DAGB0_WRCLI3__URG_LOW_MASK 0x00000F00L
-#define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB0_WRCLI3__MAX_BW_MASK 0x001FE000L
-#define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB0_WRCLI3__MIN_BW_MASK 0x01C00000L
-#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB0_WRCLI3__MAX_OSD_MASK 0xFC000000L
-//DAGB0_WRCLI4
-#define DAGB0_WRCLI4__VIRT_CHAN__SHIFT 0x0
-#define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB0_WRCLI4__URG_HIGH__SHIFT 0x4
-#define DAGB0_WRCLI4__URG_LOW__SHIFT 0x8
-#define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB0_WRCLI4__MAX_BW__SHIFT 0xd
-#define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB0_WRCLI4__MIN_BW__SHIFT 0x16
-#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB0_WRCLI4__MAX_OSD__SHIFT 0x1a
-#define DAGB0_WRCLI4__VIRT_CHAN_MASK 0x00000007L
-#define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB0_WRCLI4__URG_HIGH_MASK 0x000000F0L
-#define DAGB0_WRCLI4__URG_LOW_MASK 0x00000F00L
-#define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB0_WRCLI4__MAX_BW_MASK 0x001FE000L
-#define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB0_WRCLI4__MIN_BW_MASK 0x01C00000L
-#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB0_WRCLI4__MAX_OSD_MASK 0xFC000000L
-//DAGB0_WRCLI5
-#define DAGB0_WRCLI5__VIRT_CHAN__SHIFT 0x0
-#define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB0_WRCLI5__URG_HIGH__SHIFT 0x4
-#define DAGB0_WRCLI5__URG_LOW__SHIFT 0x8
-#define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB0_WRCLI5__MAX_BW__SHIFT 0xd
-#define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB0_WRCLI5__MIN_BW__SHIFT 0x16
-#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB0_WRCLI5__MAX_OSD__SHIFT 0x1a
-#define DAGB0_WRCLI5__VIRT_CHAN_MASK 0x00000007L
-#define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB0_WRCLI5__URG_HIGH_MASK 0x000000F0L
-#define DAGB0_WRCLI5__URG_LOW_MASK 0x00000F00L
-#define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB0_WRCLI5__MAX_BW_MASK 0x001FE000L
-#define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB0_WRCLI5__MIN_BW_MASK 0x01C00000L
-#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB0_WRCLI5__MAX_OSD_MASK 0xFC000000L
-//DAGB0_WRCLI6
-#define DAGB0_WRCLI6__VIRT_CHAN__SHIFT 0x0
-#define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB0_WRCLI6__URG_HIGH__SHIFT 0x4
-#define DAGB0_WRCLI6__URG_LOW__SHIFT 0x8
-#define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB0_WRCLI6__MAX_BW__SHIFT 0xd
-#define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB0_WRCLI6__MIN_BW__SHIFT 0x16
-#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB0_WRCLI6__MAX_OSD__SHIFT 0x1a
-#define DAGB0_WRCLI6__VIRT_CHAN_MASK 0x00000007L
-#define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB0_WRCLI6__URG_HIGH_MASK 0x000000F0L
-#define DAGB0_WRCLI6__URG_LOW_MASK 0x00000F00L
-#define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB0_WRCLI6__MAX_BW_MASK 0x001FE000L
-#define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB0_WRCLI6__MIN_BW_MASK 0x01C00000L
-#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB0_WRCLI6__MAX_OSD_MASK 0xFC000000L
-//DAGB0_WRCLI7
-#define DAGB0_WRCLI7__VIRT_CHAN__SHIFT 0x0
-#define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB0_WRCLI7__URG_HIGH__SHIFT 0x4
-#define DAGB0_WRCLI7__URG_LOW__SHIFT 0x8
-#define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB0_WRCLI7__MAX_BW__SHIFT 0xd
-#define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB0_WRCLI7__MIN_BW__SHIFT 0x16
-#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB0_WRCLI7__MAX_OSD__SHIFT 0x1a
-#define DAGB0_WRCLI7__VIRT_CHAN_MASK 0x00000007L
-#define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB0_WRCLI7__URG_HIGH_MASK 0x000000F0L
-#define DAGB0_WRCLI7__URG_LOW_MASK 0x00000F00L
-#define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB0_WRCLI7__MAX_BW_MASK 0x001FE000L
-#define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB0_WRCLI7__MIN_BW_MASK 0x01C00000L
-#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB0_WRCLI7__MAX_OSD_MASK 0xFC000000L
-//DAGB0_WRCLI8
-#define DAGB0_WRCLI8__VIRT_CHAN__SHIFT 0x0
-#define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB0_WRCLI8__URG_HIGH__SHIFT 0x4
-#define DAGB0_WRCLI8__URG_LOW__SHIFT 0x8
-#define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB0_WRCLI8__MAX_BW__SHIFT 0xd
-#define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB0_WRCLI8__MIN_BW__SHIFT 0x16
-#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB0_WRCLI8__MAX_OSD__SHIFT 0x1a
-#define DAGB0_WRCLI8__VIRT_CHAN_MASK 0x00000007L
-#define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB0_WRCLI8__URG_HIGH_MASK 0x000000F0L
-#define DAGB0_WRCLI8__URG_LOW_MASK 0x00000F00L
-#define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB0_WRCLI8__MAX_BW_MASK 0x001FE000L
-#define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB0_WRCLI8__MIN_BW_MASK 0x01C00000L
-#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB0_WRCLI8__MAX_OSD_MASK 0xFC000000L
-//DAGB0_WRCLI9
-#define DAGB0_WRCLI9__VIRT_CHAN__SHIFT 0x0
-#define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB0_WRCLI9__URG_HIGH__SHIFT 0x4
-#define DAGB0_WRCLI9__URG_LOW__SHIFT 0x8
-#define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB0_WRCLI9__MAX_BW__SHIFT 0xd
-#define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB0_WRCLI9__MIN_BW__SHIFT 0x16
-#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB0_WRCLI9__MAX_OSD__SHIFT 0x1a
-#define DAGB0_WRCLI9__VIRT_CHAN_MASK 0x00000007L
-#define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB0_WRCLI9__URG_HIGH_MASK 0x000000F0L
-#define DAGB0_WRCLI9__URG_LOW_MASK 0x00000F00L
-#define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB0_WRCLI9__MAX_BW_MASK 0x001FE000L
-#define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB0_WRCLI9__MIN_BW_MASK 0x01C00000L
-#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB0_WRCLI9__MAX_OSD_MASK 0xFC000000L
-//DAGB0_WRCLI10
-#define DAGB0_WRCLI10__VIRT_CHAN__SHIFT 0x0
-#define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB0_WRCLI10__URG_HIGH__SHIFT 0x4
-#define DAGB0_WRCLI10__URG_LOW__SHIFT 0x8
-#define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB0_WRCLI10__MAX_BW__SHIFT 0xd
-#define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB0_WRCLI10__MIN_BW__SHIFT 0x16
-#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB0_WRCLI10__MAX_OSD__SHIFT 0x1a
-#define DAGB0_WRCLI10__VIRT_CHAN_MASK 0x00000007L
-#define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB0_WRCLI10__URG_HIGH_MASK 0x000000F0L
-#define DAGB0_WRCLI10__URG_LOW_MASK 0x00000F00L
-#define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB0_WRCLI10__MAX_BW_MASK 0x001FE000L
-#define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB0_WRCLI10__MIN_BW_MASK 0x01C00000L
-#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB0_WRCLI10__MAX_OSD_MASK 0xFC000000L
-//DAGB0_WRCLI11
-#define DAGB0_WRCLI11__VIRT_CHAN__SHIFT 0x0
-#define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB0_WRCLI11__URG_HIGH__SHIFT 0x4
-#define DAGB0_WRCLI11__URG_LOW__SHIFT 0x8
-#define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB0_WRCLI11__MAX_BW__SHIFT 0xd
-#define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB0_WRCLI11__MIN_BW__SHIFT 0x16
-#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB0_WRCLI11__MAX_OSD__SHIFT 0x1a
-#define DAGB0_WRCLI11__VIRT_CHAN_MASK 0x00000007L
-#define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB0_WRCLI11__URG_HIGH_MASK 0x000000F0L
-#define DAGB0_WRCLI11__URG_LOW_MASK 0x00000F00L
-#define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB0_WRCLI11__MAX_BW_MASK 0x001FE000L
-#define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB0_WRCLI11__MIN_BW_MASK 0x01C00000L
-#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB0_WRCLI11__MAX_OSD_MASK 0xFC000000L
-//DAGB0_WRCLI12
-#define DAGB0_WRCLI12__VIRT_CHAN__SHIFT 0x0
-#define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB0_WRCLI12__URG_HIGH__SHIFT 0x4
-#define DAGB0_WRCLI12__URG_LOW__SHIFT 0x8
-#define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB0_WRCLI12__MAX_BW__SHIFT 0xd
-#define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB0_WRCLI12__MIN_BW__SHIFT 0x16
-#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB0_WRCLI12__MAX_OSD__SHIFT 0x1a
-#define DAGB0_WRCLI12__VIRT_CHAN_MASK 0x00000007L
-#define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB0_WRCLI12__URG_HIGH_MASK 0x000000F0L
-#define DAGB0_WRCLI12__URG_LOW_MASK 0x00000F00L
-#define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB0_WRCLI12__MAX_BW_MASK 0x001FE000L
-#define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB0_WRCLI12__MIN_BW_MASK 0x01C00000L
-#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB0_WRCLI12__MAX_OSD_MASK 0xFC000000L
-//DAGB0_WRCLI13
-#define DAGB0_WRCLI13__VIRT_CHAN__SHIFT 0x0
-#define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB0_WRCLI13__URG_HIGH__SHIFT 0x4
-#define DAGB0_WRCLI13__URG_LOW__SHIFT 0x8
-#define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB0_WRCLI13__MAX_BW__SHIFT 0xd
-#define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB0_WRCLI13__MIN_BW__SHIFT 0x16
-#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB0_WRCLI13__MAX_OSD__SHIFT 0x1a
-#define DAGB0_WRCLI13__VIRT_CHAN_MASK 0x00000007L
-#define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB0_WRCLI13__URG_HIGH_MASK 0x000000F0L
-#define DAGB0_WRCLI13__URG_LOW_MASK 0x00000F00L
-#define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB0_WRCLI13__MAX_BW_MASK 0x001FE000L
-#define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB0_WRCLI13__MIN_BW_MASK 0x01C00000L
-#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB0_WRCLI13__MAX_OSD_MASK 0xFC000000L
-//DAGB0_WRCLI14
-#define DAGB0_WRCLI14__VIRT_CHAN__SHIFT 0x0
-#define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB0_WRCLI14__URG_HIGH__SHIFT 0x4
-#define DAGB0_WRCLI14__URG_LOW__SHIFT 0x8
-#define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB0_WRCLI14__MAX_BW__SHIFT 0xd
-#define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB0_WRCLI14__MIN_BW__SHIFT 0x16
-#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB0_WRCLI14__MAX_OSD__SHIFT 0x1a
-#define DAGB0_WRCLI14__VIRT_CHAN_MASK 0x00000007L
-#define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB0_WRCLI14__URG_HIGH_MASK 0x000000F0L
-#define DAGB0_WRCLI14__URG_LOW_MASK 0x00000F00L
-#define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB0_WRCLI14__MAX_BW_MASK 0x001FE000L
-#define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB0_WRCLI14__MIN_BW_MASK 0x01C00000L
-#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB0_WRCLI14__MAX_OSD_MASK 0xFC000000L
-//DAGB0_WRCLI15
-#define DAGB0_WRCLI15__VIRT_CHAN__SHIFT 0x0
-#define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB0_WRCLI15__URG_HIGH__SHIFT 0x4
-#define DAGB0_WRCLI15__URG_LOW__SHIFT 0x8
-#define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB0_WRCLI15__MAX_BW__SHIFT 0xd
-#define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB0_WRCLI15__MIN_BW__SHIFT 0x16
-#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB0_WRCLI15__MAX_OSD__SHIFT 0x1a
-#define DAGB0_WRCLI15__VIRT_CHAN_MASK 0x00000007L
-#define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB0_WRCLI15__URG_HIGH_MASK 0x000000F0L
-#define DAGB0_WRCLI15__URG_LOW_MASK 0x00000F00L
-#define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB0_WRCLI15__MAX_BW_MASK 0x001FE000L
-#define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB0_WRCLI15__MIN_BW_MASK 0x01C00000L
-#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB0_WRCLI15__MAX_OSD_MASK 0xFC000000L
-//DAGB0_WR_CNTL
-#define DAGB0_WR_CNTL__SCLK_FREQ__SHIFT 0x0
-#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4
-#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
-#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
-#define DAGB0_WR_CNTL__IO_LEVEL__SHIFT 0x11
-#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14
-#define DAGB0_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17
-#define DAGB0_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL
-#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L
-#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L
-#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L
-#define DAGB0_WR_CNTL__IO_LEVEL_MASK 0x000E0000L
-#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L
-#define DAGB0_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L
-//DAGB0_WR_GMI_CNTL
-#define DAGB0_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0
-#define DAGB0_WR_GMI_CNTL__LEVEL__SHIFT 0x6
-#define DAGB0_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9
-#define DAGB0_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd
-#define DAGB0_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL
-#define DAGB0_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L
-#define DAGB0_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L
-#define DAGB0_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L
-//DAGB0_WR_ADDR_DAGB
-#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0
-#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
-#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
-#define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7
-#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L
-#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
-#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
-#define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L
-//DAGB0_WR_OUTPUT_DAGB_MAX_BURST
-#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0
-#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4
-#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8
-#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc
-#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10
-#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14
-#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18
-#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c
-#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL
-#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L
-#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L
-#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L
-#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L
-#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L
-#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L
-#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L
-//DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER
-#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0
-#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4
-#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8
-#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc
-#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10
-#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14
-#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18
-#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c
-#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL
-#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L
-#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L
-#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L
-#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L
-#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L
-#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L
-#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L
-//DAGB0_WR_CGTT_CLK_CTRL
-#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
-#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
-#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
-#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
-#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
-#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
-#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
-#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
-#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
-#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
-#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
-#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
-//DAGB0_L1TLB_WR_CGTT_CLK_CTRL
-#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
-#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
-#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
-#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
-#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
-#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
-#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
-#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
-#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
-#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
-#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
-#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
-//DAGB0_ATCVM_WR_CGTT_CLK_CTRL
-#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
-#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
-#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
-#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
-#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
-#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
-#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
-#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
-#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
-#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
-#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
-#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
-//DAGB0_WR_ADDR_DAGB_MAX_BURST0
-#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
-#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
-#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
-#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
-#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
-#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
-#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
-#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
-#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
-#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
-#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
-#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
-#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
-#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
-#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
-#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
-//DAGB0_WR_ADDR_DAGB_LAZY_TIMER0
-#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
-#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
-#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
-#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
-#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
-#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
-#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
-#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
-#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
-#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
-#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
-#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
-#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
-#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
-#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
-#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
-//DAGB0_WR_ADDR_DAGB_MAX_BURST1
-#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
-#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
-#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
-#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
-#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
-#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
-#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
-#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
-#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
-#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
-#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
-#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
-#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
-#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
-#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
-#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
-//DAGB0_WR_ADDR_DAGB_LAZY_TIMER1
-#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
-#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
-#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
-#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
-#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
-#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
-#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
-#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
-#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
-#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
-#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
-#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
-#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
-#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
-#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
-#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
-//DAGB0_WR_DATA_DAGB
-#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0
-#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
-#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
-#define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT 0x7
-#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L
-#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
-#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
-#define DAGB0_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L
-//DAGB0_WR_DATA_DAGB_MAX_BURST0
-#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
-#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
-#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
-#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
-#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
-#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
-#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
-#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
-#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
-#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
-#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
-#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
-#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
-#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
-#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
-#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
-//DAGB0_WR_DATA_DAGB_LAZY_TIMER0
-#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
-#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
-#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
-#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
-#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
-#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
-#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
-#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
-#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
-#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
-#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
-#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
-#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
-#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
-#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
-#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
-//DAGB0_WR_DATA_DAGB_MAX_BURST1
-#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
-#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
-#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
-#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
-#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
-#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
-#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
-#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
-#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
-#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
-#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
-#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
-#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
-#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
-#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
-#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
-//DAGB0_WR_DATA_DAGB_LAZY_TIMER1
-#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
-#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
-#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
-#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
-#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
-#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
-#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
-#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
-#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
-#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
-#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
-#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
-#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
-#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
-#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
-#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
-//DAGB0_WR_VC0_CNTL
-#define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0
-#define DAGB0_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5
-#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb
-#define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT 0xc
-#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14
-#define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT 0x15
-#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
-#define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19
-#define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL
-#define DAGB0_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L
-#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
-#define DAGB0_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L
-#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
-#define DAGB0_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L
-#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
-#define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L
-//DAGB0_WR_VC1_CNTL
-#define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0
-#define DAGB0_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5
-#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb
-#define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT 0xc
-#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14
-#define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT 0x15
-#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
-#define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19
-#define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL
-#define DAGB0_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L
-#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
-#define DAGB0_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L
-#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
-#define DAGB0_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L
-#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
-#define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L
-//DAGB0_WR_VC2_CNTL
-#define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0
-#define DAGB0_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5
-#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb
-#define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT 0xc
-#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14
-#define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT 0x15
-#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
-#define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19
-#define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL
-#define DAGB0_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L
-#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
-#define DAGB0_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L
-#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
-#define DAGB0_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L
-#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
-#define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L
-//DAGB0_WR_VC3_CNTL
-#define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0
-#define DAGB0_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5
-#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb
-#define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT 0xc
-#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14
-#define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT 0x15
-#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
-#define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19
-#define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL
-#define DAGB0_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L
-#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
-#define DAGB0_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L
-#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
-#define DAGB0_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L
-#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
-#define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L
-//DAGB0_WR_VC4_CNTL
-#define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0
-#define DAGB0_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5
-#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb
-#define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT 0xc
-#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14
-#define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT 0x15
-#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
-#define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19
-#define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL
-#define DAGB0_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L
-#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
-#define DAGB0_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L
-#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
-#define DAGB0_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L
-#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
-#define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L
-//DAGB0_WR_VC5_CNTL
-#define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0
-#define DAGB0_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5
-#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb
-#define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT 0xc
-#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14
-#define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT 0x15
-#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
-#define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19
-#define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL
-#define DAGB0_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L
-#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
-#define DAGB0_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L
-#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
-#define DAGB0_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L
-#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
-#define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L
-//DAGB0_WR_VC6_CNTL
-#define DAGB0_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0
-#define DAGB0_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5
-#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb
-#define DAGB0_WR_VC6_CNTL__MAX_BW__SHIFT 0xc
-#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14
-#define DAGB0_WR_VC6_CNTL__MIN_BW__SHIFT 0x15
-#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
-#define DAGB0_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19
-#define DAGB0_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL
-#define DAGB0_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L
-#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
-#define DAGB0_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L
-#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
-#define DAGB0_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L
-#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
-#define DAGB0_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L
-//DAGB0_WR_VC7_CNTL
-#define DAGB0_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0
-#define DAGB0_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5
-#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb
-#define DAGB0_WR_VC7_CNTL__MAX_BW__SHIFT 0xc
-#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14
-#define DAGB0_WR_VC7_CNTL__MIN_BW__SHIFT 0x15
-#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
-#define DAGB0_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19
-#define DAGB0_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL
-#define DAGB0_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L
-#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
-#define DAGB0_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L
-#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
-#define DAGB0_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L
-#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
-#define DAGB0_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L
-//DAGB0_WR_CNTL_MISC
-#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0
-#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6
-#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd
-#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13
-#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14
-#define DAGB0_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15
-#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL
-#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L
-#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L
-#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L
-#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L
-#define DAGB0_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L
-//DAGB0_WR_TLB_CREDIT
-#define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT 0x0
-#define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT 0x5
-#define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa
-#define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT 0xf
-#define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT 0x14
-#define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT 0x19
-#define DAGB0_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL
-#define DAGB0_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L
-#define DAGB0_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L
-#define DAGB0_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L
-#define DAGB0_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L
-#define DAGB0_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L
-//DAGB0_WR_DATA_CREDIT
-#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0
-#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8
-#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10
-#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18
-#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL
-#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L
-#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L
-#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L
-//DAGB0_WR_MISC_CREDIT
-#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0
-#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6
-#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9
-#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10
-#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL
-#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L
-#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L
-#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L
-//DAGB0_WRCLI_ASK_PENDING
-#define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0
-#define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
-//DAGB0_WRCLI_GO_PENDING
-#define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT 0x0
-#define DAGB0_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
-//DAGB0_WRCLI_GBLSEND_PENDING
-#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0
-#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL
-//DAGB0_WRCLI_TLB_PENDING
-#define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0
-#define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL
-//DAGB0_WRCLI_OARB_PENDING
-#define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0
-#define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL
-//DAGB0_WRCLI_OSD_PENDING
-#define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0
-#define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
-//DAGB0_WRCLI_DBUS_ASK_PENDING
-#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0
-#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
-//DAGB0_WRCLI_DBUS_GO_PENDING
-#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0
-#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
-//DAGB0_DAGB_DLY
-#define DAGB0_DAGB_DLY__DLY__SHIFT 0x0
-#define DAGB0_DAGB_DLY__CLI__SHIFT 0x8
-#define DAGB0_DAGB_DLY__POS__SHIFT 0x10
-#define DAGB0_DAGB_DLY__DLY_MASK 0x000000FFL
-#define DAGB0_DAGB_DLY__CLI_MASK 0x0000FF00L
-#define DAGB0_DAGB_DLY__POS_MASK 0x000F0000L
-//DAGB0_CNTL_MISC
-#define DAGB0_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0
-#define DAGB0_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3
-#define DAGB0_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6
-#define DAGB0_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9
-#define DAGB0_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc
-#define DAGB0_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf
-#define DAGB0_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12
-#define DAGB0_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15
-#define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18
-#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e
-#define DAGB0_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L
-#define DAGB0_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L
-#define DAGB0_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L
-#define DAGB0_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L
-#define DAGB0_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L
-#define DAGB0_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L
-#define DAGB0_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L
-#define DAGB0_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L
-#define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L
-#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L
-//DAGB0_CNTL_MISC2
-#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0
-#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1
-#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2
-#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3
-#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4
-#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5
-#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6
-#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7
-#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8
-#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9
-#define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0xa
-#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L
-#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L
-#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L
-#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L
-#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L
-#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L
-#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L
-#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L
-#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L
-#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L
-#define DAGB0_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L
-//DAGB0_FIFO_EMPTY
-#define DAGB0_FIFO_EMPTY__EMPTY__SHIFT 0x0
-#define DAGB0_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL
-//DAGB0_FIFO_FULL
-#define DAGB0_FIFO_FULL__FULL__SHIFT 0x0
-#define DAGB0_FIFO_FULL__FULL_MASK 0x007FFFFFL
-//DAGB0_WR_CREDITS_FULL
-#define DAGB0_WR_CREDITS_FULL__FULL__SHIFT 0x0
-#define DAGB0_WR_CREDITS_FULL__FULL_MASK 0x0007FFFFL
-//DAGB0_RD_CREDITS_FULL
-#define DAGB0_RD_CREDITS_FULL__FULL__SHIFT 0x0
-#define DAGB0_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL
-//DAGB0_PERFCOUNTER_LO
-#define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
-#define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
-//DAGB0_PERFCOUNTER_HI
-#define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
-#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
-#define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
-#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
-//DAGB0_PERFCOUNTER0_CFG
-#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
-#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
-#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
-#define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
-#define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
-#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
-#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
-#define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
-#define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
-//DAGB0_PERFCOUNTER1_CFG
-#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
-#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
-#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
-#define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
-#define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
-#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
-#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
-#define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
-#define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
-//DAGB0_PERFCOUNTER2_CFG
-#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
-#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
-#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
-#define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
-#define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
-#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
-#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
-#define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
-#define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
-//DAGB0_PERFCOUNTER_RSLT_CNTL
-#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
-#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
-#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
-#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
-#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
-#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
-#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
-#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
-#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
-#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
-#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
-#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
-//DAGB0_RESERVE0
-#define DAGB0_RESERVE0__RESERVE__SHIFT 0x0
-#define DAGB0_RESERVE0__RESERVE_MASK 0xFFFFFFFFL
-//DAGB0_RESERVE1
-#define DAGB0_RESERVE1__RESERVE__SHIFT 0x0
-#define DAGB0_RESERVE1__RESERVE_MASK 0xFFFFFFFFL
-//DAGB0_RESERVE2
-#define DAGB0_RESERVE2__RESERVE__SHIFT 0x0
-#define DAGB0_RESERVE2__RESERVE_MASK 0xFFFFFFFFL
-//DAGB0_RESERVE3
-#define DAGB0_RESERVE3__RESERVE__SHIFT 0x0
-#define DAGB0_RESERVE3__RESERVE_MASK 0xFFFFFFFFL
-//DAGB0_RESERVE4
-#define DAGB0_RESERVE4__RESERVE__SHIFT 0x0
-#define DAGB0_RESERVE4__RESERVE_MASK 0xFFFFFFFFL
-//DAGB0_RESERVE5
-#define DAGB0_RESERVE5__RESERVE__SHIFT 0x0
-#define DAGB0_RESERVE5__RESERVE_MASK 0xFFFFFFFFL
-//DAGB0_RESERVE6
-#define DAGB0_RESERVE6__RESERVE__SHIFT 0x0
-#define DAGB0_RESERVE6__RESERVE_MASK 0xFFFFFFFFL
-//DAGB0_RESERVE7
-#define DAGB0_RESERVE7__RESERVE__SHIFT 0x0
-#define DAGB0_RESERVE7__RESERVE_MASK 0xFFFFFFFFL
-//DAGB0_RESERVE8
-#define DAGB0_RESERVE8__RESERVE__SHIFT 0x0
-#define DAGB0_RESERVE8__RESERVE_MASK 0xFFFFFFFFL
-//DAGB0_RESERVE9
-#define DAGB0_RESERVE9__RESERVE__SHIFT 0x0
-#define DAGB0_RESERVE9__RESERVE_MASK 0xFFFFFFFFL
-//DAGB0_RESERVE10
-#define DAGB0_RESERVE10__RESERVE__SHIFT 0x0
-#define DAGB0_RESERVE10__RESERVE_MASK 0xFFFFFFFFL
-//DAGB0_RESERVE11
-#define DAGB0_RESERVE11__RESERVE__SHIFT 0x0
-#define DAGB0_RESERVE11__RESERVE_MASK 0xFFFFFFFFL
-//DAGB0_RESERVE12
-#define DAGB0_RESERVE12__RESERVE__SHIFT 0x0
-#define DAGB0_RESERVE12__RESERVE_MASK 0xFFFFFFFFL
-//DAGB0_RESERVE13
-#define DAGB0_RESERVE13__RESERVE__SHIFT 0x0
-#define DAGB0_RESERVE13__RESERVE_MASK 0xFFFFFFFFL
-//DAGB0_RESERVE14
-#define DAGB0_RESERVE14__RESERVE__SHIFT 0x0
-#define DAGB0_RESERVE14__RESERVE_MASK 0xFFFFFFFFL
-//DAGB0_RESERVE15
-#define DAGB0_RESERVE15__RESERVE__SHIFT 0x0
-#define DAGB0_RESERVE15__RESERVE_MASK 0xFFFFFFFFL
-//DAGB0_RESERVE16
-#define DAGB0_RESERVE16__RESERVE__SHIFT 0x0
-#define DAGB0_RESERVE16__RESERVE_MASK 0xFFFFFFFFL
-//DAGB0_RESERVE17
-#define DAGB0_RESERVE17__RESERVE__SHIFT 0x0
-#define DAGB0_RESERVE17__RESERVE_MASK 0xFFFFFFFFL
-//DAGB1_RDCLI0
-#define DAGB1_RDCLI0__VIRT_CHAN__SHIFT 0x0
-#define DAGB1_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB1_RDCLI0__URG_HIGH__SHIFT 0x4
-#define DAGB1_RDCLI0__URG_LOW__SHIFT 0x8
-#define DAGB1_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB1_RDCLI0__MAX_BW__SHIFT 0xd
-#define DAGB1_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB1_RDCLI0__MIN_BW__SHIFT 0x16
-#define DAGB1_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB1_RDCLI0__MAX_OSD__SHIFT 0x1a
-#define DAGB1_RDCLI0__VIRT_CHAN_MASK 0x00000007L
-#define DAGB1_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB1_RDCLI0__URG_HIGH_MASK 0x000000F0L
-#define DAGB1_RDCLI0__URG_LOW_MASK 0x00000F00L
-#define DAGB1_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB1_RDCLI0__MAX_BW_MASK 0x001FE000L
-#define DAGB1_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB1_RDCLI0__MIN_BW_MASK 0x01C00000L
-#define DAGB1_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB1_RDCLI0__MAX_OSD_MASK 0xFC000000L
-//DAGB1_RDCLI1
-#define DAGB1_RDCLI1__VIRT_CHAN__SHIFT 0x0
-#define DAGB1_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB1_RDCLI1__URG_HIGH__SHIFT 0x4
-#define DAGB1_RDCLI1__URG_LOW__SHIFT 0x8
-#define DAGB1_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB1_RDCLI1__MAX_BW__SHIFT 0xd
-#define DAGB1_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB1_RDCLI1__MIN_BW__SHIFT 0x16
-#define DAGB1_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB1_RDCLI1__MAX_OSD__SHIFT 0x1a
-#define DAGB1_RDCLI1__VIRT_CHAN_MASK 0x00000007L
-#define DAGB1_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB1_RDCLI1__URG_HIGH_MASK 0x000000F0L
-#define DAGB1_RDCLI1__URG_LOW_MASK 0x00000F00L
-#define DAGB1_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB1_RDCLI1__MAX_BW_MASK 0x001FE000L
-#define DAGB1_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB1_RDCLI1__MIN_BW_MASK 0x01C00000L
-#define DAGB1_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB1_RDCLI1__MAX_OSD_MASK 0xFC000000L
-//DAGB1_RDCLI2
-#define DAGB1_RDCLI2__VIRT_CHAN__SHIFT 0x0
-#define DAGB1_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB1_RDCLI2__URG_HIGH__SHIFT 0x4
-#define DAGB1_RDCLI2__URG_LOW__SHIFT 0x8
-#define DAGB1_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB1_RDCLI2__MAX_BW__SHIFT 0xd
-#define DAGB1_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB1_RDCLI2__MIN_BW__SHIFT 0x16
-#define DAGB1_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB1_RDCLI2__MAX_OSD__SHIFT 0x1a
-#define DAGB1_RDCLI2__VIRT_CHAN_MASK 0x00000007L
-#define DAGB1_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB1_RDCLI2__URG_HIGH_MASK 0x000000F0L
-#define DAGB1_RDCLI2__URG_LOW_MASK 0x00000F00L
-#define DAGB1_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB1_RDCLI2__MAX_BW_MASK 0x001FE000L
-#define DAGB1_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB1_RDCLI2__MIN_BW_MASK 0x01C00000L
-#define DAGB1_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB1_RDCLI2__MAX_OSD_MASK 0xFC000000L
-//DAGB1_RDCLI3
-#define DAGB1_RDCLI3__VIRT_CHAN__SHIFT 0x0
-#define DAGB1_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB1_RDCLI3__URG_HIGH__SHIFT 0x4
-#define DAGB1_RDCLI3__URG_LOW__SHIFT 0x8
-#define DAGB1_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB1_RDCLI3__MAX_BW__SHIFT 0xd
-#define DAGB1_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB1_RDCLI3__MIN_BW__SHIFT 0x16
-#define DAGB1_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB1_RDCLI3__MAX_OSD__SHIFT 0x1a
-#define DAGB1_RDCLI3__VIRT_CHAN_MASK 0x00000007L
-#define DAGB1_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB1_RDCLI3__URG_HIGH_MASK 0x000000F0L
-#define DAGB1_RDCLI3__URG_LOW_MASK 0x00000F00L
-#define DAGB1_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB1_RDCLI3__MAX_BW_MASK 0x001FE000L
-#define DAGB1_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB1_RDCLI3__MIN_BW_MASK 0x01C00000L
-#define DAGB1_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB1_RDCLI3__MAX_OSD_MASK 0xFC000000L
-//DAGB1_RDCLI4
-#define DAGB1_RDCLI4__VIRT_CHAN__SHIFT 0x0
-#define DAGB1_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB1_RDCLI4__URG_HIGH__SHIFT 0x4
-#define DAGB1_RDCLI4__URG_LOW__SHIFT 0x8
-#define DAGB1_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB1_RDCLI4__MAX_BW__SHIFT 0xd
-#define DAGB1_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB1_RDCLI4__MIN_BW__SHIFT 0x16
-#define DAGB1_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB1_RDCLI4__MAX_OSD__SHIFT 0x1a
-#define DAGB1_RDCLI4__VIRT_CHAN_MASK 0x00000007L
-#define DAGB1_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB1_RDCLI4__URG_HIGH_MASK 0x000000F0L
-#define DAGB1_RDCLI4__URG_LOW_MASK 0x00000F00L
-#define DAGB1_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB1_RDCLI4__MAX_BW_MASK 0x001FE000L
-#define DAGB1_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB1_RDCLI4__MIN_BW_MASK 0x01C00000L
-#define DAGB1_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB1_RDCLI4__MAX_OSD_MASK 0xFC000000L
-//DAGB1_RDCLI5
-#define DAGB1_RDCLI5__VIRT_CHAN__SHIFT 0x0
-#define DAGB1_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB1_RDCLI5__URG_HIGH__SHIFT 0x4
-#define DAGB1_RDCLI5__URG_LOW__SHIFT 0x8
-#define DAGB1_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB1_RDCLI5__MAX_BW__SHIFT 0xd
-#define DAGB1_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB1_RDCLI5__MIN_BW__SHIFT 0x16
-#define DAGB1_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB1_RDCLI5__MAX_OSD__SHIFT 0x1a
-#define DAGB1_RDCLI5__VIRT_CHAN_MASK 0x00000007L
-#define DAGB1_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB1_RDCLI5__URG_HIGH_MASK 0x000000F0L
-#define DAGB1_RDCLI5__URG_LOW_MASK 0x00000F00L
-#define DAGB1_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB1_RDCLI5__MAX_BW_MASK 0x001FE000L
-#define DAGB1_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB1_RDCLI5__MIN_BW_MASK 0x01C00000L
-#define DAGB1_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB1_RDCLI5__MAX_OSD_MASK 0xFC000000L
-//DAGB1_RDCLI6
-#define DAGB1_RDCLI6__VIRT_CHAN__SHIFT 0x0
-#define DAGB1_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB1_RDCLI6__URG_HIGH__SHIFT 0x4
-#define DAGB1_RDCLI6__URG_LOW__SHIFT 0x8
-#define DAGB1_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB1_RDCLI6__MAX_BW__SHIFT 0xd
-#define DAGB1_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB1_RDCLI6__MIN_BW__SHIFT 0x16
-#define DAGB1_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB1_RDCLI6__MAX_OSD__SHIFT 0x1a
-#define DAGB1_RDCLI6__VIRT_CHAN_MASK 0x00000007L
-#define DAGB1_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB1_RDCLI6__URG_HIGH_MASK 0x000000F0L
-#define DAGB1_RDCLI6__URG_LOW_MASK 0x00000F00L
-#define DAGB1_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB1_RDCLI6__MAX_BW_MASK 0x001FE000L
-#define DAGB1_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB1_RDCLI6__MIN_BW_MASK 0x01C00000L
-#define DAGB1_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB1_RDCLI6__MAX_OSD_MASK 0xFC000000L
-//DAGB1_RDCLI7
-#define DAGB1_RDCLI7__VIRT_CHAN__SHIFT 0x0
-#define DAGB1_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB1_RDCLI7__URG_HIGH__SHIFT 0x4
-#define DAGB1_RDCLI7__URG_LOW__SHIFT 0x8
-#define DAGB1_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB1_RDCLI7__MAX_BW__SHIFT 0xd
-#define DAGB1_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB1_RDCLI7__MIN_BW__SHIFT 0x16
-#define DAGB1_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB1_RDCLI7__MAX_OSD__SHIFT 0x1a
-#define DAGB1_RDCLI7__VIRT_CHAN_MASK 0x00000007L
-#define DAGB1_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB1_RDCLI7__URG_HIGH_MASK 0x000000F0L
-#define DAGB1_RDCLI7__URG_LOW_MASK 0x00000F00L
-#define DAGB1_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB1_RDCLI7__MAX_BW_MASK 0x001FE000L
-#define DAGB1_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB1_RDCLI7__MIN_BW_MASK 0x01C00000L
-#define DAGB1_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB1_RDCLI7__MAX_OSD_MASK 0xFC000000L
-//DAGB1_RDCLI8
-#define DAGB1_RDCLI8__VIRT_CHAN__SHIFT 0x0
-#define DAGB1_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB1_RDCLI8__URG_HIGH__SHIFT 0x4
-#define DAGB1_RDCLI8__URG_LOW__SHIFT 0x8
-#define DAGB1_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB1_RDCLI8__MAX_BW__SHIFT 0xd
-#define DAGB1_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB1_RDCLI8__MIN_BW__SHIFT 0x16
-#define DAGB1_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB1_RDCLI8__MAX_OSD__SHIFT 0x1a
-#define DAGB1_RDCLI8__VIRT_CHAN_MASK 0x00000007L
-#define DAGB1_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB1_RDCLI8__URG_HIGH_MASK 0x000000F0L
-#define DAGB1_RDCLI8__URG_LOW_MASK 0x00000F00L
-#define DAGB1_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB1_RDCLI8__MAX_BW_MASK 0x001FE000L
-#define DAGB1_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB1_RDCLI8__MIN_BW_MASK 0x01C00000L
-#define DAGB1_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB1_RDCLI8__MAX_OSD_MASK 0xFC000000L
-//DAGB1_RDCLI9
-#define DAGB1_RDCLI9__VIRT_CHAN__SHIFT 0x0
-#define DAGB1_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB1_RDCLI9__URG_HIGH__SHIFT 0x4
-#define DAGB1_RDCLI9__URG_LOW__SHIFT 0x8
-#define DAGB1_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB1_RDCLI9__MAX_BW__SHIFT 0xd
-#define DAGB1_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB1_RDCLI9__MIN_BW__SHIFT 0x16
-#define DAGB1_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB1_RDCLI9__MAX_OSD__SHIFT 0x1a
-#define DAGB1_RDCLI9__VIRT_CHAN_MASK 0x00000007L
-#define DAGB1_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB1_RDCLI9__URG_HIGH_MASK 0x000000F0L
-#define DAGB1_RDCLI9__URG_LOW_MASK 0x00000F00L
-#define DAGB1_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB1_RDCLI9__MAX_BW_MASK 0x001FE000L
-#define DAGB1_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB1_RDCLI9__MIN_BW_MASK 0x01C00000L
-#define DAGB1_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB1_RDCLI9__MAX_OSD_MASK 0xFC000000L
-//DAGB1_RDCLI10
-#define DAGB1_RDCLI10__VIRT_CHAN__SHIFT 0x0
-#define DAGB1_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB1_RDCLI10__URG_HIGH__SHIFT 0x4
-#define DAGB1_RDCLI10__URG_LOW__SHIFT 0x8
-#define DAGB1_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB1_RDCLI10__MAX_BW__SHIFT 0xd
-#define DAGB1_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB1_RDCLI10__MIN_BW__SHIFT 0x16
-#define DAGB1_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB1_RDCLI10__MAX_OSD__SHIFT 0x1a
-#define DAGB1_RDCLI10__VIRT_CHAN_MASK 0x00000007L
-#define DAGB1_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB1_RDCLI10__URG_HIGH_MASK 0x000000F0L
-#define DAGB1_RDCLI10__URG_LOW_MASK 0x00000F00L
-#define DAGB1_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB1_RDCLI10__MAX_BW_MASK 0x001FE000L
-#define DAGB1_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB1_RDCLI10__MIN_BW_MASK 0x01C00000L
-#define DAGB1_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB1_RDCLI10__MAX_OSD_MASK 0xFC000000L
-//DAGB1_RDCLI11
-#define DAGB1_RDCLI11__VIRT_CHAN__SHIFT 0x0
-#define DAGB1_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB1_RDCLI11__URG_HIGH__SHIFT 0x4
-#define DAGB1_RDCLI11__URG_LOW__SHIFT 0x8
-#define DAGB1_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB1_RDCLI11__MAX_BW__SHIFT 0xd
-#define DAGB1_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB1_RDCLI11__MIN_BW__SHIFT 0x16
-#define DAGB1_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB1_RDCLI11__MAX_OSD__SHIFT 0x1a
-#define DAGB1_RDCLI11__VIRT_CHAN_MASK 0x00000007L
-#define DAGB1_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB1_RDCLI11__URG_HIGH_MASK 0x000000F0L
-#define DAGB1_RDCLI11__URG_LOW_MASK 0x00000F00L
-#define DAGB1_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB1_RDCLI11__MAX_BW_MASK 0x001FE000L
-#define DAGB1_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB1_RDCLI11__MIN_BW_MASK 0x01C00000L
-#define DAGB1_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB1_RDCLI11__MAX_OSD_MASK 0xFC000000L
-//DAGB1_RDCLI12
-#define DAGB1_RDCLI12__VIRT_CHAN__SHIFT 0x0
-#define DAGB1_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB1_RDCLI12__URG_HIGH__SHIFT 0x4
-#define DAGB1_RDCLI12__URG_LOW__SHIFT 0x8
-#define DAGB1_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB1_RDCLI12__MAX_BW__SHIFT 0xd
-#define DAGB1_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB1_RDCLI12__MIN_BW__SHIFT 0x16
-#define DAGB1_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB1_RDCLI12__MAX_OSD__SHIFT 0x1a
-#define DAGB1_RDCLI12__VIRT_CHAN_MASK 0x00000007L
-#define DAGB1_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB1_RDCLI12__URG_HIGH_MASK 0x000000F0L
-#define DAGB1_RDCLI12__URG_LOW_MASK 0x00000F00L
-#define DAGB1_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB1_RDCLI12__MAX_BW_MASK 0x001FE000L
-#define DAGB1_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB1_RDCLI12__MIN_BW_MASK 0x01C00000L
-#define DAGB1_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB1_RDCLI12__MAX_OSD_MASK 0xFC000000L
-//DAGB1_RDCLI13
-#define DAGB1_RDCLI13__VIRT_CHAN__SHIFT 0x0
-#define DAGB1_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB1_RDCLI13__URG_HIGH__SHIFT 0x4
-#define DAGB1_RDCLI13__URG_LOW__SHIFT 0x8
-#define DAGB1_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB1_RDCLI13__MAX_BW__SHIFT 0xd
-#define DAGB1_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB1_RDCLI13__MIN_BW__SHIFT 0x16
-#define DAGB1_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB1_RDCLI13__MAX_OSD__SHIFT 0x1a
-#define DAGB1_RDCLI13__VIRT_CHAN_MASK 0x00000007L
-#define DAGB1_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB1_RDCLI13__URG_HIGH_MASK 0x000000F0L
-#define DAGB1_RDCLI13__URG_LOW_MASK 0x00000F00L
-#define DAGB1_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB1_RDCLI13__MAX_BW_MASK 0x001FE000L
-#define DAGB1_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB1_RDCLI13__MIN_BW_MASK 0x01C00000L
-#define DAGB1_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB1_RDCLI13__MAX_OSD_MASK 0xFC000000L
-//DAGB1_RDCLI14
-#define DAGB1_RDCLI14__VIRT_CHAN__SHIFT 0x0
-#define DAGB1_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB1_RDCLI14__URG_HIGH__SHIFT 0x4
-#define DAGB1_RDCLI14__URG_LOW__SHIFT 0x8
-#define DAGB1_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB1_RDCLI14__MAX_BW__SHIFT 0xd
-#define DAGB1_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB1_RDCLI14__MIN_BW__SHIFT 0x16
-#define DAGB1_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB1_RDCLI14__MAX_OSD__SHIFT 0x1a
-#define DAGB1_RDCLI14__VIRT_CHAN_MASK 0x00000007L
-#define DAGB1_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB1_RDCLI14__URG_HIGH_MASK 0x000000F0L
-#define DAGB1_RDCLI14__URG_LOW_MASK 0x00000F00L
-#define DAGB1_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB1_RDCLI14__MAX_BW_MASK 0x001FE000L
-#define DAGB1_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB1_RDCLI14__MIN_BW_MASK 0x01C00000L
-#define DAGB1_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB1_RDCLI14__MAX_OSD_MASK 0xFC000000L
-//DAGB1_RDCLI15
-#define DAGB1_RDCLI15__VIRT_CHAN__SHIFT 0x0
-#define DAGB1_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB1_RDCLI15__URG_HIGH__SHIFT 0x4
-#define DAGB1_RDCLI15__URG_LOW__SHIFT 0x8
-#define DAGB1_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB1_RDCLI15__MAX_BW__SHIFT 0xd
-#define DAGB1_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB1_RDCLI15__MIN_BW__SHIFT 0x16
-#define DAGB1_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB1_RDCLI15__MAX_OSD__SHIFT 0x1a
-#define DAGB1_RDCLI15__VIRT_CHAN_MASK 0x00000007L
-#define DAGB1_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB1_RDCLI15__URG_HIGH_MASK 0x000000F0L
-#define DAGB1_RDCLI15__URG_LOW_MASK 0x00000F00L
-#define DAGB1_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB1_RDCLI15__MAX_BW_MASK 0x001FE000L
-#define DAGB1_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB1_RDCLI15__MIN_BW_MASK 0x01C00000L
-#define DAGB1_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB1_RDCLI15__MAX_OSD_MASK 0xFC000000L
-//DAGB1_RD_CNTL
-#define DAGB1_RD_CNTL__SCLK_FREQ__SHIFT 0x0
-#define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4
-#define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
-#define DAGB1_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
-#define DAGB1_RD_CNTL__IO_LEVEL__SHIFT 0x11
-#define DAGB1_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14
-#define DAGB1_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17
-#define DAGB1_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL
-#define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L
-#define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L
-#define DAGB1_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L
-#define DAGB1_RD_CNTL__IO_LEVEL_MASK 0x000E0000L
-#define DAGB1_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L
-#define DAGB1_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L
-//DAGB1_RD_GMI_CNTL
-#define DAGB1_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0
-#define DAGB1_RD_GMI_CNTL__LEVEL__SHIFT 0x6
-#define DAGB1_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9
-#define DAGB1_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd
-#define DAGB1_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL
-#define DAGB1_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L
-#define DAGB1_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L
-#define DAGB1_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L
-//DAGB1_RD_ADDR_DAGB
-#define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0
-#define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
-#define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
-#define DAGB1_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7
-#define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L
-#define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
-#define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
-#define DAGB1_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L
-//DAGB1_RD_OUTPUT_DAGB_MAX_BURST
-#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0
-#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4
-#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8
-#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc
-#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10
-#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14
-#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18
-#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c
-#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL
-#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L
-#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L
-#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L
-#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L
-#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L
-#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L
-#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L
-//DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER
-#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0
-#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4
-#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8
-#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc
-#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10
-#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14
-#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18
-#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c
-#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL
-#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L
-#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L
-#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L
-#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L
-#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L
-#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L
-#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L
-//DAGB1_RD_CGTT_CLK_CTRL
-#define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define DAGB1_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
-#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
-#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
-#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
-#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
-#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
-#define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define DAGB1_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
-#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
-#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
-#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
-#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
-#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
-//DAGB1_L1TLB_RD_CGTT_CLK_CTRL
-#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
-#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
-#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
-#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
-#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
-#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
-#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
-#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
-#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
-#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
-#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
-#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
-//DAGB1_ATCVM_RD_CGTT_CLK_CTRL
-#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
-#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
-#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
-#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
-#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
-#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
-#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
-#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
-#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
-#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
-#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
-#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
-//DAGB1_RD_ADDR_DAGB_MAX_BURST0
-#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
-#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
-#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
-#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
-#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
-#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
-#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
-#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
-#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
-#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
-#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
-#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
-#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
-#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
-#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
-#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
-//DAGB1_RD_ADDR_DAGB_LAZY_TIMER0
-#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
-#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
-#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
-#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
-#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
-#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
-#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
-#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
-#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
-#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
-#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
-#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
-#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
-#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
-#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
-#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
-//DAGB1_RD_ADDR_DAGB_MAX_BURST1
-#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
-#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
-#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
-#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
-#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
-#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
-#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
-#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
-#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
-#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
-#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
-#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
-#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
-#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
-#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
-#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
-//DAGB1_RD_ADDR_DAGB_LAZY_TIMER1
-#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
-#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
-#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
-#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
-#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
-#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
-#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
-#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
-#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
-#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
-#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
-#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
-#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
-#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
-#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
-#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
-//DAGB1_RD_VC0_CNTL
-#define DAGB1_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0
-#define DAGB1_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5
-#define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb
-#define DAGB1_RD_VC0_CNTL__MAX_BW__SHIFT 0xc
-#define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14
-#define DAGB1_RD_VC0_CNTL__MIN_BW__SHIFT 0x15
-#define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
-#define DAGB1_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19
-#define DAGB1_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL
-#define DAGB1_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L
-#define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
-#define DAGB1_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L
-#define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
-#define DAGB1_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L
-#define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
-#define DAGB1_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L
-//DAGB1_RD_VC1_CNTL
-#define DAGB1_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0
-#define DAGB1_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5
-#define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb
-#define DAGB1_RD_VC1_CNTL__MAX_BW__SHIFT 0xc
-#define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14
-#define DAGB1_RD_VC1_CNTL__MIN_BW__SHIFT 0x15
-#define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
-#define DAGB1_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19
-#define DAGB1_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL
-#define DAGB1_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L
-#define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
-#define DAGB1_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L
-#define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
-#define DAGB1_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L
-#define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
-#define DAGB1_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L
-//DAGB1_RD_VC2_CNTL
-#define DAGB1_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0
-#define DAGB1_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5
-#define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb
-#define DAGB1_RD_VC2_CNTL__MAX_BW__SHIFT 0xc
-#define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14
-#define DAGB1_RD_VC2_CNTL__MIN_BW__SHIFT 0x15
-#define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
-#define DAGB1_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19
-#define DAGB1_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL
-#define DAGB1_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L
-#define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
-#define DAGB1_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L
-#define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
-#define DAGB1_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L
-#define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
-#define DAGB1_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L
-//DAGB1_RD_VC3_CNTL
-#define DAGB1_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0
-#define DAGB1_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5
-#define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb
-#define DAGB1_RD_VC3_CNTL__MAX_BW__SHIFT 0xc
-#define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14
-#define DAGB1_RD_VC3_CNTL__MIN_BW__SHIFT 0x15
-#define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
-#define DAGB1_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19
-#define DAGB1_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL
-#define DAGB1_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L
-#define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
-#define DAGB1_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L
-#define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
-#define DAGB1_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L
-#define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
-#define DAGB1_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L
-//DAGB1_RD_VC4_CNTL
-#define DAGB1_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0
-#define DAGB1_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5
-#define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb
-#define DAGB1_RD_VC4_CNTL__MAX_BW__SHIFT 0xc
-#define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14
-#define DAGB1_RD_VC4_CNTL__MIN_BW__SHIFT 0x15
-#define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
-#define DAGB1_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19
-#define DAGB1_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL
-#define DAGB1_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L
-#define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
-#define DAGB1_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L
-#define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
-#define DAGB1_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L
-#define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
-#define DAGB1_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L
-//DAGB1_RD_VC5_CNTL
-#define DAGB1_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0
-#define DAGB1_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5
-#define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb
-#define DAGB1_RD_VC5_CNTL__MAX_BW__SHIFT 0xc
-#define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14
-#define DAGB1_RD_VC5_CNTL__MIN_BW__SHIFT 0x15
-#define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
-#define DAGB1_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19
-#define DAGB1_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL
-#define DAGB1_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L
-#define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
-#define DAGB1_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L
-#define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
-#define DAGB1_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L
-#define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
-#define DAGB1_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L
-//DAGB1_RD_VC6_CNTL
-#define DAGB1_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0
-#define DAGB1_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5
-#define DAGB1_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb
-#define DAGB1_RD_VC6_CNTL__MAX_BW__SHIFT 0xc
-#define DAGB1_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14
-#define DAGB1_RD_VC6_CNTL__MIN_BW__SHIFT 0x15
-#define DAGB1_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
-#define DAGB1_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19
-#define DAGB1_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL
-#define DAGB1_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L
-#define DAGB1_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
-#define DAGB1_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L
-#define DAGB1_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
-#define DAGB1_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L
-#define DAGB1_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
-#define DAGB1_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L
-//DAGB1_RD_VC7_CNTL
-#define DAGB1_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0
-#define DAGB1_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5
-#define DAGB1_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb
-#define DAGB1_RD_VC7_CNTL__MAX_BW__SHIFT 0xc
-#define DAGB1_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14
-#define DAGB1_RD_VC7_CNTL__MIN_BW__SHIFT 0x15
-#define DAGB1_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
-#define DAGB1_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19
-#define DAGB1_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL
-#define DAGB1_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L
-#define DAGB1_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
-#define DAGB1_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L
-#define DAGB1_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
-#define DAGB1_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L
-#define DAGB1_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
-#define DAGB1_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L
-//DAGB1_RD_CNTL_MISC
-#define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0
-#define DAGB1_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6
-#define DAGB1_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd
-#define DAGB1_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13
-#define DAGB1_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14
-#define DAGB1_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15
-#define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL
-#define DAGB1_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L
-#define DAGB1_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L
-#define DAGB1_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L
-#define DAGB1_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L
-#define DAGB1_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L
-//DAGB1_RD_TLB_CREDIT
-#define DAGB1_RD_TLB_CREDIT__TLB0__SHIFT 0x0
-#define DAGB1_RD_TLB_CREDIT__TLB1__SHIFT 0x5
-#define DAGB1_RD_TLB_CREDIT__TLB2__SHIFT 0xa
-#define DAGB1_RD_TLB_CREDIT__TLB3__SHIFT 0xf
-#define DAGB1_RD_TLB_CREDIT__TLB4__SHIFT 0x14
-#define DAGB1_RD_TLB_CREDIT__TLB5__SHIFT 0x19
-#define DAGB1_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL
-#define DAGB1_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L
-#define DAGB1_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L
-#define DAGB1_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L
-#define DAGB1_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L
-#define DAGB1_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L
-//DAGB1_RDCLI_ASK_PENDING
-#define DAGB1_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0
-#define DAGB1_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
-//DAGB1_RDCLI_GO_PENDING
-#define DAGB1_RDCLI_GO_PENDING__BUSY__SHIFT 0x0
-#define DAGB1_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
-//DAGB1_RDCLI_GBLSEND_PENDING
-#define DAGB1_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0
-#define DAGB1_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL
-//DAGB1_RDCLI_TLB_PENDING
-#define DAGB1_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0
-#define DAGB1_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL
-//DAGB1_RDCLI_OARB_PENDING
-#define DAGB1_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0
-#define DAGB1_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL
-//DAGB1_RDCLI_OSD_PENDING
-#define DAGB1_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0
-#define DAGB1_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
-//DAGB1_WRCLI0
-#define DAGB1_WRCLI0__VIRT_CHAN__SHIFT 0x0
-#define DAGB1_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB1_WRCLI0__URG_HIGH__SHIFT 0x4
-#define DAGB1_WRCLI0__URG_LOW__SHIFT 0x8
-#define DAGB1_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB1_WRCLI0__MAX_BW__SHIFT 0xd
-#define DAGB1_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB1_WRCLI0__MIN_BW__SHIFT 0x16
-#define DAGB1_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB1_WRCLI0__MAX_OSD__SHIFT 0x1a
-#define DAGB1_WRCLI0__VIRT_CHAN_MASK 0x00000007L
-#define DAGB1_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB1_WRCLI0__URG_HIGH_MASK 0x000000F0L
-#define DAGB1_WRCLI0__URG_LOW_MASK 0x00000F00L
-#define DAGB1_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB1_WRCLI0__MAX_BW_MASK 0x001FE000L
-#define DAGB1_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB1_WRCLI0__MIN_BW_MASK 0x01C00000L
-#define DAGB1_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB1_WRCLI0__MAX_OSD_MASK 0xFC000000L
-//DAGB1_WRCLI1
-#define DAGB1_WRCLI1__VIRT_CHAN__SHIFT 0x0
-#define DAGB1_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB1_WRCLI1__URG_HIGH__SHIFT 0x4
-#define DAGB1_WRCLI1__URG_LOW__SHIFT 0x8
-#define DAGB1_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB1_WRCLI1__MAX_BW__SHIFT 0xd
-#define DAGB1_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB1_WRCLI1__MIN_BW__SHIFT 0x16
-#define DAGB1_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB1_WRCLI1__MAX_OSD__SHIFT 0x1a
-#define DAGB1_WRCLI1__VIRT_CHAN_MASK 0x00000007L
-#define DAGB1_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB1_WRCLI1__URG_HIGH_MASK 0x000000F0L
-#define DAGB1_WRCLI1__URG_LOW_MASK 0x00000F00L
-#define DAGB1_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB1_WRCLI1__MAX_BW_MASK 0x001FE000L
-#define DAGB1_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB1_WRCLI1__MIN_BW_MASK 0x01C00000L
-#define DAGB1_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB1_WRCLI1__MAX_OSD_MASK 0xFC000000L
-//DAGB1_WRCLI2
-#define DAGB1_WRCLI2__VIRT_CHAN__SHIFT 0x0
-#define DAGB1_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB1_WRCLI2__URG_HIGH__SHIFT 0x4
-#define DAGB1_WRCLI2__URG_LOW__SHIFT 0x8
-#define DAGB1_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB1_WRCLI2__MAX_BW__SHIFT 0xd
-#define DAGB1_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB1_WRCLI2__MIN_BW__SHIFT 0x16
-#define DAGB1_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB1_WRCLI2__MAX_OSD__SHIFT 0x1a
-#define DAGB1_WRCLI2__VIRT_CHAN_MASK 0x00000007L
-#define DAGB1_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB1_WRCLI2__URG_HIGH_MASK 0x000000F0L
-#define DAGB1_WRCLI2__URG_LOW_MASK 0x00000F00L
-#define DAGB1_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB1_WRCLI2__MAX_BW_MASK 0x001FE000L
-#define DAGB1_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB1_WRCLI2__MIN_BW_MASK 0x01C00000L
-#define DAGB1_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB1_WRCLI2__MAX_OSD_MASK 0xFC000000L
-//DAGB1_WRCLI3
-#define DAGB1_WRCLI3__VIRT_CHAN__SHIFT 0x0
-#define DAGB1_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB1_WRCLI3__URG_HIGH__SHIFT 0x4
-#define DAGB1_WRCLI3__URG_LOW__SHIFT 0x8
-#define DAGB1_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB1_WRCLI3__MAX_BW__SHIFT 0xd
-#define DAGB1_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB1_WRCLI3__MIN_BW__SHIFT 0x16
-#define DAGB1_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB1_WRCLI3__MAX_OSD__SHIFT 0x1a
-#define DAGB1_WRCLI3__VIRT_CHAN_MASK 0x00000007L
-#define DAGB1_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB1_WRCLI3__URG_HIGH_MASK 0x000000F0L
-#define DAGB1_WRCLI3__URG_LOW_MASK 0x00000F00L
-#define DAGB1_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB1_WRCLI3__MAX_BW_MASK 0x001FE000L
-#define DAGB1_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB1_WRCLI3__MIN_BW_MASK 0x01C00000L
-#define DAGB1_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB1_WRCLI3__MAX_OSD_MASK 0xFC000000L
-//DAGB1_WRCLI4
-#define DAGB1_WRCLI4__VIRT_CHAN__SHIFT 0x0
-#define DAGB1_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB1_WRCLI4__URG_HIGH__SHIFT 0x4
-#define DAGB1_WRCLI4__URG_LOW__SHIFT 0x8
-#define DAGB1_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB1_WRCLI4__MAX_BW__SHIFT 0xd
-#define DAGB1_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB1_WRCLI4__MIN_BW__SHIFT 0x16
-#define DAGB1_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB1_WRCLI4__MAX_OSD__SHIFT 0x1a
-#define DAGB1_WRCLI4__VIRT_CHAN_MASK 0x00000007L
-#define DAGB1_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB1_WRCLI4__URG_HIGH_MASK 0x000000F0L
-#define DAGB1_WRCLI4__URG_LOW_MASK 0x00000F00L
-#define DAGB1_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB1_WRCLI4__MAX_BW_MASK 0x001FE000L
-#define DAGB1_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB1_WRCLI4__MIN_BW_MASK 0x01C00000L
-#define DAGB1_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB1_WRCLI4__MAX_OSD_MASK 0xFC000000L
-//DAGB1_WRCLI5
-#define DAGB1_WRCLI5__VIRT_CHAN__SHIFT 0x0
-#define DAGB1_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB1_WRCLI5__URG_HIGH__SHIFT 0x4
-#define DAGB1_WRCLI5__URG_LOW__SHIFT 0x8
-#define DAGB1_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB1_WRCLI5__MAX_BW__SHIFT 0xd
-#define DAGB1_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB1_WRCLI5__MIN_BW__SHIFT 0x16
-#define DAGB1_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB1_WRCLI5__MAX_OSD__SHIFT 0x1a
-#define DAGB1_WRCLI5__VIRT_CHAN_MASK 0x00000007L
-#define DAGB1_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB1_WRCLI5__URG_HIGH_MASK 0x000000F0L
-#define DAGB1_WRCLI5__URG_LOW_MASK 0x00000F00L
-#define DAGB1_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB1_WRCLI5__MAX_BW_MASK 0x001FE000L
-#define DAGB1_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB1_WRCLI5__MIN_BW_MASK 0x01C00000L
-#define DAGB1_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB1_WRCLI5__MAX_OSD_MASK 0xFC000000L
-//DAGB1_WRCLI6
-#define DAGB1_WRCLI6__VIRT_CHAN__SHIFT 0x0
-#define DAGB1_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB1_WRCLI6__URG_HIGH__SHIFT 0x4
-#define DAGB1_WRCLI6__URG_LOW__SHIFT 0x8
-#define DAGB1_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB1_WRCLI6__MAX_BW__SHIFT 0xd
-#define DAGB1_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB1_WRCLI6__MIN_BW__SHIFT 0x16
-#define DAGB1_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB1_WRCLI6__MAX_OSD__SHIFT 0x1a
-#define DAGB1_WRCLI6__VIRT_CHAN_MASK 0x00000007L
-#define DAGB1_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB1_WRCLI6__URG_HIGH_MASK 0x000000F0L
-#define DAGB1_WRCLI6__URG_LOW_MASK 0x00000F00L
-#define DAGB1_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB1_WRCLI6__MAX_BW_MASK 0x001FE000L
-#define DAGB1_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB1_WRCLI6__MIN_BW_MASK 0x01C00000L
-#define DAGB1_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB1_WRCLI6__MAX_OSD_MASK 0xFC000000L
-//DAGB1_WRCLI7
-#define DAGB1_WRCLI7__VIRT_CHAN__SHIFT 0x0
-#define DAGB1_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB1_WRCLI7__URG_HIGH__SHIFT 0x4
-#define DAGB1_WRCLI7__URG_LOW__SHIFT 0x8
-#define DAGB1_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB1_WRCLI7__MAX_BW__SHIFT 0xd
-#define DAGB1_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB1_WRCLI7__MIN_BW__SHIFT 0x16
-#define DAGB1_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB1_WRCLI7__MAX_OSD__SHIFT 0x1a
-#define DAGB1_WRCLI7__VIRT_CHAN_MASK 0x00000007L
-#define DAGB1_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB1_WRCLI7__URG_HIGH_MASK 0x000000F0L
-#define DAGB1_WRCLI7__URG_LOW_MASK 0x00000F00L
-#define DAGB1_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB1_WRCLI7__MAX_BW_MASK 0x001FE000L
-#define DAGB1_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB1_WRCLI7__MIN_BW_MASK 0x01C00000L
-#define DAGB1_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB1_WRCLI7__MAX_OSD_MASK 0xFC000000L
-//DAGB1_WRCLI8
-#define DAGB1_WRCLI8__VIRT_CHAN__SHIFT 0x0
-#define DAGB1_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB1_WRCLI8__URG_HIGH__SHIFT 0x4
-#define DAGB1_WRCLI8__URG_LOW__SHIFT 0x8
-#define DAGB1_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB1_WRCLI8__MAX_BW__SHIFT 0xd
-#define DAGB1_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB1_WRCLI8__MIN_BW__SHIFT 0x16
-#define DAGB1_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB1_WRCLI8__MAX_OSD__SHIFT 0x1a
-#define DAGB1_WRCLI8__VIRT_CHAN_MASK 0x00000007L
-#define DAGB1_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB1_WRCLI8__URG_HIGH_MASK 0x000000F0L
-#define DAGB1_WRCLI8__URG_LOW_MASK 0x00000F00L
-#define DAGB1_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB1_WRCLI8__MAX_BW_MASK 0x001FE000L
-#define DAGB1_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB1_WRCLI8__MIN_BW_MASK 0x01C00000L
-#define DAGB1_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB1_WRCLI8__MAX_OSD_MASK 0xFC000000L
-//DAGB1_WRCLI9
-#define DAGB1_WRCLI9__VIRT_CHAN__SHIFT 0x0
-#define DAGB1_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB1_WRCLI9__URG_HIGH__SHIFT 0x4
-#define DAGB1_WRCLI9__URG_LOW__SHIFT 0x8
-#define DAGB1_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB1_WRCLI9__MAX_BW__SHIFT 0xd
-#define DAGB1_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB1_WRCLI9__MIN_BW__SHIFT 0x16
-#define DAGB1_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB1_WRCLI9__MAX_OSD__SHIFT 0x1a
-#define DAGB1_WRCLI9__VIRT_CHAN_MASK 0x00000007L
-#define DAGB1_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB1_WRCLI9__URG_HIGH_MASK 0x000000F0L
-#define DAGB1_WRCLI9__URG_LOW_MASK 0x00000F00L
-#define DAGB1_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB1_WRCLI9__MAX_BW_MASK 0x001FE000L
-#define DAGB1_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB1_WRCLI9__MIN_BW_MASK 0x01C00000L
-#define DAGB1_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB1_WRCLI9__MAX_OSD_MASK 0xFC000000L
-//DAGB1_WRCLI10
-#define DAGB1_WRCLI10__VIRT_CHAN__SHIFT 0x0
-#define DAGB1_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB1_WRCLI10__URG_HIGH__SHIFT 0x4
-#define DAGB1_WRCLI10__URG_LOW__SHIFT 0x8
-#define DAGB1_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB1_WRCLI10__MAX_BW__SHIFT 0xd
-#define DAGB1_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB1_WRCLI10__MIN_BW__SHIFT 0x16
-#define DAGB1_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB1_WRCLI10__MAX_OSD__SHIFT 0x1a
-#define DAGB1_WRCLI10__VIRT_CHAN_MASK 0x00000007L
-#define DAGB1_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB1_WRCLI10__URG_HIGH_MASK 0x000000F0L
-#define DAGB1_WRCLI10__URG_LOW_MASK 0x00000F00L
-#define DAGB1_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB1_WRCLI10__MAX_BW_MASK 0x001FE000L
-#define DAGB1_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB1_WRCLI10__MIN_BW_MASK 0x01C00000L
-#define DAGB1_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB1_WRCLI10__MAX_OSD_MASK 0xFC000000L
-//DAGB1_WRCLI11
-#define DAGB1_WRCLI11__VIRT_CHAN__SHIFT 0x0
-#define DAGB1_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB1_WRCLI11__URG_HIGH__SHIFT 0x4
-#define DAGB1_WRCLI11__URG_LOW__SHIFT 0x8
-#define DAGB1_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB1_WRCLI11__MAX_BW__SHIFT 0xd
-#define DAGB1_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB1_WRCLI11__MIN_BW__SHIFT 0x16
-#define DAGB1_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB1_WRCLI11__MAX_OSD__SHIFT 0x1a
-#define DAGB1_WRCLI11__VIRT_CHAN_MASK 0x00000007L
-#define DAGB1_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB1_WRCLI11__URG_HIGH_MASK 0x000000F0L
-#define DAGB1_WRCLI11__URG_LOW_MASK 0x00000F00L
-#define DAGB1_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB1_WRCLI11__MAX_BW_MASK 0x001FE000L
-#define DAGB1_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB1_WRCLI11__MIN_BW_MASK 0x01C00000L
-#define DAGB1_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB1_WRCLI11__MAX_OSD_MASK 0xFC000000L
-//DAGB1_WRCLI12
-#define DAGB1_WRCLI12__VIRT_CHAN__SHIFT 0x0
-#define DAGB1_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB1_WRCLI12__URG_HIGH__SHIFT 0x4
-#define DAGB1_WRCLI12__URG_LOW__SHIFT 0x8
-#define DAGB1_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB1_WRCLI12__MAX_BW__SHIFT 0xd
-#define DAGB1_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB1_WRCLI12__MIN_BW__SHIFT 0x16
-#define DAGB1_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB1_WRCLI12__MAX_OSD__SHIFT 0x1a
-#define DAGB1_WRCLI12__VIRT_CHAN_MASK 0x00000007L
-#define DAGB1_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB1_WRCLI12__URG_HIGH_MASK 0x000000F0L
-#define DAGB1_WRCLI12__URG_LOW_MASK 0x00000F00L
-#define DAGB1_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB1_WRCLI12__MAX_BW_MASK 0x001FE000L
-#define DAGB1_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB1_WRCLI12__MIN_BW_MASK 0x01C00000L
-#define DAGB1_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB1_WRCLI12__MAX_OSD_MASK 0xFC000000L
-//DAGB1_WRCLI13
-#define DAGB1_WRCLI13__VIRT_CHAN__SHIFT 0x0
-#define DAGB1_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB1_WRCLI13__URG_HIGH__SHIFT 0x4
-#define DAGB1_WRCLI13__URG_LOW__SHIFT 0x8
-#define DAGB1_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB1_WRCLI13__MAX_BW__SHIFT 0xd
-#define DAGB1_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB1_WRCLI13__MIN_BW__SHIFT 0x16
-#define DAGB1_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB1_WRCLI13__MAX_OSD__SHIFT 0x1a
-#define DAGB1_WRCLI13__VIRT_CHAN_MASK 0x00000007L
-#define DAGB1_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB1_WRCLI13__URG_HIGH_MASK 0x000000F0L
-#define DAGB1_WRCLI13__URG_LOW_MASK 0x00000F00L
-#define DAGB1_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB1_WRCLI13__MAX_BW_MASK 0x001FE000L
-#define DAGB1_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB1_WRCLI13__MIN_BW_MASK 0x01C00000L
-#define DAGB1_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB1_WRCLI13__MAX_OSD_MASK 0xFC000000L
-//DAGB1_WRCLI14
-#define DAGB1_WRCLI14__VIRT_CHAN__SHIFT 0x0
-#define DAGB1_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB1_WRCLI14__URG_HIGH__SHIFT 0x4
-#define DAGB1_WRCLI14__URG_LOW__SHIFT 0x8
-#define DAGB1_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB1_WRCLI14__MAX_BW__SHIFT 0xd
-#define DAGB1_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB1_WRCLI14__MIN_BW__SHIFT 0x16
-#define DAGB1_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB1_WRCLI14__MAX_OSD__SHIFT 0x1a
-#define DAGB1_WRCLI14__VIRT_CHAN_MASK 0x00000007L
-#define DAGB1_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB1_WRCLI14__URG_HIGH_MASK 0x000000F0L
-#define DAGB1_WRCLI14__URG_LOW_MASK 0x00000F00L
-#define DAGB1_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB1_WRCLI14__MAX_BW_MASK 0x001FE000L
-#define DAGB1_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB1_WRCLI14__MIN_BW_MASK 0x01C00000L
-#define DAGB1_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB1_WRCLI14__MAX_OSD_MASK 0xFC000000L
-//DAGB1_WRCLI15
-#define DAGB1_WRCLI15__VIRT_CHAN__SHIFT 0x0
-#define DAGB1_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3
-#define DAGB1_WRCLI15__URG_HIGH__SHIFT 0x4
-#define DAGB1_WRCLI15__URG_LOW__SHIFT 0x8
-#define DAGB1_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc
-#define DAGB1_WRCLI15__MAX_BW__SHIFT 0xd
-#define DAGB1_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15
-#define DAGB1_WRCLI15__MIN_BW__SHIFT 0x16
-#define DAGB1_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19
-#define DAGB1_WRCLI15__MAX_OSD__SHIFT 0x1a
-#define DAGB1_WRCLI15__VIRT_CHAN_MASK 0x00000007L
-#define DAGB1_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L
-#define DAGB1_WRCLI15__URG_HIGH_MASK 0x000000F0L
-#define DAGB1_WRCLI15__URG_LOW_MASK 0x00000F00L
-#define DAGB1_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L
-#define DAGB1_WRCLI15__MAX_BW_MASK 0x001FE000L
-#define DAGB1_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L
-#define DAGB1_WRCLI15__MIN_BW_MASK 0x01C00000L
-#define DAGB1_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L
-#define DAGB1_WRCLI15__MAX_OSD_MASK 0xFC000000L
-//DAGB1_WR_CNTL
-#define DAGB1_WR_CNTL__SCLK_FREQ__SHIFT 0x0
-#define DAGB1_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4
-#define DAGB1_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
-#define DAGB1_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
-#define DAGB1_WR_CNTL__IO_LEVEL__SHIFT 0x11
-#define DAGB1_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14
-#define DAGB1_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17
-#define DAGB1_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL
-#define DAGB1_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L
-#define DAGB1_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L
-#define DAGB1_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L
-#define DAGB1_WR_CNTL__IO_LEVEL_MASK 0x000E0000L
-#define DAGB1_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L
-#define DAGB1_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L
-//DAGB1_WR_GMI_CNTL
-#define DAGB1_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0
-#define DAGB1_WR_GMI_CNTL__LEVEL__SHIFT 0x6
-#define DAGB1_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9
-#define DAGB1_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd
-#define DAGB1_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL
-#define DAGB1_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L
-#define DAGB1_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L
-#define DAGB1_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L
-//DAGB1_WR_ADDR_DAGB
-#define DAGB1_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0
-#define DAGB1_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
-#define DAGB1_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
-#define DAGB1_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7
-#define DAGB1_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L
-#define DAGB1_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
-#define DAGB1_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
-#define DAGB1_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L
-//DAGB1_WR_OUTPUT_DAGB_MAX_BURST
-#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0
-#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4
-#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8
-#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc
-#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10
-#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14
-#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18
-#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c
-#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL
-#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L
-#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L
-#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L
-#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L
-#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L
-#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L
-#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L
-//DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER
-#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0
-#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4
-#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8
-#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc
-#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10
-#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14
-#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18
-#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c
-#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL
-#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L
-#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L
-#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L
-#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L
-#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L
-#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L
-#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L
-//DAGB1_WR_CGTT_CLK_CTRL
-#define DAGB1_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define DAGB1_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define DAGB1_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
-#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
-#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
-#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
-#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
-#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
-#define DAGB1_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define DAGB1_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define DAGB1_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
-#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
-#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
-#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
-#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
-#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
-//DAGB1_L1TLB_WR_CGTT_CLK_CTRL
-#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
-#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
-#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
-#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
-#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
-#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
-#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
-#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
-#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
-#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
-#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
-#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
-//DAGB1_ATCVM_WR_CGTT_CLK_CTRL
-#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
-#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
-#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
-#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
-#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
-#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
-#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
-#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
-#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
-#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
-#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
-#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
-//DAGB1_WR_ADDR_DAGB_MAX_BURST0
-#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
-#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
-#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
-#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
-#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
-#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
-#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
-#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
-#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
-#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
-#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
-#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
-#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
-#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
-#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
-#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
-//DAGB1_WR_ADDR_DAGB_LAZY_TIMER0
-#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
-#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
-#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
-#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
-#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
-#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
-#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
-#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
-#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
-#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
-#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
-#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
-#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
-#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
-#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
-#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
-//DAGB1_WR_ADDR_DAGB_MAX_BURST1
-#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
-#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
-#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
-#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
-#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
-#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
-#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
-#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
-#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
-#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
-#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
-#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
-#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
-#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
-#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
-#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
-//DAGB1_WR_ADDR_DAGB_LAZY_TIMER1
-#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
-#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
-#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
-#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
-#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
-#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
-#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
-#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
-#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
-#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
-#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
-#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
-#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
-#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
-#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
-#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
-//DAGB1_WR_DATA_DAGB
-#define DAGB1_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0
-#define DAGB1_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
-#define DAGB1_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
-#define DAGB1_WR_DATA_DAGB__WHOAMI__SHIFT 0x7
-#define DAGB1_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L
-#define DAGB1_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
-#define DAGB1_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
-#define DAGB1_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L
-//DAGB1_WR_DATA_DAGB_MAX_BURST0
-#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
-#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
-#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
-#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
-#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
-#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
-#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
-#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
-#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
-#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
-#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
-#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
-#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
-#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
-#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
-#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
-//DAGB1_WR_DATA_DAGB_LAZY_TIMER0
-#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
-#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
-#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
-#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
-#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
-#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
-#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
-#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
-#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
-#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
-#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
-#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
-#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
-#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
-#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
-#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
-//DAGB1_WR_DATA_DAGB_MAX_BURST1
-#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
-#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
-#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
-#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
-#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
-#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
-#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
-#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
-#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
-#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
-#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
-#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
-#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
-#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
-#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
-#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
-//DAGB1_WR_DATA_DAGB_LAZY_TIMER1
-#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
-#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
-#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
-#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
-#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
-#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
-#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
-#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
-#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
-#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
-#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
-#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
-#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
-#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
-#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
-#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
-//DAGB1_WR_VC0_CNTL
-#define DAGB1_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0
-#define DAGB1_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5
-#define DAGB1_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb
-#define DAGB1_WR_VC0_CNTL__MAX_BW__SHIFT 0xc
-#define DAGB1_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14
-#define DAGB1_WR_VC0_CNTL__MIN_BW__SHIFT 0x15
-#define DAGB1_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
-#define DAGB1_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19
-#define DAGB1_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL
-#define DAGB1_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L
-#define DAGB1_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
-#define DAGB1_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L
-#define DAGB1_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
-#define DAGB1_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L
-#define DAGB1_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
-#define DAGB1_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L
-//DAGB1_WR_VC1_CNTL
-#define DAGB1_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0
-#define DAGB1_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5
-#define DAGB1_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb
-#define DAGB1_WR_VC1_CNTL__MAX_BW__SHIFT 0xc
-#define DAGB1_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14
-#define DAGB1_WR_VC1_CNTL__MIN_BW__SHIFT 0x15
-#define DAGB1_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
-#define DAGB1_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19
-#define DAGB1_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL
-#define DAGB1_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L
-#define DAGB1_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
-#define DAGB1_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L
-#define DAGB1_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
-#define DAGB1_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L
-#define DAGB1_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
-#define DAGB1_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L
-//DAGB1_WR_VC2_CNTL
-#define DAGB1_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0
-#define DAGB1_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5
-#define DAGB1_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb
-#define DAGB1_WR_VC2_CNTL__MAX_BW__SHIFT 0xc
-#define DAGB1_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14
-#define DAGB1_WR_VC2_CNTL__MIN_BW__SHIFT 0x15
-#define DAGB1_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
-#define DAGB1_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19
-#define DAGB1_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL
-#define DAGB1_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L
-#define DAGB1_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
-#define DAGB1_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L
-#define DAGB1_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
-#define DAGB1_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L
-#define DAGB1_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
-#define DAGB1_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L
-//DAGB1_WR_VC3_CNTL
-#define DAGB1_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0
-#define DAGB1_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5
-#define DAGB1_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb
-#define DAGB1_WR_VC3_CNTL__MAX_BW__SHIFT 0xc
-#define DAGB1_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14
-#define DAGB1_WR_VC3_CNTL__MIN_BW__SHIFT 0x15
-#define DAGB1_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
-#define DAGB1_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19
-#define DAGB1_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL
-#define DAGB1_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L
-#define DAGB1_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
-#define DAGB1_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L
-#define DAGB1_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
-#define DAGB1_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L
-#define DAGB1_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
-#define DAGB1_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L
-//DAGB1_WR_VC4_CNTL
-#define DAGB1_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0
-#define DAGB1_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5
-#define DAGB1_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb
-#define DAGB1_WR_VC4_CNTL__MAX_BW__SHIFT 0xc
-#define DAGB1_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14
-#define DAGB1_WR_VC4_CNTL__MIN_BW__SHIFT 0x15
-#define DAGB1_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
-#define DAGB1_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19
-#define DAGB1_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL
-#define DAGB1_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L
-#define DAGB1_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
-#define DAGB1_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L
-#define DAGB1_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
-#define DAGB1_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L
-#define DAGB1_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
-#define DAGB1_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L
-//DAGB1_WR_VC5_CNTL
-#define DAGB1_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0
-#define DAGB1_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5
-#define DAGB1_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb
-#define DAGB1_WR_VC5_CNTL__MAX_BW__SHIFT 0xc
-#define DAGB1_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14
-#define DAGB1_WR_VC5_CNTL__MIN_BW__SHIFT 0x15
-#define DAGB1_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
-#define DAGB1_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19
-#define DAGB1_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL
-#define DAGB1_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L
-#define DAGB1_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
-#define DAGB1_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L
-#define DAGB1_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
-#define DAGB1_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L
-#define DAGB1_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
-#define DAGB1_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L
-//DAGB1_WR_VC6_CNTL
-#define DAGB1_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0
-#define DAGB1_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5
-#define DAGB1_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb
-#define DAGB1_WR_VC6_CNTL__MAX_BW__SHIFT 0xc
-#define DAGB1_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14
-#define DAGB1_WR_VC6_CNTL__MIN_BW__SHIFT 0x15
-#define DAGB1_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
-#define DAGB1_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19
-#define DAGB1_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL
-#define DAGB1_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L
-#define DAGB1_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
-#define DAGB1_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L
-#define DAGB1_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
-#define DAGB1_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L
-#define DAGB1_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
-#define DAGB1_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L
-//DAGB1_WR_VC7_CNTL
-#define DAGB1_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0
-#define DAGB1_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5
-#define DAGB1_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb
-#define DAGB1_WR_VC7_CNTL__MAX_BW__SHIFT 0xc
-#define DAGB1_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14
-#define DAGB1_WR_VC7_CNTL__MIN_BW__SHIFT 0x15
-#define DAGB1_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
-#define DAGB1_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19
-#define DAGB1_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL
-#define DAGB1_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L
-#define DAGB1_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
-#define DAGB1_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L
-#define DAGB1_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
-#define DAGB1_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L
-#define DAGB1_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
-#define DAGB1_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L
-//DAGB1_WR_CNTL_MISC
-#define DAGB1_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0
-#define DAGB1_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6
-#define DAGB1_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd
-#define DAGB1_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13
-#define DAGB1_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14
-#define DAGB1_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15
-#define DAGB1_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL
-#define DAGB1_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L
-#define DAGB1_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L
-#define DAGB1_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L
-#define DAGB1_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L
-#define DAGB1_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L
-//DAGB1_WR_TLB_CREDIT
-#define DAGB1_WR_TLB_CREDIT__TLB0__SHIFT 0x0
-#define DAGB1_WR_TLB_CREDIT__TLB1__SHIFT 0x5
-#define DAGB1_WR_TLB_CREDIT__TLB2__SHIFT 0xa
-#define DAGB1_WR_TLB_CREDIT__TLB3__SHIFT 0xf
-#define DAGB1_WR_TLB_CREDIT__TLB4__SHIFT 0x14
-#define DAGB1_WR_TLB_CREDIT__TLB5__SHIFT 0x19
-#define DAGB1_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL
-#define DAGB1_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L
-#define DAGB1_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L
-#define DAGB1_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L
-#define DAGB1_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L
-#define DAGB1_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L
-//DAGB1_WR_DATA_CREDIT
-#define DAGB1_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0
-#define DAGB1_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8
-#define DAGB1_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10
-#define DAGB1_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18
-#define DAGB1_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL
-#define DAGB1_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L
-#define DAGB1_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L
-#define DAGB1_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L
-//DAGB1_WR_MISC_CREDIT
-#define DAGB1_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0
-#define DAGB1_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6
-#define DAGB1_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9
-#define DAGB1_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10
-#define DAGB1_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL
-#define DAGB1_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L
-#define DAGB1_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L
-#define DAGB1_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L
-//DAGB1_WRCLI_ASK_PENDING
-#define DAGB1_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0
-#define DAGB1_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
-//DAGB1_WRCLI_GO_PENDING
-#define DAGB1_WRCLI_GO_PENDING__BUSY__SHIFT 0x0
-#define DAGB1_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
-//DAGB1_WRCLI_GBLSEND_PENDING
-#define DAGB1_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0
-#define DAGB1_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL
-//DAGB1_WRCLI_TLB_PENDING
-#define DAGB1_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0
-#define DAGB1_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL
-//DAGB1_WRCLI_OARB_PENDING
-#define DAGB1_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0
-#define DAGB1_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL
-//DAGB1_WRCLI_OSD_PENDING
-#define DAGB1_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0
-#define DAGB1_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
-//DAGB1_WRCLI_DBUS_ASK_PENDING
-#define DAGB1_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0
-#define DAGB1_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
-//DAGB1_WRCLI_DBUS_GO_PENDING
-#define DAGB1_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0
-#define DAGB1_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
-//DAGB1_DAGB_DLY
-#define DAGB1_DAGB_DLY__DLY__SHIFT 0x0
-#define DAGB1_DAGB_DLY__CLI__SHIFT 0x8
-#define DAGB1_DAGB_DLY__POS__SHIFT 0x10
-#define DAGB1_DAGB_DLY__DLY_MASK 0x000000FFL
-#define DAGB1_DAGB_DLY__CLI_MASK 0x0000FF00L
-#define DAGB1_DAGB_DLY__POS_MASK 0x000F0000L
-//DAGB1_CNTL_MISC
-#define DAGB1_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0
-#define DAGB1_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3
-#define DAGB1_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6
-#define DAGB1_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9
-#define DAGB1_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc
-#define DAGB1_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf
-#define DAGB1_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12
-#define DAGB1_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15
-#define DAGB1_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18
-#define DAGB1_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e
-#define DAGB1_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L
-#define DAGB1_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L
-#define DAGB1_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L
-#define DAGB1_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L
-#define DAGB1_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L
-#define DAGB1_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L
-#define DAGB1_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L
-#define DAGB1_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L
-#define DAGB1_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L
-#define DAGB1_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L
-//DAGB1_CNTL_MISC2
-#define DAGB1_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0
-#define DAGB1_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1
-#define DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2
-#define DAGB1_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3
-#define DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4
-#define DAGB1_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5
-#define DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6
-#define DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7
-#define DAGB1_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8
-#define DAGB1_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9
-#define DAGB1_CNTL_MISC2__SWAP_CTL__SHIFT 0xa
-#define DAGB1_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L
-#define DAGB1_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L
-#define DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L
-#define DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L
-#define DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L
-#define DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L
-#define DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L
-#define DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L
-#define DAGB1_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L
-#define DAGB1_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L
-#define DAGB1_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L
-//DAGB1_FIFO_EMPTY
-#define DAGB1_FIFO_EMPTY__EMPTY__SHIFT 0x0
-#define DAGB1_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL
-//DAGB1_FIFO_FULL
-#define DAGB1_FIFO_FULL__FULL__SHIFT 0x0
-#define DAGB1_FIFO_FULL__FULL_MASK 0x007FFFFFL
-//DAGB1_WR_CREDITS_FULL
-#define DAGB1_WR_CREDITS_FULL__FULL__SHIFT 0x0
-#define DAGB1_WR_CREDITS_FULL__FULL_MASK 0x0007FFFFL
-//DAGB1_RD_CREDITS_FULL
-#define DAGB1_RD_CREDITS_FULL__FULL__SHIFT 0x0
-#define DAGB1_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL
-//DAGB1_PERFCOUNTER_LO
-#define DAGB1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
-#define DAGB1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
-//DAGB1_PERFCOUNTER_HI
-#define DAGB1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
-#define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
-#define DAGB1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
-#define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
-//DAGB1_PERFCOUNTER0_CFG
-#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
-#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
-#define DAGB1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
-#define DAGB1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
-#define DAGB1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
-#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
-#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define DAGB1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
-#define DAGB1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
-#define DAGB1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
-//DAGB1_PERFCOUNTER1_CFG
-#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
-#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
-#define DAGB1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
-#define DAGB1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
-#define DAGB1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
-#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
-#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define DAGB1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
-#define DAGB1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
-#define DAGB1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
-//DAGB1_PERFCOUNTER2_CFG
-#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
-#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
-#define DAGB1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
-#define DAGB1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
-#define DAGB1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
-#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
-#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define DAGB1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
-#define DAGB1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
-#define DAGB1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
-//DAGB1_PERFCOUNTER_RSLT_CNTL
-#define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
-#define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
-#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
-#define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
-#define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
-#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
-#define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
-#define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
-#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
-#define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
-#define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
-#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
-//DAGB1_RESERVE0
-#define DAGB1_RESERVE0__RESERVE__SHIFT 0x0
-#define DAGB1_RESERVE0__RESERVE_MASK 0xFFFFFFFFL
-//DAGB1_RESERVE1
-#define DAGB1_RESERVE1__RESERVE__SHIFT 0x0
-#define DAGB1_RESERVE1__RESERVE_MASK 0xFFFFFFFFL
-//DAGB1_RESERVE2
-#define DAGB1_RESERVE2__RESERVE__SHIFT 0x0
-#define DAGB1_RESERVE2__RESERVE_MASK 0xFFFFFFFFL
-//DAGB1_RESERVE3
-#define DAGB1_RESERVE3__RESERVE__SHIFT 0x0
-#define DAGB1_RESERVE3__RESERVE_MASK 0xFFFFFFFFL
-//DAGB1_RESERVE4
-#define DAGB1_RESERVE4__RESERVE__SHIFT 0x0
-#define DAGB1_RESERVE4__RESERVE_MASK 0xFFFFFFFFL
-//DAGB1_RESERVE5
-#define DAGB1_RESERVE5__RESERVE__SHIFT 0x0
-#define DAGB1_RESERVE5__RESERVE_MASK 0xFFFFFFFFL
-//DAGB1_RESERVE6
-#define DAGB1_RESERVE6__RESERVE__SHIFT 0x0
-#define DAGB1_RESERVE6__RESERVE_MASK 0xFFFFFFFFL
-//DAGB1_RESERVE7
-#define DAGB1_RESERVE7__RESERVE__SHIFT 0x0
-#define DAGB1_RESERVE7__RESERVE_MASK 0xFFFFFFFFL
-//DAGB1_RESERVE8
-#define DAGB1_RESERVE8__RESERVE__SHIFT 0x0
-#define DAGB1_RESERVE8__RESERVE_MASK 0xFFFFFFFFL
-//DAGB1_RESERVE9
-#define DAGB1_RESERVE9__RESERVE__SHIFT 0x0
-#define DAGB1_RESERVE9__RESERVE_MASK 0xFFFFFFFFL
-//DAGB1_RESERVE10
-#define DAGB1_RESERVE10__RESERVE__SHIFT 0x0
-#define DAGB1_RESERVE10__RESERVE_MASK 0xFFFFFFFFL
-//DAGB1_RESERVE11
-#define DAGB1_RESERVE11__RESERVE__SHIFT 0x0
-#define DAGB1_RESERVE11__RESERVE_MASK 0xFFFFFFFFL
-//DAGB1_RESERVE12
-#define DAGB1_RESERVE12__RESERVE__SHIFT 0x0
-#define DAGB1_RESERVE12__RESERVE_MASK 0xFFFFFFFFL
-//DAGB1_RESERVE13
-#define DAGB1_RESERVE13__RESERVE__SHIFT 0x0
-#define DAGB1_RESERVE13__RESERVE_MASK 0xFFFFFFFFL
-//DAGB1_RESERVE14
-#define DAGB1_RESERVE14__RESERVE__SHIFT 0x0
-#define DAGB1_RESERVE14__RESERVE_MASK 0xFFFFFFFFL
-//DAGB1_RESERVE15
-#define DAGB1_RESERVE15__RESERVE__SHIFT 0x0
-#define DAGB1_RESERVE15__RESERVE_MASK 0xFFFFFFFFL
-//DAGB1_RESERVE16
-#define DAGB1_RESERVE16__RESERVE__SHIFT 0x0
-#define DAGB1_RESERVE16__RESERVE_MASK 0xFFFFFFFFL
-//DAGB1_RESERVE17
-#define DAGB1_RESERVE17__RESERVE__SHIFT 0x0
-#define DAGB1_RESERVE17__RESERVE_MASK 0xFFFFFFFFL
-
-
-// addressBlock: mmhub_ea_mmeadec
-//MMEA0_DRAM_RD_CLI2GRP_MAP0
-#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
-#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
-#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
-#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
-#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
-#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
-#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
-#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
-#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
-#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
-#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
-#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
-#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
-#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
-#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
-#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
-#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
-#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
-#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
-#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
-#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
-#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
-#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
-#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
-#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
-#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
-#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
-#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
-#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
-#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
-#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
-#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
-//MMEA0_DRAM_RD_CLI2GRP_MAP1
-#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
-#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
-#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
-#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
-#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
-#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
-#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
-#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
-#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
-#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
-#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
-#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
-#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
-#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
-#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
-#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
-#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
-#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
-#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
-#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
-#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
-#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
-#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
-#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
-#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
-#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
-#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
-#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
-#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
-#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
-#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
-#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
-//MMEA0_DRAM_WR_CLI2GRP_MAP0
-#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
-#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
-#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
-#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
-#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
-#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
-#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
-#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
-#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
-#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
-#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
-#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
-#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
-#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
-#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
-#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
-#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
-#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
-#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
-#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
-#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
-#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
-#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
-#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
-#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
-#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
-#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
-#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
-#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
-#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
-#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
-#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
-//MMEA0_DRAM_WR_CLI2GRP_MAP1
-#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
-#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
-#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
-#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
-#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
-#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
-#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
-#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
-#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
-#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
-#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
-#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
-#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
-#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
-#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
-#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
-#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
-#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
-#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
-#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
-#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
-#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
-#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
-#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
-#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
-#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
-#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
-#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
-#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
-#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
-#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
-#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
-//MMEA0_DRAM_RD_GRP2VC_MAP
-#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
-#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
-#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
-#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
-#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
-#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
-#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
-#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
-//MMEA0_DRAM_WR_GRP2VC_MAP
-#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
-#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
-#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
-#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
-#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
-#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
-#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
-#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
-//MMEA0_DRAM_RD_LAZY
-#define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0
-#define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3
-#define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6
-#define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9
-#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
-#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
-#define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L
-#define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L
-#define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L
-#define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L
-#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
-#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
-//MMEA0_DRAM_WR_LAZY
-#define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0
-#define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3
-#define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6
-#define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9
-#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
-#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
-#define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L
-#define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L
-#define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L
-#define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L
-#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
-#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
-//MMEA0_DRAM_RD_CAM_CNTL
-#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
-#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
-#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
-#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
-#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
-#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
-#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
-#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
-#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
-#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
-#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
-#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
-#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
-#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
-#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
-#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
-//MMEA0_DRAM_WR_CAM_CNTL
-#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
-#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
-#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
-#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
-#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
-#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
-#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
-#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
-#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
-#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
-#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
-#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
-#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
-#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
-#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
-#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
-//MMEA0_DRAM_PAGE_BURST
-#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0
-#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8
-#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10
-#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18
-#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL
-#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
-#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
-#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L
-//MMEA0_DRAM_RD_PRI_AGE
-#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
-#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
-#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
-#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
-#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
-#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
-#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
-#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
-#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
-#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
-#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
-#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
-#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
-#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
-#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
-#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
-//MMEA0_DRAM_WR_PRI_AGE
-#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
-#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
-#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
-#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
-#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
-#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
-#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
-#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
-#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
-#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
-#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
-#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
-#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
-#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
-#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
-#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
-//MMEA0_DRAM_RD_PRI_QUEUING
-#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
-#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
-#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
-#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
-#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
-#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
-#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
-#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
-//MMEA0_DRAM_WR_PRI_QUEUING
-#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
-#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
-#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
-#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
-#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
-#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
-#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
-#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
-//MMEA0_DRAM_RD_PRI_FIXED
-#define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
-#define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
-#define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
-#define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
-#define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
-#define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
-#define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
-#define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
-//MMEA0_DRAM_WR_PRI_FIXED
-#define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
-#define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
-#define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
-#define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
-#define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
-#define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
-#define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
-#define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
-//MMEA0_DRAM_RD_PRI_URGENCY
-#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
-#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
-#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
-#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
-#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
-#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
-#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
-#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
-#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
-#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
-#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
-#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
-#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
-#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
-#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
-#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
-//MMEA0_DRAM_WR_PRI_URGENCY
-#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
-#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
-#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
-#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
-#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
-#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
-#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
-#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
-#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
-#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
-#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
-#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
-#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
-#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
-#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
-#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
-//MMEA0_DRAM_RD_PRI_QUANT_PRI1
-#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
-#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
-#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
-#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
-#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
-//MMEA0_DRAM_RD_PRI_QUANT_PRI2
-#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
-#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
-#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
-#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
-#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
-//MMEA0_DRAM_RD_PRI_QUANT_PRI3
-#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
-#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
-#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
-#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
-#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
-//MMEA0_DRAM_WR_PRI_QUANT_PRI1
-#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
-#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
-#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
-#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
-#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
-//MMEA0_DRAM_WR_PRI_QUANT_PRI2
-#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
-#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
-#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
-#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
-#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
-//MMEA0_DRAM_WR_PRI_QUANT_PRI3
-#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
-#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
-#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
-#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
-#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
-//MMEA0_ADDRNORM_BASE_ADDR0
-#define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0
-#define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1
-#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x4
-#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x8
-#define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc
-#define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L
-#define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
-#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x000000F0L
-#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000700L
-#define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L
-//MMEA0_ADDRNORM_LIMIT_ADDR0
-#define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0
-#define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8
-#define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES__SHIFT 0xa
-#define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc
-#define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL
-#define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L
-#define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES_MASK 0x00000C00L
-#define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L
-//MMEA0_ADDRNORM_BASE_ADDR1
-#define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0
-#define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1
-#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x4
-#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x8
-#define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc
-#define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L
-#define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
-#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x000000F0L
-#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000700L
-#define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L
-//MMEA0_ADDRNORM_LIMIT_ADDR1
-#define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0
-#define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8
-#define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES__SHIFT 0xa
-#define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc
-#define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL
-#define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L
-#define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES_MASK 0x00000C00L
-#define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L
-//MMEA0_ADDRNORM_OFFSET_ADDR1
-#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0
-#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14
-#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L
-#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L
-//MMEA0_ADDRNORMDRAM_HOLE_CNTL
-#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0
-#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7
-#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L
-#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L
-//MMEA0_ADDRNORMDRAM_TRICHANNEL_CFG
-#define MMEA0_ADDRNORMDRAM_TRICHANNEL_CFG__LOG2_ADDR64K_SPACE__SHIFT 0x0
-#define MMEA0_ADDRNORMDRAM_TRICHANNEL_CFG__LOG2_ADDR64K_SPACE_MASK 0x0000003FL
-//MMEA0_ADDRDEC_BANK_CFG
-#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0
-#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x5
-#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa
-#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xd
-#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x10
-#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x11
-#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001FL
-#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003E0L
-#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001C00L
-#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000E000L
-#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L
-#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L
-//MMEA0_ADDRDEC_MISC_CFG
-#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0
-#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1
-#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2
-#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x3
-#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x4
-#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8
-#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9
-#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc
-#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11
-#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16
-#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18
-#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a
-#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d
-#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L
-#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L
-#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L
-#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L
-#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L
-#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L
-#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L
-#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L
-#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L
-#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L
-#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L
-#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L
-#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L
-//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L
-//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L
-//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L
-//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L
-//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L
-//MMEA0_ADDRDECDRAM_ADDR_HASH_PC
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L
-//MMEA0_ADDRDECDRAM_ADDR_HASH_PC2
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000001FL
-//MMEA0_ADDRDECDRAM_ADDR_HASH_CS0
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL
-//MMEA0_ADDRDECDRAM_ADDR_HASH_CS1
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L
-#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL
-//MMEA0_ADDRDECDRAM_HARVEST_ENABLE
-#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0
-#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1
-#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2
-#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3
-#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L
-#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L
-#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L
-#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L
-//MMEA0_ADDRDEC0_BASE_ADDR_CS0
-#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0
-#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
-#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L
-#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
-//MMEA0_ADDRDEC0_BASE_ADDR_CS1
-#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0
-#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
-#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L
-#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
-//MMEA0_ADDRDEC0_BASE_ADDR_CS2
-#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0
-#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
-#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L
-#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
-//MMEA0_ADDRDEC0_BASE_ADDR_CS3
-#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0
-#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
-#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L
-#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
-//MMEA0_ADDRDEC0_BASE_ADDR_SECCS0
-#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0
-#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
-#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L
-#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
-//MMEA0_ADDRDEC0_BASE_ADDR_SECCS1
-#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0
-#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
-#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L
-#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
-//MMEA0_ADDRDEC0_BASE_ADDR_SECCS2
-#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0
-#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
-#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L
-#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
-//MMEA0_ADDRDEC0_BASE_ADDR_SECCS3
-#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0
-#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
-#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L
-#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
-//MMEA0_ADDRDEC0_ADDR_MASK_CS01
-#define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
-#define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
-//MMEA0_ADDRDEC0_ADDR_MASK_CS23
-#define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
-#define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
-//MMEA0_ADDRDEC0_ADDR_MASK_SECCS01
-#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
-#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
-//MMEA0_ADDRDEC0_ADDR_MASK_SECCS23
-#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
-#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
-//MMEA0_ADDRDEC0_ADDR_CFG_CS01
-#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2
-#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
-#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
-#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
-#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
-#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
-#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f
-#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL
-#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
-#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
-#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
-#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
-#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
-#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L
-//MMEA0_ADDRDEC0_ADDR_CFG_CS23
-#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2
-#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
-#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
-#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
-#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
-#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
-#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f
-#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL
-#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
-#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
-#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
-#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
-#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
-#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L
-//MMEA0_ADDRDEC0_ADDR_SEL_CS01
-#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0
-#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4
-#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8
-#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc
-#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10
-#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
-#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
-#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
-#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
-#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
-#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
-#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L
-#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
-#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
-//MMEA0_ADDRDEC0_ADDR_SEL_CS23
-#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0
-#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4
-#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8
-#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc
-#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10
-#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
-#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
-#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
-#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
-#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
-#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
-#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L
-#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
-#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
-//MMEA0_ADDRDEC0_COL_SEL_LO_CS01
-#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0
-#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4
-#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8
-#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc
-#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10
-#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14
-#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18
-#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
-#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
-#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
-#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
-#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
-#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
-#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
-#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
-#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
-//MMEA0_ADDRDEC0_COL_SEL_LO_CS23
-#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0
-#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4
-#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8
-#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc
-#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10
-#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14
-#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18
-#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
-#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
-#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
-#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
-#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
-#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
-#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
-#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
-#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
-//MMEA0_ADDRDEC0_COL_SEL_HI_CS01
-#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0
-#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4
-#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8
-#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc
-#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10
-#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14
-#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18
-#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
-#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
-#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
-#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
-#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
-#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
-#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
-#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
-#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
-//MMEA0_ADDRDEC0_COL_SEL_HI_CS23
-#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0
-#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4
-#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8
-#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc
-#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10
-#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14
-#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18
-#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
-#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
-#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
-#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
-#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
-#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
-#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
-#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
-#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
-//MMEA0_ADDRDEC0_RM_SEL_CS01
-#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0
-#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4
-#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8
-#define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
-#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
-#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
-#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL
-#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L
-#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L
-#define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
-#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
-#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
-//MMEA0_ADDRDEC0_RM_SEL_CS23
-#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0
-#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4
-#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8
-#define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
-#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
-#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
-#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL
-#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L
-#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L
-#define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
-#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
-#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
-//MMEA0_ADDRDEC0_RM_SEL_SECCS01
-#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0
-#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4
-#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8
-#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
-#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
-#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
-#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
-#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
-#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
-#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
-#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
-#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
-//MMEA0_ADDRDEC0_RM_SEL_SECCS23
-#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0
-#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4
-#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8
-#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
-#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
-#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
-#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
-#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
-#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
-#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
-#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
-#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
-//MMEA0_ADDRDEC1_BASE_ADDR_CS0
-#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0
-#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
-#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L
-#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
-//MMEA0_ADDRDEC1_BASE_ADDR_CS1
-#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0
-#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
-#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L
-#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
-//MMEA0_ADDRDEC1_BASE_ADDR_CS2
-#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0
-#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
-#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L
-#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
-//MMEA0_ADDRDEC1_BASE_ADDR_CS3
-#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0
-#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
-#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L
-#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
-//MMEA0_ADDRDEC1_BASE_ADDR_SECCS0
-#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0
-#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
-#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L
-#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
-//MMEA0_ADDRDEC1_BASE_ADDR_SECCS1
-#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0
-#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
-#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L
-#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
-//MMEA0_ADDRDEC1_BASE_ADDR_SECCS2
-#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0
-#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
-#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L
-#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
-//MMEA0_ADDRDEC1_BASE_ADDR_SECCS3
-#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0
-#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
-#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L
-#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
-//MMEA0_ADDRDEC1_ADDR_MASK_CS01
-#define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
-#define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
-//MMEA0_ADDRDEC1_ADDR_MASK_CS23
-#define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
-#define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
-//MMEA0_ADDRDEC1_ADDR_MASK_SECCS01
-#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
-#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
-//MMEA0_ADDRDEC1_ADDR_MASK_SECCS23
-#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
-#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
-//MMEA0_ADDRDEC1_ADDR_CFG_CS01
-#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2
-#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
-#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
-#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
-#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
-#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
-#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f
-#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL
-#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
-#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
-#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
-#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
-#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
-#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L
-//MMEA0_ADDRDEC1_ADDR_CFG_CS23
-#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2
-#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
-#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
-#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
-#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
-#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
-#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f
-#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL
-#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
-#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
-#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
-#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
-#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
-#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L
-//MMEA0_ADDRDEC1_ADDR_SEL_CS01
-#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0
-#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4
-#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8
-#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc
-#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10
-#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
-#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
-#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
-#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
-#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
-#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
-#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L
-#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
-#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
-//MMEA0_ADDRDEC1_ADDR_SEL_CS23
-#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0
-#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4
-#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8
-#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc
-#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10
-#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
-#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
-#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
-#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
-#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
-#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
-#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L
-#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
-#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
-//MMEA0_ADDRDEC1_COL_SEL_LO_CS01
-#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0
-#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4
-#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8
-#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc
-#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10
-#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14
-#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18
-#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
-#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
-#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
-#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
-#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
-#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
-#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
-#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
-#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
-//MMEA0_ADDRDEC1_COL_SEL_LO_CS23
-#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0
-#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4
-#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8
-#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc
-#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10
-#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14
-#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18
-#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
-#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
-#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
-#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
-#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
-#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
-#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
-#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
-#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
-//MMEA0_ADDRDEC1_COL_SEL_HI_CS01
-#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0
-#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4
-#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8
-#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc
-#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10
-#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14
-#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18
-#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
-#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
-#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
-#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
-#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
-#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
-#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
-#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
-#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
-//MMEA0_ADDRDEC1_COL_SEL_HI_CS23
-#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0
-#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4
-#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8
-#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc
-#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10
-#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14
-#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18
-#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
-#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
-#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
-#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
-#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
-#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
-#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
-#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
-#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
-//MMEA0_ADDRDEC1_RM_SEL_CS01
-#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0
-#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4
-#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8
-#define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
-#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
-#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
-#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL
-#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L
-#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L
-#define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
-#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
-#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
-//MMEA0_ADDRDEC1_RM_SEL_CS23
-#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0
-#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4
-#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8
-#define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
-#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
-#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
-#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL
-#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L
-#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L
-#define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
-#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
-#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
-//MMEA0_ADDRDEC1_RM_SEL_SECCS01
-#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0
-#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4
-#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8
-#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
-#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
-#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
-#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
-#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
-#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
-#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
-#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
-#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
-//MMEA0_ADDRDEC1_RM_SEL_SECCS23
-#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0
-#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4
-#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8
-#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
-#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
-#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
-#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
-#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
-#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
-#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
-#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
-#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
-//MMEA0_IO_RD_CLI2GRP_MAP0
-#define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
-#define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
-#define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
-#define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
-#define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
-#define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
-#define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
-#define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
-#define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
-#define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
-#define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
-#define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
-#define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
-#define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
-#define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
-#define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
-#define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
-#define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
-#define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
-#define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
-#define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
-#define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
-#define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
-#define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
-#define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
-#define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
-#define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
-#define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
-#define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
-#define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
-#define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
-#define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
-//MMEA0_IO_RD_CLI2GRP_MAP1
-#define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
-#define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
-#define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
-#define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
-#define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
-#define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
-#define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
-#define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
-#define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
-#define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
-#define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
-#define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
-#define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
-#define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
-#define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
-#define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
-#define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
-#define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
-#define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
-#define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
-#define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
-#define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
-#define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
-#define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
-#define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
-#define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
-#define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
-#define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
-#define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
-#define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
-#define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
-#define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
-//MMEA0_IO_WR_CLI2GRP_MAP0
-#define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
-#define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
-#define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
-#define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
-#define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
-#define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
-#define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
-#define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
-#define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
-#define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
-#define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
-#define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
-#define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
-#define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
-#define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
-#define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
-#define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
-#define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
-#define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
-#define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
-#define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
-#define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
-#define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
-#define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
-#define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
-#define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
-#define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
-#define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
-#define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
-#define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
-#define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
-#define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
-//MMEA0_IO_WR_CLI2GRP_MAP1
-#define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
-#define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
-#define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
-#define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
-#define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
-#define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
-#define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
-#define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
-#define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
-#define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
-#define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
-#define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
-#define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
-#define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
-#define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
-#define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
-#define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
-#define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
-#define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
-#define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
-#define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
-#define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
-#define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
-#define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
-#define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
-#define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
-#define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
-#define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
-#define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
-#define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
-#define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
-#define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
-//MMEA0_IO_RD_COMBINE_FLUSH
-#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0
-#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4
-#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8
-#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc
-#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL
-#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L
-#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L
-#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L
-//MMEA0_IO_WR_COMBINE_FLUSH
-#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0
-#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4
-#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8
-#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc
-#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL
-#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L
-#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L
-#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L
-//MMEA0_IO_GROUP_BURST
-#define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0
-#define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8
-#define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10
-#define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18
-#define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL
-#define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
-#define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
-#define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L
-//MMEA0_IO_RD_PRI_AGE
-#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
-#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
-#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
-#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
-#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
-#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
-#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
-#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
-#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
-#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
-#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
-#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
-#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
-#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
-#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
-#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
-//MMEA0_IO_WR_PRI_AGE
-#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
-#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
-#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
-#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
-#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
-#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
-#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
-#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
-#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
-#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
-#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
-#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
-#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
-#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
-#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
-#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
-//MMEA0_IO_RD_PRI_QUEUING
-#define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
-#define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
-#define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
-#define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
-#define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
-#define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
-#define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
-#define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
-//MMEA0_IO_WR_PRI_QUEUING
-#define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
-#define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
-#define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
-#define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
-#define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
-#define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
-#define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
-#define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
-//MMEA0_IO_RD_PRI_FIXED
-#define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
-#define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
-#define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
-#define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
-#define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
-#define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
-#define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
-#define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
-//MMEA0_IO_WR_PRI_FIXED
-#define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
-#define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
-#define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
-#define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
-#define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
-#define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
-#define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
-#define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
-//MMEA0_IO_RD_PRI_URGENCY
-#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
-#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
-#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
-#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
-#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
-#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
-#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
-#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
-#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
-#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
-#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
-#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
-#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
-#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
-#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
-#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
-//MMEA0_IO_WR_PRI_URGENCY
-#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
-#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
-#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
-#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
-#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
-#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
-#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
-#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
-#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
-#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
-#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
-#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
-#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
-#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
-#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
-#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
-//MMEA0_IO_RD_PRI_URGENCY_MASK
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L
-#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L
-//MMEA0_IO_WR_PRI_URGENCY_MASK
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L
-#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L
-//MMEA0_IO_RD_PRI_QUANT_PRI1
-#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
-#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
-#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
-#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
-#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
-//MMEA0_IO_RD_PRI_QUANT_PRI2
-#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
-#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
-#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
-#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
-#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
-//MMEA0_IO_RD_PRI_QUANT_PRI3
-#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
-#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
-#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
-#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
-#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
-//MMEA0_IO_WR_PRI_QUANT_PRI1
-#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
-#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
-#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
-#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
-#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
-//MMEA0_IO_WR_PRI_QUANT_PRI2
-#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
-#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
-#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
-#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
-#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
-//MMEA0_IO_WR_PRI_QUANT_PRI3
-#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
-#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
-#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
-#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
-#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
-//MMEA0_SDP_ARB_DRAM
-#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0
-#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8
-#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10
-#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11
-#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12
-#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13
-#define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14
-#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL
-#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L
-#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L
-#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L
-#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L
-#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L
-#define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L
-//MMEA0_SDP_ARB_FINAL
-#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0
-#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5
-#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa
-#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf
-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11
-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12
-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13
-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14
-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15
-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16
-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17
-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18
-#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19
-#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a
-#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL
-#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L
-#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L
-#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L
-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L
-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L
-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L
-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L
-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L
-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L
-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L
-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L
-#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L
-#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L
-//MMEA0_SDP_DRAM_PRIORITY
-#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0
-#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4
-#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8
-#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc
-#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10
-#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14
-#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18
-#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c
-#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL
-#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L
-#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L
-#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L
-#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L
-#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L
-#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L
-#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L
-//MMEA0_SDP_IO_PRIORITY
-#define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0
-#define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4
-#define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8
-#define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc
-#define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10
-#define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14
-#define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18
-#define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c
-#define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL
-#define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L
-#define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L
-#define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L
-#define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L
-#define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L
-#define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L
-#define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L
-//MMEA0_SDP_CREDITS
-#define MMEA0_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0
-#define MMEA0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8
-#define MMEA0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10
-#define MMEA0_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL
-#define MMEA0_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L
-#define MMEA0_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L
-//MMEA0_SDP_TAG_RESERVE0
-#define MMEA0_SDP_TAG_RESERVE0__VC0__SHIFT 0x0
-#define MMEA0_SDP_TAG_RESERVE0__VC1__SHIFT 0x8
-#define MMEA0_SDP_TAG_RESERVE0__VC2__SHIFT 0x10
-#define MMEA0_SDP_TAG_RESERVE0__VC3__SHIFT 0x18
-#define MMEA0_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL
-#define MMEA0_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L
-#define MMEA0_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L
-#define MMEA0_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L
-//MMEA0_SDP_TAG_RESERVE1
-#define MMEA0_SDP_TAG_RESERVE1__VC4__SHIFT 0x0
-#define MMEA0_SDP_TAG_RESERVE1__VC5__SHIFT 0x8
-#define MMEA0_SDP_TAG_RESERVE1__VC6__SHIFT 0x10
-#define MMEA0_SDP_TAG_RESERVE1__VC7__SHIFT 0x18
-#define MMEA0_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL
-#define MMEA0_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L
-#define MMEA0_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L
-#define MMEA0_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L
-//MMEA0_SDP_VCC_RESERVE0
-#define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0
-#define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6
-#define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc
-#define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12
-#define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18
-#define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL
-#define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L
-#define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L
-#define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L
-#define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L
-//MMEA0_SDP_VCC_RESERVE1
-#define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0
-#define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6
-#define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc
-#define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f
-#define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL
-#define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L
-#define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L
-#define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L
-//MMEA0_SDP_VCD_RESERVE0
-#define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0
-#define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6
-#define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc
-#define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12
-#define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18
-#define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL
-#define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L
-#define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L
-#define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L
-#define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L
-//MMEA0_SDP_VCD_RESERVE1
-#define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0
-#define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6
-#define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc
-#define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f
-#define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL
-#define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L
-#define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L
-#define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L
-//MMEA0_SDP_REQ_CNTL
-#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0
-#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1
-#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2
-#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3
-#define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4
-#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L
-#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L
-#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L
-#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L
-#define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L
-//MMEA0_MISC
-#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0
-#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1
-#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2
-#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3
-#define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4
-#define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5
-#define MMEA0_MISC__RRET_SWAP_MODE__SHIFT 0x6
-#define MMEA0_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x7
-#define MMEA0_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x8
-#define MMEA0_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0xa
-#define MMEA0_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0xc
-#define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xe
-#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x13
-#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x14
-#define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x15
-#define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x16
-#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x17
-#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x18
-#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L
-#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L
-#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L
-#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L
-#define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L
-#define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L
-#define MMEA0_MISC__RRET_SWAP_MODE_MASK 0x00000040L
-#define MMEA0_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000080L
-#define MMEA0_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000300L
-#define MMEA0_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00000C00L
-#define MMEA0_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00003000L
-#define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x0007C000L
-#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x00080000L
-#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x00100000L
-#define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x00200000L
-#define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x00400000L
-#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x00800000L
-#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x01000000L
-//MMEA0_LATENCY_SAMPLING
-#define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0
-#define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1
-#define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2
-#define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3
-#define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4
-#define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5
-#define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6
-#define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7
-#define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8
-#define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9
-#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa
-#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb
-#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc
-#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd
-#define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe
-#define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16
-#define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L
-#define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L
-#define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L
-#define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L
-#define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L
-#define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L
-#define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L
-#define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L
-#define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L
-#define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L
-#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L
-#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L
-#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L
-#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L
-#define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L
-#define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L
-//MMEA0_PERFCOUNTER_LO
-#define MMEA0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
-#define MMEA0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
-//MMEA0_PERFCOUNTER_HI
-#define MMEA0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
-#define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
-#define MMEA0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
-#define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
-//MMEA0_PERFCOUNTER0_CFG
-#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
-#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
-#define MMEA0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
-#define MMEA0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
-#define MMEA0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
-#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
-#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define MMEA0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
-#define MMEA0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
-#define MMEA0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
-//MMEA0_PERFCOUNTER1_CFG
-#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
-#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
-#define MMEA0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
-#define MMEA0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
-#define MMEA0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
-#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
-#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define MMEA0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
-#define MMEA0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
-#define MMEA0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
-//MMEA0_PERFCOUNTER_RSLT_CNTL
-#define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
-#define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
-#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
-#define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
-#define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
-#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
-#define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
-#define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
-#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
-#define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
-#define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
-#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
-//MMEA0_EDC_CNT
-#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0
-#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2
-#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4
-#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6
-#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8
-#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa
-#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc
-#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe
-#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10
-#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12
-#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14
-#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16
-#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18
-#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a
-#define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c
-#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
-#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
-#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
-#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
-#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
-#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
-#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L
-#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L
-#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L
-#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L
-#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L
-#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L
-#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L
-#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L
-#define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L
-//MMEA0_EDC_CNT2
-#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0
-#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2
-#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4
-#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6
-#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8
-#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa
-#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc
-#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe
-#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
-#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
-#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
-#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
-#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
-#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
-#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L
-#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L
-//MMEA0_DSM_CNTL
-#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0
-#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
-#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3
-#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5
-#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6
-#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8
-#define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9
-#define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb
-#define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc
-#define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
-#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf
-#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11
-#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12
-#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14
-#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15
-#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17
-#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
-#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
-#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L
-#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L
-#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L
-#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
-#define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L
-#define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
-#define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L
-#define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
-#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L
-#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L
-#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L
-#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L
-#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L
-#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L
-//MMEA0_DSM_CNTLA
-#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0
-#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
-#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3
-#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5
-#define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6
-#define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8
-#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9
-#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb
-#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc
-#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
-#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf
-#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11
-#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12
-#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14
-#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
-#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
-#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L
-#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L
-#define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L
-#define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
-#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L
-#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
-#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L
-#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
-#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L
-#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L
-#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L
-#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L
-//MMEA0_DSM_CNTLB
-//MMEA0_DSM_CNTL2
-#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2
-#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3
-#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5
-#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6
-#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8
-#define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9
-#define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb
-#define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc
-#define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe
-#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf
-#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11
-#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12
-#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14
-#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15
-#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17
-#define MMEA0_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
-#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L
-#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L
-#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
-#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L
-#define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L
-#define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L
-#define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
-#define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L
-#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L
-#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L
-#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L
-#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L
-#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L
-#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L
-#define MMEA0_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
-//MMEA0_DSM_CNTL2A
-#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2
-#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3
-#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5
-#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6
-#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8
-#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9
-#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb
-#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc
-#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe
-#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf
-#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11
-#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12
-#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14
-#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L
-#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L
-#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
-#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L
-#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L
-#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L
-#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
-#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L
-#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L
-#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L
-#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L
-#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L
-//MMEA0_DSM_CNTL2B
-//MMEA0_CGTT_CLK_CTRL
-#define MMEA0_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14
-#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15
-#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16
-#define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
-#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c
-#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d
-#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e
-#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f
-#define MMEA0_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L
-#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L
-#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L
-#define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
-#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L
-#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L
-#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L
-#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L
-//MMEA0_EDC_MODE
-#define MMEA0_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10
-#define MMEA0_EDC_MODE__GATE_FUE__SHIFT 0x11
-#define MMEA0_EDC_MODE__DED_MODE__SHIFT 0x14
-#define MMEA0_EDC_MODE__PROP_FED__SHIFT 0x1d
-#define MMEA0_EDC_MODE__BYPASS__SHIFT 0x1f
-#define MMEA0_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L
-#define MMEA0_EDC_MODE__GATE_FUE_MASK 0x00020000L
-#define MMEA0_EDC_MODE__DED_MODE_MASK 0x00300000L
-#define MMEA0_EDC_MODE__PROP_FED_MASK 0x20000000L
-#define MMEA0_EDC_MODE__BYPASS_MASK 0x80000000L
-//MMEA0_ERR_STATUS
-#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0
-#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4
-#define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8
-#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa
-#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb
-#define MMEA0_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc
-#define MMEA0_ERR_STATUS__FUE_FLAG__SHIFT 0xd
-#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL
-#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L
-#define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L
-#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L
-#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L
-#define MMEA0_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L
-#define MMEA0_ERR_STATUS__FUE_FLAG_MASK 0x00002000L
-//MMEA0_MISC2
-#define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0
-#define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1
-#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2
-#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7
-#define MMEA0_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc
-#define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L
-#define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L
-#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL
-#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L
-#define MMEA0_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L
-//MMEA1_DRAM_RD_CLI2GRP_MAP0
-#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
-#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
-#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
-#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
-#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
-#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
-#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
-#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
-#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
-#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
-#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
-#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
-#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
-#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
-#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
-#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
-#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
-#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
-#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
-#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
-#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
-#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
-#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
-#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
-#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
-#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
-#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
-#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
-#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
-#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
-#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
-#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
-//MMEA1_DRAM_RD_CLI2GRP_MAP1
-#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
-#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
-#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
-#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
-#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
-#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
-#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
-#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
-#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
-#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
-#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
-#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
-#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
-#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
-#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
-#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
-#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
-#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
-#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
-#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
-#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
-#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
-#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
-#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
-#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
-#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
-#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
-#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
-#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
-#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
-#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
-#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
-//MMEA1_DRAM_WR_CLI2GRP_MAP0
-#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
-#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
-#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
-#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
-#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
-#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
-#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
-#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
-#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
-#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
-#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
-#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
-#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
-#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
-#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
-#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
-#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
-#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
-#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
-#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
-#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
-#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
-#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
-#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
-#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
-#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
-#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
-#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
-#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
-#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
-#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
-#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
-//MMEA1_DRAM_WR_CLI2GRP_MAP1
-#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
-#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
-#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
-#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
-#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
-#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
-#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
-#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
-#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
-#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
-#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
-#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
-#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
-#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
-#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
-#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
-#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
-#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
-#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
-#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
-#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
-#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
-#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
-#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
-#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
-#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
-#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
-#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
-#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
-#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
-#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
-#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
-//MMEA1_DRAM_RD_GRP2VC_MAP
-#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
-#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
-#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
-#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
-#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
-#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
-#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
-#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
-//MMEA1_DRAM_WR_GRP2VC_MAP
-#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
-#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
-#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
-#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
-#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
-#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
-#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
-#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
-//MMEA1_DRAM_RD_LAZY
-#define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0
-#define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3
-#define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6
-#define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9
-#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
-#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
-#define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L
-#define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L
-#define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L
-#define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L
-#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
-#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
-//MMEA1_DRAM_WR_LAZY
-#define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0
-#define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3
-#define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6
-#define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9
-#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
-#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
-#define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L
-#define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L
-#define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L
-#define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L
-#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
-#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
-//MMEA1_DRAM_RD_CAM_CNTL
-#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
-#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
-#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
-#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
-#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
-#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
-#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
-#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
-#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
-#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
-#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
-#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
-#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
-#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
-#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
-#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
-//MMEA1_DRAM_WR_CAM_CNTL
-#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
-#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
-#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
-#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
-#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
-#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
-#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
-#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
-#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
-#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
-#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
-#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
-#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
-#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
-#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
-#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
-//MMEA1_DRAM_PAGE_BURST
-#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0
-#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8
-#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10
-#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18
-#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL
-#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
-#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
-#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L
-//MMEA1_DRAM_RD_PRI_AGE
-#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
-#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
-#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
-#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
-#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
-#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
-#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
-#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
-#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
-#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
-#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
-#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
-#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
-#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
-#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
-#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
-//MMEA1_DRAM_WR_PRI_AGE
-#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
-#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
-#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
-#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
-#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
-#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
-#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
-#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
-#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
-#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
-#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
-#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
-#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
-#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
-#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
-#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
-//MMEA1_DRAM_RD_PRI_QUEUING
-#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
-#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
-#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
-#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
-#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
-#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
-#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
-#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
-//MMEA1_DRAM_WR_PRI_QUEUING
-#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
-#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
-#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
-#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
-#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
-#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
-#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
-#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
-//MMEA1_DRAM_RD_PRI_FIXED
-#define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
-#define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
-#define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
-#define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
-#define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
-#define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
-#define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
-#define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
-//MMEA1_DRAM_WR_PRI_FIXED
-#define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
-#define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
-#define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
-#define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
-#define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
-#define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
-#define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
-#define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
-//MMEA1_DRAM_RD_PRI_URGENCY
-#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
-#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
-#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
-#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
-#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
-#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
-#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
-#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
-#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
-#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
-#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
-#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
-#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
-#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
-#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
-#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
-//MMEA1_DRAM_WR_PRI_URGENCY
-#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
-#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
-#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
-#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
-#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
-#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
-#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
-#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
-#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
-#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
-#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
-#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
-#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
-#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
-#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
-#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
-//MMEA1_DRAM_RD_PRI_QUANT_PRI1
-#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
-#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
-#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
-#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
-#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
-//MMEA1_DRAM_RD_PRI_QUANT_PRI2
-#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
-#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
-#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
-#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
-#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
-//MMEA1_DRAM_RD_PRI_QUANT_PRI3
-#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
-#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
-#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
-#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
-#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
-//MMEA1_DRAM_WR_PRI_QUANT_PRI1
-#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
-#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
-#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
-#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
-#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
-//MMEA1_DRAM_WR_PRI_QUANT_PRI2
-#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
-#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
-#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
-#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
-#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
-//MMEA1_DRAM_WR_PRI_QUANT_PRI3
-#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
-#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
-#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
-#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
-#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
-//MMEA1_ADDRNORM_BASE_ADDR0
-#define MMEA1_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0
-#define MMEA1_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1
-#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x4
-#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x8
-#define MMEA1_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc
-#define MMEA1_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L
-#define MMEA1_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
-#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x000000F0L
-#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000700L
-#define MMEA1_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L
-//MMEA1_ADDRNORM_LIMIT_ADDR0
-#define MMEA1_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0
-#define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8
-#define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES__SHIFT 0xa
-#define MMEA1_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc
-#define MMEA1_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL
-#define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L
-#define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES_MASK 0x00000C00L
-#define MMEA1_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L
-//MMEA1_ADDRNORM_BASE_ADDR1
-#define MMEA1_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0
-#define MMEA1_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1
-#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x4
-#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x8
-#define MMEA1_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc
-#define MMEA1_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L
-#define MMEA1_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
-#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x000000F0L
-#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000700L
-#define MMEA1_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L
-//MMEA1_ADDRNORM_LIMIT_ADDR1
-#define MMEA1_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0
-#define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8
-#define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES__SHIFT 0xa
-#define MMEA1_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc
-#define MMEA1_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL
-#define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L
-#define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES_MASK 0x00000C00L
-#define MMEA1_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L
-//MMEA1_ADDRNORM_OFFSET_ADDR1
-#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0
-#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14
-#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L
-#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L
-//MMEA1_ADDRNORMDRAM_HOLE_CNTL
-#define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0
-#define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7
-#define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L
-#define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L
-//MMEA1_ADDRNORMDRAM_TRICHANNEL_CFG
-#define MMEA1_ADDRNORMDRAM_TRICHANNEL_CFG__LOG2_ADDR64K_SPACE__SHIFT 0x0
-#define MMEA1_ADDRNORMDRAM_TRICHANNEL_CFG__LOG2_ADDR64K_SPACE_MASK 0x0000003FL
-//MMEA1_ADDRDEC_BANK_CFG
-#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0
-#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x5
-#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa
-#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xd
-#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x10
-#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x11
-#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001FL
-#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003E0L
-#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001C00L
-#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000E000L
-#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L
-#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L
-//MMEA1_ADDRDEC_MISC_CFG
-#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0
-#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1
-#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2
-#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x3
-#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x4
-#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8
-#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9
-#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc
-#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11
-#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16
-#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18
-#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a
-#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d
-#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L
-#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L
-#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L
-#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L
-#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L
-#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L
-#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L
-#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L
-#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L
-#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L
-#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L
-#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L
-#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L
-//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L
-//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L
-//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L
-//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L
-//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L
-//MMEA1_ADDRDECDRAM_ADDR_HASH_PC
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L
-//MMEA1_ADDRDECDRAM_ADDR_HASH_PC2
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000001FL
-//MMEA1_ADDRDECDRAM_ADDR_HASH_CS0
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL
-//MMEA1_ADDRDECDRAM_ADDR_HASH_CS1
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L
-#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL
-//MMEA1_ADDRDECDRAM_HARVEST_ENABLE
-#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0
-#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1
-#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2
-#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3
-#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L
-#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L
-#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L
-#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L
-//MMEA1_ADDRDEC0_BASE_ADDR_CS0
-#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0
-#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
-#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L
-#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
-//MMEA1_ADDRDEC0_BASE_ADDR_CS1
-#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0
-#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
-#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L
-#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
-//MMEA1_ADDRDEC0_BASE_ADDR_CS2
-#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0
-#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
-#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L
-#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
-//MMEA1_ADDRDEC0_BASE_ADDR_CS3
-#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0
-#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
-#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L
-#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
-//MMEA1_ADDRDEC0_BASE_ADDR_SECCS0
-#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0
-#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
-#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L
-#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
-//MMEA1_ADDRDEC0_BASE_ADDR_SECCS1
-#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0
-#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
-#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L
-#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
-//MMEA1_ADDRDEC0_BASE_ADDR_SECCS2
-#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0
-#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
-#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L
-#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
-//MMEA1_ADDRDEC0_BASE_ADDR_SECCS3
-#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0
-#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
-#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L
-#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
-//MMEA1_ADDRDEC0_ADDR_MASK_CS01
-#define MMEA1_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
-#define MMEA1_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
-//MMEA1_ADDRDEC0_ADDR_MASK_CS23
-#define MMEA1_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
-#define MMEA1_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
-//MMEA1_ADDRDEC0_ADDR_MASK_SECCS01
-#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
-#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
-//MMEA1_ADDRDEC0_ADDR_MASK_SECCS23
-#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
-#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
-//MMEA1_ADDRDEC0_ADDR_CFG_CS01
-#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2
-#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
-#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
-#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
-#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
-#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
-#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f
-#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL
-#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
-#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
-#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
-#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
-#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
-#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L
-//MMEA1_ADDRDEC0_ADDR_CFG_CS23
-#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2
-#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
-#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
-#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
-#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
-#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
-#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f
-#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL
-#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
-#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
-#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
-#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
-#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
-#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L
-//MMEA1_ADDRDEC0_ADDR_SEL_CS01
-#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0
-#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4
-#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8
-#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc
-#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10
-#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
-#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
-#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
-#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
-#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
-#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
-#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L
-#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
-#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
-//MMEA1_ADDRDEC0_ADDR_SEL_CS23
-#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0
-#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4
-#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8
-#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc
-#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10
-#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
-#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
-#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
-#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
-#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
-#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
-#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L
-#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
-#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
-//MMEA1_ADDRDEC0_COL_SEL_LO_CS01
-#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0
-#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4
-#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8
-#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc
-#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10
-#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14
-#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18
-#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
-#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
-#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
-#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
-#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
-#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
-#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
-#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
-#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
-//MMEA1_ADDRDEC0_COL_SEL_LO_CS23
-#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0
-#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4
-#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8
-#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc
-#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10
-#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14
-#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18
-#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
-#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
-#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
-#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
-#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
-#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
-#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
-#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
-#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
-//MMEA1_ADDRDEC0_COL_SEL_HI_CS01
-#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0
-#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4
-#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8
-#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc
-#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10
-#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14
-#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18
-#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
-#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
-#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
-#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
-#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
-#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
-#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
-#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
-#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
-//MMEA1_ADDRDEC0_COL_SEL_HI_CS23
-#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0
-#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4
-#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8
-#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc
-#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10
-#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14
-#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18
-#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
-#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
-#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
-#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
-#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
-#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
-#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
-#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
-#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
-//MMEA1_ADDRDEC0_RM_SEL_CS01
-#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0
-#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4
-#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8
-#define MMEA1_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
-#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
-#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
-#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL
-#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L
-#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L
-#define MMEA1_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
-#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
-#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
-//MMEA1_ADDRDEC0_RM_SEL_CS23
-#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0
-#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4
-#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8
-#define MMEA1_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
-#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
-#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
-#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL
-#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L
-#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L
-#define MMEA1_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
-#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
-#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
-//MMEA1_ADDRDEC0_RM_SEL_SECCS01
-#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0
-#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4
-#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8
-#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
-#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
-#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
-#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
-#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
-#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
-#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
-#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
-#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
-//MMEA1_ADDRDEC0_RM_SEL_SECCS23
-#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0
-#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4
-#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8
-#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
-#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
-#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
-#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
-#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
-#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
-#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
-#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
-#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
-//MMEA1_ADDRDEC1_BASE_ADDR_CS0
-#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0
-#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
-#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L
-#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
-//MMEA1_ADDRDEC1_BASE_ADDR_CS1
-#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0
-#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
-#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L
-#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
-//MMEA1_ADDRDEC1_BASE_ADDR_CS2
-#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0
-#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
-#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L
-#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
-//MMEA1_ADDRDEC1_BASE_ADDR_CS3
-#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0
-#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
-#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L
-#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
-//MMEA1_ADDRDEC1_BASE_ADDR_SECCS0
-#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0
-#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
-#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L
-#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
-//MMEA1_ADDRDEC1_BASE_ADDR_SECCS1
-#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0
-#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
-#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L
-#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
-//MMEA1_ADDRDEC1_BASE_ADDR_SECCS2
-#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0
-#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
-#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L
-#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
-//MMEA1_ADDRDEC1_BASE_ADDR_SECCS3
-#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0
-#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
-#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L
-#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
-//MMEA1_ADDRDEC1_ADDR_MASK_CS01
-#define MMEA1_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
-#define MMEA1_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
-//MMEA1_ADDRDEC1_ADDR_MASK_CS23
-#define MMEA1_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
-#define MMEA1_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
-//MMEA1_ADDRDEC1_ADDR_MASK_SECCS01
-#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
-#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
-//MMEA1_ADDRDEC1_ADDR_MASK_SECCS23
-#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
-#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
-//MMEA1_ADDRDEC1_ADDR_CFG_CS01
-#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2
-#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
-#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
-#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
-#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
-#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
-#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f
-#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL
-#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
-#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
-#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
-#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
-#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
-#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L
-//MMEA1_ADDRDEC1_ADDR_CFG_CS23
-#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2
-#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
-#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
-#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
-#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
-#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
-#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f
-#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL
-#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
-#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
-#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
-#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
-#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
-#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L
-//MMEA1_ADDRDEC1_ADDR_SEL_CS01
-#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0
-#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4
-#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8
-#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc
-#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10
-#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
-#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
-#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
-#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
-#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
-#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
-#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L
-#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
-#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
-//MMEA1_ADDRDEC1_ADDR_SEL_CS23
-#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0
-#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4
-#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8
-#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc
-#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10
-#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
-#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
-#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
-#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
-#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
-#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
-#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L
-#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
-#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
-//MMEA1_ADDRDEC1_COL_SEL_LO_CS01
-#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0
-#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4
-#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8
-#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc
-#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10
-#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14
-#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18
-#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
-#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
-#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
-#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
-#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
-#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
-#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
-#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
-#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
-//MMEA1_ADDRDEC1_COL_SEL_LO_CS23
-#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0
-#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4
-#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8
-#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc
-#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10
-#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14
-#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18
-#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
-#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
-#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
-#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
-#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
-#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
-#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
-#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
-#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
-//MMEA1_ADDRDEC1_COL_SEL_HI_CS01
-#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0
-#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4
-#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8
-#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc
-#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10
-#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14
-#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18
-#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
-#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
-#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
-#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
-#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
-#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
-#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
-#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
-#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
-//MMEA1_ADDRDEC1_COL_SEL_HI_CS23
-#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0
-#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4
-#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8
-#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc
-#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10
-#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14
-#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18
-#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
-#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
-#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
-#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
-#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
-#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
-#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
-#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
-#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
-//MMEA1_ADDRDEC1_RM_SEL_CS01
-#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0
-#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4
-#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8
-#define MMEA1_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
-#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
-#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
-#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL
-#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L
-#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L
-#define MMEA1_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
-#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
-#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
-//MMEA1_ADDRDEC1_RM_SEL_CS23
-#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0
-#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4
-#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8
-#define MMEA1_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
-#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
-#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
-#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL
-#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L
-#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L
-#define MMEA1_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
-#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
-#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
-//MMEA1_ADDRDEC1_RM_SEL_SECCS01
-#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0
-#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4
-#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8
-#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
-#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
-#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
-#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
-#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
-#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
-#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
-#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
-#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
-//MMEA1_ADDRDEC1_RM_SEL_SECCS23
-#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0
-#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4
-#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8
-#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
-#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
-#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
-#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
-#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
-#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
-#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
-#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
-#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
-//MMEA1_IO_RD_CLI2GRP_MAP0
-#define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
-#define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
-#define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
-#define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
-#define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
-#define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
-#define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
-#define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
-#define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
-#define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
-#define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
-#define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
-#define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
-#define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
-#define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
-#define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
-#define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
-#define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
-#define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
-#define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
-#define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
-#define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
-#define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
-#define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
-#define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
-#define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
-#define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
-#define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
-#define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
-#define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
-#define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
-#define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
-//MMEA1_IO_RD_CLI2GRP_MAP1
-#define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
-#define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
-#define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
-#define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
-#define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
-#define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
-#define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
-#define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
-#define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
-#define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
-#define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
-#define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
-#define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
-#define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
-#define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
-#define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
-#define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
-#define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
-#define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
-#define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
-#define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
-#define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
-#define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
-#define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
-#define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
-#define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
-#define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
-#define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
-#define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
-#define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
-#define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
-#define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
-//MMEA1_IO_WR_CLI2GRP_MAP0
-#define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
-#define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
-#define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
-#define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
-#define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
-#define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
-#define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
-#define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
-#define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
-#define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
-#define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
-#define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
-#define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
-#define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
-#define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
-#define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
-#define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
-#define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
-#define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
-#define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
-#define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
-#define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
-#define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
-#define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
-#define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
-#define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
-#define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
-#define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
-#define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
-#define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
-#define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
-#define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
-//MMEA1_IO_WR_CLI2GRP_MAP1
-#define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
-#define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
-#define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
-#define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
-#define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
-#define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
-#define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
-#define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
-#define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
-#define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
-#define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
-#define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
-#define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
-#define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
-#define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
-#define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
-#define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
-#define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
-#define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
-#define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
-#define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
-#define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
-#define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
-#define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
-#define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
-#define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
-#define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
-#define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
-#define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
-#define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
-#define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
-#define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
-//MMEA1_IO_RD_COMBINE_FLUSH
-#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0
-#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4
-#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8
-#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc
-#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL
-#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L
-#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L
-#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L
-//MMEA1_IO_WR_COMBINE_FLUSH
-#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0
-#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4
-#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8
-#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc
-#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL
-#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L
-#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L
-#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L
-//MMEA1_IO_GROUP_BURST
-#define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0
-#define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8
-#define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10
-#define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18
-#define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL
-#define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
-#define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
-#define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L
-//MMEA1_IO_RD_PRI_AGE
-#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
-#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
-#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
-#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
-#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
-#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
-#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
-#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
-#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
-#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
-#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
-#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
-#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
-#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
-#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
-#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
-//MMEA1_IO_WR_PRI_AGE
-#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
-#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
-#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
-#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
-#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
-#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
-#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
-#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
-#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
-#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
-#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
-#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
-#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
-#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
-#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
-#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
-//MMEA1_IO_RD_PRI_QUEUING
-#define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
-#define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
-#define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
-#define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
-#define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
-#define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
-#define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
-#define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
-//MMEA1_IO_WR_PRI_QUEUING
-#define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
-#define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
-#define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
-#define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
-#define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
-#define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
-#define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
-#define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
-//MMEA1_IO_RD_PRI_FIXED
-#define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
-#define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
-#define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
-#define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
-#define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
-#define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
-#define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
-#define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
-//MMEA1_IO_WR_PRI_FIXED
-#define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
-#define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
-#define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
-#define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
-#define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
-#define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
-#define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
-#define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
-//MMEA1_IO_RD_PRI_URGENCY
-#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
-#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
-#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
-#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
-#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
-#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
-#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
-#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
-#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
-#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
-#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
-#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
-#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
-#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
-#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
-#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
-//MMEA1_IO_WR_PRI_URGENCY
-#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
-#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
-#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
-#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
-#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
-#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
-#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
-#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
-#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
-#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
-#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
-#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
-#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
-#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
-#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
-#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
-//MMEA1_IO_RD_PRI_URGENCY_MASK
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L
-#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L
-//MMEA1_IO_WR_PRI_URGENCY_MASK
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L
-#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L
-//MMEA1_IO_RD_PRI_QUANT_PRI1
-#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
-#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
-#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
-#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
-#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
-//MMEA1_IO_RD_PRI_QUANT_PRI2
-#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
-#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
-#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
-#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
-#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
-//MMEA1_IO_RD_PRI_QUANT_PRI3
-#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
-#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
-#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
-#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
-#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
-//MMEA1_IO_WR_PRI_QUANT_PRI1
-#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
-#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
-#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
-#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
-#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
-//MMEA1_IO_WR_PRI_QUANT_PRI2
-#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
-#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
-#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
-#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
-#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
-//MMEA1_IO_WR_PRI_QUANT_PRI3
-#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
-#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
-#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
-#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
-#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
-#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
-#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
-#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
-//MMEA1_SDP_ARB_DRAM
-#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0
-#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8
-#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10
-#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11
-#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12
-#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13
-#define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14
-#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL
-#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L
-#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L
-#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L
-#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L
-#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L
-#define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L
-//MMEA1_SDP_ARB_FINAL
-#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0
-#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5
-#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa
-#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf
-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11
-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12
-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13
-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14
-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15
-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16
-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17
-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18
-#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19
-#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a
-#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL
-#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L
-#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L
-#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L
-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L
-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L
-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L
-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L
-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L
-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L
-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L
-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L
-#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L
-#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L
-//MMEA1_SDP_DRAM_PRIORITY
-#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0
-#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4
-#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8
-#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc
-#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10
-#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14
-#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18
-#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c
-#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL
-#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L
-#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L
-#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L
-#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L
-#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L
-#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L
-#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L
-//MMEA1_SDP_IO_PRIORITY
-#define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0
-#define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4
-#define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8
-#define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc
-#define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10
-#define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14
-#define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18
-#define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c
-#define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL
-#define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L
-#define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L
-#define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L
-#define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L
-#define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L
-#define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L
-#define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L
-//MMEA1_SDP_CREDITS
-#define MMEA1_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0
-#define MMEA1_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8
-#define MMEA1_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10
-#define MMEA1_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL
-#define MMEA1_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L
-#define MMEA1_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L
-//MMEA1_SDP_TAG_RESERVE0
-#define MMEA1_SDP_TAG_RESERVE0__VC0__SHIFT 0x0
-#define MMEA1_SDP_TAG_RESERVE0__VC1__SHIFT 0x8
-#define MMEA1_SDP_TAG_RESERVE0__VC2__SHIFT 0x10
-#define MMEA1_SDP_TAG_RESERVE0__VC3__SHIFT 0x18
-#define MMEA1_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL
-#define MMEA1_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L
-#define MMEA1_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L
-#define MMEA1_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L
-//MMEA1_SDP_TAG_RESERVE1
-#define MMEA1_SDP_TAG_RESERVE1__VC4__SHIFT 0x0
-#define MMEA1_SDP_TAG_RESERVE1__VC5__SHIFT 0x8
-#define MMEA1_SDP_TAG_RESERVE1__VC6__SHIFT 0x10
-#define MMEA1_SDP_TAG_RESERVE1__VC7__SHIFT 0x18
-#define MMEA1_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL
-#define MMEA1_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L
-#define MMEA1_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L
-#define MMEA1_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L
-//MMEA1_SDP_VCC_RESERVE0
-#define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0
-#define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6
-#define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc
-#define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12
-#define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18
-#define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL
-#define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L
-#define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L
-#define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L
-#define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L
-//MMEA1_SDP_VCC_RESERVE1
-#define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0
-#define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6
-#define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc
-#define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f
-#define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL
-#define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L
-#define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L
-#define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L
-//MMEA1_SDP_VCD_RESERVE0
-#define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0
-#define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6
-#define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc
-#define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12
-#define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18
-#define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL
-#define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L
-#define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L
-#define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L
-#define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L
-//MMEA1_SDP_VCD_RESERVE1
-#define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0
-#define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6
-#define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc
-#define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f
-#define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL
-#define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L
-#define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L
-#define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L
-//MMEA1_SDP_REQ_CNTL
-#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0
-#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1
-#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2
-#define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3
-#define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4
-#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L
-#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L
-#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L
-#define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L
-#define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L
-//MMEA1_MISC
-#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0
-#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1
-#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2
-#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3
-#define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4
-#define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5
-#define MMEA1_MISC__RRET_SWAP_MODE__SHIFT 0x6
-#define MMEA1_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x7
-#define MMEA1_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x8
-#define MMEA1_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0xa
-#define MMEA1_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0xc
-#define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xe
-#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x13
-#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x14
-#define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x15
-#define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x16
-#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x17
-#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x18
-#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L
-#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L
-#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L
-#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L
-#define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L
-#define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L
-#define MMEA1_MISC__RRET_SWAP_MODE_MASK 0x00000040L
-#define MMEA1_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000080L
-#define MMEA1_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000300L
-#define MMEA1_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00000C00L
-#define MMEA1_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00003000L
-#define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x0007C000L
-#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x00080000L
-#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x00100000L
-#define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x00200000L
-#define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x00400000L
-#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x00800000L
-#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x01000000L
-//MMEA1_LATENCY_SAMPLING
-#define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0
-#define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1
-#define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2
-#define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3
-#define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4
-#define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5
-#define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6
-#define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7
-#define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8
-#define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9
-#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa
-#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb
-#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc
-#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd
-#define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe
-#define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16
-#define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L
-#define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L
-#define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L
-#define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L
-#define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L
-#define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L
-#define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L
-#define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L
-#define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L
-#define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L
-#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L
-#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L
-#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L
-#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L
-#define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L
-#define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L
-//MMEA1_PERFCOUNTER_LO
-#define MMEA1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
-#define MMEA1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
-//MMEA1_PERFCOUNTER_HI
-#define MMEA1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
-#define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
-#define MMEA1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
-#define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
-//MMEA1_PERFCOUNTER0_CFG
-#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
-#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
-#define MMEA1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
-#define MMEA1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
-#define MMEA1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
-#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
-#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define MMEA1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
-#define MMEA1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
-#define MMEA1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
-//MMEA1_PERFCOUNTER1_CFG
-#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
-#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
-#define MMEA1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
-#define MMEA1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
-#define MMEA1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
-#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
-#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define MMEA1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
-#define MMEA1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
-#define MMEA1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
-//MMEA1_PERFCOUNTER_RSLT_CNTL
-#define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
-#define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
-#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
-#define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
-#define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
-#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
-#define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
-#define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
-#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
-#define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
-#define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
-#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
-//MMEA1_EDC_CNT
-#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0
-#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2
-#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4
-#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6
-#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8
-#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa
-#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc
-#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe
-#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10
-#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12
-#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14
-#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16
-#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18
-#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a
-#define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c
-#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
-#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
-#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
-#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
-#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
-#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
-#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L
-#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L
-#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L
-#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L
-#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L
-#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L
-#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L
-#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L
-#define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L
-//MMEA1_EDC_CNT2
-#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0
-#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2
-#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4
-#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6
-#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8
-#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa
-#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc
-#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe
-#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
-#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
-#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
-#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
-#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
-#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
-#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L
-#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L
-//MMEA1_DSM_CNTL
-#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0
-#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
-#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3
-#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5
-#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6
-#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8
-#define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9
-#define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb
-#define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc
-#define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
-#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf
-#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11
-#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12
-#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14
-#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15
-#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17
-#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
-#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
-#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L
-#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L
-#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L
-#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
-#define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L
-#define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
-#define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L
-#define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
-#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L
-#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L
-#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L
-#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L
-#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L
-#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L
-//MMEA1_DSM_CNTLA
-#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0
-#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
-#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3
-#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5
-#define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6
-#define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8
-#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9
-#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb
-#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc
-#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
-#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf
-#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11
-#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12
-#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14
-#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
-#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
-#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L
-#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L
-#define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L
-#define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
-#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L
-#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
-#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L
-#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
-#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L
-#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L
-#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L
-#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L
-//MMEA1_DSM_CNTLB
-//MMEA1_DSM_CNTL2
-#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2
-#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3
-#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5
-#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6
-#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8
-#define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9
-#define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb
-#define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc
-#define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe
-#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf
-#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11
-#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12
-#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14
-#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15
-#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17
-#define MMEA1_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
-#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L
-#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L
-#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
-#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L
-#define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L
-#define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L
-#define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
-#define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L
-#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L
-#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L
-#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L
-#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L
-#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L
-#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L
-#define MMEA1_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
-//MMEA1_DSM_CNTL2A
-#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0
-#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2
-#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3
-#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5
-#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6
-#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8
-#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9
-#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb
-#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc
-#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe
-#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf
-#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11
-#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12
-#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14
-#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
-#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L
-#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L
-#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L
-#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
-#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L
-#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L
-#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L
-#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
-#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L
-#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L
-#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L
-#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L
-#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L
-//MMEA1_DSM_CNTL2B
-//MMEA1_CGTT_CLK_CTRL
-#define MMEA1_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14
-#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15
-#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16
-#define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
-#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c
-#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d
-#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e
-#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f
-#define MMEA1_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L
-#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L
-#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L
-#define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
-#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L
-#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L
-#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L
-#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L
-//MMEA1_EDC_MODE
-#define MMEA1_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10
-#define MMEA1_EDC_MODE__GATE_FUE__SHIFT 0x11
-#define MMEA1_EDC_MODE__DED_MODE__SHIFT 0x14
-#define MMEA1_EDC_MODE__PROP_FED__SHIFT 0x1d
-#define MMEA1_EDC_MODE__BYPASS__SHIFT 0x1f
-#define MMEA1_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L
-#define MMEA1_EDC_MODE__GATE_FUE_MASK 0x00020000L
-#define MMEA1_EDC_MODE__DED_MODE_MASK 0x00300000L
-#define MMEA1_EDC_MODE__PROP_FED_MASK 0x20000000L
-#define MMEA1_EDC_MODE__BYPASS_MASK 0x80000000L
-//MMEA1_ERR_STATUS
-#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0
-#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4
-#define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8
-#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa
-#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb
-#define MMEA1_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc
-#define MMEA1_ERR_STATUS__FUE_FLAG__SHIFT 0xd
-#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL
-#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L
-#define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L
-#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L
-#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L
-#define MMEA1_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L
-#define MMEA1_ERR_STATUS__FUE_FLAG_MASK 0x00002000L
-//MMEA1_MISC2
-#define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0
-#define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1
-#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2
-#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7
-#define MMEA1_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc
-#define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L
-#define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L
-#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL
-#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L
-#define MMEA1_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L
-
-
-// addressBlock: mmhub_pctldec
-//PCTL_MISC
-#define PCTL_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x0
-#define PCTL_MISC__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT 0x3
-#define PCTL_MISC__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT 0x6
-#define PCTL_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0xb
-#define PCTL_MISC__IGNORE_EA0_SDP_ACK__SHIFT 0xc
-#define PCTL_MISC__IGNORE_EA1_SDP_ACK__SHIFT 0xd
-#define PCTL_MISC__PGFSM_CMD_STATUS__SHIFT 0xe
-#define PCTL_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x00000007L
-#define PCTL_MISC__STCTRL_RSMU_IDLE_THRESHOLD_MASK 0x00000038L
-#define PCTL_MISC__STCTRL_DAGB_IDLE_THRESHOLD_MASK 0x000007C0L
-#define PCTL_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x00000800L
-#define PCTL_MISC__IGNORE_EA0_SDP_ACK_MASK 0x00001000L
-#define PCTL_MISC__IGNORE_EA1_SDP_ACK_MASK 0x00002000L
-#define PCTL_MISC__PGFSM_CMD_STATUS_MASK 0x0000C000L
-//PCTL_MMHUB_DEEPSLEEP
-#define PCTL_MMHUB_DEEPSLEEP__DS0__SHIFT 0x0
-#define PCTL_MMHUB_DEEPSLEEP__DS1__SHIFT 0x1
-#define PCTL_MMHUB_DEEPSLEEP__DS2__SHIFT 0x2
-#define PCTL_MMHUB_DEEPSLEEP__DS3__SHIFT 0x3
-#define PCTL_MMHUB_DEEPSLEEP__DS4__SHIFT 0x4
-#define PCTL_MMHUB_DEEPSLEEP__DS5__SHIFT 0x5
-#define PCTL_MMHUB_DEEPSLEEP__DS6__SHIFT 0x6
-#define PCTL_MMHUB_DEEPSLEEP__DS7__SHIFT 0x7
-#define PCTL_MMHUB_DEEPSLEEP__DS8__SHIFT 0x8
-#define PCTL_MMHUB_DEEPSLEEP__DS9__SHIFT 0x9
-#define PCTL_MMHUB_DEEPSLEEP__DS10__SHIFT 0xa
-#define PCTL_MMHUB_DEEPSLEEP__DS11__SHIFT 0xb
-#define PCTL_MMHUB_DEEPSLEEP__DS12__SHIFT 0xc
-#define PCTL_MMHUB_DEEPSLEEP__DS13__SHIFT 0xd
-#define PCTL_MMHUB_DEEPSLEEP__DS14__SHIFT 0xe
-#define PCTL_MMHUB_DEEPSLEEP__DS15__SHIFT 0xf
-#define PCTL_MMHUB_DEEPSLEEP__DS16__SHIFT 0x10
-#define PCTL_MMHUB_DEEPSLEEP__SETCLEAR__SHIFT 0x1f
-#define PCTL_MMHUB_DEEPSLEEP__DS0_MASK 0x00000001L
-#define PCTL_MMHUB_DEEPSLEEP__DS1_MASK 0x00000002L
-#define PCTL_MMHUB_DEEPSLEEP__DS2_MASK 0x00000004L
-#define PCTL_MMHUB_DEEPSLEEP__DS3_MASK 0x00000008L
-#define PCTL_MMHUB_DEEPSLEEP__DS4_MASK 0x00000010L
-#define PCTL_MMHUB_DEEPSLEEP__DS5_MASK 0x00000020L
-#define PCTL_MMHUB_DEEPSLEEP__DS6_MASK 0x00000040L
-#define PCTL_MMHUB_DEEPSLEEP__DS7_MASK 0x00000080L
-#define PCTL_MMHUB_DEEPSLEEP__DS8_MASK 0x00000100L
-#define PCTL_MMHUB_DEEPSLEEP__DS9_MASK 0x00000200L
-#define PCTL_MMHUB_DEEPSLEEP__DS10_MASK 0x00000400L
-#define PCTL_MMHUB_DEEPSLEEP__DS11_MASK 0x00000800L
-#define PCTL_MMHUB_DEEPSLEEP__DS12_MASK 0x00001000L
-#define PCTL_MMHUB_DEEPSLEEP__DS13_MASK 0x00002000L
-#define PCTL_MMHUB_DEEPSLEEP__DS14_MASK 0x00004000L
-#define PCTL_MMHUB_DEEPSLEEP__DS15_MASK 0x00008000L
-#define PCTL_MMHUB_DEEPSLEEP__DS16_MASK 0x00010000L
-#define PCTL_MMHUB_DEEPSLEEP__SETCLEAR_MASK 0x80000000L
-//PCTL_MMHUB_DEEPSLEEP_OVERRIDE
-#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT 0x0
-#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT 0x1
-#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT 0x2
-#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT 0x3
-#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT 0x4
-#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT 0x5
-#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT 0x6
-#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT 0x7
-#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT 0x8
-#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT 0x9
-#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT 0xa
-#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT 0xb
-#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT 0xc
-#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT 0xd
-#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT 0xe
-#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT 0xf
-#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT 0x10
-#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK 0x00000001L
-#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK 0x00000002L
-#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK 0x00000004L
-#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK 0x00000008L
-#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK 0x00000010L
-#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK 0x00000020L
-#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK 0x00000040L
-#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK 0x00000080L
-#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK 0x00000100L
-#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK 0x00000200L
-#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK 0x00000400L
-#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK 0x00000800L
-#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK 0x00001000L
-#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK 0x00002000L
-#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK 0x00004000L
-#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK 0x00008000L
-#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK 0x00010000L
-//PCTL_PG_IGNORE_DEEPSLEEP
-#define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT 0x0
-#define PCTL_PG_IGNORE_DEEPSLEEP__DS0__SHIFT 0x1
-#define PCTL_PG_IGNORE_DEEPSLEEP__DS1__SHIFT 0x2
-#define PCTL_PG_IGNORE_DEEPSLEEP__DS2__SHIFT 0x3
-#define PCTL_PG_IGNORE_DEEPSLEEP__DS3__SHIFT 0x4
-#define PCTL_PG_IGNORE_DEEPSLEEP__DS4__SHIFT 0x5
-#define PCTL_PG_IGNORE_DEEPSLEEP__DS5__SHIFT 0x6
-#define PCTL_PG_IGNORE_DEEPSLEEP__DS6__SHIFT 0x7
-#define PCTL_PG_IGNORE_DEEPSLEEP__DS7__SHIFT 0x8
-#define PCTL_PG_IGNORE_DEEPSLEEP__DS8__SHIFT 0x9
-#define PCTL_PG_IGNORE_DEEPSLEEP__DS9__SHIFT 0xa
-#define PCTL_PG_IGNORE_DEEPSLEEP__DS10__SHIFT 0xb
-#define PCTL_PG_IGNORE_DEEPSLEEP__DS11__SHIFT 0xc
-#define PCTL_PG_IGNORE_DEEPSLEEP__DS12__SHIFT 0xd
-#define PCTL_PG_IGNORE_DEEPSLEEP__DS13__SHIFT 0xe
-#define PCTL_PG_IGNORE_DEEPSLEEP__DS14__SHIFT 0xf
-#define PCTL_PG_IGNORE_DEEPSLEEP__DS15__SHIFT 0x10
-#define PCTL_PG_IGNORE_DEEPSLEEP__DS16__SHIFT 0x11
-#define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK 0x00000001L
-#define PCTL_PG_IGNORE_DEEPSLEEP__DS0_MASK 0x00000002L
-#define PCTL_PG_IGNORE_DEEPSLEEP__DS1_MASK 0x00000004L
-#define PCTL_PG_IGNORE_DEEPSLEEP__DS2_MASK 0x00000008L
-#define PCTL_PG_IGNORE_DEEPSLEEP__DS3_MASK 0x00000010L
-#define PCTL_PG_IGNORE_DEEPSLEEP__DS4_MASK 0x00000020L
-#define PCTL_PG_IGNORE_DEEPSLEEP__DS5_MASK 0x00000040L
-#define PCTL_PG_IGNORE_DEEPSLEEP__DS6_MASK 0x00000080L
-#define PCTL_PG_IGNORE_DEEPSLEEP__DS7_MASK 0x00000100L
-#define PCTL_PG_IGNORE_DEEPSLEEP__DS8_MASK 0x00000200L
-#define PCTL_PG_IGNORE_DEEPSLEEP__DS9_MASK 0x00000400L
-#define PCTL_PG_IGNORE_DEEPSLEEP__DS10_MASK 0x00000800L
-#define PCTL_PG_IGNORE_DEEPSLEEP__DS11_MASK 0x00001000L
-#define PCTL_PG_IGNORE_DEEPSLEEP__DS12_MASK 0x00002000L
-#define PCTL_PG_IGNORE_DEEPSLEEP__DS13_MASK 0x00004000L
-#define PCTL_PG_IGNORE_DEEPSLEEP__DS14_MASK 0x00008000L
-#define PCTL_PG_IGNORE_DEEPSLEEP__DS15_MASK 0x00010000L
-#define PCTL_PG_IGNORE_DEEPSLEEP__DS16_MASK 0x00020000L
-//PCTL_PG_DAGB
-#define PCTL_PG_DAGB__DS0__SHIFT 0x0
-#define PCTL_PG_DAGB__DS1__SHIFT 0x1
-#define PCTL_PG_DAGB__DS2__SHIFT 0x2
-#define PCTL_PG_DAGB__DS3__SHIFT 0x3
-#define PCTL_PG_DAGB__DS4__SHIFT 0x4
-#define PCTL_PG_DAGB__DS5__SHIFT 0x5
-#define PCTL_PG_DAGB__DS6__SHIFT 0x6
-#define PCTL_PG_DAGB__DS7__SHIFT 0x7
-#define PCTL_PG_DAGB__DS8__SHIFT 0x8
-#define PCTL_PG_DAGB__DS9__SHIFT 0x9
-#define PCTL_PG_DAGB__DS10__SHIFT 0xa
-#define PCTL_PG_DAGB__DS11__SHIFT 0xb
-#define PCTL_PG_DAGB__DS12__SHIFT 0xc
-#define PCTL_PG_DAGB__DS13__SHIFT 0xd
-#define PCTL_PG_DAGB__DS14__SHIFT 0xe
-#define PCTL_PG_DAGB__DS15__SHIFT 0xf
-#define PCTL_PG_DAGB__DS16__SHIFT 0x10
-#define PCTL_PG_DAGB__DS0_MASK 0x00000001L
-#define PCTL_PG_DAGB__DS1_MASK 0x00000002L
-#define PCTL_PG_DAGB__DS2_MASK 0x00000004L
-#define PCTL_PG_DAGB__DS3_MASK 0x00000008L
-#define PCTL_PG_DAGB__DS4_MASK 0x00000010L
-#define PCTL_PG_DAGB__DS5_MASK 0x00000020L
-#define PCTL_PG_DAGB__DS6_MASK 0x00000040L
-#define PCTL_PG_DAGB__DS7_MASK 0x00000080L
-#define PCTL_PG_DAGB__DS8_MASK 0x00000100L
-#define PCTL_PG_DAGB__DS9_MASK 0x00000200L
-#define PCTL_PG_DAGB__DS10_MASK 0x00000400L
-#define PCTL_PG_DAGB__DS11_MASK 0x00000800L
-#define PCTL_PG_DAGB__DS12_MASK 0x00001000L
-#define PCTL_PG_DAGB__DS13_MASK 0x00002000L
-#define PCTL_PG_DAGB__DS14_MASK 0x00004000L
-#define PCTL_PG_DAGB__DS15_MASK 0x00008000L
-#define PCTL_PG_DAGB__DS16_MASK 0x00010000L
-//PCTL0_RENG_RAM_INDEX
-#define PCTL0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0
-#define PCTL0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000007FFL
-//PCTL0_RENG_RAM_DATA
-#define PCTL0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0
-#define PCTL0_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL
-//PCTL0_RENG_EXECUTE
-#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0
-#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1
-#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x2
-#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x3
-#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xe
-#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x19
-#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x00000001L
-#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000002L
-#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000004L
-#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00003FF8L
-#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x01FFC000L
-#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x02000000L
-//PCTL0_MISC
-#define PCTL0_MISC__CRITICAL_REGS_LOCK__SHIFT 0xb
-#define PCTL0_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xc
-#define PCTL0_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xf
-#define PCTL0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10
-#define PCTL0_MISC__CRITICAL_REGS_LOCK_MASK 0x00000800L
-#define PCTL0_MISC__TILE_IDLE_THRESHOLD_MASK 0x00007000L
-#define PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK 0x00008000L
-#define PCTL0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00010000L
-//PCTL0_STCTRL_REGISTER_SAVE_RANGE0
-#define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
-#define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
-#define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
-#define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
-//PCTL0_STCTRL_REGISTER_SAVE_RANGE1
-#define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
-#define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
-#define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
-#define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
-//PCTL0_STCTRL_REGISTER_SAVE_RANGE2
-#define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
-#define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
-#define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
-#define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
-//PCTL0_STCTRL_REGISTER_SAVE_RANGE3
-#define PCTL0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
-#define PCTL0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
-#define PCTL0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
-#define PCTL0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
-//PCTL0_STCTRL_REGISTER_SAVE_RANGE4
-#define PCTL0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
-#define PCTL0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
-#define PCTL0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
-#define PCTL0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
-//PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET
-#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0
-#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10
-#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL
-#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L
-//PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1
-#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0
-#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10
-#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL
-#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L
-//PCTL1_RENG_RAM_INDEX
-#define PCTL1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0
-#define PCTL1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL
-//PCTL1_RENG_RAM_DATA
-#define PCTL1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0
-#define PCTL1_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL
-//PCTL1_RENG_EXECUTE
-#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0
-#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1
-#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x2
-#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x3
-#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd
-#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x17
-#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x00000001L
-#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000002L
-#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000004L
-#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FF8L
-#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x007FE000L
-#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00800000L
-//PCTL1_MISC
-#define PCTL1_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa
-#define PCTL1_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb
-#define PCTL1_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe
-#define PCTL1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf
-#define PCTL1_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10
-#define PCTL1_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L
-#define PCTL1_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L
-#define PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L
-#define PCTL1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L
-#define PCTL1_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L
-//PCTL1_STCTRL_REGISTER_SAVE_RANGE0
-#define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
-#define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
-#define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
-#define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
-//PCTL1_STCTRL_REGISTER_SAVE_RANGE1
-#define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
-#define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
-#define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
-#define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
-//PCTL1_STCTRL_REGISTER_SAVE_RANGE2
-#define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
-#define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
-#define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
-#define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
-//PCTL1_STCTRL_REGISTER_SAVE_RANGE3
-#define PCTL1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
-#define PCTL1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
-#define PCTL1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
-#define PCTL1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
-//PCTL1_STCTRL_REGISTER_SAVE_RANGE4
-#define PCTL1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
-#define PCTL1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
-#define PCTL1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
-#define PCTL1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
-//PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET
-#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0
-#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10
-#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL
-#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L
-//PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1
-#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0
-#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10
-#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL
-#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L
-//PCTL2_RENG_RAM_INDEX
-#define PCTL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0
-#define PCTL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL
-//PCTL2_RENG_RAM_DATA
-#define PCTL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0
-#define PCTL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL
-//PCTL2_RENG_EXECUTE
-#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0
-#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1
-#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x2
-#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x3
-#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd
-#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x17
-#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x00000001L
-#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000002L
-#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000004L
-#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FF8L
-#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x007FE000L
-#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00800000L
-//PCTL2_MISC
-#define PCTL2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa
-#define PCTL2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb
-#define PCTL2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe
-#define PCTL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf
-#define PCTL2_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10
-#define PCTL2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L
-#define PCTL2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L
-#define PCTL2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L
-#define PCTL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L
-#define PCTL2_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L
-//PCTL2_STCTRL_REGISTER_SAVE_RANGE0
-#define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
-#define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
-#define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
-#define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
-//PCTL2_STCTRL_REGISTER_SAVE_RANGE1
-#define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
-#define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
-#define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
-#define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
-//PCTL2_STCTRL_REGISTER_SAVE_RANGE2
-#define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
-#define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
-#define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
-#define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
-//PCTL2_STCTRL_REGISTER_SAVE_RANGE3
-#define PCTL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
-#define PCTL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
-#define PCTL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
-#define PCTL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
-//PCTL2_STCTRL_REGISTER_SAVE_RANGE4
-#define PCTL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0
-#define PCTL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10
-#define PCTL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL
-#define PCTL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L
-//PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET
-#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0
-#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10
-#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL
-#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L
-//PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1
-#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0
-#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10
-#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL
-#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L
-
-
-// addressBlock: mmhub_l1tlb_vml1dec
-//MC_VM_MX_L1_TLB0_STATUS
-#define MC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT 0x0
-#define MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
-#define MC_VM_MX_L1_TLB0_STATUS__BUSY_MASK 0x00000001L
-#define MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
-//MC_VM_MX_L1_TLB1_STATUS
-#define MC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT 0x0
-#define MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
-#define MC_VM_MX_L1_TLB1_STATUS__BUSY_MASK 0x00000001L
-#define MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
-//MC_VM_MX_L1_TLB2_STATUS
-#define MC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT 0x0
-#define MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
-#define MC_VM_MX_L1_TLB2_STATUS__BUSY_MASK 0x00000001L
-#define MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
-//MC_VM_MX_L1_TLB3_STATUS
-#define MC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT 0x0
-#define MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
-#define MC_VM_MX_L1_TLB3_STATUS__BUSY_MASK 0x00000001L
-#define MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
-//MC_VM_MX_L1_TLB4_STATUS
-#define MC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT 0x0
-#define MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
-#define MC_VM_MX_L1_TLB4_STATUS__BUSY_MASK 0x00000001L
-#define MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
-//MC_VM_MX_L1_TLB5_STATUS
-#define MC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT 0x0
-#define MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
-#define MC_VM_MX_L1_TLB5_STATUS__BUSY_MASK 0x00000001L
-#define MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
-//MC_VM_MX_L1_TLB6_STATUS
-#define MC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT 0x0
-#define MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
-#define MC_VM_MX_L1_TLB6_STATUS__BUSY_MASK 0x00000001L
-#define MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
-//MC_VM_MX_L1_TLB7_STATUS
-#define MC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT 0x0
-#define MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1
-#define MC_VM_MX_L1_TLB7_STATUS__BUSY_MASK 0x00000001L
-#define MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L
-
-
-// addressBlock: mmhub_l1tlb_vml1pldec
-//MC_VM_MX_L1_PERFCOUNTER0_CFG
-#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
-#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
-#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
-#define MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
-#define MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
-#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
-#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
-#define MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
-#define MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
-//MC_VM_MX_L1_PERFCOUNTER1_CFG
-#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
-#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
-#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
-#define MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
-#define MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
-#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
-#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
-#define MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
-#define MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
-//MC_VM_MX_L1_PERFCOUNTER2_CFG
-#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
-#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
-#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
-#define MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
-#define MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
-#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
-#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
-#define MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
-#define MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
-//MC_VM_MX_L1_PERFCOUNTER3_CFG
-#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
-#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
-#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
-#define MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
-#define MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
-#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL
-#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L
-#define MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L
-#define MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L
-//MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL
-#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
-#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
-#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
-#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
-#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
-#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
-#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
-#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
-#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
-#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
-#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
-#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
-
-
-// addressBlock: mmhub_l1tlb_vml1prdec
-//MC_VM_MX_L1_PERFCOUNTER_LO
-#define MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
-#define MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
-//MC_VM_MX_L1_PERFCOUNTER_HI
-#define MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
-#define MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
-#define MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
-#define MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
-
-
-// addressBlock: mmhub_utcl2_atcl2dec
-//ATC_L2_CNTL
-#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0
-#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3
-#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6
-#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7
-#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x8
-#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
-#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L
-#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L
-#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L
-#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L
-#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00000700L
-#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L
-//ATC_L2_CNTL2
-#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0
-#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6
-#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8
-#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9
-#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc
-#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf
-#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL
-#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L
-#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000100L
-#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00000E00L
-#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00007000L
-#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x001F8000L
-//ATC_L2_CACHE_DATA0
-#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0
-#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1
-#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2
-#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x17
-#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L
-#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L
-#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x007FFFFCL
-#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x07800000L
-//ATC_L2_CACHE_DATA1
-#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0
-#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL
-//ATC_L2_CACHE_DATA2
-#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0
-#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL
-//ATC_L2_CNTL3
-#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x0
-#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x3
-#define ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT 0x9
-#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x00000007L
-#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x000001F8L
-#define ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK 0x00000E00L
-//ATC_L2_STATUS
-#define ATC_L2_STATUS__BUSY__SHIFT 0x0
-#define ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1
-#define ATC_L2_STATUS__BUSY_MASK 0x00000001L
-#define ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3FFFFFFEL
-//ATC_L2_STATUS2
-#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0
-#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8
-#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL
-#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L
-//ATC_L2_MISC_CG
-#define ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6
-#define ATC_L2_MISC_CG__ENABLE__SHIFT 0x12
-#define ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13
-#define ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L
-#define ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L
-#define ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L
-//ATC_L2_MEM_POWER_LS
-#define ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
-#define ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
-#define ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL
-#define ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L
-//ATC_L2_CGTT_CLK_CTRL
-#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
-#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10
-#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18
-#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
-#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
-#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
-
-
-// addressBlock: mmhub_utcl2_vml2pfdec
-//VM_L2_CNTL
-#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0
-#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1
-#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2
-#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4
-#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8
-#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9
-#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa
-#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
-#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc
-#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf
-#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12
-#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13
-#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15
-#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a
-#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L
-#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L
-#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL
-#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L
-#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L
-#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L
-#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L
-#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L
-#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L
-#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L
-#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L
-#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L
-#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L
-#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L
-//VM_L2_CNTL2
-#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0
-#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1
-#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15
-#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16
-#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17
-#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a
-#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c
-#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L
-#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L
-#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L
-#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L
-#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L
-#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L
-#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L
-//VM_L2_CNTL3
-#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0
-#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6
-#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8
-#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf
-#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14
-#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15
-#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18
-#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c
-#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d
-#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e
-#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f
-#define VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL
-#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L
-#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L
-#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L
-#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L
-#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L
-#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L
-#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L
-#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L
-#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L
-#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L
-//VM_L2_STATUS
-#define VM_L2_STATUS__L2_BUSY__SHIFT 0x0
-#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1
-#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11
-#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12
-#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13
-#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14
-#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15
-#define VM_L2_STATUS__L2_BUSY_MASK 0x00000001L
-#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL
-#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L
-#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L
-#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L
-#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L
-#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L
-//VM_DUMMY_PAGE_FAULT_CNTL
-#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0
-#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1
-#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2
-#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L
-#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L
-#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL
-//VM_DUMMY_PAGE_FAULT_ADDR_LO32
-#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0
-#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
-//VM_DUMMY_PAGE_FAULT_ADDR_HI32
-#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0
-#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL
-//VM_L2_PROTECTION_FAULT_CNTL
-#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
-#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1
-#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2
-#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3
-#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
-#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5
-#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6
-#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
-#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8
-#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9
-#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb
-#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd
-#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d
-#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e
-#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f
-#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L
-#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L
-#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L
-#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L
-#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L
-#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L
-#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L
-#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L
-#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L
-#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L
-#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L
-#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L
-#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L
-#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L
-#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L
-//VM_L2_PROTECTION_FAULT_CNTL2
-#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0
-#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10
-#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11
-#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12
-#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13
-#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL
-#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L
-#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L
-#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L
-#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L
-//VM_L2_PROTECTION_FAULT_MM_CNTL3
-#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0
-#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL
-//VM_L2_PROTECTION_FAULT_MM_CNTL4
-#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0
-#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL
-//VM_L2_PROTECTION_FAULT_STATUS
-#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0
-#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1
-#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4
-#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8
-#define VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9
-#define VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12
-#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13
-#define VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14
-#define VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18
-#define VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19
-#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L
-#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL
-#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L
-#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L
-#define VM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L
-#define VM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L
-#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L
-#define VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L
-#define VM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L
-#define VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L
-//VM_L2_PROTECTION_FAULT_ADDR_LO32
-#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0
-#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
-//VM_L2_PROTECTION_FAULT_ADDR_HI32
-#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0
-#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL
-//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32
-#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0
-#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
-//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32
-#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0
-#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL
-//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32
-#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32
-#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32
-#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32
-#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32
-#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0
-#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL
-//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32
-#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0
-#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL
-//VM_L2_CNTL4
-#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0
-#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6
-#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7
-#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8
-#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12
-#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c
-#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL
-#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L
-#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L
-#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L
-#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L
-#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L
-//VM_L2_MM_GROUP_RT_CLASSES
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L
-#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L
-//VM_L2_BANK_SELECT_RESERVED_CID
-#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0
-#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
-#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14
-#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18
-#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19
-#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL
-#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L
-#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L
-#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L
-#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L
-//VM_L2_BANK_SELECT_RESERVED_CID2
-#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0
-#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
-#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14
-#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18
-#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19
-#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL
-#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L
-#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L
-#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L
-#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L
-//VM_L2_CACHE_PARITY_CNTL
-#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0
-#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1
-#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2
-#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3
-#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4
-#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5
-#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6
-#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9
-#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc
-#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L
-#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L
-#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L
-#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L
-#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L
-#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L
-#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L
-#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L
-#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L
-//VM_L2_CGTT_CLK_CTRL
-#define VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
-#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10
-#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18
-#define VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
-#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
-#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
-
-
-// addressBlock: mmhub_utcl2_vml2vcdec
-//VM_CONTEXT0_CNTL
-#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT1_CNTL
-#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT2_CNTL
-#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT3_CNTL
-#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT4_CNTL
-#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT5_CNTL
-#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT6_CNTL
-#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT7_CNTL
-#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT8_CNTL
-#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT9_CNTL
-#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT10_CNTL
-#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT11_CNTL
-#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT12_CNTL
-#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT13_CNTL
-#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT14_CNTL
-#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXT15_CNTL
-#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0
-#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
-#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
-#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
-#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
-#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
-#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
-#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
-#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
-#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
-#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
-#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
-#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
-#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
-#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
-#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
-#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
-#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
-#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
-#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
-#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
-#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
-#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
-#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
-#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
-#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
-#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
-#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
-#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
-#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
-#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
-#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
-#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
-#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
-#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
-#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
-#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
-#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
-//VM_CONTEXTS_DISABLE
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L
-#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L
-//VM_INVALIDATE_ENG0_SEM
-#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG1_SEM
-#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG2_SEM
-#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG3_SEM
-#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG4_SEM
-#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG5_SEM
-#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG6_SEM
-#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG7_SEM
-#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG8_SEM
-#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG9_SEM
-#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG10_SEM
-#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG11_SEM
-#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG12_SEM
-#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG13_SEM
-#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG14_SEM
-#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG15_SEM
-#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG16_SEM
-#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG17_SEM
-#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0
-#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L
-//VM_INVALIDATE_ENG0_REQ
-#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG1_REQ
-#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG2_REQ
-#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG3_REQ
-#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG4_REQ
-#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG5_REQ
-#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG6_REQ
-#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG7_REQ
-#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG8_REQ
-#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG9_REQ
-#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG10_REQ
-#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG11_REQ
-#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG12_REQ
-#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG13_REQ
-#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG14_REQ
-#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG15_REQ
-#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG16_REQ
-#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG17_REQ
-#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
-#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10
-#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
-#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
-#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
-#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
-#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
-#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
-#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00030000L
-#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
-#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
-#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
-#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
-#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
-#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
-//VM_INVALIDATE_ENG0_ACK
-#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG1_ACK
-#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG2_ACK
-#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG3_ACK
-#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG4_ACK
-#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG5_ACK
-#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG6_ACK
-#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG7_ACK
-#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG8_ACK
-#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG9_ACK
-#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG10_ACK
-#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG11_ACK
-#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG12_ACK
-#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG13_ACK
-#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG14_ACK
-#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG15_ACK
-#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG16_ACK
-#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG17_ACK
-#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
-#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10
-#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
-#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L
-//VM_INVALIDATE_ENG0_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG0_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG1_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG1_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG2_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG2_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG3_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG3_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG4_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG4_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG5_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG5_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG6_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG6_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG7_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG7_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG8_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG8_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG9_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG9_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG10_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG10_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG11_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG11_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG12_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG12_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG13_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG13_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG14_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG14_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG15_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG15_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG16_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG16_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_INVALIDATE_ENG17_ADDR_RANGE_LO32
-#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
-#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
-#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
-#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
-//VM_INVALIDATE_ENG17_ADDR_RANGE_HI32
-#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
-#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
-//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
-#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
-#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
-#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
-#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
-//VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
-#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
-#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-//VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
-#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
-#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
-//VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
-#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
-#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
-
-
-// addressBlock: mmhub_utcl2_vml2pldec
-//MC_VM_L2_PERFCOUNTER0_CFG
-#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
-#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
-#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
-#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
-#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
-#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
-#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
-#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
-#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
-//MC_VM_L2_PERFCOUNTER1_CFG
-#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
-#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
-#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
-#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
-#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
-#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
-#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
-#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
-#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
-//MC_VM_L2_PERFCOUNTER2_CFG
-#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
-#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
-#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
-#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
-#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
-#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
-#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
-#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
-#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
-//MC_VM_L2_PERFCOUNTER3_CFG
-#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
-#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
-#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
-#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
-#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
-#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL
-#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L
-#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L
-#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L
-//MC_VM_L2_PERFCOUNTER4_CFG
-#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0
-#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8
-#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18
-#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c
-#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d
-#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL
-#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L
-#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L
-#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L
-//MC_VM_L2_PERFCOUNTER5_CFG
-#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0
-#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8
-#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18
-#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c
-#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d
-#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL
-#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L
-#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L
-#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L
-//MC_VM_L2_PERFCOUNTER6_CFG
-#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0
-#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8
-#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18
-#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c
-#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d
-#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL
-#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L
-#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L
-#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L
-//MC_VM_L2_PERFCOUNTER7_CFG
-#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0
-#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8
-#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18
-#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c
-#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d
-#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL
-#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L
-#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L
-#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L
-//MC_VM_L2_PERFCOUNTER_RSLT_CNTL
-#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
-#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
-#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
-#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
-#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
-#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
-#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
-#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
-#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
-#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
-#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
-#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
-
-
-// addressBlock: mmhub_utcl2_vml2prdec
-//MC_VM_L2_PERFCOUNTER_LO
-#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
-#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
-//MC_VM_L2_PERFCOUNTER_HI
-#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
-#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
-#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
-#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
-
-
-// addressBlock: mmhub_utcl2_vmsharedhvdec
-//MC_VM_FB_SIZE_OFFSET_VF0
-#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF1
-#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF2
-#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF3
-#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF4
-#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF5
-#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF6
-#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF7
-#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF8
-#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF9
-#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF10
-#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF11
-#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF12
-#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF13
-#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF14
-#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L
-//MC_VM_FB_SIZE_OFFSET_VF15
-#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0
-#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10
-#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL
-#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L
-//VM_IOMMU_MMIO_CNTRL_1
-#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT 0x8
-#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK 0x00000100L
-//MC_VM_MARC_BASE_LO_0
-#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc
-#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L
-//MC_VM_MARC_BASE_LO_1
-#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc
-#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L
-//MC_VM_MARC_BASE_LO_2
-#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc
-#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L
-//MC_VM_MARC_BASE_LO_3
-#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc
-#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L
-//MC_VM_MARC_BASE_HI_0
-#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0
-#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL
-//MC_VM_MARC_BASE_HI_1
-#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0
-#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL
-//MC_VM_MARC_BASE_HI_2
-#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0
-#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL
-//MC_VM_MARC_BASE_HI_3
-#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0
-#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL
-//MC_VM_MARC_RELOC_LO_0
-#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0
-#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1
-#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc
-#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L
-#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L
-#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L
-//MC_VM_MARC_RELOC_LO_1
-#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0
-#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1
-#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc
-#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L
-#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L
-#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L
-//MC_VM_MARC_RELOC_LO_2
-#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0
-#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1
-#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc
-#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L
-#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L
-#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L
-//MC_VM_MARC_RELOC_LO_3
-#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0
-#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1
-#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc
-#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L
-#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L
-#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L
-//MC_VM_MARC_RELOC_HI_0
-#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0
-#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL
-//MC_VM_MARC_RELOC_HI_1
-#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0
-#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL
-//MC_VM_MARC_RELOC_HI_2
-#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0
-#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL
-//MC_VM_MARC_RELOC_HI_3
-#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0
-#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL
-//MC_VM_MARC_LEN_LO_0
-#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc
-#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L
-//MC_VM_MARC_LEN_LO_1
-#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc
-#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L
-//MC_VM_MARC_LEN_LO_2
-#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc
-#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L
-//MC_VM_MARC_LEN_LO_3
-#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc
-#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L
-//MC_VM_MARC_LEN_HI_0
-#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0
-#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL
-//MC_VM_MARC_LEN_HI_1
-#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0
-#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL
-//MC_VM_MARC_LEN_HI_2
-#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0
-#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL
-//MC_VM_MARC_LEN_HI_3
-#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0
-#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL
-//VM_IOMMU_CONTROL_REGISTER
-#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0
-#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L
-//VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER
-#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd
-#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L
-//VM_PCIE_ATS_CNTL
-#define VM_PCIE_ATS_CNTL__STU__SHIFT 0x10
-#define VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L
-#define VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_0
-#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_1
-#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_2
-#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_3
-#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_4
-#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_5
-#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_6
-#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_7
-#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_8
-#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_9
-#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_10
-#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_11
-#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_12
-#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_13
-#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_14
-#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L
-//VM_PCIE_ATS_CNTL_VF_15
-#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f
-#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L
-//UTCL2_CGTT_CLK_CTRL
-#define UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT 0xc
-#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
-#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10
-#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18
-#define UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK 0x00007000L
-#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
-#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
-#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
-//MC_SHARED_ACTIVE_FCN_ID
-#define MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0
-#define MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f
-#define MC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
-#define MC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L
-//MC_VM_XGMI_GPUIOV_ENABLE
-#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0__SHIFT 0x0
-#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1__SHIFT 0x1
-#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2__SHIFT 0x2
-#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3__SHIFT 0x3
-#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4__SHIFT 0x4
-#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5__SHIFT 0x5
-#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6__SHIFT 0x6
-#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7__SHIFT 0x7
-#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8__SHIFT 0x8
-#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9__SHIFT 0x9
-#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10__SHIFT 0xa
-#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11__SHIFT 0xb
-#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12__SHIFT 0xc
-#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13__SHIFT 0xd
-#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14__SHIFT 0xe
-#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15__SHIFT 0xf
-#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF__SHIFT 0x1f
-#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0_MASK 0x00000001L
-#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1_MASK 0x00000002L
-#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2_MASK 0x00000004L
-#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3_MASK 0x00000008L
-#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4_MASK 0x00000010L
-#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5_MASK 0x00000020L
-#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6_MASK 0x00000040L
-#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7_MASK 0x00000080L
-#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8_MASK 0x00000100L
-#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9_MASK 0x00000200L
-#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10_MASK 0x00000400L
-#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11_MASK 0x00000800L
-#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12_MASK 0x00001000L
-#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13_MASK 0x00002000L
-#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14_MASK 0x00004000L
-#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15_MASK 0x00008000L
-#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF_MASK 0x80000000L
-
-
-// addressBlock: mmhub_utcl2_vmsharedpfdec
-//MC_VM_NB_MMIOBASE
-#define MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0
-#define MC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL
-//MC_VM_NB_MMIOLIMIT
-#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0
-#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL
-//MC_VM_NB_PCI_CTRL
-#define MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17
-#define MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L
-//MC_VM_NB_PCI_ARB
-#define MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3
-#define MC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L
-//MC_VM_NB_TOP_OF_DRAM_SLOT1
-#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17
-#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L
-//MC_VM_NB_LOWER_TOP_OF_DRAM2
-#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0
-#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17
-#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L
-#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L
-//MC_VM_NB_UPPER_TOP_OF_DRAM2
-#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0
-#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL
-//MC_VM_FB_OFFSET
-#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0
-#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL
-//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
-#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0
-#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL
-//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
-#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0
-#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL
-//MC_VM_STEERING
-#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0
-#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L
-//MC_SHARED_VIRT_RESET_REQ
-#define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0
-#define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f
-#define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL
-#define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L
-//MC_MEM_POWER_LS
-#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
-#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
-#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL
-#define MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L
-//MC_VM_CACHEABLE_DRAM_ADDRESS_START
-#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0
-#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL
-//MC_VM_CACHEABLE_DRAM_ADDRESS_END
-#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0
-#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL
-//MC_VM_APT_CNTL
-#define MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0
-#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1
-#define MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L
-#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L
-//MC_VM_LOCAL_HBM_ADDRESS_START
-#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0
-#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL
-//MC_VM_LOCAL_HBM_ADDRESS_END
-#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0
-#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL
-//MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL
-#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0
-#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L
-//MC_VM_XGMI_LFB_CNTL
-#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT 0x0
-#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT 0x3
-#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK 0x00000007L
-#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK 0x00000038L
-//MC_VM_XGMI_LFB_SIZE
-#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT 0x0
-#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK 0x0000FFFFL
-
-
-// addressBlock: mmhub_utcl2_vmsharedvcdec
-//MC_VM_FB_LOCATION_BASE
-#define MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0
-#define MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL
-//MC_VM_FB_LOCATION_TOP
-#define MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0
-#define MC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL
-//MC_VM_AGP_TOP
-#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0
-#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL
-//MC_VM_AGP_BOT
-#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0
-#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL
-//MC_VM_AGP_BASE
-#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0
-#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL
-//MC_VM_SYSTEM_APERTURE_LOW_ADDR
-#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0
-#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL
-//MC_VM_SYSTEM_APERTURE_HIGH_ADDR
-#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0
-#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL
-//MC_VM_MX_L1_TLB_CNTL
-#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0
-#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3
-#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5
-#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6
-#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7
-#define MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb
-#define MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT 0xd
-#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L
-#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L
-#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L
-#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L
-#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L
-#define MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L
-#define MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK 0x00002000L
-
-
-// addressBlock: mmhub_utcl2_atcl2pfcntrdec
-//ATC_L2_PERFCOUNTER_LO
-#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
-#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
-//ATC_L2_PERFCOUNTER_HI
-#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
-#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
-#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
-#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
-
-
-// addressBlock: mmhub_utcl2_atcl2pfcntldec
-//ATC_L2_PERFCOUNTER0_CFG
-#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
-#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
-#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
-#define ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
-#define ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
-#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
-#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
-#define ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
-#define ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
-//ATC_L2_PERFCOUNTER1_CFG
-#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
-#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
-#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
-#define ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
-#define ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
-#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
-#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
-#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
-#define ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
-#define ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
-//ATC_L2_PERFCOUNTER_RSLT_CNTL
-#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
-#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
-#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
-#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
-#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
-#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
-#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
-#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
-#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
-#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
-#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
-#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_8_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_8_sh_mask.h
deleted file mode 100644
index b7d3d0df3..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_8_sh_mask.h
+++ /dev/null
@@ -1,355 +0,0 @@
-/*
- * Copyright (C) 2021 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _mp_11_0_8_SH_MASK_HEADER
-#define _mp_11_0_8_SH_MASK_HEADER
-
-#define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
-#define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0
-#define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
-#define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10
-#define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
-#define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
-#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L
-#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8
-#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L
-#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0
-#define MP0_SMN_IH_SW_INT__ID_MASK 0x000000FFL
-#define MP0_SMN_IH_SW_INT__ID__SHIFT 0x0
-#define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000100L
-#define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x8
-#define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
-#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL
-#define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL
-#define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL
-#define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL
-#define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL
-#define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL
-#define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL
-#define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL
-#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0
-#define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL
-#define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0
-#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
-#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10
-#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
-#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
-#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L
-#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8
-#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L
-#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0
-#define MP1_SMN_IH_SW_INT__ID_MASK 0x000000FFL
-#define MP1_SMN_IH_SW_INT__ID__SHIFT 0x0
-#define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000100L
-#define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x8
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_5_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_5_sh_mask.h
deleted file mode 100644
index 4b9383128..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_5_sh_mask.h
+++ /dev/null
@@ -1,672 +0,0 @@
-/*
- * Copyright 2022 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- *
- */
-#ifndef _mp_13_0_5_SH_MASK_HEADER
-#define _mp_13_0_5_SH_MASK_HEADER
-
-
-// addressBlock: mp_SmuMp0_SmnDec
-//MP0_SMN_C2PMSG_32
-#define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_33
-#define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_34
-#define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_35
-#define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_36
-#define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_37
-#define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_38
-#define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_39
-#define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_40
-#define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_41
-#define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_42
-#define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_43
-#define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_44
-#define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_45
-#define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_46
-#define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_47
-#define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_48
-#define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_49
-#define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_50
-#define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_51
-#define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_52
-#define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_53
-#define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_54
-#define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_55
-#define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_56
-#define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_57
-#define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_58
-#define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_59
-#define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_60
-#define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_61
-#define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_62
-#define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_63
-#define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_64
-#define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_65
-#define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_66
-#define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_67
-#define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_68
-#define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_69
-#define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_70
-#define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_71
-#define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_72
-#define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_73
-#define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_74
-#define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_75
-#define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_76
-#define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_77
-#define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_78
-#define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_79
-#define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_80
-#define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_81
-#define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_82
-#define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_83
-#define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_84
-#define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_85
-#define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_86
-#define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_87
-#define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_88
-#define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_89
-#define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_90
-#define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_91
-#define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_92
-#define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_93
-#define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_94
-#define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_95
-#define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_96
-#define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_97
-#define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_98
-#define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_99
-#define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_100
-#define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_101
-#define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_102
-#define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_C2PMSG_103
-#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0
-#define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
-//MP0_SMN_IH_CREDIT
-#define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
-#define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10
-#define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
-#define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
-//MP0_SMN_IH_SW_INT
-#define MP0_SMN_IH_SW_INT__ID__SHIFT 0x0
-#define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x8
-#define MP0_SMN_IH_SW_INT__ID_MASK 0x000000FFL
-#define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000100L
-//MP0_SMN_IH_SW_INT_CTRL
-#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0
-#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8
-#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L
-#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L
-
-
-// addressBlock: mp_SmuMp1_SmnDec
-//MP1_SMN_C2PMSG_32
-#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_33
-#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_34
-#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_35
-#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_36
-#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_37
-#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_38
-#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_39
-#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_40
-#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_41
-#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_42
-#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_43
-#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_44
-#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_45
-#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_46
-#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_47
-#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_48
-#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_49
-#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_50
-#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_51
-#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_52
-#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_53
-#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_54
-#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_55
-#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_56
-#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_57
-#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_58
-#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_59
-#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_60
-#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_61
-#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_62
-#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_63
-#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_64
-#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_65
-#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_66
-#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_67
-#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_68
-#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_69
-#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_70
-#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_71
-#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_72
-#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_73
-#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_74
-#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_75
-#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_76
-#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_77
-#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_78
-#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_79
-#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_80
-#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_81
-#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_82
-#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_83
-#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_84
-#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_85
-#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_86
-#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_87
-#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_88
-#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_89
-#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_90
-#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_91
-#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_92
-#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_93
-#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_94
-#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_95
-#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_96
-#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_97
-#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_98
-#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_99
-#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_100
-#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_101
-#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_102
-#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_103
-#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_104
-#define MP1_SMN_C2PMSG_104__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_104__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_105
-#define MP1_SMN_C2PMSG_105__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_105__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_106
-#define MP1_SMN_C2PMSG_106__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_106__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_107
-#define MP1_SMN_C2PMSG_107__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_107__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_108
-#define MP1_SMN_C2PMSG_108__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_108__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_109
-#define MP1_SMN_C2PMSG_109__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_109__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_110
-#define MP1_SMN_C2PMSG_110__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_110__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_111
-#define MP1_SMN_C2PMSG_111__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_111__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_112
-#define MP1_SMN_C2PMSG_112__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_112__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_113
-#define MP1_SMN_C2PMSG_113__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_113__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_114
-#define MP1_SMN_C2PMSG_114__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_114__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_115
-#define MP1_SMN_C2PMSG_115__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_115__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_116
-#define MP1_SMN_C2PMSG_116__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_116__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_117
-#define MP1_SMN_C2PMSG_117__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_117__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_118
-#define MP1_SMN_C2PMSG_118__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_118__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_119
-#define MP1_SMN_C2PMSG_119__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_119__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_120
-#define MP1_SMN_C2PMSG_120__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_120__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_121
-#define MP1_SMN_C2PMSG_121__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_121__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_122
-#define MP1_SMN_C2PMSG_122__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_122__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_123
-#define MP1_SMN_C2PMSG_123__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_123__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_124
-#define MP1_SMN_C2PMSG_124__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_124__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_125
-#define MP1_SMN_C2PMSG_125__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_125__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_126
-#define MP1_SMN_C2PMSG_126__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_126__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_C2PMSG_127
-#define MP1_SMN_C2PMSG_127__CONTENT__SHIFT 0x0
-#define MP1_SMN_C2PMSG_127__CONTENT_MASK 0xFFFFFFFFL
-//MP1_SMN_IH_CREDIT
-#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
-#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10
-#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
-#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
-//MP1_SMN_IH_SW_INT
-#define MP1_SMN_IH_SW_INT__ID__SHIFT 0x0
-#define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x8
-#define MP1_SMN_IH_SW_INT__ID_MASK 0x000000FFL
-#define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000100L
-//MP1_SMN_IH_SW_INT_CTRL
-#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0
-#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8
-#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L
-#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L
-//MP1_SMN_FPS_CNT
-#define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0
-#define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH0
-#define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH1
-#define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH2
-#define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH3
-#define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH4
-#define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH5
-#define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH6
-#define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH7
-#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH8
-#define MP1_SMN_EXT_SCRATCH8__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH8__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH10
-#define MP1_SMN_EXT_SCRATCH10__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH10__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH11
-#define MP1_SMN_EXT_SCRATCH11__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH11__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH12
-#define MP1_SMN_EXT_SCRATCH12__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH12__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH13
-#define MP1_SMN_EXT_SCRATCH13__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH13__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH14
-#define MP1_SMN_EXT_SCRATCH14__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH14__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH15
-#define MP1_SMN_EXT_SCRATCH15__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH15__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH16
-#define MP1_SMN_EXT_SCRATCH16__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH16__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH17
-#define MP1_SMN_EXT_SCRATCH17__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH17__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH18
-#define MP1_SMN_EXT_SCRATCH18__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH18__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH19
-#define MP1_SMN_EXT_SCRATCH19__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH19__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH20
-#define MP1_SMN_EXT_SCRATCH20__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH20__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH21
-#define MP1_SMN_EXT_SCRATCH21__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH21__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH22
-#define MP1_SMN_EXT_SCRATCH22__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH22__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH23
-#define MP1_SMN_EXT_SCRATCH23__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH23__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH24
-#define MP1_SMN_EXT_SCRATCH24__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH24__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH25
-#define MP1_SMN_EXT_SCRATCH25__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH25__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH26
-#define MP1_SMN_EXT_SCRATCH26__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH26__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH27
-#define MP1_SMN_EXT_SCRATCH27__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH27__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH28
-#define MP1_SMN_EXT_SCRATCH28__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH28__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH29
-#define MP1_SMN_EXT_SCRATCH29__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH29__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH30
-#define MP1_SMN_EXT_SCRATCH30__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH30__DATA_MASK 0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH31
-#define MP1_SMN_EXT_SCRATCH31__DATA__SHIFT 0x0
-#define MP1_SMN_EXT_SCRATCH31__DATA_MASK 0xFFFFFFFFL
-
-
-// addressBlock: mp_SmuMp1Pub_CruDec
-//MP1_FIRMWARE_FLAGS
-#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0
-#define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1
-#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L
-#define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL
-
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_sh_mask.h
deleted file mode 100644
index c7518b84f..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_sh_mask.h
+++ /dev/null
@@ -1,10281 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _nbif_6_1_SH_MASK_HEADER
-#define _nbif_6_1_SH_MASK_HEADER
-
-
-// addressBlock: bif_cfg_dev0_epf0_bifcfgdecp
-//VENDOR_ID
-#define VENDOR_ID__VENDOR_ID__SHIFT 0x0
-//DEVICE_ID
-#define DEVICE_ID__DEVICE_ID__SHIFT 0x0
-//COMMAND
-#define COMMAND__IO_ACCESS_EN__SHIFT 0x0
-#define COMMAND__MEM_ACCESS_EN__SHIFT 0x1
-#define COMMAND__BUS_MASTER_EN__SHIFT 0x2
-#define COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
-#define COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
-#define COMMAND__PAL_SNOOP_EN__SHIFT 0x5
-#define COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
-#define COMMAND__AD_STEPPING__SHIFT 0x7
-#define COMMAND__SERR_EN__SHIFT 0x8
-#define COMMAND__FAST_B2B_EN__SHIFT 0x9
-#define COMMAND__INT_DIS__SHIFT 0xa
-//STATUS
-#define STATUS__INT_STATUS__SHIFT 0x3
-#define STATUS__CAP_LIST__SHIFT 0x4
-#define STATUS__PCI_66_EN__SHIFT 0x5
-#define STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
-#define STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
-#define STATUS__DEVSEL_TIMING__SHIFT 0x9
-#define STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
-#define STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
-#define STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
-#define STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
-#define STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
-//REVISION_ID
-#define REVISION_ID__MINOR_REV_ID__SHIFT 0x0
-#define REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
-//PROG_INTERFACE
-#define PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
-//SUB_CLASS
-#define SUB_CLASS__SUB_CLASS__SHIFT 0x0
-//BASE_CLASS
-#define BASE_CLASS__BASE_CLASS__SHIFT 0x0
-//CACHE_LINE
-#define CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
-//LATENCY
-#define LATENCY__LATENCY_TIMER__SHIFT 0x0
-//HEADER
-#define HEADER__HEADER_TYPE__SHIFT 0x0
-#define HEADER__DEVICE_TYPE__SHIFT 0x7
-//BIST
-#define BIST__BIST_COMP__SHIFT 0x0
-#define BIST__BIST_STRT__SHIFT 0x6
-#define BIST__BIST_CAP__SHIFT 0x7
-//BASE_ADDR_1
-#define BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
-//BASE_ADDR_2
-#define BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
-//BASE_ADDR_3
-#define BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
-//BASE_ADDR_4
-#define BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
-//BASE_ADDR_5
-#define BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
-//BASE_ADDR_6
-#define BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
-//ADAPTER_ID
-#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
-#define ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
-//ROM_BASE_ADDR
-#define ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
-//CAP_PTR
-#define CAP_PTR__CAP_PTR__SHIFT 0x0
-//INTERRUPT_LINE
-#define INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
-//INTERRUPT_PIN
-#define INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
-//MIN_GRANT
-#define MIN_GRANT__MIN_GNT__SHIFT 0x0
-//MAX_LATENCY
-#define MAX_LATENCY__MAX_LAT__SHIFT 0x0
-//VENDOR_CAP_LIST
-#define VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
-#define VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
-#define VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
-//ADAPTER_ID_W
-#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
-#define ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
-//PMI_CAP_LIST
-#define PMI_CAP_LIST__CAP_ID__SHIFT 0x0
-#define PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
-//PMI_CAP
-#define PMI_CAP__VERSION__SHIFT 0x0
-#define PMI_CAP__PME_CLOCK__SHIFT 0x3
-#define PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
-#define PMI_CAP__AUX_CURRENT__SHIFT 0x6
-#define PMI_CAP__D1_SUPPORT__SHIFT 0x9
-#define PMI_CAP__D2_SUPPORT__SHIFT 0xa
-#define PMI_CAP__PME_SUPPORT__SHIFT 0xb
-//PMI_STATUS_CNTL
-#define PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
-#define PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
-#define PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
-#define PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
-#define PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
-#define PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
-#define PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
-#define PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
-#define PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
-//PCIE_CAP_LIST
-#define PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
-#define PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
-//PCIE_CAP
-#define PCIE_CAP__VERSION__SHIFT 0x0
-#define PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
-#define PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
-#define PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
-//DEVICE_CAP
-#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
-#define DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
-#define DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
-#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
-#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
-#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
-#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
-#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
-#define DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
-//DEVICE_CNTL
-#define DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
-#define DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
-#define DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
-#define DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
-#define DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
-#define DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
-#define DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
-#define DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
-#define DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
-#define DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
-#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
-#define DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
-//DEVICE_STATUS
-#define DEVICE_STATUS__CORR_ERR__SHIFT 0x0
-#define DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
-#define DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
-#define DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
-#define DEVICE_STATUS__AUX_PWR__SHIFT 0x4
-#define DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
-//LINK_CAP
-#define LINK_CAP__LINK_SPEED__SHIFT 0x0
-#define LINK_CAP__LINK_WIDTH__SHIFT 0x4
-#define LINK_CAP__PM_SUPPORT__SHIFT 0xa
-#define LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
-#define LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
-#define LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
-#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
-#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
-#define LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
-#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
-#define LINK_CAP__PORT_NUMBER__SHIFT 0x18
-//LINK_CNTL
-#define LINK_CNTL__PM_CONTROL__SHIFT 0x0
-#define LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
-#define LINK_CNTL__LINK_DIS__SHIFT 0x4
-#define LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
-#define LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
-#define LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
-#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
-#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
-#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
-#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
-//LINK_STATUS
-#define LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
-#define LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
-#define LINK_STATUS__LINK_TRAINING__SHIFT 0xb
-#define LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
-#define LINK_STATUS__DL_ACTIVE__SHIFT 0xd
-#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
-#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
-//DEVICE_CAP2
-#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
-#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
-#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
-#define DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
-#define DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
-#define DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
-#define DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
-#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
-#define DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
-#define DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
-#define DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
-#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
-#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
-#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
-//DEVICE_CNTL2
-#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
-#define DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
-#define DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
-#define DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
-#define DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
-#define DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
-#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
-#define DEVICE_CNTL2__LTR_EN__SHIFT 0xa
-#define DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
-#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
-//DEVICE_STATUS2
-#define DEVICE_STATUS2__RESERVED__SHIFT 0x0
-//LINK_CAP2
-#define LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
-#define LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
-#define LINK_CAP2__RESERVED__SHIFT 0x9
-//LINK_CNTL2
-#define LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
-#define LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
-#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
-#define LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
-#define LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
-#define LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
-#define LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
-#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
-//LINK_STATUS2
-#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
-#define LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
-#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
-#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
-#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
-#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
-//SLOT_CAP2
-#define SLOT_CAP2__RESERVED__SHIFT 0x0
-//SLOT_CNTL2
-#define SLOT_CNTL2__RESERVED__SHIFT 0x0
-//SLOT_STATUS2
-#define SLOT_STATUS2__RESERVED__SHIFT 0x0
-//MSI_CAP_LIST
-#define MSI_CAP_LIST__CAP_ID__SHIFT 0x0
-#define MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
-//MSI_MSG_CNTL
-#define MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
-#define MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
-#define MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
-#define MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
-#define MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
-//MSI_MSG_ADDR_LO
-#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
-//MSI_MSG_ADDR_HI
-#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
-//MSI_MSG_DATA
-#define MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
-//MSI_MSG_DATA_64
-#define MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
-//MSI_MASK
-#define MSI_MASK__MSI_MASK__SHIFT 0x0
-//MSI_PENDING
-#define MSI_PENDING__MSI_PENDING__SHIFT 0x0
-//MSI_MASK_64
-#define MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
-//MSI_PENDING_64
-#define MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
-//MSIX_CAP_LIST
-#define MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
-#define MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
-//MSIX_MSG_CNTL
-#define MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
-#define MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
-#define MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
-//MSIX_TABLE
-#define MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
-#define MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
-//MSIX_PBA
-#define MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
-#define MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
-//PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
-#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
-#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
-#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
-//PCIE_VENDOR_SPECIFIC_HDR
-#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
-#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
-#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
-//PCIE_VENDOR_SPECIFIC1
-#define PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
-//PCIE_VENDOR_SPECIFIC2
-#define PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
-//PCIE_VC_ENH_CAP_LIST
-#define PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
-#define PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
-#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
-//PCIE_PORT_VC_CAP_REG1
-#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
-#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
-#define PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
-#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
-//PCIE_PORT_VC_CAP_REG2
-#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
-#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
-//PCIE_PORT_VC_CNTL
-#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
-#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
-//PCIE_PORT_VC_STATUS
-#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
-//PCIE_VC0_RESOURCE_CAP
-#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
-#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
-#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
-#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
-//PCIE_VC0_RESOURCE_CNTL
-#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
-#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
-#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
-#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
-#define PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
-#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
-//PCIE_VC0_RESOURCE_STATUS
-#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
-#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
-//PCIE_VC1_RESOURCE_CAP
-#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
-#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
-#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
-#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
-//PCIE_VC1_RESOURCE_CNTL
-#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
-#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
-#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
-#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
-#define PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
-#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
-//PCIE_VC1_RESOURCE_STATUS
-#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
-#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
-//PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
-#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
-#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
-#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
-//PCIE_DEV_SERIAL_NUM_DW1
-#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
-//PCIE_DEV_SERIAL_NUM_DW2
-#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
-//PCIE_ADV_ERR_RPT_ENH_CAP_LIST
-#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
-#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
-#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
-//PCIE_UNCORR_ERR_STATUS
-#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
-#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
-#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
-#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
-#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
-#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
-#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
-#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
-#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
-#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
-#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
-#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
-#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
-#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
-#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
-#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
-//PCIE_UNCORR_ERR_MASK
-#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
-#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
-#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
-#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
-#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
-#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
-#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
-#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
-#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
-#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
-#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
-#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
-#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
-#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
-#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
-#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
-//PCIE_UNCORR_ERR_SEVERITY
-#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
-#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
-#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
-#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
-#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
-#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
-#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
-#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
-#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
-#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
-#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
-#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
-#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
-#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
-#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
-#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
-//PCIE_CORR_ERR_STATUS
-#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
-#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
-#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
-#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
-#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
-#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
-#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
-#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
-//PCIE_CORR_ERR_MASK
-#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
-#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
-#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
-#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
-#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
-#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
-#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
-#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
-//PCIE_ADV_ERR_CAP_CNTL
-#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
-#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
-#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
-#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
-#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
-#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
-#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
-#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
-//PCIE_HDR_LOG0
-#define PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
-//PCIE_HDR_LOG1
-#define PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
-//PCIE_HDR_LOG2
-#define PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
-//PCIE_HDR_LOG3
-#define PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
-//PCIE_ROOT_ERR_CMD
-#define PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
-#define PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
-#define PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
-//PCIE_ROOT_ERR_STATUS
-#define PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
-#define PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
-#define PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
-#define PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
-#define PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
-#define PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
-#define PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
-#define PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
-//PCIE_ERR_SRC_ID
-#define PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
-#define PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
-//PCIE_TLP_PREFIX_LOG0
-#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
-//PCIE_TLP_PREFIX_LOG1
-#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
-//PCIE_TLP_PREFIX_LOG2
-#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
-//PCIE_TLP_PREFIX_LOG3
-#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
-//PCIE_BAR_ENH_CAP_LIST
-#define PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
-#define PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
-#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
-//PCIE_BAR1_CAP
-#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
-//PCIE_BAR1_CNTL
-#define PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
-#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
-#define PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
-//PCIE_BAR2_CAP
-#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
-//PCIE_BAR2_CNTL
-#define PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
-#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
-#define PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
-//PCIE_BAR3_CAP
-#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
-//PCIE_BAR3_CNTL
-#define PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
-#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
-#define PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
-//PCIE_BAR4_CAP
-#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
-//PCIE_BAR4_CNTL
-#define PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
-#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
-#define PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
-//PCIE_BAR5_CAP
-#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
-//PCIE_BAR5_CNTL
-#define PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
-#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
-#define PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
-//PCIE_BAR6_CAP
-#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
-//PCIE_BAR6_CNTL
-#define PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
-#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
-#define PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
-//PCIE_PWR_BUDGET_ENH_CAP_LIST
-#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
-#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
-#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
-//PCIE_PWR_BUDGET_DATA_SELECT
-#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
-//PCIE_PWR_BUDGET_DATA
-#define PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
-#define PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
-#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
-#define PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
-#define PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
-#define PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
-//PCIE_PWR_BUDGET_CAP
-#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
-//PCIE_DPA_ENH_CAP_LIST
-#define PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
-#define PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
-#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
-//PCIE_DPA_CAP
-#define PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
-#define PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
-#define PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
-#define PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
-#define PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
-//PCIE_DPA_LATENCY_INDICATOR
-#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
-//PCIE_DPA_STATUS
-#define PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
-#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
-//PCIE_DPA_CNTL
-#define PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
-//PCIE_DPA_SUBSTATE_PWR_ALLOC_0
-#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
-//PCIE_DPA_SUBSTATE_PWR_ALLOC_1
-#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
-//PCIE_DPA_SUBSTATE_PWR_ALLOC_2
-#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
-//PCIE_DPA_SUBSTATE_PWR_ALLOC_3
-#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
-//PCIE_DPA_SUBSTATE_PWR_ALLOC_4
-#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
-//PCIE_DPA_SUBSTATE_PWR_ALLOC_5
-#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
-//PCIE_DPA_SUBSTATE_PWR_ALLOC_6
-#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
-//PCIE_DPA_SUBSTATE_PWR_ALLOC_7
-#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
-//PCIE_SECONDARY_ENH_CAP_LIST
-#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
-#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
-#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
-//PCIE_LINK_CNTL3
-#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
-#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
-#define PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
-//PCIE_LANE_ERROR_STATUS
-#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
-#define PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
-//PCIE_LANE_0_EQUALIZATION_CNTL
-#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
-#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
-#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
-#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
-#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
-//PCIE_LANE_1_EQUALIZATION_CNTL
-#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
-#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
-#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
-#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
-#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
-//PCIE_LANE_2_EQUALIZATION_CNTL
-#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
-#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
-#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
-#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
-#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
-//PCIE_LANE_3_EQUALIZATION_CNTL
-#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
-#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
-#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
-#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
-#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
-//PCIE_LANE_4_EQUALIZATION_CNTL
-#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
-#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
-#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
-#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
-#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
-//PCIE_LANE_5_EQUALIZATION_CNTL
-#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
-#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
-#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
-#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
-#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
-//PCIE_LANE_6_EQUALIZATION_CNTL
-#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
-#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
-#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
-#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
-#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
-//PCIE_LANE_7_EQUALIZATION_CNTL
-#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
-#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
-#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
-#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
-#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
-//PCIE_LANE_8_EQUALIZATION_CNTL
-#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
-#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
-#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
-#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
-#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
-//PCIE_LANE_9_EQUALIZATION_CNTL
-#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
-#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
-#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
-#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
-#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
-//PCIE_LANE_10_EQUALIZATION_CNTL
-#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
-#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
-#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
-#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
-#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
-//PCIE_LANE_11_EQUALIZATION_CNTL
-#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
-#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
-#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
-#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
-#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
-//PCIE_LANE_12_EQUALIZATION_CNTL
-#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
-#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
-#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
-#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
-#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
-//PCIE_LANE_13_EQUALIZATION_CNTL
-#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
-#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
-#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
-#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
-#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
-//PCIE_LANE_14_EQUALIZATION_CNTL
-#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
-#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
-#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
-#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
-#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
-//PCIE_LANE_15_EQUALIZATION_CNTL
-#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
-#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
-#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
-#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
-#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
-//PCIE_ACS_ENH_CAP_LIST
-#define PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
-#define PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
-#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
-//PCIE_ACS_CAP
-#define PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
-#define PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
-#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
-#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
-#define PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
-#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
-#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
-#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
-//PCIE_ACS_CNTL
-#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
-#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
-#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
-#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
-#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
-#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
-#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
-//PCIE_ATS_ENH_CAP_LIST
-#define PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
-#define PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
-#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
-//PCIE_ATS_CAP
-#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
-#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
-#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
-//PCIE_ATS_CNTL
-#define PCIE_ATS_CNTL__STU__SHIFT 0x0
-#define PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
-//PCIE_PAGE_REQ_ENH_CAP_LIST
-#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
-#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
-#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
-//PCIE_PAGE_REQ_CNTL
-#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
-#define PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
-//PCIE_PAGE_REQ_STATUS
-#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0
-#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1
-#define PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8
-#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf
-//PCIE_OUTSTAND_PAGE_REQ_CAPACITY
-#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0
-//PCIE_OUTSTAND_PAGE_REQ_ALLOC
-#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
-//PCIE_PASID_ENH_CAP_LIST
-#define PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
-#define PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
-#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
-//PCIE_PASID_CAP
-#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
-#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
-#define PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
-//PCIE_PASID_CNTL
-#define PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
-#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
-#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
-//PCIE_TPH_REQR_ENH_CAP_LIST
-#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
-#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
-#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
-//PCIE_TPH_REQR_CAP
-#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
-#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
-#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
-#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
-#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
-#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
-//PCIE_TPH_REQR_CNTL
-#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
-#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
-//PCIE_MC_ENH_CAP_LIST
-#define PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
-#define PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
-#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
-//PCIE_MC_CAP
-#define PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
-#define PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
-#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
-//PCIE_MC_CNTL
-#define PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
-#define PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
-//PCIE_MC_ADDR0
-#define PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
-#define PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
-//PCIE_MC_ADDR1
-#define PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
-//PCIE_MC_RCV0
-#define PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
-//PCIE_MC_RCV1
-#define PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
-//PCIE_MC_BLOCK_ALL0
-#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
-//PCIE_MC_BLOCK_ALL1
-#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
-//PCIE_MC_BLOCK_UNTRANSLATED_0
-#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
-//PCIE_MC_BLOCK_UNTRANSLATED_1
-#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
-//PCIE_LTR_ENH_CAP_LIST
-#define PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
-#define PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
-#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
-//PCIE_LTR_CAP
-#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
-#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
-#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
-#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
-//PCIE_ARI_ENH_CAP_LIST
-#define PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
-#define PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
-#define PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
-//PCIE_ARI_CAP
-#define PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
-#define PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
-#define PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
-//PCIE_ARI_CNTL
-#define PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
-#define PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
-#define PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
-//PCIE_SRIOV_ENH_CAP_LIST
-#define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
-#define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
-#define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
-//PCIE_SRIOV_CAP
-#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0
-#define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1
-#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15
-//PCIE_SRIOV_CONTROL
-#define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0
-#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1
-#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2
-#define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3
-#define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4
-//PCIE_SRIOV_STATUS
-#define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0
-//PCIE_SRIOV_INITIAL_VFS
-#define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0
-//PCIE_SRIOV_TOTAL_VFS
-#define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0
-//PCIE_SRIOV_NUM_VFS
-#define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0
-//PCIE_SRIOV_FUNC_DEP_LINK
-#define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0
-//PCIE_SRIOV_FIRST_VF_OFFSET
-#define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0
-//PCIE_SRIOV_VF_STRIDE
-#define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0
-//PCIE_SRIOV_VF_DEVICE_ID
-#define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0
-//PCIE_SRIOV_SUPPORTED_PAGE_SIZE
-#define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0
-//PCIE_SRIOV_SYSTEM_PAGE_SIZE
-#define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0
-//PCIE_SRIOV_VF_BASE_ADDR_0
-#define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0
-//PCIE_SRIOV_VF_BASE_ADDR_1
-#define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0
-//PCIE_SRIOV_VF_BASE_ADDR_2
-#define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0
-//PCIE_SRIOV_VF_BASE_ADDR_3
-#define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0
-//PCIE_SRIOV_VF_BASE_ADDR_4
-#define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0
-//PCIE_SRIOV_VF_BASE_ADDR_5
-#define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0
-//PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
-#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT 0x0
-#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3
-//PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
-#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0
-#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10
-#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x0
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0
-
-
-// addressBlock: bif_cfg_dev0_swds_bifcfgdecp
-//SUB_BUS_NUMBER_LATENCY
-#define SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
-#define SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
-#define SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
-#define SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
-//IO_BASE_LIMIT
-#define IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
-#define IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
-#define IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
-#define IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
-//SECONDARY_STATUS
-#define SECONDARY_STATUS__CAP_LIST__SHIFT 0x4
-#define SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5
-#define SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
-#define SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
-#define SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
-#define SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
-#define SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
-#define SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
-#define SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
-#define SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
-//MEM_BASE_LIMIT
-#define MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
-#define MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
-#define MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
-#define MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
-//PREF_BASE_LIMIT
-#define PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
-#define PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
-#define PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
-#define PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
-//PREF_BASE_UPPER
-#define PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
-//PREF_LIMIT_UPPER
-#define PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
-//IO_BASE_LIMIT_HI
-#define IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
-#define IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
-//IRQ_BRIDGE_CNTL
-#define IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
-#define IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
-#define IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
-#define IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
-#define IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
-#define IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
-#define IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
-#define IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
-//SLOT_CAP
-#define SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
-#define SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
-#define SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
-#define SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
-#define SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
-#define SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
-#define SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
-#define SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
-#define SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
-#define SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
-#define SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
-#define SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
-//SLOT_CNTL
-#define SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
-#define SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
-#define SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
-#define SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
-#define SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
-#define SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
-#define SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
-#define SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
-#define SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
-#define SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
-#define SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
-//SLOT_STATUS
-#define SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
-#define SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
-#define SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
-#define SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
-#define SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
-#define SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
-#define SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
-#define SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
-#define SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
-//SSID_CAP_LIST
-#define SSID_CAP_LIST__CAP_ID__SHIFT 0x0
-#define SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
-//SSID_CAP
-#define SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
-#define SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
-
-
-// addressBlock: rcc_shadow_reg_shadowdec
-//SHADOW_COMMAND
-#define SHADOW_COMMAND__IOEN_UP__SHIFT 0x0
-#define SHADOW_COMMAND__MEMEN_UP__SHIFT 0x1
-//SHADOW_BASE_ADDR_1
-#define SHADOW_BASE_ADDR_1__BAR1_UP__SHIFT 0x0
-//SHADOW_BASE_ADDR_2
-#define SHADOW_BASE_ADDR_2__BAR2_UP__SHIFT 0x0
-//SHADOW_SUB_BUS_NUMBER_LATENCY
-#define SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP__SHIFT 0x8
-#define SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP__SHIFT 0x10
-//SHADOW_IO_BASE_LIMIT
-#define SHADOW_IO_BASE_LIMIT__IO_BASE_UP__SHIFT 0x4
-#define SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP__SHIFT 0xc
-//SHADOW_MEM_BASE_LIMIT
-#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
-#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP__SHIFT 0x4
-#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
-#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP__SHIFT 0x14
-//SHADOW_PREF_BASE_LIMIT
-#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
-#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP__SHIFT 0x4
-#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
-#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP__SHIFT 0x14
-//SHADOW_PREF_BASE_UPPER
-#define SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP__SHIFT 0x0
-//SHADOW_PREF_LIMIT_UPPER
-#define SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP__SHIFT 0x0
-//SHADOW_IO_BASE_LIMIT_HI
-#define SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP__SHIFT 0x0
-#define SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP__SHIFT 0x10
-//SHADOW_IRQ_BRIDGE_CNTL
-#define SHADOW_IRQ_BRIDGE_CNTL__ISA_EN_UP__SHIFT 0x2
-#define SHADOW_IRQ_BRIDGE_CNTL__VGA_EN_UP__SHIFT 0x3
-#define SHADOW_IRQ_BRIDGE_CNTL__VGA_DEC_UP__SHIFT 0x4
-#define SHADOW_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_UP__SHIFT 0x6
-//SUC_INDEX
-#define SUC_INDEX__SUC_INDEX__SHIFT 0x0
-//SUC_DATA
-#define SUC_DATA__SUC_DATA__SHIFT 0x0
-
-
-// addressBlock: bif_bx_pf_SUMDEC
-//SUM_INDEX
-#define SUM_INDEX__SUM_INDEX__SHIFT 0x0
-//SUM_DATA
-#define SUM_DATA__SUM_DATA__SHIFT 0x0
-
-
-// addressBlock: gdc_GDCDEC
-//A2S_CNTL_CL0
-#define A2S_CNTL_CL0__NSNOOP_MAP__SHIFT 0x0
-#define A2S_CNTL_CL0__REQPASSPW_VC0_MAP__SHIFT 0x2
-#define A2S_CNTL_CL0__REQPASSPW_NVC0_MAP__SHIFT 0x4
-#define A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP__SHIFT 0x6
-#define A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8
-#define A2S_CNTL_CL0__BLKLVL_MAP__SHIFT 0xa
-#define A2S_CNTL_CL0__DATERR_MAP__SHIFT 0xc
-#define A2S_CNTL_CL0__EXOKAY_WR_MAP__SHIFT 0xe
-#define A2S_CNTL_CL0__EXOKAY_RD_MAP__SHIFT 0x10
-#define A2S_CNTL_CL0__RESP_WR_MAP__SHIFT 0x12
-#define A2S_CNTL_CL0__RESP_RD_MAP__SHIFT 0x14
-//A2S_CNTL_CL1
-#define A2S_CNTL_CL1__NSNOOP_MAP__SHIFT 0x0
-#define A2S_CNTL_CL1__REQPASSPW_VC0_MAP__SHIFT 0x2
-#define A2S_CNTL_CL1__REQPASSPW_NVC0_MAP__SHIFT 0x4
-#define A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP__SHIFT 0x6
-#define A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8
-#define A2S_CNTL_CL1__BLKLVL_MAP__SHIFT 0xa
-#define A2S_CNTL_CL1__DATERR_MAP__SHIFT 0xc
-#define A2S_CNTL_CL1__EXOKAY_WR_MAP__SHIFT 0xe
-#define A2S_CNTL_CL1__EXOKAY_RD_MAP__SHIFT 0x10
-#define A2S_CNTL_CL1__RESP_WR_MAP__SHIFT 0x12
-#define A2S_CNTL_CL1__RESP_RD_MAP__SHIFT 0x14
-//A2S_CNTL_CL2
-#define A2S_CNTL_CL2__NSNOOP_MAP__SHIFT 0x0
-#define A2S_CNTL_CL2__REQPASSPW_VC0_MAP__SHIFT 0x2
-#define A2S_CNTL_CL2__REQPASSPW_NVC0_MAP__SHIFT 0x4
-#define A2S_CNTL_CL2__REQRSPPASSPW_VC0_MAP__SHIFT 0x6
-#define A2S_CNTL_CL2__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8
-#define A2S_CNTL_CL2__BLKLVL_MAP__SHIFT 0xa
-#define A2S_CNTL_CL2__DATERR_MAP__SHIFT 0xc
-#define A2S_CNTL_CL2__EXOKAY_WR_MAP__SHIFT 0xe
-#define A2S_CNTL_CL2__EXOKAY_RD_MAP__SHIFT 0x10
-#define A2S_CNTL_CL2__RESP_WR_MAP__SHIFT 0x12
-#define A2S_CNTL_CL2__RESP_RD_MAP__SHIFT 0x14
-//A2S_CNTL_CL3
-#define A2S_CNTL_CL3__NSNOOP_MAP__SHIFT 0x0
-#define A2S_CNTL_CL3__REQPASSPW_VC0_MAP__SHIFT 0x2
-#define A2S_CNTL_CL3__REQPASSPW_NVC0_MAP__SHIFT 0x4
-#define A2S_CNTL_CL3__REQRSPPASSPW_VC0_MAP__SHIFT 0x6
-#define A2S_CNTL_CL3__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8
-#define A2S_CNTL_CL3__BLKLVL_MAP__SHIFT 0xa
-#define A2S_CNTL_CL3__DATERR_MAP__SHIFT 0xc
-#define A2S_CNTL_CL3__EXOKAY_WR_MAP__SHIFT 0xe
-#define A2S_CNTL_CL3__EXOKAY_RD_MAP__SHIFT 0x10
-#define A2S_CNTL_CL3__RESP_WR_MAP__SHIFT 0x12
-#define A2S_CNTL_CL3__RESP_RD_MAP__SHIFT 0x14
-//A2S_CNTL_CL4
-#define A2S_CNTL_CL4__NSNOOP_MAP__SHIFT 0x0
-#define A2S_CNTL_CL4__REQPASSPW_VC0_MAP__SHIFT 0x2
-#define A2S_CNTL_CL4__REQPASSPW_NVC0_MAP__SHIFT 0x4
-#define A2S_CNTL_CL4__REQRSPPASSPW_VC0_MAP__SHIFT 0x6
-#define A2S_CNTL_CL4__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8
-#define A2S_CNTL_CL4__BLKLVL_MAP__SHIFT 0xa
-#define A2S_CNTL_CL4__DATERR_MAP__SHIFT 0xc
-#define A2S_CNTL_CL4__EXOKAY_WR_MAP__SHIFT 0xe
-#define A2S_CNTL_CL4__EXOKAY_RD_MAP__SHIFT 0x10
-#define A2S_CNTL_CL4__RESP_WR_MAP__SHIFT 0x12
-#define A2S_CNTL_CL4__RESP_RD_MAP__SHIFT 0x14
-//A2S_CNTL_SW0
-#define A2S_CNTL_SW0__WR_TAG_SET_MIN__SHIFT 0x0
-#define A2S_CNTL_SW0__RD_TAG_SET_MIN__SHIFT 0x3
-#define A2S_CNTL_SW0__FORCE_RSP_REORDER_EN__SHIFT 0x6
-#define A2S_CNTL_SW0__RSP_REORDER_DIS__SHIFT 0x7
-#define A2S_CNTL_SW0__WRRSP_ACCUM_SEL__SHIFT 0x8
-#define A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__SHIFT 0x9
-#define A2S_CNTL_SW0__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0xa
-#define A2S_CNTL_SW0__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0xb
-#define A2S_CNTL_SW0__RDRSP_STS_DATSTS_PRIORITY__SHIFT 0xc
-#define A2S_CNTL_SW0__WRR_RD_WEIGHT__SHIFT 0x10
-#define A2S_CNTL_SW0__WRR_WR_WEIGHT__SHIFT 0x18
-//A2S_CNTL_SW1
-#define A2S_CNTL_SW1__WR_TAG_SET_MIN__SHIFT 0x0
-#define A2S_CNTL_SW1__RD_TAG_SET_MIN__SHIFT 0x3
-#define A2S_CNTL_SW1__FORCE_RSP_REORDER_EN__SHIFT 0x6
-#define A2S_CNTL_SW1__RSP_REORDER_DIS__SHIFT 0x7
-#define A2S_CNTL_SW1__WRRSP_ACCUM_SEL__SHIFT 0x8
-#define A2S_CNTL_SW1__SDP_WR_CHAIN_DIS__SHIFT 0x9
-#define A2S_CNTL_SW1__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0xa
-#define A2S_CNTL_SW1__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0xb
-#define A2S_CNTL_SW1__RDRSP_STS_DATSTS_PRIORITY__SHIFT 0xc
-#define A2S_CNTL_SW1__WRR_RD_WEIGHT__SHIFT 0x10
-#define A2S_CNTL_SW1__WRR_WR_WEIGHT__SHIFT 0x18
-//A2S_CNTL_SW2
-#define A2S_CNTL_SW2__WR_TAG_SET_MIN__SHIFT 0x0
-#define A2S_CNTL_SW2__RD_TAG_SET_MIN__SHIFT 0x3
-#define A2S_CNTL_SW2__FORCE_RSP_REORDER_EN__SHIFT 0x6
-#define A2S_CNTL_SW2__RSP_REORDER_DIS__SHIFT 0x7
-#define A2S_CNTL_SW2__WRRSP_ACCUM_SEL__SHIFT 0x8
-#define A2S_CNTL_SW2__SDP_WR_CHAIN_DIS__SHIFT 0x9
-#define A2S_CNTL_SW2__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0xa
-#define A2S_CNTL_SW2__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0xb
-#define A2S_CNTL_SW2__RDRSP_STS_DATSTS_PRIORITY__SHIFT 0xc
-#define A2S_CNTL_SW2__WRR_RD_WEIGHT__SHIFT 0x10
-#define A2S_CNTL_SW2__WRR_WR_WEIGHT__SHIFT 0x18
-//NGDC_MGCG_CTRL
-#define NGDC_MGCG_CTRL__NGDC_MGCG_EN__SHIFT 0x0
-#define NGDC_MGCG_CTRL__NGDC_MGCG_MODE__SHIFT 0x1
-#define NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__SHIFT 0x2
-//A2S_MISC_CNTL
-#define A2S_MISC_CNTL__BLKLVL_FOR_MSG__SHIFT 0x0
-#define A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS__SHIFT 0x2
-//NGDC_SDP_PORT_CTRL
-#define NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT 0x0
-//NGDC_RESERVED_0
-#define NGDC_RESERVED_0__RESERVED__SHIFT 0x0
-//NGDC_RESERVED_1
-#define NGDC_RESERVED_1__RESERVED__SHIFT 0x0
-//BIF_SDMA0_DOORBELL_RANGE
-#define BIF_SDMA0_DOORBELL_RANGE__OFFSET__SHIFT 0x2
-#define BIF_SDMA0_DOORBELL_RANGE__SIZE__SHIFT 0x10
-//BIF_SDMA1_DOORBELL_RANGE
-#define BIF_SDMA1_DOORBELL_RANGE__OFFSET__SHIFT 0x2
-#define BIF_SDMA1_DOORBELL_RANGE__SIZE__SHIFT 0x10
-//BIF_IH_DOORBELL_RANGE
-#define BIF_IH_DOORBELL_RANGE__OFFSET__SHIFT 0x2
-#define BIF_IH_DOORBELL_RANGE__SIZE__SHIFT 0x10
-//BIF_MMSCH0_DOORBELL_RANGE
-#define BIF_MMSCH0_DOORBELL_RANGE__OFFSET__SHIFT 0x2
-#define BIF_MMSCH0_DOORBELL_RANGE__SIZE__SHIFT 0x10
-//BIF_DOORBELL_FENCE_CNTL
-#define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE__SHIFT 0x0
-//S2A_MISC_CNTL
-#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__SHIFT 0x0
-#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__SHIFT 0x1
-#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__SHIFT 0x2
-//A2S_CNTL2_SEC_CL0
-#define A2S_CNTL2_SEC_CL0__SECLVL_MAP__SHIFT 0x0
-//A2S_CNTL2_SEC_CL1
-#define A2S_CNTL2_SEC_CL1__SECLVL_MAP__SHIFT 0x0
-//A2S_CNTL2_SEC_CL2
-#define A2S_CNTL2_SEC_CL2__SECLVL_MAP__SHIFT 0x0
-//A2S_CNTL2_SEC_CL3
-#define A2S_CNTL2_SEC_CL3__SECLVL_MAP__SHIFT 0x0
-//A2S_CNTL2_SEC_CL4
-#define A2S_CNTL2_SEC_CL4__SECLVL_MAP__SHIFT 0x0
-
-
-// addressBlock: nbif_sion_SIONDEC
-//SION_CL0_RdRsp_BurstTarget_REG0
-#define SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0
-//SION_CL0_RdRsp_BurstTarget_REG1
-#define SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0
-//SION_CL0_RdRsp_TimeSlot_REG0
-#define SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0
-//SION_CL0_RdRsp_TimeSlot_REG1
-#define SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0
-//SION_CL0_WrRsp_BurstTarget_REG0
-#define SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0
-//SION_CL0_WrRsp_BurstTarget_REG1
-#define SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0
-//SION_CL0_WrRsp_TimeSlot_REG0
-#define SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0
-//SION_CL0_WrRsp_TimeSlot_REG1
-#define SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0
-//SION_CL0_Req_BurstTarget_REG0
-#define SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0
-//SION_CL0_Req_BurstTarget_REG1
-#define SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0
-//SION_CL0_Req_TimeSlot_REG0
-#define SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0
-//SION_CL0_Req_TimeSlot_REG1
-#define SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0
-//SION_CL0_ReqPoolCredit_Alloc_REG0
-#define SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0
-//SION_CL0_ReqPoolCredit_Alloc_REG1
-#define SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0
-//SION_CL0_DataPoolCredit_Alloc_REG0
-#define SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0
-//SION_CL0_DataPoolCredit_Alloc_REG1
-#define SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0
-//SION_CL0_RdRspPoolCredit_Alloc_REG0
-#define SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0
-//SION_CL0_RdRspPoolCredit_Alloc_REG1
-#define SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0
-//SION_CL0_WrRspPoolCredit_Alloc_REG0
-#define SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0
-//SION_CL0_WrRspPoolCredit_Alloc_REG1
-#define SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0
-//SION_CL1_RdRsp_BurstTarget_REG0
-#define SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0
-//SION_CL1_RdRsp_BurstTarget_REG1
-#define SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0
-//SION_CL1_RdRsp_TimeSlot_REG0
-#define SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0
-//SION_CL1_RdRsp_TimeSlot_REG1
-#define SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0
-//SION_CL1_WrRsp_BurstTarget_REG0
-#define SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0
-//SION_CL1_WrRsp_BurstTarget_REG1
-#define SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0
-//SION_CL1_WrRsp_TimeSlot_REG0
-#define SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0
-//SION_CL1_WrRsp_TimeSlot_REG1
-#define SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0
-//SION_CL1_Req_BurstTarget_REG0
-#define SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0
-//SION_CL1_Req_BurstTarget_REG1
-#define SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0
-//SION_CL1_Req_TimeSlot_REG0
-#define SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0
-//SION_CL1_Req_TimeSlot_REG1
-#define SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0
-//SION_CL1_ReqPoolCredit_Alloc_REG0
-#define SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0
-//SION_CL1_ReqPoolCredit_Alloc_REG1
-#define SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0
-//SION_CL1_DataPoolCredit_Alloc_REG0
-#define SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0
-//SION_CL1_DataPoolCredit_Alloc_REG1
-#define SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0
-//SION_CL1_RdRspPoolCredit_Alloc_REG0
-#define SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0
-//SION_CL1_RdRspPoolCredit_Alloc_REG1
-#define SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0
-//SION_CL1_WrRspPoolCredit_Alloc_REG0
-#define SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0
-//SION_CL1_WrRspPoolCredit_Alloc_REG1
-#define SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0
-//SION_CL2_RdRsp_BurstTarget_REG0
-#define SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0
-//SION_CL2_RdRsp_BurstTarget_REG1
-#define SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0
-//SION_CL2_RdRsp_TimeSlot_REG0
-#define SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0
-//SION_CL2_RdRsp_TimeSlot_REG1
-#define SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0
-//SION_CL2_WrRsp_BurstTarget_REG0
-#define SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0
-//SION_CL2_WrRsp_BurstTarget_REG1
-#define SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0
-//SION_CL2_WrRsp_TimeSlot_REG0
-#define SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0
-//SION_CL2_WrRsp_TimeSlot_REG1
-#define SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0
-//SION_CL2_Req_BurstTarget_REG0
-#define SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0
-//SION_CL2_Req_BurstTarget_REG1
-#define SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0
-//SION_CL2_Req_TimeSlot_REG0
-#define SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0
-//SION_CL2_Req_TimeSlot_REG1
-#define SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0
-//SION_CL2_ReqPoolCredit_Alloc_REG0
-#define SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0
-//SION_CL2_ReqPoolCredit_Alloc_REG1
-#define SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0
-//SION_CL2_DataPoolCredit_Alloc_REG0
-#define SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0
-//SION_CL2_DataPoolCredit_Alloc_REG1
-#define SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0
-//SION_CL2_RdRspPoolCredit_Alloc_REG0
-#define SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0
-//SION_CL2_RdRspPoolCredit_Alloc_REG1
-#define SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0
-//SION_CL2_WrRspPoolCredit_Alloc_REG0
-#define SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0
-//SION_CL2_WrRspPoolCredit_Alloc_REG1
-#define SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0
-//SION_CL3_RdRsp_BurstTarget_REG0
-#define SION_CL3_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0
-//SION_CL3_RdRsp_BurstTarget_REG1
-#define SION_CL3_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0
-//SION_CL3_RdRsp_TimeSlot_REG0
-#define SION_CL3_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0
-//SION_CL3_RdRsp_TimeSlot_REG1
-#define SION_CL3_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0
-//SION_CL3_WrRsp_BurstTarget_REG0
-#define SION_CL3_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0
-//SION_CL3_WrRsp_BurstTarget_REG1
-#define SION_CL3_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0
-//SION_CL3_WrRsp_TimeSlot_REG0
-#define SION_CL3_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0
-//SION_CL3_WrRsp_TimeSlot_REG1
-#define SION_CL3_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0
-//SION_CL3_Req_BurstTarget_REG0
-#define SION_CL3_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0
-//SION_CL3_Req_BurstTarget_REG1
-#define SION_CL3_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0
-//SION_CL3_Req_TimeSlot_REG0
-#define SION_CL3_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0
-//SION_CL3_Req_TimeSlot_REG1
-#define SION_CL3_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0
-//SION_CL3_ReqPoolCredit_Alloc_REG0
-#define SION_CL3_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0
-//SION_CL3_ReqPoolCredit_Alloc_REG1
-#define SION_CL3_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0
-//SION_CL3_DataPoolCredit_Alloc_REG0
-#define SION_CL3_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0
-//SION_CL3_DataPoolCredit_Alloc_REG1
-#define SION_CL3_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0
-//SION_CL3_RdRspPoolCredit_Alloc_REG0
-#define SION_CL3_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0
-//SION_CL3_RdRspPoolCredit_Alloc_REG1
-#define SION_CL3_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0
-//SION_CL3_WrRspPoolCredit_Alloc_REG0
-#define SION_CL3_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0
-//SION_CL3_WrRspPoolCredit_Alloc_REG1
-#define SION_CL3_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0
-//SION_CL4_RdRsp_BurstTarget_REG0
-#define SION_CL4_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0
-//SION_CL4_RdRsp_BurstTarget_REG1
-#define SION_CL4_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0
-//SION_CL4_RdRsp_TimeSlot_REG0
-#define SION_CL4_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0
-//SION_CL4_RdRsp_TimeSlot_REG1
-#define SION_CL4_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0
-//SION_CL4_WrRsp_BurstTarget_REG0
-#define SION_CL4_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0
-//SION_CL4_WrRsp_BurstTarget_REG1
-#define SION_CL4_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0
-//SION_CL4_WrRsp_TimeSlot_REG0
-#define SION_CL4_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0
-//SION_CL4_WrRsp_TimeSlot_REG1
-#define SION_CL4_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0
-//SION_CL4_Req_BurstTarget_REG0
-#define SION_CL4_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0
-//SION_CL4_Req_BurstTarget_REG1
-#define SION_CL4_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0
-//SION_CL4_Req_TimeSlot_REG0
-#define SION_CL4_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0
-//SION_CL4_Req_TimeSlot_REG1
-#define SION_CL4_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0
-//SION_CL4_ReqPoolCredit_Alloc_REG0
-#define SION_CL4_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0
-//SION_CL4_ReqPoolCredit_Alloc_REG1
-#define SION_CL4_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0
-//SION_CL4_DataPoolCredit_Alloc_REG0
-#define SION_CL4_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0
-//SION_CL4_DataPoolCredit_Alloc_REG1
-#define SION_CL4_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0
-//SION_CL4_RdRspPoolCredit_Alloc_REG0
-#define SION_CL4_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0
-//SION_CL4_RdRspPoolCredit_Alloc_REG1
-#define SION_CL4_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0
-//SION_CL4_WrRspPoolCredit_Alloc_REG0
-#define SION_CL4_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0
-//SION_CL4_WrRspPoolCredit_Alloc_REG1
-#define SION_CL4_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0
-//SION_CL5_RdRsp_BurstTarget_REG0
-#define SION_CL5_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0
-//SION_CL5_RdRsp_BurstTarget_REG1
-#define SION_CL5_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0
-//SION_CL5_RdRsp_TimeSlot_REG0
-#define SION_CL5_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0
-//SION_CL5_RdRsp_TimeSlot_REG1
-#define SION_CL5_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0
-//SION_CL5_WrRsp_BurstTarget_REG0
-#define SION_CL5_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0
-//SION_CL5_WrRsp_BurstTarget_REG1
-#define SION_CL5_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0
-//SION_CL5_WrRsp_TimeSlot_REG0
-#define SION_CL5_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0
-//SION_CL5_WrRsp_TimeSlot_REG1
-#define SION_CL5_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0
-//SION_CL5_Req_BurstTarget_REG0
-#define SION_CL5_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0
-//SION_CL5_Req_BurstTarget_REG1
-#define SION_CL5_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0
-//SION_CL5_Req_TimeSlot_REG0
-#define SION_CL5_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0
-//SION_CL5_Req_TimeSlot_REG1
-#define SION_CL5_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0
-//SION_CL5_ReqPoolCredit_Alloc_REG0
-#define SION_CL5_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0
-//SION_CL5_ReqPoolCredit_Alloc_REG1
-#define SION_CL5_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0
-//SION_CL5_DataPoolCredit_Alloc_REG0
-#define SION_CL5_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0
-//SION_CL5_DataPoolCredit_Alloc_REG1
-#define SION_CL5_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0
-//SION_CL5_RdRspPoolCredit_Alloc_REG0
-#define SION_CL5_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0
-//SION_CL5_RdRspPoolCredit_Alloc_REG1
-#define SION_CL5_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0
-//SION_CL5_WrRspPoolCredit_Alloc_REG0
-#define SION_CL5_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0
-//SION_CL5_WrRspPoolCredit_Alloc_REG1
-#define SION_CL5_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0
-//SION_CNTL_REG0
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT 0x0
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT 0x1
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT 0x2
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT 0x3
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT 0x4
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT 0x5
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT 0x6
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT 0x7
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT 0x8
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT 0x9
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__SHIFT 0xa
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__SHIFT 0xb
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__SHIFT 0xc
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__SHIFT 0xd
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__SHIFT 0xe
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__SHIFT 0xf
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__SHIFT 0x10
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__SHIFT 0x11
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__SHIFT 0x12
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__SHIFT 0x13
-//SION_CNTL_REG1
-#define SION_CNTL_REG1__LIVELOCK_WATCHDOG_THRESHOLD__SHIFT 0x0
-#define SION_CNTL_REG1__CG_OFF_HYSTERESIS__SHIFT 0x8
-
-
-// addressBlock: syshub_mmreg_direct_syshubdirect
-//SYSHUB_DS_CTRL_SOCCLK
-#define SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0
-#define SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1
-#define SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2
-#define SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3
-#define SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4
-#define SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5
-#define SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6
-#define SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7
-#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10
-#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11
-#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12
-#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13
-#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14
-#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15
-#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16
-#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17
-#define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c
-#define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__SHIFT 0x1f
-//SYSHUB_DS_CTRL2_SOCCLK
-#define SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__SHIFT 0x0
-//SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK
-#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en__SHIFT 0x0
-#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en__SHIFT 0x1
-#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__SHIFT 0xf
-#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__SHIFT 0x10
-#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__SHIFT 0x11
-//SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK
-#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en__SHIFT 0x0
-#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en__SHIFT 0x1
-#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__SHIFT 0xf
-#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__SHIFT 0x10
-#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__SHIFT 0x11
-//DMA_CLK0_SW0_SYSHUB_QOS_CNTL
-#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0
-#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1
-#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5
-//DMA_CLK0_SW1_SYSHUB_QOS_CNTL
-#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0
-#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1
-#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5
-//DMA_CLK0_SW0_CL0_CNTL
-#define DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
-#define DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
-#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
-#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
-#define DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
-#define DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
-//DMA_CLK0_SW0_CL1_CNTL
-#define DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
-#define DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
-#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
-#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
-#define DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
-#define DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
-//DMA_CLK0_SW0_CL2_CNTL
-#define DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
-#define DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
-#define DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
-#define DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
-#define DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
-#define DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
-//DMA_CLK0_SW0_CL3_CNTL
-#define DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
-#define DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
-#define DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
-#define DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
-#define DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
-#define DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
-//DMA_CLK0_SW0_CL4_CNTL
-#define DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
-#define DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
-#define DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
-#define DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
-#define DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
-#define DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
-//DMA_CLK0_SW0_CL5_CNTL
-#define DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
-#define DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
-#define DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
-#define DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
-#define DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
-#define DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
-//DMA_CLK0_SW1_CL0_CNTL
-#define DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
-#define DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
-#define DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
-#define DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
-#define DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
-#define DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
-//DMA_CLK0_SW2_CL0_CNTL
-#define DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
-#define DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
-#define DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
-#define DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
-#define DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
-#define DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
-//SYSHUB_CG_CNTL
-#define SYSHUB_CG_CNTL__SYSHUB_CG_EN__SHIFT 0x0
-#define SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER__SHIFT 0x8
-#define SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER__SHIFT 0x10
-//SYSHUB_TRANS_IDLE
-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0__SHIFT 0x0
-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1__SHIFT 0x1
-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2__SHIFT 0x2
-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3__SHIFT 0x3
-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4__SHIFT 0x4
-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5__SHIFT 0x5
-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6__SHIFT 0x6
-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7__SHIFT 0x7
-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8__SHIFT 0x8
-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9__SHIFT 0x9
-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10__SHIFT 0xa
-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11__SHIFT 0xb
-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12__SHIFT 0xc
-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13__SHIFT 0xd
-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14__SHIFT 0xe
-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15__SHIFT 0xf
-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF__SHIFT 0x10
-//SYSHUB_HP_TIMER
-#define SYSHUB_HP_TIMER__SYSHUB_HP_TIMER__SHIFT 0x0
-//SYSHUB_SCRATCH
-#define SYSHUB_SCRATCH__SCRATCH__SHIFT 0x0
-//SYSHUB_DS_CTRL_SHUBCLK
-#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0
-#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1
-#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2
-#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3
-#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4
-#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5
-#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6
-#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7
-#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10
-#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11
-#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12
-#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13
-#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14
-#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15
-#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16
-#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17
-#define SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c
-#define SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN__SHIFT 0x1f
-//SYSHUB_DS_CTRL2_SHUBCLK
-#define SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER__SHIFT 0x0
-//SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK
-#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en__SHIFT 0xf
-#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en__SHIFT 0x10
-//SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK
-#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en__SHIFT 0xf
-#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en__SHIFT 0x10
-//DMA_CLK1_SW0_SYSHUB_QOS_CNTL
-#define DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0
-#define DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1
-#define DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5
-//DMA_CLK1_SW1_SYSHUB_QOS_CNTL
-#define DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0
-#define DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1
-#define DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5
-//DMA_CLK1_SW0_CL0_CNTL
-#define DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
-#define DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
-#define DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
-#define DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
-#define DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
-#define DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
-//DMA_CLK1_SW0_CL1_CNTL
-#define DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
-#define DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
-#define DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
-#define DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
-#define DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
-#define DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
-//DMA_CLK1_SW0_CL2_CNTL
-#define DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
-#define DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
-#define DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
-#define DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
-#define DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
-#define DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
-//DMA_CLK1_SW0_CL3_CNTL
-#define DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
-#define DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
-#define DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
-#define DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
-#define DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
-#define DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
-//DMA_CLK1_SW0_CL4_CNTL
-#define DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
-#define DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
-#define DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
-#define DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
-#define DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
-#define DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
-//DMA_CLK1_SW1_CL0_CNTL
-#define DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
-#define DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
-#define DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
-#define DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
-#define DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
-#define DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
-//DMA_CLK1_SW1_CL1_CNTL
-#define DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
-#define DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
-#define DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
-#define DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
-#define DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
-#define DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
-//DMA_CLK1_SW1_CL2_CNTL
-#define DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
-#define DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
-#define DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
-#define DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
-#define DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
-#define DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
-//DMA_CLK1_SW1_CL3_CNTL
-#define DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
-#define DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
-#define DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
-#define DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
-#define DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
-#define DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
-//DMA_CLK1_SW1_CL4_CNTL
-#define DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
-#define DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
-#define DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
-#define DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
-#define DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
-#define DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
-
-
-// addressBlock: gdc_ras_gdc_ras_regblk
-//GDC_RAS_LEAF0_CTRL
-#define GDC_RAS_LEAF0_CTRL__POISON_DET_EN__SHIFT 0x0
-#define GDC_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
-#define GDC_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT 0x2
-#define GDC_RAS_LEAF0_CTRL__PARITY_DET_EN__SHIFT 0x4
-#define GDC_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5
-#define GDC_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT 0x6
-#define GDC_RAS_LEAF0_CTRL__ERR_EVENT_RECV__SHIFT 0x10
-#define GDC_RAS_LEAF0_CTRL__LINK_DIS_RECV__SHIFT 0x11
-#define GDC_RAS_LEAF0_CTRL__POISON_ERR_DET__SHIFT 0x12
-#define GDC_RAS_LEAF0_CTRL__PARITY_ERR_DET__SHIFT 0x13
-#define GDC_RAS_LEAF0_CTRL__ERR_EVENT_SENT__SHIFT 0x14
-#define GDC_RAS_LEAF0_CTRL__EGRESS_STALLED__SHIFT 0x15
-//GDC_RAS_LEAF1_CTRL
-#define GDC_RAS_LEAF1_CTRL__POISON_DET_EN__SHIFT 0x0
-#define GDC_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
-#define GDC_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT 0x2
-#define GDC_RAS_LEAF1_CTRL__PARITY_DET_EN__SHIFT 0x4
-#define GDC_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5
-#define GDC_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT 0x6
-#define GDC_RAS_LEAF1_CTRL__ERR_EVENT_RECV__SHIFT 0x10
-#define GDC_RAS_LEAF1_CTRL__LINK_DIS_RECV__SHIFT 0x11
-#define GDC_RAS_LEAF1_CTRL__POISON_ERR_DET__SHIFT 0x12
-#define GDC_RAS_LEAF1_CTRL__PARITY_ERR_DET__SHIFT 0x13
-#define GDC_RAS_LEAF1_CTRL__ERR_EVENT_SENT__SHIFT 0x14
-#define GDC_RAS_LEAF1_CTRL__EGRESS_STALLED__SHIFT 0x15
-//GDC_RAS_LEAF2_CTRL
-#define GDC_RAS_LEAF2_CTRL__POISON_DET_EN__SHIFT 0x0
-#define GDC_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
-#define GDC_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT 0x2
-#define GDC_RAS_LEAF2_CTRL__PARITY_DET_EN__SHIFT 0x4
-#define GDC_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5
-#define GDC_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT 0x6
-#define GDC_RAS_LEAF2_CTRL__ERR_EVENT_RECV__SHIFT 0x10
-#define GDC_RAS_LEAF2_CTRL__LINK_DIS_RECV__SHIFT 0x11
-#define GDC_RAS_LEAF2_CTRL__POISON_ERR_DET__SHIFT 0x12
-#define GDC_RAS_LEAF2_CTRL__PARITY_ERR_DET__SHIFT 0x13
-#define GDC_RAS_LEAF2_CTRL__ERR_EVENT_SENT__SHIFT 0x14
-#define GDC_RAS_LEAF2_CTRL__EGRESS_STALLED__SHIFT 0x15
-//GDC_RAS_LEAF3_CTRL
-#define GDC_RAS_LEAF3_CTRL__POISON_DET_EN__SHIFT 0x0
-#define GDC_RAS_LEAF3_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
-#define GDC_RAS_LEAF3_CTRL__POISON_STALL_EN__SHIFT 0x2
-#define GDC_RAS_LEAF3_CTRL__PARITY_DET_EN__SHIFT 0x4
-#define GDC_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5
-#define GDC_RAS_LEAF3_CTRL__PARITY_STALL_EN__SHIFT 0x6
-#define GDC_RAS_LEAF3_CTRL__ERR_EVENT_RECV__SHIFT 0x10
-#define GDC_RAS_LEAF3_CTRL__LINK_DIS_RECV__SHIFT 0x11
-#define GDC_RAS_LEAF3_CTRL__POISON_ERR_DET__SHIFT 0x12
-#define GDC_RAS_LEAF3_CTRL__PARITY_ERR_DET__SHIFT 0x13
-#define GDC_RAS_LEAF3_CTRL__ERR_EVENT_SENT__SHIFT 0x14
-#define GDC_RAS_LEAF3_CTRL__EGRESS_STALLED__SHIFT 0x15
-//GDC_RAS_LEAF4_CTRL
-#define GDC_RAS_LEAF4_CTRL__POISON_DET_EN__SHIFT 0x0
-#define GDC_RAS_LEAF4_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
-#define GDC_RAS_LEAF4_CTRL__POISON_STALL_EN__SHIFT 0x2
-#define GDC_RAS_LEAF4_CTRL__PARITY_DET_EN__SHIFT 0x4
-#define GDC_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5
-#define GDC_RAS_LEAF4_CTRL__PARITY_STALL_EN__SHIFT 0x6
-#define GDC_RAS_LEAF4_CTRL__ERR_EVENT_RECV__SHIFT 0x10
-#define GDC_RAS_LEAF4_CTRL__LINK_DIS_RECV__SHIFT 0x11
-#define GDC_RAS_LEAF4_CTRL__POISON_ERR_DET__SHIFT 0x12
-#define GDC_RAS_LEAF4_CTRL__PARITY_ERR_DET__SHIFT 0x13
-#define GDC_RAS_LEAF4_CTRL__ERR_EVENT_SENT__SHIFT 0x14
-#define GDC_RAS_LEAF4_CTRL__EGRESS_STALLED__SHIFT 0x15
-//GDC_RAS_LEAF5_CTRL
-#define GDC_RAS_LEAF5_CTRL__POISON_DET_EN__SHIFT 0x0
-#define GDC_RAS_LEAF5_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
-#define GDC_RAS_LEAF5_CTRL__POISON_STALL_EN__SHIFT 0x2
-#define GDC_RAS_LEAF5_CTRL__PARITY_DET_EN__SHIFT 0x4
-#define GDC_RAS_LEAF5_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5
-#define GDC_RAS_LEAF5_CTRL__PARITY_STALL_EN__SHIFT 0x6
-#define GDC_RAS_LEAF5_CTRL__ERR_EVENT_RECV__SHIFT 0x10
-#define GDC_RAS_LEAF5_CTRL__LINK_DIS_RECV__SHIFT 0x11
-#define GDC_RAS_LEAF5_CTRL__POISON_ERR_DET__SHIFT 0x12
-#define GDC_RAS_LEAF5_CTRL__PARITY_ERR_DET__SHIFT 0x13
-#define GDC_RAS_LEAF5_CTRL__ERR_EVENT_SENT__SHIFT 0x14
-#define GDC_RAS_LEAF5_CTRL__EGRESS_STALLED__SHIFT 0x15
-
-
-// addressBlock: gdc_rst_GDCRST_DEC
-//SHUB_PF_FLR_RST
-#define SHUB_PF_FLR_RST__PF0_FLR_RST__SHIFT 0x0
-#define SHUB_PF_FLR_RST__PF1_FLR_RST__SHIFT 0x1
-#define SHUB_PF_FLR_RST__PF2_FLR_RST__SHIFT 0x2
-#define SHUB_PF_FLR_RST__PF3_FLR_RST__SHIFT 0x3
-#define SHUB_PF_FLR_RST__PF4_FLR_RST__SHIFT 0x4
-#define SHUB_PF_FLR_RST__PF5_FLR_RST__SHIFT 0x5
-#define SHUB_PF_FLR_RST__PF6_FLR_RST__SHIFT 0x6
-#define SHUB_PF_FLR_RST__PF7_FLR_RST__SHIFT 0x7
-//SHUB_GFX_DRV_MODE1_RST
-#define SHUB_GFX_DRV_MODE1_RST__GFX_DRV_MODE1_RST__SHIFT 0x0
-//SHUB_LINK_RESET
-#define SHUB_LINK_RESET__LINK_RESET__SHIFT 0x0
-//SHUB_PF0_VF_FLR_RST
-#define SHUB_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__SHIFT 0x0
-#define SHUB_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__SHIFT 0x1
-#define SHUB_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__SHIFT 0x2
-#define SHUB_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__SHIFT 0x3
-#define SHUB_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__SHIFT 0x4
-#define SHUB_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__SHIFT 0x5
-#define SHUB_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__SHIFT 0x6
-#define SHUB_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__SHIFT 0x7
-#define SHUB_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__SHIFT 0x8
-#define SHUB_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__SHIFT 0x9
-#define SHUB_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__SHIFT 0xa
-#define SHUB_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__SHIFT 0xb
-#define SHUB_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__SHIFT 0xc
-#define SHUB_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__SHIFT 0xd
-#define SHUB_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__SHIFT 0xe
-#define SHUB_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__SHIFT 0xf
-#define SHUB_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__SHIFT 0x1f
-//SHUB_HARD_RST_CTRL
-#define SHUB_HARD_RST_CTRL__COR_RESET_EN__SHIFT 0x0
-#define SHUB_HARD_RST_CTRL__REG_RESET_EN__SHIFT 0x1
-#define SHUB_HARD_RST_CTRL__STY_RESET_EN__SHIFT 0x2
-#define SHUB_HARD_RST_CTRL__NIC400_RESET_EN__SHIFT 0x3
-#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4
-//SHUB_SOFT_RST_CTRL
-#define SHUB_SOFT_RST_CTRL__COR_RESET_EN__SHIFT 0x0
-#define SHUB_SOFT_RST_CTRL__REG_RESET_EN__SHIFT 0x1
-#define SHUB_SOFT_RST_CTRL__STY_RESET_EN__SHIFT 0x2
-#define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN__SHIFT 0x3
-#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4
-//SHUB_SDP_PORT_RST
-#define SHUB_SDP_PORT_RST__SDP_PORT_RST__SHIFT 0x0
-
-
-// addressBlock: bif_bx_pf_SYSDEC
-//SBIOS_SCRATCH_0
-#define SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__SHIFT 0x0
-//SBIOS_SCRATCH_1
-#define SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__SHIFT 0x0
-//SBIOS_SCRATCH_2
-#define SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__SHIFT 0x0
-//SBIOS_SCRATCH_3
-#define SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__SHIFT 0x0
-//BIOS_SCRATCH_0
-#define BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0
-//BIOS_SCRATCH_1
-#define BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0
-//BIOS_SCRATCH_2
-#define BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0
-//BIOS_SCRATCH_3
-#define BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0
-//BIOS_SCRATCH_4
-#define BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0
-//BIOS_SCRATCH_5
-#define BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0
-//BIOS_SCRATCH_6
-#define BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0
-//BIOS_SCRATCH_7
-#define BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0
-//BIOS_SCRATCH_8
-#define BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0
-//BIOS_SCRATCH_9
-#define BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0
-//BIOS_SCRATCH_10
-#define BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0
-//BIOS_SCRATCH_11
-#define BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0
-//BIOS_SCRATCH_12
-#define BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0
-//BIOS_SCRATCH_13
-#define BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0
-//BIOS_SCRATCH_14
-#define BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0
-//BIOS_SCRATCH_15
-#define BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0
-//BIF_RLC_INTR_CNTL
-#define BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT 0x0
-#define BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT 0x1
-#define BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT 0x2
-#define BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT 0x3
-//BIF_VCE_INTR_CNTL
-#define BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT 0x0
-#define BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT 0x1
-#define BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT 0x2
-#define BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT 0x3
-//BIF_UVD_INTR_CNTL
-#define BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT 0x0
-#define BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT 0x1
-#define BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT 0x2
-#define BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT 0x3
-//GFX_MMIOREG_CAM_ADDR0
-#define GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0
-//GFX_MMIOREG_CAM_REMAP_ADDR0
-#define GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0
-//GFX_MMIOREG_CAM_ADDR1
-#define GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0
-//GFX_MMIOREG_CAM_REMAP_ADDR1
-#define GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0
-//GFX_MMIOREG_CAM_ADDR2
-#define GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0
-//GFX_MMIOREG_CAM_REMAP_ADDR2
-#define GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0
-//GFX_MMIOREG_CAM_ADDR3
-#define GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0
-//GFX_MMIOREG_CAM_REMAP_ADDR3
-#define GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0
-//GFX_MMIOREG_CAM_ADDR4
-#define GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0
-//GFX_MMIOREG_CAM_REMAP_ADDR4
-#define GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0
-//GFX_MMIOREG_CAM_ADDR5
-#define GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0
-//GFX_MMIOREG_CAM_REMAP_ADDR5
-#define GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0
-//GFX_MMIOREG_CAM_ADDR6
-#define GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0
-//GFX_MMIOREG_CAM_REMAP_ADDR6
-#define GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0
-//GFX_MMIOREG_CAM_ADDR7
-#define GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0
-//GFX_MMIOREG_CAM_REMAP_ADDR7
-#define GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0
-//GFX_MMIOREG_CAM_CNTL
-#define GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0
-//GFX_MMIOREG_CAM_ZERO_CPL
-#define GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0
-//GFX_MMIOREG_CAM_ONE_CPL
-#define GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0
-//GFX_MMIOREG_CAM_PROGRAMMABLE_CPL
-#define GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0
-
-
-// addressBlock: bif_bx_pf_SYSPFVFDEC
-//MM_INDEX
-#define MM_INDEX__MM_OFFSET__SHIFT 0x0
-#define MM_INDEX__MM_APER__SHIFT 0x1f
-//MM_DATA
-#define MM_DATA__MM_DATA__SHIFT 0x0
-//MM_INDEX_HI
-#define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
-//SYSHUB_INDEX_OVLP
-#define SYSHUB_INDEX_OVLP__SYSHUB_OFFSET__SHIFT 0x0
-//SYSHUB_DATA_OVLP
-#define SYSHUB_DATA_OVLP__SYSHUB_DATA__SHIFT 0x0
-//PCIE_INDEX
-#define PCIE_INDEX__PCIE_INDEX__SHIFT 0x0
-//PCIE_DATA
-#define PCIE_DATA__PCIE_DATA__SHIFT 0x0
-//PCIE_INDEX2
-#define PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0
-//PCIE_DATA2
-#define PCIE_DATA2__PCIE_DATA2__SHIFT 0x0
-
-
-// addressBlock: rcc_dwn_BIFDEC1
-//DN_PCIE_RESERVED
-#define DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
-//DN_PCIE_SCRATCH
-#define DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
-//DN_PCIE_CNTL
-#define DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
-#define DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7
-#define DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
-//DN_PCIE_CONFIG_CNTL
-#define DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
-//DN_PCIE_RX_CNTL2
-#define DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c
-//DN_PCIE_BUS_CNTL
-#define DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
-#define DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8
-//DN_PCIE_CFG_CNTL
-#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
-#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
-#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
-//DN_PCIE_STRAP_F0
-#define DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0
-#define DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11
-#define DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15
-//DN_PCIE_STRAP_MISC
-#define DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18
-#define DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
-//DN_PCIE_STRAP_MISC2
-#define DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2
-
-
-// addressBlock: rcc_dwnp_BIFDEC1
-//PCIEP_RESERVED
-#define PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
-//PCIEP_SCRATCH
-#define PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
-//PCIE_ERR_CNTL
-#define PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
-#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
-#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
-#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
-//PCIE_RX_CNTL
-#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
-#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9
-#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
-#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15
-#define PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
-//PCIE_LC_SPEED_CNTL
-#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
-#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
-//PCIE_LC_CNTL2
-#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
-//PCIEP_STRAP_MISC
-#define PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa
-//LTR_MSG_INFO_FROM_EP
-#define LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0
-
-
-// addressBlock: rcc_ep_BIFDEC1
-//EP_PCIE_SCRATCH
-#define EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
-//EP_PCIE_CNTL
-#define EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
-#define EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
-#define EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
-//EP_PCIE_INT_CNTL
-#define EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0
-#define EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1
-#define EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2
-#define EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3
-#define EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4
-#define EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6
-//EP_PCIE_INT_STATUS
-#define EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0
-#define EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1
-#define EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2
-#define EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3
-#define EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4
-#define EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6
-//EP_PCIE_RX_CNTL2
-#define EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
-//EP_PCIE_BUS_CNTL
-#define EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
-//EP_PCIE_CFG_CNTL
-#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
-#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
-#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
-//EP_PCIE_OBFF_CNTL
-#define EP_PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE__SHIFT 0x0
-#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN__SHIFT 0x1
-#define EP_PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE__SHIFT 0x2
-#define EP_PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE__SHIFT 0x3
-#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH__SHIFT 0x4
-#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH__SHIFT 0x8
-#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD__SHIFT 0xc
-#define EP_PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE__SHIFT 0x10
-#define EP_PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE__SHIFT 0x11
-#define EP_PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE__SHIFT 0x12
-#define EP_PCIE_OBFF_CNTL__TX_OBFF_ACCEPT_IN_NOND0__SHIFT 0x13
-#define EP_PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE__SHIFT 0x14
-//EP_PCIE_TX_LTR_CNTL
-#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0
-#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3
-#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6
-#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7
-#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa
-#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd
-#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe
-#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf
-#define EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10
-//EP_PCIE_STRAP_MISC
-#define EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
-//EP_PCIE_STRAP_MISC2
-#define EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4
-//EP_PCIE_STRAP_PI
-//EP_PCIE_F0_DPA_CAP
-#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
-#define EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
-#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
-#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
-//EP_PCIE_F0_DPA_LATENCY_INDICATOR
-#define EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
-//EP_PCIE_F0_DPA_CNTL
-#define EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0
-#define EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8
-//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
-#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
-//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
-#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
-//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
-#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
-//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
-#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
-//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
-#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
-//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
-#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
-//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
-#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
-//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
-#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
-//EP_PCIE_PME_CONTROL
-#define EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0
-//EP_PCIEP_RESERVED
-#define EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
-//EP_PCIE_TX_CNTL
-#define EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
-#define EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
-#define EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18
-#define EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19
-#define EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a
-//EP_PCIE_TX_REQUESTER_ID
-#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
-#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
-#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
-//EP_PCIE_ERR_CNTL
-#define EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
-#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
-#define EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
-#define EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
-#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18
-#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19
-#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a
-#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b
-#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c
-#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d
-#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e
-#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f
-//EP_PCIE_RX_CNTL
-#define EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
-#define EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
-#define EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
-#define EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
-#define EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
-#define EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
-#define EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
-#define EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
-//EP_PCIE_LC_SPEED_CNTL
-#define EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
-#define EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
-
-
-// addressBlock: bif_bx_pf_BIFDEC1
-//BIF_MM_INDACCESS_CNTL
-#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
-//BUS_CNTL
-#define BUS_CNTL__PMI_INT_DIS_EP__SHIFT 0x3
-#define BUS_CNTL__PMI_INT_DIS_DN__SHIFT 0x4
-#define BUS_CNTL__PMI_INT_DIS_SWUS__SHIFT 0x5
-#define BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6
-#define BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7
-#define BUS_CNTL__SET_AZ_TC__SHIFT 0xa
-#define BUS_CNTL__SET_MC_TC__SHIFT 0xd
-#define BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10
-#define BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11
-#define BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12
-#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT 0x13
-#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT 0x14
-#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT 0x15
-#define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT 0x16
-#define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT 0x17
-#define BUS_CNTL__UR_OVRD_FOR_ECRC_EN__SHIFT 0x18
-//BIF_SCRATCH0
-#define BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0
-//BIF_SCRATCH1
-#define BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0
-//BX_RESET_EN
-#define BX_RESET_EN__COR_RESET_EN__SHIFT 0x0
-#define BX_RESET_EN__REG_RESET_EN__SHIFT 0x1
-#define BX_RESET_EN__STY_RESET_EN__SHIFT 0x2
-#define BX_RESET_EN__FLR_TWICE_EN__SHIFT 0x8
-#define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10
-//MM_CFGREGS_CNTL
-#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0
-#define MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6
-#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f
-//BX_RESET_CNTL
-#define BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0
-//INTERRUPT_CNTL
-#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0
-#define INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1
-#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3
-#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4
-#define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8
-#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf
-//INTERRUPT_CNTL2
-#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0
-//CLKREQB_PAD_CNTL
-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0
-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1
-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2
-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3
-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5
-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6
-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7
-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8
-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9
-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa
-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb
-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc
-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd
-#define CLKREQB_PAD_CNTL__CLKREQB_PERF_COUNTER_UPPER__SHIFT 0x18
-//CLKREQB_PERF_COUNTER
-#define CLKREQB_PERF_COUNTER__CLKREQB_PERF_COUNTER_LOWER__SHIFT 0x0
-//BIF_CLK_CTRL
-#define BIF_CLK_CTRL__BIF_XSTCLK_READY__SHIFT 0x0
-#define BIF_CLK_CTRL__BACO_XSTCLK_SWITCH_BYPASS__SHIFT 0x1
-//BIF_FEATURES_CONTROL_MISC
-#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0
-#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1
-#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2
-#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3
-#define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS__SHIFT 0x9
-#define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS__SHIFT 0xa
-#define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0xb
-#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc
-#define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd
-#define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf
-#define BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS__SHIFT 0x11
-#define BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS__SHIFT 0x12
-#define BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x18
-//BIF_DOORBELL_CNTL
-#define BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0
-#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1
-#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2
-#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3
-#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4
-#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18
-#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19
-#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a
-#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b
-//BIF_DOORBELL_INT_CNTL
-#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0
-#define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS__SHIFT 0x1
-#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10
-#define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR__SHIFT 0x11
-//BIF_SLVARB_MODE
-#define BIF_SLVARB_MODE__SLVARB_MODE__SHIFT 0x0
-//BIF_FB_EN
-#define BIF_FB_EN__FB_READ_EN__SHIFT 0x0
-#define BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1
-//BIF_BUSY_DELAY_CNTR
-#define BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x0
-//BIF_PERFMON_CNTL
-#define BIF_PERFMON_CNTL__PERFCOUNTER_EN__SHIFT 0x0
-#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0__SHIFT 0x1
-#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__SHIFT 0x2
-#define BIF_PERFMON_CNTL__PERF_SEL0__SHIFT 0x8
-#define BIF_PERFMON_CNTL__PERF_SEL1__SHIFT 0xd
-//BIF_PERFCOUNTER0_RESULT
-#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0
-//BIF_PERFCOUNTER1_RESULT
-#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0
-//BIF_MST_TRANS_PENDING_VF
-#define BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0
-//BIF_SLV_TRANS_PENDING_VF
-#define BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0
-//BACO_CNTL
-#define BACO_CNTL__BACO_EN__SHIFT 0x0
-#define BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT 0x1
-#define BACO_CNTL__BACO_DUMMY_EN__SHIFT 0x2
-#define BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3
-#define BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT 0x5
-#define BACO_CNTL__BACO_RST_INTR_MASK__SHIFT 0x6
-#define BACO_CNTL__BACO_MODE__SHIFT 0x8
-#define BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x9
-#define BACO_CNTL__BACO_AUTO_EXIT__SHIFT 0x1f
-//BIF_BACO_EXIT_TIME0
-#define BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT 0x0
-//BIF_BACO_EXIT_TIMER1
-#define BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT 0x0
-#define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT 0x1a
-#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT 0x1b
-#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT 0x1c
-#define BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT 0x1d
-#define BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT 0x1f
-//BIF_BACO_EXIT_TIMER2
-#define BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT 0x0
-//BIF_BACO_EXIT_TIMER3
-#define BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT 0x0
-//BIF_BACO_EXIT_TIMER4
-#define BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT 0x0
-//MEM_TYPE_CNTL
-#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0
-//SMU_BIF_VDDGFX_PWR_STATUS
-#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__SHIFT 0x0
-//BIF_VDDGFX_GFX0_LOWER
-#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT 0x2
-#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__SHIFT 0x1e
-#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__SHIFT 0x1f
-//BIF_VDDGFX_GFX0_UPPER
-#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT 0x2
-//BIF_VDDGFX_GFX1_LOWER
-#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT 0x2
-#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__SHIFT 0x1e
-#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__SHIFT 0x1f
-//BIF_VDDGFX_GFX1_UPPER
-#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT 0x2
-//BIF_VDDGFX_GFX2_LOWER
-#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT 0x2
-#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__SHIFT 0x1e
-#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__SHIFT 0x1f
-//BIF_VDDGFX_GFX2_UPPER
-#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT 0x2
-//BIF_VDDGFX_GFX3_LOWER
-#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT 0x2
-#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__SHIFT 0x1e
-#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__SHIFT 0x1f
-//BIF_VDDGFX_GFX3_UPPER
-#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT 0x2
-//BIF_VDDGFX_GFX4_LOWER
-#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT 0x2
-#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__SHIFT 0x1e
-#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__SHIFT 0x1f
-//BIF_VDDGFX_GFX4_UPPER
-#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2
-//BIF_VDDGFX_GFX5_LOWER
-#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT 0x2
-#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__SHIFT 0x1e
-#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__SHIFT 0x1f
-//BIF_VDDGFX_GFX5_UPPER
-#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT 0x2
-//BIF_VDDGFX_RSV1_LOWER
-#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT 0x2
-#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__SHIFT 0x1e
-#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__SHIFT 0x1f
-//BIF_VDDGFX_RSV1_UPPER
-#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT 0x2
-//BIF_VDDGFX_RSV2_LOWER
-#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT 0x2
-#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__SHIFT 0x1e
-#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__SHIFT 0x1f
-//BIF_VDDGFX_RSV2_UPPER
-#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT 0x2
-//BIF_VDDGFX_RSV3_LOWER
-#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT 0x2
-#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT 0x1e
-#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__SHIFT 0x1f
-//BIF_VDDGFX_RSV3_UPPER
-#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT 0x2
-//BIF_VDDGFX_RSV4_LOWER
-#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT 0x2
-#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__SHIFT 0x1e
-#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__SHIFT 0x1f
-//BIF_VDDGFX_RSV4_UPPER
-#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT 0x2
-//BIF_VDDGFX_FB_CMP
-#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__SHIFT 0x0
-#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__SHIFT 0x1
-#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x2
-#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__SHIFT 0x3
-#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__SHIFT 0x4
-#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__SHIFT 0x5
-//BIF_DOORBELL_GBLAPER1_LOWER
-#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT 0x2
-#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__SHIFT 0x1f
-//BIF_DOORBELL_GBLAPER1_UPPER
-#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT 0x2
-//BIF_DOORBELL_GBLAPER2_LOWER
-#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT 0x2
-#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__SHIFT 0x1f
-//BIF_DOORBELL_GBLAPER2_UPPER
-#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT 0x2
-//REMAP_HDP_MEM_FLUSH_CNTL
-#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2
-//REMAP_HDP_REG_FLUSH_CNTL
-#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2
-//BIF_RB_CNTL
-#define BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0
-#define BIF_RB_CNTL__RB_SIZE__SHIFT 0x1
-#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
-#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9
-#define BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11
-#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
-//BIF_RB_BASE
-#define BIF_RB_BASE__ADDR__SHIFT 0x0
-//BIF_RB_RPTR
-#define BIF_RB_RPTR__OFFSET__SHIFT 0x2
-//BIF_RB_WPTR
-#define BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0
-#define BIF_RB_WPTR__OFFSET__SHIFT 0x2
-//BIF_RB_WPTR_ADDR_HI
-#define BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0
-//BIF_RB_WPTR_ADDR_LO
-#define BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
-//MAILBOX_INDEX
-#define MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0
-//BIF_GPUIOV_RESET_NOTIFICATION
-#define BIF_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION__SHIFT 0x0
-//BIF_UVD_GPUIOV_CFG_SIZE
-#define BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE__SHIFT 0x0
-//BIF_VCE_GPUIOV_CFG_SIZE
-#define BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE__SHIFT 0x0
-//BIF_GFX_SDMA_GPUIOV_CFG_SIZE
-#define BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT 0x0
-//BIF_GMI_WRR_WEIGHT
-#define BIF_GMI_WRR_WEIGHT__GMI_REQ_REALTIME_WEIGHT__SHIFT 0x0
-#define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_P_WEIGHT__SHIFT 0x8
-#define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_NP_WEIGHT__SHIFT 0x10
-//NBIF_STRAP_WRITE_CTRL
-#define NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE__SHIFT 0x0
-//BIF_PERSTB_PAD_CNTL
-#define BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT 0x0
-//BIF_PX_EN_PAD_CNTL
-#define BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT 0x0
-//BIF_REFPADKIN_PAD_CNTL
-#define BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT 0x0
-//BIF_CLKREQB_PAD_CNTL
-#define BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT 0x0
-
-
-// addressBlock: rcc_pf_0_BIFDEC1
-//RCC_BACO_CNTL_MISC
-#define RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0
-#define RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1
-//RCC_RESET_EN
-#define RCC_RESET_EN__DB_APER_RESET_EN__SHIFT 0xf
-//RCC_VDM_SUPPORT
-#define RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0
-#define RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1
-#define RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2
-#define RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3
-#define RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4
-//RCC_PEER_REG_RANGE0
-#define RCC_PEER_REG_RANGE0__START_ADDR__SHIFT 0x0
-#define RCC_PEER_REG_RANGE0__END_ADDR__SHIFT 0x10
-//RCC_PEER_REG_RANGE1
-#define RCC_PEER_REG_RANGE1__START_ADDR__SHIFT 0x0
-#define RCC_PEER_REG_RANGE1__END_ADDR__SHIFT 0x10
-//RCC_BUS_CNTL
-#define RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2
-#define RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3
-#define RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4
-#define RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5
-#define RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6
-#define RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7
-#define RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8
-#define RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc
-#define RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd
-#define RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10
-#define RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11
-#define RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12
-#define RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13
-#define RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14
-#define RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15
-#define RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18
-#define RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19
-#define RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c
-#define RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d
-//RCC_CONFIG_CNTL
-#define RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0
-#define RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2
-#define RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3
-//RCC_CONFIG_F0_BASE
-#define RCC_CONFIG_F0_BASE__F0_BASE__SHIFT 0x0
-//RCC_CONFIG_APER_SIZE
-#define RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0
-//RCC_CONFIG_REG_APER_SIZE
-#define RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0
-//RCC_XDMA_LO
-#define RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0
-#define RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f
-//RCC_XDMA_HI
-#define RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0
-//RCC_FEATURES_CONTROL_MISC
-#define RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x4
-#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x5
-#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x6
-#define RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8
-#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9
-#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa
-#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb
-#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc
-#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd
-#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe
-#define RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT 0xf
-#define RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10
-#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11
-#define RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12
-//RCC_BUSNUM_CNTL1
-#define RCC_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0
-//RCC_BUSNUM_LIST0
-#define RCC_BUSNUM_LIST0__ID0__SHIFT 0x0
-#define RCC_BUSNUM_LIST0__ID1__SHIFT 0x8
-#define RCC_BUSNUM_LIST0__ID2__SHIFT 0x10
-#define RCC_BUSNUM_LIST0__ID3__SHIFT 0x18
-//RCC_BUSNUM_LIST1
-#define RCC_BUSNUM_LIST1__ID4__SHIFT 0x0
-#define RCC_BUSNUM_LIST1__ID5__SHIFT 0x8
-#define RCC_BUSNUM_LIST1__ID6__SHIFT 0x10
-#define RCC_BUSNUM_LIST1__ID7__SHIFT 0x18
-//RCC_BUSNUM_CNTL2
-#define RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0
-#define RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8
-#define RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10
-#define RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11
-//RCC_CAPTURE_HOST_BUSNUM
-#define RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0
-//RCC_HOST_BUSNUM
-#define RCC_HOST_BUSNUM__HOST_ID__SHIFT 0x0
-//RCC_PEER0_FB_OFFSET_HI
-#define RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0
-//RCC_PEER0_FB_OFFSET_LO
-#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0
-#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f
-//RCC_PEER1_FB_OFFSET_HI
-#define RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0
-//RCC_PEER1_FB_OFFSET_LO
-#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0
-#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f
-//RCC_PEER2_FB_OFFSET_HI
-#define RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0
-//RCC_PEER2_FB_OFFSET_LO
-#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0
-#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f
-//RCC_PEER3_FB_OFFSET_HI
-#define RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0
-//RCC_PEER3_FB_OFFSET_LO
-#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0
-#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f
-//RCC_DEVFUNCNUM_LIST0
-#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0
-#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8
-#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10
-#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18
-//RCC_DEVFUNCNUM_LIST1
-#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0
-#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8
-#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10
-#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18
-//RCC_DEV0_LINK_CNTL
-#define RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0
-#define RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8
-//RCC_CMN_LINK_CNTL
-#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0
-#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1
-#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2
-#define RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3
-//RCC_EP_REQUESTERID_RESTORE
-#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0
-#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8
-//RCC_LTR_LSWITCH_CNTL
-#define RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0
-//RCC_MH_ARB_CNTL
-#define RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0
-#define RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1
-
-
-// addressBlock: rcc_pf_0_BIFDEC2
-//GFXMSIX_VECT0_ADDR_LO
-#define GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
-//GFXMSIX_VECT0_ADDR_HI
-#define GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
-//GFXMSIX_VECT0_MSG_DATA
-#define GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
-//GFXMSIX_VECT0_CONTROL
-#define GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
-//GFXMSIX_VECT1_ADDR_LO
-#define GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
-//GFXMSIX_VECT1_ADDR_HI
-#define GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
-//GFXMSIX_VECT1_MSG_DATA
-#define GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
-//GFXMSIX_VECT1_CONTROL
-#define GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
-//GFXMSIX_VECT2_ADDR_LO
-#define GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
-//GFXMSIX_VECT2_ADDR_HI
-#define GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
-//GFXMSIX_VECT2_MSG_DATA
-#define GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
-//GFXMSIX_VECT2_CONTROL
-#define GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
-//GFXMSIX_PBA
-#define GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
-#define GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
-#define GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
-
-
-// addressBlock: rcc_strap_BIFDEC1
-//RCC_DEV0_PORT_STRAP0
-#define RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x1
-#define RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x2
-#define RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x3
-#define RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x4
-#define RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x5
-#define RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15
-#define RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18
-#define RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19
-#define RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c
-#define RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f
-//RCC_DEV0_PORT_STRAP1
-#define RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0
-#define RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10
-//RCC_DEV0_PORT_STRAP2
-#define RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0
-#define RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1
-#define RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2
-#define RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3
-#define RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4
-#define RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5
-#define RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT 0x6
-#define RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7
-#define RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8
-#define RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9
-#define RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc
-#define RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd
-#define RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe
-#define RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf
-#define RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10
-#define RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x11
-#define RCC_DEV0_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x13
-#define RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14
-#define RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17
-#define RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a
-#define RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d
-//RCC_DEV0_PORT_STRAP3
-#define RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0
-#define RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1
-#define RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2
-#define RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3
-#define RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6
-#define RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7
-#define RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8
-#define RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9
-#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb
-#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe
-#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12
-#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15
-#define RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19
-#define RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b
-#define RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d
-#define RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__SHIFT 0x1e
-#define RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f
-//RCC_DEV0_PORT_STRAP4
-#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0
-#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8
-#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10
-#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18
-//RCC_DEV0_PORT_STRAP5
-#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0
-#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8
-#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10
-#define RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11
-#define RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12
-#define RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13
-#define RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14
-#define RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15
-#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17
-#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18
-#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19
-#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a
-#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b
-#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c
-#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d
-#define RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT 0x1e
-#define RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f
-//RCC_DEV0_PORT_STRAP6
-#define RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0
-#define RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1
-//RCC_DEV0_PORT_STRAP7
-#define RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0
-#define RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8
-#define RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc
-#define RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10
-#define RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18
-#define RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d
-//RCC_DEV0_EPF0_STRAP0
-#define RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0
-#define RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10
-#define RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14
-#define RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18
-#define RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c
-#define RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d
-#define RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e
-#define RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f
-//RCC_DEV0_EPF0_STRAP1
-#define RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0
-#define RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10
-//RCC_DEV0_EPF0_STRAP13
-#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0
-#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8
-#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10
-//RCC_DEV0_EPF0_STRAP2
-#define RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0
-#define RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x1
-#define RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6
-#define RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7
-#define RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8
-#define RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9
-#define RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe
-#define RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf
-#define RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10
-#define RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11
-#define RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12
-#define RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14
-#define RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15
-#define RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16
-#define RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17
-#define RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18
-#define RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b
-#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c
-#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d
-#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e
-#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f
-//RCC_DEV0_EPF0_STRAP3
-#define RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x0
-#define RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x1
-#define RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x2
-#define RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12
-#define RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13
-#define RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14
-#define RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15
-#define RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18
-#define RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__SHIFT 0x19
-#define RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a
-#define RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b
-//RCC_DEV0_EPF0_STRAP4
-#define RCC_DEV0_EPF0_STRAP4__STRAP_MSIX_TABLE_OFFSET_DEV0_F0__SHIFT 0x0
-#define RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14
-#define RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15
-#define RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16
-#define RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17
-#define RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c
-#define RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT 0x1f
-//RCC_DEV0_EPF0_STRAP5
-#define RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0
-//RCC_DEV0_EPF0_STRAP8
-#define RCC_DEV0_EPF0_STRAP8__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x0
-#define RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x1
-#define RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3
-#define RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x4
-#define RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x5
-#define RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7
-#define RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8
-#define RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0x9
-#define RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xc
-#define RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0xe
-#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x10
-#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x13
-#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x16
-#define RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT 0x18
-#define RCC_DEV0_EPF0_STRAP8__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x19
-#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x1a
-#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b
-#define RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e
-//RCC_DEV0_EPF0_STRAP9
-//RCC_DEV0_EPF1_STRAP0
-#define RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0
-#define RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10
-#define RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14
-#define RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c
-#define RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d
-#define RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e
-#define RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f
-//RCC_DEV0_EPF1_STRAP10
-#define RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__SHIFT 0x0
-#define RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1
-//RCC_DEV0_EPF1_STRAP11
-#define RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__SHIFT 0x0
-#define RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1
-//RCC_DEV0_EPF1_STRAP12
-#define RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__SHIFT 0x0
-#define RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1
-//RCC_DEV0_EPF1_STRAP13
-#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT 0x0
-#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT 0x8
-#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT 0x10
-//RCC_DEV0_EPF1_STRAP2
-#define RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7
-#define RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8
-#define RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe
-#define RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10
-#define RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11
-#define RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT 0x12
-#define RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14
-#define RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15
-#define RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT 0x16
-#define RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT 0x17
-#define RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18
-//RCC_DEV0_EPF1_STRAP3
-#define RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x0
-#define RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x1
-#define RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x2
-#define RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12
-#define RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13
-#define RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14
-#define RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18
-#define RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__SHIFT 0x19
-#define RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a
-#define RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b
-//RCC_DEV0_EPF1_STRAP4
-#define RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14
-#define RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15
-#define RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16
-#define RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17
-#define RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c
-#define RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f
-//RCC_DEV0_EPF1_STRAP5
-#define RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0
-//RCC_DEV0_EPF1_STRAP6
-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT 0x0
-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x1
-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT 0x2
-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__SHIFT 0x4
-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__SHIFT 0x8
-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x9
-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__SHIFT 0x10
-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x11
-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__SHIFT 0x18
-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x19
-//RCC_DEV0_EPF1_STRAP7
-#define RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__SHIFT 0x0
-#define RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__SHIFT 0x1
-
-
-// addressBlock: bif_bx_pf_BIFPFVFDEC1
-//BIF_BME_STATUS
-#define BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
-#define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
-//BIF_ATOMIC_ERR_LOG
-#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
-#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
-#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
-#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
-//DOORBELL_SELFRING_GPA_APER_BASE_HIGH
-#define DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
-//DOORBELL_SELFRING_GPA_APER_BASE_LOW
-#define DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
-//DOORBELL_SELFRING_GPA_APER_CNTL
-#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
-#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
-//HDP_REG_COHERENCY_FLUSH_CNTL
-#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
-//HDP_MEM_COHERENCY_FLUSH_CNTL
-#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
-//GPU_HDP_FLUSH_REQ
-#define GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
-#define GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
-#define GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
-#define GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
-#define GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
-#define GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
-#define GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
-#define GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
-#define GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
-#define GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
-#define GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
-#define GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
-//GPU_HDP_FLUSH_DONE
-#define GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
-#define GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
-#define GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
-#define GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
-#define GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
-#define GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
-#define GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
-#define GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
-#define GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
-#define GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
-#define GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
-#define GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
-//BIF_TRANS_PENDING
-#define BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
-#define BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
-//MAILBOX_MSGBUF_TRN_DW0
-#define MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
-//MAILBOX_MSGBUF_TRN_DW1
-#define MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
-//MAILBOX_MSGBUF_TRN_DW2
-#define MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
-//MAILBOX_MSGBUF_TRN_DW3
-#define MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
-//MAILBOX_MSGBUF_RCV_DW0
-#define MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
-//MAILBOX_MSGBUF_RCV_DW1
-#define MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
-//MAILBOX_MSGBUF_RCV_DW2
-#define MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
-//MAILBOX_MSGBUF_RCV_DW3
-#define MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
-//MAILBOX_CONTROL
-#define MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
-#define MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
-#define MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
-#define MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
-//MAILBOX_INT_CNTL
-#define MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
-#define MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
-//BIF_VMHV_MAILBOX
-#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
-#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
-#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
-#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
-#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
-#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
-#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
-#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
-
-
-// addressBlock: rcc_pf_0_BIFPFVFDEC1
-//RCC_DOORBELL_APER_EN
-#define RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
-//RCC_CONFIG_MEMSIZE
-#define RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
-//RCC_CONFIG_RESERVED
-#define RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
-//RCC_IOV_FUNC_IDENTIFIER
-#define RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
-#define RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
-
-
-// addressBlock: syshub_mmreg_ind_syshubdec
-//SYSHUB_INDEX
-#define SYSHUB_INDEX__INDEX__SHIFT 0x0
-//SYSHUB_DATA
-#define SYSHUB_DATA__DATA__SHIFT 0x0
-
-
-// addressBlock: rcc_strap_rcc_strap_internal
-//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x1
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x2
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x3
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x4
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x5
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f
-//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10
-//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT 0x6
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x11
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x13
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d
-//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__SHIFT 0x1e
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f
-//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18
-//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT 0x1e
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f
-//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1
-//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d
-//RCC_DEV1_PORT_STRAP0
-#define RCC_DEV1_PORT_STRAP0__STRAP_ARI_EN_DN_DEV1__SHIFT 0x1
-#define RCC_DEV1_PORT_STRAP0__STRAP_ACS_EN_DN_DEV1__SHIFT 0x2
-#define RCC_DEV1_PORT_STRAP0__STRAP_AER_EN_DN_DEV1__SHIFT 0x3
-#define RCC_DEV1_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV1__SHIFT 0x4
-#define RCC_DEV1_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV1__SHIFT 0x5
-#define RCC_DEV1_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV1__SHIFT 0x15
-#define RCC_DEV1_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV1__SHIFT 0x18
-#define RCC_DEV1_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV1__SHIFT 0x19
-#define RCC_DEV1_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV1__SHIFT 0x1c
-#define RCC_DEV1_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV1__SHIFT 0x1f
-//RCC_DEV1_PORT_STRAP1
-#define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV1__SHIFT 0x0
-#define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV1__SHIFT 0x10
-//RCC_DEV1_PORT_STRAP2
-#define RCC_DEV1_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV1__SHIFT 0x0
-#define RCC_DEV1_PORT_STRAP2__STRAP_DSN_EN_DN_DEV1__SHIFT 0x1
-#define RCC_DEV1_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV1__SHIFT 0x2
-#define RCC_DEV1_PORT_STRAP2__STRAP_ECN1P1_EN_DEV1__SHIFT 0x3
-#define RCC_DEV1_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV1__SHIFT 0x4
-#define RCC_DEV1_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV1__SHIFT 0x5
-#define RCC_DEV1_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV1__SHIFT 0x6
-#define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV1__SHIFT 0x7
-#define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV1__SHIFT 0x8
-#define RCC_DEV1_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV1__SHIFT 0x9
-#define RCC_DEV1_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV1__SHIFT 0xc
-#define RCC_DEV1_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV1__SHIFT 0xd
-#define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV1__SHIFT 0xe
-#define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_EN_DEV1__SHIFT 0xf
-#define RCC_DEV1_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV1__SHIFT 0x10
-#define RCC_DEV1_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV1__SHIFT 0x11
-#define RCC_DEV1_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV1__SHIFT 0x13
-#define RCC_DEV1_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV1__SHIFT 0x14
-#define RCC_DEV1_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV1__SHIFT 0x17
-#define RCC_DEV1_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV1__SHIFT 0x1a
-#define RCC_DEV1_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV1__SHIFT 0x1d
-//RCC_DEV1_PORT_STRAP3
-#define RCC_DEV1_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV1__SHIFT 0x0
-#define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DEV1__SHIFT 0x1
-#define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DN_DEV1__SHIFT 0x2
-#define RCC_DEV1_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV1__SHIFT 0x3
-#define RCC_DEV1_PORT_STRAP3__STRAP_MSI_EN_DN_DEV1__SHIFT 0x6
-#define RCC_DEV1_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV1__SHIFT 0x7
-#define RCC_DEV1_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV1__SHIFT 0x8
-#define RCC_DEV1_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV1__SHIFT 0x9
-#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV1__SHIFT 0xb
-#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV1__SHIFT 0xe
-#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV1__SHIFT 0x12
-#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV1__SHIFT 0x15
-#define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DEV1__SHIFT 0x19
-#define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV1__SHIFT 0x1b
-#define RCC_DEV1_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV1__SHIFT 0x1d
-#define RCC_DEV1_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV1__SHIFT 0x1e
-#define RCC_DEV1_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV1__SHIFT 0x1f
-//RCC_DEV1_PORT_STRAP4
-#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV1__SHIFT 0x0
-#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV1__SHIFT 0x8
-#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV1__SHIFT 0x10
-#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV1__SHIFT 0x18
-//RCC_DEV1_PORT_STRAP5
-#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV1__SHIFT 0x0
-#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV1__SHIFT 0x8
-#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV1__SHIFT 0x10
-#define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV1__SHIFT 0x11
-#define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV1__SHIFT 0x12
-#define RCC_DEV1_PORT_STRAP5__STRAP_VC_EN_DN_DEV1__SHIFT 0x13
-#define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DEV1__SHIFT 0x14
-#define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV1__SHIFT 0x15
-#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV1__SHIFT 0x17
-#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV1__SHIFT 0x18
-#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV1__SHIFT 0x19
-#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV1__SHIFT 0x1a
-#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV1__SHIFT 0x1b
-#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV1__SHIFT 0x1c
-#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV1__SHIFT 0x1d
-#define RCC_DEV1_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV1__SHIFT 0x1e
-#define RCC_DEV1_PORT_STRAP5__STRAP_SSID_EN_DEV1__SHIFT 0x1f
-//RCC_DEV1_PORT_STRAP6
-#define RCC_DEV1_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV1__SHIFT 0x0
-#define RCC_DEV1_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV1__SHIFT 0x1
-//RCC_DEV1_PORT_STRAP7
-#define RCC_DEV1_PORT_STRAP7__STRAP_PORT_NUMBER_DEV1__SHIFT 0x0
-#define RCC_DEV1_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV1__SHIFT 0x8
-#define RCC_DEV1_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV1__SHIFT 0xc
-#define RCC_DEV1_PORT_STRAP7__STRAP_RP_BUSNUM_DEV1__SHIFT 0x10
-#define RCC_DEV1_PORT_STRAP7__STRAP_DN_DEVNUM_DEV1__SHIFT 0x18
-#define RCC_DEV1_PORT_STRAP7__STRAP_DN_FUNCID_DEV1__SHIFT 0x1d
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x1
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x0
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x1
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x2
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__SHIFT 0x19
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_MSIX_TABLE_OFFSET_DEV0_F0__SHIFT 0x0
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT 0x1f
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x0
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x1
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x4
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x5
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0x9
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xc
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0xe
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x10
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x13
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x16
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT 0x18
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x19
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x1a
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP9
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT 0x12
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT 0x16
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT 0x17
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x0
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x1
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x2
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__SHIFT 0x19
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT 0x0
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x1
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT 0x2
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__SHIFT 0x4
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__SHIFT 0x8
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x9
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__SHIFT 0x10
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x11
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__SHIFT 0x18
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x19
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__SHIFT 0x0
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__SHIFT 0x1
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__SHIFT 0x0
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__SHIFT 0x0
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__SHIFT 0x0
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT 0x0
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT 0x8
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT 0x10
-//RCC_DEV0_EPF2_STRAP0
-#define RCC_DEV0_EPF2_STRAP0__STRAP_DEVICE_ID_DEV0_F2__SHIFT 0x0
-#define RCC_DEV0_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F2__SHIFT 0x10
-#define RCC_DEV0_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV0_F2__SHIFT 0x14
-#define RCC_DEV0_EPF2_STRAP0__STRAP_FUNC_EN_DEV0_F2__SHIFT 0x1c
-#define RCC_DEV0_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2__SHIFT 0x1d
-#define RCC_DEV0_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV0_F2__SHIFT 0x1e
-#define RCC_DEV0_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV0_F2__SHIFT 0x1f
-//RCC_DEV0_EPF2_STRAP2
-#define RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2__SHIFT 0x7
-#define RCC_DEV0_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F2__SHIFT 0x8
-#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2__SHIFT 0xe
-#define RCC_DEV0_EPF2_STRAP2__STRAP_AER_EN_DEV0_F2__SHIFT 0x10
-#define RCC_DEV0_EPF2_STRAP2__STRAP_ACS_EN_DEV0_F2__SHIFT 0x11
-#define RCC_DEV0_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F2__SHIFT 0x14
-#define RCC_DEV0_EPF2_STRAP2__STRAP_DPA_EN_DEV0_F2__SHIFT 0x15
-#define RCC_DEV0_EPF2_STRAP2__STRAP_VC_EN_DEV0_F2__SHIFT 0x17
-#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F2__SHIFT 0x18
-//RCC_DEV0_EPF2_STRAP3
-#define RCC_DEV0_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2__SHIFT 0x0
-#define RCC_DEV0_EPF2_STRAP3__STRAP_PWR_EN_DEV0_F2__SHIFT 0x1
-#define RCC_DEV0_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV0_F2__SHIFT 0x2
-#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_EN_DEV0_F2__SHIFT 0x12
-#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F2__SHIFT 0x13
-#define RCC_DEV0_EPF2_STRAP3__STRAP_MSIX_EN_DEV0_F2__SHIFT 0x14
-#define RCC_DEV0_EPF2_STRAP3__STRAP_PMC_DSI_DEV0_F2__SHIFT 0x18
-#define RCC_DEV0_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F2__SHIFT 0x19
-#define RCC_DEV0_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2__SHIFT 0x1a
-#define RCC_DEV0_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2__SHIFT 0x1b
-//RCC_DEV0_EPF2_STRAP4
-#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F2__SHIFT 0x14
-#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV0_F2__SHIFT 0x15
-#define RCC_DEV0_EPF2_STRAP4__STRAP_FLR_EN_DEV0_F2__SHIFT 0x16
-#define RCC_DEV0_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV0_F2__SHIFT 0x17
-#define RCC_DEV0_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F2__SHIFT 0x1c
-#define RCC_DEV0_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F2__SHIFT 0x1f
-//RCC_DEV0_EPF2_STRAP5
-#define RCC_DEV0_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F2__SHIFT 0x0
-#define RCC_DEV0_EPF2_STRAP5__STRAP_SATAIDP_EN_DEV0_F2__SHIFT 0x18
-//RCC_DEV0_EPF2_STRAP6
-#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_EN_DEV0_F2__SHIFT 0x0
-#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F2__SHIFT 0x1
-#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F2__SHIFT 0x4
-#define RCC_DEV0_EPF2_STRAP6__STRAP_APER1_EN_DEV0_F2__SHIFT 0x8
-#define RCC_DEV0_EPF2_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F2__SHIFT 0x9
-//RCC_DEV0_EPF2_STRAP13
-#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F2__SHIFT 0x0
-#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F2__SHIFT 0x8
-#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F2__SHIFT 0x10
-//RCC_DEV0_EPF3_STRAP0
-#define RCC_DEV0_EPF3_STRAP0__STRAP_DEVICE_ID_DEV0_F3__SHIFT 0x0
-#define RCC_DEV0_EPF3_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F3__SHIFT 0x10
-#define RCC_DEV0_EPF3_STRAP0__STRAP_MINOR_REV_ID_DEV0_F3__SHIFT 0x14
-#define RCC_DEV0_EPF3_STRAP0__STRAP_FUNC_EN_DEV0_F3__SHIFT 0x1c
-#define RCC_DEV0_EPF3_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3__SHIFT 0x1d
-#define RCC_DEV0_EPF3_STRAP0__STRAP_D1_SUPPORT_DEV0_F3__SHIFT 0x1e
-#define RCC_DEV0_EPF3_STRAP0__STRAP_D2_SUPPORT_DEV0_F3__SHIFT 0x1f
-//RCC_DEV0_EPF3_STRAP2
-#define RCC_DEV0_EPF3_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F3__SHIFT 0x7
-#define RCC_DEV0_EPF3_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F3__SHIFT 0x8
-#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3__SHIFT 0xe
-#define RCC_DEV0_EPF3_STRAP2__STRAP_AER_EN_DEV0_F3__SHIFT 0x10
-#define RCC_DEV0_EPF3_STRAP2__STRAP_ACS_EN_DEV0_F3__SHIFT 0x11
-#define RCC_DEV0_EPF3_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F3__SHIFT 0x14
-#define RCC_DEV0_EPF3_STRAP2__STRAP_DPA_EN_DEV0_F3__SHIFT 0x15
-#define RCC_DEV0_EPF3_STRAP2__STRAP_VC_EN_DEV0_F3__SHIFT 0x17
-#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F3__SHIFT 0x18
-//RCC_DEV0_EPF3_STRAP3
-#define RCC_DEV0_EPF3_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3__SHIFT 0x0
-#define RCC_DEV0_EPF3_STRAP3__STRAP_PWR_EN_DEV0_F3__SHIFT 0x1
-#define RCC_DEV0_EPF3_STRAP3__STRAP_SUBSYS_ID_DEV0_F3__SHIFT 0x2
-#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_EN_DEV0_F3__SHIFT 0x12
-#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F3__SHIFT 0x13
-#define RCC_DEV0_EPF3_STRAP3__STRAP_MSIX_EN_DEV0_F3__SHIFT 0x14
-#define RCC_DEV0_EPF3_STRAP3__STRAP_PMC_DSI_DEV0_F3__SHIFT 0x18
-#define RCC_DEV0_EPF3_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F3__SHIFT 0x19
-#define RCC_DEV0_EPF3_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3__SHIFT 0x1a
-#define RCC_DEV0_EPF3_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3__SHIFT 0x1b
-//RCC_DEV0_EPF3_STRAP4
-#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F3__SHIFT 0x14
-#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_EN_DEV0_F3__SHIFT 0x15
-#define RCC_DEV0_EPF3_STRAP4__STRAP_FLR_EN_DEV0_F3__SHIFT 0x16
-#define RCC_DEV0_EPF3_STRAP4__STRAP_PME_SUPPORT_DEV0_F3__SHIFT 0x17
-#define RCC_DEV0_EPF3_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F3__SHIFT 0x1c
-#define RCC_DEV0_EPF3_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F3__SHIFT 0x1f
-//RCC_DEV0_EPF3_STRAP5
-#define RCC_DEV0_EPF3_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F3__SHIFT 0x0
-#define RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESEL_DEV0_F3__SHIFT 0x10
-#define RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESELD_DEV0_F3__SHIFT 0x14
-//RCC_DEV0_EPF3_STRAP6
-#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_EN_DEV0_F3__SHIFT 0x0
-#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F3__SHIFT 0x1
-#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F3__SHIFT 0x4
-//RCC_DEV0_EPF3_STRAP13
-#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F3__SHIFT 0x0
-#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F3__SHIFT 0x8
-#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F3__SHIFT 0x10
-//RCC_DEV0_EPF4_STRAP0
-#define RCC_DEV0_EPF4_STRAP0__STRAP_DEVICE_ID_DEV0_F4__SHIFT 0x0
-#define RCC_DEV0_EPF4_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F4__SHIFT 0x10
-#define RCC_DEV0_EPF4_STRAP0__STRAP_MINOR_REV_ID_DEV0_F4__SHIFT 0x14
-#define RCC_DEV0_EPF4_STRAP0__STRAP_FUNC_EN_DEV0_F4__SHIFT 0x1c
-#define RCC_DEV0_EPF4_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F4__SHIFT 0x1d
-#define RCC_DEV0_EPF4_STRAP0__STRAP_D1_SUPPORT_DEV0_F4__SHIFT 0x1e
-#define RCC_DEV0_EPF4_STRAP0__STRAP_D2_SUPPORT_DEV0_F4__SHIFT 0x1f
-//RCC_DEV0_EPF4_STRAP2
-#define RCC_DEV0_EPF4_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F4__SHIFT 0x7
-#define RCC_DEV0_EPF4_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F4__SHIFT 0x8
-#define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F4__SHIFT 0xe
-#define RCC_DEV0_EPF4_STRAP2__STRAP_AER_EN_DEV0_F4__SHIFT 0x10
-#define RCC_DEV0_EPF4_STRAP2__STRAP_ACS_EN_DEV0_F4__SHIFT 0x11
-#define RCC_DEV0_EPF4_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F4__SHIFT 0x14
-#define RCC_DEV0_EPF4_STRAP2__STRAP_DPA_EN_DEV0_F4__SHIFT 0x15
-#define RCC_DEV0_EPF4_STRAP2__STRAP_VC_EN_DEV0_F4__SHIFT 0x17
-#define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F4__SHIFT 0x18
-//RCC_DEV0_EPF4_STRAP3
-#define RCC_DEV0_EPF4_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F4__SHIFT 0x0
-#define RCC_DEV0_EPF4_STRAP3__STRAP_PWR_EN_DEV0_F4__SHIFT 0x1
-#define RCC_DEV0_EPF4_STRAP3__STRAP_SUBSYS_ID_DEV0_F4__SHIFT 0x2
-#define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_EN_DEV0_F4__SHIFT 0x12
-#define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F4__SHIFT 0x13
-#define RCC_DEV0_EPF4_STRAP3__STRAP_MSIX_EN_DEV0_F4__SHIFT 0x14
-#define RCC_DEV0_EPF4_STRAP3__STRAP_PMC_DSI_DEV0_F4__SHIFT 0x18
-#define RCC_DEV0_EPF4_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F4__SHIFT 0x19
-#define RCC_DEV0_EPF4_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F4__SHIFT 0x1a
-#define RCC_DEV0_EPF4_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F4__SHIFT 0x1b
-//RCC_DEV0_EPF4_STRAP4
-#define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F4__SHIFT 0x14
-#define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_EN_DEV0_F4__SHIFT 0x15
-#define RCC_DEV0_EPF4_STRAP4__STRAP_FLR_EN_DEV0_F4__SHIFT 0x16
-#define RCC_DEV0_EPF4_STRAP4__STRAP_PME_SUPPORT_DEV0_F4__SHIFT 0x17
-#define RCC_DEV0_EPF4_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F4__SHIFT 0x1c
-#define RCC_DEV0_EPF4_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F4__SHIFT 0x1f
-//RCC_DEV0_EPF4_STRAP5
-#define RCC_DEV0_EPF4_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F4__SHIFT 0x0
-#define RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESEL_DEV0_F4__SHIFT 0x10
-#define RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESELD_DEV0_F4__SHIFT 0x14
-//RCC_DEV0_EPF4_STRAP6
-#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_EN_DEV0_F4__SHIFT 0x0
-#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F4__SHIFT 0x1
-#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F4__SHIFT 0x4
-#define RCC_DEV0_EPF4_STRAP6__STRAP_APER1_EN_DEV0_F4__SHIFT 0x8
-#define RCC_DEV0_EPF4_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F4__SHIFT 0x9
-#define RCC_DEV0_EPF4_STRAP6__STRAP_APER2_EN_DEV0_F4__SHIFT 0x10
-#define RCC_DEV0_EPF4_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F4__SHIFT 0x11
-//RCC_DEV0_EPF4_STRAP13
-#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F4__SHIFT 0x0
-#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F4__SHIFT 0x8
-#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F4__SHIFT 0x10
-//RCC_DEV0_EPF5_STRAP0
-#define RCC_DEV0_EPF5_STRAP0__STRAP_DEVICE_ID_DEV0_F5__SHIFT 0x0
-#define RCC_DEV0_EPF5_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F5__SHIFT 0x10
-#define RCC_DEV0_EPF5_STRAP0__STRAP_MINOR_REV_ID_DEV0_F5__SHIFT 0x14
-#define RCC_DEV0_EPF5_STRAP0__STRAP_FUNC_EN_DEV0_F5__SHIFT 0x1c
-#define RCC_DEV0_EPF5_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F5__SHIFT 0x1d
-#define RCC_DEV0_EPF5_STRAP0__STRAP_D1_SUPPORT_DEV0_F5__SHIFT 0x1e
-#define RCC_DEV0_EPF5_STRAP0__STRAP_D2_SUPPORT_DEV0_F5__SHIFT 0x1f
-//RCC_DEV0_EPF5_STRAP2
-#define RCC_DEV0_EPF5_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F5__SHIFT 0x7
-#define RCC_DEV0_EPF5_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F5__SHIFT 0x8
-#define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F5__SHIFT 0xe
-#define RCC_DEV0_EPF5_STRAP2__STRAP_AER_EN_DEV0_F5__SHIFT 0x10
-#define RCC_DEV0_EPF5_STRAP2__STRAP_ACS_EN_DEV0_F5__SHIFT 0x11
-#define RCC_DEV0_EPF5_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F5__SHIFT 0x14
-#define RCC_DEV0_EPF5_STRAP2__STRAP_DPA_EN_DEV0_F5__SHIFT 0x15
-#define RCC_DEV0_EPF5_STRAP2__STRAP_VC_EN_DEV0_F5__SHIFT 0x17
-#define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F5__SHIFT 0x18
-//RCC_DEV0_EPF5_STRAP3
-#define RCC_DEV0_EPF5_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F5__SHIFT 0x0
-#define RCC_DEV0_EPF5_STRAP3__STRAP_PWR_EN_DEV0_F5__SHIFT 0x1
-#define RCC_DEV0_EPF5_STRAP3__STRAP_SUBSYS_ID_DEV0_F5__SHIFT 0x2
-#define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_EN_DEV0_F5__SHIFT 0x12
-#define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F5__SHIFT 0x13
-#define RCC_DEV0_EPF5_STRAP3__STRAP_MSIX_EN_DEV0_F5__SHIFT 0x14
-#define RCC_DEV0_EPF5_STRAP3__STRAP_PMC_DSI_DEV0_F5__SHIFT 0x18
-#define RCC_DEV0_EPF5_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F5__SHIFT 0x19
-#define RCC_DEV0_EPF5_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F5__SHIFT 0x1a
-#define RCC_DEV0_EPF5_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F5__SHIFT 0x1b
-//RCC_DEV0_EPF5_STRAP4
-#define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F5__SHIFT 0x14
-#define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_EN_DEV0_F5__SHIFT 0x15
-#define RCC_DEV0_EPF5_STRAP4__STRAP_FLR_EN_DEV0_F5__SHIFT 0x16
-#define RCC_DEV0_EPF5_STRAP4__STRAP_PME_SUPPORT_DEV0_F5__SHIFT 0x17
-#define RCC_DEV0_EPF5_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F5__SHIFT 0x1c
-#define RCC_DEV0_EPF5_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F5__SHIFT 0x1f
-//RCC_DEV0_EPF5_STRAP5
-#define RCC_DEV0_EPF5_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F5__SHIFT 0x0
-//RCC_DEV0_EPF5_STRAP6
-#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_EN_DEV0_F5__SHIFT 0x0
-#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F5__SHIFT 0x1
-#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F5__SHIFT 0x4
-#define RCC_DEV0_EPF5_STRAP6__STRAP_APER1_EN_DEV0_F5__SHIFT 0x8
-#define RCC_DEV0_EPF5_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F5__SHIFT 0x9
-#define RCC_DEV0_EPF5_STRAP6__STRAP_APER2_EN_DEV0_F5__SHIFT 0x10
-#define RCC_DEV0_EPF5_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F5__SHIFT 0x11
-//RCC_DEV0_EPF5_STRAP13
-#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F5__SHIFT 0x0
-#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F5__SHIFT 0x8
-#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F5__SHIFT 0x10
-//RCC_DEV0_EPF6_STRAP0
-#define RCC_DEV0_EPF6_STRAP0__STRAP_DEVICE_ID_DEV0_F6__SHIFT 0x0
-#define RCC_DEV0_EPF6_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F6__SHIFT 0x10
-#define RCC_DEV0_EPF6_STRAP0__STRAP_MINOR_REV_ID_DEV0_F6__SHIFT 0x14
-#define RCC_DEV0_EPF6_STRAP0__STRAP_FUNC_EN_DEV0_F6__SHIFT 0x1c
-#define RCC_DEV0_EPF6_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F6__SHIFT 0x1d
-#define RCC_DEV0_EPF6_STRAP0__STRAP_D1_SUPPORT_DEV0_F6__SHIFT 0x1e
-#define RCC_DEV0_EPF6_STRAP0__STRAP_D2_SUPPORT_DEV0_F6__SHIFT 0x1f
-//RCC_DEV0_EPF6_STRAP2
-#define RCC_DEV0_EPF6_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F6__SHIFT 0x7
-#define RCC_DEV0_EPF6_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F6__SHIFT 0x8
-#define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F6__SHIFT 0xe
-#define RCC_DEV0_EPF6_STRAP2__STRAP_AER_EN_DEV0_F6__SHIFT 0x10
-#define RCC_DEV0_EPF6_STRAP2__STRAP_ACS_EN_DEV0_F6__SHIFT 0x11
-#define RCC_DEV0_EPF6_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F6__SHIFT 0x14
-#define RCC_DEV0_EPF6_STRAP2__STRAP_DPA_EN_DEV0_F6__SHIFT 0x15
-#define RCC_DEV0_EPF6_STRAP2__STRAP_VC_EN_DEV0_F6__SHIFT 0x17
-#define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F6__SHIFT 0x18
-//RCC_DEV0_EPF6_STRAP3
-#define RCC_DEV0_EPF6_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F6__SHIFT 0x0
-#define RCC_DEV0_EPF6_STRAP3__STRAP_PWR_EN_DEV0_F6__SHIFT 0x1
-#define RCC_DEV0_EPF6_STRAP3__STRAP_SUBSYS_ID_DEV0_F6__SHIFT 0x2
-#define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_EN_DEV0_F6__SHIFT 0x12
-#define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F6__SHIFT 0x13
-#define RCC_DEV0_EPF6_STRAP3__STRAP_MSIX_EN_DEV0_F6__SHIFT 0x14
-#define RCC_DEV0_EPF6_STRAP3__STRAP_PMC_DSI_DEV0_F6__SHIFT 0x18
-#define RCC_DEV0_EPF6_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F6__SHIFT 0x19
-#define RCC_DEV0_EPF6_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F6__SHIFT 0x1a
-#define RCC_DEV0_EPF6_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F6__SHIFT 0x1b
-//RCC_DEV0_EPF6_STRAP4
-#define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F6__SHIFT 0x14
-#define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_EN_DEV0_F6__SHIFT 0x15
-#define RCC_DEV0_EPF6_STRAP4__STRAP_FLR_EN_DEV0_F6__SHIFT 0x16
-#define RCC_DEV0_EPF6_STRAP4__STRAP_PME_SUPPORT_DEV0_F6__SHIFT 0x17
-#define RCC_DEV0_EPF6_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F6__SHIFT 0x1c
-#define RCC_DEV0_EPF6_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F6__SHIFT 0x1f
-//RCC_DEV0_EPF6_STRAP5
-#define RCC_DEV0_EPF6_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F6__SHIFT 0x0
-//RCC_DEV0_EPF6_STRAP6
-#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_EN_DEV0_F6__SHIFT 0x0
-#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F6__SHIFT 0x1
-#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F6__SHIFT 0x4
-#define RCC_DEV0_EPF6_STRAP6__STRAP_APER1_EN_DEV0_F6__SHIFT 0x8
-#define RCC_DEV0_EPF6_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F6__SHIFT 0x9
-#define RCC_DEV0_EPF6_STRAP6__STRAP_APER2_EN_DEV0_F6__SHIFT 0x10
-#define RCC_DEV0_EPF6_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F6__SHIFT 0x11
-//RCC_DEV0_EPF6_STRAP13
-#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F6__SHIFT 0x0
-#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F6__SHIFT 0x8
-#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F6__SHIFT 0x10
-//RCC_DEV0_EPF7_STRAP0
-#define RCC_DEV0_EPF7_STRAP0__STRAP_DEVICE_ID_DEV0_F7__SHIFT 0x0
-#define RCC_DEV0_EPF7_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F7__SHIFT 0x10
-#define RCC_DEV0_EPF7_STRAP0__STRAP_MINOR_REV_ID_DEV0_F7__SHIFT 0x14
-#define RCC_DEV0_EPF7_STRAP0__STRAP_FUNC_EN_DEV0_F7__SHIFT 0x1c
-#define RCC_DEV0_EPF7_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F7__SHIFT 0x1d
-#define RCC_DEV0_EPF7_STRAP0__STRAP_D1_SUPPORT_DEV0_F7__SHIFT 0x1e
-#define RCC_DEV0_EPF7_STRAP0__STRAP_D2_SUPPORT_DEV0_F7__SHIFT 0x1f
-//RCC_DEV0_EPF7_STRAP2
-#define RCC_DEV0_EPF7_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F7__SHIFT 0x7
-#define RCC_DEV0_EPF7_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F7__SHIFT 0x8
-#define RCC_DEV0_EPF7_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F7__SHIFT 0xe
-#define RCC_DEV0_EPF7_STRAP2__STRAP_AER_EN_DEV0_F7__SHIFT 0x10
-#define RCC_DEV0_EPF7_STRAP2__STRAP_ACS_EN_DEV0_F7__SHIFT 0x11
-#define RCC_DEV0_EPF7_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F7__SHIFT 0x14
-#define RCC_DEV0_EPF7_STRAP2__STRAP_DPA_EN_DEV0_F7__SHIFT 0x15
-#define RCC_DEV0_EPF7_STRAP2__STRAP_VC_EN_DEV0_F7__SHIFT 0x17
-#define RCC_DEV0_EPF7_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F7__SHIFT 0x18
-//RCC_DEV0_EPF7_STRAP3
-#define RCC_DEV0_EPF7_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F7__SHIFT 0x0
-#define RCC_DEV0_EPF7_STRAP3__STRAP_PWR_EN_DEV0_F7__SHIFT 0x1
-#define RCC_DEV0_EPF7_STRAP3__STRAP_SUBSYS_ID_DEV0_F7__SHIFT 0x2
-#define RCC_DEV0_EPF7_STRAP3__STRAP_MSI_EN_DEV0_F7__SHIFT 0x12
-#define RCC_DEV0_EPF7_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F7__SHIFT 0x13
-#define RCC_DEV0_EPF7_STRAP3__STRAP_MSIX_EN_DEV0_F7__SHIFT 0x14
-#define RCC_DEV0_EPF7_STRAP3__STRAP_PMC_DSI_DEV0_F7__SHIFT 0x18
-#define RCC_DEV0_EPF7_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F7__SHIFT 0x19
-#define RCC_DEV0_EPF7_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F7__SHIFT 0x1a
-#define RCC_DEV0_EPF7_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F7__SHIFT 0x1b
-//RCC_DEV0_EPF7_STRAP4
-#define RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F7__SHIFT 0x14
-#define RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_EN_DEV0_F7__SHIFT 0x15
-#define RCC_DEV0_EPF7_STRAP4__STRAP_FLR_EN_DEV0_F7__SHIFT 0x16
-#define RCC_DEV0_EPF7_STRAP4__STRAP_PME_SUPPORT_DEV0_F7__SHIFT 0x17
-#define RCC_DEV0_EPF7_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F7__SHIFT 0x1c
-#define RCC_DEV0_EPF7_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F7__SHIFT 0x1f
-//RCC_DEV0_EPF7_STRAP5
-#define RCC_DEV0_EPF7_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F7__SHIFT 0x0
-//RCC_DEV0_EPF7_STRAP6
-#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_EN_DEV0_F7__SHIFT 0x0
-#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F7__SHIFT 0x1
-#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F7__SHIFT 0x4
-#define RCC_DEV0_EPF7_STRAP6__STRAP_APER1_EN_DEV0_F7__SHIFT 0x8
-#define RCC_DEV0_EPF7_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F7__SHIFT 0x9
-#define RCC_DEV0_EPF7_STRAP6__STRAP_APER2_EN_DEV0_F7__SHIFT 0x10
-#define RCC_DEV0_EPF7_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F7__SHIFT 0x11
-//RCC_DEV0_EPF7_STRAP13
-#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F7__SHIFT 0x0
-#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F7__SHIFT 0x8
-#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F7__SHIFT 0x10
-//RCC_DEV1_EPF0_STRAP0
-#define RCC_DEV1_EPF0_STRAP0__STRAP_DEVICE_ID_DEV1_F0__SHIFT 0x0
-#define RCC_DEV1_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F0__SHIFT 0x10
-#define RCC_DEV1_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV1_F0__SHIFT 0x14
-#define RCC_DEV1_EPF0_STRAP0__STRAP_FUNC_EN_DEV1_F0__SHIFT 0x1c
-#define RCC_DEV1_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F0__SHIFT 0x1d
-#define RCC_DEV1_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV1_F0__SHIFT 0x1e
-#define RCC_DEV1_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV1_F0__SHIFT 0x1f
-//RCC_DEV1_EPF0_STRAP2
-#define RCC_DEV1_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F0__SHIFT 0x7
-#define RCC_DEV1_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F0__SHIFT 0x8
-#define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F0__SHIFT 0xe
-#define RCC_DEV1_EPF0_STRAP2__STRAP_ARI_EN_DEV1_F0__SHIFT 0xf
-#define RCC_DEV1_EPF0_STRAP2__STRAP_AER_EN_DEV1_F0__SHIFT 0x10
-#define RCC_DEV1_EPF0_STRAP2__STRAP_ACS_EN_DEV1_F0__SHIFT 0x11
-#define RCC_DEV1_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F0__SHIFT 0x14
-#define RCC_DEV1_EPF0_STRAP2__STRAP_DPA_EN_DEV1_F0__SHIFT 0x15
-#define RCC_DEV1_EPF0_STRAP2__STRAP_VC_EN_DEV1_F0__SHIFT 0x17
-#define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F0__SHIFT 0x18
-//RCC_DEV1_EPF0_STRAP3
-#define RCC_DEV1_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F0__SHIFT 0x0
-#define RCC_DEV1_EPF0_STRAP3__STRAP_PWR_EN_DEV1_F0__SHIFT 0x1
-#define RCC_DEV1_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV1_F0__SHIFT 0x2
-#define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_EN_DEV1_F0__SHIFT 0x12
-#define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F0__SHIFT 0x13
-#define RCC_DEV1_EPF0_STRAP3__STRAP_MSIX_EN_DEV1_F0__SHIFT 0x14
-#define RCC_DEV1_EPF0_STRAP3__STRAP_PMC_DSI_DEV1_F0__SHIFT 0x18
-#define RCC_DEV1_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F0__SHIFT 0x19
-#define RCC_DEV1_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F0__SHIFT 0x1a
-#define RCC_DEV1_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F0__SHIFT 0x1b
-//RCC_DEV1_EPF0_STRAP4
-#define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F0__SHIFT 0x14
-#define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV1_F0__SHIFT 0x15
-#define RCC_DEV1_EPF0_STRAP4__STRAP_FLR_EN_DEV1_F0__SHIFT 0x16
-#define RCC_DEV1_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV1_F0__SHIFT 0x17
-#define RCC_DEV1_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F0__SHIFT 0x1c
-#define RCC_DEV1_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F0__SHIFT 0x1f
-//RCC_DEV1_EPF0_STRAP5
-#define RCC_DEV1_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F0__SHIFT 0x0
-#define RCC_DEV1_EPF0_STRAP5__STRAP_SATAIDP_EN_DEV1_F0__SHIFT 0x18
-//RCC_DEV1_EPF0_STRAP6
-#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_EN_DEV1_F0__SHIFT 0x0
-#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F0__SHIFT 0x1
-#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F0__SHIFT 0x4
-//RCC_DEV1_EPF0_STRAP13
-#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F0__SHIFT 0x0
-#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F0__SHIFT 0x8
-#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F0__SHIFT 0x10
-//RCC_DEV1_EPF1_STRAP0
-#define RCC_DEV1_EPF1_STRAP0__STRAP_DEVICE_ID_DEV1_F1__SHIFT 0x0
-#define RCC_DEV1_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F1__SHIFT 0x10
-#define RCC_DEV1_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV1_F1__SHIFT 0x14
-#define RCC_DEV1_EPF1_STRAP0__STRAP_FUNC_EN_DEV1_F1__SHIFT 0x1c
-#define RCC_DEV1_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F1__SHIFT 0x1d
-#define RCC_DEV1_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV1_F1__SHIFT 0x1e
-#define RCC_DEV1_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV1_F1__SHIFT 0x1f
-//RCC_DEV1_EPF1_STRAP2
-#define RCC_DEV1_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F1__SHIFT 0x7
-#define RCC_DEV1_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F1__SHIFT 0x8
-#define RCC_DEV1_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F1__SHIFT 0xe
-#define RCC_DEV1_EPF1_STRAP2__STRAP_AER_EN_DEV1_F1__SHIFT 0x10
-#define RCC_DEV1_EPF1_STRAP2__STRAP_ACS_EN_DEV1_F1__SHIFT 0x11
-#define RCC_DEV1_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F1__SHIFT 0x14
-#define RCC_DEV1_EPF1_STRAP2__STRAP_DPA_EN_DEV1_F1__SHIFT 0x15
-#define RCC_DEV1_EPF1_STRAP2__STRAP_VC_EN_DEV1_F1__SHIFT 0x17
-#define RCC_DEV1_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F1__SHIFT 0x18
-//RCC_DEV1_EPF1_STRAP3
-#define RCC_DEV1_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F1__SHIFT 0x0
-#define RCC_DEV1_EPF1_STRAP3__STRAP_PWR_EN_DEV1_F1__SHIFT 0x1
-#define RCC_DEV1_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV1_F1__SHIFT 0x2
-#define RCC_DEV1_EPF1_STRAP3__STRAP_MSI_EN_DEV1_F1__SHIFT 0x12
-#define RCC_DEV1_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F1__SHIFT 0x13
-#define RCC_DEV1_EPF1_STRAP3__STRAP_MSIX_EN_DEV1_F1__SHIFT 0x14
-#define RCC_DEV1_EPF1_STRAP3__STRAP_PMC_DSI_DEV1_F1__SHIFT 0x18
-#define RCC_DEV1_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F1__SHIFT 0x19
-#define RCC_DEV1_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F1__SHIFT 0x1a
-#define RCC_DEV1_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F1__SHIFT 0x1b
-//RCC_DEV1_EPF1_STRAP4
-#define RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F1__SHIFT 0x14
-#define RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV1_F1__SHIFT 0x15
-#define RCC_DEV1_EPF1_STRAP4__STRAP_FLR_EN_DEV1_F1__SHIFT 0x16
-#define RCC_DEV1_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV1_F1__SHIFT 0x17
-#define RCC_DEV1_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F1__SHIFT 0x1c
-#define RCC_DEV1_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F1__SHIFT 0x1f
-//RCC_DEV1_EPF1_STRAP5
-#define RCC_DEV1_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F1__SHIFT 0x0
-//RCC_DEV1_EPF1_STRAP6
-#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_EN_DEV1_F1__SHIFT 0x0
-#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F1__SHIFT 0x1
-#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F1__SHIFT 0x4
-#define RCC_DEV1_EPF1_STRAP6__STRAP_APER1_EN_DEV1_F1__SHIFT 0x8
-#define RCC_DEV1_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV1_F1__SHIFT 0x9
-#define RCC_DEV1_EPF1_STRAP6__STRAP_APER2_EN_DEV1_F1__SHIFT 0x10
-#define RCC_DEV1_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV1_F1__SHIFT 0x11
-#define RCC_DEV1_EPF1_STRAP6__STRAP_APER3_EN_DEV1_F1__SHIFT 0x18
-#define RCC_DEV1_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV1_F1__SHIFT 0x19
-//RCC_DEV1_EPF1_STRAP13
-#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F1__SHIFT 0x0
-#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F1__SHIFT 0x8
-#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F1__SHIFT 0x10
-//RCC_DEV1_EPF2_STRAP0
-#define RCC_DEV1_EPF2_STRAP0__STRAP_DEVICE_ID_DEV1_F2__SHIFT 0x0
-#define RCC_DEV1_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F2__SHIFT 0x10
-#define RCC_DEV1_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV1_F2__SHIFT 0x14
-#define RCC_DEV1_EPF2_STRAP0__STRAP_FUNC_EN_DEV1_F2__SHIFT 0x1c
-#define RCC_DEV1_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F2__SHIFT 0x1d
-#define RCC_DEV1_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV1_F2__SHIFT 0x1e
-#define RCC_DEV1_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV1_F2__SHIFT 0x1f
-//RCC_DEV1_EPF2_STRAP2
-#define RCC_DEV1_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F2__SHIFT 0x7
-#define RCC_DEV1_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F2__SHIFT 0x8
-#define RCC_DEV1_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F2__SHIFT 0xe
-#define RCC_DEV1_EPF2_STRAP2__STRAP_AER_EN_DEV1_F2__SHIFT 0x10
-#define RCC_DEV1_EPF2_STRAP2__STRAP_ACS_EN_DEV1_F2__SHIFT 0x11
-#define RCC_DEV1_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F2__SHIFT 0x14
-#define RCC_DEV1_EPF2_STRAP2__STRAP_DPA_EN_DEV1_F2__SHIFT 0x15
-#define RCC_DEV1_EPF2_STRAP2__STRAP_VC_EN_DEV1_F2__SHIFT 0x17
-#define RCC_DEV1_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F2__SHIFT 0x18
-//RCC_DEV1_EPF2_STRAP3
-#define RCC_DEV1_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F2__SHIFT 0x0
-#define RCC_DEV1_EPF2_STRAP3__STRAP_PWR_EN_DEV1_F2__SHIFT 0x1
-#define RCC_DEV1_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV1_F2__SHIFT 0x2
-#define RCC_DEV1_EPF2_STRAP3__STRAP_MSI_EN_DEV1_F2__SHIFT 0x12
-#define RCC_DEV1_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F2__SHIFT 0x13
-#define RCC_DEV1_EPF2_STRAP3__STRAP_MSIX_EN_DEV1_F2__SHIFT 0x14
-#define RCC_DEV1_EPF2_STRAP3__STRAP_PMC_DSI_DEV1_F2__SHIFT 0x18
-#define RCC_DEV1_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F2__SHIFT 0x19
-#define RCC_DEV1_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F2__SHIFT 0x1a
-#define RCC_DEV1_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F2__SHIFT 0x1b
-//RCC_DEV1_EPF2_STRAP4
-#define RCC_DEV1_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F2__SHIFT 0x14
-#define RCC_DEV1_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV1_F2__SHIFT 0x15
-#define RCC_DEV1_EPF2_STRAP4__STRAP_FLR_EN_DEV1_F2__SHIFT 0x16
-#define RCC_DEV1_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV1_F2__SHIFT 0x17
-#define RCC_DEV1_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F2__SHIFT 0x1c
-#define RCC_DEV1_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F2__SHIFT 0x1f
-//RCC_DEV1_EPF2_STRAP5
-#define RCC_DEV1_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F2__SHIFT 0x0
-//RCC_DEV1_EPF2_STRAP6
-#define RCC_DEV1_EPF2_STRAP6__STRAP_APER0_EN_DEV1_F2__SHIFT 0x0
-#define RCC_DEV1_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F2__SHIFT 0x1
-#define RCC_DEV1_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F2__SHIFT 0x4
-#define RCC_DEV1_EPF2_STRAP6__STRAP_APER1_EN_DEV1_F2__SHIFT 0x8
-#define RCC_DEV1_EPF2_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV1_F2__SHIFT 0x9
-#define RCC_DEV1_EPF2_STRAP6__STRAP_APER2_EN_DEV1_F2__SHIFT 0x10
-#define RCC_DEV1_EPF2_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV1_F2__SHIFT 0x11
-#define RCC_DEV1_EPF2_STRAP6__STRAP_APER3_EN_DEV1_F2__SHIFT 0x18
-#define RCC_DEV1_EPF2_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV1_F2__SHIFT 0x19
-//RCC_DEV1_EPF2_STRAP13
-#define RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F2__SHIFT 0x0
-#define RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F2__SHIFT 0x8
-#define RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F2__SHIFT 0x10
-
-
-// addressBlock: bif_rst_bif_rst_regblk
-//HARD_RST_CTRL
-#define HARD_RST_CTRL__DSPT_CFG_RST_EN__SHIFT 0x0
-#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT 0x1
-#define HARD_RST_CTRL__DSPT_PRV_RST_EN__SHIFT 0x2
-#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT 0x3
-#define HARD_RST_CTRL__EP_CFG_RST_EN__SHIFT 0x4
-#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT 0x5
-#define HARD_RST_CTRL__EP_PRV_RST_EN__SHIFT 0x6
-#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT 0x7
-#define HARD_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT 0x1c
-#define HARD_RST_CTRL__CORE_STICKY_RST_EN__SHIFT 0x1d
-#define HARD_RST_CTRL__RELOAD_STRAP_EN__SHIFT 0x1e
-#define HARD_RST_CTRL__CORE_RST_EN__SHIFT 0x1f
-//RSMU_SOFT_RST_CTRL
-#define RSMU_SOFT_RST_CTRL__DSPT_CFG_RST_EN__SHIFT 0x0
-#define RSMU_SOFT_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT 0x1
-#define RSMU_SOFT_RST_CTRL__DSPT_PRV_RST_EN__SHIFT 0x2
-#define RSMU_SOFT_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT 0x3
-#define RSMU_SOFT_RST_CTRL__EP_CFG_RST_EN__SHIFT 0x4
-#define RSMU_SOFT_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT 0x5
-#define RSMU_SOFT_RST_CTRL__EP_PRV_RST_EN__SHIFT 0x6
-#define RSMU_SOFT_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT 0x7
-#define RSMU_SOFT_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT 0x1c
-#define RSMU_SOFT_RST_CTRL__CORE_STICKY_RST_EN__SHIFT 0x1d
-#define RSMU_SOFT_RST_CTRL__RELOAD_STRAP_EN__SHIFT 0x1e
-#define RSMU_SOFT_RST_CTRL__CORE_RST_EN__SHIFT 0x1f
-//SELF_SOFT_RST
-#define SELF_SOFT_RST__DSPT0_CFG_RST__SHIFT 0x0
-#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST__SHIFT 0x1
-#define SELF_SOFT_RST__DSPT0_PRV_RST__SHIFT 0x2
-#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST__SHIFT 0x3
-#define SELF_SOFT_RST__EP0_CFG_RST__SHIFT 0x4
-#define SELF_SOFT_RST__EP0_CFG_STICKY_RST__SHIFT 0x5
-#define SELF_SOFT_RST__EP0_PRV_RST__SHIFT 0x6
-#define SELF_SOFT_RST__EP0_PRV_STICKY_RST__SHIFT 0x7
-#define SELF_SOFT_RST__SDP_PORT_RST__SHIFT 0x1b
-#define SELF_SOFT_RST__SWUS_SHADOW_RST__SHIFT 0x1c
-#define SELF_SOFT_RST__CORE_STICKY_RST__SHIFT 0x1d
-#define SELF_SOFT_RST__RELOAD_STRAP__SHIFT 0x1e
-#define SELF_SOFT_RST__CORE_RST__SHIFT 0x1f
-//GFX_DRV_MODE1_RST_CTRL
-#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_RST__SHIFT 0x0
-#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_FLR_EXC_RST__SHIFT 0x1
-#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_STICKY_RST__SHIFT 0x2
-#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_PRV_RST__SHIFT 0x3
-#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_PRV_STICKY_RST__SHIFT 0x4
-#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_CFG_RST__SHIFT 0x5
-#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_CFG_STICKY_RST__SHIFT 0x6
-#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_PRV_RST__SHIFT 0x7
-//BIF_RST_MISC_CTRL
-#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__SHIFT 0x0
-#define BIF_RST_MISC_CTRL__DRV_RST_MODE__SHIFT 0x2
-#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__SHIFT 0x4
-#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__SHIFT 0x5
-#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__SHIFT 0x6
-#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN__SHIFT 0x8
-#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__SHIFT 0x9
-#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__SHIFT 0xa
-#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__SHIFT 0xd
-#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__SHIFT 0xf
-#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT 0x11
-#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__SHIFT 0x17
-#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__SHIFT 0x18
-//BIF_RST_MISC_CTRL2
-#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__SHIFT 0x10
-#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__SHIFT 0x11
-#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__SHIFT 0x12
-#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__SHIFT 0x1f
-//BIF_RST_MISC_CTRL3
-#define BIF_RST_MISC_CTRL3__TIMER_SCALE__SHIFT 0x0
-#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__SHIFT 0x4
-#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__SHIFT 0x6
-#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD__SHIFT 0x7
-#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT__SHIFT 0xa
-#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF__SHIFT 0xd
-//BIF_RST_GFXVF_FLR_IDLE
-#define BIF_RST_GFXVF_FLR_IDLE__VF0_TRANS_IDLE__SHIFT 0x0
-#define BIF_RST_GFXVF_FLR_IDLE__VF1_TRANS_IDLE__SHIFT 0x1
-#define BIF_RST_GFXVF_FLR_IDLE__VF2_TRANS_IDLE__SHIFT 0x2
-#define BIF_RST_GFXVF_FLR_IDLE__VF3_TRANS_IDLE__SHIFT 0x3
-#define BIF_RST_GFXVF_FLR_IDLE__VF4_TRANS_IDLE__SHIFT 0x4
-#define BIF_RST_GFXVF_FLR_IDLE__VF5_TRANS_IDLE__SHIFT 0x5
-#define BIF_RST_GFXVF_FLR_IDLE__VF6_TRANS_IDLE__SHIFT 0x6
-#define BIF_RST_GFXVF_FLR_IDLE__VF7_TRANS_IDLE__SHIFT 0x7
-#define BIF_RST_GFXVF_FLR_IDLE__VF8_TRANS_IDLE__SHIFT 0x8
-#define BIF_RST_GFXVF_FLR_IDLE__VF9_TRANS_IDLE__SHIFT 0x9
-#define BIF_RST_GFXVF_FLR_IDLE__VF10_TRANS_IDLE__SHIFT 0xa
-#define BIF_RST_GFXVF_FLR_IDLE__VF11_TRANS_IDLE__SHIFT 0xb
-#define BIF_RST_GFXVF_FLR_IDLE__VF12_TRANS_IDLE__SHIFT 0xc
-#define BIF_RST_GFXVF_FLR_IDLE__VF13_TRANS_IDLE__SHIFT 0xd
-#define BIF_RST_GFXVF_FLR_IDLE__VF14_TRANS_IDLE__SHIFT 0xe
-#define BIF_RST_GFXVF_FLR_IDLE__VF15_TRANS_IDLE__SHIFT 0xf
-#define BIF_RST_GFXVF_FLR_IDLE__SOFTPF_TRANS_IDLE__SHIFT 0x1f
-//DEV0_PF0_FLR_RST_CTRL
-#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
-#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
-#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
-#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
-#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
-#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN__SHIFT 0x5
-#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN__SHIFT 0x6
-#define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN__SHIFT 0x7
-#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN__SHIFT 0x8
-#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__SHIFT 0x9
-#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__SHIFT 0xa
-#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN__SHIFT 0xb
-#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__SHIFT 0xc
-#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN__SHIFT 0xd
-#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN__SHIFT 0xe
-#define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN__SHIFT 0xf
-#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN__SHIFT 0x10
-#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
-#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
-#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
-#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
-//DEV0_PF1_FLR_RST_CTRL
-#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
-#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
-#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
-#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
-#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
-#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
-#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
-#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
-#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
-//DEV0_PF2_FLR_RST_CTRL
-#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
-#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
-#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
-#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
-#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
-#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
-#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
-#define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
-#define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
-//DEV0_PF3_FLR_RST_CTRL
-#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
-#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
-#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
-#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
-#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
-#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
-#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
-#define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
-#define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
-//DEV0_PF4_FLR_RST_CTRL
-#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
-#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
-#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
-#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
-#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
-#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
-#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
-#define DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
-#define DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
-//DEV0_PF5_FLR_RST_CTRL
-#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
-#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
-#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
-#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
-#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
-#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
-#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
-#define DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
-#define DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
-//DEV0_PF6_FLR_RST_CTRL
-#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
-#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
-#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
-#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
-#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
-#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
-#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
-#define DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
-#define DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
-//DEV0_PF7_FLR_RST_CTRL
-#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
-#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
-#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
-#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
-#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
-#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
-#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
-#define DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
-#define DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
-//BIF_INST_RESET_INTR_STS
-#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__SHIFT 0x0
-#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT 0x1
-#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__SHIFT 0x2
-#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__SHIFT 0x3
-#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__SHIFT 0x4
-//BIF_PF_FLR_INTR_STS
-#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__SHIFT 0x0
-#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__SHIFT 0x1
-#define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS__SHIFT 0x2
-#define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS__SHIFT 0x3
-#define BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS__SHIFT 0x4
-#define BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS__SHIFT 0x5
-#define BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS__SHIFT 0x6
-#define BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS__SHIFT 0x7
-//BIF_D3HOTD0_INTR_STS
-#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__SHIFT 0x0
-#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__SHIFT 0x1
-#define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS__SHIFT 0x2
-#define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS__SHIFT 0x3
-#define BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS__SHIFT 0x4
-#define BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS__SHIFT 0x5
-#define BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS__SHIFT 0x6
-#define BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS__SHIFT 0x7
-//BIF_POWER_INTR_STS
-#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__SHIFT 0x0
-#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__SHIFT 0x10
-//BIF_PF_DSTATE_INTR_STS
-#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__SHIFT 0x0
-#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__SHIFT 0x1
-#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__SHIFT 0x2
-#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__SHIFT 0x3
-#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__SHIFT 0x4
-#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__SHIFT 0x5
-#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__SHIFT 0x6
-#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__SHIFT 0x7
-//BIF_PF0_VF_FLR_INTR_STS
-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF0_FLR_INTR_STS__SHIFT 0x0
-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF1_FLR_INTR_STS__SHIFT 0x1
-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF2_FLR_INTR_STS__SHIFT 0x2
-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF3_FLR_INTR_STS__SHIFT 0x3
-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF4_FLR_INTR_STS__SHIFT 0x4
-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF5_FLR_INTR_STS__SHIFT 0x5
-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF6_FLR_INTR_STS__SHIFT 0x6
-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF7_FLR_INTR_STS__SHIFT 0x7
-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF8_FLR_INTR_STS__SHIFT 0x8
-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF9_FLR_INTR_STS__SHIFT 0x9
-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF10_FLR_INTR_STS__SHIFT 0xa
-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF11_FLR_INTR_STS__SHIFT 0xb
-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF12_FLR_INTR_STS__SHIFT 0xc
-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF13_FLR_INTR_STS__SHIFT 0xd
-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF14_FLR_INTR_STS__SHIFT 0xe
-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF15_FLR_INTR_STS__SHIFT 0xf
-#define BIF_PF0_VF_FLR_INTR_STS__PF0_SOFTPF_FLR_INTR_STS__SHIFT 0x1f
-//BIF_INST_RESET_INTR_MASK
-#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__SHIFT 0x0
-#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT 0x1
-#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__SHIFT 0x2
-#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__SHIFT 0x3
-#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__SHIFT 0x4
-//BIF_PF_FLR_INTR_MASK
-#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__SHIFT 0x0
-#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__SHIFT 0x1
-#define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK__SHIFT 0x2
-#define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK__SHIFT 0x3
-#define BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK__SHIFT 0x4
-#define BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK__SHIFT 0x5
-#define BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK__SHIFT 0x6
-#define BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK__SHIFT 0x7
-//BIF_D3HOTD0_INTR_MASK
-#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__SHIFT 0x0
-#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__SHIFT 0x1
-#define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK__SHIFT 0x2
-#define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK__SHIFT 0x3
-#define BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK__SHIFT 0x4
-#define BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK__SHIFT 0x5
-#define BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK__SHIFT 0x6
-#define BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK__SHIFT 0x7
-//BIF_POWER_INTR_MASK
-#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__SHIFT 0x0
-#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__SHIFT 0x10
-//BIF_PF_DSTATE_INTR_MASK
-#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__SHIFT 0x0
-#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__SHIFT 0x1
-#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__SHIFT 0x2
-#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__SHIFT 0x3
-#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__SHIFT 0x4
-#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__SHIFT 0x5
-#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__SHIFT 0x6
-#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__SHIFT 0x7
-//BIF_PF0_VF_FLR_INTR_MASK
-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF0_FLR_INTR_MASK__SHIFT 0x0
-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF1_FLR_INTR_MASK__SHIFT 0x1
-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF2_FLR_INTR_MASK__SHIFT 0x2
-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF3_FLR_INTR_MASK__SHIFT 0x3
-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF4_FLR_INTR_MASK__SHIFT 0x4
-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF5_FLR_INTR_MASK__SHIFT 0x5
-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF6_FLR_INTR_MASK__SHIFT 0x6
-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF7_FLR_INTR_MASK__SHIFT 0x7
-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF8_FLR_INTR_MASK__SHIFT 0x8
-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF9_FLR_INTR_MASK__SHIFT 0x9
-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF10_FLR_INTR_MASK__SHIFT 0xa
-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF11_FLR_INTR_MASK__SHIFT 0xb
-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF12_FLR_INTR_MASK__SHIFT 0xc
-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF13_FLR_INTR_MASK__SHIFT 0xd
-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF14_FLR_INTR_MASK__SHIFT 0xe
-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF15_FLR_INTR_MASK__SHIFT 0xf
-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_SOFTPF_FLR_INTR_MASK__SHIFT 0x1f
-//BIF_PF_FLR_RST
-#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT 0x0
-#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT 0x1
-#define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST__SHIFT 0x2
-#define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST__SHIFT 0x3
-#define BIF_PF_FLR_RST__DEV0_PF4_FLR_RST__SHIFT 0x4
-#define BIF_PF_FLR_RST__DEV0_PF5_FLR_RST__SHIFT 0x5
-#define BIF_PF_FLR_RST__DEV0_PF6_FLR_RST__SHIFT 0x6
-#define BIF_PF_FLR_RST__DEV0_PF7_FLR_RST__SHIFT 0x7
-//BIF_PF0_VF_FLR_RST
-#define BIF_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__SHIFT 0x0
-#define BIF_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__SHIFT 0x1
-#define BIF_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__SHIFT 0x2
-#define BIF_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__SHIFT 0x3
-#define BIF_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__SHIFT 0x4
-#define BIF_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__SHIFT 0x5
-#define BIF_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__SHIFT 0x6
-#define BIF_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__SHIFT 0x7
-#define BIF_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__SHIFT 0x8
-#define BIF_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__SHIFT 0x9
-#define BIF_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__SHIFT 0xa
-#define BIF_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__SHIFT 0xb
-#define BIF_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__SHIFT 0xc
-#define BIF_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__SHIFT 0xd
-#define BIF_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__SHIFT 0xe
-#define BIF_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__SHIFT 0xf
-#define BIF_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__SHIFT 0x1f
-//BIF_DEV0_PF0_DSTATE_VALUE
-#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__SHIFT 0x0
-#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
-#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__SHIFT 0x10
-//BIF_DEV0_PF1_DSTATE_VALUE
-#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__SHIFT 0x0
-#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
-#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__SHIFT 0x10
-//BIF_DEV0_PF2_DSTATE_VALUE
-#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE__SHIFT 0x0
-#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
-#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE__SHIFT 0x10
-//BIF_DEV0_PF3_DSTATE_VALUE
-#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE__SHIFT 0x0
-#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
-#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE__SHIFT 0x10
-//BIF_DEV0_PF4_DSTATE_VALUE
-#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE__SHIFT 0x0
-#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
-#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE__SHIFT 0x10
-//BIF_DEV0_PF5_DSTATE_VALUE
-#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE__SHIFT 0x0
-#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
-#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE__SHIFT 0x10
-//BIF_DEV0_PF6_DSTATE_VALUE
-#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE__SHIFT 0x0
-#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
-#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE__SHIFT 0x10
-//BIF_DEV0_PF7_DSTATE_VALUE
-#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE__SHIFT 0x0
-#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
-#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE__SHIFT 0x10
-//DEV0_PF0_D3HOTD0_RST_CTRL
-#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
-#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
-#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
-#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
-#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
-//DEV0_PF1_D3HOTD0_RST_CTRL
-#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
-#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
-#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
-#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
-#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
-//DEV0_PF2_D3HOTD0_RST_CTRL
-#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
-#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
-#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
-#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
-#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
-//DEV0_PF3_D3HOTD0_RST_CTRL
-#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
-#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
-#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
-#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
-#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
-//DEV0_PF4_D3HOTD0_RST_CTRL
-#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
-#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
-#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
-#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
-#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
-//DEV0_PF5_D3HOTD0_RST_CTRL
-#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
-#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
-#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
-#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
-#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
-//DEV0_PF6_D3HOTD0_RST_CTRL
-#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
-#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
-#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
-#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
-#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
-//DEV0_PF7_D3HOTD0_RST_CTRL
-#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
-#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
-#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
-#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
-#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
-//BIF_PORT0_DSTATE_VALUE
-#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__SHIFT 0x0
-#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__SHIFT 0x10
-
-
-// addressBlock: bif_misc_bif_misc_regblk
-//MISC_SCRATCH
-#define MISC_SCRATCH__MISC_SCRATCH0__SHIFT 0x0
-//INTR_LINE_POLARITY
-#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__SHIFT 0x0
-//INTR_LINE_ENABLE
-#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__SHIFT 0x0
-//OUTSTANDING_VC_ALLOC
-#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__SHIFT 0x0
-#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__SHIFT 0x2
-#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__SHIFT 0x4
-#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__SHIFT 0x6
-#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__SHIFT 0x8
-#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__SHIFT 0xa
-#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__SHIFT 0xc
-#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__SHIFT 0xe
-#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__SHIFT 0x10
-#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__SHIFT 0x18
-#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__SHIFT 0x1a
-#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__SHIFT 0x1c
-//BIFC_MISC_CTRL0
-#define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN__SHIFT 0x0
-#define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN__SHIFT 0x1
-#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__SHIFT 0x8
-#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK__SHIFT 0x9
-#define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK__SHIFT 0xa
-#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__SHIFT 0x10
-#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__SHIFT 0x11
-#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__SHIFT 0x18
-#define BIFC_MISC_CTRL0__VC7_DMA_IOCFG_DIS__SHIFT 0x19
-#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__SHIFT 0x1a
-#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__SHIFT 0x1b
-#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE__SHIFT 0x1c
-#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION__SHIFT 0x1f
-//BIFC_MISC_CTRL1
-#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__SHIFT 0x0
-#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__SHIFT 0x1
-#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__SHIFT 0x2
-#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__SHIFT 0x3
-#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__SHIFT 0x4
-#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__SHIFT 0x5
-#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__SHIFT 0x6
-#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__SHIFT 0x7
-#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__SHIFT 0x8
-#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__SHIFT 0xa
-#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__SHIFT 0xc
-#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__SHIFT 0xd
-#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__SHIFT 0xe
-#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__SHIFT 0xf
-#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__SHIFT 0x10
-#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__SHIFT 0x11
-#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__SHIFT 0x12
-#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__SHIFT 0x13
-//BIFC_BME_ERR_LOG
-#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x0
-#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x1
-#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F2__SHIFT 0x2
-#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F3__SHIFT 0x3
-#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F4__SHIFT 0x4
-#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F5__SHIFT 0x5
-#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F6__SHIFT 0x6
-#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F7__SHIFT 0x7
-#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x10
-#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x11
-#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F2__SHIFT 0x12
-#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F3__SHIFT 0x13
-#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F4__SHIFT 0x14
-#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F5__SHIFT 0x15
-#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F6__SHIFT 0x16
-#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F7__SHIFT 0x17
-//BIFC_RCCBIH_BME_ERR_LOG
-#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x0
-#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x1
-#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT 0x2
-#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT 0x3
-#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT 0x4
-#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT 0x5
-#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT 0x6
-#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT 0x7
-#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x10
-#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x11
-#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT 0x12
-#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT 0x13
-#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT 0x14
-#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT 0x15
-#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT 0x16
-#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT 0x17
-//BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__SHIFT 0x0
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__SHIFT 0x2
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__SHIFT 0x6
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__SHIFT 0x8
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__SHIFT 0xa
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__SHIFT 0xc
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__SHIFT 0x10
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__SHIFT 0x12
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__SHIFT 0x16
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__SHIFT 0x18
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__SHIFT 0x1a
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__SHIFT 0x1c
-//BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__SHIFT 0x0
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__SHIFT 0x2
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__SHIFT 0x6
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__SHIFT 0x8
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__SHIFT 0xa
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__SHIFT 0xc
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__SHIFT 0x10
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__SHIFT 0x12
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__SHIFT 0x16
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__SHIFT 0x18
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__SHIFT 0x1a
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__SHIFT 0x1c
-//BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__SHIFT 0x0
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__SHIFT 0x2
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__SHIFT 0x6
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__SHIFT 0x8
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__SHIFT 0xa
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__SHIFT 0xc
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__SHIFT 0x10
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__SHIFT 0x12
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__SHIFT 0x16
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__SHIFT 0x18
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__SHIFT 0x1a
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__SHIFT 0x1c
-//BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__SHIFT 0x0
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__SHIFT 0x2
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__SHIFT 0x6
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__SHIFT 0x8
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__SHIFT 0xa
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__SHIFT 0xc
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__SHIFT 0x10
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__SHIFT 0x12
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__SHIFT 0x16
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__SHIFT 0x18
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__SHIFT 0x1a
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__SHIFT 0x1c
-//NBIF_VWIRE_CTRL
-#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT__SHIFT 0x4
-#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED__SHIFT 0x8
-#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT__SHIFT 0x14
-#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL__SHIFT 0x1a
-//NBIF_SMN_VWR_VCHG_DIS_CTRL
-#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS__SHIFT 0x0
-#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS__SHIFT 0x1
-#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS__SHIFT 0x2
-#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS__SHIFT 0x3
-#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS__SHIFT 0x4
-#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS__SHIFT 0x5
-#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS__SHIFT 0x6
-//NBIF_SMN_VWR_VCHG_RST_CTRL0
-#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV__SHIFT 0x0
-#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV__SHIFT 0x1
-#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV__SHIFT 0x2
-#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV__SHIFT 0x3
-#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV__SHIFT 0x4
-#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV__SHIFT 0x5
-#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV__SHIFT 0x6
-//NBIF_SMN_VWR_VCHG_TRIG
-#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG__SHIFT 0x0
-#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG__SHIFT 0x1
-#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG__SHIFT 0x2
-#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG__SHIFT 0x3
-#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG__SHIFT 0x4
-#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG__SHIFT 0x5
-#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG__SHIFT 0x6
-//NBIF_SMN_VWR_WTRIG_CNTL
-#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS__SHIFT 0x0
-#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS__SHIFT 0x1
-#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS__SHIFT 0x2
-#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS__SHIFT 0x3
-#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS__SHIFT 0x4
-#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS__SHIFT 0x5
-#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS__SHIFT 0x6
-//NBIF_SMN_VWR_VCHG_DIS_CTRL_1
-#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV__SHIFT 0x0
-#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV__SHIFT 0x1
-#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV__SHIFT 0x2
-#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV__SHIFT 0x3
-#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV__SHIFT 0x4
-#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV__SHIFT 0x5
-#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV__SHIFT 0x6
-//NBIF_MGCG_CTRL
-#define NBIF_MGCG_CTRL__NBIF_MGCG_EN__SHIFT 0x0
-#define NBIF_MGCG_CTRL__NBIF_MGCG_MODE__SHIFT 0x1
-#define NBIF_MGCG_CTRL__NBIF_MGCG_HYSTERESIS__SHIFT 0x2
-//NBIF_DS_CTRL_LCLK
-#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN__SHIFT 0x0
-#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER__SHIFT 0x10
-//SMN_MST_CNTL0
-#define SMN_MST_CNTL0__SMN_ARB_MODE__SHIFT 0x0
-#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS__SHIFT 0x8
-#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS__SHIFT 0x9
-#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS__SHIFT 0xa
-#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS__SHIFT 0xb
-#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0__SHIFT 0x10
-#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0__SHIFT 0x14
-#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0__SHIFT 0x18
-#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0__SHIFT 0x1c
-//SMN_MST_EP_CNTL1
-#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0__SHIFT 0x0
-#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1__SHIFT 0x1
-#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2__SHIFT 0x2
-#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3__SHIFT 0x3
-#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4__SHIFT 0x4
-#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5__SHIFT 0x5
-#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6__SHIFT 0x6
-#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7__SHIFT 0x7
-//SMN_MST_EP_CNTL2
-#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0__SHIFT 0x0
-#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1__SHIFT 0x1
-#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2__SHIFT 0x2
-#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3__SHIFT 0x3
-#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4__SHIFT 0x4
-#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5__SHIFT 0x5
-#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6__SHIFT 0x6
-#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7__SHIFT 0x7
-//NBIF_SDP_VWR_VCHG_DIS_CTRL
-#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS__SHIFT 0x0
-#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS__SHIFT 0x1
-#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS__SHIFT 0x2
-#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS__SHIFT 0x3
-#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS__SHIFT 0x4
-#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS__SHIFT 0x5
-#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS__SHIFT 0x6
-#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS__SHIFT 0x7
-#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS__SHIFT 0x18
-//NBIF_SDP_VWR_VCHG_RST_CTRL0
-#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN__SHIFT 0x0
-#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN__SHIFT 0x1
-#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN__SHIFT 0x2
-#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN__SHIFT 0x3
-#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN__SHIFT 0x4
-#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN__SHIFT 0x5
-#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN__SHIFT 0x6
-#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN__SHIFT 0x7
-#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN__SHIFT 0x18
-//NBIF_SDP_VWR_VCHG_RST_CTRL1
-#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL__SHIFT 0x0
-#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL__SHIFT 0x1
-#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL__SHIFT 0x2
-#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL__SHIFT 0x3
-#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL__SHIFT 0x4
-#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL__SHIFT 0x5
-#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL__SHIFT 0x6
-#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL__SHIFT 0x7
-#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL__SHIFT 0x18
-//NBIF_SDP_VWR_VCHG_TRIG
-#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG__SHIFT 0x0
-#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG__SHIFT 0x1
-#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG__SHIFT 0x2
-#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG__SHIFT 0x3
-#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG__SHIFT 0x4
-#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG__SHIFT 0x5
-#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG__SHIFT 0x6
-#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG__SHIFT 0x7
-#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG__SHIFT 0x18
-//BME_DUMMY_CNTL_0
-#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__SHIFT 0x0
-#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__SHIFT 0x2
-#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__SHIFT 0x4
-#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__SHIFT 0x6
-#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__SHIFT 0x8
-#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__SHIFT 0xa
-#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__SHIFT 0xc
-#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__SHIFT 0xe
-//BIFC_THT_CNTL
-#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0__SHIFT 0x0
-#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0__SHIFT 0x4
-#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1__SHIFT 0x8
-//BIFC_HSTARB_CNTL
-#define BIFC_HSTARB_CNTL__SLVARB_MODE__SHIFT 0x0
-//BIFC_GSI_CNTL
-#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__SHIFT 0x0
-#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__SHIFT 0x2
-#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__SHIFT 0x5
-#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__SHIFT 0x6
-#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__SHIFT 0x7
-#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__SHIFT 0x8
-#define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN__SHIFT 0x9
-#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__SHIFT 0xa
-#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__SHIFT 0xc
-//BIFC_PCIEFUNC_CNTL
-#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__SHIFT 0x0
-#define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC__SHIFT 0x10
-//BIFC_SDP_CNTL_0
-#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__SHIFT 0x0
-#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__SHIFT 0x6
-#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__SHIFT 0xc
-#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__SHIFT 0x12
-//BIFC_PERF_CNTL_0
-#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__SHIFT 0x0
-#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__SHIFT 0x1
-#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__SHIFT 0x8
-#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__SHIFT 0x9
-#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__SHIFT 0x10
-#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__SHIFT 0x18
-//BIFC_PERF_CNTL_1
-#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__SHIFT 0x0
-#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__SHIFT 0x1
-#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__SHIFT 0x8
-#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__SHIFT 0x9
-#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__SHIFT 0x10
-#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__SHIFT 0x18
-//BIFC_PERF_CNT_MMIO_RD
-#define BIFC_PERF_CNT_MMIO_RD__PERF_CNT_MMIO_RD_VALUE__SHIFT 0x0
-//BIFC_PERF_CNT_MMIO_WR
-#define BIFC_PERF_CNT_MMIO_WR__PERF_CNT_MMIO_WR_VALUE__SHIFT 0x0
-//BIFC_PERF_CNT_DMA_RD
-#define BIFC_PERF_CNT_DMA_RD__PERF_CNT_DMA_RD_VALUE__SHIFT 0x0
-//BIFC_PERF_CNT_DMA_WR
-#define BIFC_PERF_CNT_DMA_WR__PERF_CNT_DMA_WR_VALUE__SHIFT 0x0
-//NBIF_REGIF_ERRSET_CTRL
-#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0
-//SMN_MST_EP_CNTL3
-#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0__SHIFT 0x0
-#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1__SHIFT 0x1
-#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2__SHIFT 0x2
-#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3__SHIFT 0x3
-#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4__SHIFT 0x4
-#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5__SHIFT 0x5
-#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6__SHIFT 0x6
-#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7__SHIFT 0x7
-//SMN_MST_EP_CNTL4
-#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0__SHIFT 0x0
-#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1__SHIFT 0x1
-#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2__SHIFT 0x2
-#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3__SHIFT 0x3
-#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4__SHIFT 0x4
-#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5__SHIFT 0x5
-#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6__SHIFT 0x6
-#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7__SHIFT 0x7
-//BIF_SELFRING_BUFFER_VID
-#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID__SHIFT 0x0
-#define BIF_SELFRING_BUFFER_VID__IOHUB_RAS_INTR_CID__SHIFT 0x8
-//BIF_SELFRING_VECTOR_CNTL
-#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS__SHIFT 0x0
-
-
-// addressBlock: bif_ras_bif_ras_regblk
-//BIF_RAS_LEAF0_CTRL
-#define BIF_RAS_LEAF0_CTRL__POISON_DET_EN__SHIFT 0x0
-#define BIF_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
-#define BIF_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT 0x2
-#define BIF_RAS_LEAF0_CTRL__PARITY_DET_EN__SHIFT 0x4
-#define BIF_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5
-#define BIF_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT 0x6
-#define BIF_RAS_LEAF0_CTRL__ERR_EVENT_RECV__SHIFT 0x10
-#define BIF_RAS_LEAF0_CTRL__LINK_DIS_RECV__SHIFT 0x11
-#define BIF_RAS_LEAF0_CTRL__POISON_ERR_DET__SHIFT 0x12
-#define BIF_RAS_LEAF0_CTRL__PARITY_ERR_DET__SHIFT 0x13
-#define BIF_RAS_LEAF0_CTRL__ERR_EVENT_SENT__SHIFT 0x14
-#define BIF_RAS_LEAF0_CTRL__EGRESS_STALLED__SHIFT 0x15
-//BIF_RAS_LEAF1_CTRL
-#define BIF_RAS_LEAF1_CTRL__POISON_DET_EN__SHIFT 0x0
-#define BIF_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
-#define BIF_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT 0x2
-#define BIF_RAS_LEAF1_CTRL__PARITY_DET_EN__SHIFT 0x4
-#define BIF_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5
-#define BIF_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT 0x6
-#define BIF_RAS_LEAF1_CTRL__ERR_EVENT_RECV__SHIFT 0x10
-#define BIF_RAS_LEAF1_CTRL__LINK_DIS_RECV__SHIFT 0x11
-#define BIF_RAS_LEAF1_CTRL__POISON_ERR_DET__SHIFT 0x12
-#define BIF_RAS_LEAF1_CTRL__PARITY_ERR_DET__SHIFT 0x13
-#define BIF_RAS_LEAF1_CTRL__ERR_EVENT_SENT__SHIFT 0x14
-#define BIF_RAS_LEAF1_CTRL__EGRESS_STALLED__SHIFT 0x15
-//BIF_RAS_LEAF2_CTRL
-#define BIF_RAS_LEAF2_CTRL__POISON_DET_EN__SHIFT 0x0
-#define BIF_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
-#define BIF_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT 0x2
-#define BIF_RAS_LEAF2_CTRL__PARITY_DET_EN__SHIFT 0x4
-#define BIF_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5
-#define BIF_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT 0x6
-#define BIF_RAS_LEAF2_CTRL__ERR_EVENT_RECV__SHIFT 0x10
-#define BIF_RAS_LEAF2_CTRL__LINK_DIS_RECV__SHIFT 0x11
-#define BIF_RAS_LEAF2_CTRL__POISON_ERR_DET__SHIFT 0x12
-#define BIF_RAS_LEAF2_CTRL__PARITY_ERR_DET__SHIFT 0x13
-#define BIF_RAS_LEAF2_CTRL__ERR_EVENT_SENT__SHIFT 0x14
-#define BIF_RAS_LEAF2_CTRL__EGRESS_STALLED__SHIFT 0x15
-//BIF_RAS_MISC_CTRL
-#define BIF_RAS_MISC_CTRL__LINKDIS_TRIG_ERREVENT_EN__SHIFT 0x0
-//BIF_IOHUB_RAS_IH_CNTL
-#define BIF_IOHUB_RAS_IH_CNTL__RAS_IH_INTR_EN__SHIFT 0x0
-//BIF_RAS_VWR_FROM_IOHUB
-#define BIF_RAS_VWR_FROM_IOHUB__RAS_IH_INTR_TRIG__SHIFT 0x0
-
-
-// addressBlock: rcc_pfc_amdgfx_RCCPFCDEC
-//RCC_PFC_LTR_CNTL
-#define RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0
-#define RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa
-#define RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf
-#define RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10
-#define RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a
-#define RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f
-//RCC_PFC_PME_RESTORE
-#define RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0
-#define RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8
-//RCC_PFC_STICKY_RESTORE_0
-#define RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0
-#define RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1
-#define RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2
-#define RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3
-#define RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4
-#define RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5
-#define RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6
-#define RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7
-//RCC_PFC_STICKY_RESTORE_1
-#define RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0
-//RCC_PFC_STICKY_RESTORE_2
-#define RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0
-//RCC_PFC_STICKY_RESTORE_3
-#define RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0
-//RCC_PFC_STICKY_RESTORE_4
-#define RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0
-//RCC_PFC_STICKY_RESTORE_5
-#define RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0
-//RCC_PFC_AUXPWR_CNTL
-#define RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0
-#define RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3
-
-
-// addressBlock: rcc_pfc_amdgfxaz_RCCPFCDEC
-//RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL
-#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0
-#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa
-#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf
-#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10
-#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a
-#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f
-//RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE
-#define RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0
-#define RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8
-//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0
-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0
-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1
-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2
-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3
-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4
-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5
-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6
-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7
-//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1
-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0
-//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2
-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0
-//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3
-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0
-//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4
-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0
-//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5
-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0
-//RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL
-#define RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0
-#define RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3
-
-
-// addressBlock: pciemsix_amdgfx_MSIXTDEC
-//PCIEMSIX_VECT0_ADDR_LO
-#define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
-//PCIEMSIX_VECT0_ADDR_HI
-#define PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
-//PCIEMSIX_VECT0_MSG_DATA
-#define PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
-//PCIEMSIX_VECT0_CONTROL
-#define PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
-//PCIEMSIX_VECT1_ADDR_LO
-#define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
-//PCIEMSIX_VECT1_ADDR_HI
-#define PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
-//PCIEMSIX_VECT1_MSG_DATA
-#define PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
-//PCIEMSIX_VECT1_CONTROL
-#define PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
-//PCIEMSIX_VECT2_ADDR_LO
-#define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
-//PCIEMSIX_VECT2_ADDR_HI
-#define PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
-//PCIEMSIX_VECT2_MSG_DATA
-#define PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
-//PCIEMSIX_VECT2_CONTROL
-#define PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
-//PCIEMSIX_VECT3_ADDR_LO
-#define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
-//PCIEMSIX_VECT3_ADDR_HI
-#define PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
-//PCIEMSIX_VECT3_MSG_DATA
-#define PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
-//PCIEMSIX_VECT3_CONTROL
-#define PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
-//PCIEMSIX_VECT4_ADDR_LO
-#define PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
-//PCIEMSIX_VECT4_ADDR_HI
-#define PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
-//PCIEMSIX_VECT4_MSG_DATA
-#define PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0
-//PCIEMSIX_VECT4_CONTROL
-#define PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0
-//PCIEMSIX_VECT5_ADDR_LO
-#define PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
-//PCIEMSIX_VECT5_ADDR_HI
-#define PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
-//PCIEMSIX_VECT5_MSG_DATA
-#define PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0
-//PCIEMSIX_VECT5_CONTROL
-#define PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0
-//PCIEMSIX_VECT6_ADDR_LO
-#define PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
-//PCIEMSIX_VECT6_ADDR_HI
-#define PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
-//PCIEMSIX_VECT6_MSG_DATA
-#define PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0
-//PCIEMSIX_VECT6_CONTROL
-#define PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0
-//PCIEMSIX_VECT7_ADDR_LO
-#define PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
-//PCIEMSIX_VECT7_ADDR_HI
-#define PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
-//PCIEMSIX_VECT7_MSG_DATA
-#define PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0
-//PCIEMSIX_VECT7_CONTROL
-#define PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0
-//PCIEMSIX_VECT8_ADDR_LO
-#define PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
-//PCIEMSIX_VECT8_ADDR_HI
-#define PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
-//PCIEMSIX_VECT8_MSG_DATA
-#define PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0
-//PCIEMSIX_VECT8_CONTROL
-#define PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0
-//PCIEMSIX_VECT9_ADDR_LO
-#define PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
-//PCIEMSIX_VECT9_ADDR_HI
-#define PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
-//PCIEMSIX_VECT9_MSG_DATA
-#define PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT 0x0
-//PCIEMSIX_VECT9_CONTROL
-#define PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT 0x0
-//PCIEMSIX_VECT10_ADDR_LO
-#define PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
-//PCIEMSIX_VECT10_ADDR_HI
-#define PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
-//PCIEMSIX_VECT10_MSG_DATA
-#define PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT 0x0
-//PCIEMSIX_VECT10_CONTROL
-#define PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT 0x0
-//PCIEMSIX_VECT11_ADDR_LO
-#define PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
-//PCIEMSIX_VECT11_ADDR_HI
-#define PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
-//PCIEMSIX_VECT11_MSG_DATA
-#define PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT 0x0
-//PCIEMSIX_VECT11_CONTROL
-#define PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT 0x0
-//PCIEMSIX_VECT12_ADDR_LO
-#define PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
-//PCIEMSIX_VECT12_ADDR_HI
-#define PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
-//PCIEMSIX_VECT12_MSG_DATA
-#define PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT 0x0
-//PCIEMSIX_VECT12_CONTROL
-#define PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT 0x0
-//PCIEMSIX_VECT13_ADDR_LO
-#define PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
-//PCIEMSIX_VECT13_ADDR_HI
-#define PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
-//PCIEMSIX_VECT13_MSG_DATA
-#define PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT 0x0
-//PCIEMSIX_VECT13_CONTROL
-#define PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT 0x0
-//PCIEMSIX_VECT14_ADDR_LO
-#define PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
-//PCIEMSIX_VECT14_ADDR_HI
-#define PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
-//PCIEMSIX_VECT14_MSG_DATA
-#define PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT 0x0
-//PCIEMSIX_VECT14_CONTROL
-#define PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT 0x0
-//PCIEMSIX_VECT15_ADDR_LO
-#define PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
-//PCIEMSIX_VECT15_ADDR_HI
-#define PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
-//PCIEMSIX_VECT15_MSG_DATA
-#define PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT 0x0
-//PCIEMSIX_VECT15_CONTROL
-#define PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT 0x0
-//PCIEMSIX_VECT16_ADDR_LO
-#define PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
-//PCIEMSIX_VECT16_ADDR_HI
-#define PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
-//PCIEMSIX_VECT16_MSG_DATA
-#define PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT 0x0
-//PCIEMSIX_VECT16_CONTROL
-#define PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT 0x0
-//PCIEMSIX_VECT17_ADDR_LO
-#define PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
-//PCIEMSIX_VECT17_ADDR_HI
-#define PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
-//PCIEMSIX_VECT17_MSG_DATA
-#define PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT 0x0
-//PCIEMSIX_VECT17_CONTROL
-#define PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT 0x0
-//PCIEMSIX_VECT18_ADDR_LO
-#define PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
-//PCIEMSIX_VECT18_ADDR_HI
-#define PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
-//PCIEMSIX_VECT18_MSG_DATA
-#define PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT 0x0
-//PCIEMSIX_VECT18_CONTROL
-#define PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT 0x0
-//PCIEMSIX_VECT19_ADDR_LO
-#define PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
-//PCIEMSIX_VECT19_ADDR_HI
-#define PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
-//PCIEMSIX_VECT19_MSG_DATA
-#define PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT 0x0
-//PCIEMSIX_VECT19_CONTROL
-#define PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT 0x0
-//PCIEMSIX_VECT20_ADDR_LO
-#define PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
-//PCIEMSIX_VECT20_ADDR_HI
-#define PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
-//PCIEMSIX_VECT20_MSG_DATA
-#define PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT 0x0
-//PCIEMSIX_VECT20_CONTROL
-#define PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT 0x0
-//PCIEMSIX_VECT21_ADDR_LO
-#define PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
-//PCIEMSIX_VECT21_ADDR_HI
-#define PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
-//PCIEMSIX_VECT21_MSG_DATA
-#define PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT 0x0
-//PCIEMSIX_VECT21_CONTROL
-#define PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT 0x0
-//PCIEMSIX_VECT22_ADDR_LO
-#define PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
-//PCIEMSIX_VECT22_ADDR_HI
-#define PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
-//PCIEMSIX_VECT22_MSG_DATA
-#define PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT 0x0
-//PCIEMSIX_VECT22_CONTROL
-#define PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT 0x0
-//PCIEMSIX_VECT23_ADDR_LO
-#define PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
-//PCIEMSIX_VECT23_ADDR_HI
-#define PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
-//PCIEMSIX_VECT23_MSG_DATA
-#define PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT 0x0
-//PCIEMSIX_VECT23_CONTROL
-#define PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT 0x0
-//PCIEMSIX_VECT24_ADDR_LO
-#define PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
-//PCIEMSIX_VECT24_ADDR_HI
-#define PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
-//PCIEMSIX_VECT24_MSG_DATA
-#define PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT 0x0
-//PCIEMSIX_VECT24_CONTROL
-#define PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT 0x0
-//PCIEMSIX_VECT25_ADDR_LO
-#define PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
-//PCIEMSIX_VECT25_ADDR_HI
-#define PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
-//PCIEMSIX_VECT25_MSG_DATA
-#define PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT 0x0
-//PCIEMSIX_VECT25_CONTROL
-#define PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT 0x0
-//PCIEMSIX_VECT26_ADDR_LO
-#define PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
-//PCIEMSIX_VECT26_ADDR_HI
-#define PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
-//PCIEMSIX_VECT26_MSG_DATA
-#define PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT 0x0
-//PCIEMSIX_VECT26_CONTROL
-#define PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT 0x0
-//PCIEMSIX_VECT27_ADDR_LO
-#define PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
-//PCIEMSIX_VECT27_ADDR_HI
-#define PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
-//PCIEMSIX_VECT27_MSG_DATA
-#define PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT 0x0
-//PCIEMSIX_VECT27_CONTROL
-#define PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT 0x0
-//PCIEMSIX_VECT28_ADDR_LO
-#define PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
-//PCIEMSIX_VECT28_ADDR_HI
-#define PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
-//PCIEMSIX_VECT28_MSG_DATA
-#define PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT 0x0
-//PCIEMSIX_VECT28_CONTROL
-#define PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT 0x0
-//PCIEMSIX_VECT29_ADDR_LO
-#define PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
-//PCIEMSIX_VECT29_ADDR_HI
-#define PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
-//PCIEMSIX_VECT29_MSG_DATA
-#define PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT 0x0
-//PCIEMSIX_VECT29_CONTROL
-#define PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT 0x0
-//PCIEMSIX_VECT30_ADDR_LO
-#define PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
-//PCIEMSIX_VECT30_ADDR_HI
-#define PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
-//PCIEMSIX_VECT30_MSG_DATA
-#define PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT 0x0
-//PCIEMSIX_VECT30_CONTROL
-#define PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT 0x0
-//PCIEMSIX_VECT31_ADDR_LO
-#define PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
-//PCIEMSIX_VECT31_ADDR_HI
-#define PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
-//PCIEMSIX_VECT31_MSG_DATA
-#define PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT 0x0
-//PCIEMSIX_VECT31_CONTROL
-#define PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT 0x0
-
-
-// addressBlock: pciemsix_amdgfx_MSIXPDEC
-//PCIEMSIX_PBA
-#define PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT 0x0
-
-
-// addressBlock: syshub_mmreg_ind_syshubind
-//SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__SHIFT 0x1f
-//SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__SHIFT 0x0
-//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK
-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en__SHIFT 0x0
-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en__SHIFT 0x1
-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__SHIFT 0xf
-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__SHIFT 0x10
-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__SHIFT 0x11
-//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK
-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en__SHIFT 0x0
-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en__SHIFT 0x1
-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__SHIFT 0xf
-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__SHIFT 0x10
-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__SHIFT 0x11
-//SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5
-//SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL
-#define SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0
-#define SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1
-#define SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5
-//SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
-//SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
-//SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
-//SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
-//SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
-//SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
-//SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL
-#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
-#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
-#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
-#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
-#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
-#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
-//SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL
-#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
-#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
-#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
-#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
-#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
-#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
-//SYSHUBMMREGIND_SYSHUB_CG_CNTL
-#define SYSHUBMMREGIND_SYSHUB_CG_CNTL__SYSHUB_CG_EN__SHIFT 0x0
-#define SYSHUBMMREGIND_SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER__SHIFT 0x8
-#define SYSHUBMMREGIND_SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER__SHIFT 0x10
-//SYSHUBMMREGIND_SYSHUB_TRANS_IDLE
-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0__SHIFT 0x0
-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1__SHIFT 0x1
-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2__SHIFT 0x2
-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3__SHIFT 0x3
-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4__SHIFT 0x4
-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5__SHIFT 0x5
-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6__SHIFT 0x6
-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7__SHIFT 0x7
-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8__SHIFT 0x8
-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9__SHIFT 0x9
-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10__SHIFT 0xa
-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11__SHIFT 0xb
-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12__SHIFT 0xc
-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13__SHIFT 0xd
-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14__SHIFT 0xe
-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15__SHIFT 0xf
-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF__SHIFT 0x10
-//SYSHUBMMREGIND_SYSHUB_HP_TIMER
-#define SYSHUBMMREGIND_SYSHUB_HP_TIMER__SYSHUB_HP_TIMER__SHIFT 0x0
-//SYSHUBMMREGIND_SYSHUB_SCRATCH
-#define SYSHUBMMREGIND_SYSHUB_SCRATCH__SCRATCH__SHIFT 0x0
-//SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN__SHIFT 0x1f
-//SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER__SHIFT 0x0
-//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK
-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en__SHIFT 0xf
-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en__SHIFT 0x10
-//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK
-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en__SHIFT 0xf
-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en__SHIFT 0x10
-//SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5
-//SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5
-//SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
-//SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
-//SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
-//SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
-//SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
-//SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
-//SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
-//SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
-//SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
-//SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18
-//MASK
-
-
-// addressBlock: bif_cfg_dev0_epf0_bifcfgdecp
-//VENDOR_ID
-#define VENDOR_ID__VENDOR_ID__MASK 0xFFFFL
-//DEVICE_ID
-#define DEVICE_ID__DEVICE_ID__MASK 0xFFFFL
-//COMMAND
-#define COMMAND__IO_ACCESS_EN__MASK 0x0001L
-#define COMMAND__MEM_ACCESS_EN__MASK 0x0002L
-#define COMMAND__BUS_MASTER_EN__MASK 0x0004L
-#define COMMAND__SPECIAL_CYCLE_EN__MASK 0x0008L
-#define COMMAND__MEM_WRITE_INVALIDATE_EN__MASK 0x0010L
-#define COMMAND__PAL_SNOOP_EN__MASK 0x0020L
-#define COMMAND__PARITY_ERROR_RESPONSE__MASK 0x0040L
-#define COMMAND__AD_STEPPING__MASK 0x0080L
-#define COMMAND__SERR_EN__MASK 0x0100L
-#define COMMAND__FAST_B2B_EN__MASK 0x0200L
-#define COMMAND__INT_DIS__MASK 0x0400L
-//STATUS
-#define STATUS__INT_STATUS__MASK 0x0008L
-#define STATUS__CAP_LIST__MASK 0x0010L
-#define STATUS__PCI_66_EN__MASK 0x0020L
-#define STATUS__FAST_BACK_CAPABLE__MASK 0x0080L
-#define STATUS__MASTER_DATA_PARITY_ERROR__MASK 0x0100L
-#define STATUS__DEVSEL_TIMING__MASK 0x0600L
-#define STATUS__SIGNAL_TARGET_ABORT__MASK 0x0800L
-#define STATUS__RECEIVED_TARGET_ABORT__MASK 0x1000L
-#define STATUS__RECEIVED_MASTER_ABORT__MASK 0x2000L
-#define STATUS__SIGNALED_SYSTEM_ERROR__MASK 0x4000L
-#define STATUS__PARITY_ERROR_DETECTED__MASK 0x8000L
-//REVISION_ID
-#define REVISION_ID__MINOR_REV_ID__MASK 0x0FL
-#define REVISION_ID__MAJOR_REV_ID__MASK 0xF0L
-//PROG_INTERFACE
-#define PROG_INTERFACE__PROG_INTERFACE__MASK 0xFFL
-//SUB_CLASS
-#define SUB_CLASS__SUB_CLASS__MASK 0xFFL
-//BASE_CLASS
-#define BASE_CLASS__BASE_CLASS__MASK 0xFFL
-//CACHE_LINE
-#define CACHE_LINE__CACHE_LINE_SIZE__MASK 0xFFL
-//LATENCY
-#define LATENCY__LATENCY_TIMER__MASK 0xFFL
-//HEADER
-#define HEADER__HEADER_TYPE__MASK 0x7FL
-#define HEADER__DEVICE_TYPE__MASK 0x80L
-//BIST
-#define BIST__BIST_COMP__MASK 0x0FL
-#define BIST__BIST_STRT__MASK 0x40L
-#define BIST__BIST_CAP__MASK 0x80L
-//BASE_ADDR_1
-#define BASE_ADDR_1__BASE_ADDR__MASK 0xFFFFFFFFL
-//BASE_ADDR_2
-#define BASE_ADDR_2__BASE_ADDR__MASK 0xFFFFFFFFL
-//BASE_ADDR_3
-#define BASE_ADDR_3__BASE_ADDR__MASK 0xFFFFFFFFL
-//BASE_ADDR_4
-#define BASE_ADDR_4__BASE_ADDR__MASK 0xFFFFFFFFL
-//BASE_ADDR_5
-#define BASE_ADDR_5__BASE_ADDR__MASK 0xFFFFFFFFL
-//BASE_ADDR_6
-#define BASE_ADDR_6__BASE_ADDR__MASK 0xFFFFFFFFL
-//ADAPTER_ID
-#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID__MASK 0x0000FFFFL
-#define ADAPTER_ID__SUBSYSTEM_ID__MASK 0xFFFF0000L
-//ROM_BASE_ADDR
-#define ROM_BASE_ADDR__BASE_ADDR__MASK 0xFFFFFFFFL
-//CAP_PTR
-#define CAP_PTR__CAP_PTR__MASK 0x000000FFL
-//INTERRUPT_LINE
-#define INTERRUPT_LINE__INTERRUPT_LINE__MASK 0xFFL
-//INTERRUPT_PIN
-#define INTERRUPT_PIN__INTERRUPT_PIN__MASK 0xFFL
-//MIN_GRANT
-#define MIN_GRANT__MIN_GNT__MASK 0xFFL
-//MAX_LATENCY
-#define MAX_LATENCY__MAX_LAT__MASK 0xFFL
-//VENDOR_CAP_LIST
-#define VENDOR_CAP_LIST__CAP_ID__MASK 0x000000FFL
-#define VENDOR_CAP_LIST__NEXT_PTR__MASK 0x0000FF00L
-#define VENDOR_CAP_LIST__LENGTH__MASK 0x00FF0000L
-//ADAPTER_ID_W
-#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__MASK 0x0000FFFFL
-#define ADAPTER_ID_W__SUBSYSTEM_ID__MASK 0xFFFF0000L
-//PMI_CAP_LIST
-#define PMI_CAP_LIST__CAP_ID__MASK 0x00FFL
-#define PMI_CAP_LIST__NEXT_PTR__MASK 0xFF00L
-//PMI_CAP
-#define PMI_CAP__VERSION__MASK 0x0007L
-#define PMI_CAP__PME_CLOCK__MASK 0x0008L
-#define PMI_CAP__DEV_SPECIFIC_INIT__MASK 0x0020L
-#define PMI_CAP__AUX_CURRENT__MASK 0x01C0L
-#define PMI_CAP__D1_SUPPORT__MASK 0x0200L
-#define PMI_CAP__D2_SUPPORT__MASK 0x0400L
-#define PMI_CAP__PME_SUPPORT__MASK 0xF800L
-//PMI_STATUS_CNTL
-#define PMI_STATUS_CNTL__POWER_STATE__MASK 0x00000003L
-#define PMI_STATUS_CNTL__NO_SOFT_RESET__MASK 0x00000008L
-#define PMI_STATUS_CNTL__PME_EN__MASK 0x00000100L
-#define PMI_STATUS_CNTL__DATA_SELECT__MASK 0x00001E00L
-#define PMI_STATUS_CNTL__DATA_SCALE__MASK 0x00006000L
-#define PMI_STATUS_CNTL__PME_STATUS__MASK 0x00008000L
-#define PMI_STATUS_CNTL__B2_B3_SUPPORT__MASK 0x00400000L
-#define PMI_STATUS_CNTL__BUS_PWR_EN__MASK 0x00800000L
-#define PMI_STATUS_CNTL__PMI_DATA__MASK 0xFF000000L
-//PCIE_CAP_LIST
-#define PCIE_CAP_LIST__CAP_ID__MASK 0x00FFL
-#define PCIE_CAP_LIST__NEXT_PTR__MASK 0xFF00L
-//PCIE_CAP
-#define PCIE_CAP__VERSION__MASK 0x000FL
-#define PCIE_CAP__DEVICE_TYPE__MASK 0x00F0L
-#define PCIE_CAP__SLOT_IMPLEMENTED__MASK 0x0100L
-#define PCIE_CAP__INT_MESSAGE_NUM__MASK 0x3E00L
-//DEVICE_CAP
-#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT__MASK 0x00000007L
-#define DEVICE_CAP__PHANTOM_FUNC__MASK 0x00000018L
-#define DEVICE_CAP__EXTENDED_TAG__MASK 0x00000020L
-#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__MASK 0x000001C0L
-#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY__MASK 0x00000E00L
-#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING__MASK 0x00008000L
-#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__MASK 0x03FC0000L
-#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__MASK 0x0C000000L
-#define DEVICE_CAP__FLR_CAPABLE__MASK 0x10000000L
-//DEVICE_CNTL
-#define DEVICE_CNTL__CORR_ERR_EN__MASK 0x0001L
-#define DEVICE_CNTL__NON_FATAL_ERR_EN__MASK 0x0002L
-#define DEVICE_CNTL__FATAL_ERR_EN__MASK 0x0004L
-#define DEVICE_CNTL__USR_REPORT_EN__MASK 0x0008L
-#define DEVICE_CNTL__RELAXED_ORD_EN__MASK 0x0010L
-#define DEVICE_CNTL__MAX_PAYLOAD_SIZE__MASK 0x00E0L
-#define DEVICE_CNTL__EXTENDED_TAG_EN__MASK 0x0100L
-#define DEVICE_CNTL__PHANTOM_FUNC_EN__MASK 0x0200L
-#define DEVICE_CNTL__AUX_POWER_PM_EN__MASK 0x0400L
-#define DEVICE_CNTL__NO_SNOOP_EN__MASK 0x0800L
-#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE__MASK 0x7000L
-#define DEVICE_CNTL__INITIATE_FLR__MASK 0x8000L
-//DEVICE_STATUS
-#define DEVICE_STATUS__CORR_ERR__MASK 0x0001L
-#define DEVICE_STATUS__NON_FATAL_ERR__MASK 0x0002L
-#define DEVICE_STATUS__FATAL_ERR__MASK 0x0004L
-#define DEVICE_STATUS__USR_DETECTED__MASK 0x0008L
-#define DEVICE_STATUS__AUX_PWR__MASK 0x0010L
-#define DEVICE_STATUS__TRANSACTIONS_PEND__MASK 0x0020L
-//LINK_CAP
-#define LINK_CAP__LINK_SPEED__MASK 0x0000000FL
-#define LINK_CAP__LINK_WIDTH__MASK 0x000003F0L
-#define LINK_CAP__PM_SUPPORT__MASK 0x00000C00L
-#define LINK_CAP__L0S_EXIT_LATENCY__MASK 0x00007000L
-#define LINK_CAP__L1_EXIT_LATENCY__MASK 0x00038000L
-#define LINK_CAP__CLOCK_POWER_MANAGEMENT__MASK 0x00040000L
-#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__MASK 0x00080000L
-#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__MASK 0x00100000L
-#define LINK_CAP__LINK_BW_NOTIFICATION_CAP__MASK 0x00200000L
-#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__MASK 0x00400000L
-#define LINK_CAP__PORT_NUMBER__MASK 0xFF000000L
-//LINK_CNTL
-#define LINK_CNTL__PM_CONTROL__MASK 0x0003L
-#define LINK_CNTL__READ_CPL_BOUNDARY__MASK 0x0008L
-#define LINK_CNTL__LINK_DIS__MASK 0x0010L
-#define LINK_CNTL__RETRAIN_LINK__MASK 0x0020L
-#define LINK_CNTL__COMMON_CLOCK_CFG__MASK 0x0040L
-#define LINK_CNTL__EXTENDED_SYNC__MASK 0x0080L
-#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__MASK 0x0100L
-#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__MASK 0x0200L
-#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__MASK 0x0400L
-#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__MASK 0x0800L
-//LINK_STATUS
-#define LINK_STATUS__CURRENT_LINK_SPEED__MASK 0x000FL
-#define LINK_STATUS__NEGOTIATED_LINK_WIDTH__MASK 0x03F0L
-#define LINK_STATUS__LINK_TRAINING__MASK 0x0800L
-#define LINK_STATUS__SLOT_CLOCK_CFG__MASK 0x1000L
-#define LINK_STATUS__DL_ACTIVE__MASK 0x2000L
-#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__MASK 0x4000L
-#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__MASK 0x8000L
-//DEVICE_CAP2
-#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__MASK 0x0000000FL
-#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__MASK 0x00000010L
-#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__MASK 0x00000020L
-#define DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__MASK 0x00000040L
-#define DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__MASK 0x00000080L
-#define DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__MASK 0x00000100L
-#define DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__MASK 0x00000200L
-#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__MASK 0x00000400L
-#define DEVICE_CAP2__LTR_SUPPORTED__MASK 0x00000800L
-#define DEVICE_CAP2__TPH_CPLR_SUPPORTED__MASK 0x00003000L
-#define DEVICE_CAP2__OBFF_SUPPORTED__MASK 0x000C0000L
-#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__MASK 0x00100000L
-#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__MASK 0x00200000L
-#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__MASK 0x00C00000L
-//DEVICE_CNTL2
-#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE__MASK 0x000FL
-#define DEVICE_CNTL2__CPL_TIMEOUT_DIS__MASK 0x0010L
-#define DEVICE_CNTL2__ARI_FORWARDING_EN__MASK 0x0020L
-#define DEVICE_CNTL2__ATOMICOP_REQUEST_EN__MASK 0x0040L
-#define DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__MASK 0x0080L
-#define DEVICE_CNTL2__IDO_REQUEST_ENABLE__MASK 0x0100L
-#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE__MASK 0x0200L
-#define DEVICE_CNTL2__LTR_EN__MASK 0x0400L
-#define DEVICE_CNTL2__OBFF_EN__MASK 0x6000L
-#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__MASK 0x8000L
-//DEVICE_STATUS2
-#define DEVICE_STATUS2__RESERVED__MASK 0xFFFFL
-//LINK_CAP2
-#define LINK_CAP2__SUPPORTED_LINK_SPEED__MASK 0x000000FEL
-#define LINK_CAP2__CROSSLINK_SUPPORTED__MASK 0x00000100L
-#define LINK_CAP2__RESERVED__MASK 0xFFFFFE00L
-//LINK_CNTL2
-#define LINK_CNTL2__TARGET_LINK_SPEED__MASK 0x000FL
-#define LINK_CNTL2__ENTER_COMPLIANCE__MASK 0x0010L
-#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__MASK 0x0020L
-#define LINK_CNTL2__SELECTABLE_DEEMPHASIS__MASK 0x0040L
-#define LINK_CNTL2__XMIT_MARGIN__MASK 0x0380L
-#define LINK_CNTL2__ENTER_MOD_COMPLIANCE__MASK 0x0400L
-#define LINK_CNTL2__COMPLIANCE_SOS__MASK 0x0800L
-#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS__MASK 0xF000L
-//LINK_STATUS2
-#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__MASK 0x0001L
-#define LINK_STATUS2__EQUALIZATION_COMPLETE__MASK 0x0002L
-#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__MASK 0x0004L
-#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__MASK 0x0008L
-#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__MASK 0x0010L
-#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST__MASK 0x0020L
-//SLOT_CAP2
-#define SLOT_CAP2__RESERVED__MASK 0xFFFFFFFFL
-//SLOT_CNTL2
-#define SLOT_CNTL2__RESERVED__MASK 0xFFFFL
-//SLOT_STATUS2
-#define SLOT_STATUS2__RESERVED__MASK 0xFFFFL
-//MSI_CAP_LIST
-#define MSI_CAP_LIST__CAP_ID__MASK 0x00FFL
-#define MSI_CAP_LIST__NEXT_PTR__MASK 0xFF00L
-//MSI_MSG_CNTL
-#define MSI_MSG_CNTL__MSI_EN__MASK 0x0001L
-#define MSI_MSG_CNTL__MSI_MULTI_CAP__MASK 0x000EL
-#define MSI_MSG_CNTL__MSI_MULTI_EN__MASK 0x0070L
-#define MSI_MSG_CNTL__MSI_64BIT__MASK 0x0080L
-#define MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__MASK 0x0100L
-//MSI_MSG_ADDR_LO
-#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__MASK 0xFFFFFFFCL
-//MSI_MSG_ADDR_HI
-#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__MASK 0xFFFFFFFFL
-//MSI_MSG_DATA
-#define MSI_MSG_DATA__MSI_DATA__MASK 0x0000FFFFL
-//MSI_MSG_DATA_64
-#define MSI_MSG_DATA_64__MSI_DATA_64__MASK 0x0000FFFFL
-//MSI_MASK
-#define MSI_MASK__MSI_MASK__MASK 0xFFFFFFFFL
-//MSI_PENDING
-#define MSI_PENDING__MSI_PENDING__MASK 0xFFFFFFFFL
-//MSI_MASK_64
-#define MSI_MASK_64__MSI_MASK_64__MASK 0xFFFFFFFFL
-//MSI_PENDING_64
-#define MSI_PENDING_64__MSI_PENDING_64__MASK 0xFFFFFFFFL
-//MSIX_CAP_LIST
-#define MSIX_CAP_LIST__CAP_ID__MASK 0x00FFL
-#define MSIX_CAP_LIST__NEXT_PTR__MASK 0xFF00L
-//MSIX_MSG_CNTL
-#define MSIX_MSG_CNTL__MSIX_TABLE_SIZE__MASK 0x07FFL
-#define MSIX_MSG_CNTL__MSIX_FUNC_MASK__MASK 0x4000L
-#define MSIX_MSG_CNTL__MSIX_EN__MASK 0x8000L
-//MSIX_TABLE
-#define MSIX_TABLE__MSIX_TABLE_BIR__MASK 0x00000007L
-#define MSIX_TABLE__MSIX_TABLE_OFFSET__MASK 0xFFFFFFF8L
-//MSIX_PBA
-#define MSIX_PBA__MSIX_PBA_BIR__MASK 0x00000007L
-#define MSIX_PBA__MSIX_PBA_OFFSET__MASK 0xFFFFFFF8L
-//PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
-#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL
-#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L
-#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L
-//PCIE_VENDOR_SPECIFIC_HDR
-#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__MASK 0x0000FFFFL
-#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__MASK 0x000F0000L
-#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__MASK 0xFFF00000L
-//PCIE_VENDOR_SPECIFIC1
-#define PCIE_VENDOR_SPECIFIC1__SCRATCH__MASK 0xFFFFFFFFL
-//PCIE_VENDOR_SPECIFIC2
-#define PCIE_VENDOR_SPECIFIC2__SCRATCH__MASK 0xFFFFFFFFL
-//PCIE_VC_ENH_CAP_LIST
-#define PCIE_VC_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL
-#define PCIE_VC_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L
-#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L
-//PCIE_PORT_VC_CAP_REG1
-#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__MASK 0x00000007L
-#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__MASK 0x00000070L
-#define PCIE_PORT_VC_CAP_REG1__REF_CLK__MASK 0x00000300L
-#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__MASK 0x00000C00L
-//PCIE_PORT_VC_CAP_REG2
-#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__MASK 0x000000FFL
-#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__MASK 0xFF000000L
-//PCIE_PORT_VC_CNTL
-#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__MASK 0x0001L
-#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT__MASK 0x000EL
-//PCIE_PORT_VC_STATUS
-#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__MASK 0x0001L
-//PCIE_VC0_RESOURCE_CAP
-#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__MASK 0x000000FFL
-#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__MASK 0x00008000L
-#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__MASK 0x003F0000L
-#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__MASK 0xFF000000L
-//PCIE_VC0_RESOURCE_CNTL
-#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__MASK 0x00000001L
-#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__MASK 0x000000FEL
-#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__MASK 0x00010000L
-#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__MASK 0x000E0000L
-#define PCIE_VC0_RESOURCE_CNTL__VC_ID__MASK 0x07000000L
-#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__MASK 0x80000000L
-//PCIE_VC0_RESOURCE_STATUS
-#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__MASK 0x0001L
-#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__MASK 0x0002L
-//PCIE_VC1_RESOURCE_CAP
-#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__MASK 0x000000FFL
-#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__MASK 0x00008000L
-#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__MASK 0x003F0000L
-#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__MASK 0xFF000000L
-//PCIE_VC1_RESOURCE_CNTL
-#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__MASK 0x00000001L
-#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__MASK 0x000000FEL
-#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__MASK 0x00010000L
-#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__MASK 0x000E0000L
-#define PCIE_VC1_RESOURCE_CNTL__VC_ID__MASK 0x07000000L
-#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__MASK 0x80000000L
-//PCIE_VC1_RESOURCE_STATUS
-#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__MASK 0x0001L
-#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__MASK 0x0002L
-//PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
-#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL
-#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L
-#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L
-//PCIE_DEV_SERIAL_NUM_DW1
-#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__MASK 0xFFFFFFFFL
-//PCIE_DEV_SERIAL_NUM_DW2
-#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__MASK 0xFFFFFFFFL
-//PCIE_ADV_ERR_RPT_ENH_CAP_LIST
-#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL
-#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L
-#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L
-//PCIE_UNCORR_ERR_STATUS
-#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__MASK 0x00000010L
-#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__MASK 0x00000020L
-#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__MASK 0x00001000L
-#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__MASK 0x00002000L
-#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__MASK 0x00004000L
-#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__MASK 0x00008000L
-#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__MASK 0x00010000L
-#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__MASK 0x00020000L
-#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__MASK 0x00040000L
-#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__MASK 0x00080000L
-#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__MASK 0x00100000L
-#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__MASK 0x00200000L
-#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__MASK 0x00400000L
-#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__MASK 0x00800000L
-#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__MASK 0x01000000L
-#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__MASK 0x02000000L
-//PCIE_UNCORR_ERR_MASK
-#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__MASK 0x00000010L
-#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__MASK 0x00000020L
-#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__MASK 0x00001000L
-#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__MASK 0x00002000L
-#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__MASK 0x00004000L
-#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__MASK 0x00008000L
-#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__MASK 0x00010000L
-#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__MASK 0x00020000L
-#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__MASK 0x00040000L
-#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__MASK 0x00080000L
-#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__MASK 0x00100000L
-#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__MASK 0x00200000L
-#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__MASK 0x00400000L
-#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__MASK 0x00800000L
-#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__MASK 0x01000000L
-#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__MASK 0x02000000L
-//PCIE_UNCORR_ERR_SEVERITY
-#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__MASK 0x00000010L
-#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__MASK 0x00000020L
-#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__MASK 0x00001000L
-#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__MASK 0x00002000L
-#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__MASK 0x00004000L
-#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__MASK 0x00008000L
-#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__MASK 0x00010000L
-#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__MASK 0x00020000L
-#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__MASK 0x00040000L
-#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__MASK 0x00080000L
-#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__MASK 0x00100000L
-#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__MASK 0x00200000L
-#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__MASK 0x00400000L
-#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__MASK 0x00800000L
-#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__MASK 0x01000000L
-#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__MASK 0x02000000L
-//PCIE_CORR_ERR_STATUS
-#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__MASK 0x00000001L
-#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__MASK 0x00000040L
-#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__MASK 0x00000080L
-#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__MASK 0x00000100L
-#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__MASK 0x00001000L
-#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__MASK 0x00002000L
-#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__MASK 0x00004000L
-#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__MASK 0x00008000L
-//PCIE_CORR_ERR_MASK
-#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK__MASK 0x00000001L
-#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK__MASK 0x00000040L
-#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__MASK 0x00000080L
-#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__MASK 0x00000100L
-#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__MASK 0x00001000L
-#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__MASK 0x00002000L
-#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__MASK 0x00004000L
-#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__MASK 0x00008000L
-//PCIE_ADV_ERR_CAP_CNTL
-#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__MASK 0x0000001FL
-#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__MASK 0x00000020L
-#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__MASK 0x00000040L
-#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__MASK 0x00000080L
-#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__MASK 0x00000100L
-#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__MASK 0x00000200L
-#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__MASK 0x00000400L
-#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__MASK 0x00000800L
-//PCIE_HDR_LOG0
-#define PCIE_HDR_LOG0__TLP_HDR__MASK 0xFFFFFFFFL
-//PCIE_HDR_LOG1
-#define PCIE_HDR_LOG1__TLP_HDR__MASK 0xFFFFFFFFL
-//PCIE_HDR_LOG2
-#define PCIE_HDR_LOG2__TLP_HDR__MASK 0xFFFFFFFFL
-//PCIE_HDR_LOG3
-#define PCIE_HDR_LOG3__TLP_HDR__MASK 0xFFFFFFFFL
-//PCIE_ROOT_ERR_CMD
-#define PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__MASK 0x00000001L
-#define PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__MASK 0x00000002L
-#define PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__MASK 0x00000004L
-//PCIE_ROOT_ERR_STATUS
-#define PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__MASK 0x00000001L
-#define PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__MASK 0x00000002L
-#define PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__MASK 0x00000004L
-#define PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__MASK 0x00000008L
-#define PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__MASK 0x00000010L
-#define PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__MASK 0x00000020L
-#define PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__MASK 0x00000040L
-#define PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__MASK 0xF8000000L
-//PCIE_ERR_SRC_ID
-#define PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__MASK 0x0000FFFFL
-#define PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__MASK 0xFFFF0000L
-//PCIE_TLP_PREFIX_LOG0
-#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__MASK 0xFFFFFFFFL
-//PCIE_TLP_PREFIX_LOG1
-#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__MASK 0xFFFFFFFFL
-//PCIE_TLP_PREFIX_LOG2
-#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__MASK 0xFFFFFFFFL
-//PCIE_TLP_PREFIX_LOG3
-#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__MASK 0xFFFFFFFFL
-//PCIE_BAR_ENH_CAP_LIST
-#define PCIE_BAR_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL
-#define PCIE_BAR_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L
-#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L
-//PCIE_BAR1_CAP
-#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__MASK 0x00FFFFF0L
-//PCIE_BAR1_CNTL
-#define PCIE_BAR1_CNTL__BAR_INDEX__MASK 0x0007L
-#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM__MASK 0x00E0L
-#define PCIE_BAR1_CNTL__BAR_SIZE__MASK 0x1F00L
-//PCIE_BAR2_CAP
-#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__MASK 0x00FFFFF0L
-//PCIE_BAR2_CNTL
-#define PCIE_BAR2_CNTL__BAR_INDEX__MASK 0x0007L
-#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM__MASK 0x00E0L
-#define PCIE_BAR2_CNTL__BAR_SIZE__MASK 0x1F00L
-//PCIE_BAR3_CAP
-#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__MASK 0x00FFFFF0L
-//PCIE_BAR3_CNTL
-#define PCIE_BAR3_CNTL__BAR_INDEX__MASK 0x0007L
-#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM__MASK 0x00E0L
-#define PCIE_BAR3_CNTL__BAR_SIZE__MASK 0x1F00L
-//PCIE_BAR4_CAP
-#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__MASK 0x00FFFFF0L
-//PCIE_BAR4_CNTL
-#define PCIE_BAR4_CNTL__BAR_INDEX__MASK 0x0007L
-#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM__MASK 0x00E0L
-#define PCIE_BAR4_CNTL__BAR_SIZE__MASK 0x1F00L
-//PCIE_BAR5_CAP
-#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__MASK 0x00FFFFF0L
-//PCIE_BAR5_CNTL
-#define PCIE_BAR5_CNTL__BAR_INDEX__MASK 0x0007L
-#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM__MASK 0x00E0L
-#define PCIE_BAR5_CNTL__BAR_SIZE__MASK 0x1F00L
-//PCIE_BAR6_CAP
-#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__MASK 0x00FFFFF0L
-//PCIE_BAR6_CNTL
-#define PCIE_BAR6_CNTL__BAR_INDEX__MASK 0x0007L
-#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM__MASK 0x00E0L
-#define PCIE_BAR6_CNTL__BAR_SIZE__MASK 0x1F00L
-//PCIE_PWR_BUDGET_ENH_CAP_LIST
-#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL
-#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L
-#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L
-//PCIE_PWR_BUDGET_DATA_SELECT
-#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__MASK 0xFFL
-//PCIE_PWR_BUDGET_DATA
-#define PCIE_PWR_BUDGET_DATA__BASE_POWER__MASK 0x000000FFL
-#define PCIE_PWR_BUDGET_DATA__DATA_SCALE__MASK 0x00000300L
-#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__MASK 0x00001C00L
-#define PCIE_PWR_BUDGET_DATA__PM_STATE__MASK 0x00006000L
-#define PCIE_PWR_BUDGET_DATA__TYPE__MASK 0x00038000L
-#define PCIE_PWR_BUDGET_DATA__POWER_RAIL__MASK 0x001C0000L
-//PCIE_PWR_BUDGET_CAP
-#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__MASK 0x01L
-//PCIE_DPA_ENH_CAP_LIST
-#define PCIE_DPA_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL
-#define PCIE_DPA_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L
-#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L
-//PCIE_DPA_CAP
-#define PCIE_DPA_CAP__SUBSTATE_MAX__MASK 0x0000001FL
-#define PCIE_DPA_CAP__TRANS_LAT_UNIT__MASK 0x00000300L
-#define PCIE_DPA_CAP__PWR_ALLOC_SCALE__MASK 0x00003000L
-#define PCIE_DPA_CAP__TRANS_LAT_VAL_0__MASK 0x00FF0000L
-#define PCIE_DPA_CAP__TRANS_LAT_VAL_1__MASK 0xFF000000L
-//PCIE_DPA_LATENCY_INDICATOR
-#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__MASK 0xFFL
-//PCIE_DPA_STATUS
-#define PCIE_DPA_STATUS__SUBSTATE_STATUS__MASK 0x001FL
-#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__MASK 0x0100L
-//PCIE_DPA_CNTL
-#define PCIE_DPA_CNTL__SUBSTATE_CNTL__MASK 0x1FL
-//PCIE_DPA_SUBSTATE_PWR_ALLOC_0
-#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__MASK 0xFFL
-//PCIE_DPA_SUBSTATE_PWR_ALLOC_1
-#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__MASK 0xFFL
-//PCIE_DPA_SUBSTATE_PWR_ALLOC_2
-#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__MASK 0xFFL
-//PCIE_DPA_SUBSTATE_PWR_ALLOC_3
-#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__MASK 0xFFL
-//PCIE_DPA_SUBSTATE_PWR_ALLOC_4
-#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__MASK 0xFFL
-//PCIE_DPA_SUBSTATE_PWR_ALLOC_5
-#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__MASK 0xFFL
-//PCIE_DPA_SUBSTATE_PWR_ALLOC_6
-#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__MASK 0xFFL
-//PCIE_DPA_SUBSTATE_PWR_ALLOC_7
-#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__MASK 0xFFL
-//PCIE_SECONDARY_ENH_CAP_LIST
-#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL
-#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L
-#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L
-//PCIE_LINK_CNTL3
-#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__MASK 0x00000001L
-#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__MASK 0x00000002L
-#define PCIE_LINK_CNTL3__RESERVED__MASK 0xFFFFFFFCL
-//PCIE_LANE_ERROR_STATUS
-#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__MASK 0x0000FFFFL
-#define PCIE_LANE_ERROR_STATUS__RESERVED__MASK 0xFFFF0000L
-//PCIE_LANE_0_EQUALIZATION_CNTL
-#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL
-#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L
-#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L
-#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L
-#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L
-//PCIE_LANE_1_EQUALIZATION_CNTL
-#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL
-#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L
-#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L
-#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L
-#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L
-//PCIE_LANE_2_EQUALIZATION_CNTL
-#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL
-#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L
-#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L
-#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L
-#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L
-//PCIE_LANE_3_EQUALIZATION_CNTL
-#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL
-#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L
-#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L
-#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L
-#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L
-//PCIE_LANE_4_EQUALIZATION_CNTL
-#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL
-#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L
-#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L
-#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L
-#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L
-//PCIE_LANE_5_EQUALIZATION_CNTL
-#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL
-#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L
-#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L
-#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L
-#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L
-//PCIE_LANE_6_EQUALIZATION_CNTL
-#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL
-#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L
-#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L
-#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L
-#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L
-//PCIE_LANE_7_EQUALIZATION_CNTL
-#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL
-#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L
-#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L
-#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L
-#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L
-//PCIE_LANE_8_EQUALIZATION_CNTL
-#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL
-#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L
-#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L
-#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L
-#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L
-//PCIE_LANE_9_EQUALIZATION_CNTL
-#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL
-#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L
-#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L
-#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L
-#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L
-//PCIE_LANE_10_EQUALIZATION_CNTL
-#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL
-#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L
-#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L
-#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L
-#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L
-//PCIE_LANE_11_EQUALIZATION_CNTL
-#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL
-#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L
-#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L
-#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L
-#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L
-//PCIE_LANE_12_EQUALIZATION_CNTL
-#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL
-#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L
-#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L
-#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L
-#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L
-//PCIE_LANE_13_EQUALIZATION_CNTL
-#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL
-#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L
-#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L
-#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L
-#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L
-//PCIE_LANE_14_EQUALIZATION_CNTL
-#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL
-#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L
-#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L
-#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L
-#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L
-//PCIE_LANE_15_EQUALIZATION_CNTL
-#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL
-#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L
-#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L
-#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L
-#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L
-//PCIE_ACS_ENH_CAP_LIST
-#define PCIE_ACS_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL
-#define PCIE_ACS_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L
-#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L
-//PCIE_ACS_CAP
-#define PCIE_ACS_CAP__SOURCE_VALIDATION__MASK 0x0001L
-#define PCIE_ACS_CAP__TRANSLATION_BLOCKING__MASK 0x0002L
-#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__MASK 0x0004L
-#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__MASK 0x0008L
-#define PCIE_ACS_CAP__UPSTREAM_FORWARDING__MASK 0x0010L
-#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL__MASK 0x0020L
-#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__MASK 0x0040L
-#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__MASK 0xFF00L
-//PCIE_ACS_CNTL
-#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__MASK 0x0001L
-#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__MASK 0x0002L
-#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__MASK 0x0004L
-#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__MASK 0x0008L
-#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__MASK 0x0010L
-#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__MASK 0x0020L
-#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__MASK 0x0040L
-//PCIE_ATS_ENH_CAP_LIST
-#define PCIE_ATS_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL
-#define PCIE_ATS_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L
-#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L
-//PCIE_ATS_CAP
-#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__MASK 0x001FL
-#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__MASK 0x0020L
-#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__MASK 0x0040L
-//PCIE_ATS_CNTL
-#define PCIE_ATS_CNTL__STU__MASK 0x001FL
-#define PCIE_ATS_CNTL__ATC_ENABLE__MASK 0x8000L
-//PCIE_PAGE_REQ_ENH_CAP_LIST
-#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL
-#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L
-#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L
-//PCIE_PAGE_REQ_CNTL
-#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE__MASK 0x0001L
-#define PCIE_PAGE_REQ_CNTL__PRI_RESET__MASK 0x0002L
-//PCIE_PAGE_REQ_STATUS
-#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__MASK 0x0001L
-#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__MASK 0x0002L
-#define PCIE_PAGE_REQ_STATUS__STOPPED__MASK 0x0100L
-#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__MASK 0x8000L
-//PCIE_OUTSTAND_PAGE_REQ_CAPACITY
-#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__MASK 0xFFFFFFFFL
-//PCIE_OUTSTAND_PAGE_REQ_ALLOC
-#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__MASK 0xFFFFFFFFL
-//PCIE_PASID_ENH_CAP_LIST
-#define PCIE_PASID_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL
-#define PCIE_PASID_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L
-#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L
-//PCIE_PASID_CAP
-#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__MASK 0x0002L
-#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__MASK 0x0004L
-#define PCIE_PASID_CAP__MAX_PASID_WIDTH__MASK 0x1F00L
-//PCIE_PASID_CNTL
-#define PCIE_PASID_CNTL__PASID_ENABLE__MASK 0x0001L
-#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__MASK 0x0002L
-#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__MASK 0x0004L
-//PCIE_TPH_REQR_ENH_CAP_LIST
-#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL
-#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L
-#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L
-//PCIE_TPH_REQR_CAP
-#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__MASK 0x00000001L
-#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__MASK 0x00000002L
-#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__MASK 0x00000004L
-#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__MASK 0x00000100L
-#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__MASK 0x00000600L
-#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__MASK 0x07FF0000L
-//PCIE_TPH_REQR_CNTL
-#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__MASK 0x00000007L
-#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN__MASK 0x00000300L
-//PCIE_MC_ENH_CAP_LIST
-#define PCIE_MC_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL
-#define PCIE_MC_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L
-#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L
-//PCIE_MC_CAP
-#define PCIE_MC_CAP__MC_MAX_GROUP__MASK 0x003FL
-#define PCIE_MC_CAP__MC_WIN_SIZE_REQ__MASK 0x3F00L
-#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__MASK 0x8000L
-//PCIE_MC_CNTL
-#define PCIE_MC_CNTL__MC_NUM_GROUP__MASK 0x003FL
-#define PCIE_MC_CNTL__MC_ENABLE__MASK 0x8000L
-//PCIE_MC_ADDR0
-#define PCIE_MC_ADDR0__MC_INDEX_POS__MASK 0x0000003FL
-#define PCIE_MC_ADDR0__MC_BASE_ADDR_0__MASK 0xFFFFF000L
-//PCIE_MC_ADDR1
-#define PCIE_MC_ADDR1__MC_BASE_ADDR_1__MASK 0xFFFFFFFFL
-//PCIE_MC_RCV0
-#define PCIE_MC_RCV0__MC_RECEIVE_0__MASK 0xFFFFFFFFL
-//PCIE_MC_RCV1
-#define PCIE_MC_RCV1__MC_RECEIVE_1__MASK 0xFFFFFFFFL
-//PCIE_MC_BLOCK_ALL0
-#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__MASK 0xFFFFFFFFL
-//PCIE_MC_BLOCK_ALL1
-#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__MASK 0xFFFFFFFFL
-//PCIE_MC_BLOCK_UNTRANSLATED_0
-#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__MASK 0xFFFFFFFFL
-//PCIE_MC_BLOCK_UNTRANSLATED_1
-#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__MASK 0xFFFFFFFFL
-//PCIE_LTR_ENH_CAP_LIST
-#define PCIE_LTR_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL
-#define PCIE_LTR_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L
-#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L
-//PCIE_LTR_CAP
-#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__MASK 0x000003FFL
-#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__MASK 0x00001C00L
-#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__MASK 0x03FF0000L
-#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__MASK 0x1C000000L
-//PCIE_ARI_ENH_CAP_LIST
-#define PCIE_ARI_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL
-#define PCIE_ARI_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L
-#define PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L
-//PCIE_ARI_CAP
-#define PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__MASK 0x0001L
-#define PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__MASK 0x0002L
-#define PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__MASK 0xFF00L
-//PCIE_ARI_CNTL
-#define PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__MASK 0x0001L
-#define PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__MASK 0x0002L
-#define PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__MASK 0x0070L
-//PCIE_SRIOV_ENH_CAP_LIST
-#define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL
-#define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L
-#define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L
-//PCIE_SRIOV_CAP
-#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__MASK 0x00000001L
-#define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__MASK 0x00000002L
-#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__MASK 0xFFE00000L
-//PCIE_SRIOV_CONTROL
-#define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__MASK 0x0001L
-#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__MASK 0x0002L
-#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__MASK 0x0004L
-#define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__MASK 0x0008L
-#define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__MASK 0x0010L
-//PCIE_SRIOV_STATUS
-#define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__MASK 0x0001L
-//PCIE_SRIOV_INITIAL_VFS
-#define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__MASK 0xFFFFL
-//PCIE_SRIOV_TOTAL_VFS
-#define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__MASK 0xFFFFL
-//PCIE_SRIOV_NUM_VFS
-#define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__MASK 0xFFFFL
-//PCIE_SRIOV_FUNC_DEP_LINK
-#define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__MASK 0x00FFL
-//PCIE_SRIOV_FIRST_VF_OFFSET
-#define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__MASK 0xFFFFL
-//PCIE_SRIOV_VF_STRIDE
-#define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__MASK 0xFFFFL
-//PCIE_SRIOV_VF_DEVICE_ID
-#define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__MASK 0xFFFFL
-//PCIE_SRIOV_SUPPORTED_PAGE_SIZE
-#define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__MASK 0xFFFFFFFFL
-//PCIE_SRIOV_SYSTEM_PAGE_SIZE
-#define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__MASK 0xFFFFFFFFL
-//PCIE_SRIOV_VF_BASE_ADDR_0
-#define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__MASK 0xFFFFFFFFL
-//PCIE_SRIOV_VF_BASE_ADDR_1
-#define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__MASK 0xFFFFFFFFL
-//PCIE_SRIOV_VF_BASE_ADDR_2
-#define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__MASK 0xFFFFFFFFL
-//PCIE_SRIOV_VF_BASE_ADDR_3
-#define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__MASK 0xFFFFFFFFL
-//PCIE_SRIOV_VF_BASE_ADDR_4
-#define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__MASK 0xFFFFFFFFL
-//PCIE_SRIOV_VF_BASE_ADDR_5
-#define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__MASK 0xFFFFFFFFL
-//PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
-#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__MASK 0x00000007L
-#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__MASK 0xFFFFFFF8L
-//PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
-#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__MASK 0x0000FFFFL
-#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__MASK 0x000F0000L
-#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__MASK 0xFFF00000L
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__MASK 0x0000FFFFL
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__MASK 0x000F0000L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__MASK 0xFFF00000L
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__MASK 0x00000001L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__MASK 0xFFFF0000L
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__MASK 0x00000001L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__MASK 0x00000002L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__MASK 0x00000004L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__MASK 0x00000008L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__MASK 0x00000100L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__MASK 0x00000200L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__MASK 0x00000400L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__MASK 0x00000800L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__MASK 0x00010000L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__MASK 0x00020000L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__MASK 0x00040000L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__MASK 0x00080000L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__MASK 0x01000000L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__MASK 0x02000000L
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__MASK 0x00000001L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__MASK 0x00000002L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__MASK 0x00000004L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__MASK 0x00000008L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__MASK 0x00000100L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__MASK 0x00000200L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__MASK 0x00000400L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__MASK 0x00000800L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__MASK 0x00010000L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__MASK 0x00020000L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__MASK 0x00040000L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__MASK 0x00080000L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__MASK 0x01000000L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__MASK 0x02000000L
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__MASK 0x0001L
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__MASK 0x000000FFL
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__MASK 0x00000F00L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__MASK 0x00008000L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__MASK 0x000F0000L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__MASK 0x01000000L
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__MASK 0x00000001L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__MASK 0x00000002L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__MASK 0x00000004L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__MASK 0x00000008L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__MASK 0x00000010L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__MASK 0x00000020L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__MASK 0x00000040L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__MASK 0x00000080L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__MASK 0x00000100L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__MASK 0x00000200L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__MASK 0x00000400L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__MASK 0x00000800L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__MASK 0x00001000L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__MASK 0x00002000L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__MASK 0x00004000L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__MASK 0x00008000L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__MASK 0x00010000L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__MASK 0x00020000L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__MASK 0x00040000L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__MASK 0x00080000L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__MASK 0x00100000L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__MASK 0x00200000L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__MASK 0x00400000L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__MASK 0x00800000L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__MASK 0x01000000L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__MASK 0x02000000L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__MASK 0x04000000L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__MASK 0x08000000L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__MASK 0x10000000L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__MASK 0x20000000L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__MASK 0x40000000L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__MASK 0x80000000L
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__MASK 0x00000001L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__MASK 0x00000002L
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__MASK 0x0000007FL
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__MASK 0x00000080L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__MASK 0xFFFFFC00L
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__MASK 0x0000FFFFL
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__MASK 0xFFFF0000L
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__MASK 0x000000FFL
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__MASK 0x0000FF00L
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__MASK 0x00FF0000L
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__MASK 0x0000FFFFL
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__MASK 0xFFFF0000L
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__MASK 0x0000FFFFL
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__MASK 0xFFFF0000L
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__MASK 0x0000FFFFL
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__MASK 0xFFFF0000L
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__MASK 0x0000FFFFL
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__MASK 0xFFFF0000L
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__MASK 0x0000FFFFL
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__MASK 0xFFFF0000L
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__MASK 0x0000FFFFL
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__MASK 0xFFFF0000L
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__MASK 0x0000FFFFL
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__MASK 0xFFFF0000L
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__MASK 0x0000FFFFL
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__MASK 0xFFFF0000L
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__MASK 0x0000FFFFL
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__MASK 0xFFFF0000L
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__MASK 0x0000FFFFL
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__MASK 0xFFFF0000L
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__MASK 0x0000FFFFL
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__MASK 0xFFFF0000L
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__MASK 0x0000FFFFL
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__MASK 0xFFFF0000L
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__MASK 0x0000FFFFL
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__MASK 0xFFFF0000L
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__MASK 0x0000FFFFL
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__MASK 0xFFFF0000L
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__MASK 0x0000FFFFL
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__MASK 0xFFFF0000L
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__MASK 0x0000FFFFL
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__MASK 0xFFFF0000L
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__MASK 0xFFFFFFFFL
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__MASK 0xFFFFFFFFL
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__MASK 0xFFFFFFFFL
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__MASK 0xFFFFFFFFL
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__MASK 0xFFFFFFFFL
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__MASK 0xFFFFFFFFL
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__MASK 0xFFFFFFFFL
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__MASK 0xFFFFFFFFL
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__MASK 0xFFFFFFFFL
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__MASK 0xFFFFFFFFL
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__MASK 0xFFFFFFFFL
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__MASK 0xFFFFFFFFL
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__MASK 0xFFFFFFFFL
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__MASK 0xFFFFFFFFL
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__MASK 0xFFFFFFFFL
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__MASK 0xFFFFFFFFL
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__MASK 0xFFFFFFFFL
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__MASK 0xFFFFFFFFL
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__MASK 0xFFFFFFFFL
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__MASK 0xFFFFFFFFL
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__MASK 0xFFFFFFFFL
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__MASK 0xFFFFFFFFL
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__MASK 0xFFFFFFFFL
-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7
-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__MASK 0xFFFFFFFFL
-
-
-// addressBlock: bif_cfg_dev0_swds_bifcfgdecp
-//SUB_BUS_NUMBER_LATENCY
-#define SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__MASK 0x000000FFL
-#define SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__MASK 0x0000FF00L
-#define SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__MASK 0x00FF0000L
-#define SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__MASK 0xFF000000L
-//IO_BASE_LIMIT
-#define IO_BASE_LIMIT__IO_BASE_TYPE__MASK 0x000FL
-#define IO_BASE_LIMIT__IO_BASE__MASK 0x00F0L
-#define IO_BASE_LIMIT__IO_LIMIT_TYPE__MASK 0x0F00L
-#define IO_BASE_LIMIT__IO_LIMIT__MASK 0xF000L
-//SECONDARY_STATUS
-#define SECONDARY_STATUS__CAP_LIST__MASK 0x0010L
-#define SECONDARY_STATUS__PCI_66_EN__MASK 0x0020L
-#define SECONDARY_STATUS__FAST_BACK_CAPABLE__MASK 0x0080L
-#define SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__MASK 0x0100L
-#define SECONDARY_STATUS__DEVSEL_TIMING__MASK 0x0600L
-#define SECONDARY_STATUS__SIGNAL_TARGET_ABORT__MASK 0x0800L
-#define SECONDARY_STATUS__RECEIVED_TARGET_ABORT__MASK 0x1000L
-#define SECONDARY_STATUS__RECEIVED_MASTER_ABORT__MASK 0x2000L
-#define SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__MASK 0x4000L
-#define SECONDARY_STATUS__PARITY_ERROR_DETECTED__MASK 0x8000L
-//MEM_BASE_LIMIT
-#define MEM_BASE_LIMIT__MEM_BASE_TYPE__MASK 0x0000000FL
-#define MEM_BASE_LIMIT__MEM_BASE_31_20__MASK 0x0000FFF0L
-#define MEM_BASE_LIMIT__MEM_LIMIT_TYPE__MASK 0x000F0000L
-#define MEM_BASE_LIMIT__MEM_LIMIT_31_20__MASK 0xFFF00000L
-//PREF_BASE_LIMIT
-#define PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__MASK 0x0000000FL
-#define PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__MASK 0x0000FFF0L
-#define PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__MASK 0x000F0000L
-#define PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__MASK 0xFFF00000L
-//PREF_BASE_UPPER
-#define PREF_BASE_UPPER__PREF_BASE_UPPER__MASK 0xFFFFFFFFL
-//PREF_LIMIT_UPPER
-#define PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__MASK 0xFFFFFFFFL
-//IO_BASE_LIMIT_HI
-#define IO_BASE_LIMIT_HI__IO_BASE_31_16__MASK 0x0000FFFFL
-#define IO_BASE_LIMIT_HI__IO_LIMIT_31_16__MASK 0xFFFF0000L
-//IRQ_BRIDGE_CNTL
-#define IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__MASK 0x0001L
-#define IRQ_BRIDGE_CNTL__SERR_EN__MASK 0x0002L
-#define IRQ_BRIDGE_CNTL__ISA_EN__MASK 0x0004L
-#define IRQ_BRIDGE_CNTL__VGA_EN__MASK 0x0008L
-#define IRQ_BRIDGE_CNTL__VGA_DEC__MASK 0x0010L
-#define IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__MASK 0x0020L
-#define IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__MASK 0x0040L
-#define IRQ_BRIDGE_CNTL__FAST_B2B_EN__MASK 0x0080L
-//SLOT_CAP
-#define SLOT_CAP__ATTN_BUTTON_PRESENT__MASK 0x00000001L
-#define SLOT_CAP__PWR_CONTROLLER_PRESENT__MASK 0x00000002L
-#define SLOT_CAP__MRL_SENSOR_PRESENT__MASK 0x00000004L
-#define SLOT_CAP__ATTN_INDICATOR_PRESENT__MASK 0x00000008L
-#define SLOT_CAP__PWR_INDICATOR_PRESENT__MASK 0x00000010L
-#define SLOT_CAP__HOTPLUG_SURPRISE__MASK 0x00000020L
-#define SLOT_CAP__HOTPLUG_CAPABLE__MASK 0x00000040L
-#define SLOT_CAP__SLOT_PWR_LIMIT_VALUE__MASK 0x00007F80L
-#define SLOT_CAP__SLOT_PWR_LIMIT_SCALE__MASK 0x00018000L
-#define SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__MASK 0x00020000L
-#define SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__MASK 0x00040000L
-#define SLOT_CAP__PHYSICAL_SLOT_NUM__MASK 0xFFF80000L
-//SLOT_CNTL
-#define SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__MASK 0x0001L
-#define SLOT_CNTL__PWR_FAULT_DETECTED_EN__MASK 0x0002L
-#define SLOT_CNTL__MRL_SENSOR_CHANGED_EN__MASK 0x0004L
-#define SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__MASK 0x0008L
-#define SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__MASK 0x0010L
-#define SLOT_CNTL__HOTPLUG_INTR_EN__MASK 0x0020L
-#define SLOT_CNTL__ATTN_INDICATOR_CNTL__MASK 0x00C0L
-#define SLOT_CNTL__PWR_INDICATOR_CNTL__MASK 0x0300L
-#define SLOT_CNTL__PWR_CONTROLLER_CNTL__MASK 0x0400L
-#define SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__MASK 0x0800L
-#define SLOT_CNTL__DL_STATE_CHANGED_EN__MASK 0x1000L
-//SLOT_STATUS
-#define SLOT_STATUS__ATTN_BUTTON_PRESSED__MASK 0x0001L
-#define SLOT_STATUS__PWR_FAULT_DETECTED__MASK 0x0002L
-#define SLOT_STATUS__MRL_SENSOR_CHANGED__MASK 0x0004L
-#define SLOT_STATUS__PRESENCE_DETECT_CHANGED__MASK 0x0008L
-#define SLOT_STATUS__COMMAND_COMPLETED__MASK 0x0010L
-#define SLOT_STATUS__MRL_SENSOR_STATE__MASK 0x0020L
-#define SLOT_STATUS__PRESENCE_DETECT_STATE__MASK 0x0040L
-#define SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__MASK 0x0080L
-#define SLOT_STATUS__DL_STATE_CHANGED__MASK 0x0100L
-//SSID_CAP_LIST
-#define SSID_CAP_LIST__CAP_ID__MASK 0x00FFL
-#define SSID_CAP_LIST__NEXT_PTR__MASK 0xFF00L
-//SSID_CAP
-#define SSID_CAP__SUBSYSTEM_VENDOR_ID__MASK 0x0000FFFFL
-#define SSID_CAP__SUBSYSTEM_ID__MASK 0xFFFF0000L
-
-
-// addressBlock: rcc_shadow_reg_shadowdec
-//SHADOW_COMMAND
-#define SHADOW_COMMAND__IOEN_UP__MASK 0x0001L
-#define SHADOW_COMMAND__MEMEN_UP__MASK 0x0002L
-//SHADOW_BASE_ADDR_1
-#define SHADOW_BASE_ADDR_1__BAR1_UP__MASK 0xFFFFFFFFL
-//SHADOW_BASE_ADDR_2
-#define SHADOW_BASE_ADDR_2__BAR2_UP__MASK 0xFFFFFFFFL
-//SHADOW_SUB_BUS_NUMBER_LATENCY
-#define SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP__MASK 0x0000FF00L
-#define SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP__MASK 0x00FF0000L
-//SHADOW_IO_BASE_LIMIT
-#define SHADOW_IO_BASE_LIMIT__IO_BASE_UP__MASK 0x00F0L
-#define SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP__MASK 0xF000L
-//SHADOW_MEM_BASE_LIMIT
-#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE__MASK 0x0000000FL
-#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP__MASK 0x0000FFF0L
-#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__MASK 0x000F0000L
-#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP__MASK 0xFFF00000L
-//SHADOW_PREF_BASE_LIMIT
-#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__MASK 0x0000000FL
-#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP__MASK 0x0000FFF0L
-#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__MASK 0x000F0000L
-#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP__MASK 0xFFF00000L
-//SHADOW_PREF_BASE_UPPER
-#define SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP__MASK 0xFFFFFFFFL
-//SHADOW_PREF_LIMIT_UPPER
-#define SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP__MASK 0xFFFFFFFFL
-//SHADOW_IO_BASE_LIMIT_HI
-#define SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP__MASK 0x0000FFFFL
-#define SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP__MASK 0xFFFF0000L
-//SHADOW_IRQ_BRIDGE_CNTL
-#define SHADOW_IRQ_BRIDGE_CNTL__ISA_EN_UP__MASK 0x0004L
-#define SHADOW_IRQ_BRIDGE_CNTL__VGA_EN_UP__MASK 0x0008L
-#define SHADOW_IRQ_BRIDGE_CNTL__VGA_DEC_UP__MASK 0x0010L
-#define SHADOW_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_UP__MASK 0x0040L
-//SUC_INDEX
-#define SUC_INDEX__SUC_INDEX__MASK 0xFFFFFFFFL
-//SUC_DATA
-#define SUC_DATA__SUC_DATA__MASK 0xFFFFFFFFL
-
-
-// addressBlock: bif_bx_pf_SUMDEC
-//SUM_INDEX
-#define SUM_INDEX__SUM_INDEX__MASK 0xFFFFFFFFL
-//SUM_DATA
-#define SUM_DATA__SUM_DATA__MASK 0xFFFFFFFFL
-
-
-// addressBlock: gdc_GDCDEC
-//A2S_CNTL_CL0
-#define A2S_CNTL_CL0__NSNOOP_MAP__MASK 0x00000003L
-#define A2S_CNTL_CL0__REQPASSPW_VC0_MAP__MASK 0x0000000CL
-#define A2S_CNTL_CL0__REQPASSPW_NVC0_MAP__MASK 0x00000030L
-#define A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP__MASK 0x000000C0L
-#define A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP__MASK 0x00000300L
-#define A2S_CNTL_CL0__BLKLVL_MAP__MASK 0x00000C00L
-#define A2S_CNTL_CL0__DATERR_MAP__MASK 0x00003000L
-#define A2S_CNTL_CL0__EXOKAY_WR_MAP__MASK 0x0000C000L
-#define A2S_CNTL_CL0__EXOKAY_RD_MAP__MASK 0x00030000L
-#define A2S_CNTL_CL0__RESP_WR_MAP__MASK 0x000C0000L
-#define A2S_CNTL_CL0__RESP_RD_MAP__MASK 0x00300000L
-//A2S_CNTL_CL1
-#define A2S_CNTL_CL1__NSNOOP_MAP__MASK 0x00000003L
-#define A2S_CNTL_CL1__REQPASSPW_VC0_MAP__MASK 0x0000000CL
-#define A2S_CNTL_CL1__REQPASSPW_NVC0_MAP__MASK 0x00000030L
-#define A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP__MASK 0x000000C0L
-#define A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP__MASK 0x00000300L
-#define A2S_CNTL_CL1__BLKLVL_MAP__MASK 0x00000C00L
-#define A2S_CNTL_CL1__DATERR_MAP__MASK 0x00003000L
-#define A2S_CNTL_CL1__EXOKAY_WR_MAP__MASK 0x0000C000L
-#define A2S_CNTL_CL1__EXOKAY_RD_MAP__MASK 0x00030000L
-#define A2S_CNTL_CL1__RESP_WR_MAP__MASK 0x000C0000L
-#define A2S_CNTL_CL1__RESP_RD_MAP__MASK 0x00300000L
-//A2S_CNTL_CL2
-#define A2S_CNTL_CL2__NSNOOP_MAP__MASK 0x00000003L
-#define A2S_CNTL_CL2__REQPASSPW_VC0_MAP__MASK 0x0000000CL
-#define A2S_CNTL_CL2__REQPASSPW_NVC0_MAP__MASK 0x00000030L
-#define A2S_CNTL_CL2__REQRSPPASSPW_VC0_MAP__MASK 0x000000C0L
-#define A2S_CNTL_CL2__REQRSPPASSPW_NVC0_MAP__MASK 0x00000300L
-#define A2S_CNTL_CL2__BLKLVL_MAP__MASK 0x00000C00L
-#define A2S_CNTL_CL2__DATERR_MAP__MASK 0x00003000L
-#define A2S_CNTL_CL2__EXOKAY_WR_MAP__MASK 0x0000C000L
-#define A2S_CNTL_CL2__EXOKAY_RD_MAP__MASK 0x00030000L
-#define A2S_CNTL_CL2__RESP_WR_MAP__MASK 0x000C0000L
-#define A2S_CNTL_CL2__RESP_RD_MAP__MASK 0x00300000L
-//A2S_CNTL_CL3
-#define A2S_CNTL_CL3__NSNOOP_MAP__MASK 0x00000003L
-#define A2S_CNTL_CL3__REQPASSPW_VC0_MAP__MASK 0x0000000CL
-#define A2S_CNTL_CL3__REQPASSPW_NVC0_MAP__MASK 0x00000030L
-#define A2S_CNTL_CL3__REQRSPPASSPW_VC0_MAP__MASK 0x000000C0L
-#define A2S_CNTL_CL3__REQRSPPASSPW_NVC0_MAP__MASK 0x00000300L
-#define A2S_CNTL_CL3__BLKLVL_MAP__MASK 0x00000C00L
-#define A2S_CNTL_CL3__DATERR_MAP__MASK 0x00003000L
-#define A2S_CNTL_CL3__EXOKAY_WR_MAP__MASK 0x0000C000L
-#define A2S_CNTL_CL3__EXOKAY_RD_MAP__MASK 0x00030000L
-#define A2S_CNTL_CL3__RESP_WR_MAP__MASK 0x000C0000L
-#define A2S_CNTL_CL3__RESP_RD_MAP__MASK 0x00300000L
-//A2S_CNTL_CL4
-#define A2S_CNTL_CL4__NSNOOP_MAP__MASK 0x00000003L
-#define A2S_CNTL_CL4__REQPASSPW_VC0_MAP__MASK 0x0000000CL
-#define A2S_CNTL_CL4__REQPASSPW_NVC0_MAP__MASK 0x00000030L
-#define A2S_CNTL_CL4__REQRSPPASSPW_VC0_MAP__MASK 0x000000C0L
-#define A2S_CNTL_CL4__REQRSPPASSPW_NVC0_MAP__MASK 0x00000300L
-#define A2S_CNTL_CL4__BLKLVL_MAP__MASK 0x00000C00L
-#define A2S_CNTL_CL4__DATERR_MAP__MASK 0x00003000L
-#define A2S_CNTL_CL4__EXOKAY_WR_MAP__MASK 0x0000C000L
-#define A2S_CNTL_CL4__EXOKAY_RD_MAP__MASK 0x00030000L
-#define A2S_CNTL_CL4__RESP_WR_MAP__MASK 0x000C0000L
-#define A2S_CNTL_CL4__RESP_RD_MAP__MASK 0x00300000L
-//A2S_CNTL_SW0
-#define A2S_CNTL_SW0__WR_TAG_SET_MIN__MASK 0x00000007L
-#define A2S_CNTL_SW0__RD_TAG_SET_MIN__MASK 0x00000038L
-#define A2S_CNTL_SW0__FORCE_RSP_REORDER_EN__MASK 0x00000040L
-#define A2S_CNTL_SW0__RSP_REORDER_DIS__MASK 0x00000080L
-#define A2S_CNTL_SW0__WRRSP_ACCUM_SEL__MASK 0x00000100L
-#define A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__MASK 0x00000200L
-#define A2S_CNTL_SW0__WRRSP_TAGFIFO_CONT_RD_DIS__MASK 0x00000400L
-#define A2S_CNTL_SW0__RDRSP_TAGFIFO_CONT_RD_DIS__MASK 0x00000800L
-#define A2S_CNTL_SW0__RDRSP_STS_DATSTS_PRIORITY__MASK 0x00001000L
-#define A2S_CNTL_SW0__WRR_RD_WEIGHT__MASK 0x00FF0000L
-#define A2S_CNTL_SW0__WRR_WR_WEIGHT__MASK 0xFF000000L
-//A2S_CNTL_SW1
-#define A2S_CNTL_SW1__WR_TAG_SET_MIN__MASK 0x00000007L
-#define A2S_CNTL_SW1__RD_TAG_SET_MIN__MASK 0x00000038L
-#define A2S_CNTL_SW1__FORCE_RSP_REORDER_EN__MASK 0x00000040L
-#define A2S_CNTL_SW1__RSP_REORDER_DIS__MASK 0x00000080L
-#define A2S_CNTL_SW1__WRRSP_ACCUM_SEL__MASK 0x00000100L
-#define A2S_CNTL_SW1__SDP_WR_CHAIN_DIS__MASK 0x00000200L
-#define A2S_CNTL_SW1__WRRSP_TAGFIFO_CONT_RD_DIS__MASK 0x00000400L
-#define A2S_CNTL_SW1__RDRSP_TAGFIFO_CONT_RD_DIS__MASK 0x00000800L
-#define A2S_CNTL_SW1__RDRSP_STS_DATSTS_PRIORITY__MASK 0x00001000L
-#define A2S_CNTL_SW1__WRR_RD_WEIGHT__MASK 0x00FF0000L
-#define A2S_CNTL_SW1__WRR_WR_WEIGHT__MASK 0xFF000000L
-//A2S_CNTL_SW2
-#define A2S_CNTL_SW2__WR_TAG_SET_MIN__MASK 0x00000007L
-#define A2S_CNTL_SW2__RD_TAG_SET_MIN__MASK 0x00000038L
-#define A2S_CNTL_SW2__FORCE_RSP_REORDER_EN__MASK 0x00000040L
-#define A2S_CNTL_SW2__RSP_REORDER_DIS__MASK 0x00000080L
-#define A2S_CNTL_SW2__WRRSP_ACCUM_SEL__MASK 0x00000100L
-#define A2S_CNTL_SW2__SDP_WR_CHAIN_DIS__MASK 0x00000200L
-#define A2S_CNTL_SW2__WRRSP_TAGFIFO_CONT_RD_DIS__MASK 0x00000400L
-#define A2S_CNTL_SW2__RDRSP_TAGFIFO_CONT_RD_DIS__MASK 0x00000800L
-#define A2S_CNTL_SW2__RDRSP_STS_DATSTS_PRIORITY__MASK 0x00001000L
-#define A2S_CNTL_SW2__WRR_RD_WEIGHT__MASK 0x00FF0000L
-#define A2S_CNTL_SW2__WRR_WR_WEIGHT__MASK 0xFF000000L
-//NGDC_MGCG_CTRL
-#define NGDC_MGCG_CTRL__NGDC_MGCG_EN__MASK 0x00000001L
-#define NGDC_MGCG_CTRL__NGDC_MGCG_MODE__MASK 0x00000002L
-#define NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__MASK 0x000003FCL
-//A2S_MISC_CNTL
-#define A2S_MISC_CNTL__BLKLVL_FOR_MSG__MASK 0x00000003L
-#define A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS__MASK 0x00000004L
-//NGDC_SDP_PORT_CTRL
-#define NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__MASK 0x0000003FL
-//NGDC_RESERVED_0
-#define NGDC_RESERVED_0__RESERVED__MASK 0xFFFFFFFFL
-//NGDC_RESERVED_1
-#define NGDC_RESERVED_1__RESERVED__MASK 0xFFFFFFFFL
-//BIF_SDMA0_DOORBELL_RANGE
-#define BIF_SDMA0_DOORBELL_RANGE__OFFSET__MASK 0x00000FFCL
-#define BIF_SDMA0_DOORBELL_RANGE__SIZE__MASK 0x001F0000L
-//BIF_SDMA1_DOORBELL_RANGE
-#define BIF_SDMA1_DOORBELL_RANGE__OFFSET__MASK 0x00000FFCL
-#define BIF_SDMA1_DOORBELL_RANGE__SIZE__MASK 0x001F0000L
-//BIF_IH_DOORBELL_RANGE
-#define BIF_IH_DOORBELL_RANGE__OFFSET__MASK 0x00000FFCL
-#define BIF_IH_DOORBELL_RANGE__SIZE__MASK 0x001F0000L
-//BIF_MMSCH0_DOORBELL_RANGE
-#define BIF_MMSCH0_DOORBELL_RANGE__OFFSET__MASK 0x00000FFCL
-#define BIF_MMSCH0_DOORBELL_RANGE__SIZE__MASK 0x001F0000L
-//BIF_DOORBELL_FENCE_CNTL
-#define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE__MASK 0x00000001L
-//S2A_MISC_CNTL
-#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__MASK 0x00000001L
-#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__MASK 0x00000002L
-#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__MASK 0x00000004L
-//A2S_CNTL2_SEC_CL0
-#define A2S_CNTL2_SEC_CL0__SECLVL_MAP__MASK 0x00000007L
-//A2S_CNTL2_SEC_CL1
-#define A2S_CNTL2_SEC_CL1__SECLVL_MAP__MASK 0x00000007L
-//A2S_CNTL2_SEC_CL2
-#define A2S_CNTL2_SEC_CL2__SECLVL_MAP__MASK 0x00000007L
-//A2S_CNTL2_SEC_CL3
-#define A2S_CNTL2_SEC_CL3__SECLVL_MAP__MASK 0x00000007L
-//A2S_CNTL2_SEC_CL4
-#define A2S_CNTL2_SEC_CL4__SECLVL_MAP__MASK 0x00000007L
-
-
-// addressBlock: nbif_sion_SIONDEC
-//SION_CL0_RdRsp_BurstTarget_REG0
-#define SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL
-//SION_CL0_RdRsp_BurstTarget_REG1
-#define SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL
-//SION_CL0_RdRsp_TimeSlot_REG0
-#define SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL
-//SION_CL0_RdRsp_TimeSlot_REG1
-#define SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL
-//SION_CL0_WrRsp_BurstTarget_REG0
-#define SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL
-//SION_CL0_WrRsp_BurstTarget_REG1
-#define SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL
-//SION_CL0_WrRsp_TimeSlot_REG0
-#define SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL
-//SION_CL0_WrRsp_TimeSlot_REG1
-#define SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL
-//SION_CL0_Req_BurstTarget_REG0
-#define SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__MASK 0xFFFFFFFFL
-//SION_CL0_Req_BurstTarget_REG1
-#define SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__MASK 0xFFFFFFFFL
-//SION_CL0_Req_TimeSlot_REG0
-#define SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__MASK 0xFFFFFFFFL
-//SION_CL0_Req_TimeSlot_REG1
-#define SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__MASK 0xFFFFFFFFL
-//SION_CL0_ReqPoolCredit_Alloc_REG0
-#define SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
-//SION_CL0_ReqPoolCredit_Alloc_REG1
-#define SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
-//SION_CL0_DataPoolCredit_Alloc_REG0
-#define SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
-//SION_CL0_DataPoolCredit_Alloc_REG1
-#define SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
-//SION_CL0_RdRspPoolCredit_Alloc_REG0
-#define SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
-//SION_CL0_RdRspPoolCredit_Alloc_REG1
-#define SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
-//SION_CL0_WrRspPoolCredit_Alloc_REG0
-#define SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
-//SION_CL0_WrRspPoolCredit_Alloc_REG1
-#define SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
-//SION_CL1_RdRsp_BurstTarget_REG0
-#define SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL
-//SION_CL1_RdRsp_BurstTarget_REG1
-#define SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL
-//SION_CL1_RdRsp_TimeSlot_REG0
-#define SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL
-//SION_CL1_RdRsp_TimeSlot_REG1
-#define SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL
-//SION_CL1_WrRsp_BurstTarget_REG0
-#define SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL
-//SION_CL1_WrRsp_BurstTarget_REG1
-#define SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL
-//SION_CL1_WrRsp_TimeSlot_REG0
-#define SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL
-//SION_CL1_WrRsp_TimeSlot_REG1
-#define SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL
-//SION_CL1_Req_BurstTarget_REG0
-#define SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__MASK 0xFFFFFFFFL
-//SION_CL1_Req_BurstTarget_REG1
-#define SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__MASK 0xFFFFFFFFL
-//SION_CL1_Req_TimeSlot_REG0
-#define SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__MASK 0xFFFFFFFFL
-//SION_CL1_Req_TimeSlot_REG1
-#define SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__MASK 0xFFFFFFFFL
-//SION_CL1_ReqPoolCredit_Alloc_REG0
-#define SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
-//SION_CL1_ReqPoolCredit_Alloc_REG1
-#define SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
-//SION_CL1_DataPoolCredit_Alloc_REG0
-#define SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
-//SION_CL1_DataPoolCredit_Alloc_REG1
-#define SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
-//SION_CL1_RdRspPoolCredit_Alloc_REG0
-#define SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
-//SION_CL1_RdRspPoolCredit_Alloc_REG1
-#define SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
-//SION_CL1_WrRspPoolCredit_Alloc_REG0
-#define SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
-//SION_CL1_WrRspPoolCredit_Alloc_REG1
-#define SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
-//SION_CL2_RdRsp_BurstTarget_REG0
-#define SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL
-//SION_CL2_RdRsp_BurstTarget_REG1
-#define SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL
-//SION_CL2_RdRsp_TimeSlot_REG0
-#define SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL
-//SION_CL2_RdRsp_TimeSlot_REG1
-#define SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL
-//SION_CL2_WrRsp_BurstTarget_REG0
-#define SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL
-//SION_CL2_WrRsp_BurstTarget_REG1
-#define SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL
-//SION_CL2_WrRsp_TimeSlot_REG0
-#define SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL
-//SION_CL2_WrRsp_TimeSlot_REG1
-#define SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL
-//SION_CL2_Req_BurstTarget_REG0
-#define SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0__MASK 0xFFFFFFFFL
-//SION_CL2_Req_BurstTarget_REG1
-#define SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32__MASK 0xFFFFFFFFL
-//SION_CL2_Req_TimeSlot_REG0
-#define SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0__MASK 0xFFFFFFFFL
-//SION_CL2_Req_TimeSlot_REG1
-#define SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32__MASK 0xFFFFFFFFL
-//SION_CL2_ReqPoolCredit_Alloc_REG0
-#define SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
-//SION_CL2_ReqPoolCredit_Alloc_REG1
-#define SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
-//SION_CL2_DataPoolCredit_Alloc_REG0
-#define SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
-//SION_CL2_DataPoolCredit_Alloc_REG1
-#define SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
-//SION_CL2_RdRspPoolCredit_Alloc_REG0
-#define SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
-//SION_CL2_RdRspPoolCredit_Alloc_REG1
-#define SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
-//SION_CL2_WrRspPoolCredit_Alloc_REG0
-#define SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
-//SION_CL2_WrRspPoolCredit_Alloc_REG1
-#define SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
-//SION_CL3_RdRsp_BurstTarget_REG0
-#define SION_CL3_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL
-//SION_CL3_RdRsp_BurstTarget_REG1
-#define SION_CL3_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL
-//SION_CL3_RdRsp_TimeSlot_REG0
-#define SION_CL3_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL
-//SION_CL3_RdRsp_TimeSlot_REG1
-#define SION_CL3_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL
-//SION_CL3_WrRsp_BurstTarget_REG0
-#define SION_CL3_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL
-//SION_CL3_WrRsp_BurstTarget_REG1
-#define SION_CL3_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL
-//SION_CL3_WrRsp_TimeSlot_REG0
-#define SION_CL3_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL
-//SION_CL3_WrRsp_TimeSlot_REG1
-#define SION_CL3_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL
-//SION_CL3_Req_BurstTarget_REG0
-#define SION_CL3_Req_BurstTarget_REG0__Req_BurstTarget_31_0__MASK 0xFFFFFFFFL
-//SION_CL3_Req_BurstTarget_REG1
-#define SION_CL3_Req_BurstTarget_REG1__Req_BurstTarget_63_32__MASK 0xFFFFFFFFL
-//SION_CL3_Req_TimeSlot_REG0
-#define SION_CL3_Req_TimeSlot_REG0__Req_TimeSlot_31_0__MASK 0xFFFFFFFFL
-//SION_CL3_Req_TimeSlot_REG1
-#define SION_CL3_Req_TimeSlot_REG1__Req_TimeSlot_63_32__MASK 0xFFFFFFFFL
-//SION_CL3_ReqPoolCredit_Alloc_REG0
-#define SION_CL3_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
-//SION_CL3_ReqPoolCredit_Alloc_REG1
-#define SION_CL3_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
-//SION_CL3_DataPoolCredit_Alloc_REG0
-#define SION_CL3_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
-//SION_CL3_DataPoolCredit_Alloc_REG1
-#define SION_CL3_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
-//SION_CL3_RdRspPoolCredit_Alloc_REG0
-#define SION_CL3_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
-//SION_CL3_RdRspPoolCredit_Alloc_REG1
-#define SION_CL3_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
-//SION_CL3_WrRspPoolCredit_Alloc_REG0
-#define SION_CL3_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
-//SION_CL3_WrRspPoolCredit_Alloc_REG1
-#define SION_CL3_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
-//SION_CL4_RdRsp_BurstTarget_REG0
-#define SION_CL4_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL
-//SION_CL4_RdRsp_BurstTarget_REG1
-#define SION_CL4_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL
-//SION_CL4_RdRsp_TimeSlot_REG0
-#define SION_CL4_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL
-//SION_CL4_RdRsp_TimeSlot_REG1
-#define SION_CL4_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL
-//SION_CL4_WrRsp_BurstTarget_REG0
-#define SION_CL4_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL
-//SION_CL4_WrRsp_BurstTarget_REG1
-#define SION_CL4_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL
-//SION_CL4_WrRsp_TimeSlot_REG0
-#define SION_CL4_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL
-//SION_CL4_WrRsp_TimeSlot_REG1
-#define SION_CL4_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL
-//SION_CL4_Req_BurstTarget_REG0
-#define SION_CL4_Req_BurstTarget_REG0__Req_BurstTarget_31_0__MASK 0xFFFFFFFFL
-//SION_CL4_Req_BurstTarget_REG1
-#define SION_CL4_Req_BurstTarget_REG1__Req_BurstTarget_63_32__MASK 0xFFFFFFFFL
-//SION_CL4_Req_TimeSlot_REG0
-#define SION_CL4_Req_TimeSlot_REG0__Req_TimeSlot_31_0__MASK 0xFFFFFFFFL
-//SION_CL4_Req_TimeSlot_REG1
-#define SION_CL4_Req_TimeSlot_REG1__Req_TimeSlot_63_32__MASK 0xFFFFFFFFL
-//SION_CL4_ReqPoolCredit_Alloc_REG0
-#define SION_CL4_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
-//SION_CL4_ReqPoolCredit_Alloc_REG1
-#define SION_CL4_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
-//SION_CL4_DataPoolCredit_Alloc_REG0
-#define SION_CL4_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
-//SION_CL4_DataPoolCredit_Alloc_REG1
-#define SION_CL4_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
-//SION_CL4_RdRspPoolCredit_Alloc_REG0
-#define SION_CL4_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
-//SION_CL4_RdRspPoolCredit_Alloc_REG1
-#define SION_CL4_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
-//SION_CL4_WrRspPoolCredit_Alloc_REG0
-#define SION_CL4_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
-//SION_CL4_WrRspPoolCredit_Alloc_REG1
-#define SION_CL4_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
-//SION_CL5_RdRsp_BurstTarget_REG0
-#define SION_CL5_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL
-//SION_CL5_RdRsp_BurstTarget_REG1
-#define SION_CL5_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL
-//SION_CL5_RdRsp_TimeSlot_REG0
-#define SION_CL5_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL
-//SION_CL5_RdRsp_TimeSlot_REG1
-#define SION_CL5_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL
-//SION_CL5_WrRsp_BurstTarget_REG0
-#define SION_CL5_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL
-//SION_CL5_WrRsp_BurstTarget_REG1
-#define SION_CL5_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL
-//SION_CL5_WrRsp_TimeSlot_REG0
-#define SION_CL5_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL
-//SION_CL5_WrRsp_TimeSlot_REG1
-#define SION_CL5_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL
-//SION_CL5_Req_BurstTarget_REG0
-#define SION_CL5_Req_BurstTarget_REG0__Req_BurstTarget_31_0__MASK 0xFFFFFFFFL
-//SION_CL5_Req_BurstTarget_REG1
-#define SION_CL5_Req_BurstTarget_REG1__Req_BurstTarget_63_32__MASK 0xFFFFFFFFL
-//SION_CL5_Req_TimeSlot_REG0
-#define SION_CL5_Req_TimeSlot_REG0__Req_TimeSlot_31_0__MASK 0xFFFFFFFFL
-//SION_CL5_Req_TimeSlot_REG1
-#define SION_CL5_Req_TimeSlot_REG1__Req_TimeSlot_63_32__MASK 0xFFFFFFFFL
-//SION_CL5_ReqPoolCredit_Alloc_REG0
-#define SION_CL5_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
-//SION_CL5_ReqPoolCredit_Alloc_REG1
-#define SION_CL5_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
-//SION_CL5_DataPoolCredit_Alloc_REG0
-#define SION_CL5_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
-//SION_CL5_DataPoolCredit_Alloc_REG1
-#define SION_CL5_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
-//SION_CL5_RdRspPoolCredit_Alloc_REG0
-#define SION_CL5_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
-//SION_CL5_RdRspPoolCredit_Alloc_REG1
-#define SION_CL5_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
-//SION_CL5_WrRspPoolCredit_Alloc_REG0
-#define SION_CL5_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL
-//SION_CL5_WrRspPoolCredit_Alloc_REG1
-#define SION_CL5_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL
-//SION_CNTL_REG0
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__MASK 0x00000001L
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__MASK 0x00000002L
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__MASK 0x00000004L
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__MASK 0x00000008L
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__MASK 0x00000010L
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__MASK 0x00000020L
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__MASK 0x00000040L
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__MASK 0x00000080L
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__MASK 0x00000100L
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__MASK 0x00000200L
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__MASK 0x00000400L
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__MASK 0x00000800L
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__MASK 0x00001000L
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__MASK 0x00002000L
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__MASK 0x00004000L
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__MASK 0x00008000L
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__MASK 0x00010000L
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__MASK 0x00020000L
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__MASK 0x00040000L
-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__MASK 0x00080000L
-//SION_CNTL_REG1
-#define SION_CNTL_REG1__LIVELOCK_WATCHDOG_THRESHOLD__MASK 0x000000FFL
-#define SION_CNTL_REG1__CG_OFF_HYSTERESIS__MASK 0x0000FF00L
-
-
-// addressBlock: syshub_mmreg_direct_syshubdirect
-//SYSHUB_DS_CTRL_SOCCLK
-#define SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000001L
-#define SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000002L
-#define SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000004L
-#define SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000008L
-#define SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000010L
-#define SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000020L
-#define SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000040L
-#define SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000080L
-#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00010000L
-#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00020000L
-#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00040000L
-#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00080000L
-#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00100000L
-#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00200000L
-#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00400000L
-#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00800000L
-#define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x10000000L
-#define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__MASK 0x80000000L
-//SYSHUB_DS_CTRL2_SOCCLK
-#define SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__MASK 0x0000FFFFL
-//SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK
-#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en__MASK 0x00000001L
-#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en__MASK 0x00000002L
-#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__MASK 0x00008000L
-#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__MASK 0x00010000L
-#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__MASK 0x00020000L
-//SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK
-#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en__MASK 0x00000001L
-#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en__MASK 0x00000002L
-#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__MASK 0x00008000L
-#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__MASK 0x00010000L
-#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__MASK 0x00020000L
-//DMA_CLK0_SW0_SYSHUB_QOS_CNTL
-#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L
-#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL
-#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L
-//DMA_CLK0_SW1_SYSHUB_QOS_CNTL
-#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L
-#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL
-#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L
-//DMA_CLK0_SW0_CL0_CNTL
-#define DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
-#define DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
-#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
-#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
-#define DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
-#define DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
-//DMA_CLK0_SW0_CL1_CNTL
-#define DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
-#define DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
-#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
-#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
-#define DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
-#define DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
-//DMA_CLK0_SW0_CL2_CNTL
-#define DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
-#define DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
-#define DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
-#define DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
-#define DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
-#define DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
-//DMA_CLK0_SW0_CL3_CNTL
-#define DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
-#define DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
-#define DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
-#define DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
-#define DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
-#define DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
-//DMA_CLK0_SW0_CL4_CNTL
-#define DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
-#define DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
-#define DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
-#define DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
-#define DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
-#define DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
-//DMA_CLK0_SW0_CL5_CNTL
-#define DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
-#define DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
-#define DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
-#define DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
-#define DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
-#define DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
-//DMA_CLK0_SW1_CL0_CNTL
-#define DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
-#define DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
-#define DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
-#define DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
-#define DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
-#define DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
-//DMA_CLK0_SW2_CL0_CNTL
-#define DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
-#define DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
-#define DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
-#define DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
-#define DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
-#define DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
-//SYSHUB_CG_CNTL
-#define SYSHUB_CG_CNTL__SYSHUB_CG_EN__MASK 0x00000001L
-#define SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER__MASK 0x0000FF00L
-#define SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER__MASK 0x00FF0000L
-//SYSHUB_TRANS_IDLE
-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0__MASK 0x00000001L
-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1__MASK 0x00000002L
-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2__MASK 0x00000004L
-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3__MASK 0x00000008L
-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4__MASK 0x00000010L
-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5__MASK 0x00000020L
-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6__MASK 0x00000040L
-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7__MASK 0x00000080L
-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8__MASK 0x00000100L
-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9__MASK 0x00000200L
-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10__MASK 0x00000400L
-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11__MASK 0x00000800L
-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12__MASK 0x00001000L
-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13__MASK 0x00002000L
-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14__MASK 0x00004000L
-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15__MASK 0x00008000L
-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF__MASK 0x00010000L
-//SYSHUB_HP_TIMER
-#define SYSHUB_HP_TIMER__SYSHUB_HP_TIMER__MASK 0xFFFFFFFFL
-//SYSHUB_SCRATCH
-#define SYSHUB_SCRATCH__SCRATCH__MASK 0xFFFFFFFFL
-//SYSHUB_DS_CTRL_SHUBCLK
-#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000001L
-#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000002L
-#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000004L
-#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000008L
-#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000010L
-#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000020L
-#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000040L
-#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000080L
-#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00010000L
-#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00020000L
-#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00040000L
-#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00080000L
-#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00100000L
-#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00200000L
-#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00400000L
-#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00800000L
-#define SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x10000000L
-#define SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN__MASK 0x80000000L
-//SYSHUB_DS_CTRL2_SHUBCLK
-#define SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER__MASK 0x0000FFFFL
-//SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK
-#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en__MASK 0x00008000L
-#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en__MASK 0x00010000L
-//SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK
-#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en__MASK 0x00008000L
-#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en__MASK 0x00010000L
-//DMA_CLK1_SW0_SYSHUB_QOS_CNTL
-#define DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L
-#define DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL
-#define DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L
-//DMA_CLK1_SW1_SYSHUB_QOS_CNTL
-#define DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L
-#define DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL
-#define DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L
-//DMA_CLK1_SW0_CL0_CNTL
-#define DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
-#define DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
-#define DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
-#define DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
-#define DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
-#define DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
-//DMA_CLK1_SW0_CL1_CNTL
-#define DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
-#define DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
-#define DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
-#define DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
-#define DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
-#define DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
-//DMA_CLK1_SW0_CL2_CNTL
-#define DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
-#define DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
-#define DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
-#define DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
-#define DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
-#define DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
-//DMA_CLK1_SW0_CL3_CNTL
-#define DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
-#define DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
-#define DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
-#define DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
-#define DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
-#define DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
-//DMA_CLK1_SW0_CL4_CNTL
-#define DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
-#define DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
-#define DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
-#define DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
-#define DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
-#define DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
-//DMA_CLK1_SW1_CL0_CNTL
-#define DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
-#define DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
-#define DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
-#define DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
-#define DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
-#define DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
-//DMA_CLK1_SW1_CL1_CNTL
-#define DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
-#define DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
-#define DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
-#define DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
-#define DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
-#define DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
-//DMA_CLK1_SW1_CL2_CNTL
-#define DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
-#define DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
-#define DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
-#define DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
-#define DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
-#define DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
-//DMA_CLK1_SW1_CL3_CNTL
-#define DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
-#define DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
-#define DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
-#define DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
-#define DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
-#define DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
-//DMA_CLK1_SW1_CL4_CNTL
-#define DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
-#define DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
-#define DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
-#define DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
-#define DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
-#define DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
-
-
-// addressBlock: gdc_ras_gdc_ras_regblk
-//GDC_RAS_LEAF0_CTRL
-#define GDC_RAS_LEAF0_CTRL__POISON_DET_EN__MASK 0x00000001L
-#define GDC_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L
-#define GDC_RAS_LEAF0_CTRL__POISON_STALL_EN__MASK 0x00000004L
-#define GDC_RAS_LEAF0_CTRL__PARITY_DET_EN__MASK 0x00000010L
-#define GDC_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L
-#define GDC_RAS_LEAF0_CTRL__PARITY_STALL_EN__MASK 0x00000040L
-#define GDC_RAS_LEAF0_CTRL__ERR_EVENT_RECV__MASK 0x00010000L
-#define GDC_RAS_LEAF0_CTRL__LINK_DIS_RECV__MASK 0x00020000L
-#define GDC_RAS_LEAF0_CTRL__POISON_ERR_DET__MASK 0x00040000L
-#define GDC_RAS_LEAF0_CTRL__PARITY_ERR_DET__MASK 0x00080000L
-#define GDC_RAS_LEAF0_CTRL__ERR_EVENT_SENT__MASK 0x00100000L
-#define GDC_RAS_LEAF0_CTRL__EGRESS_STALLED__MASK 0x00200000L
-//GDC_RAS_LEAF1_CTRL
-#define GDC_RAS_LEAF1_CTRL__POISON_DET_EN__MASK 0x00000001L
-#define GDC_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L
-#define GDC_RAS_LEAF1_CTRL__POISON_STALL_EN__MASK 0x00000004L
-#define GDC_RAS_LEAF1_CTRL__PARITY_DET_EN__MASK 0x00000010L
-#define GDC_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L
-#define GDC_RAS_LEAF1_CTRL__PARITY_STALL_EN__MASK 0x00000040L
-#define GDC_RAS_LEAF1_CTRL__ERR_EVENT_RECV__MASK 0x00010000L
-#define GDC_RAS_LEAF1_CTRL__LINK_DIS_RECV__MASK 0x00020000L
-#define GDC_RAS_LEAF1_CTRL__POISON_ERR_DET__MASK 0x00040000L
-#define GDC_RAS_LEAF1_CTRL__PARITY_ERR_DET__MASK 0x00080000L
-#define GDC_RAS_LEAF1_CTRL__ERR_EVENT_SENT__MASK 0x00100000L
-#define GDC_RAS_LEAF1_CTRL__EGRESS_STALLED__MASK 0x00200000L
-//GDC_RAS_LEAF2_CTRL
-#define GDC_RAS_LEAF2_CTRL__POISON_DET_EN__MASK 0x00000001L
-#define GDC_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L
-#define GDC_RAS_LEAF2_CTRL__POISON_STALL_EN__MASK 0x00000004L
-#define GDC_RAS_LEAF2_CTRL__PARITY_DET_EN__MASK 0x00000010L
-#define GDC_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L
-#define GDC_RAS_LEAF2_CTRL__PARITY_STALL_EN__MASK 0x00000040L
-#define GDC_RAS_LEAF2_CTRL__ERR_EVENT_RECV__MASK 0x00010000L
-#define GDC_RAS_LEAF2_CTRL__LINK_DIS_RECV__MASK 0x00020000L
-#define GDC_RAS_LEAF2_CTRL__POISON_ERR_DET__MASK 0x00040000L
-#define GDC_RAS_LEAF2_CTRL__PARITY_ERR_DET__MASK 0x00080000L
-#define GDC_RAS_LEAF2_CTRL__ERR_EVENT_SENT__MASK 0x00100000L
-#define GDC_RAS_LEAF2_CTRL__EGRESS_STALLED__MASK 0x00200000L
-//GDC_RAS_LEAF3_CTRL
-#define GDC_RAS_LEAF3_CTRL__POISON_DET_EN__MASK 0x00000001L
-#define GDC_RAS_LEAF3_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L
-#define GDC_RAS_LEAF3_CTRL__POISON_STALL_EN__MASK 0x00000004L
-#define GDC_RAS_LEAF3_CTRL__PARITY_DET_EN__MASK 0x00000010L
-#define GDC_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L
-#define GDC_RAS_LEAF3_CTRL__PARITY_STALL_EN__MASK 0x00000040L
-#define GDC_RAS_LEAF3_CTRL__ERR_EVENT_RECV__MASK 0x00010000L
-#define GDC_RAS_LEAF3_CTRL__LINK_DIS_RECV__MASK 0x00020000L
-#define GDC_RAS_LEAF3_CTRL__POISON_ERR_DET__MASK 0x00040000L
-#define GDC_RAS_LEAF3_CTRL__PARITY_ERR_DET__MASK 0x00080000L
-#define GDC_RAS_LEAF3_CTRL__ERR_EVENT_SENT__MASK 0x00100000L
-#define GDC_RAS_LEAF3_CTRL__EGRESS_STALLED__MASK 0x00200000L
-//GDC_RAS_LEAF4_CTRL
-#define GDC_RAS_LEAF4_CTRL__POISON_DET_EN__MASK 0x00000001L
-#define GDC_RAS_LEAF4_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L
-#define GDC_RAS_LEAF4_CTRL__POISON_STALL_EN__MASK 0x00000004L
-#define GDC_RAS_LEAF4_CTRL__PARITY_DET_EN__MASK 0x00000010L
-#define GDC_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L
-#define GDC_RAS_LEAF4_CTRL__PARITY_STALL_EN__MASK 0x00000040L
-#define GDC_RAS_LEAF4_CTRL__ERR_EVENT_RECV__MASK 0x00010000L
-#define GDC_RAS_LEAF4_CTRL__LINK_DIS_RECV__MASK 0x00020000L
-#define GDC_RAS_LEAF4_CTRL__POISON_ERR_DET__MASK 0x00040000L
-#define GDC_RAS_LEAF4_CTRL__PARITY_ERR_DET__MASK 0x00080000L
-#define GDC_RAS_LEAF4_CTRL__ERR_EVENT_SENT__MASK 0x00100000L
-#define GDC_RAS_LEAF4_CTRL__EGRESS_STALLED__MASK 0x00200000L
-//GDC_RAS_LEAF5_CTRL
-#define GDC_RAS_LEAF5_CTRL__POISON_DET_EN__MASK 0x00000001L
-#define GDC_RAS_LEAF5_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L
-#define GDC_RAS_LEAF5_CTRL__POISON_STALL_EN__MASK 0x00000004L
-#define GDC_RAS_LEAF5_CTRL__PARITY_DET_EN__MASK 0x00000010L
-#define GDC_RAS_LEAF5_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L
-#define GDC_RAS_LEAF5_CTRL__PARITY_STALL_EN__MASK 0x00000040L
-#define GDC_RAS_LEAF5_CTRL__ERR_EVENT_RECV__MASK 0x00010000L
-#define GDC_RAS_LEAF5_CTRL__LINK_DIS_RECV__MASK 0x00020000L
-#define GDC_RAS_LEAF5_CTRL__POISON_ERR_DET__MASK 0x00040000L
-#define GDC_RAS_LEAF5_CTRL__PARITY_ERR_DET__MASK 0x00080000L
-#define GDC_RAS_LEAF5_CTRL__ERR_EVENT_SENT__MASK 0x00100000L
-#define GDC_RAS_LEAF5_CTRL__EGRESS_STALLED__MASK 0x00200000L
-
-
-// addressBlock: gdc_rst_GDCRST_DEC
-//SHUB_PF_FLR_RST
-#define SHUB_PF_FLR_RST__PF0_FLR_RST__MASK 0x00000001L
-#define SHUB_PF_FLR_RST__PF1_FLR_RST__MASK 0x00000002L
-#define SHUB_PF_FLR_RST__PF2_FLR_RST__MASK 0x00000004L
-#define SHUB_PF_FLR_RST__PF3_FLR_RST__MASK 0x00000008L
-#define SHUB_PF_FLR_RST__PF4_FLR_RST__MASK 0x00000010L
-#define SHUB_PF_FLR_RST__PF5_FLR_RST__MASK 0x00000020L
-#define SHUB_PF_FLR_RST__PF6_FLR_RST__MASK 0x00000040L
-#define SHUB_PF_FLR_RST__PF7_FLR_RST__MASK 0x00000080L
-//SHUB_GFX_DRV_MODE1_RST
-#define SHUB_GFX_DRV_MODE1_RST__GFX_DRV_MODE1_RST__MASK 0x00000001L
-//SHUB_LINK_RESET
-#define SHUB_LINK_RESET__LINK_RESET__MASK 0x00000001L
-//SHUB_PF0_VF_FLR_RST
-#define SHUB_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__MASK 0x00000001L
-#define SHUB_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__MASK 0x00000002L
-#define SHUB_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__MASK 0x00000004L
-#define SHUB_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__MASK 0x00000008L
-#define SHUB_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__MASK 0x00000010L
-#define SHUB_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__MASK 0x00000020L
-#define SHUB_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__MASK 0x00000040L
-#define SHUB_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__MASK 0x00000080L
-#define SHUB_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__MASK 0x00000100L
-#define SHUB_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__MASK 0x00000200L
-#define SHUB_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__MASK 0x00000400L
-#define SHUB_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__MASK 0x00000800L
-#define SHUB_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__MASK 0x00001000L
-#define SHUB_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__MASK 0x00002000L
-#define SHUB_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__MASK 0x00004000L
-#define SHUB_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__MASK 0x00008000L
-#define SHUB_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__MASK 0x80000000L
-//SHUB_HARD_RST_CTRL
-#define SHUB_HARD_RST_CTRL__COR_RESET_EN__MASK 0x00000001L
-#define SHUB_HARD_RST_CTRL__REG_RESET_EN__MASK 0x00000002L
-#define SHUB_HARD_RST_CTRL__STY_RESET_EN__MASK 0x00000004L
-#define SHUB_HARD_RST_CTRL__NIC400_RESET_EN__MASK 0x00000008L
-#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN__MASK 0x00000010L
-//SHUB_SOFT_RST_CTRL
-#define SHUB_SOFT_RST_CTRL__COR_RESET_EN__MASK 0x00000001L
-#define SHUB_SOFT_RST_CTRL__REG_RESET_EN__MASK 0x00000002L
-#define SHUB_SOFT_RST_CTRL__STY_RESET_EN__MASK 0x00000004L
-#define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN__MASK 0x00000008L
-#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN__MASK 0x00000010L
-//SHUB_SDP_PORT_RST
-#define SHUB_SDP_PORT_RST__SDP_PORT_RST__MASK 0x00000001L
-
-
-// addressBlock: bif_bx_pf_SYSDEC
-//SBIOS_SCRATCH_0
-#define SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__MASK 0xFFFFFFFFL
-//SBIOS_SCRATCH_1
-#define SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__MASK 0xFFFFFFFFL
-//SBIOS_SCRATCH_2
-#define SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__MASK 0xFFFFFFFFL
-//SBIOS_SCRATCH_3
-#define SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__MASK 0xFFFFFFFFL
-//BIOS_SCRATCH_0
-#define BIOS_SCRATCH_0__BIOS_SCRATCH_0__MASK 0xFFFFFFFFL
-//BIOS_SCRATCH_1
-#define BIOS_SCRATCH_1__BIOS_SCRATCH_1__MASK 0xFFFFFFFFL
-//BIOS_SCRATCH_2
-#define BIOS_SCRATCH_2__BIOS_SCRATCH_2__MASK 0xFFFFFFFFL
-//BIOS_SCRATCH_3
-#define BIOS_SCRATCH_3__BIOS_SCRATCH_3__MASK 0xFFFFFFFFL
-//BIOS_SCRATCH_4
-#define BIOS_SCRATCH_4__BIOS_SCRATCH_4__MASK 0xFFFFFFFFL
-//BIOS_SCRATCH_5
-#define BIOS_SCRATCH_5__BIOS_SCRATCH_5__MASK 0xFFFFFFFFL
-//BIOS_SCRATCH_6
-#define BIOS_SCRATCH_6__BIOS_SCRATCH_6__MASK 0xFFFFFFFFL
-//BIOS_SCRATCH_7
-#define BIOS_SCRATCH_7__BIOS_SCRATCH_7__MASK 0xFFFFFFFFL
-//BIOS_SCRATCH_8
-#define BIOS_SCRATCH_8__BIOS_SCRATCH_8__MASK 0xFFFFFFFFL
-//BIOS_SCRATCH_9
-#define BIOS_SCRATCH_9__BIOS_SCRATCH_9__MASK 0xFFFFFFFFL
-//BIOS_SCRATCH_10
-#define BIOS_SCRATCH_10__BIOS_SCRATCH_10__MASK 0xFFFFFFFFL
-//BIOS_SCRATCH_11
-#define BIOS_SCRATCH_11__BIOS_SCRATCH_11__MASK 0xFFFFFFFFL
-//BIOS_SCRATCH_12
-#define BIOS_SCRATCH_12__BIOS_SCRATCH_12__MASK 0xFFFFFFFFL
-//BIOS_SCRATCH_13
-#define BIOS_SCRATCH_13__BIOS_SCRATCH_13__MASK 0xFFFFFFFFL
-//BIOS_SCRATCH_14
-#define BIOS_SCRATCH_14__BIOS_SCRATCH_14__MASK 0xFFFFFFFFL
-//BIOS_SCRATCH_15
-#define BIOS_SCRATCH_15__BIOS_SCRATCH_15__MASK 0xFFFFFFFFL
-//BIF_RLC_INTR_CNTL
-#define BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__MASK 0x00000001L
-#define BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__MASK 0x00000002L
-#define BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__MASK 0x00000004L
-#define BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__MASK 0x00000008L
-//BIF_VCE_INTR_CNTL
-#define BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__MASK 0x00000001L
-#define BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__MASK 0x00000002L
-#define BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__MASK 0x00000004L
-#define BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__MASK 0x00000008L
-//BIF_UVD_INTR_CNTL
-#define BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__MASK 0x00000001L
-#define BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__MASK 0x00000002L
-#define BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__MASK 0x00000004L
-#define BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__MASK 0x00000008L
-//GFX_MMIOREG_CAM_ADDR0
-#define GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__MASK 0x000FFFFFL
-//GFX_MMIOREG_CAM_REMAP_ADDR0
-#define GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__MASK 0x000FFFFFL
-//GFX_MMIOREG_CAM_ADDR1
-#define GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__MASK 0x000FFFFFL
-//GFX_MMIOREG_CAM_REMAP_ADDR1
-#define GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__MASK 0x000FFFFFL
-//GFX_MMIOREG_CAM_ADDR2
-#define GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__MASK 0x000FFFFFL
-//GFX_MMIOREG_CAM_REMAP_ADDR2
-#define GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__MASK 0x000FFFFFL
-//GFX_MMIOREG_CAM_ADDR3
-#define GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__MASK 0x000FFFFFL
-//GFX_MMIOREG_CAM_REMAP_ADDR3
-#define GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__MASK 0x000FFFFFL
-//GFX_MMIOREG_CAM_ADDR4
-#define GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__MASK 0x000FFFFFL
-//GFX_MMIOREG_CAM_REMAP_ADDR4
-#define GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__MASK 0x000FFFFFL
-//GFX_MMIOREG_CAM_ADDR5
-#define GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__MASK 0x000FFFFFL
-//GFX_MMIOREG_CAM_REMAP_ADDR5
-#define GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__MASK 0x000FFFFFL
-//GFX_MMIOREG_CAM_ADDR6
-#define GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__MASK 0x000FFFFFL
-//GFX_MMIOREG_CAM_REMAP_ADDR6
-#define GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__MASK 0x000FFFFFL
-//GFX_MMIOREG_CAM_ADDR7
-#define GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__MASK 0x000FFFFFL
-//GFX_MMIOREG_CAM_REMAP_ADDR7
-#define GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__MASK 0x000FFFFFL
-//GFX_MMIOREG_CAM_CNTL
-#define GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__MASK 0x000000FFL
-//GFX_MMIOREG_CAM_ZERO_CPL
-#define GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__MASK 0xFFFFFFFFL
-//GFX_MMIOREG_CAM_ONE_CPL
-#define GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__MASK 0xFFFFFFFFL
-//GFX_MMIOREG_CAM_PROGRAMMABLE_CPL
-#define GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__MASK 0xFFFFFFFFL
-
-
-// addressBlock: bif_bx_pf_SYSPFVFDEC
-//MM_INDEX
-#define MM_INDEX__MM_OFFSET__MASK 0x7FFFFFFFL
-#define MM_INDEX__MM_APER__MASK 0x80000000L
-//MM_DATA
-#define MM_DATA__MM_DATA__MASK 0xFFFFFFFFL
-//MM_INDEX_HI
-#define MM_INDEX_HI__MM_OFFSET_HI__MASK 0xFFFFFFFFL
-//SYSHUB_INDEX_OVLP
-#define SYSHUB_INDEX_OVLP__SYSHUB_OFFSET__MASK 0x003FFFFFL
-//SYSHUB_DATA_OVLP
-#define SYSHUB_DATA_OVLP__SYSHUB_DATA__MASK 0xFFFFFFFFL
-//PCIE_INDEX
-#define PCIE_INDEX__PCIE_INDEX__MASK 0xFFFFFFFFL
-//PCIE_DATA
-#define PCIE_DATA__PCIE_DATA__MASK 0xFFFFFFFFL
-//PCIE_INDEX2
-#define PCIE_INDEX2__PCIE_INDEX2__MASK 0xFFFFFFFFL
-//PCIE_DATA2
-#define PCIE_DATA2__PCIE_DATA2__MASK 0xFFFFFFFFL
-
-
-// addressBlock: rcc_dwn_BIFDEC1
-//DN_PCIE_RESERVED
-#define DN_PCIE_RESERVED__PCIE_RESERVED__MASK 0xFFFFFFFFL
-//DN_PCIE_SCRATCH
-#define DN_PCIE_SCRATCH__PCIE_SCRATCH__MASK 0xFFFFFFFFL
-//DN_PCIE_CNTL
-#define DN_PCIE_CNTL__HWINIT_WR_LOCK__MASK 0x00000001L
-#define DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__MASK 0x00000080L
-#define DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__MASK 0x40000000L
-//DN_PCIE_CONFIG_CNTL
-#define DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__MASK 0x06000000L
-//DN_PCIE_RX_CNTL2
-#define DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__MASK 0x70000000L
-//DN_PCIE_BUS_CNTL
-#define DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__MASK 0x00000080L
-#define DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__MASK 0x00000100L
-//DN_PCIE_CFG_CNTL
-#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__MASK 0x00000001L
-#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__MASK 0x00000002L
-#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__MASK 0x00000004L
-//DN_PCIE_STRAP_F0
-#define DN_PCIE_STRAP_F0__STRAP_F0_EN__MASK 0x00000001L
-#define DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__MASK 0x00020000L
-#define DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__MASK 0x00E00000L
-//DN_PCIE_STRAP_MISC
-#define DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__MASK 0x01000000L
-#define DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__MASK 0x20000000L
-//DN_PCIE_STRAP_MISC2
-#define DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__MASK 0x00000004L
-
-
-// addressBlock: rcc_dwnp_BIFDEC1
-//PCIEP_RESERVED
-#define PCIEP_RESERVED__PCIEP_RESERVED__MASK 0xFFFFFFFFL
-//PCIEP_SCRATCH
-#define PCIEP_SCRATCH__PCIEP_SCRATCH__MASK 0xFFFFFFFFL
-//PCIE_ERR_CNTL
-#define PCIE_ERR_CNTL__ERR_REPORTING_DIS__MASK 0x00000001L
-#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__MASK 0x00000700L
-#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__MASK 0x00000800L
-#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__MASK 0x00020000L
-//PCIE_RX_CNTL
-#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__MASK 0x00000100L
-#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__MASK 0x00000200L
-#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__MASK 0x00100000L
-#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__MASK 0x00200000L
-#define PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__MASK 0x08000000L
-//PCIE_LC_SPEED_CNTL
-#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__MASK 0x00000001L
-#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__MASK 0x00000002L
-//PCIE_LC_CNTL2
-#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__MASK 0x08000000L
-//PCIEP_STRAP_MISC
-#define PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__MASK 0x00000400L
-//LTR_MSG_INFO_FROM_EP
-#define LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__MASK 0xFFFFFFFFL
-
-
-// addressBlock: rcc_ep_BIFDEC1
-//EP_PCIE_SCRATCH
-#define EP_PCIE_SCRATCH__PCIE_SCRATCH__MASK 0xFFFFFFFFL
-//EP_PCIE_CNTL
-#define EP_PCIE_CNTL__UR_ERR_REPORT_DIS__MASK 0x00000080L
-#define EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__MASK 0x00000100L
-#define EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__MASK 0x40000000L
-//EP_PCIE_INT_CNTL
-#define EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__MASK 0x00000001L
-#define EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__MASK 0x00000002L
-#define EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__MASK 0x00000004L
-#define EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__MASK 0x00000008L
-#define EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__MASK 0x00000010L
-#define EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__MASK 0x00000040L
-//EP_PCIE_INT_STATUS
-#define EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__MASK 0x00000001L
-#define EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__MASK 0x00000002L
-#define EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__MASK 0x00000004L
-#define EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__MASK 0x00000008L
-#define EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__MASK 0x00000010L
-#define EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__MASK 0x00000040L
-//EP_PCIE_RX_CNTL2
-#define EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__MASK 0x00000001L
-//EP_PCIE_BUS_CNTL
-#define EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__MASK 0x00000080L
-//EP_PCIE_CFG_CNTL
-#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__MASK 0x00000001L
-#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__MASK 0x00000002L
-#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__MASK 0x00000004L
-//EP_PCIE_OBFF_CNTL
-#define EP_PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE__MASK 0x00000001L
-#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN__MASK 0x00000002L
-#define EP_PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE__MASK 0x00000004L
-#define EP_PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE__MASK 0x00000008L
-#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH__MASK 0x000000F0L
-#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH__MASK 0x00000F00L
-#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD__MASK 0x0000F000L
-#define EP_PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE__MASK 0x00010000L
-#define EP_PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE__MASK 0x00020000L
-#define EP_PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE__MASK 0x00040000L
-#define EP_PCIE_OBFF_CNTL__TX_OBFF_ACCEPT_IN_NOND0__MASK 0x00080000L
-#define EP_PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE__MASK 0x00F00000L
-//EP_PCIE_TX_LTR_CNTL
-#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__MASK 0x00000007L
-#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__MASK 0x00000038L
-#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__MASK 0x00000040L
-#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__MASK 0x00000380L
-#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__MASK 0x00001C00L
-#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__MASK 0x00002000L
-#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__MASK 0x00004000L
-#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__MASK 0x00008000L
-#define EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__MASK 0x00010000L
-//EP_PCIE_STRAP_MISC
-#define EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__MASK 0x20000000L
-//EP_PCIE_STRAP_MISC2
-#define EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__MASK 0x00000010L
-//EP_PCIE_STRAP_PI
-//EP_PCIE_F0_DPA_CAP
-#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__MASK 0x00000300L
-#define EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__MASK 0x00003000L
-#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__MASK 0x00FF0000L
-#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__MASK 0xFF000000L
-//EP_PCIE_F0_DPA_LATENCY_INDICATOR
-#define EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__MASK 0xFFL
-//EP_PCIE_F0_DPA_CNTL
-#define EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__MASK 0x001FL
-#define EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__MASK 0x0100L
-//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
-#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__MASK 0xFFL
-//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
-#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__MASK 0xFFL
-//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
-#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__MASK 0xFFL
-//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
-#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__MASK 0xFFL
-//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
-#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__MASK 0xFFL
-//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
-#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__MASK 0xFFL
-//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
-#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__MASK 0xFFL
-//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
-#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__MASK 0xFFL
-//EP_PCIE_PME_CONTROL
-#define EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__MASK 0x1FL
-//EP_PCIEP_RESERVED
-#define EP_PCIEP_RESERVED__PCIEP_RESERVED__MASK 0xFFFFFFFFL
-//EP_PCIE_TX_CNTL
-#define EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__MASK 0x00000C00L
-#define EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__MASK 0x00003000L
-#define EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__MASK 0x01000000L
-#define EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__MASK 0x02000000L
-#define EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__MASK 0x04000000L
-//EP_PCIE_TX_REQUESTER_ID
-#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__MASK 0x00000007L
-#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__MASK 0x000000F8L
-#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__MASK 0x0000FF00L
-//EP_PCIE_ERR_CNTL
-#define EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__MASK 0x00000001L
-#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__MASK 0x00000700L
-#define EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__MASK 0x00020000L
-#define EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__MASK 0x00040000L
-#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__MASK 0x01000000L
-#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__MASK 0x02000000L
-#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__MASK 0x04000000L
-#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__MASK 0x08000000L
-#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__MASK 0x10000000L
-#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__MASK 0x20000000L
-#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__MASK 0x40000000L
-#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__MASK 0x80000000L
-//EP_PCIE_RX_CNTL
-#define EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__MASK 0x00000100L
-#define EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__MASK 0x00000200L
-#define EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__MASK 0x00100000L
-#define EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__MASK 0x00200000L
-#define EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__MASK 0x00400000L
-#define EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__MASK 0x01000000L
-#define EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__MASK 0x02000000L
-#define EP_PCIE_RX_CNTL__RX_TPH_DIS__MASK 0x04000000L
-//EP_PCIE_LC_SPEED_CNTL
-#define EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__MASK 0x00000001L
-#define EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__MASK 0x00000002L
-
-
-// addressBlock: bif_bx_pf_BIFDEC1
-//BIF_MM_INDACCESS_CNTL
-#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__MASK 0x00000002L
-//BUS_CNTL
-#define BUS_CNTL__PMI_INT_DIS_EP__MASK 0x00000008L
-#define BUS_CNTL__PMI_INT_DIS_DN__MASK 0x00000010L
-#define BUS_CNTL__PMI_INT_DIS_SWUS__MASK 0x00000020L
-#define BUS_CNTL__VGA_REG_COHERENCY_DIS__MASK 0x00000040L
-#define BUS_CNTL__VGA_MEM_COHERENCY_DIS__MASK 0x00000080L
-#define BUS_CNTL__SET_AZ_TC__MASK 0x00001C00L
-#define BUS_CNTL__SET_MC_TC__MASK 0x0000E000L
-#define BUS_CNTL__ZERO_BE_WR_EN__MASK 0x00010000L
-#define BUS_CNTL__ZERO_BE_RD_EN__MASK 0x00020000L
-#define BUS_CNTL__RD_STALL_IO_WR__MASK 0x00040000L
-#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__MASK 0x00080000L
-#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__MASK 0x00100000L
-#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__MASK 0x00200000L
-#define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__MASK 0x00400000L
-#define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__MASK 0x00800000L
-#define BUS_CNTL__UR_OVRD_FOR_ECRC_EN__MASK 0x01000000L
-//BIF_SCRATCH0
-#define BIF_SCRATCH0__BIF_SCRATCH0__MASK 0xFFFFFFFFL
-//BIF_SCRATCH1
-#define BIF_SCRATCH1__BIF_SCRATCH1__MASK 0xFFFFFFFFL
-//BX_RESET_EN
-#define BX_RESET_EN__COR_RESET_EN__MASK 0x00000001L
-#define BX_RESET_EN__REG_RESET_EN__MASK 0x00000002L
-#define BX_RESET_EN__STY_RESET_EN__MASK 0x00000004L
-#define BX_RESET_EN__FLR_TWICE_EN__MASK 0x00000100L
-#define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__MASK 0x00010000L
-//MM_CFGREGS_CNTL
-#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__MASK 0x00000007L
-#define MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__MASK 0x000000C0L
-#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__MASK 0x80000000L
-//BX_RESET_CNTL
-#define BX_RESET_CNTL__LINK_TRAIN_EN__MASK 0x00000001L
-//INTERRUPT_CNTL
-#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__MASK 0x00000001L
-#define INTERRUPT_CNTL__IH_DUMMY_RD_EN__MASK 0x00000002L
-#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__MASK 0x00000008L
-#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__MASK 0x000000F0L
-#define INTERRUPT_CNTL__GEN_IH_INT_EN__MASK 0x00000100L
-#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__MASK 0x00008000L
-//INTERRUPT_CNTL2
-#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__MASK 0xFFFFFFFFL
-//CLKREQB_PAD_CNTL
-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__MASK 0x00000001L
-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__MASK 0x00000002L
-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__MASK 0x00000004L
-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__MASK 0x00000018L
-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__MASK 0x00000020L
-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__MASK 0x00000040L
-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__MASK 0x00000080L
-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__MASK 0x00000100L
-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__MASK 0x00000200L
-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__MASK 0x00000400L
-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__MASK 0x00000800L
-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__MASK 0x00001000L
-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__MASK 0x00002000L
-#define CLKREQB_PAD_CNTL__CLKREQB_PERF_COUNTER_UPPER__MASK 0xFF000000L
-//CLKREQB_PERF_COUNTER
-#define CLKREQB_PERF_COUNTER__CLKREQB_PERF_COUNTER_LOWER__MASK 0xFFFFFFFFL
-//BIF_CLK_CTRL
-#define BIF_CLK_CTRL__BIF_XSTCLK_READY__MASK 0x00000001L
-#define BIF_CLK_CTRL__BACO_XSTCLK_SWITCH_BYPASS__MASK 0x00000002L
-//BIF_FEATURES_CONTROL_MISC
-#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__MASK 0x00000001L
-#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__MASK 0x00000002L
-#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__MASK 0x00000004L
-#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__MASK 0x00000008L
-#define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS__MASK 0x00000200L
-#define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS__MASK 0x00000400L
-#define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__MASK 0x00000800L
-#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__MASK 0x00001000L
-#define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__MASK 0x00002000L
-#define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__MASK 0x00008000L
-#define BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS__MASK 0x00020000L
-#define BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS__MASK 0x00040000L
-#define BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__MASK 0x01000000L
-//BIF_DOORBELL_CNTL
-#define BIF_DOORBELL_CNTL__SELF_RING_DIS__MASK 0x00000001L
-#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__MASK 0x00000002L
-#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__MASK 0x00000004L
-#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__MASK 0x00000008L
-#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__MASK 0x00000010L
-#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__MASK 0x01000000L
-#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__MASK 0x02000000L
-#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__MASK 0x04000000L
-#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__MASK 0x08000000L
-//BIF_DOORBELL_INT_CNTL
-#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__MASK 0x00000001L
-#define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS__MASK 0x00000002L
-#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__MASK 0x00010000L
-#define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR__MASK 0x00020000L
-//BIF_SLVARB_MODE
-#define BIF_SLVARB_MODE__SLVARB_MODE__MASK 0x00000003L
-//BIF_FB_EN
-#define BIF_FB_EN__FB_READ_EN__MASK 0x00000001L
-#define BIF_FB_EN__FB_WRITE_EN__MASK 0x00000002L
-//BIF_BUSY_DELAY_CNTR
-#define BIF_BUSY_DELAY_CNTR__DELAY_CNT__MASK 0x0000003FL
-//BIF_PERFMON_CNTL
-#define BIF_PERFMON_CNTL__PERFCOUNTER_EN__MASK 0x00000001L
-#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0__MASK 0x00000002L
-#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__MASK 0x00000004L
-#define BIF_PERFMON_CNTL__PERF_SEL0__MASK 0x00001F00L
-#define BIF_PERFMON_CNTL__PERF_SEL1__MASK 0x0003E000L
-//BIF_PERFCOUNTER0_RESULT
-#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT__MASK 0xFFFFFFFFL
-//BIF_PERFCOUNTER1_RESULT
-#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT__MASK 0xFFFFFFFFL
-//BIF_MST_TRANS_PENDING_VF
-#define BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__MASK 0x0000FFFFL
-//BIF_SLV_TRANS_PENDING_VF
-#define BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__MASK 0x0000FFFFL
-//BACO_CNTL
-#define BACO_CNTL__BACO_EN__MASK 0x00000001L
-#define BACO_CNTL__BACO_BIF_LCLK_SWITCH__MASK 0x00000002L
-#define BACO_CNTL__BACO_DUMMY_EN__MASK 0x00000004L
-#define BACO_CNTL__BACO_POWER_OFF__MASK 0x00000008L
-#define BACO_CNTL__BACO_DSTATE_BYPASS__MASK 0x00000020L
-#define BACO_CNTL__BACO_RST_INTR_MASK__MASK 0x00000040L
-#define BACO_CNTL__BACO_MODE__MASK 0x00000100L
-#define BACO_CNTL__RCU_BIF_CONFIG_DONE__MASK 0x00000200L
-#define BACO_CNTL__BACO_AUTO_EXIT__MASK 0x80000000L
-//BIF_BACO_EXIT_TIME0
-#define BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__MASK 0x000FFFFFL
-//BIF_BACO_EXIT_TIMER1
-#define BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__MASK 0x000FFFFFL
-#define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__MASK 0x04000000L
-#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__MASK 0x08000000L
-#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__MASK 0x10000000L
-#define BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__MASK 0x60000000L
-#define BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__MASK 0x80000000L
-//BIF_BACO_EXIT_TIMER2
-#define BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__MASK 0x000FFFFFL
-//BIF_BACO_EXIT_TIMER3
-#define BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__MASK 0x000FFFFFL
-//BIF_BACO_EXIT_TIMER4
-#define BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__MASK 0x000FFFFFL
-//MEM_TYPE_CNTL
-#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__MASK 0x00000001L
-//SMU_BIF_VDDGFX_PWR_STATUS
-#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__MASK 0x00000001L
-//BIF_VDDGFX_GFX0_LOWER
-#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__MASK 0x0003FFFCL
-#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__MASK 0x40000000L
-#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__MASK 0x80000000L
-//BIF_VDDGFX_GFX0_UPPER
-#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__MASK 0x0003FFFCL
-//BIF_VDDGFX_GFX1_LOWER
-#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__MASK 0x0003FFFCL
-#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__MASK 0x40000000L
-#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__MASK 0x80000000L
-//BIF_VDDGFX_GFX1_UPPER
-#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__MASK 0x0003FFFCL
-//BIF_VDDGFX_GFX2_LOWER
-#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__MASK 0x0003FFFCL
-#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__MASK 0x40000000L
-#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__MASK 0x80000000L
-//BIF_VDDGFX_GFX2_UPPER
-#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__MASK 0x0003FFFCL
-//BIF_VDDGFX_GFX3_LOWER
-#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__MASK 0x0003FFFCL
-#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__MASK 0x40000000L
-#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__MASK 0x80000000L
-//BIF_VDDGFX_GFX3_UPPER
-#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__MASK 0x0003FFFCL
-//BIF_VDDGFX_GFX4_LOWER
-#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__MASK 0x0003FFFCL
-#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__MASK 0x40000000L
-#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__MASK 0x80000000L
-//BIF_VDDGFX_GFX4_UPPER
-#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__MASK 0x0003FFFCL
-//BIF_VDDGFX_GFX5_LOWER
-#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__MASK 0x0003FFFCL
-#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__MASK 0x40000000L
-#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__MASK 0x80000000L
-//BIF_VDDGFX_GFX5_UPPER
-#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__MASK 0x0003FFFCL
-//BIF_VDDGFX_RSV1_LOWER
-#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__MASK 0x0003FFFCL
-#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__MASK 0x40000000L
-#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__MASK 0x80000000L
-//BIF_VDDGFX_RSV1_UPPER
-#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__MASK 0x0003FFFCL
-//BIF_VDDGFX_RSV2_LOWER
-#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__MASK 0x0003FFFCL
-#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__MASK 0x40000000L
-#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__MASK 0x80000000L
-//BIF_VDDGFX_RSV2_UPPER
-#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__MASK 0x0003FFFCL
-//BIF_VDDGFX_RSV3_LOWER
-#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__MASK 0x0003FFFCL
-#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__MASK 0x40000000L
-#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__MASK 0x80000000L
-//BIF_VDDGFX_RSV3_UPPER
-#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__MASK 0x0003FFFCL
-//BIF_VDDGFX_RSV4_LOWER
-#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__MASK 0x0003FFFCL
-#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__MASK 0x40000000L
-#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__MASK 0x80000000L
-//BIF_VDDGFX_RSV4_UPPER
-#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__MASK 0x0003FFFCL
-//BIF_VDDGFX_FB_CMP
-#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__MASK 0x00000001L
-#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__MASK 0x00000002L
-#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__MASK 0x00000004L
-#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__MASK 0x00000008L
-#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__MASK 0x00000010L
-#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__MASK 0x00000020L
-//BIF_DOORBELL_GBLAPER1_LOWER
-#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__MASK 0x00000FFCL
-#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__MASK 0x80000000L
-//BIF_DOORBELL_GBLAPER1_UPPER
-#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__MASK 0x00000FFCL
-//BIF_DOORBELL_GBLAPER2_LOWER
-#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__MASK 0x00000FFCL
-#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__MASK 0x80000000L
-//BIF_DOORBELL_GBLAPER2_UPPER
-#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__MASK 0x00000FFCL
-//REMAP_HDP_MEM_FLUSH_CNTL
-#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__MASK 0x0007FFFCL
-//REMAP_HDP_REG_FLUSH_CNTL
-#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__MASK 0x0007FFFCL
-//BIF_RB_CNTL
-#define BIF_RB_CNTL__RB_ENABLE__MASK 0x00000001L
-#define BIF_RB_CNTL__RB_SIZE__MASK 0x0000003EL
-#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__MASK 0x00000100L
-#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__MASK 0x00003E00L
-#define BIF_RB_CNTL__BIF_RB_TRAN__MASK 0x00020000L
-#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__MASK 0x80000000L
-//BIF_RB_BASE
-#define BIF_RB_BASE__ADDR__MASK 0xFFFFFFFFL
-//BIF_RB_RPTR
-#define BIF_RB_RPTR__OFFSET__MASK 0x0003FFFCL
-//BIF_RB_WPTR
-#define BIF_RB_WPTR__BIF_RB_OVERFLOW__MASK 0x00000001L
-#define BIF_RB_WPTR__OFFSET__MASK 0x0003FFFCL
-//BIF_RB_WPTR_ADDR_HI
-#define BIF_RB_WPTR_ADDR_HI__ADDR__MASK 0x000000FFL
-//BIF_RB_WPTR_ADDR_LO
-#define BIF_RB_WPTR_ADDR_LO__ADDR__MASK 0xFFFFFFFCL
-//MAILBOX_INDEX
-#define MAILBOX_INDEX__MAILBOX_INDEX__MASK 0x0000001FL
-//BIF_GPUIOV_RESET_NOTIFICATION
-#define BIF_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION__MASK 0xFFFFFFFFL
-//BIF_UVD_GPUIOV_CFG_SIZE
-#define BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE__MASK 0x0000000FL
-//BIF_VCE_GPUIOV_CFG_SIZE
-#define BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE__MASK 0x0000000FL
-//BIF_GFX_SDMA_GPUIOV_CFG_SIZE
-#define BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__MASK 0x0000000FL
-//BIF_GMI_WRR_WEIGHT
-#define BIF_GMI_WRR_WEIGHT__GMI_REQ_REALTIME_WEIGHT__MASK 0x000000FFL
-#define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_P_WEIGHT__MASK 0x0000FF00L
-#define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_NP_WEIGHT__MASK 0x00FF0000L
-//NBIF_STRAP_WRITE_CTRL
-#define NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE__MASK 0x00000001L
-//BIF_PERSTB_PAD_CNTL
-#define BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__MASK 0x0000FFFFL
-//BIF_PX_EN_PAD_CNTL
-#define BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__MASK 0x000000FFL
-//BIF_REFPADKIN_PAD_CNTL
-#define BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__MASK 0x000000FFL
-//BIF_CLKREQB_PAD_CNTL
-#define BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__MASK 0x00FFFFFFL
-
-
-// addressBlock: rcc_pf_0_BIFDEC1
-//RCC_BACO_CNTL_MISC
-#define RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__MASK 0x00000001L
-#define RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__MASK 0x00000002L
-//RCC_RESET_EN
-#define RCC_RESET_EN__DB_APER_RESET_EN__MASK 0x00008000L
-//RCC_VDM_SUPPORT
-#define RCC_VDM_SUPPORT__MCTP_SUPPORT__MASK 0x00000001L
-#define RCC_VDM_SUPPORT__AMPTP_SUPPORT__MASK 0x00000002L
-#define RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__MASK 0x00000004L
-#define RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__MASK 0x00000008L
-#define RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__MASK 0x00000010L
-//RCC_PEER_REG_RANGE0
-#define RCC_PEER_REG_RANGE0__START_ADDR__MASK 0x0000FFFFL
-#define RCC_PEER_REG_RANGE0__END_ADDR__MASK 0xFFFF0000L
-//RCC_PEER_REG_RANGE1
-#define RCC_PEER_REG_RANGE1__START_ADDR__MASK 0x0000FFFFL
-#define RCC_PEER_REG_RANGE1__END_ADDR__MASK 0xFFFF0000L
-//RCC_BUS_CNTL
-#define RCC_BUS_CNTL__PMI_IO_DIS__MASK 0x00000004L
-#define RCC_BUS_CNTL__PMI_MEM_DIS__MASK 0x00000008L
-#define RCC_BUS_CNTL__PMI_BM_DIS__MASK 0x00000010L
-#define RCC_BUS_CNTL__PMI_IO_DIS_DN__MASK 0x00000020L
-#define RCC_BUS_CNTL__PMI_MEM_DIS_DN__MASK 0x00000040L
-#define RCC_BUS_CNTL__PMI_IO_DIS_UP__MASK 0x00000080L
-#define RCC_BUS_CNTL__PMI_MEM_DIS_UP__MASK 0x00000100L
-#define RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__MASK 0x00001000L
-#define RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__MASK 0x00002000L
-#define RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__MASK 0x00010000L
-#define RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__MASK 0x00020000L
-#define RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__MASK 0x00040000L
-#define RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__MASK 0x00080000L
-#define RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__MASK 0x00100000L
-#define RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__MASK 0x00200000L
-#define RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__MASK 0x01000000L
-#define RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__MASK 0x0E000000L
-#define RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__MASK 0x10000000L
-#define RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__MASK 0xE0000000L
-//RCC_CONFIG_CNTL
-#define RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__MASK 0x00000001L
-#define RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__MASK 0x00000004L
-#define RCC_CONFIG_CNTL__GRPH_ADRSEL__MASK 0x00000018L
-//RCC_CONFIG_F0_BASE
-#define RCC_CONFIG_F0_BASE__F0_BASE__MASK 0xFFFFFFFFL
-//RCC_CONFIG_APER_SIZE
-#define RCC_CONFIG_APER_SIZE__APER_SIZE__MASK 0xFFFFFFFFL
-//RCC_CONFIG_REG_APER_SIZE
-#define RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__MASK 0x000FFFFFL
-//RCC_XDMA_LO
-#define RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__MASK 0x1FFFFFFFL
-#define RCC_XDMA_LO__BIF_XDMA_APER_EN__MASK 0x80000000L
-//RCC_XDMA_HI
-#define RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__MASK 0x1FFFFFFFL
-//RCC_FEATURES_CONTROL_MISC
-#define RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__MASK 0x00000010L
-#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__MASK 0x00000020L
-#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__MASK 0x00000040L
-#define RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__MASK 0x00000100L
-#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__MASK 0x00000200L
-#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__MASK 0x00000400L
-#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__MASK 0x00000800L
-#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__MASK 0x00001000L
-#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__MASK 0x00002000L
-#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__MASK 0x00004000L
-#define RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__MASK 0x00008000L
-#define RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__MASK 0x00010000L
-#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__MASK 0x00020000L
-#define RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__MASK 0x00040000L
-//RCC_BUSNUM_CNTL1
-#define RCC_BUSNUM_CNTL1__ID_MASK__MASK 0x000000FFL
-//RCC_BUSNUM_LIST0
-#define RCC_BUSNUM_LIST0__ID0__MASK 0x000000FFL
-#define RCC_BUSNUM_LIST0__ID1__MASK 0x0000FF00L
-#define RCC_BUSNUM_LIST0__ID2__MASK 0x00FF0000L
-#define RCC_BUSNUM_LIST0__ID3__MASK 0xFF000000L
-//RCC_BUSNUM_LIST1
-#define RCC_BUSNUM_LIST1__ID4__MASK 0x000000FFL
-#define RCC_BUSNUM_LIST1__ID5__MASK 0x0000FF00L
-#define RCC_BUSNUM_LIST1__ID6__MASK 0x00FF0000L
-#define RCC_BUSNUM_LIST1__ID7__MASK 0xFF000000L
-//RCC_BUSNUM_CNTL2
-#define RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__MASK 0x000000FFL
-#define RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__MASK 0x00000100L
-#define RCC_BUSNUM_CNTL2__HDPREG_CNTL__MASK 0x00010000L
-#define RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__MASK 0x00020000L
-//RCC_CAPTURE_HOST_BUSNUM
-#define RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__MASK 0x00000001L
-//RCC_HOST_BUSNUM
-#define RCC_HOST_BUSNUM__HOST_ID__MASK 0x0000FFFFL
-//RCC_PEER0_FB_OFFSET_HI
-#define RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__MASK 0x000FFFFFL
-//RCC_PEER0_FB_OFFSET_LO
-#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__MASK 0x000FFFFFL
-#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__MASK 0x80000000L
-//RCC_PEER1_FB_OFFSET_HI
-#define RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__MASK 0x000FFFFFL
-//RCC_PEER1_FB_OFFSET_LO
-#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__MASK 0x000FFFFFL
-#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__MASK 0x80000000L
-//RCC_PEER2_FB_OFFSET_HI
-#define RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__MASK 0x000FFFFFL
-//RCC_PEER2_FB_OFFSET_LO
-#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__MASK 0x000FFFFFL
-#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__MASK 0x80000000L
-//RCC_PEER3_FB_OFFSET_HI
-#define RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__MASK 0x000FFFFFL
-//RCC_PEER3_FB_OFFSET_LO
-#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__MASK 0x000FFFFFL
-#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__MASK 0x80000000L
-//RCC_DEVFUNCNUM_LIST0
-#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__MASK 0x000000FFL
-#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__MASK 0x0000FF00L
-#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__MASK 0x00FF0000L
-#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__MASK 0xFF000000L
-//RCC_DEVFUNCNUM_LIST1
-#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__MASK 0x000000FFL
-#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__MASK 0x0000FF00L
-#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__MASK 0x00FF0000L
-#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__MASK 0xFF000000L
-//RCC_DEV0_LINK_CNTL
-#define RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__MASK 0x00000001L
-#define RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__MASK 0x00000100L
-//RCC_CMN_LINK_CNTL
-#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__MASK 0x00000001L
-#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__MASK 0x00000002L
-#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__MASK 0x00000004L
-#define RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__MASK 0x00000008L
-//RCC_EP_REQUESTERID_RESTORE
-#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__MASK 0x000000FFL
-#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__MASK 0x00001F00L
-//RCC_LTR_LSWITCH_CNTL
-#define RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__MASK 0x000003FFL
-//RCC_MH_ARB_CNTL
-#define RCC_MH_ARB_CNTL__MH_ARB_MODE__MASK 0x00000001L
-#define RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__MASK 0x00007FFEL
-
-
-// addressBlock: rcc_pf_0_BIFDEC2
-//GFXMSIX_VECT0_ADDR_LO
-#define GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
-//GFXMSIX_VECT0_ADDR_HI
-#define GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
-//GFXMSIX_VECT0_MSG_DATA
-#define GFXMSIX_VECT0_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
-//GFXMSIX_VECT0_CONTROL
-#define GFXMSIX_VECT0_CONTROL__MASK_BIT__MASK 0x00000001L
-//GFXMSIX_VECT1_ADDR_LO
-#define GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
-//GFXMSIX_VECT1_ADDR_HI
-#define GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
-//GFXMSIX_VECT1_MSG_DATA
-#define GFXMSIX_VECT1_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
-//GFXMSIX_VECT1_CONTROL
-#define GFXMSIX_VECT1_CONTROL__MASK_BIT__MASK 0x00000001L
-//GFXMSIX_VECT2_ADDR_LO
-#define GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
-//GFXMSIX_VECT2_ADDR_HI
-#define GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
-//GFXMSIX_VECT2_MSG_DATA
-#define GFXMSIX_VECT2_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
-//GFXMSIX_VECT2_CONTROL
-#define GFXMSIX_VECT2_CONTROL__MASK_BIT__MASK 0x00000001L
-//GFXMSIX_PBA
-#define GFXMSIX_PBA__MSIX_PENDING_BITS_0__MASK 0x00000001L
-#define GFXMSIX_PBA__MSIX_PENDING_BITS_1__MASK 0x00000002L
-#define GFXMSIX_PBA__MSIX_PENDING_BITS_2__MASK 0x00000004L
-
-
-// addressBlock: rcc_strap_BIFDEC1
-//RCC_DEV0_PORT_STRAP0
-#define RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__MASK 0x00000002L
-#define RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__MASK 0x00000004L
-#define RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__MASK 0x00000008L
-#define RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__MASK 0x00000010L
-#define RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__MASK 0x001FFFE0L
-#define RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__MASK 0x00E00000L
-#define RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__MASK 0x01000000L
-#define RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__MASK 0x0E000000L
-#define RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__MASK 0x70000000L
-#define RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__MASK 0x80000000L
-//RCC_DEV0_PORT_STRAP1
-#define RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__MASK 0x0000FFFFL
-#define RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__MASK 0xFFFF0000L
-//RCC_DEV0_PORT_STRAP2
-#define RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__MASK 0x00000001L
-#define RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__MASK 0x00000002L
-#define RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__MASK 0x00000004L
-#define RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__MASK 0x00000008L
-#define RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__MASK 0x00000010L
-#define RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__MASK 0x00000020L
-#define RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__MASK 0x00000040L
-#define RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__MASK 0x00000080L
-#define RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__MASK 0x00000100L
-#define RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__MASK 0x00000E00L
-#define RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__MASK 0x00001000L
-#define RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__MASK 0x00002000L
-#define RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__MASK 0x00004000L
-#define RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__MASK 0x00008000L
-#define RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__MASK 0x00010000L
-#define RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__MASK 0x00060000L
-#define RCC_DEV0_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV0__MASK 0x00080000L
-#define RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__MASK 0x00700000L
-#define RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__MASK 0x03800000L
-#define RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__MASK 0x1C000000L
-#define RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__MASK 0xE0000000L
-//RCC_DEV0_PORT_STRAP3
-#define RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__MASK 0x00000001L
-#define RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__MASK 0x00000002L
-#define RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__MASK 0x00000004L
-#define RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__MASK 0x00000038L
-#define RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__MASK 0x00000040L
-#define RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__MASK 0x00000080L
-#define RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__MASK 0x00000100L
-#define RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__MASK 0x00000600L
-#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__MASK 0x00003800L
-#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__MASK 0x0003C000L
-#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__MASK 0x001C0000L
-#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__MASK 0x01E00000L
-#define RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__MASK 0x06000000L
-#define RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__MASK 0x18000000L
-#define RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__MASK 0x20000000L
-#define RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__MASK 0x40000000L
-#define RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__MASK 0x80000000L
-//RCC_DEV0_PORT_STRAP4
-#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__MASK 0x000000FFL
-#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__MASK 0x0000FF00L
-#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__MASK 0x00FF0000L
-#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__MASK 0xFF000000L
-//RCC_DEV0_PORT_STRAP5
-#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__MASK 0x000000FFL
-#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__MASK 0x0000FF00L
-#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__MASK 0x00010000L
-#define RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__MASK 0x00020000L
-#define RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__MASK 0x00040000L
-#define RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__MASK 0x00080000L
-#define RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__MASK 0x00100000L
-#define RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__MASK 0x00200000L
-#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__MASK 0x00800000L
-#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__MASK 0x01000000L
-#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__MASK 0x02000000L
-#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__MASK 0x04000000L
-#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__MASK 0x08000000L
-#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__MASK 0x10000000L
-#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__MASK 0x20000000L
-#define RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__MASK 0x40000000L
-#define RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__MASK 0x80000000L
-//RCC_DEV0_PORT_STRAP6
-#define RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__MASK 0x00000001L
-#define RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__MASK 0x00000002L
-//RCC_DEV0_PORT_STRAP7
-#define RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__MASK 0x000000FFL
-#define RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__MASK 0x00000F00L
-#define RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__MASK 0x0000F000L
-#define RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__MASK 0x00FF0000L
-#define RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__MASK 0x1F000000L
-#define RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__MASK 0xE0000000L
-//RCC_DEV0_EPF0_STRAP0
-#define RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__MASK 0x0000FFFFL
-#define RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__MASK 0x000F0000L
-#define RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__MASK 0x00F00000L
-#define RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__MASK 0x0F000000L
-#define RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__MASK 0x10000000L
-#define RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__MASK 0x20000000L
-#define RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__MASK 0x40000000L
-#define RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__MASK 0x80000000L
-//RCC_DEV0_EPF0_STRAP1
-#define RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__MASK 0x0000FFFFL
-#define RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__MASK 0xFFFF0000L
-//RCC_DEV0_EPF0_STRAP13
-#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__MASK 0x000000FFL
-#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__MASK 0x0000FF00L
-#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__MASK 0x00FF0000L
-//RCC_DEV0_EPF0_STRAP2
-#define RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__MASK 0x00000001L
-#define RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__MASK 0x0000003EL
-#define RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__MASK 0x00000040L
-#define RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__MASK 0x00000080L
-#define RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__MASK 0x00000100L
-#define RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__MASK 0x00003E00L
-#define RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__MASK 0x00004000L
-#define RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__MASK 0x00008000L
-#define RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__MASK 0x00010000L
-#define RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__MASK 0x00020000L
-#define RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__MASK 0x00040000L
-#define RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__MASK 0x00100000L
-#define RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__MASK 0x00200000L
-#define RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__MASK 0x00400000L
-#define RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__MASK 0x00800000L
-#define RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__MASK 0x07000000L
-#define RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__MASK 0x08000000L
-#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__MASK 0x10000000L
-#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__MASK 0x20000000L
-#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__MASK 0x40000000L
-#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__MASK 0x80000000L
-//RCC_DEV0_EPF0_STRAP3
-#define RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__MASK 0x00000001L
-#define RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__MASK 0x00000002L
-#define RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__MASK 0x0003FFFCL
-#define RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__MASK 0x00040000L
-#define RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__MASK 0x00080000L
-#define RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__MASK 0x00100000L
-#define RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__MASK 0x00E00000L
-#define RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__MASK 0x01000000L
-#define RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__MASK 0x02000000L
-#define RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__MASK 0x04000000L
-#define RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__MASK 0x08000000L
-//RCC_DEV0_EPF0_STRAP4
-#define RCC_DEV0_EPF0_STRAP4__STRAP_MSIX_TABLE_OFFSET_DEV0_F0__MASK 0x000FFFFFL
-#define RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__MASK 0x00100000L
-#define RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__MASK 0x00200000L
-#define RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__MASK 0x00400000L
-#define RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__MASK 0x0F800000L
-#define RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__MASK 0x70000000L
-#define RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__MASK 0x80000000L
-//RCC_DEV0_EPF0_STRAP5
-#define RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__MASK 0x0000FFFFL
-//RCC_DEV0_EPF0_STRAP8
-#define RCC_DEV0_EPF0_STRAP8__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__MASK 0x00000001L
-#define RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__MASK 0x00000006L
-#define RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__MASK 0x00000008L
-#define RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__MASK 0x00000010L
-#define RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__MASK 0x00000060L
-#define RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__MASK 0x00000080L
-#define RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__MASK 0x00000100L
-#define RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__MASK 0x00000E00L
-#define RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__MASK 0x00003000L
-#define RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__MASK 0x0000C000L
-#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__MASK 0x00070000L
-#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__MASK 0x00380000L
-#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__MASK 0x00C00000L
-#define RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__MASK 0x01000000L
-#define RCC_DEV0_EPF0_STRAP8__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__MASK 0x02000000L
-#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_PROT_DIS_DEV0_F0__MASK 0x04000000L
-#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__MASK 0x38000000L
-#define RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__MASK 0xC0000000L
-//RCC_DEV0_EPF0_STRAP9
-//RCC_DEV0_EPF1_STRAP0
-#define RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__MASK 0x0000FFFFL
-#define RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__MASK 0x000F0000L
-#define RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__MASK 0x00F00000L
-#define RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__MASK 0x10000000L
-#define RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__MASK 0x20000000L
-#define RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__MASK 0x40000000L
-#define RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__MASK 0x80000000L
-//RCC_DEV0_EPF1_STRAP10
-#define RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__MASK 0x00000001L
-#define RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__MASK 0x001FFFFEL
-//RCC_DEV0_EPF1_STRAP11
-#define RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__MASK 0x00000001L
-#define RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__MASK 0x001FFFFEL
-//RCC_DEV0_EPF1_STRAP12
-#define RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__MASK 0x00000001L
-#define RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__MASK 0x001FFFFEL
-//RCC_DEV0_EPF1_STRAP13
-#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__MASK 0x000000FFL
-#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__MASK 0x0000FF00L
-#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__MASK 0x00FF0000L
-//RCC_DEV0_EPF1_STRAP2
-#define RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__MASK 0x00000080L
-#define RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__MASK 0x00000100L
-#define RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__MASK 0x00004000L
-#define RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__MASK 0x00010000L
-#define RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__MASK 0x00020000L
-#define RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__MASK 0x00040000L
-#define RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__MASK 0x00100000L
-#define RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__MASK 0x00200000L
-#define RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__MASK 0x00400000L
-#define RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__MASK 0x00800000L
-#define RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__MASK 0x07000000L
-//RCC_DEV0_EPF1_STRAP3
-#define RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__MASK 0x00000001L
-#define RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__MASK 0x00000002L
-#define RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__MASK 0x0003FFFCL
-#define RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__MASK 0x00040000L
-#define RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__MASK 0x00080000L
-#define RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__MASK 0x00100000L
-#define RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__MASK 0x01000000L
-#define RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__MASK 0x02000000L
-#define RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__MASK 0x04000000L
-#define RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__MASK 0x08000000L
-//RCC_DEV0_EPF1_STRAP4
-#define RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__MASK 0x00100000L
-#define RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__MASK 0x00200000L
-#define RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__MASK 0x00400000L
-#define RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__MASK 0x0F800000L
-#define RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__MASK 0x70000000L
-#define RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__MASK 0x80000000L
-//RCC_DEV0_EPF1_STRAP5
-#define RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__MASK 0x0000FFFFL
-//RCC_DEV0_EPF1_STRAP6
-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__MASK 0x00000001L
-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__MASK 0x00000002L
-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__MASK 0x00000004L
-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__MASK 0x00000070L
-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__MASK 0x00000100L
-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__MASK 0x00000200L
-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__MASK 0x00010000L
-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__MASK 0x00020000L
-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__MASK 0x01000000L
-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__MASK 0x02000000L
-//RCC_DEV0_EPF1_STRAP7
-#define RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__MASK 0x00000001L
-#define RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__MASK 0x0000001EL
-
-
-// addressBlock: bif_bx_pf_BIFPFVFDEC1
-//BIF_BME_STATUS
-#define BIF_BME_STATUS__DMA_ON_BME_LOW__MASK 0x00000001L
-#define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__MASK 0x00010000L
-//BIF_ATOMIC_ERR_LOG
-#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__MASK 0x00000001L
-#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__MASK 0x00000002L
-#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__MASK 0x00010000L
-#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__MASK 0x00020000L
-//DOORBELL_SELFRING_GPA_APER_BASE_HIGH
-#define DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__MASK 0xFFFFFFFFL
-//DOORBELL_SELFRING_GPA_APER_BASE_LOW
-#define DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__MASK 0xFFFFFFFFL
-//DOORBELL_SELFRING_GPA_APER_CNTL
-#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__MASK 0x00000001L
-#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__MASK 0x0000FF00L
-//HDP_REG_COHERENCY_FLUSH_CNTL
-#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__MASK 0x00000001L
-//HDP_MEM_COHERENCY_FLUSH_CNTL
-#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__MASK 0x00000001L
-//GPU_HDP_FLUSH_REQ
-#define GPU_HDP_FLUSH_REQ__CP0__MASK 0x00000001L
-#define GPU_HDP_FLUSH_REQ__CP1__MASK 0x00000002L
-#define GPU_HDP_FLUSH_REQ__CP2__MASK 0x00000004L
-#define GPU_HDP_FLUSH_REQ__CP3__MASK 0x00000008L
-#define GPU_HDP_FLUSH_REQ__CP4__MASK 0x00000010L
-#define GPU_HDP_FLUSH_REQ__CP5__MASK 0x00000020L
-#define GPU_HDP_FLUSH_REQ__CP6__MASK 0x00000040L
-#define GPU_HDP_FLUSH_REQ__CP7__MASK 0x00000080L
-#define GPU_HDP_FLUSH_REQ__CP8__MASK 0x00000100L
-#define GPU_HDP_FLUSH_REQ__CP9__MASK 0x00000200L
-#define GPU_HDP_FLUSH_REQ__SDMA0__MASK 0x00000400L
-#define GPU_HDP_FLUSH_REQ__SDMA1__MASK 0x00000800L
-//GPU_HDP_FLUSH_DONE
-#define GPU_HDP_FLUSH_DONE__CP0__MASK 0x00000001L
-#define GPU_HDP_FLUSH_DONE__CP1__MASK 0x00000002L
-#define GPU_HDP_FLUSH_DONE__CP2__MASK 0x00000004L
-#define GPU_HDP_FLUSH_DONE__CP3__MASK 0x00000008L
-#define GPU_HDP_FLUSH_DONE__CP4__MASK 0x00000010L
-#define GPU_HDP_FLUSH_DONE__CP5__MASK 0x00000020L
-#define GPU_HDP_FLUSH_DONE__CP6__MASK 0x00000040L
-#define GPU_HDP_FLUSH_DONE__CP7__MASK 0x00000080L
-#define GPU_HDP_FLUSH_DONE__CP8__MASK 0x00000100L
-#define GPU_HDP_FLUSH_DONE__CP9__MASK 0x00000200L
-#define GPU_HDP_FLUSH_DONE__SDMA0__MASK 0x00000400L
-#define GPU_HDP_FLUSH_DONE__SDMA1__MASK 0x00000800L
-//BIF_TRANS_PENDING
-#define BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__MASK 0x00000001L
-#define BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__MASK 0x00000002L
-//MAILBOX_MSGBUF_TRN_DW0
-#define MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__MASK 0xFFFFFFFFL
-//MAILBOX_MSGBUF_TRN_DW1
-#define MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__MASK 0xFFFFFFFFL
-//MAILBOX_MSGBUF_TRN_DW2
-#define MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__MASK 0xFFFFFFFFL
-//MAILBOX_MSGBUF_TRN_DW3
-#define MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__MASK 0xFFFFFFFFL
-//MAILBOX_MSGBUF_RCV_DW0
-#define MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__MASK 0xFFFFFFFFL
-//MAILBOX_MSGBUF_RCV_DW1
-#define MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__MASK 0xFFFFFFFFL
-//MAILBOX_MSGBUF_RCV_DW2
-#define MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__MASK 0xFFFFFFFFL
-//MAILBOX_MSGBUF_RCV_DW3
-#define MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__MASK 0xFFFFFFFFL
-//MAILBOX_CONTROL
-#define MAILBOX_CONTROL__TRN_MSG_VALID__MASK 0x00000001L
-#define MAILBOX_CONTROL__TRN_MSG_ACK__MASK 0x00000002L
-#define MAILBOX_CONTROL__RCV_MSG_VALID__MASK 0x00000100L
-#define MAILBOX_CONTROL__RCV_MSG_ACK__MASK 0x00000200L
-//MAILBOX_INT_CNTL
-#define MAILBOX_INT_CNTL__VALID_INT_EN__MASK 0x00000001L
-#define MAILBOX_INT_CNTL__ACK_INT_EN__MASK 0x00000002L
-//BIF_VMHV_MAILBOX
-#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__MASK 0x00000001L
-#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__MASK 0x00000002L
-#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__MASK 0x00000F00L
-#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__MASK 0x00008000L
-#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__MASK 0x000F0000L
-#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__MASK 0x00800000L
-#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__MASK 0x01000000L
-#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__MASK 0x02000000L
-
-
-// addressBlock: rcc_pf_0_BIFPFVFDEC1
-//RCC_DOORBELL_APER_EN
-#define RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__MASK 0x00000001L
-//RCC_CONFIG_MEMSIZE
-#define RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__MASK 0xFFFFFFFFL
-//RCC_CONFIG_RESERVED
-#define RCC_CONFIG_RESERVED__CONFIG_RESERVED__MASK 0xFFFFFFFFL
-//RCC_IOV_FUNC_IDENTIFIER
-#define RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__MASK 0x00000001L
-#define RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__MASK 0x80000000L
-
-
-// addressBlock: syshub_mmreg_ind_syshubdec
-//SYSHUB_INDEX
-#define SYSHUB_INDEX__INDEX__MASK 0xFFFFFFFFL
-//SYSHUB_DATA
-#define SYSHUB_DATA__DATA__MASK 0xFFFFFFFFL
-
-
-// addressBlock: rcc_strap_rcc_strap_internal
-//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__MASK 0x00000002L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__MASK 0x00000004L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__MASK 0x00000008L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__MASK 0x00000010L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__MASK 0x001FFFE0L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__MASK 0x00E00000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__MASK 0x01000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__MASK 0x0E000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__MASK 0x70000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__MASK 0x80000000L
-//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__MASK 0x0000FFFFL
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__MASK 0xFFFF0000L
-//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__MASK 0x00000001L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__MASK 0x00000002L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__MASK 0x00000004L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__MASK 0x00000008L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__MASK 0x00000010L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__MASK 0x00000020L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__MASK 0x00000040L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__MASK 0x00000080L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__MASK 0x00000100L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__MASK 0x00000E00L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__MASK 0x00001000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__MASK 0x00002000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__MASK 0x00004000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__MASK 0x00008000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__MASK 0x00010000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__MASK 0x00060000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV0__MASK 0x00080000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__MASK 0x00700000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__MASK 0x03800000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__MASK 0x1C000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__MASK 0xE0000000L
-//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__MASK 0x00000001L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__MASK 0x00000002L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__MASK 0x00000004L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__MASK 0x00000038L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__MASK 0x00000040L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__MASK 0x00000080L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__MASK 0x00000100L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__MASK 0x00000600L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__MASK 0x00003800L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__MASK 0x0003C000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__MASK 0x001C0000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__MASK 0x01E00000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__MASK 0x06000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__MASK 0x18000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__MASK 0x20000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__MASK 0x40000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__MASK 0x80000000L
-//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__MASK 0x000000FFL
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__MASK 0x0000FF00L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__MASK 0x00FF0000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__MASK 0xFF000000L
-//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__MASK 0x000000FFL
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__MASK 0x0000FF00L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__MASK 0x00010000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__MASK 0x00020000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__MASK 0x00040000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__MASK 0x00080000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__MASK 0x00100000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__MASK 0x00200000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__MASK 0x00800000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__MASK 0x01000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__MASK 0x02000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__MASK 0x04000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__MASK 0x08000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__MASK 0x10000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__MASK 0x20000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__MASK 0x40000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__MASK 0x80000000L
-//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__MASK 0x00000001L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__MASK 0x00000002L
-//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__MASK 0x000000FFL
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__MASK 0x00000F00L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__MASK 0x0000F000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__MASK 0x00FF0000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__MASK 0x1F000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__MASK 0xE0000000L
-//RCC_DEV1_PORT_STRAP0
-#define RCC_DEV1_PORT_STRAP0__STRAP_ARI_EN_DN_DEV1__MASK 0x00000002L
-#define RCC_DEV1_PORT_STRAP0__STRAP_ACS_EN_DN_DEV1__MASK 0x00000004L
-#define RCC_DEV1_PORT_STRAP0__STRAP_AER_EN_DN_DEV1__MASK 0x00000008L
-#define RCC_DEV1_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV1__MASK 0x00000010L
-#define RCC_DEV1_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV1__MASK 0x001FFFE0L
-#define RCC_DEV1_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV1__MASK 0x00E00000L
-#define RCC_DEV1_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV1__MASK 0x01000000L
-#define RCC_DEV1_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV1__MASK 0x0E000000L
-#define RCC_DEV1_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV1__MASK 0x70000000L
-#define RCC_DEV1_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV1__MASK 0x80000000L
-//RCC_DEV1_PORT_STRAP1
-#define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV1__MASK 0x0000FFFFL
-#define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV1__MASK 0xFFFF0000L
-//RCC_DEV1_PORT_STRAP2
-#define RCC_DEV1_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV1__MASK 0x00000001L
-#define RCC_DEV1_PORT_STRAP2__STRAP_DSN_EN_DN_DEV1__MASK 0x00000002L
-#define RCC_DEV1_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV1__MASK 0x00000004L
-#define RCC_DEV1_PORT_STRAP2__STRAP_ECN1P1_EN_DEV1__MASK 0x00000008L
-#define RCC_DEV1_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV1__MASK 0x00000010L
-#define RCC_DEV1_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV1__MASK 0x00000020L
-#define RCC_DEV1_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV1__MASK 0x00000040L
-#define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV1__MASK 0x00000080L
-#define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV1__MASK 0x00000100L
-#define RCC_DEV1_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV1__MASK 0x00000E00L
-#define RCC_DEV1_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV1__MASK 0x00001000L
-#define RCC_DEV1_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV1__MASK 0x00002000L
-#define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV1__MASK 0x00004000L
-#define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_EN_DEV1__MASK 0x00008000L
-#define RCC_DEV1_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV1__MASK 0x00010000L
-#define RCC_DEV1_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV1__MASK 0x00060000L
-#define RCC_DEV1_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV1__MASK 0x00080000L
-#define RCC_DEV1_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV1__MASK 0x00700000L
-#define RCC_DEV1_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV1__MASK 0x03800000L
-#define RCC_DEV1_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV1__MASK 0x1C000000L
-#define RCC_DEV1_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV1__MASK 0xE0000000L
-//RCC_DEV1_PORT_STRAP3
-#define RCC_DEV1_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV1__MASK 0x00000001L
-#define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DEV1__MASK 0x00000002L
-#define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DN_DEV1__MASK 0x00000004L
-#define RCC_DEV1_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV1__MASK 0x00000038L
-#define RCC_DEV1_PORT_STRAP3__STRAP_MSI_EN_DN_DEV1__MASK 0x00000040L
-#define RCC_DEV1_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV1__MASK 0x00000080L
-#define RCC_DEV1_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV1__MASK 0x00000100L
-#define RCC_DEV1_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV1__MASK 0x00000600L
-#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV1__MASK 0x00003800L
-#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV1__MASK 0x0003C000L
-#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV1__MASK 0x001C0000L
-#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV1__MASK 0x01E00000L
-#define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DEV1__MASK 0x06000000L
-#define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV1__MASK 0x18000000L
-#define RCC_DEV1_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV1__MASK 0x20000000L
-#define RCC_DEV1_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV1__MASK 0x40000000L
-#define RCC_DEV1_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV1__MASK 0x80000000L
-//RCC_DEV1_PORT_STRAP4
-#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV1__MASK 0x000000FFL
-#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV1__MASK 0x0000FF00L
-#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV1__MASK 0x00FF0000L
-#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV1__MASK 0xFF000000L
-//RCC_DEV1_PORT_STRAP5
-#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV1__MASK 0x000000FFL
-#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV1__MASK 0x0000FF00L
-#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV1__MASK 0x00010000L
-#define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV1__MASK 0x00020000L
-#define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV1__MASK 0x00040000L
-#define RCC_DEV1_PORT_STRAP5__STRAP_VC_EN_DN_DEV1__MASK 0x00080000L
-#define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DEV1__MASK 0x00100000L
-#define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV1__MASK 0x00200000L
-#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV1__MASK 0x00800000L
-#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV1__MASK 0x01000000L
-#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV1__MASK 0x02000000L
-#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV1__MASK 0x04000000L
-#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV1__MASK 0x08000000L
-#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV1__MASK 0x10000000L
-#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV1__MASK 0x20000000L
-#define RCC_DEV1_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV1__MASK 0x40000000L
-#define RCC_DEV1_PORT_STRAP5__STRAP_SSID_EN_DEV1__MASK 0x80000000L
-//RCC_DEV1_PORT_STRAP6
-#define RCC_DEV1_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV1__MASK 0x00000001L
-#define RCC_DEV1_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV1__MASK 0x00000002L
-//RCC_DEV1_PORT_STRAP7
-#define RCC_DEV1_PORT_STRAP7__STRAP_PORT_NUMBER_DEV1__MASK 0x000000FFL
-#define RCC_DEV1_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV1__MASK 0x00000F00L
-#define RCC_DEV1_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV1__MASK 0x0000F000L
-#define RCC_DEV1_PORT_STRAP7__STRAP_RP_BUSNUM_DEV1__MASK 0x00FF0000L
-#define RCC_DEV1_PORT_STRAP7__STRAP_DN_DEVNUM_DEV1__MASK 0x1F000000L
-#define RCC_DEV1_PORT_STRAP7__STRAP_DN_FUNCID_DEV1__MASK 0xE0000000L
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__MASK 0x0000FFFFL
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__MASK 0x000F0000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__MASK 0x00F00000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__MASK 0x0F000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__MASK 0x10000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__MASK 0x20000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__MASK 0x40000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__MASK 0x80000000L
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__MASK 0x0000FFFFL
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__MASK 0xFFFF0000L
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__MASK 0x00000001L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__MASK 0x0000003EL
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__MASK 0x00000040L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__MASK 0x00000080L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__MASK 0x00000100L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__MASK 0x00003E00L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__MASK 0x00004000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__MASK 0x00008000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__MASK 0x00010000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__MASK 0x00020000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__MASK 0x00040000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__MASK 0x00100000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__MASK 0x00200000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__MASK 0x00400000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__MASK 0x00800000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__MASK 0x07000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__MASK 0x08000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__MASK 0x10000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__MASK 0x20000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__MASK 0x40000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__MASK 0x80000000L
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__MASK 0x00000001L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__MASK 0x00000002L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__MASK 0x0003FFFCL
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__MASK 0x00040000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__MASK 0x00080000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__MASK 0x00100000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__MASK 0x00E00000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__MASK 0x01000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__MASK 0x02000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__MASK 0x04000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__MASK 0x08000000L
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_MSIX_TABLE_OFFSET_DEV0_F0__MASK 0x000FFFFFL
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__MASK 0x00100000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__MASK 0x00200000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__MASK 0x00400000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__MASK 0x0F800000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__MASK 0x70000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__MASK 0x80000000L
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__MASK 0x0000FFFFL
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__MASK 0x00000001L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__MASK 0x00000006L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__MASK 0x00000008L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__MASK 0x00000010L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__MASK 0x00000060L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__MASK 0x00000080L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__MASK 0x00000100L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__MASK 0x00000E00L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__MASK 0x00003000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__MASK 0x0000C000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__MASK 0x00070000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__MASK 0x00380000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__MASK 0x00C00000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__MASK 0x01000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__MASK 0x02000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_PROT_DIS_DEV0_F0__MASK 0x04000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__MASK 0x38000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__MASK 0xC0000000L
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP9
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__MASK 0x000000FFL
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__MASK 0x0000FF00L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__MASK 0x00FF0000L
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__MASK 0x0000FFFFL
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__MASK 0x000F0000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__MASK 0x00F00000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__MASK 0x10000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__MASK 0x20000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__MASK 0x40000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__MASK 0x80000000L
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__MASK 0x00000080L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__MASK 0x00000100L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__MASK 0x00004000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__MASK 0x00010000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__MASK 0x00020000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__MASK 0x00040000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__MASK 0x00100000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__MASK 0x00200000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__MASK 0x00400000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__MASK 0x00800000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__MASK 0x07000000L
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__MASK 0x00000001L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__MASK 0x00000002L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__MASK 0x0003FFFCL
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__MASK 0x00040000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__MASK 0x00080000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__MASK 0x00100000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__MASK 0x01000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__MASK 0x02000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__MASK 0x04000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__MASK 0x08000000L
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__MASK 0x00100000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__MASK 0x00200000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__MASK 0x00400000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__MASK 0x0F800000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__MASK 0x70000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__MASK 0x80000000L
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__MASK 0x0000FFFFL
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__MASK 0x00000001L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__MASK 0x00000002L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__MASK 0x00000004L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__MASK 0x00000070L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__MASK 0x00000100L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__MASK 0x00000200L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__MASK 0x00010000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__MASK 0x00020000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__MASK 0x01000000L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__MASK 0x02000000L
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__MASK 0x00000001L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__MASK 0x0000001EL
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__MASK 0x00000001L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__MASK 0x001FFFFEL
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__MASK 0x00000001L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__MASK 0x001FFFFEL
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__MASK 0x00000001L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__MASK 0x001FFFFEL
-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__MASK 0x000000FFL
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__MASK 0x0000FF00L
-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__MASK 0x00FF0000L
-//RCC_DEV0_EPF2_STRAP0
-#define RCC_DEV0_EPF2_STRAP0__STRAP_DEVICE_ID_DEV0_F2__MASK 0x0000FFFFL
-#define RCC_DEV0_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F2__MASK 0x000F0000L
-#define RCC_DEV0_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV0_F2__MASK 0x00F00000L
-#define RCC_DEV0_EPF2_STRAP0__STRAP_FUNC_EN_DEV0_F2__MASK 0x10000000L
-#define RCC_DEV0_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2__MASK 0x20000000L
-#define RCC_DEV0_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV0_F2__MASK 0x40000000L
-#define RCC_DEV0_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV0_F2__MASK 0x80000000L
-//RCC_DEV0_EPF2_STRAP2
-#define RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2__MASK 0x00000080L
-#define RCC_DEV0_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F2__MASK 0x00000100L
-#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2__MASK 0x00004000L
-#define RCC_DEV0_EPF2_STRAP2__STRAP_AER_EN_DEV0_F2__MASK 0x00010000L
-#define RCC_DEV0_EPF2_STRAP2__STRAP_ACS_EN_DEV0_F2__MASK 0x00020000L
-#define RCC_DEV0_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F2__MASK 0x00100000L
-#define RCC_DEV0_EPF2_STRAP2__STRAP_DPA_EN_DEV0_F2__MASK 0x00200000L
-#define RCC_DEV0_EPF2_STRAP2__STRAP_VC_EN_DEV0_F2__MASK 0x00800000L
-#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F2__MASK 0x07000000L
-//RCC_DEV0_EPF2_STRAP3
-#define RCC_DEV0_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2__MASK 0x00000001L
-#define RCC_DEV0_EPF2_STRAP3__STRAP_PWR_EN_DEV0_F2__MASK 0x00000002L
-#define RCC_DEV0_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV0_F2__MASK 0x0003FFFCL
-#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_EN_DEV0_F2__MASK 0x00040000L
-#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F2__MASK 0x00080000L
-#define RCC_DEV0_EPF2_STRAP3__STRAP_MSIX_EN_DEV0_F2__MASK 0x00100000L
-#define RCC_DEV0_EPF2_STRAP3__STRAP_PMC_DSI_DEV0_F2__MASK 0x01000000L
-#define RCC_DEV0_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F2__MASK 0x02000000L
-#define RCC_DEV0_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2__MASK 0x04000000L
-#define RCC_DEV0_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2__MASK 0x08000000L
-//RCC_DEV0_EPF2_STRAP4
-#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F2__MASK 0x00100000L
-#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV0_F2__MASK 0x00200000L
-#define RCC_DEV0_EPF2_STRAP4__STRAP_FLR_EN_DEV0_F2__MASK 0x00400000L
-#define RCC_DEV0_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV0_F2__MASK 0x0F800000L
-#define RCC_DEV0_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F2__MASK 0x70000000L
-#define RCC_DEV0_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F2__MASK 0x80000000L
-//RCC_DEV0_EPF2_STRAP5
-#define RCC_DEV0_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F2__MASK 0x0000FFFFL
-#define RCC_DEV0_EPF2_STRAP5__STRAP_SATAIDP_EN_DEV0_F2__MASK 0x01000000L
-//RCC_DEV0_EPF2_STRAP6
-#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_EN_DEV0_F2__MASK 0x00000001L
-#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F2__MASK 0x00000002L
-#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F2__MASK 0x00000070L
-#define RCC_DEV0_EPF2_STRAP6__STRAP_APER1_EN_DEV0_F2__MASK 0x00000100L
-#define RCC_DEV0_EPF2_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F2__MASK 0x00000200L
-//RCC_DEV0_EPF2_STRAP13
-#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F2__MASK 0x000000FFL
-#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F2__MASK 0x0000FF00L
-#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F2__MASK 0x00FF0000L
-//RCC_DEV0_EPF3_STRAP0
-#define RCC_DEV0_EPF3_STRAP0__STRAP_DEVICE_ID_DEV0_F3__MASK 0x0000FFFFL
-#define RCC_DEV0_EPF3_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F3__MASK 0x000F0000L
-#define RCC_DEV0_EPF3_STRAP0__STRAP_MINOR_REV_ID_DEV0_F3__MASK 0x00F00000L
-#define RCC_DEV0_EPF3_STRAP0__STRAP_FUNC_EN_DEV0_F3__MASK 0x10000000L
-#define RCC_DEV0_EPF3_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3__MASK 0x20000000L
-#define RCC_DEV0_EPF3_STRAP0__STRAP_D1_SUPPORT_DEV0_F3__MASK 0x40000000L
-#define RCC_DEV0_EPF3_STRAP0__STRAP_D2_SUPPORT_DEV0_F3__MASK 0x80000000L
-//RCC_DEV0_EPF3_STRAP2
-#define RCC_DEV0_EPF3_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F3__MASK 0x00000080L
-#define RCC_DEV0_EPF3_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F3__MASK 0x00000100L
-#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3__MASK 0x00004000L
-#define RCC_DEV0_EPF3_STRAP2__STRAP_AER_EN_DEV0_F3__MASK 0x00010000L
-#define RCC_DEV0_EPF3_STRAP2__STRAP_ACS_EN_DEV0_F3__MASK 0x00020000L
-#define RCC_DEV0_EPF3_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F3__MASK 0x00100000L
-#define RCC_DEV0_EPF3_STRAP2__STRAP_DPA_EN_DEV0_F3__MASK 0x00200000L
-#define RCC_DEV0_EPF3_STRAP2__STRAP_VC_EN_DEV0_F3__MASK 0x00800000L
-#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F3__MASK 0x07000000L
-//RCC_DEV0_EPF3_STRAP3
-#define RCC_DEV0_EPF3_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3__MASK 0x00000001L
-#define RCC_DEV0_EPF3_STRAP3__STRAP_PWR_EN_DEV0_F3__MASK 0x00000002L
-#define RCC_DEV0_EPF3_STRAP3__STRAP_SUBSYS_ID_DEV0_F3__MASK 0x0003FFFCL
-#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_EN_DEV0_F3__MASK 0x00040000L
-#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F3__MASK 0x00080000L
-#define RCC_DEV0_EPF3_STRAP3__STRAP_MSIX_EN_DEV0_F3__MASK 0x00100000L
-#define RCC_DEV0_EPF3_STRAP3__STRAP_PMC_DSI_DEV0_F3__MASK 0x01000000L
-#define RCC_DEV0_EPF3_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F3__MASK 0x02000000L
-#define RCC_DEV0_EPF3_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3__MASK 0x04000000L
-#define RCC_DEV0_EPF3_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3__MASK 0x08000000L
-//RCC_DEV0_EPF3_STRAP4
-#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F3__MASK 0x00100000L
-#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_EN_DEV0_F3__MASK 0x00200000L
-#define RCC_DEV0_EPF3_STRAP4__STRAP_FLR_EN_DEV0_F3__MASK 0x00400000L
-#define RCC_DEV0_EPF3_STRAP4__STRAP_PME_SUPPORT_DEV0_F3__MASK 0x0F800000L
-#define RCC_DEV0_EPF3_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F3__MASK 0x70000000L
-#define RCC_DEV0_EPF3_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F3__MASK 0x80000000L
-//RCC_DEV0_EPF3_STRAP5
-#define RCC_DEV0_EPF3_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F3__MASK 0x0000FFFFL
-#define RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESEL_DEV0_F3__MASK 0x000F0000L
-#define RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESELD_DEV0_F3__MASK 0x00F00000L
-//RCC_DEV0_EPF3_STRAP6
-#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_EN_DEV0_F3__MASK 0x00000001L
-#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F3__MASK 0x00000002L
-#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F3__MASK 0x00000070L
-//RCC_DEV0_EPF3_STRAP13
-#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F3__MASK 0x000000FFL
-#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F3__MASK 0x0000FF00L
-#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F3__MASK 0x00FF0000L
-//RCC_DEV0_EPF4_STRAP0
-#define RCC_DEV0_EPF4_STRAP0__STRAP_DEVICE_ID_DEV0_F4__MASK 0x0000FFFFL
-#define RCC_DEV0_EPF4_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F4__MASK 0x000F0000L
-#define RCC_DEV0_EPF4_STRAP0__STRAP_MINOR_REV_ID_DEV0_F4__MASK 0x00F00000L
-#define RCC_DEV0_EPF4_STRAP0__STRAP_FUNC_EN_DEV0_F4__MASK 0x10000000L
-#define RCC_DEV0_EPF4_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F4__MASK 0x20000000L
-#define RCC_DEV0_EPF4_STRAP0__STRAP_D1_SUPPORT_DEV0_F4__MASK 0x40000000L
-#define RCC_DEV0_EPF4_STRAP0__STRAP_D2_SUPPORT_DEV0_F4__MASK 0x80000000L
-//RCC_DEV0_EPF4_STRAP2
-#define RCC_DEV0_EPF4_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F4__MASK 0x00000080L
-#define RCC_DEV0_EPF4_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F4__MASK 0x00000100L
-#define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F4__MASK 0x00004000L
-#define RCC_DEV0_EPF4_STRAP2__STRAP_AER_EN_DEV0_F4__MASK 0x00010000L
-#define RCC_DEV0_EPF4_STRAP2__STRAP_ACS_EN_DEV0_F4__MASK 0x00020000L
-#define RCC_DEV0_EPF4_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F4__MASK 0x00100000L
-#define RCC_DEV0_EPF4_STRAP2__STRAP_DPA_EN_DEV0_F4__MASK 0x00200000L
-#define RCC_DEV0_EPF4_STRAP2__STRAP_VC_EN_DEV0_F4__MASK 0x00800000L
-#define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F4__MASK 0x07000000L
-//RCC_DEV0_EPF4_STRAP3
-#define RCC_DEV0_EPF4_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F4__MASK 0x00000001L
-#define RCC_DEV0_EPF4_STRAP3__STRAP_PWR_EN_DEV0_F4__MASK 0x00000002L
-#define RCC_DEV0_EPF4_STRAP3__STRAP_SUBSYS_ID_DEV0_F4__MASK 0x0003FFFCL
-#define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_EN_DEV0_F4__MASK 0x00040000L
-#define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F4__MASK 0x00080000L
-#define RCC_DEV0_EPF4_STRAP3__STRAP_MSIX_EN_DEV0_F4__MASK 0x00100000L
-#define RCC_DEV0_EPF4_STRAP3__STRAP_PMC_DSI_DEV0_F4__MASK 0x01000000L
-#define RCC_DEV0_EPF4_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F4__MASK 0x02000000L
-#define RCC_DEV0_EPF4_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F4__MASK 0x04000000L
-#define RCC_DEV0_EPF4_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F4__MASK 0x08000000L
-//RCC_DEV0_EPF4_STRAP4
-#define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F4__MASK 0x00100000L
-#define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_EN_DEV0_F4__MASK 0x00200000L
-#define RCC_DEV0_EPF4_STRAP4__STRAP_FLR_EN_DEV0_F4__MASK 0x00400000L
-#define RCC_DEV0_EPF4_STRAP4__STRAP_PME_SUPPORT_DEV0_F4__MASK 0x0F800000L
-#define RCC_DEV0_EPF4_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F4__MASK 0x70000000L
-#define RCC_DEV0_EPF4_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F4__MASK 0x80000000L
-//RCC_DEV0_EPF4_STRAP5
-#define RCC_DEV0_EPF4_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F4__MASK 0x0000FFFFL
-#define RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESEL_DEV0_F4__MASK 0x000F0000L
-#define RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESELD_DEV0_F4__MASK 0x00F00000L
-//RCC_DEV0_EPF4_STRAP6
-#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_EN_DEV0_F4__MASK 0x00000001L
-#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F4__MASK 0x00000002L
-#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F4__MASK 0x00000070L
-#define RCC_DEV0_EPF4_STRAP6__STRAP_APER1_EN_DEV0_F4__MASK 0x00000100L
-#define RCC_DEV0_EPF4_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F4__MASK 0x00000200L
-#define RCC_DEV0_EPF4_STRAP6__STRAP_APER2_EN_DEV0_F4__MASK 0x00010000L
-#define RCC_DEV0_EPF4_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F4__MASK 0x00020000L
-//RCC_DEV0_EPF4_STRAP13
-#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F4__MASK 0x000000FFL
-#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F4__MASK 0x0000FF00L
-#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F4__MASK 0x00FF0000L
-//RCC_DEV0_EPF5_STRAP0
-#define RCC_DEV0_EPF5_STRAP0__STRAP_DEVICE_ID_DEV0_F5__MASK 0x0000FFFFL
-#define RCC_DEV0_EPF5_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F5__MASK 0x000F0000L
-#define RCC_DEV0_EPF5_STRAP0__STRAP_MINOR_REV_ID_DEV0_F5__MASK 0x00F00000L
-#define RCC_DEV0_EPF5_STRAP0__STRAP_FUNC_EN_DEV0_F5__MASK 0x10000000L
-#define RCC_DEV0_EPF5_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F5__MASK 0x20000000L
-#define RCC_DEV0_EPF5_STRAP0__STRAP_D1_SUPPORT_DEV0_F5__MASK 0x40000000L
-#define RCC_DEV0_EPF5_STRAP0__STRAP_D2_SUPPORT_DEV0_F5__MASK 0x80000000L
-//RCC_DEV0_EPF5_STRAP2
-#define RCC_DEV0_EPF5_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F5__MASK 0x00000080L
-#define RCC_DEV0_EPF5_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F5__MASK 0x00000100L
-#define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F5__MASK 0x00004000L
-#define RCC_DEV0_EPF5_STRAP2__STRAP_AER_EN_DEV0_F5__MASK 0x00010000L
-#define RCC_DEV0_EPF5_STRAP2__STRAP_ACS_EN_DEV0_F5__MASK 0x00020000L
-#define RCC_DEV0_EPF5_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F5__MASK 0x00100000L
-#define RCC_DEV0_EPF5_STRAP2__STRAP_DPA_EN_DEV0_F5__MASK 0x00200000L
-#define RCC_DEV0_EPF5_STRAP2__STRAP_VC_EN_DEV0_F5__MASK 0x00800000L
-#define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F5__MASK 0x07000000L
-//RCC_DEV0_EPF5_STRAP3
-#define RCC_DEV0_EPF5_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F5__MASK 0x00000001L
-#define RCC_DEV0_EPF5_STRAP3__STRAP_PWR_EN_DEV0_F5__MASK 0x00000002L
-#define RCC_DEV0_EPF5_STRAP3__STRAP_SUBSYS_ID_DEV0_F5__MASK 0x0003FFFCL
-#define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_EN_DEV0_F5__MASK 0x00040000L
-#define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F5__MASK 0x00080000L
-#define RCC_DEV0_EPF5_STRAP3__STRAP_MSIX_EN_DEV0_F5__MASK 0x00100000L
-#define RCC_DEV0_EPF5_STRAP3__STRAP_PMC_DSI_DEV0_F5__MASK 0x01000000L
-#define RCC_DEV0_EPF5_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F5__MASK 0x02000000L
-#define RCC_DEV0_EPF5_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F5__MASK 0x04000000L
-#define RCC_DEV0_EPF5_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F5__MASK 0x08000000L
-//RCC_DEV0_EPF5_STRAP4
-#define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F5__MASK 0x00100000L
-#define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_EN_DEV0_F5__MASK 0x00200000L
-#define RCC_DEV0_EPF5_STRAP4__STRAP_FLR_EN_DEV0_F5__MASK 0x00400000L
-#define RCC_DEV0_EPF5_STRAP4__STRAP_PME_SUPPORT_DEV0_F5__MASK 0x0F800000L
-#define RCC_DEV0_EPF5_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F5__MASK 0x70000000L
-#define RCC_DEV0_EPF5_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F5__MASK 0x80000000L
-//RCC_DEV0_EPF5_STRAP5
-#define RCC_DEV0_EPF5_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F5__MASK 0x0000FFFFL
-//RCC_DEV0_EPF5_STRAP6
-#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_EN_DEV0_F5__MASK 0x00000001L
-#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F5__MASK 0x00000002L
-#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F5__MASK 0x00000070L
-#define RCC_DEV0_EPF5_STRAP6__STRAP_APER1_EN_DEV0_F5__MASK 0x00000100L
-#define RCC_DEV0_EPF5_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F5__MASK 0x00000200L
-#define RCC_DEV0_EPF5_STRAP6__STRAP_APER2_EN_DEV0_F5__MASK 0x00010000L
-#define RCC_DEV0_EPF5_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F5__MASK 0x00020000L
-//RCC_DEV0_EPF5_STRAP13
-#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F5__MASK 0x000000FFL
-#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F5__MASK 0x0000FF00L
-#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F5__MASK 0x00FF0000L
-//RCC_DEV0_EPF6_STRAP0
-#define RCC_DEV0_EPF6_STRAP0__STRAP_DEVICE_ID_DEV0_F6__MASK 0x0000FFFFL
-#define RCC_DEV0_EPF6_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F6__MASK 0x000F0000L
-#define RCC_DEV0_EPF6_STRAP0__STRAP_MINOR_REV_ID_DEV0_F6__MASK 0x00F00000L
-#define RCC_DEV0_EPF6_STRAP0__STRAP_FUNC_EN_DEV0_F6__MASK 0x10000000L
-#define RCC_DEV0_EPF6_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F6__MASK 0x20000000L
-#define RCC_DEV0_EPF6_STRAP0__STRAP_D1_SUPPORT_DEV0_F6__MASK 0x40000000L
-#define RCC_DEV0_EPF6_STRAP0__STRAP_D2_SUPPORT_DEV0_F6__MASK 0x80000000L
-//RCC_DEV0_EPF6_STRAP2
-#define RCC_DEV0_EPF6_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F6__MASK 0x00000080L
-#define RCC_DEV0_EPF6_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F6__MASK 0x00000100L
-#define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F6__MASK 0x00004000L
-#define RCC_DEV0_EPF6_STRAP2__STRAP_AER_EN_DEV0_F6__MASK 0x00010000L
-#define RCC_DEV0_EPF6_STRAP2__STRAP_ACS_EN_DEV0_F6__MASK 0x00020000L
-#define RCC_DEV0_EPF6_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F6__MASK 0x00100000L
-#define RCC_DEV0_EPF6_STRAP2__STRAP_DPA_EN_DEV0_F6__MASK 0x00200000L
-#define RCC_DEV0_EPF6_STRAP2__STRAP_VC_EN_DEV0_F6__MASK 0x00800000L
-#define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F6__MASK 0x07000000L
-//RCC_DEV0_EPF6_STRAP3
-#define RCC_DEV0_EPF6_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F6__MASK 0x00000001L
-#define RCC_DEV0_EPF6_STRAP3__STRAP_PWR_EN_DEV0_F6__MASK 0x00000002L
-#define RCC_DEV0_EPF6_STRAP3__STRAP_SUBSYS_ID_DEV0_F6__MASK 0x0003FFFCL
-#define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_EN_DEV0_F6__MASK 0x00040000L
-#define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F6__MASK 0x00080000L
-#define RCC_DEV0_EPF6_STRAP3__STRAP_MSIX_EN_DEV0_F6__MASK 0x00100000L
-#define RCC_DEV0_EPF6_STRAP3__STRAP_PMC_DSI_DEV0_F6__MASK 0x01000000L
-#define RCC_DEV0_EPF6_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F6__MASK 0x02000000L
-#define RCC_DEV0_EPF6_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F6__MASK 0x04000000L
-#define RCC_DEV0_EPF6_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F6__MASK 0x08000000L
-//RCC_DEV0_EPF6_STRAP4
-#define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F6__MASK 0x00100000L
-#define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_EN_DEV0_F6__MASK 0x00200000L
-#define RCC_DEV0_EPF6_STRAP4__STRAP_FLR_EN_DEV0_F6__MASK 0x00400000L
-#define RCC_DEV0_EPF6_STRAP4__STRAP_PME_SUPPORT_DEV0_F6__MASK 0x0F800000L
-#define RCC_DEV0_EPF6_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F6__MASK 0x70000000L
-#define RCC_DEV0_EPF6_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F6__MASK 0x80000000L
-//RCC_DEV0_EPF6_STRAP5
-#define RCC_DEV0_EPF6_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F6__MASK 0x0000FFFFL
-//RCC_DEV0_EPF6_STRAP6
-#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_EN_DEV0_F6__MASK 0x00000001L
-#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F6__MASK 0x00000002L
-#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F6__MASK 0x00000070L
-#define RCC_DEV0_EPF6_STRAP6__STRAP_APER1_EN_DEV0_F6__MASK 0x00000100L
-#define RCC_DEV0_EPF6_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F6__MASK 0x00000200L
-#define RCC_DEV0_EPF6_STRAP6__STRAP_APER2_EN_DEV0_F6__MASK 0x00010000L
-#define RCC_DEV0_EPF6_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F6__MASK 0x00020000L
-//RCC_DEV0_EPF6_STRAP13
-#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F6__MASK 0x000000FFL
-#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F6__MASK 0x0000FF00L
-#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F6__MASK 0x00FF0000L
-//RCC_DEV0_EPF7_STRAP0
-#define RCC_DEV0_EPF7_STRAP0__STRAP_DEVICE_ID_DEV0_F7__MASK 0x0000FFFFL
-#define RCC_DEV0_EPF7_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F7__MASK 0x000F0000L
-#define RCC_DEV0_EPF7_STRAP0__STRAP_MINOR_REV_ID_DEV0_F7__MASK 0x00F00000L
-#define RCC_DEV0_EPF7_STRAP0__STRAP_FUNC_EN_DEV0_F7__MASK 0x10000000L
-#define RCC_DEV0_EPF7_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F7__MASK 0x20000000L
-#define RCC_DEV0_EPF7_STRAP0__STRAP_D1_SUPPORT_DEV0_F7__MASK 0x40000000L
-#define RCC_DEV0_EPF7_STRAP0__STRAP_D2_SUPPORT_DEV0_F7__MASK 0x80000000L
-//RCC_DEV0_EPF7_STRAP2
-#define RCC_DEV0_EPF7_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F7__MASK 0x00000080L
-#define RCC_DEV0_EPF7_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F7__MASK 0x00000100L
-#define RCC_DEV0_EPF7_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F7__MASK 0x00004000L
-#define RCC_DEV0_EPF7_STRAP2__STRAP_AER_EN_DEV0_F7__MASK 0x00010000L
-#define RCC_DEV0_EPF7_STRAP2__STRAP_ACS_EN_DEV0_F7__MASK 0x00020000L
-#define RCC_DEV0_EPF7_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F7__MASK 0x00100000L
-#define RCC_DEV0_EPF7_STRAP2__STRAP_DPA_EN_DEV0_F7__MASK 0x00200000L
-#define RCC_DEV0_EPF7_STRAP2__STRAP_VC_EN_DEV0_F7__MASK 0x00800000L
-#define RCC_DEV0_EPF7_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F7__MASK 0x07000000L
-//RCC_DEV0_EPF7_STRAP3
-#define RCC_DEV0_EPF7_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F7__MASK 0x00000001L
-#define RCC_DEV0_EPF7_STRAP3__STRAP_PWR_EN_DEV0_F7__MASK 0x00000002L
-#define RCC_DEV0_EPF7_STRAP3__STRAP_SUBSYS_ID_DEV0_F7__MASK 0x0003FFFCL
-#define RCC_DEV0_EPF7_STRAP3__STRAP_MSI_EN_DEV0_F7__MASK 0x00040000L
-#define RCC_DEV0_EPF7_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F7__MASK 0x00080000L
-#define RCC_DEV0_EPF7_STRAP3__STRAP_MSIX_EN_DEV0_F7__MASK 0x00100000L
-#define RCC_DEV0_EPF7_STRAP3__STRAP_PMC_DSI_DEV0_F7__MASK 0x01000000L
-#define RCC_DEV0_EPF7_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F7__MASK 0x02000000L
-#define RCC_DEV0_EPF7_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F7__MASK 0x04000000L
-#define RCC_DEV0_EPF7_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F7__MASK 0x08000000L
-//RCC_DEV0_EPF7_STRAP4
-#define RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F7__MASK 0x00100000L
-#define RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_EN_DEV0_F7__MASK 0x00200000L
-#define RCC_DEV0_EPF7_STRAP4__STRAP_FLR_EN_DEV0_F7__MASK 0x00400000L
-#define RCC_DEV0_EPF7_STRAP4__STRAP_PME_SUPPORT_DEV0_F7__MASK 0x0F800000L
-#define RCC_DEV0_EPF7_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F7__MASK 0x70000000L
-#define RCC_DEV0_EPF7_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F7__MASK 0x80000000L
-//RCC_DEV0_EPF7_STRAP5
-#define RCC_DEV0_EPF7_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F7__MASK 0x0000FFFFL
-//RCC_DEV0_EPF7_STRAP6
-#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_EN_DEV0_F7__MASK 0x00000001L
-#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F7__MASK 0x00000002L
-#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F7__MASK 0x00000070L
-#define RCC_DEV0_EPF7_STRAP6__STRAP_APER1_EN_DEV0_F7__MASK 0x00000100L
-#define RCC_DEV0_EPF7_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F7__MASK 0x00000200L
-#define RCC_DEV0_EPF7_STRAP6__STRAP_APER2_EN_DEV0_F7__MASK 0x00010000L
-#define RCC_DEV0_EPF7_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F7__MASK 0x00020000L
-//RCC_DEV0_EPF7_STRAP13
-#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F7__MASK 0x000000FFL
-#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F7__MASK 0x0000FF00L
-#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F7__MASK 0x00FF0000L
-//RCC_DEV1_EPF0_STRAP0
-#define RCC_DEV1_EPF0_STRAP0__STRAP_DEVICE_ID_DEV1_F0__MASK 0x0000FFFFL
-#define RCC_DEV1_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F0__MASK 0x000F0000L
-#define RCC_DEV1_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV1_F0__MASK 0x00F00000L
-#define RCC_DEV1_EPF0_STRAP0__STRAP_FUNC_EN_DEV1_F0__MASK 0x10000000L
-#define RCC_DEV1_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F0__MASK 0x20000000L
-#define RCC_DEV1_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV1_F0__MASK 0x40000000L
-#define RCC_DEV1_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV1_F0__MASK 0x80000000L
-//RCC_DEV1_EPF0_STRAP2
-#define RCC_DEV1_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F0__MASK 0x00000080L
-#define RCC_DEV1_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F0__MASK 0x00000100L
-#define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F0__MASK 0x00004000L
-#define RCC_DEV1_EPF0_STRAP2__STRAP_ARI_EN_DEV1_F0__MASK 0x00008000L
-#define RCC_DEV1_EPF0_STRAP2__STRAP_AER_EN_DEV1_F0__MASK 0x00010000L
-#define RCC_DEV1_EPF0_STRAP2__STRAP_ACS_EN_DEV1_F0__MASK 0x00020000L
-#define RCC_DEV1_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F0__MASK 0x00100000L
-#define RCC_DEV1_EPF0_STRAP2__STRAP_DPA_EN_DEV1_F0__MASK 0x00200000L
-#define RCC_DEV1_EPF0_STRAP2__STRAP_VC_EN_DEV1_F0__MASK 0x00800000L
-#define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F0__MASK 0x07000000L
-//RCC_DEV1_EPF0_STRAP3
-#define RCC_DEV1_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F0__MASK 0x00000001L
-#define RCC_DEV1_EPF0_STRAP3__STRAP_PWR_EN_DEV1_F0__MASK 0x00000002L
-#define RCC_DEV1_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV1_F0__MASK 0x0003FFFCL
-#define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_EN_DEV1_F0__MASK 0x00040000L
-#define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F0__MASK 0x00080000L
-#define RCC_DEV1_EPF0_STRAP3__STRAP_MSIX_EN_DEV1_F0__MASK 0x00100000L
-#define RCC_DEV1_EPF0_STRAP3__STRAP_PMC_DSI_DEV1_F0__MASK 0x01000000L
-#define RCC_DEV1_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F0__MASK 0x02000000L
-#define RCC_DEV1_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F0__MASK 0x04000000L
-#define RCC_DEV1_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F0__MASK 0x08000000L
-//RCC_DEV1_EPF0_STRAP4
-#define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F0__MASK 0x00100000L
-#define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV1_F0__MASK 0x00200000L
-#define RCC_DEV1_EPF0_STRAP4__STRAP_FLR_EN_DEV1_F0__MASK 0x00400000L
-#define RCC_DEV1_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV1_F0__MASK 0x0F800000L
-#define RCC_DEV1_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F0__MASK 0x70000000L
-#define RCC_DEV1_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F0__MASK 0x80000000L
-//RCC_DEV1_EPF0_STRAP5
-#define RCC_DEV1_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F0__MASK 0x0000FFFFL
-#define RCC_DEV1_EPF0_STRAP5__STRAP_SATAIDP_EN_DEV1_F0__MASK 0x01000000L
-//RCC_DEV1_EPF0_STRAP6
-#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_EN_DEV1_F0__MASK 0x00000001L
-#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F0__MASK 0x00000002L
-#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F0__MASK 0x00000070L
-//RCC_DEV1_EPF0_STRAP13
-#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F0__MASK 0x000000FFL
-#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F0__MASK 0x0000FF00L
-#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F0__MASK 0x00FF0000L
-//RCC_DEV1_EPF1_STRAP0
-#define RCC_DEV1_EPF1_STRAP0__STRAP_DEVICE_ID_DEV1_F1__MASK 0x0000FFFFL
-#define RCC_DEV1_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F1__MASK 0x000F0000L
-#define RCC_DEV1_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV1_F1__MASK 0x00F00000L
-#define RCC_DEV1_EPF1_STRAP0__STRAP_FUNC_EN_DEV1_F1__MASK 0x10000000L
-#define RCC_DEV1_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F1__MASK 0x20000000L
-#define RCC_DEV1_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV1_F1__MASK 0x40000000L
-#define RCC_DEV1_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV1_F1__MASK 0x80000000L
-//RCC_DEV1_EPF1_STRAP2
-#define RCC_DEV1_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F1__MASK 0x00000080L
-#define RCC_DEV1_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F1__MASK 0x00000100L
-#define RCC_DEV1_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F1__MASK 0x00004000L
-#define RCC_DEV1_EPF1_STRAP2__STRAP_AER_EN_DEV1_F1__MASK 0x00010000L
-#define RCC_DEV1_EPF1_STRAP2__STRAP_ACS_EN_DEV1_F1__MASK 0x00020000L
-#define RCC_DEV1_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F1__MASK 0x00100000L
-#define RCC_DEV1_EPF1_STRAP2__STRAP_DPA_EN_DEV1_F1__MASK 0x00200000L
-#define RCC_DEV1_EPF1_STRAP2__STRAP_VC_EN_DEV1_F1__MASK 0x00800000L
-#define RCC_DEV1_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F1__MASK 0x07000000L
-//RCC_DEV1_EPF1_STRAP3
-#define RCC_DEV1_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F1__MASK 0x00000001L
-#define RCC_DEV1_EPF1_STRAP3__STRAP_PWR_EN_DEV1_F1__MASK 0x00000002L
-#define RCC_DEV1_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV1_F1__MASK 0x0003FFFCL
-#define RCC_DEV1_EPF1_STRAP3__STRAP_MSI_EN_DEV1_F1__MASK 0x00040000L
-#define RCC_DEV1_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F1__MASK 0x00080000L
-#define RCC_DEV1_EPF1_STRAP3__STRAP_MSIX_EN_DEV1_F1__MASK 0x00100000L
-#define RCC_DEV1_EPF1_STRAP3__STRAP_PMC_DSI_DEV1_F1__MASK 0x01000000L
-#define RCC_DEV1_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F1__MASK 0x02000000L
-#define RCC_DEV1_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F1__MASK 0x04000000L
-#define RCC_DEV1_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F1__MASK 0x08000000L
-//RCC_DEV1_EPF1_STRAP4
-#define RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F1__MASK 0x00100000L
-#define RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV1_F1__MASK 0x00200000L
-#define RCC_DEV1_EPF1_STRAP4__STRAP_FLR_EN_DEV1_F1__MASK 0x00400000L
-#define RCC_DEV1_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV1_F1__MASK 0x0F800000L
-#define RCC_DEV1_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F1__MASK 0x70000000L
-#define RCC_DEV1_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F1__MASK 0x80000000L
-//RCC_DEV1_EPF1_STRAP5
-#define RCC_DEV1_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F1__MASK 0x0000FFFFL
-//RCC_DEV1_EPF1_STRAP6
-#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_EN_DEV1_F1__MASK 0x00000001L
-#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F1__MASK 0x00000002L
-#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F1__MASK 0x00000070L
-#define RCC_DEV1_EPF1_STRAP6__STRAP_APER1_EN_DEV1_F1__MASK 0x00000100L
-#define RCC_DEV1_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV1_F1__MASK 0x00000200L
-#define RCC_DEV1_EPF1_STRAP6__STRAP_APER2_EN_DEV1_F1__MASK 0x00010000L
-#define RCC_DEV1_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV1_F1__MASK 0x00020000L
-#define RCC_DEV1_EPF1_STRAP6__STRAP_APER3_EN_DEV1_F1__MASK 0x01000000L
-#define RCC_DEV1_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV1_F1__MASK 0x02000000L
-//RCC_DEV1_EPF1_STRAP13
-#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F1__MASK 0x000000FFL
-#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F1__MASK 0x0000FF00L
-#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F1__MASK 0x00FF0000L
-//RCC_DEV1_EPF2_STRAP0
-#define RCC_DEV1_EPF2_STRAP0__STRAP_DEVICE_ID_DEV1_F2__MASK 0x0000FFFFL
-#define RCC_DEV1_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F2__MASK 0x000F0000L
-#define RCC_DEV1_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV1_F2__MASK 0x00F00000L
-#define RCC_DEV1_EPF2_STRAP0__STRAP_FUNC_EN_DEV1_F2__MASK 0x10000000L
-#define RCC_DEV1_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F2__MASK 0x20000000L
-#define RCC_DEV1_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV1_F2__MASK 0x40000000L
-#define RCC_DEV1_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV1_F2__MASK 0x80000000L
-//RCC_DEV1_EPF2_STRAP2
-#define RCC_DEV1_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F2__MASK 0x00000080L
-#define RCC_DEV1_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F2__MASK 0x00000100L
-#define RCC_DEV1_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F2__MASK 0x00004000L
-#define RCC_DEV1_EPF2_STRAP2__STRAP_AER_EN_DEV1_F2__MASK 0x00010000L
-#define RCC_DEV1_EPF2_STRAP2__STRAP_ACS_EN_DEV1_F2__MASK 0x00020000L
-#define RCC_DEV1_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F2__MASK 0x00100000L
-#define RCC_DEV1_EPF2_STRAP2__STRAP_DPA_EN_DEV1_F2__MASK 0x00200000L
-#define RCC_DEV1_EPF2_STRAP2__STRAP_VC_EN_DEV1_F2__MASK 0x00800000L
-#define RCC_DEV1_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F2__MASK 0x07000000L
-//RCC_DEV1_EPF2_STRAP3
-#define RCC_DEV1_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F2__MASK 0x00000001L
-#define RCC_DEV1_EPF2_STRAP3__STRAP_PWR_EN_DEV1_F2__MASK 0x00000002L
-#define RCC_DEV1_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV1_F2__MASK 0x0003FFFCL
-#define RCC_DEV1_EPF2_STRAP3__STRAP_MSI_EN_DEV1_F2__MASK 0x00040000L
-#define RCC_DEV1_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F2__MASK 0x00080000L
-#define RCC_DEV1_EPF2_STRAP3__STRAP_MSIX_EN_DEV1_F2__MASK 0x00100000L
-#define RCC_DEV1_EPF2_STRAP3__STRAP_PMC_DSI_DEV1_F2__MASK 0x01000000L
-#define RCC_DEV1_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F2__MASK 0x02000000L
-#define RCC_DEV1_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F2__MASK 0x04000000L
-#define RCC_DEV1_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F2__MASK 0x08000000L
-//RCC_DEV1_EPF2_STRAP4
-#define RCC_DEV1_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F2__MASK 0x00100000L
-#define RCC_DEV1_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV1_F2__MASK 0x00200000L
-#define RCC_DEV1_EPF2_STRAP4__STRAP_FLR_EN_DEV1_F2__MASK 0x00400000L
-#define RCC_DEV1_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV1_F2__MASK 0x0F800000L
-#define RCC_DEV1_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F2__MASK 0x70000000L
-#define RCC_DEV1_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F2__MASK 0x80000000L
-//RCC_DEV1_EPF2_STRAP5
-#define RCC_DEV1_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F2__MASK 0x0000FFFFL
-//RCC_DEV1_EPF2_STRAP6
-#define RCC_DEV1_EPF2_STRAP6__STRAP_APER0_EN_DEV1_F2__MASK 0x00000001L
-#define RCC_DEV1_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F2__MASK 0x00000002L
-#define RCC_DEV1_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F2__MASK 0x00000070L
-#define RCC_DEV1_EPF2_STRAP6__STRAP_APER1_EN_DEV1_F2__MASK 0x00000100L
-#define RCC_DEV1_EPF2_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV1_F2__MASK 0x00000200L
-#define RCC_DEV1_EPF2_STRAP6__STRAP_APER2_EN_DEV1_F2__MASK 0x00010000L
-#define RCC_DEV1_EPF2_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV1_F2__MASK 0x00020000L
-#define RCC_DEV1_EPF2_STRAP6__STRAP_APER3_EN_DEV1_F2__MASK 0x01000000L
-#define RCC_DEV1_EPF2_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV1_F2__MASK 0x02000000L
-//RCC_DEV1_EPF2_STRAP13
-#define RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F2__MASK 0x000000FFL
-#define RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F2__MASK 0x0000FF00L
-#define RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F2__MASK 0x00FF0000L
-
-
-// addressBlock: bif_rst_bif_rst_regblk
-//HARD_RST_CTRL
-#define HARD_RST_CTRL__DSPT_CFG_RST_EN__MASK 0x00000001L
-#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__MASK 0x00000002L
-#define HARD_RST_CTRL__DSPT_PRV_RST_EN__MASK 0x00000004L
-#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__MASK 0x00000008L
-#define HARD_RST_CTRL__EP_CFG_RST_EN__MASK 0x00000010L
-#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__MASK 0x00000020L
-#define HARD_RST_CTRL__EP_PRV_RST_EN__MASK 0x00000040L
-#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__MASK 0x00000080L
-#define HARD_RST_CTRL__SWUS_SHADOW_RST_EN__MASK 0x10000000L
-#define HARD_RST_CTRL__CORE_STICKY_RST_EN__MASK 0x20000000L
-#define HARD_RST_CTRL__RELOAD_STRAP_EN__MASK 0x40000000L
-#define HARD_RST_CTRL__CORE_RST_EN__MASK 0x80000000L
-//RSMU_SOFT_RST_CTRL
-#define RSMU_SOFT_RST_CTRL__DSPT_CFG_RST_EN__MASK 0x00000001L
-#define RSMU_SOFT_RST_CTRL__DSPT_CFG_STICKY_RST_EN__MASK 0x00000002L
-#define RSMU_SOFT_RST_CTRL__DSPT_PRV_RST_EN__MASK 0x00000004L
-#define RSMU_SOFT_RST_CTRL__DSPT_PRV_STICKY_RST_EN__MASK 0x00000008L
-#define RSMU_SOFT_RST_CTRL__EP_CFG_RST_EN__MASK 0x00000010L
-#define RSMU_SOFT_RST_CTRL__EP_CFG_STICKY_RST_EN__MASK 0x00000020L
-#define RSMU_SOFT_RST_CTRL__EP_PRV_RST_EN__MASK 0x00000040L
-#define RSMU_SOFT_RST_CTRL__EP_PRV_STICKY_RST_EN__MASK 0x00000080L
-#define RSMU_SOFT_RST_CTRL__SWUS_SHADOW_RST_EN__MASK 0x10000000L
-#define RSMU_SOFT_RST_CTRL__CORE_STICKY_RST_EN__MASK 0x20000000L
-#define RSMU_SOFT_RST_CTRL__RELOAD_STRAP_EN__MASK 0x40000000L
-#define RSMU_SOFT_RST_CTRL__CORE_RST_EN__MASK 0x80000000L
-//SELF_SOFT_RST
-#define SELF_SOFT_RST__DSPT0_CFG_RST__MASK 0x00000001L
-#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST__MASK 0x00000002L
-#define SELF_SOFT_RST__DSPT0_PRV_RST__MASK 0x00000004L
-#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST__MASK 0x00000008L
-#define SELF_SOFT_RST__EP0_CFG_RST__MASK 0x00000010L
-#define SELF_SOFT_RST__EP0_CFG_STICKY_RST__MASK 0x00000020L
-#define SELF_SOFT_RST__EP0_PRV_RST__MASK 0x00000040L
-#define SELF_SOFT_RST__EP0_PRV_STICKY_RST__MASK 0x00000080L
-#define SELF_SOFT_RST__SDP_PORT_RST__MASK 0x08000000L
-#define SELF_SOFT_RST__SWUS_SHADOW_RST__MASK 0x10000000L
-#define SELF_SOFT_RST__CORE_STICKY_RST__MASK 0x20000000L
-#define SELF_SOFT_RST__RELOAD_STRAP__MASK 0x40000000L
-#define SELF_SOFT_RST__CORE_RST__MASK 0x80000000L
-//GFX_DRV_MODE1_RST_CTRL
-#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_RST__MASK 0x00000001L
-#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_FLR_EXC_RST__MASK 0x00000002L
-#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_STICKY_RST__MASK 0x00000004L
-#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_PRV_RST__MASK 0x00000008L
-#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_PRV_STICKY_RST__MASK 0x00000010L
-#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_CFG_RST__MASK 0x00000020L
-#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_CFG_STICKY_RST__MASK 0x00000040L
-#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_PRV_RST__MASK 0x00000080L
-//BIF_RST_MISC_CTRL
-#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__MASK 0x00000001L
-#define BIF_RST_MISC_CTRL__DRV_RST_MODE__MASK 0x0000000CL
-#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__MASK 0x00000010L
-#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__MASK 0x00000020L
-#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__MASK 0x00000040L
-#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN__MASK 0x00000100L
-#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__MASK 0x00000200L
-#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__MASK 0x00001C00L
-#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__MASK 0x00006000L
-#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__MASK 0x00018000L
-#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__MASK 0x00060000L
-#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__MASK 0x00800000L
-#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__MASK 0x03000000L
-//BIF_RST_MISC_CTRL2
-#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__MASK 0x00010000L
-#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__MASK 0x00020000L
-#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__MASK 0x00040000L
-#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__MASK 0x80000000L
-//BIF_RST_MISC_CTRL3
-#define BIF_RST_MISC_CTRL3__TIMER_SCALE__MASK 0x0000000FL
-#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__MASK 0x00000030L
-#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__MASK 0x00000040L
-#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD__MASK 0x00000380L
-#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT__MASK 0x00001C00L
-#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF__MASK 0x0000E000L
-//BIF_RST_GFXVF_FLR_IDLE
-#define BIF_RST_GFXVF_FLR_IDLE__VF0_TRANS_IDLE__MASK 0x00000001L
-#define BIF_RST_GFXVF_FLR_IDLE__VF1_TRANS_IDLE__MASK 0x00000002L
-#define BIF_RST_GFXVF_FLR_IDLE__VF2_TRANS_IDLE__MASK 0x00000004L
-#define BIF_RST_GFXVF_FLR_IDLE__VF3_TRANS_IDLE__MASK 0x00000008L
-#define BIF_RST_GFXVF_FLR_IDLE__VF4_TRANS_IDLE__MASK 0x00000010L
-#define BIF_RST_GFXVF_FLR_IDLE__VF5_TRANS_IDLE__MASK 0x00000020L
-#define BIF_RST_GFXVF_FLR_IDLE__VF6_TRANS_IDLE__MASK 0x00000040L
-#define BIF_RST_GFXVF_FLR_IDLE__VF7_TRANS_IDLE__MASK 0x00000080L
-#define BIF_RST_GFXVF_FLR_IDLE__VF8_TRANS_IDLE__MASK 0x00000100L
-#define BIF_RST_GFXVF_FLR_IDLE__VF9_TRANS_IDLE__MASK 0x00000200L
-#define BIF_RST_GFXVF_FLR_IDLE__VF10_TRANS_IDLE__MASK 0x00000400L
-#define BIF_RST_GFXVF_FLR_IDLE__VF11_TRANS_IDLE__MASK 0x00000800L
-#define BIF_RST_GFXVF_FLR_IDLE__VF12_TRANS_IDLE__MASK 0x00001000L
-#define BIF_RST_GFXVF_FLR_IDLE__VF13_TRANS_IDLE__MASK 0x00002000L
-#define BIF_RST_GFXVF_FLR_IDLE__VF14_TRANS_IDLE__MASK 0x00004000L
-#define BIF_RST_GFXVF_FLR_IDLE__VF15_TRANS_IDLE__MASK 0x00008000L
-#define BIF_RST_GFXVF_FLR_IDLE__SOFTPF_TRANS_IDLE__MASK 0x80000000L
-//DEV0_PF0_FLR_RST_CTRL
-#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L
-#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L
-#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L
-#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L
-#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L
-#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN__MASK 0x00000020L
-#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN__MASK 0x00000040L
-#define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN__MASK 0x00000080L
-#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN__MASK 0x00000100L
-#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__MASK 0x00000200L
-#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__MASK 0x00000400L
-#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN__MASK 0x00000800L
-#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__MASK 0x00001000L
-#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN__MASK 0x00002000L
-#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN__MASK 0x00004000L
-#define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN__MASK 0x00008000L
-#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN__MASK 0x00010000L
-#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L
-#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L
-#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L
-#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L
-//DEV0_PF1_FLR_RST_CTRL
-#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L
-#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L
-#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L
-#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L
-#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L
-#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L
-#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L
-#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L
-#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L
-//DEV0_PF2_FLR_RST_CTRL
-#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L
-#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L
-#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L
-#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L
-#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L
-#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L
-#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L
-#define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L
-#define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L
-//DEV0_PF3_FLR_RST_CTRL
-#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L
-#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L
-#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L
-#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L
-#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L
-#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L
-#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L
-#define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L
-#define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L
-//DEV0_PF4_FLR_RST_CTRL
-#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L
-#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L
-#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L
-#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L
-#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L
-#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L
-#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L
-#define DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L
-#define DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L
-//DEV0_PF5_FLR_RST_CTRL
-#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L
-#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L
-#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L
-#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L
-#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L
-#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L
-#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L
-#define DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L
-#define DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L
-//DEV0_PF6_FLR_RST_CTRL
-#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L
-#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L
-#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L
-#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L
-#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L
-#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L
-#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L
-#define DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L
-#define DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L
-//DEV0_PF7_FLR_RST_CTRL
-#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L
-#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L
-#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L
-#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L
-#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L
-#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L
-#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L
-#define DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L
-#define DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L
-//BIF_INST_RESET_INTR_STS
-#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__MASK 0x00000001L
-#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__MASK 0x00000002L
-#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__MASK 0x00000004L
-#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__MASK 0x00000008L
-#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__MASK 0x00000010L
-//BIF_PF_FLR_INTR_STS
-#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__MASK 0x00000001L
-#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__MASK 0x00000002L
-#define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS__MASK 0x00000004L
-#define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS__MASK 0x00000008L
-#define BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS__MASK 0x00000010L
-#define BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS__MASK 0x00000020L
-#define BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS__MASK 0x00000040L
-#define BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS__MASK 0x00000080L
-//BIF_D3HOTD0_INTR_STS
-#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__MASK 0x00000001L
-#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__MASK 0x00000002L
-#define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS__MASK 0x00000004L
-#define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS__MASK 0x00000008L
-#define BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS__MASK 0x00000010L
-#define BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS__MASK 0x00000020L
-#define BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS__MASK 0x00000040L
-#define BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS__MASK 0x00000080L
-//BIF_POWER_INTR_STS
-#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__MASK 0x00000001L
-#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__MASK 0x00010000L
-//BIF_PF_DSTATE_INTR_STS
-#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__MASK 0x00000001L
-#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__MASK 0x00000002L
-#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__MASK 0x00000004L
-#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__MASK 0x00000008L
-#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__MASK 0x00000010L
-#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__MASK 0x00000020L
-#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__MASK 0x00000040L
-#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__MASK 0x00000080L
-//BIF_PF0_VF_FLR_INTR_STS
-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF0_FLR_INTR_STS__MASK 0x00000001L
-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF1_FLR_INTR_STS__MASK 0x00000002L
-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF2_FLR_INTR_STS__MASK 0x00000004L
-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF3_FLR_INTR_STS__MASK 0x00000008L
-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF4_FLR_INTR_STS__MASK 0x00000010L
-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF5_FLR_INTR_STS__MASK 0x00000020L
-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF6_FLR_INTR_STS__MASK 0x00000040L
-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF7_FLR_INTR_STS__MASK 0x00000080L
-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF8_FLR_INTR_STS__MASK 0x00000100L
-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF9_FLR_INTR_STS__MASK 0x00000200L
-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF10_FLR_INTR_STS__MASK 0x00000400L
-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF11_FLR_INTR_STS__MASK 0x00000800L
-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF12_FLR_INTR_STS__MASK 0x00001000L
-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF13_FLR_INTR_STS__MASK 0x00002000L
-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF14_FLR_INTR_STS__MASK 0x00004000L
-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF15_FLR_INTR_STS__MASK 0x00008000L
-#define BIF_PF0_VF_FLR_INTR_STS__PF0_SOFTPF_FLR_INTR_STS__MASK 0x80000000L
-//BIF_INST_RESET_INTR_MASK
-#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__MASK 0x00000001L
-#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__MASK 0x00000002L
-#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__MASK 0x00000004L
-#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__MASK 0x00000008L
-#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__MASK 0x00000010L
-//BIF_PF_FLR_INTR_MASK
-#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__MASK 0x00000001L
-#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__MASK 0x00000002L
-#define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK__MASK 0x00000004L
-#define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK__MASK 0x00000008L
-#define BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK__MASK 0x00000010L
-#define BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK__MASK 0x00000020L
-#define BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK__MASK 0x00000040L
-#define BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK__MASK 0x00000080L
-//BIF_D3HOTD0_INTR_MASK
-#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__MASK 0x00000001L
-#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__MASK 0x00000002L
-#define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK__MASK 0x00000004L
-#define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK__MASK 0x00000008L
-#define BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK__MASK 0x00000010L
-#define BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK__MASK 0x00000020L
-#define BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK__MASK 0x00000040L
-#define BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK__MASK 0x00000080L
-//BIF_POWER_INTR_MASK
-#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__MASK 0x00000001L
-#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__MASK 0x00010000L
-//BIF_PF_DSTATE_INTR_MASK
-#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__MASK 0x00000001L
-#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__MASK 0x00000002L
-#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__MASK 0x00000004L
-#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__MASK 0x00000008L
-#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__MASK 0x00000010L
-#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__MASK 0x00000020L
-#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__MASK 0x00000040L
-#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__MASK 0x00000080L
-//BIF_PF0_VF_FLR_INTR_MASK
-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF0_FLR_INTR_MASK__MASK 0x00000001L
-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF1_FLR_INTR_MASK__MASK 0x00000002L
-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF2_FLR_INTR_MASK__MASK 0x00000004L
-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF3_FLR_INTR_MASK__MASK 0x00000008L
-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF4_FLR_INTR_MASK__MASK 0x00000010L
-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF5_FLR_INTR_MASK__MASK 0x00000020L
-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF6_FLR_INTR_MASK__MASK 0x00000040L
-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF7_FLR_INTR_MASK__MASK 0x00000080L
-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF8_FLR_INTR_MASK__MASK 0x00000100L
-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF9_FLR_INTR_MASK__MASK 0x00000200L
-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF10_FLR_INTR_MASK__MASK 0x00000400L
-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF11_FLR_INTR_MASK__MASK 0x00000800L
-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF12_FLR_INTR_MASK__MASK 0x00001000L
-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF13_FLR_INTR_MASK__MASK 0x00002000L
-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF14_FLR_INTR_MASK__MASK 0x00004000L
-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF15_FLR_INTR_MASK__MASK 0x00008000L
-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_SOFTPF_FLR_INTR_MASK__MASK 0x80000000L
-//BIF_PF_FLR_RST
-#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__MASK 0x00000001L
-#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__MASK 0x00000002L
-#define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST__MASK 0x00000004L
-#define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST__MASK 0x00000008L
-#define BIF_PF_FLR_RST__DEV0_PF4_FLR_RST__MASK 0x00000010L
-#define BIF_PF_FLR_RST__DEV0_PF5_FLR_RST__MASK 0x00000020L
-#define BIF_PF_FLR_RST__DEV0_PF6_FLR_RST__MASK 0x00000040L
-#define BIF_PF_FLR_RST__DEV0_PF7_FLR_RST__MASK 0x00000080L
-//BIF_PF0_VF_FLR_RST
-#define BIF_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__MASK 0x00000001L
-#define BIF_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__MASK 0x00000002L
-#define BIF_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__MASK 0x00000004L
-#define BIF_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__MASK 0x00000008L
-#define BIF_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__MASK 0x00000010L
-#define BIF_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__MASK 0x00000020L
-#define BIF_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__MASK 0x00000040L
-#define BIF_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__MASK 0x00000080L
-#define BIF_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__MASK 0x00000100L
-#define BIF_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__MASK 0x00000200L
-#define BIF_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__MASK 0x00000400L
-#define BIF_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__MASK 0x00000800L
-#define BIF_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__MASK 0x00001000L
-#define BIF_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__MASK 0x00002000L
-#define BIF_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__MASK 0x00004000L
-#define BIF_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__MASK 0x00008000L
-#define BIF_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__MASK 0x80000000L
-//BIF_DEV0_PF0_DSTATE_VALUE
-#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__MASK 0x00000003L
-#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L
-#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__MASK 0x00030000L
-//BIF_DEV0_PF1_DSTATE_VALUE
-#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__MASK 0x00000003L
-#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L
-#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__MASK 0x00030000L
-//BIF_DEV0_PF2_DSTATE_VALUE
-#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE__MASK 0x00000003L
-#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L
-#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE__MASK 0x00030000L
-//BIF_DEV0_PF3_DSTATE_VALUE
-#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE__MASK 0x00000003L
-#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L
-#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE__MASK 0x00030000L
-//BIF_DEV0_PF4_DSTATE_VALUE
-#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE__MASK 0x00000003L
-#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L
-#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE__MASK 0x00030000L
-//BIF_DEV0_PF5_DSTATE_VALUE
-#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE__MASK 0x00000003L
-#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L
-#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE__MASK 0x00030000L
-//BIF_DEV0_PF6_DSTATE_VALUE
-#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE__MASK 0x00000003L
-#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L
-#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE__MASK 0x00030000L
-//BIF_DEV0_PF7_DSTATE_VALUE
-#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE__MASK 0x00000003L
-#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L
-#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE__MASK 0x00030000L
-//DEV0_PF0_D3HOTD0_RST_CTRL
-#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L
-#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L
-#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L
-#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L
-#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L
-//DEV0_PF1_D3HOTD0_RST_CTRL
-#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L
-#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L
-#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L
-#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L
-#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L
-//DEV0_PF2_D3HOTD0_RST_CTRL
-#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L
-#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L
-#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L
-#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L
-#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L
-//DEV0_PF3_D3HOTD0_RST_CTRL
-#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L
-#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L
-#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L
-#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L
-#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L
-//DEV0_PF4_D3HOTD0_RST_CTRL
-#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L
-#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L
-#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L
-#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L
-#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L
-//DEV0_PF5_D3HOTD0_RST_CTRL
-#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L
-#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L
-#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L
-#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L
-#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L
-//DEV0_PF6_D3HOTD0_RST_CTRL
-#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L
-#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L
-#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L
-#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L
-#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L
-//DEV0_PF7_D3HOTD0_RST_CTRL
-#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L
-#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L
-#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L
-#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L
-#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L
-//BIF_PORT0_DSTATE_VALUE
-#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__MASK 0x00000003L
-#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__MASK 0x00030000L
-
-
-// addressBlock: bif_misc_bif_misc_regblk
-//MISC_SCRATCH
-#define MISC_SCRATCH__MISC_SCRATCH0__MASK 0xFFFFFFFFL
-//INTR_LINE_POLARITY
-#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__MASK 0x000000FFL
-//INTR_LINE_ENABLE
-#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__MASK 0x000000FFL
-//OUTSTANDING_VC_ALLOC
-#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__MASK 0x00000003L
-#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__MASK 0x0000000CL
-#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__MASK 0x00000030L
-#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__MASK 0x000000C0L
-#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__MASK 0x00000300L
-#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__MASK 0x00000C00L
-#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__MASK 0x00003000L
-#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__MASK 0x0000C000L
-#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__MASK 0x000F0000L
-#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__MASK 0x03000000L
-#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__MASK 0x0C000000L
-#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__MASK 0xF0000000L
-//BIFC_MISC_CTRL0
-#define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN__MASK 0x00000001L
-#define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN__MASK 0x00000006L
-#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__MASK 0x00000100L
-#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK__MASK 0x00000200L
-#define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK__MASK 0x00000400L
-#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__MASK 0x00010000L
-#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__MASK 0x00020000L
-#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__MASK 0x01000000L
-#define BIFC_MISC_CTRL0__VC7_DMA_IOCFG_DIS__MASK 0x02000000L
-#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__MASK 0x04000000L
-#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__MASK 0x08000000L
-#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE__MASK 0x10000000L
-#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION__MASK 0x80000000L
-//BIFC_MISC_CTRL1
-#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__MASK 0x00000001L
-#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__MASK 0x00000002L
-#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__MASK 0x00000004L
-#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__MASK 0x00000008L
-#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__MASK 0x00000010L
-#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__MASK 0x00000020L
-#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__MASK 0x00000040L
-#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__MASK 0x00000080L
-#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__MASK 0x00000300L
-#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__MASK 0x00000C00L
-#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__MASK 0x00001000L
-#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__MASK 0x00002000L
-#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__MASK 0x00004000L
-#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__MASK 0x00008000L
-#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__MASK 0x00010000L
-#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__MASK 0x00020000L
-#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__MASK 0x00040000L
-#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__MASK 0x00080000L
-//BIFC_BME_ERR_LOG
-#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F0__MASK 0x00000001L
-#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F1__MASK 0x00000002L
-#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F2__MASK 0x00000004L
-#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F3__MASK 0x00000008L
-#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F4__MASK 0x00000010L
-#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F5__MASK 0x00000020L
-#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F6__MASK 0x00000040L
-#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F7__MASK 0x00000080L
-#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F0__MASK 0x00010000L
-#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F1__MASK 0x00020000L
-#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F2__MASK 0x00040000L
-#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F3__MASK 0x00080000L
-#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F4__MASK 0x00100000L
-#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F5__MASK 0x00200000L
-#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F6__MASK 0x00400000L
-#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F7__MASK 0x00800000L
-//BIFC_RCCBIH_BME_ERR_LOG
-#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F0__MASK 0x00000001L
-#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F1__MASK 0x00000002L
-#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F2__MASK 0x00000004L
-#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F3__MASK 0x00000008L
-#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F4__MASK 0x00000010L
-#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F5__MASK 0x00000020L
-#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F6__MASK 0x00000040L
-#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F7__MASK 0x00000080L
-#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__MASK 0x00010000L
-#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__MASK 0x00020000L
-#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2__MASK 0x00040000L
-#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3__MASK 0x00080000L
-#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4__MASK 0x00100000L
-#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5__MASK 0x00200000L
-#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6__MASK 0x00400000L
-#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7__MASK 0x00800000L
-//BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__MASK 0x00000003L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__MASK 0x0000000CL
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__MASK 0x000000C0L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__MASK 0x00000300L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__MASK 0x00000C00L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__MASK 0x00003000L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__MASK 0x00030000L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__MASK 0x000C0000L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__MASK 0x00C00000L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__MASK 0x03000000L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__MASK 0x0C000000L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__MASK 0x30000000L
-//BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__MASK 0x00000003L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__MASK 0x0000000CL
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__MASK 0x000000C0L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__MASK 0x00000300L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__MASK 0x00000C00L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__MASK 0x00003000L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__MASK 0x00030000L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__MASK 0x000C0000L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__MASK 0x00C00000L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__MASK 0x03000000L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__MASK 0x0C000000L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__MASK 0x30000000L
-//BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__MASK 0x00000003L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__MASK 0x0000000CL
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__MASK 0x000000C0L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__MASK 0x00000300L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__MASK 0x00000C00L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__MASK 0x00003000L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__MASK 0x00030000L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__MASK 0x000C0000L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__MASK 0x00C00000L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__MASK 0x03000000L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__MASK 0x0C000000L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__MASK 0x30000000L
-//BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__MASK 0x00000003L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__MASK 0x0000000CL
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__MASK 0x000000C0L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__MASK 0x00000300L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__MASK 0x00000C00L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__MASK 0x00003000L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__MASK 0x00030000L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__MASK 0x000C0000L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__MASK 0x00C00000L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__MASK 0x03000000L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__MASK 0x0C000000L
-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__MASK 0x30000000L
-//NBIF_VWIRE_CTRL
-#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT__MASK 0x000000F0L
-#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED__MASK 0x00000100L
-#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT__MASK 0x00F00000L
-#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL__MASK 0x0C000000L
-//NBIF_SMN_VWR_VCHG_DIS_CTRL
-#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS__MASK 0x00000001L
-#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS__MASK 0x00000002L
-#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS__MASK 0x00000004L
-#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS__MASK 0x00000008L
-#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS__MASK 0x00000010L
-#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS__MASK 0x00000020L
-#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS__MASK 0x00000040L
-//NBIF_SMN_VWR_VCHG_RST_CTRL0
-#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV__MASK 0x00000001L
-#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV__MASK 0x00000002L
-#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV__MASK 0x00000004L
-#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV__MASK 0x00000008L
-#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV__MASK 0x00000010L
-#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV__MASK 0x00000020L
-#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV__MASK 0x00000040L
-//NBIF_SMN_VWR_VCHG_TRIG
-#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG__MASK 0x00000001L
-#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG__MASK 0x00000002L
-#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG__MASK 0x00000004L
-#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG__MASK 0x00000008L
-#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG__MASK 0x00000010L
-#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG__MASK 0x00000020L
-#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG__MASK 0x00000040L
-//NBIF_SMN_VWR_WTRIG_CNTL
-#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS__MASK 0x00000001L
-#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS__MASK 0x00000002L
-#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS__MASK 0x00000004L
-#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS__MASK 0x00000008L
-#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS__MASK 0x00000010L
-#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS__MASK 0x00000020L
-#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS__MASK 0x00000040L
-//NBIF_SMN_VWR_VCHG_DIS_CTRL_1
-#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV__MASK 0x00000001L
-#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV__MASK 0x00000002L
-#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV__MASK 0x00000004L
-#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV__MASK 0x00000008L
-#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV__MASK 0x00000010L
-#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV__MASK 0x00000020L
-#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV__MASK 0x00000040L
-//NBIF_MGCG_CTRL
-#define NBIF_MGCG_CTRL__NBIF_MGCG_EN__MASK 0x00000001L
-#define NBIF_MGCG_CTRL__NBIF_MGCG_MODE__MASK 0x00000002L
-#define NBIF_MGCG_CTRL__NBIF_MGCG_HYSTERESIS__MASK 0x000003FCL
-//NBIF_DS_CTRL_LCLK
-#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN__MASK 0x00000001L
-#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER__MASK 0xFFFF0000L
-//SMN_MST_CNTL0
-#define SMN_MST_CNTL0__SMN_ARB_MODE__MASK 0x00000003L
-#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS__MASK 0x00000100L
-#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS__MASK 0x00000200L
-#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS__MASK 0x00000400L
-#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS__MASK 0x00000800L
-#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0__MASK 0x00010000L
-#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0__MASK 0x00100000L
-#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0__MASK 0x01000000L
-#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0__MASK 0x10000000L
-//SMN_MST_EP_CNTL1
-#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0__MASK 0x00000001L
-#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1__MASK 0x00000002L
-#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2__MASK 0x00000004L
-#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3__MASK 0x00000008L
-#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4__MASK 0x00000010L
-#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5__MASK 0x00000020L
-#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6__MASK 0x00000040L
-#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7__MASK 0x00000080L
-//SMN_MST_EP_CNTL2
-#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0__MASK 0x00000001L
-#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1__MASK 0x00000002L
-#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2__MASK 0x00000004L
-#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3__MASK 0x00000008L
-#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4__MASK 0x00000010L
-#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5__MASK 0x00000020L
-#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6__MASK 0x00000040L
-#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7__MASK 0x00000080L
-//NBIF_SDP_VWR_VCHG_DIS_CTRL
-#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS__MASK 0x00000001L
-#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS__MASK 0x00000002L
-#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS__MASK 0x00000004L
-#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS__MASK 0x00000008L
-#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS__MASK 0x00000010L
-#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS__MASK 0x00000020L
-#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS__MASK 0x00000040L
-#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS__MASK 0x00000080L
-#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS__MASK 0x01000000L
-//NBIF_SDP_VWR_VCHG_RST_CTRL0
-#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN__MASK 0x00000001L
-#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN__MASK 0x00000002L
-#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN__MASK 0x00000004L
-#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN__MASK 0x00000008L
-#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN__MASK 0x00000010L
-#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN__MASK 0x00000020L
-#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN__MASK 0x00000040L
-#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN__MASK 0x00000080L
-#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN__MASK 0x01000000L
-//NBIF_SDP_VWR_VCHG_RST_CTRL1
-#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL__MASK 0x00000001L
-#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL__MASK 0x00000002L
-#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL__MASK 0x00000004L
-#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL__MASK 0x00000008L
-#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL__MASK 0x00000010L
-#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL__MASK 0x00000020L
-#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL__MASK 0x00000040L
-#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL__MASK 0x00000080L
-#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL__MASK 0x01000000L
-//NBIF_SDP_VWR_VCHG_TRIG
-#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG__MASK 0x00000001L
-#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG__MASK 0x00000002L
-#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG__MASK 0x00000004L
-#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG__MASK 0x00000008L
-#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG__MASK 0x00000010L
-#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG__MASK 0x00000020L
-#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG__MASK 0x00000040L
-#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG__MASK 0x00000080L
-#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG__MASK 0x01000000L
-//BME_DUMMY_CNTL_0
-#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__MASK 0x00000003L
-#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__MASK 0x0000000CL
-#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__MASK 0x00000030L
-#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__MASK 0x000000C0L
-#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__MASK 0x00000300L
-#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__MASK 0x00000C00L
-#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__MASK 0x00003000L
-#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__MASK 0x0000C000L
-//BIFC_THT_CNTL
-#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0__MASK 0x0000000FL
-#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0__MASK 0x000000F0L
-#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1__MASK 0x00000F00L
-//BIFC_HSTARB_CNTL
-#define BIFC_HSTARB_CNTL__SLVARB_MODE__MASK 0x00000003L
-//BIFC_GSI_CNTL
-#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__MASK 0x00000003L
-#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__MASK 0x0000001CL
-#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__MASK 0x00000020L
-#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__MASK 0x00000040L
-#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__MASK 0x00000080L
-#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__MASK 0x00000100L
-#define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN__MASK 0x00000200L
-#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__MASK 0x00000C00L
-#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__MASK 0x00003000L
-//BIFC_PCIEFUNC_CNTL
-#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__MASK 0x0000FFFFL
-#define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC__MASK 0x00010000L
-//BIFC_SDP_CNTL_0
-#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__MASK 0x0000003FL
-#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__MASK 0x00000FC0L
-#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__MASK 0x0003F000L
-#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__MASK 0x00FC0000L
-//BIFC_PERF_CNTL_0
-#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__MASK 0x00000001L
-#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__MASK 0x00000002L
-#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__MASK 0x00000100L
-#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__MASK 0x00000200L
-#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__MASK 0x001F0000L
-#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__MASK 0x1F000000L
-//BIFC_PERF_CNTL_1
-#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__MASK 0x00000001L
-#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__MASK 0x00000002L
-#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__MASK 0x00000100L
-#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__MASK 0x00000200L
-#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__MASK 0x003F0000L
-#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__MASK 0x7F000000L
-//BIFC_PERF_CNT_MMIO_RD
-#define BIFC_PERF_CNT_MMIO_RD__PERF_CNT_MMIO_RD_VALUE__MASK 0xFFFFFFFFL
-//BIFC_PERF_CNT_MMIO_WR
-#define BIFC_PERF_CNT_MMIO_WR__PERF_CNT_MMIO_WR_VALUE__MASK 0xFFFFFFFFL
-//BIFC_PERF_CNT_DMA_RD
-#define BIFC_PERF_CNT_DMA_RD__PERF_CNT_DMA_RD_VALUE__MASK 0xFFFFFFFFL
-//BIFC_PERF_CNT_DMA_WR
-#define BIFC_PERF_CNT_DMA_WR__PERF_CNT_DMA_WR_VALUE__MASK 0xFFFFFFFFL
-//NBIF_REGIF_ERRSET_CTRL
-#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS__MASK 0x00000001L
-//SMN_MST_EP_CNTL3
-#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0__MASK 0x00000001L
-#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1__MASK 0x00000002L
-#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2__MASK 0x00000004L
-#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3__MASK 0x00000008L
-#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4__MASK 0x00000010L
-#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5__MASK 0x00000020L
-#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6__MASK 0x00000040L
-#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7__MASK 0x00000080L
-//SMN_MST_EP_CNTL4
-#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0__MASK 0x00000001L
-#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1__MASK 0x00000002L
-#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2__MASK 0x00000004L
-#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3__MASK 0x00000008L
-#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4__MASK 0x00000010L
-#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5__MASK 0x00000020L
-#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6__MASK 0x00000040L
-#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7__MASK 0x00000080L
-//BIF_SELFRING_BUFFER_VID
-#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID__MASK 0x000000FFL
-#define BIF_SELFRING_BUFFER_VID__IOHUB_RAS_INTR_CID__MASK 0x0000FF00L
-//BIF_SELFRING_VECTOR_CNTL
-#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS__MASK 0x00000001L
-
-
-// addressBlock: bif_ras_bif_ras_regblk
-//BIF_RAS_LEAF0_CTRL
-#define BIF_RAS_LEAF0_CTRL__POISON_DET_EN__MASK 0x00000001L
-#define BIF_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L
-#define BIF_RAS_LEAF0_CTRL__POISON_STALL_EN__MASK 0x00000004L
-#define BIF_RAS_LEAF0_CTRL__PARITY_DET_EN__MASK 0x00000010L
-#define BIF_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L
-#define BIF_RAS_LEAF0_CTRL__PARITY_STALL_EN__MASK 0x00000040L
-#define BIF_RAS_LEAF0_CTRL__ERR_EVENT_RECV__MASK 0x00010000L
-#define BIF_RAS_LEAF0_CTRL__LINK_DIS_RECV__MASK 0x00020000L
-#define BIF_RAS_LEAF0_CTRL__POISON_ERR_DET__MASK 0x00040000L
-#define BIF_RAS_LEAF0_CTRL__PARITY_ERR_DET__MASK 0x00080000L
-#define BIF_RAS_LEAF0_CTRL__ERR_EVENT_SENT__MASK 0x00100000L
-#define BIF_RAS_LEAF0_CTRL__EGRESS_STALLED__MASK 0x00200000L
-//BIF_RAS_LEAF1_CTRL
-#define BIF_RAS_LEAF1_CTRL__POISON_DET_EN__MASK 0x00000001L
-#define BIF_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L
-#define BIF_RAS_LEAF1_CTRL__POISON_STALL_EN__MASK 0x00000004L
-#define BIF_RAS_LEAF1_CTRL__PARITY_DET_EN__MASK 0x00000010L
-#define BIF_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L
-#define BIF_RAS_LEAF1_CTRL__PARITY_STALL_EN__MASK 0x00000040L
-#define BIF_RAS_LEAF1_CTRL__ERR_EVENT_RECV__MASK 0x00010000L
-#define BIF_RAS_LEAF1_CTRL__LINK_DIS_RECV__MASK 0x00020000L
-#define BIF_RAS_LEAF1_CTRL__POISON_ERR_DET__MASK 0x00040000L
-#define BIF_RAS_LEAF1_CTRL__PARITY_ERR_DET__MASK 0x00080000L
-#define BIF_RAS_LEAF1_CTRL__ERR_EVENT_SENT__MASK 0x00100000L
-#define BIF_RAS_LEAF1_CTRL__EGRESS_STALLED__MASK 0x00200000L
-//BIF_RAS_LEAF2_CTRL
-#define BIF_RAS_LEAF2_CTRL__POISON_DET_EN__MASK 0x00000001L
-#define BIF_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L
-#define BIF_RAS_LEAF2_CTRL__POISON_STALL_EN__MASK 0x00000004L
-#define BIF_RAS_LEAF2_CTRL__PARITY_DET_EN__MASK 0x00000010L
-#define BIF_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L
-#define BIF_RAS_LEAF2_CTRL__PARITY_STALL_EN__MASK 0x00000040L
-#define BIF_RAS_LEAF2_CTRL__ERR_EVENT_RECV__MASK 0x00010000L
-#define BIF_RAS_LEAF2_CTRL__LINK_DIS_RECV__MASK 0x00020000L
-#define BIF_RAS_LEAF2_CTRL__POISON_ERR_DET__MASK 0x00040000L
-#define BIF_RAS_LEAF2_CTRL__PARITY_ERR_DET__MASK 0x00080000L
-#define BIF_RAS_LEAF2_CTRL__ERR_EVENT_SENT__MASK 0x00100000L
-#define BIF_RAS_LEAF2_CTRL__EGRESS_STALLED__MASK 0x00200000L
-//BIF_RAS_MISC_CTRL
-#define BIF_RAS_MISC_CTRL__LINKDIS_TRIG_ERREVENT_EN__MASK 0x00000001L
-//BIF_IOHUB_RAS_IH_CNTL
-#define BIF_IOHUB_RAS_IH_CNTL__RAS_IH_INTR_EN__MASK 0x00000001L
-//BIF_RAS_VWR_FROM_IOHUB
-#define BIF_RAS_VWR_FROM_IOHUB__RAS_IH_INTR_TRIG__MASK 0x00000001L
-
-
-// addressBlock: rcc_pfc_amdgfx_RCCPFCDEC
-//RCC_PFC_LTR_CNTL
-#define RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__MASK 0x000003FFL
-#define RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__MASK 0x00001C00L
-#define RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__MASK 0x00008000L
-#define RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__MASK 0x03FF0000L
-#define RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__MASK 0x1C000000L
-#define RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__MASK 0x80000000L
-//RCC_PFC_PME_RESTORE
-#define RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__MASK 0x00000001L
-#define RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__MASK 0x00000100L
-//RCC_PFC_STICKY_RESTORE_0
-#define RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__MASK 0x00000001L
-#define RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__MASK 0x00000002L
-#define RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__MASK 0x00000004L
-#define RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__MASK 0x00000008L
-#define RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__MASK 0x00000010L
-#define RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__MASK 0x00000020L
-#define RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__MASK 0x00000040L
-#define RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__MASK 0x00000080L
-//RCC_PFC_STICKY_RESTORE_1
-#define RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__MASK 0xFFFFFFFFL
-//RCC_PFC_STICKY_RESTORE_2
-#define RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__MASK 0xFFFFFFFFL
-//RCC_PFC_STICKY_RESTORE_3
-#define RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__MASK 0xFFFFFFFFL
-//RCC_PFC_STICKY_RESTORE_4
-#define RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__MASK 0xFFFFFFFFL
-//RCC_PFC_STICKY_RESTORE_5
-#define RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__MASK 0xFFFFFFFFL
-//RCC_PFC_AUXPWR_CNTL
-#define RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__MASK 0x00000007L
-#define RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__MASK 0x00000008L
-
-
-// addressBlock: rcc_pfc_amdgfxaz_RCCPFCDEC
-//RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL
-#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__MASK 0x000003FFL
-#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__MASK 0x00001C00L
-#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__MASK 0x00008000L
-#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__MASK 0x03FF0000L
-#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__MASK 0x1C000000L
-#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__MASK 0x80000000L
-//RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE
-#define RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__MASK 0x00000001L
-#define RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__MASK 0x00000100L
-//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0
-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__MASK 0x00000001L
-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__MASK 0x00000002L
-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__MASK 0x00000004L
-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__MASK 0x00000008L
-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__MASK 0x00000010L
-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__MASK 0x00000020L
-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__MASK 0x00000040L
-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__MASK 0x00000080L
-//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1
-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__MASK 0xFFFFFFFFL
-//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2
-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__MASK 0xFFFFFFFFL
-//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3
-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__MASK 0xFFFFFFFFL
-//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4
-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__MASK 0xFFFFFFFFL
-//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5
-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__MASK 0xFFFFFFFFL
-//RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL
-#define RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__MASK 0x00000007L
-#define RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__MASK 0x00000008L
-
-
-// addressBlock: pciemsix_amdgfx_MSIXTDEC
-//PCIEMSIX_VECT0_ADDR_LO
-#define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
-//PCIEMSIX_VECT0_ADDR_HI
-#define PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT0_MSG_DATA
-#define PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT0_CONTROL
-#define PCIEMSIX_VECT0_CONTROL__MASK_BIT__MASK 0x00000001L
-//PCIEMSIX_VECT1_ADDR_LO
-#define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
-//PCIEMSIX_VECT1_ADDR_HI
-#define PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT1_MSG_DATA
-#define PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT1_CONTROL
-#define PCIEMSIX_VECT1_CONTROL__MASK_BIT__MASK 0x00000001L
-//PCIEMSIX_VECT2_ADDR_LO
-#define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
-//PCIEMSIX_VECT2_ADDR_HI
-#define PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT2_MSG_DATA
-#define PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT2_CONTROL
-#define PCIEMSIX_VECT2_CONTROL__MASK_BIT__MASK 0x00000001L
-//PCIEMSIX_VECT3_ADDR_LO
-#define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
-//PCIEMSIX_VECT3_ADDR_HI
-#define PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT3_MSG_DATA
-#define PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT3_CONTROL
-#define PCIEMSIX_VECT3_CONTROL__MASK_BIT__MASK 0x00000001L
-//PCIEMSIX_VECT4_ADDR_LO
-#define PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
-//PCIEMSIX_VECT4_ADDR_HI
-#define PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT4_MSG_DATA
-#define PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT4_CONTROL
-#define PCIEMSIX_VECT4_CONTROL__MASK_BIT__MASK 0x00000001L
-//PCIEMSIX_VECT5_ADDR_LO
-#define PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
-//PCIEMSIX_VECT5_ADDR_HI
-#define PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT5_MSG_DATA
-#define PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT5_CONTROL
-#define PCIEMSIX_VECT5_CONTROL__MASK_BIT__MASK 0x00000001L
-//PCIEMSIX_VECT6_ADDR_LO
-#define PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
-//PCIEMSIX_VECT6_ADDR_HI
-#define PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT6_MSG_DATA
-#define PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT6_CONTROL
-#define PCIEMSIX_VECT6_CONTROL__MASK_BIT__MASK 0x00000001L
-//PCIEMSIX_VECT7_ADDR_LO
-#define PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
-//PCIEMSIX_VECT7_ADDR_HI
-#define PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT7_MSG_DATA
-#define PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT7_CONTROL
-#define PCIEMSIX_VECT7_CONTROL__MASK_BIT__MASK 0x00000001L
-//PCIEMSIX_VECT8_ADDR_LO
-#define PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
-//PCIEMSIX_VECT8_ADDR_HI
-#define PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT8_MSG_DATA
-#define PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT8_CONTROL
-#define PCIEMSIX_VECT8_CONTROL__MASK_BIT__MASK 0x00000001L
-//PCIEMSIX_VECT9_ADDR_LO
-#define PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
-//PCIEMSIX_VECT9_ADDR_HI
-#define PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT9_MSG_DATA
-#define PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT9_CONTROL
-#define PCIEMSIX_VECT9_CONTROL__MASK_BIT__MASK 0x00000001L
-//PCIEMSIX_VECT10_ADDR_LO
-#define PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
-//PCIEMSIX_VECT10_ADDR_HI
-#define PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT10_MSG_DATA
-#define PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT10_CONTROL
-#define PCIEMSIX_VECT10_CONTROL__MASK_BIT__MASK 0x00000001L
-//PCIEMSIX_VECT11_ADDR_LO
-#define PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
-//PCIEMSIX_VECT11_ADDR_HI
-#define PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT11_MSG_DATA
-#define PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT11_CONTROL
-#define PCIEMSIX_VECT11_CONTROL__MASK_BIT__MASK 0x00000001L
-//PCIEMSIX_VECT12_ADDR_LO
-#define PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
-//PCIEMSIX_VECT12_ADDR_HI
-#define PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT12_MSG_DATA
-#define PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT12_CONTROL
-#define PCIEMSIX_VECT12_CONTROL__MASK_BIT__MASK 0x00000001L
-//PCIEMSIX_VECT13_ADDR_LO
-#define PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
-//PCIEMSIX_VECT13_ADDR_HI
-#define PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT13_MSG_DATA
-#define PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT13_CONTROL
-#define PCIEMSIX_VECT13_CONTROL__MASK_BIT__MASK 0x00000001L
-//PCIEMSIX_VECT14_ADDR_LO
-#define PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
-//PCIEMSIX_VECT14_ADDR_HI
-#define PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT14_MSG_DATA
-#define PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT14_CONTROL
-#define PCIEMSIX_VECT14_CONTROL__MASK_BIT__MASK 0x00000001L
-//PCIEMSIX_VECT15_ADDR_LO
-#define PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
-//PCIEMSIX_VECT15_ADDR_HI
-#define PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT15_MSG_DATA
-#define PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT15_CONTROL
-#define PCIEMSIX_VECT15_CONTROL__MASK_BIT__MASK 0x00000001L
-//PCIEMSIX_VECT16_ADDR_LO
-#define PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
-//PCIEMSIX_VECT16_ADDR_HI
-#define PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT16_MSG_DATA
-#define PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT16_CONTROL
-#define PCIEMSIX_VECT16_CONTROL__MASK_BIT__MASK 0x00000001L
-//PCIEMSIX_VECT17_ADDR_LO
-#define PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
-//PCIEMSIX_VECT17_ADDR_HI
-#define PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT17_MSG_DATA
-#define PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT17_CONTROL
-#define PCIEMSIX_VECT17_CONTROL__MASK_BIT__MASK 0x00000001L
-//PCIEMSIX_VECT18_ADDR_LO
-#define PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
-//PCIEMSIX_VECT18_ADDR_HI
-#define PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT18_MSG_DATA
-#define PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT18_CONTROL
-#define PCIEMSIX_VECT18_CONTROL__MASK_BIT__MASK 0x00000001L
-//PCIEMSIX_VECT19_ADDR_LO
-#define PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
-//PCIEMSIX_VECT19_ADDR_HI
-#define PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT19_MSG_DATA
-#define PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT19_CONTROL
-#define PCIEMSIX_VECT19_CONTROL__MASK_BIT__MASK 0x00000001L
-//PCIEMSIX_VECT20_ADDR_LO
-#define PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
-//PCIEMSIX_VECT20_ADDR_HI
-#define PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT20_MSG_DATA
-#define PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT20_CONTROL
-#define PCIEMSIX_VECT20_CONTROL__MASK_BIT__MASK 0x00000001L
-//PCIEMSIX_VECT21_ADDR_LO
-#define PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
-//PCIEMSIX_VECT21_ADDR_HI
-#define PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT21_MSG_DATA
-#define PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT21_CONTROL
-#define PCIEMSIX_VECT21_CONTROL__MASK_BIT__MASK 0x00000001L
-//PCIEMSIX_VECT22_ADDR_LO
-#define PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
-//PCIEMSIX_VECT22_ADDR_HI
-#define PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT22_MSG_DATA
-#define PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT22_CONTROL
-#define PCIEMSIX_VECT22_CONTROL__MASK_BIT__MASK 0x00000001L
-//PCIEMSIX_VECT23_ADDR_LO
-#define PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
-//PCIEMSIX_VECT23_ADDR_HI
-#define PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT23_MSG_DATA
-#define PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT23_CONTROL
-#define PCIEMSIX_VECT23_CONTROL__MASK_BIT__MASK 0x00000001L
-//PCIEMSIX_VECT24_ADDR_LO
-#define PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
-//PCIEMSIX_VECT24_ADDR_HI
-#define PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT24_MSG_DATA
-#define PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT24_CONTROL
-#define PCIEMSIX_VECT24_CONTROL__MASK_BIT__MASK 0x00000001L
-//PCIEMSIX_VECT25_ADDR_LO
-#define PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
-//PCIEMSIX_VECT25_ADDR_HI
-#define PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT25_MSG_DATA
-#define PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT25_CONTROL
-#define PCIEMSIX_VECT25_CONTROL__MASK_BIT__MASK 0x00000001L
-//PCIEMSIX_VECT26_ADDR_LO
-#define PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
-//PCIEMSIX_VECT26_ADDR_HI
-#define PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT26_MSG_DATA
-#define PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT26_CONTROL
-#define PCIEMSIX_VECT26_CONTROL__MASK_BIT__MASK 0x00000001L
-//PCIEMSIX_VECT27_ADDR_LO
-#define PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
-//PCIEMSIX_VECT27_ADDR_HI
-#define PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT27_MSG_DATA
-#define PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT27_CONTROL
-#define PCIEMSIX_VECT27_CONTROL__MASK_BIT__MASK 0x00000001L
-//PCIEMSIX_VECT28_ADDR_LO
-#define PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
-//PCIEMSIX_VECT28_ADDR_HI
-#define PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT28_MSG_DATA
-#define PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT28_CONTROL
-#define PCIEMSIX_VECT28_CONTROL__MASK_BIT__MASK 0x00000001L
-//PCIEMSIX_VECT29_ADDR_LO
-#define PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
-//PCIEMSIX_VECT29_ADDR_HI
-#define PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT29_MSG_DATA
-#define PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT29_CONTROL
-#define PCIEMSIX_VECT29_CONTROL__MASK_BIT__MASK 0x00000001L
-//PCIEMSIX_VECT30_ADDR_LO
-#define PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
-//PCIEMSIX_VECT30_ADDR_HI
-#define PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT30_MSG_DATA
-#define PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT30_CONTROL
-#define PCIEMSIX_VECT30_CONTROL__MASK_BIT__MASK 0x00000001L
-//PCIEMSIX_VECT31_ADDR_LO
-#define PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL
-//PCIEMSIX_VECT31_ADDR_HI
-#define PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT31_MSG_DATA
-#define PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL
-//PCIEMSIX_VECT31_CONTROL
-#define PCIEMSIX_VECT31_CONTROL__MASK_BIT__MASK 0x00000001L
-
-
-// addressBlock: pciemsix_amdgfx_MSIXPDEC
-//PCIEMSIX_PBA
-#define PCIEMSIX_PBA__MSIX_PENDING_BITS__MASK 0xFFFFFFFFL
-
-
-// addressBlock: syshub_mmreg_ind_syshubind
-//SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000001L
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000002L
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000004L
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000008L
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000010L
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000020L
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000040L
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000080L
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00010000L
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00020000L
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00040000L
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00080000L
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00100000L
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00200000L
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00400000L
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00800000L
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x10000000L
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__MASK 0x80000000L
-//SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__MASK 0x0000FFFFL
-//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK
-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en__MASK 0x00000001L
-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en__MASK 0x00000002L
-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__MASK 0x00008000L
-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__MASK 0x00010000L
-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__MASK 0x00020000L
-//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK
-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en__MASK 0x00000001L
-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en__MASK 0x00000002L
-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__MASK 0x00008000L
-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__MASK 0x00010000L
-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__MASK 0x00020000L
-//SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L
-//SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL
-#define SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L
-#define SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL
-#define SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L
-//SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
-//SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
-//SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
-//SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
-//SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
-//SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
-//SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL
-#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
-#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
-#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
-#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
-#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
-#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
-//SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL
-#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
-#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
-#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
-#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
-#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
-#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
-//SYSHUBMMREGIND_SYSHUB_CG_CNTL
-#define SYSHUBMMREGIND_SYSHUB_CG_CNTL__SYSHUB_CG_EN__MASK 0x00000001L
-#define SYSHUBMMREGIND_SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER__MASK 0x0000FF00L
-#define SYSHUBMMREGIND_SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER__MASK 0x00FF0000L
-//SYSHUBMMREGIND_SYSHUB_TRANS_IDLE
-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0__MASK 0x00000001L
-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1__MASK 0x00000002L
-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2__MASK 0x00000004L
-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3__MASK 0x00000008L
-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4__MASK 0x00000010L
-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5__MASK 0x00000020L
-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6__MASK 0x00000040L
-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7__MASK 0x00000080L
-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8__MASK 0x00000100L
-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9__MASK 0x00000200L
-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10__MASK 0x00000400L
-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11__MASK 0x00000800L
-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12__MASK 0x00001000L
-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13__MASK 0x00002000L
-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14__MASK 0x00004000L
-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15__MASK 0x00008000L
-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF__MASK 0x00010000L
-//SYSHUBMMREGIND_SYSHUB_HP_TIMER
-#define SYSHUBMMREGIND_SYSHUB_HP_TIMER__SYSHUB_HP_TIMER__MASK 0xFFFFFFFFL
-//SYSHUBMMREGIND_SYSHUB_SCRATCH
-#define SYSHUBMMREGIND_SYSHUB_SCRATCH__SCRATCH__MASK 0xFFFFFFFFL
-//SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000001L
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000002L
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000004L
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000008L
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000010L
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000020L
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000040L
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000080L
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00010000L
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00020000L
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00040000L
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00080000L
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00100000L
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00200000L
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00400000L
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00800000L
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x10000000L
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN__MASK 0x80000000L
-//SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK
-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER__MASK 0x0000FFFFL
-//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK
-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en__MASK 0x00008000L
-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en__MASK 0x00010000L
-//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK
-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en__MASK 0x00008000L
-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en__MASK 0x00010000L
-//SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L
-//SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L
-//SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
-//SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
-//SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
-//SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
-//SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
-//SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
-//SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
-//SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
-//SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
-//SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L
-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_enum.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_enum.h
deleted file mode 100644
index 37adf0df0..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_enum.h
+++ /dev/null
@@ -1,1340 +0,0 @@
-/*
- * OSS_2_4 Register documentation
- *
- * Copyright (C) 2014 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef OSS_2_4_ENUM_H
-#define OSS_2_4_ENUM_H
-
-typedef enum IH_CLIENT_ID {
- DC_IH_SRC_ID_START = 0x1,
- DC_IH_SRC_ID_END = 0x1f,
- VGA_IH_SRC_ID_START = 0x20,
- VGA_IH_SRC_ID_END = 0x27,
- CAP_IH_SRC_ID_START = 0x28,
- CAP_IH_SRC_ID_END = 0x2f,
- VIP_IH_SRC_ID_START = 0x30,
- VIP_IH_SRC_ID_END = 0x3f,
- ROM_IH_SRC_ID_START = 0x40,
- ROM_IH_SRC_ID_END = 0x5d,
- BIF_IH_SRC_ID_START = 0x5e,
- SAM_IH_SRC_ID_START = 0x5f,
- SRBM_IH_SRC_ID_START = 0x60,
- SRBM_IH_SRC_ID_END = 0x67,
- UVD_IH_SRC_ID_START = 0x72,
- UVD_IH_SRC_ID_END = 0x85,
- VMC_IH_SRC_ID_START = 0x86,
- VMC_IH_SRC_ID_END = 0x8f,
- RLC_IH_SRC_ID_START = 0x90,
- RLC_IH_SRC_ID_END = 0xf3,
- PDMA_IH_SRC_ID_START = 0xf4,
- PDMA_IH_SRC_ID_END = 0xf7,
- CG_IH_SRC_ID_START = 0xf8,
- CG_IH_SRC_ID_END = 0xff,
-} IH_CLIENT_ID;
-typedef enum IH_PERF_SEL {
- IH_PERF_SEL_CYCLE = 0x0,
- IH_PERF_SEL_IDLE = 0x1,
- IH_PERF_SEL_INPUT_IDLE = 0x2,
- IH_PERF_SEL_CLIENT0_IH_STALL = 0x3,
- IH_PERF_SEL_CLIENT1_IH_STALL = 0x4,
- IH_PERF_SEL_CLIENT2_IH_STALL = 0x5,
- IH_PERF_SEL_CLIENT3_IH_STALL = 0x6,
- IH_PERF_SEL_CLIENT4_IH_STALL = 0x7,
- IH_PERF_SEL_CLIENT5_IH_STALL = 0x8,
- IH_PERF_SEL_CLIENT6_IH_STALL = 0x9,
- IH_PERF_SEL_CLIENT7_IH_STALL = 0xa,
- IH_PERF_SEL_RB_IDLE = 0xb,
- IH_PERF_SEL_RB_FULL = 0xc,
- IH_PERF_SEL_RB_OVERFLOW = 0xd,
- IH_PERF_SEL_RB_WPTR_WRITEBACK = 0xe,
- IH_PERF_SEL_RB_WPTR_WRAP = 0xf,
- IH_PERF_SEL_RB_RPTR_WRAP = 0x10,
- IH_PERF_SEL_MC_WR_IDLE = 0x11,
- IH_PERF_SEL_MC_WR_COUNT = 0x12,
- IH_PERF_SEL_MC_WR_STALL = 0x13,
- IH_PERF_SEL_MC_WR_CLEAN_PENDING = 0x14,
- IH_PERF_SEL_MC_WR_CLEAN_STALL = 0x15,
- IH_PERF_SEL_BIF_RISING = 0x16,
- IH_PERF_SEL_BIF_FALLING = 0x17,
- IH_PERF_SEL_CLIENT8_IH_STALL = 0x18,
- IH_PERF_SEL_CLIENT9_IH_STALL = 0x19,
- IH_PERF_SEL_CLIENT10_IH_STALL = 0x1a,
- IH_PERF_SEL_CLIENT11_IH_STALL = 0x1b,
- IH_PERF_SEL_CLIENT12_IH_STALL = 0x1c,
- IH_PERF_SEL_CLIENT13_IH_STALL = 0x1d,
- IH_PERF_SEL_CLIENT14_IH_STALL = 0x1e,
- IH_PERF_SEL_CLIENT15_IH_STALL = 0x1f,
- IH_PERF_SEL_CLIENT16_IH_STALL = 0x20,
- IH_PERF_SEL_CLIENT17_IH_STALL = 0x21,
- IH_PERF_SEL_CLIENT18_IH_STALL = 0x22,
- IH_PERF_SEL_CLIENT19_IH_STALL = 0x23,
- IH_PERF_SEL_CLIENT20_IH_STALL = 0x24,
- IH_PERF_SEL_CLIENT21_IH_STALL = 0x25,
-} IH_PERF_SEL;
-typedef enum SRBM_PERFCOUNT1_SEL {
- SRBM_PERF_SEL_COUNT = 0x0,
- SRBM_PERF_SEL_BIF_BUSY = 0x1,
- SRBM_PERF_SEL_SDMA0_BUSY = 0x3,
- SRBM_PERF_SEL_IH_BUSY = 0x4,
- SRBM_PERF_SEL_MCB_BUSY = 0x5,
- SRBM_PERF_SEL_MCB_NON_DISPLAY_BUSY = 0x6,
- SRBM_PERF_SEL_MCC_BUSY = 0x7,
- SRBM_PERF_SEL_MCD_BUSY = 0x8,
- SRBM_PERF_SEL_CHUB_BUSY = 0x9,
- SRBM_PERF_SEL_SEM_BUSY = 0xa,
- SRBM_PERF_SEL_UVD_BUSY = 0xb,
- SRBM_PERF_SEL_VMC_BUSY = 0xc,
- SRBM_PERF_SEL_XSP_BUSY = 0xd,
- SRBM_PERF_SEL_SDMA1_BUSY = 0xe,
- SRBM_PERF_SEL_SAMMSP_BUSY = 0xf,
- SRBM_PERF_SEL_VCE0_BUSY = 0x10,
- SRBM_PERF_SEL_XDMA_BUSY = 0x11,
- SRBM_PERF_SEL_ACP_BUSY = 0x12,
- SRBM_PERF_SEL_SDMA2_BUSY = 0x13,
- SRBM_PERF_SEL_SDMA3_BUSY = 0x14,
- SRBM_PERF_SEL_SAMSCP_BUSY = 0x15,
- SRBM_PERF_SEL_VMC1_BUSY = 0x16,
- SRBM_PERF_SEL_ISP_BUSY = 0x17,
- SRBM_PERF_SEL_VCE1_BUSY = 0x18,
- SRBM_PERF_SEL_GCATCL2_BUSY = 0x19,
- SRBM_PERF_SEL_OSATCL2_BUSY = 0x1a,
-} SRBM_PERFCOUNT1_SEL;
-typedef enum SYS_GRBM_GFX_INDEX_SEL {
- GRBM_GFX_INDEX_BIF = 0x0,
- GRBM_GFX_INDEX_SDMA0 = 0x1,
- GRBM_GFX_INDEX_SDMA1 = 0x2,
- RESEVERED0 = 0x3,
- GRBM_GFX_INDEX_UVD = 0x4,
- GRBM_GFX_INDEX_VCE0 = 0x5,
- GRBM_GFX_INDEX_VCE1 = 0x6,
- GRBM_GFX_INDEX_ACP = 0x7,
- GRBM_GFX_INDEX_SMU = 0x8,
- GRBM_GFX_INDEX_SAMMSP = 0x9,
- GRBM_GFX_INDEX_SAMSCP = 0xa,
- GRBM_GFX_INDEX_ISP = 0xb,
- GRBM_GFX_INDEX_TST = 0xc,
- GRBM_GFX_INDEX_SDMA2 = 0xd,
- GRBM_GFX_INDEX_SDMA3 = 0xe,
-} SYS_GRBM_GFX_INDEX_SEL;
-typedef enum SRBM_GFX_CNTL_SEL {
- SRBM_GFX_CNTL_BIF = 0x0,
- SRBM_GFX_CNTL_SDMA0 = 0x1,
- SRBM_GFX_CNTL_SDMA1 = 0x2,
- SRBM_GFX_CNTL_GRBM = 0x3,
- SRBM_GFX_CNTL_UVD = 0x4,
- SRBM_GFX_CNTL_VCE0 = 0x5,
- SRBM_GFX_CNTL_VCE1 = 0x6,
- SRBM_GFX_CNTL_ACP = 0x7,
- SRBM_GFX_CNTL_SMU = 0x8,
- SRBM_GFX_CNTL_SAMMSP = 0x9,
- SRBM_GFX_CNTL_SAMSCP = 0xa,
- SRBM_GFX_CNTL_ISP = 0xb,
- SRBM_GFX_CNTL_TST = 0xc,
- SRBM_GFX_CNTL_SDMA2 = 0xd,
- SRBM_GFX_CNTL_SDMA3 = 0xe,
-} SRBM_GFX_CNTL_SEL;
-typedef enum SDMA_PERF_SEL {
- SDMA_PERF_SEL_CYCLE = 0x0,
- SDMA_PERF_SEL_IDLE = 0x1,
- SDMA_PERF_SEL_REG_IDLE = 0x2,
- SDMA_PERF_SEL_RB_EMPTY = 0x3,
- SDMA_PERF_SEL_RB_FULL = 0x4,
- SDMA_PERF_SEL_RB_WPTR_WRAP = 0x5,
- SDMA_PERF_SEL_RB_RPTR_WRAP = 0x6,
- SDMA_PERF_SEL_RB_WPTR_POLL_READ = 0x7,
- SDMA_PERF_SEL_RB_RPTR_WB = 0x8,
- SDMA_PERF_SEL_RB_CMD_IDLE = 0x9,
- SDMA_PERF_SEL_RB_CMD_FULL = 0xa,
- SDMA_PERF_SEL_IB_CMD_IDLE = 0xb,
- SDMA_PERF_SEL_IB_CMD_FULL = 0xc,
- SDMA_PERF_SEL_EX_IDLE = 0xd,
- SDMA_PERF_SEL_SRBM_REG_SEND = 0xe,
- SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0xf,
- SDMA_PERF_SEL_MC_WR_IDLE = 0x10,
- SDMA_PERF_SEL_MC_WR_COUNT = 0x11,
- SDMA_PERF_SEL_MC_RD_IDLE = 0x12,
- SDMA_PERF_SEL_MC_RD_COUNT = 0x13,
- SDMA_PERF_SEL_MC_RD_RET_STALL = 0x14,
- SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 0x15,
- SDMA_PERF_SEL_SEM_IDLE = 0x18,
- SDMA_PERF_SEL_SEM_REQ_STALL = 0x19,
- SDMA_PERF_SEL_SEM_REQ_COUNT = 0x1a,
- SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 0x1b,
- SDMA_PERF_SEL_SEM_RESP_FAIL = 0x1c,
- SDMA_PERF_SEL_SEM_RESP_PASS = 0x1d,
- SDMA_PERF_SEL_INT_IDLE = 0x1e,
- SDMA_PERF_SEL_INT_REQ_STALL = 0x1f,
- SDMA_PERF_SEL_INT_REQ_COUNT = 0x20,
- SDMA_PERF_SEL_INT_RESP_ACCEPTED = 0x21,
- SDMA_PERF_SEL_INT_RESP_RETRY = 0x22,
- SDMA_PERF_SEL_NUM_PACKET = 0x23,
- SDMA_PERF_SEL_CE_WREQ_IDLE = 0x25,
- SDMA_PERF_SEL_CE_WR_IDLE = 0x26,
- SDMA_PERF_SEL_CE_SPLIT_IDLE = 0x27,
- SDMA_PERF_SEL_CE_RREQ_IDLE = 0x28,
- SDMA_PERF_SEL_CE_OUT_IDLE = 0x29,
- SDMA_PERF_SEL_CE_IN_IDLE = 0x2a,
- SDMA_PERF_SEL_CE_DST_IDLE = 0x2b,
- SDMA_PERF_SEL_CE_AFIFO_FULL = 0x2e,
- SDMA_PERF_SEL_CE_INFO_FULL = 0x31,
- SDMA_PERF_SEL_CE_INFO1_FULL = 0x32,
- SDMA_PERF_SEL_CE_RD_STALL = 0x33,
- SDMA_PERF_SEL_CE_WR_STALL = 0x34,
- SDMA_PERF_SEL_GFX_SELECT = 0x35,
- SDMA_PERF_SEL_RLC0_SELECT = 0x36,
- SDMA_PERF_SEL_RLC1_SELECT = 0x37,
- SDMA_PERF_SEL_CTX_CHANGE = 0x38,
- SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 0x39,
- SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 0x3a,
- SDMA_PERF_SEL_DOORBELL = 0x3b,
- SDMA_PERF_SEL_RD_BA_RTR = 0x3c,
- SDMA_PERF_SEL_WR_BA_RTR = 0x3d,
-} SDMA_PERF_SEL;
-typedef enum SurfaceEndian {
- ENDIAN_NONE = 0x0,
- ENDIAN_8IN16 = 0x1,
- ENDIAN_8IN32 = 0x2,
- ENDIAN_8IN64 = 0x3,
-} SurfaceEndian;
-typedef enum ArrayMode {
- ARRAY_LINEAR_GENERAL = 0x0,
- ARRAY_LINEAR_ALIGNED = 0x1,
- ARRAY_1D_TILED_THIN1 = 0x2,
- ARRAY_1D_TILED_THICK = 0x3,
- ARRAY_2D_TILED_THIN1 = 0x4,
- ARRAY_PRT_TILED_THIN1 = 0x5,
- ARRAY_PRT_2D_TILED_THIN1 = 0x6,
- ARRAY_2D_TILED_THICK = 0x7,
- ARRAY_2D_TILED_XTHICK = 0x8,
- ARRAY_PRT_TILED_THICK = 0x9,
- ARRAY_PRT_2D_TILED_THICK = 0xa,
- ARRAY_PRT_3D_TILED_THIN1 = 0xb,
- ARRAY_3D_TILED_THIN1 = 0xc,
- ARRAY_3D_TILED_THICK = 0xd,
- ARRAY_3D_TILED_XTHICK = 0xe,
- ARRAY_PRT_3D_TILED_THICK = 0xf,
-} ArrayMode;
-typedef enum PipeTiling {
- CONFIG_1_PIPE = 0x0,
- CONFIG_2_PIPE = 0x1,
- CONFIG_4_PIPE = 0x2,
- CONFIG_8_PIPE = 0x3,
-} PipeTiling;
-typedef enum BankTiling {
- CONFIG_4_BANK = 0x0,
- CONFIG_8_BANK = 0x1,
-} BankTiling;
-typedef enum GroupInterleave {
- CONFIG_256B_GROUP = 0x0,
- CONFIG_512B_GROUP = 0x1,
-} GroupInterleave;
-typedef enum RowTiling {
- CONFIG_1KB_ROW = 0x0,
- CONFIG_2KB_ROW = 0x1,
- CONFIG_4KB_ROW = 0x2,
- CONFIG_8KB_ROW = 0x3,
- CONFIG_1KB_ROW_OPT = 0x4,
- CONFIG_2KB_ROW_OPT = 0x5,
- CONFIG_4KB_ROW_OPT = 0x6,
- CONFIG_8KB_ROW_OPT = 0x7,
-} RowTiling;
-typedef enum BankSwapBytes {
- CONFIG_128B_SWAPS = 0x0,
- CONFIG_256B_SWAPS = 0x1,
- CONFIG_512B_SWAPS = 0x2,
- CONFIG_1KB_SWAPS = 0x3,
-} BankSwapBytes;
-typedef enum SampleSplitBytes {
- CONFIG_1KB_SPLIT = 0x0,
- CONFIG_2KB_SPLIT = 0x1,
- CONFIG_4KB_SPLIT = 0x2,
- CONFIG_8KB_SPLIT = 0x3,
-} SampleSplitBytes;
-typedef enum NumPipes {
- ADDR_CONFIG_1_PIPE = 0x0,
- ADDR_CONFIG_2_PIPE = 0x1,
- ADDR_CONFIG_4_PIPE = 0x2,
- ADDR_CONFIG_8_PIPE = 0x3,
-} NumPipes;
-typedef enum PipeInterleaveSize {
- ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
- ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
-} PipeInterleaveSize;
-typedef enum BankInterleaveSize {
- ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
- ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
- ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
- ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
-} BankInterleaveSize;
-typedef enum NumShaderEngines {
- ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
- ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
-} NumShaderEngines;
-typedef enum ShaderEngineTileSize {
- ADDR_CONFIG_SE_TILE_16 = 0x0,
- ADDR_CONFIG_SE_TILE_32 = 0x1,
-} ShaderEngineTileSize;
-typedef enum NumGPUs {
- ADDR_CONFIG_1_GPU = 0x0,
- ADDR_CONFIG_2_GPU = 0x1,
- ADDR_CONFIG_4_GPU = 0x2,
-} NumGPUs;
-typedef enum MultiGPUTileSize {
- ADDR_CONFIG_GPU_TILE_16 = 0x0,
- ADDR_CONFIG_GPU_TILE_32 = 0x1,
- ADDR_CONFIG_GPU_TILE_64 = 0x2,
- ADDR_CONFIG_GPU_TILE_128 = 0x3,
-} MultiGPUTileSize;
-typedef enum RowSize {
- ADDR_CONFIG_1KB_ROW = 0x0,
- ADDR_CONFIG_2KB_ROW = 0x1,
- ADDR_CONFIG_4KB_ROW = 0x2,
-} RowSize;
-typedef enum NumLowerPipes {
- ADDR_CONFIG_1_LOWER_PIPES = 0x0,
- ADDR_CONFIG_2_LOWER_PIPES = 0x1,
-} NumLowerPipes;
-typedef enum DebugBlockId {
- DBG_CLIENT_BLKID_RESERVED = 0x0,
- DBG_CLIENT_BLKID_dbg = 0x1,
- DBG_CLIENT_BLKID_uvdu_0 = 0x2,
- DBG_CLIENT_BLKID_uvdu_1 = 0x3,
- DBG_CLIENT_BLKID_uvdu_2 = 0x4,
- DBG_CLIENT_BLKID_uvdu_3 = 0x5,
- DBG_CLIENT_BLKID_uvdu_4 = 0x6,
- DBG_CLIENT_BLKID_uvdu_5 = 0x7,
- DBG_CLIENT_BLKID_uvdu_6 = 0x8,
- DBG_CLIENT_BLKID_uvdb_0 = 0x9,
- DBG_CLIENT_BLKID_uvdc_0 = 0xa,
- DBG_CLIENT_BLKID_uvdc_1 = 0xb,
- DBG_CLIENT_BLKID_uvdf_0 = 0xc,
- DBG_CLIENT_BLKID_uvdf_1 = 0xd,
- DBG_CLIENT_BLKID_uvdm_0 = 0xe,
- DBG_CLIENT_BLKID_uvdm_1 = 0xf,
- DBG_CLIENT_BLKID_uvdm_2 = 0x10,
- DBG_CLIENT_BLKID_uvdm_3 = 0x11,
- DBG_CLIENT_BLKID_vcea_0 = 0x12,
- DBG_CLIENT_BLKID_vcea_1 = 0x13,
- DBG_CLIENT_BLKID_vcea_2 = 0x14,
- DBG_CLIENT_BLKID_vcea_3 = 0x15,
- DBG_CLIENT_BLKID_vceb_0 = 0x16,
- DBG_CLIENT_BLKID_vcec_0 = 0x17,
- DBG_CLIENT_BLKID_dco = 0x18,
- DBG_CLIENT_BLKID_xdma = 0x19,
- DBG_CLIENT_BLKID_dci_pg = 0x1a,
- DBG_CLIENT_BLKID_smu_0 = 0x1b,
- DBG_CLIENT_BLKID_smu_1 = 0x1c,
- DBG_CLIENT_BLKID_smu_2 = 0x1d,
- DBG_CLIENT_BLKID_gck = 0x1e,
- DBG_CLIENT_BLKID_tmonw0 = 0x1f,
- DBG_CLIENT_BLKID_tmonw1 = 0x20,
- DBG_CLIENT_BLKID_grbm = 0x21,
- DBG_CLIENT_BLKID_rlc = 0x22,
- DBG_CLIENT_BLKID_ds0 = 0x23,
- DBG_CLIENT_BLKID_cpg_0 = 0x24,
- DBG_CLIENT_BLKID_cpg_1 = 0x25,
- DBG_CLIENT_BLKID_cpc_0 = 0x26,
- DBG_CLIENT_BLKID_cpc_1 = 0x27,
- DBG_CLIENT_BLKID_cpf_0 = 0x28,
- DBG_CLIENT_BLKID_cpf_1 = 0x29,
- DBG_CLIENT_BLKID_scf0 = 0x2a,
- DBG_CLIENT_BLKID_scf1 = 0x2b,
- DBG_CLIENT_BLKID_scf2 = 0x2c,
- DBG_CLIENT_BLKID_scf3 = 0x2d,
- DBG_CLIENT_BLKID_pc0 = 0x2e,
- DBG_CLIENT_BLKID_pc1 = 0x2f,
- DBG_CLIENT_BLKID_pc2 = 0x30,
- DBG_CLIENT_BLKID_pc3 = 0x31,
- DBG_CLIENT_BLKID_vgt0 = 0x32,
- DBG_CLIENT_BLKID_vgt1 = 0x33,
- DBG_CLIENT_BLKID_vgt2 = 0x34,
- DBG_CLIENT_BLKID_vgt3 = 0x35,
- DBG_CLIENT_BLKID_sx00 = 0x36,
- DBG_CLIENT_BLKID_sx10 = 0x37,
- DBG_CLIENT_BLKID_sx20 = 0x38,
- DBG_CLIENT_BLKID_sx30 = 0x39,
- DBG_CLIENT_BLKID_cb001 = 0x3a,
- DBG_CLIENT_BLKID_cb200 = 0x3b,
- DBG_CLIENT_BLKID_cb201 = 0x3c,
- DBG_CLIENT_BLKID_cbr0 = 0x3d,
- DBG_CLIENT_BLKID_cb000 = 0x3e,
- DBG_CLIENT_BLKID_cb101 = 0x3f,
- DBG_CLIENT_BLKID_cb300 = 0x40,
- DBG_CLIENT_BLKID_cb301 = 0x41,
- DBG_CLIENT_BLKID_cbr1 = 0x42,
- DBG_CLIENT_BLKID_cb100 = 0x43,
- DBG_CLIENT_BLKID_ia0 = 0x44,
- DBG_CLIENT_BLKID_ia1 = 0x45,
- DBG_CLIENT_BLKID_bci0 = 0x46,
- DBG_CLIENT_BLKID_bci1 = 0x47,
- DBG_CLIENT_BLKID_bci2 = 0x48,
- DBG_CLIENT_BLKID_bci3 = 0x49,
- DBG_CLIENT_BLKID_pa0 = 0x4a,
- DBG_CLIENT_BLKID_pa1 = 0x4b,
- DBG_CLIENT_BLKID_spim0 = 0x4c,
- DBG_CLIENT_BLKID_spim1 = 0x4d,
- DBG_CLIENT_BLKID_spim2 = 0x4e,
- DBG_CLIENT_BLKID_spim3 = 0x4f,
- DBG_CLIENT_BLKID_sdma = 0x50,
- DBG_CLIENT_BLKID_ih = 0x51,
- DBG_CLIENT_BLKID_sem = 0x52,
- DBG_CLIENT_BLKID_srbm = 0x53,
- DBG_CLIENT_BLKID_hdp = 0x54,
- DBG_CLIENT_BLKID_acp_0 = 0x55,
- DBG_CLIENT_BLKID_acp_1 = 0x56,
- DBG_CLIENT_BLKID_sam = 0x57,
- DBG_CLIENT_BLKID_mcc0 = 0x58,
- DBG_CLIENT_BLKID_mcc1 = 0x59,
- DBG_CLIENT_BLKID_mcc2 = 0x5a,
- DBG_CLIENT_BLKID_mcc3 = 0x5b,
- DBG_CLIENT_BLKID_mcd0 = 0x5c,
- DBG_CLIENT_BLKID_mcd1 = 0x5d,
- DBG_CLIENT_BLKID_mcd2 = 0x5e,
- DBG_CLIENT_BLKID_mcd3 = 0x5f,
- DBG_CLIENT_BLKID_mcb = 0x60,
- DBG_CLIENT_BLKID_vmc = 0x61,
- DBG_CLIENT_BLKID_gmcon = 0x62,
- DBG_CLIENT_BLKID_gdc_0 = 0x63,
- DBG_CLIENT_BLKID_gdc_1 = 0x64,
- DBG_CLIENT_BLKID_gdc_2 = 0x65,
- DBG_CLIENT_BLKID_gdc_3 = 0x66,
- DBG_CLIENT_BLKID_gdc_4 = 0x67,
- DBG_CLIENT_BLKID_gdc_5 = 0x68,
- DBG_CLIENT_BLKID_gdc_6 = 0x69,
- DBG_CLIENT_BLKID_gdc_7 = 0x6a,
- DBG_CLIENT_BLKID_gdc_8 = 0x6b,
- DBG_CLIENT_BLKID_gdc_9 = 0x6c,
- DBG_CLIENT_BLKID_gdc_10 = 0x6d,
- DBG_CLIENT_BLKID_gdc_11 = 0x6e,
- DBG_CLIENT_BLKID_gdc_12 = 0x6f,
- DBG_CLIENT_BLKID_gdc_13 = 0x70,
- DBG_CLIENT_BLKID_gdc_14 = 0x71,
- DBG_CLIENT_BLKID_gdc_15 = 0x72,
- DBG_CLIENT_BLKID_gdc_16 = 0x73,
- DBG_CLIENT_BLKID_gdc_17 = 0x74,
- DBG_CLIENT_BLKID_gdc_18 = 0x75,
- DBG_CLIENT_BLKID_gdc_19 = 0x76,
- DBG_CLIENT_BLKID_gdc_20 = 0x77,
- DBG_CLIENT_BLKID_gdc_21 = 0x78,
- DBG_CLIENT_BLKID_gdc_22 = 0x79,
- DBG_CLIENT_BLKID_gdc_23 = 0x7a,
- DBG_CLIENT_BLKID_gdc_24 = 0x7b,
- DBG_CLIENT_BLKID_gdc_25 = 0x7c,
- DBG_CLIENT_BLKID_gdc_26 = 0x7d,
- DBG_CLIENT_BLKID_gdc_27 = 0x7e,
- DBG_CLIENT_BLKID_gdc_28 = 0x7f,
- DBG_CLIENT_BLKID_wd = 0x80,
- DBG_CLIENT_BLKID_sdma_0 = 0x81,
- DBG_CLIENT_BLKID_sdma_1 = 0x82,
- DBG_CLIENT_BLKID_sammsp = 0x83,
- DBG_CLIENT_BLKID_dci_0 = 0x84,
- DBG_CLIENT_BLKID_dccg0_0 = 0x85,
- DBG_CLIENT_BLKID_dcfe01_0 = 0x86,
- DBG_CLIENT_BLKID_dcfe02_0 = 0x87,
- DBG_CLIENT_BLKID_dcfe03_0 = 0x88,
- DBG_CLIENT_BLKID_dccg0_1 = 0x89,
-} DebugBlockId;
-typedef enum DebugBlockId_OLD {
- DBG_BLOCK_ID_RESERVED = 0x0,
- DBG_BLOCK_ID_DBG = 0x1,
- DBG_BLOCK_ID_VMC = 0x2,
- DBG_BLOCK_ID_PDMA = 0x3,
- DBG_BLOCK_ID_CG = 0x4,
- DBG_BLOCK_ID_SRBM = 0x5,
- DBG_BLOCK_ID_GRBM = 0x6,
- DBG_BLOCK_ID_RLC = 0x7,
- DBG_BLOCK_ID_CSC = 0x8,
- DBG_BLOCK_ID_SEM = 0x9,
- DBG_BLOCK_ID_IH = 0xa,
- DBG_BLOCK_ID_SC = 0xb,
- DBG_BLOCK_ID_SQ = 0xc,
- DBG_BLOCK_ID_AVP = 0xd,
- DBG_BLOCK_ID_GMCON = 0xe,
- DBG_BLOCK_ID_SMU = 0xf,
- DBG_BLOCK_ID_DMA0 = 0x10,
- DBG_BLOCK_ID_DMA1 = 0x11,
- DBG_BLOCK_ID_SPIM = 0x12,
- DBG_BLOCK_ID_GDS = 0x13,
- DBG_BLOCK_ID_SPIS = 0x14,
- DBG_BLOCK_ID_UNUSED0 = 0x15,
- DBG_BLOCK_ID_PA0 = 0x16,
- DBG_BLOCK_ID_PA1 = 0x17,
- DBG_BLOCK_ID_CP0 = 0x18,
- DBG_BLOCK_ID_CP1 = 0x19,
- DBG_BLOCK_ID_CP2 = 0x1a,
- DBG_BLOCK_ID_UNUSED1 = 0x1b,
- DBG_BLOCK_ID_UVDU = 0x1c,
- DBG_BLOCK_ID_UVDM = 0x1d,
- DBG_BLOCK_ID_VCE = 0x1e,
- DBG_BLOCK_ID_UNUSED2 = 0x1f,
- DBG_BLOCK_ID_VGT0 = 0x20,
- DBG_BLOCK_ID_VGT1 = 0x21,
- DBG_BLOCK_ID_IA = 0x22,
- DBG_BLOCK_ID_UNUSED3 = 0x23,
- DBG_BLOCK_ID_SCT0 = 0x24,
- DBG_BLOCK_ID_SCT1 = 0x25,
- DBG_BLOCK_ID_SPM0 = 0x26,
- DBG_BLOCK_ID_SPM1 = 0x27,
- DBG_BLOCK_ID_TCAA = 0x28,
- DBG_BLOCK_ID_TCAB = 0x29,
- DBG_BLOCK_ID_TCCA = 0x2a,
- DBG_BLOCK_ID_TCCB = 0x2b,
- DBG_BLOCK_ID_MCC0 = 0x2c,
- DBG_BLOCK_ID_MCC1 = 0x2d,
- DBG_BLOCK_ID_MCC2 = 0x2e,
- DBG_BLOCK_ID_MCC3 = 0x2f,
- DBG_BLOCK_ID_SX0 = 0x30,
- DBG_BLOCK_ID_SX1 = 0x31,
- DBG_BLOCK_ID_SX2 = 0x32,
- DBG_BLOCK_ID_SX3 = 0x33,
- DBG_BLOCK_ID_UNUSED4 = 0x34,
- DBG_BLOCK_ID_UNUSED5 = 0x35,
- DBG_BLOCK_ID_UNUSED6 = 0x36,
- DBG_BLOCK_ID_UNUSED7 = 0x37,
- DBG_BLOCK_ID_PC0 = 0x38,
- DBG_BLOCK_ID_PC1 = 0x39,
- DBG_BLOCK_ID_UNUSED8 = 0x3a,
- DBG_BLOCK_ID_UNUSED9 = 0x3b,
- DBG_BLOCK_ID_UNUSED10 = 0x3c,
- DBG_BLOCK_ID_UNUSED11 = 0x3d,
- DBG_BLOCK_ID_MCB = 0x3e,
- DBG_BLOCK_ID_UNUSED12 = 0x3f,
- DBG_BLOCK_ID_SCB0 = 0x40,
- DBG_BLOCK_ID_SCB1 = 0x41,
- DBG_BLOCK_ID_UNUSED13 = 0x42,
- DBG_BLOCK_ID_UNUSED14 = 0x43,
- DBG_BLOCK_ID_SCF0 = 0x44,
- DBG_BLOCK_ID_SCF1 = 0x45,
- DBG_BLOCK_ID_UNUSED15 = 0x46,
- DBG_BLOCK_ID_UNUSED16 = 0x47,
- DBG_BLOCK_ID_BCI0 = 0x48,
- DBG_BLOCK_ID_BCI1 = 0x49,
- DBG_BLOCK_ID_BCI2 = 0x4a,
- DBG_BLOCK_ID_BCI3 = 0x4b,
- DBG_BLOCK_ID_UNUSED17 = 0x4c,
- DBG_BLOCK_ID_UNUSED18 = 0x4d,
- DBG_BLOCK_ID_UNUSED19 = 0x4e,
- DBG_BLOCK_ID_UNUSED20 = 0x4f,
- DBG_BLOCK_ID_CB00 = 0x50,
- DBG_BLOCK_ID_CB01 = 0x51,
- DBG_BLOCK_ID_CB02 = 0x52,
- DBG_BLOCK_ID_CB03 = 0x53,
- DBG_BLOCK_ID_CB04 = 0x54,
- DBG_BLOCK_ID_UNUSED21 = 0x55,
- DBG_BLOCK_ID_UNUSED22 = 0x56,
- DBG_BLOCK_ID_UNUSED23 = 0x57,
- DBG_BLOCK_ID_CB10 = 0x58,
- DBG_BLOCK_ID_CB11 = 0x59,
- DBG_BLOCK_ID_CB12 = 0x5a,
- DBG_BLOCK_ID_CB13 = 0x5b,
- DBG_BLOCK_ID_CB14 = 0x5c,
- DBG_BLOCK_ID_UNUSED24 = 0x5d,
- DBG_BLOCK_ID_UNUSED25 = 0x5e,
- DBG_BLOCK_ID_UNUSED26 = 0x5f,
- DBG_BLOCK_ID_TCP0 = 0x60,
- DBG_BLOCK_ID_TCP1 = 0x61,
- DBG_BLOCK_ID_TCP2 = 0x62,
- DBG_BLOCK_ID_TCP3 = 0x63,
- DBG_BLOCK_ID_TCP4 = 0x64,
- DBG_BLOCK_ID_TCP5 = 0x65,
- DBG_BLOCK_ID_TCP6 = 0x66,
- DBG_BLOCK_ID_TCP7 = 0x67,
- DBG_BLOCK_ID_TCP8 = 0x68,
- DBG_BLOCK_ID_TCP9 = 0x69,
- DBG_BLOCK_ID_TCP10 = 0x6a,
- DBG_BLOCK_ID_TCP11 = 0x6b,
- DBG_BLOCK_ID_TCP12 = 0x6c,
- DBG_BLOCK_ID_TCP13 = 0x6d,
- DBG_BLOCK_ID_TCP14 = 0x6e,
- DBG_BLOCK_ID_TCP15 = 0x6f,
- DBG_BLOCK_ID_TCP16 = 0x70,
- DBG_BLOCK_ID_TCP17 = 0x71,
- DBG_BLOCK_ID_TCP18 = 0x72,
- DBG_BLOCK_ID_TCP19 = 0x73,
- DBG_BLOCK_ID_TCP20 = 0x74,
- DBG_BLOCK_ID_TCP21 = 0x75,
- DBG_BLOCK_ID_TCP22 = 0x76,
- DBG_BLOCK_ID_TCP23 = 0x77,
- DBG_BLOCK_ID_TCP_RESERVED0 = 0x78,
- DBG_BLOCK_ID_TCP_RESERVED1 = 0x79,
- DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a,
- DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b,
- DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c,
- DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d,
- DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e,
- DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f,
- DBG_BLOCK_ID_DB00 = 0x80,
- DBG_BLOCK_ID_DB01 = 0x81,
- DBG_BLOCK_ID_DB02 = 0x82,
- DBG_BLOCK_ID_DB03 = 0x83,
- DBG_BLOCK_ID_DB04 = 0x84,
- DBG_BLOCK_ID_UNUSED27 = 0x85,
- DBG_BLOCK_ID_UNUSED28 = 0x86,
- DBG_BLOCK_ID_UNUSED29 = 0x87,
- DBG_BLOCK_ID_DB10 = 0x88,
- DBG_BLOCK_ID_DB11 = 0x89,
- DBG_BLOCK_ID_DB12 = 0x8a,
- DBG_BLOCK_ID_DB13 = 0x8b,
- DBG_BLOCK_ID_DB14 = 0x8c,
- DBG_BLOCK_ID_UNUSED30 = 0x8d,
- DBG_BLOCK_ID_UNUSED31 = 0x8e,
- DBG_BLOCK_ID_UNUSED32 = 0x8f,
- DBG_BLOCK_ID_TCC0 = 0x90,
- DBG_BLOCK_ID_TCC1 = 0x91,
- DBG_BLOCK_ID_TCC2 = 0x92,
- DBG_BLOCK_ID_TCC3 = 0x93,
- DBG_BLOCK_ID_TCC4 = 0x94,
- DBG_BLOCK_ID_TCC5 = 0x95,
- DBG_BLOCK_ID_TCC6 = 0x96,
- DBG_BLOCK_ID_TCC7 = 0x97,
- DBG_BLOCK_ID_SPS00 = 0x98,
- DBG_BLOCK_ID_SPS01 = 0x99,
- DBG_BLOCK_ID_SPS02 = 0x9a,
- DBG_BLOCK_ID_SPS10 = 0x9b,
- DBG_BLOCK_ID_SPS11 = 0x9c,
- DBG_BLOCK_ID_SPS12 = 0x9d,
- DBG_BLOCK_ID_UNUSED33 = 0x9e,
- DBG_BLOCK_ID_UNUSED34 = 0x9f,
- DBG_BLOCK_ID_TA00 = 0xa0,
- DBG_BLOCK_ID_TA01 = 0xa1,
- DBG_BLOCK_ID_TA02 = 0xa2,
- DBG_BLOCK_ID_TA03 = 0xa3,
- DBG_BLOCK_ID_TA04 = 0xa4,
- DBG_BLOCK_ID_TA05 = 0xa5,
- DBG_BLOCK_ID_TA06 = 0xa6,
- DBG_BLOCK_ID_TA07 = 0xa7,
- DBG_BLOCK_ID_TA08 = 0xa8,
- DBG_BLOCK_ID_TA09 = 0xa9,
- DBG_BLOCK_ID_TA0A = 0xaa,
- DBG_BLOCK_ID_TA0B = 0xab,
- DBG_BLOCK_ID_UNUSED35 = 0xac,
- DBG_BLOCK_ID_UNUSED36 = 0xad,
- DBG_BLOCK_ID_UNUSED37 = 0xae,
- DBG_BLOCK_ID_UNUSED38 = 0xaf,
- DBG_BLOCK_ID_TA10 = 0xb0,
- DBG_BLOCK_ID_TA11 = 0xb1,
- DBG_BLOCK_ID_TA12 = 0xb2,
- DBG_BLOCK_ID_TA13 = 0xb3,
- DBG_BLOCK_ID_TA14 = 0xb4,
- DBG_BLOCK_ID_TA15 = 0xb5,
- DBG_BLOCK_ID_TA16 = 0xb6,
- DBG_BLOCK_ID_TA17 = 0xb7,
- DBG_BLOCK_ID_TA18 = 0xb8,
- DBG_BLOCK_ID_TA19 = 0xb9,
- DBG_BLOCK_ID_TA1A = 0xba,
- DBG_BLOCK_ID_TA1B = 0xbb,
- DBG_BLOCK_ID_UNUSED39 = 0xbc,
- DBG_BLOCK_ID_UNUSED40 = 0xbd,
- DBG_BLOCK_ID_UNUSED41 = 0xbe,
- DBG_BLOCK_ID_UNUSED42 = 0xbf,
- DBG_BLOCK_ID_TD00 = 0xc0,
- DBG_BLOCK_ID_TD01 = 0xc1,
- DBG_BLOCK_ID_TD02 = 0xc2,
- DBG_BLOCK_ID_TD03 = 0xc3,
- DBG_BLOCK_ID_TD04 = 0xc4,
- DBG_BLOCK_ID_TD05 = 0xc5,
- DBG_BLOCK_ID_TD06 = 0xc6,
- DBG_BLOCK_ID_TD07 = 0xc7,
- DBG_BLOCK_ID_TD08 = 0xc8,
- DBG_BLOCK_ID_TD09 = 0xc9,
- DBG_BLOCK_ID_TD0A = 0xca,
- DBG_BLOCK_ID_TD0B = 0xcb,
- DBG_BLOCK_ID_UNUSED43 = 0xcc,
- DBG_BLOCK_ID_UNUSED44 = 0xcd,
- DBG_BLOCK_ID_UNUSED45 = 0xce,
- DBG_BLOCK_ID_UNUSED46 = 0xcf,
- DBG_BLOCK_ID_TD10 = 0xd0,
- DBG_BLOCK_ID_TD11 = 0xd1,
- DBG_BLOCK_ID_TD12 = 0xd2,
- DBG_BLOCK_ID_TD13 = 0xd3,
- DBG_BLOCK_ID_TD14 = 0xd4,
- DBG_BLOCK_ID_TD15 = 0xd5,
- DBG_BLOCK_ID_TD16 = 0xd6,
- DBG_BLOCK_ID_TD17 = 0xd7,
- DBG_BLOCK_ID_TD18 = 0xd8,
- DBG_BLOCK_ID_TD19 = 0xd9,
- DBG_BLOCK_ID_TD1A = 0xda,
- DBG_BLOCK_ID_TD1B = 0xdb,
- DBG_BLOCK_ID_UNUSED47 = 0xdc,
- DBG_BLOCK_ID_UNUSED48 = 0xdd,
- DBG_BLOCK_ID_UNUSED49 = 0xde,
- DBG_BLOCK_ID_UNUSED50 = 0xdf,
- DBG_BLOCK_ID_MCD0 = 0xe0,
- DBG_BLOCK_ID_MCD1 = 0xe1,
- DBG_BLOCK_ID_MCD2 = 0xe2,
- DBG_BLOCK_ID_MCD3 = 0xe3,
- DBG_BLOCK_ID_MCD4 = 0xe4,
- DBG_BLOCK_ID_MCD5 = 0xe5,
- DBG_BLOCK_ID_UNUSED51 = 0xe6,
- DBG_BLOCK_ID_UNUSED52 = 0xe7,
-} DebugBlockId_OLD;
-typedef enum DebugBlockId_BY2 {
- DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
- DBG_BLOCK_ID_VMC_BY2 = 0x1,
- DBG_BLOCK_ID_CG_BY2 = 0x2,
- DBG_BLOCK_ID_GRBM_BY2 = 0x3,
- DBG_BLOCK_ID_CSC_BY2 = 0x4,
- DBG_BLOCK_ID_IH_BY2 = 0x5,
- DBG_BLOCK_ID_SQ_BY2 = 0x6,
- DBG_BLOCK_ID_GMCON_BY2 = 0x7,
- DBG_BLOCK_ID_DMA0_BY2 = 0x8,
- DBG_BLOCK_ID_SPIM_BY2 = 0x9,
- DBG_BLOCK_ID_SPIS_BY2 = 0xa,
- DBG_BLOCK_ID_PA0_BY2 = 0xb,
- DBG_BLOCK_ID_CP0_BY2 = 0xc,
- DBG_BLOCK_ID_CP2_BY2 = 0xd,
- DBG_BLOCK_ID_UVDU_BY2 = 0xe,
- DBG_BLOCK_ID_VCE_BY2 = 0xf,
- DBG_BLOCK_ID_VGT0_BY2 = 0x10,
- DBG_BLOCK_ID_IA_BY2 = 0x11,
- DBG_BLOCK_ID_SCT0_BY2 = 0x12,
- DBG_BLOCK_ID_SPM0_BY2 = 0x13,
- DBG_BLOCK_ID_TCAA_BY2 = 0x14,
- DBG_BLOCK_ID_TCCA_BY2 = 0x15,
- DBG_BLOCK_ID_MCC0_BY2 = 0x16,
- DBG_BLOCK_ID_MCC2_BY2 = 0x17,
- DBG_BLOCK_ID_SX0_BY2 = 0x18,
- DBG_BLOCK_ID_SX2_BY2 = 0x19,
- DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a,
- DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b,
- DBG_BLOCK_ID_PC0_BY2 = 0x1c,
- DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d,
- DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e,
- DBG_BLOCK_ID_MCB_BY2 = 0x1f,
- DBG_BLOCK_ID_SCB0_BY2 = 0x20,
- DBG_BLOCK_ID_UNUSED13_BY2 = 0x21,
- DBG_BLOCK_ID_SCF0_BY2 = 0x22,
- DBG_BLOCK_ID_UNUSED15_BY2 = 0x23,
- DBG_BLOCK_ID_BCI0_BY2 = 0x24,
- DBG_BLOCK_ID_BCI2_BY2 = 0x25,
- DBG_BLOCK_ID_UNUSED17_BY2 = 0x26,
- DBG_BLOCK_ID_UNUSED19_BY2 = 0x27,
- DBG_BLOCK_ID_CB00_BY2 = 0x28,
- DBG_BLOCK_ID_CB02_BY2 = 0x29,
- DBG_BLOCK_ID_CB04_BY2 = 0x2a,
- DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b,
- DBG_BLOCK_ID_CB10_BY2 = 0x2c,
- DBG_BLOCK_ID_CB12_BY2 = 0x2d,
- DBG_BLOCK_ID_CB14_BY2 = 0x2e,
- DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f,
- DBG_BLOCK_ID_TCP0_BY2 = 0x30,
- DBG_BLOCK_ID_TCP2_BY2 = 0x31,
- DBG_BLOCK_ID_TCP4_BY2 = 0x32,
- DBG_BLOCK_ID_TCP6_BY2 = 0x33,
- DBG_BLOCK_ID_TCP8_BY2 = 0x34,
- DBG_BLOCK_ID_TCP10_BY2 = 0x35,
- DBG_BLOCK_ID_TCP12_BY2 = 0x36,
- DBG_BLOCK_ID_TCP14_BY2 = 0x37,
- DBG_BLOCK_ID_TCP16_BY2 = 0x38,
- DBG_BLOCK_ID_TCP18_BY2 = 0x39,
- DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
- DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
- DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
- DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
- DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
- DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
- DBG_BLOCK_ID_DB00_BY2 = 0x40,
- DBG_BLOCK_ID_DB02_BY2 = 0x41,
- DBG_BLOCK_ID_DB04_BY2 = 0x42,
- DBG_BLOCK_ID_UNUSED28_BY2 = 0x43,
- DBG_BLOCK_ID_DB10_BY2 = 0x44,
- DBG_BLOCK_ID_DB12_BY2 = 0x45,
- DBG_BLOCK_ID_DB14_BY2 = 0x46,
- DBG_BLOCK_ID_UNUSED31_BY2 = 0x47,
- DBG_BLOCK_ID_TCC0_BY2 = 0x48,
- DBG_BLOCK_ID_TCC2_BY2 = 0x49,
- DBG_BLOCK_ID_TCC4_BY2 = 0x4a,
- DBG_BLOCK_ID_TCC6_BY2 = 0x4b,
- DBG_BLOCK_ID_SPS00_BY2 = 0x4c,
- DBG_BLOCK_ID_SPS02_BY2 = 0x4d,
- DBG_BLOCK_ID_SPS11_BY2 = 0x4e,
- DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f,
- DBG_BLOCK_ID_TA00_BY2 = 0x50,
- DBG_BLOCK_ID_TA02_BY2 = 0x51,
- DBG_BLOCK_ID_TA04_BY2 = 0x52,
- DBG_BLOCK_ID_TA06_BY2 = 0x53,
- DBG_BLOCK_ID_TA08_BY2 = 0x54,
- DBG_BLOCK_ID_TA0A_BY2 = 0x55,
- DBG_BLOCK_ID_UNUSED35_BY2 = 0x56,
- DBG_BLOCK_ID_UNUSED37_BY2 = 0x57,
- DBG_BLOCK_ID_TA10_BY2 = 0x58,
- DBG_BLOCK_ID_TA12_BY2 = 0x59,
- DBG_BLOCK_ID_TA14_BY2 = 0x5a,
- DBG_BLOCK_ID_TA16_BY2 = 0x5b,
- DBG_BLOCK_ID_TA18_BY2 = 0x5c,
- DBG_BLOCK_ID_TA1A_BY2 = 0x5d,
- DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e,
- DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f,
- DBG_BLOCK_ID_TD00_BY2 = 0x60,
- DBG_BLOCK_ID_TD02_BY2 = 0x61,
- DBG_BLOCK_ID_TD04_BY2 = 0x62,
- DBG_BLOCK_ID_TD06_BY2 = 0x63,
- DBG_BLOCK_ID_TD08_BY2 = 0x64,
- DBG_BLOCK_ID_TD0A_BY2 = 0x65,
- DBG_BLOCK_ID_UNUSED43_BY2 = 0x66,
- DBG_BLOCK_ID_UNUSED45_BY2 = 0x67,
- DBG_BLOCK_ID_TD10_BY2 = 0x68,
- DBG_BLOCK_ID_TD12_BY2 = 0x69,
- DBG_BLOCK_ID_TD14_BY2 = 0x6a,
- DBG_BLOCK_ID_TD16_BY2 = 0x6b,
- DBG_BLOCK_ID_TD18_BY2 = 0x6c,
- DBG_BLOCK_ID_TD1A_BY2 = 0x6d,
- DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e,
- DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f,
- DBG_BLOCK_ID_MCD0_BY2 = 0x70,
- DBG_BLOCK_ID_MCD2_BY2 = 0x71,
- DBG_BLOCK_ID_MCD4_BY2 = 0x72,
- DBG_BLOCK_ID_UNUSED51_BY2 = 0x73,
-} DebugBlockId_BY2;
-typedef enum DebugBlockId_BY4 {
- DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
- DBG_BLOCK_ID_CG_BY4 = 0x1,
- DBG_BLOCK_ID_CSC_BY4 = 0x2,
- DBG_BLOCK_ID_SQ_BY4 = 0x3,
- DBG_BLOCK_ID_DMA0_BY4 = 0x4,
- DBG_BLOCK_ID_SPIS_BY4 = 0x5,
- DBG_BLOCK_ID_CP0_BY4 = 0x6,
- DBG_BLOCK_ID_UVDU_BY4 = 0x7,
- DBG_BLOCK_ID_VGT0_BY4 = 0x8,
- DBG_BLOCK_ID_SCT0_BY4 = 0x9,
- DBG_BLOCK_ID_TCAA_BY4 = 0xa,
- DBG_BLOCK_ID_MCC0_BY4 = 0xb,
- DBG_BLOCK_ID_SX0_BY4 = 0xc,
- DBG_BLOCK_ID_UNUSED4_BY4 = 0xd,
- DBG_BLOCK_ID_PC0_BY4 = 0xe,
- DBG_BLOCK_ID_UNUSED10_BY4 = 0xf,
- DBG_BLOCK_ID_SCB0_BY4 = 0x10,
- DBG_BLOCK_ID_SCF0_BY4 = 0x11,
- DBG_BLOCK_ID_BCI0_BY4 = 0x12,
- DBG_BLOCK_ID_UNUSED17_BY4 = 0x13,
- DBG_BLOCK_ID_CB00_BY4 = 0x14,
- DBG_BLOCK_ID_CB04_BY4 = 0x15,
- DBG_BLOCK_ID_CB10_BY4 = 0x16,
- DBG_BLOCK_ID_CB14_BY4 = 0x17,
- DBG_BLOCK_ID_TCP0_BY4 = 0x18,
- DBG_BLOCK_ID_TCP4_BY4 = 0x19,
- DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
- DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
- DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
- DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
- DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
- DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
- DBG_BLOCK_ID_DB_BY4 = 0x20,
- DBG_BLOCK_ID_DB04_BY4 = 0x21,
- DBG_BLOCK_ID_DB10_BY4 = 0x22,
- DBG_BLOCK_ID_DB14_BY4 = 0x23,
- DBG_BLOCK_ID_TCC0_BY4 = 0x24,
- DBG_BLOCK_ID_TCC4_BY4 = 0x25,
- DBG_BLOCK_ID_SPS00_BY4 = 0x26,
- DBG_BLOCK_ID_SPS11_BY4 = 0x27,
- DBG_BLOCK_ID_TA00_BY4 = 0x28,
- DBG_BLOCK_ID_TA04_BY4 = 0x29,
- DBG_BLOCK_ID_TA08_BY4 = 0x2a,
- DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b,
- DBG_BLOCK_ID_TA10_BY4 = 0x2c,
- DBG_BLOCK_ID_TA14_BY4 = 0x2d,
- DBG_BLOCK_ID_TA18_BY4 = 0x2e,
- DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f,
- DBG_BLOCK_ID_TD00_BY4 = 0x30,
- DBG_BLOCK_ID_TD04_BY4 = 0x31,
- DBG_BLOCK_ID_TD08_BY4 = 0x32,
- DBG_BLOCK_ID_UNUSED43_BY4 = 0x33,
- DBG_BLOCK_ID_TD10_BY4 = 0x34,
- DBG_BLOCK_ID_TD14_BY4 = 0x35,
- DBG_BLOCK_ID_TD18_BY4 = 0x36,
- DBG_BLOCK_ID_UNUSED47_BY4 = 0x37,
- DBG_BLOCK_ID_MCD0_BY4 = 0x38,
- DBG_BLOCK_ID_MCD4_BY4 = 0x39,
-} DebugBlockId_BY4;
-typedef enum DebugBlockId_BY8 {
- DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
- DBG_BLOCK_ID_CSC_BY8 = 0x1,
- DBG_BLOCK_ID_DMA0_BY8 = 0x2,
- DBG_BLOCK_ID_CP0_BY8 = 0x3,
- DBG_BLOCK_ID_VGT0_BY8 = 0x4,
- DBG_BLOCK_ID_TCAA_BY8 = 0x5,
- DBG_BLOCK_ID_SX0_BY8 = 0x6,
- DBG_BLOCK_ID_PC0_BY8 = 0x7,
- DBG_BLOCK_ID_SCB0_BY8 = 0x8,
- DBG_BLOCK_ID_BCI0_BY8 = 0x9,
- DBG_BLOCK_ID_CB00_BY8 = 0xa,
- DBG_BLOCK_ID_CB10_BY8 = 0xb,
- DBG_BLOCK_ID_TCP0_BY8 = 0xc,
- DBG_BLOCK_ID_TCP8_BY8 = 0xd,
- DBG_BLOCK_ID_TCP16_BY8 = 0xe,
- DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
- DBG_BLOCK_ID_DB00_BY8 = 0x10,
- DBG_BLOCK_ID_DB10_BY8 = 0x11,
- DBG_BLOCK_ID_TCC0_BY8 = 0x12,
- DBG_BLOCK_ID_SPS00_BY8 = 0x13,
- DBG_BLOCK_ID_TA00_BY8 = 0x14,
- DBG_BLOCK_ID_TA08_BY8 = 0x15,
- DBG_BLOCK_ID_TA10_BY8 = 0x16,
- DBG_BLOCK_ID_TA18_BY8 = 0x17,
- DBG_BLOCK_ID_TD00_BY8 = 0x18,
- DBG_BLOCK_ID_TD08_BY8 = 0x19,
- DBG_BLOCK_ID_TD10_BY8 = 0x1a,
- DBG_BLOCK_ID_TD18_BY8 = 0x1b,
- DBG_BLOCK_ID_MCD0_BY8 = 0x1c,
-} DebugBlockId_BY8;
-typedef enum DebugBlockId_BY16 {
- DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
- DBG_BLOCK_ID_DMA0_BY16 = 0x1,
- DBG_BLOCK_ID_VGT0_BY16 = 0x2,
- DBG_BLOCK_ID_SX0_BY16 = 0x3,
- DBG_BLOCK_ID_SCB0_BY16 = 0x4,
- DBG_BLOCK_ID_CB00_BY16 = 0x5,
- DBG_BLOCK_ID_TCP0_BY16 = 0x6,
- DBG_BLOCK_ID_TCP16_BY16 = 0x7,
- DBG_BLOCK_ID_DB00_BY16 = 0x8,
- DBG_BLOCK_ID_TCC0_BY16 = 0x9,
- DBG_BLOCK_ID_TA00_BY16 = 0xa,
- DBG_BLOCK_ID_TA10_BY16 = 0xb,
- DBG_BLOCK_ID_TD00_BY16 = 0xc,
- DBG_BLOCK_ID_TD10_BY16 = 0xd,
- DBG_BLOCK_ID_MCD0_BY16 = 0xe,
-} DebugBlockId_BY16;
-typedef enum ColorTransform {
- DCC_CT_AUTO = 0x0,
- DCC_CT_NONE = 0x1,
- ABGR_TO_A_BG_G_RB = 0x2,
- BGRA_TO_BG_G_RB_A = 0x3,
-} ColorTransform;
-typedef enum CompareRef {
- REF_NEVER = 0x0,
- REF_LESS = 0x1,
- REF_EQUAL = 0x2,
- REF_LEQUAL = 0x3,
- REF_GREATER = 0x4,
- REF_NOTEQUAL = 0x5,
- REF_GEQUAL = 0x6,
- REF_ALWAYS = 0x7,
-} CompareRef;
-typedef enum ReadSize {
- READ_256_BITS = 0x0,
- READ_512_BITS = 0x1,
-} ReadSize;
-typedef enum DepthFormat {
- DEPTH_INVALID = 0x0,
- DEPTH_16 = 0x1,
- DEPTH_X8_24 = 0x2,
- DEPTH_8_24 = 0x3,
- DEPTH_X8_24_FLOAT = 0x4,
- DEPTH_8_24_FLOAT = 0x5,
- DEPTH_32_FLOAT = 0x6,
- DEPTH_X24_8_32_FLOAT = 0x7,
-} DepthFormat;
-typedef enum ZFormat {
- Z_INVALID = 0x0,
- Z_16 = 0x1,
- Z_24 = 0x2,
- Z_32_FLOAT = 0x3,
-} ZFormat;
-typedef enum StencilFormat {
- STENCIL_INVALID = 0x0,
- STENCIL_8 = 0x1,
-} StencilFormat;
-typedef enum CmaskMode {
- CMASK_CLEAR_NONE = 0x0,
- CMASK_CLEAR_ONE = 0x1,
- CMASK_CLEAR_ALL = 0x2,
- CMASK_ANY_EXPANDED = 0x3,
- CMASK_ALPHA0_FRAG1 = 0x4,
- CMASK_ALPHA0_FRAG2 = 0x5,
- CMASK_ALPHA0_FRAG4 = 0x6,
- CMASK_ALPHA0_FRAGS = 0x7,
- CMASK_ALPHA1_FRAG1 = 0x8,
- CMASK_ALPHA1_FRAG2 = 0x9,
- CMASK_ALPHA1_FRAG4 = 0xa,
- CMASK_ALPHA1_FRAGS = 0xb,
- CMASK_ALPHAX_FRAG1 = 0xc,
- CMASK_ALPHAX_FRAG2 = 0xd,
- CMASK_ALPHAX_FRAG4 = 0xe,
- CMASK_ALPHAX_FRAGS = 0xf,
-} CmaskMode;
-typedef enum QuadExportFormat {
- EXPORT_UNUSED = 0x0,
- EXPORT_32_R = 0x1,
- EXPORT_32_GR = 0x2,
- EXPORT_32_AR = 0x3,
- EXPORT_FP16_ABGR = 0x4,
- EXPORT_UNSIGNED16_ABGR = 0x5,
- EXPORT_SIGNED16_ABGR = 0x6,
- EXPORT_32_ABGR = 0x7,
-} QuadExportFormat;
-typedef enum QuadExportFormatOld {
- EXPORT_4P_32BPC_ABGR = 0x0,
- EXPORT_4P_16BPC_ABGR = 0x1,
- EXPORT_4P_32BPC_GR = 0x2,
- EXPORT_4P_32BPC_AR = 0x3,
- EXPORT_2P_32BPC_ABGR = 0x4,
- EXPORT_8P_32BPC_R = 0x5,
-} QuadExportFormatOld;
-typedef enum ColorFormat {
- COLOR_INVALID = 0x0,
- COLOR_8 = 0x1,
- COLOR_16 = 0x2,
- COLOR_8_8 = 0x3,
- COLOR_32 = 0x4,
- COLOR_16_16 = 0x5,
- COLOR_10_11_11 = 0x6,
- COLOR_11_11_10 = 0x7,
- COLOR_10_10_10_2 = 0x8,
- COLOR_2_10_10_10 = 0x9,
- COLOR_8_8_8_8 = 0xa,
- COLOR_32_32 = 0xb,
- COLOR_16_16_16_16 = 0xc,
- COLOR_RESERVED_13 = 0xd,
- COLOR_32_32_32_32 = 0xe,
- COLOR_RESERVED_15 = 0xf,
- COLOR_5_6_5 = 0x10,
- COLOR_1_5_5_5 = 0x11,
- COLOR_5_5_5_1 = 0x12,
- COLOR_4_4_4_4 = 0x13,
- COLOR_8_24 = 0x14,
- COLOR_24_8 = 0x15,
- COLOR_X24_8_32_FLOAT = 0x16,
- COLOR_RESERVED_23 = 0x17,
-} ColorFormat;
-typedef enum SurfaceFormat {
- FMT_INVALID = 0x0,
- FMT_8 = 0x1,
- FMT_16 = 0x2,
- FMT_8_8 = 0x3,
- FMT_32 = 0x4,
- FMT_16_16 = 0x5,
- FMT_10_11_11 = 0x6,
- FMT_11_11_10 = 0x7,
- FMT_10_10_10_2 = 0x8,
- FMT_2_10_10_10 = 0x9,
- FMT_8_8_8_8 = 0xa,
- FMT_32_32 = 0xb,
- FMT_16_16_16_16 = 0xc,
- FMT_32_32_32 = 0xd,
- FMT_32_32_32_32 = 0xe,
- FMT_RESERVED_4 = 0xf,
- FMT_5_6_5 = 0x10,
- FMT_1_5_5_5 = 0x11,
- FMT_5_5_5_1 = 0x12,
- FMT_4_4_4_4 = 0x13,
- FMT_8_24 = 0x14,
- FMT_24_8 = 0x15,
- FMT_X24_8_32_FLOAT = 0x16,
- FMT_RESERVED_33 = 0x17,
- FMT_11_11_10_FLOAT = 0x18,
- FMT_16_FLOAT = 0x19,
- FMT_32_FLOAT = 0x1a,
- FMT_16_16_FLOAT = 0x1b,
- FMT_8_24_FLOAT = 0x1c,
- FMT_24_8_FLOAT = 0x1d,
- FMT_32_32_FLOAT = 0x1e,
- FMT_10_11_11_FLOAT = 0x1f,
- FMT_16_16_16_16_FLOAT = 0x20,
- FMT_3_3_2 = 0x21,
- FMT_6_5_5 = 0x22,
- FMT_32_32_32_32_FLOAT = 0x23,
- FMT_RESERVED_36 = 0x24,
- FMT_1 = 0x25,
- FMT_1_REVERSED = 0x26,
- FMT_GB_GR = 0x27,
- FMT_BG_RG = 0x28,
- FMT_32_AS_8 = 0x29,
- FMT_32_AS_8_8 = 0x2a,
- FMT_5_9_9_9_SHAREDEXP = 0x2b,
- FMT_8_8_8 = 0x2c,
- FMT_16_16_16 = 0x2d,
- FMT_16_16_16_FLOAT = 0x2e,
- FMT_4_4 = 0x2f,
- FMT_32_32_32_FLOAT = 0x30,
- FMT_BC1 = 0x31,
- FMT_BC2 = 0x32,
- FMT_BC3 = 0x33,
- FMT_BC4 = 0x34,
- FMT_BC5 = 0x35,
- FMT_BC6 = 0x36,
- FMT_BC7 = 0x37,
- FMT_32_AS_32_32_32_32 = 0x38,
- FMT_APC3 = 0x39,
- FMT_APC4 = 0x3a,
- FMT_APC5 = 0x3b,
- FMT_APC6 = 0x3c,
- FMT_APC7 = 0x3d,
- FMT_CTX1 = 0x3e,
- FMT_RESERVED_63 = 0x3f,
-} SurfaceFormat;
-typedef enum BUF_DATA_FORMAT {
- BUF_DATA_FORMAT_INVALID = 0x0,
- BUF_DATA_FORMAT_8 = 0x1,
- BUF_DATA_FORMAT_16 = 0x2,
- BUF_DATA_FORMAT_8_8 = 0x3,
- BUF_DATA_FORMAT_32 = 0x4,
- BUF_DATA_FORMAT_16_16 = 0x5,
- BUF_DATA_FORMAT_10_11_11 = 0x6,
- BUF_DATA_FORMAT_11_11_10 = 0x7,
- BUF_DATA_FORMAT_10_10_10_2 = 0x8,
- BUF_DATA_FORMAT_2_10_10_10 = 0x9,
- BUF_DATA_FORMAT_8_8_8_8 = 0xa,
- BUF_DATA_FORMAT_32_32 = 0xb,
- BUF_DATA_FORMAT_16_16_16_16 = 0xc,
- BUF_DATA_FORMAT_32_32_32 = 0xd,
- BUF_DATA_FORMAT_32_32_32_32 = 0xe,
- BUF_DATA_FORMAT_RESERVED_15 = 0xf,
-} BUF_DATA_FORMAT;
-typedef enum IMG_DATA_FORMAT {
- IMG_DATA_FORMAT_INVALID = 0x0,
- IMG_DATA_FORMAT_8 = 0x1,
- IMG_DATA_FORMAT_16 = 0x2,
- IMG_DATA_FORMAT_8_8 = 0x3,
- IMG_DATA_FORMAT_32 = 0x4,
- IMG_DATA_FORMAT_16_16 = 0x5,
- IMG_DATA_FORMAT_10_11_11 = 0x6,
- IMG_DATA_FORMAT_11_11_10 = 0x7,
- IMG_DATA_FORMAT_10_10_10_2 = 0x8,
- IMG_DATA_FORMAT_2_10_10_10 = 0x9,
- IMG_DATA_FORMAT_8_8_8_8 = 0xa,
- IMG_DATA_FORMAT_32_32 = 0xb,
- IMG_DATA_FORMAT_16_16_16_16 = 0xc,
- IMG_DATA_FORMAT_32_32_32 = 0xd,
- IMG_DATA_FORMAT_32_32_32_32 = 0xe,
- IMG_DATA_FORMAT_RESERVED_15 = 0xf,
- IMG_DATA_FORMAT_5_6_5 = 0x10,
- IMG_DATA_FORMAT_1_5_5_5 = 0x11,
- IMG_DATA_FORMAT_5_5_5_1 = 0x12,
- IMG_DATA_FORMAT_4_4_4_4 = 0x13,
- IMG_DATA_FORMAT_8_24 = 0x14,
- IMG_DATA_FORMAT_24_8 = 0x15,
- IMG_DATA_FORMAT_X24_8_32 = 0x16,
- IMG_DATA_FORMAT_RESERVED_23 = 0x17,
- IMG_DATA_FORMAT_RESERVED_24 = 0x18,
- IMG_DATA_FORMAT_RESERVED_25 = 0x19,
- IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
- IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
- IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
- IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
- IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
- IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
- IMG_DATA_FORMAT_GB_GR = 0x20,
- IMG_DATA_FORMAT_BG_RG = 0x21,
- IMG_DATA_FORMAT_5_9_9_9 = 0x22,
- IMG_DATA_FORMAT_BC1 = 0x23,
- IMG_DATA_FORMAT_BC2 = 0x24,
- IMG_DATA_FORMAT_BC3 = 0x25,
- IMG_DATA_FORMAT_BC4 = 0x26,
- IMG_DATA_FORMAT_BC5 = 0x27,
- IMG_DATA_FORMAT_BC6 = 0x28,
- IMG_DATA_FORMAT_BC7 = 0x29,
- IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
- IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
- IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
- IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
- IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
- IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
- IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
- IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
- IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
- IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
- IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
- IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
- IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
- IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
- IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
- IMG_DATA_FORMAT_4_4 = 0x39,
- IMG_DATA_FORMAT_6_5_5 = 0x3a,
- IMG_DATA_FORMAT_1 = 0x3b,
- IMG_DATA_FORMAT_1_REVERSED = 0x3c,
- IMG_DATA_FORMAT_32_AS_8 = 0x3d,
- IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
- IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
-} IMG_DATA_FORMAT;
-typedef enum BUF_NUM_FORMAT {
- BUF_NUM_FORMAT_UNORM = 0x0,
- BUF_NUM_FORMAT_SNORM = 0x1,
- BUF_NUM_FORMAT_USCALED = 0x2,
- BUF_NUM_FORMAT_SSCALED = 0x3,
- BUF_NUM_FORMAT_UINT = 0x4,
- BUF_NUM_FORMAT_SINT = 0x5,
- BUF_NUM_FORMAT_RESERVED_6 = 0x6,
- BUF_NUM_FORMAT_FLOAT = 0x7,
-} BUF_NUM_FORMAT;
-typedef enum IMG_NUM_FORMAT {
- IMG_NUM_FORMAT_UNORM = 0x0,
- IMG_NUM_FORMAT_SNORM = 0x1,
- IMG_NUM_FORMAT_USCALED = 0x2,
- IMG_NUM_FORMAT_SSCALED = 0x3,
- IMG_NUM_FORMAT_UINT = 0x4,
- IMG_NUM_FORMAT_SINT = 0x5,
- IMG_NUM_FORMAT_RESERVED_6 = 0x6,
- IMG_NUM_FORMAT_FLOAT = 0x7,
- IMG_NUM_FORMAT_RESERVED_8 = 0x8,
- IMG_NUM_FORMAT_SRGB = 0x9,
- IMG_NUM_FORMAT_RESERVED_10 = 0xa,
- IMG_NUM_FORMAT_RESERVED_11 = 0xb,
- IMG_NUM_FORMAT_RESERVED_12 = 0xc,
- IMG_NUM_FORMAT_RESERVED_13 = 0xd,
- IMG_NUM_FORMAT_RESERVED_14 = 0xe,
- IMG_NUM_FORMAT_RESERVED_15 = 0xf,
-} IMG_NUM_FORMAT;
-typedef enum TileType {
- ARRAY_COLOR_TILE = 0x0,
- ARRAY_DEPTH_TILE = 0x1,
-} TileType;
-typedef enum NonDispTilingOrder {
- ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
- ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
-} NonDispTilingOrder;
-typedef enum MicroTileMode {
- ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
- ADDR_SURF_THIN_MICRO_TILING = 0x1,
- ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
- ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
- ADDR_SURF_THICK_MICRO_TILING = 0x4,
-} MicroTileMode;
-typedef enum TileSplit {
- ADDR_SURF_TILE_SPLIT_64B = 0x0,
- ADDR_SURF_TILE_SPLIT_128B = 0x1,
- ADDR_SURF_TILE_SPLIT_256B = 0x2,
- ADDR_SURF_TILE_SPLIT_512B = 0x3,
- ADDR_SURF_TILE_SPLIT_1KB = 0x4,
- ADDR_SURF_TILE_SPLIT_2KB = 0x5,
- ADDR_SURF_TILE_SPLIT_4KB = 0x6,
-} TileSplit;
-typedef enum SampleSplit {
- ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
- ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
- ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
- ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
-} SampleSplit;
-typedef enum PipeConfig {
- ADDR_SURF_P2 = 0x0,
- ADDR_SURF_P2_RESERVED0 = 0x1,
- ADDR_SURF_P2_RESERVED1 = 0x2,
- ADDR_SURF_P2_RESERVED2 = 0x3,
- ADDR_SURF_P4_8x16 = 0x4,
- ADDR_SURF_P4_16x16 = 0x5,
- ADDR_SURF_P4_16x32 = 0x6,
- ADDR_SURF_P4_32x32 = 0x7,
- ADDR_SURF_P8_16x16_8x16 = 0x8,
- ADDR_SURF_P8_16x32_8x16 = 0x9,
- ADDR_SURF_P8_32x32_8x16 = 0xa,
- ADDR_SURF_P8_16x32_16x16 = 0xb,
- ADDR_SURF_P8_32x32_16x16 = 0xc,
- ADDR_SURF_P8_32x32_16x32 = 0xd,
- ADDR_SURF_P8_32x64_32x32 = 0xe,
- ADDR_SURF_P8_RESERVED0 = 0xf,
- ADDR_SURF_P16_32x32_8x16 = 0x10,
- ADDR_SURF_P16_32x32_16x16 = 0x11,
-} PipeConfig;
-typedef enum NumBanks {
- ADDR_SURF_2_BANK = 0x0,
- ADDR_SURF_4_BANK = 0x1,
- ADDR_SURF_8_BANK = 0x2,
- ADDR_SURF_16_BANK = 0x3,
-} NumBanks;
-typedef enum BankWidth {
- ADDR_SURF_BANK_WIDTH_1 = 0x0,
- ADDR_SURF_BANK_WIDTH_2 = 0x1,
- ADDR_SURF_BANK_WIDTH_4 = 0x2,
- ADDR_SURF_BANK_WIDTH_8 = 0x3,
-} BankWidth;
-typedef enum BankHeight {
- ADDR_SURF_BANK_HEIGHT_1 = 0x0,
- ADDR_SURF_BANK_HEIGHT_2 = 0x1,
- ADDR_SURF_BANK_HEIGHT_4 = 0x2,
- ADDR_SURF_BANK_HEIGHT_8 = 0x3,
-} BankHeight;
-typedef enum BankWidthHeight {
- ADDR_SURF_BANK_WH_1 = 0x0,
- ADDR_SURF_BANK_WH_2 = 0x1,
- ADDR_SURF_BANK_WH_4 = 0x2,
- ADDR_SURF_BANK_WH_8 = 0x3,
-} BankWidthHeight;
-typedef enum MacroTileAspect {
- ADDR_SURF_MACRO_ASPECT_1 = 0x0,
- ADDR_SURF_MACRO_ASPECT_2 = 0x1,
- ADDR_SURF_MACRO_ASPECT_4 = 0x2,
- ADDR_SURF_MACRO_ASPECT_8 = 0x3,
-} MacroTileAspect;
-typedef enum GATCL1RequestType {
- GATCL1_TYPE_NORMAL = 0x0,
- GATCL1_TYPE_SHOOTDOWN = 0x1,
- GATCL1_TYPE_BYPASS = 0x2,
-} GATCL1RequestType;
-typedef enum TCC_CACHE_POLICIES {
- TCC_CACHE_POLICY_LRU = 0x0,
- TCC_CACHE_POLICY_STREAM = 0x1,
-} TCC_CACHE_POLICIES;
-typedef enum MTYPE {
- MTYPE_NC_NV = 0x0,
- MTYPE_NC = 0x1,
- MTYPE_CC = 0x2,
- MTYPE_UC = 0x3,
-} MTYPE;
-typedef enum PERFMON_COUNTER_MODE {
- PERFMON_COUNTER_MODE_ACCUM = 0x0,
- PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
- PERFMON_COUNTER_MODE_MAX = 0x2,
- PERFMON_COUNTER_MODE_DIRTY = 0x3,
- PERFMON_COUNTER_MODE_SAMPLE = 0x4,
- PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
- PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
- PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
- PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
- PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
- PERFMON_COUNTER_MODE_RESERVED = 0xf,
-} PERFMON_COUNTER_MODE;
-typedef enum PERFMON_SPM_MODE {
- PERFMON_SPM_MODE_OFF = 0x0,
- PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
- PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
- PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
- PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
- PERFMON_SPM_MODE_RESERVED_5 = 0x5,
- PERFMON_SPM_MODE_RESERVED_6 = 0x6,
- PERFMON_SPM_MODE_RESERVED_7 = 0x7,
- PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
- PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
- PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
-} PERFMON_SPM_MODE;
-typedef enum SurfaceTiling {
- ARRAY_LINEAR = 0x0,
- ARRAY_TILED = 0x1,
-} SurfaceTiling;
-typedef enum SurfaceArray {
- ARRAY_1D = 0x0,
- ARRAY_2D = 0x1,
- ARRAY_3D = 0x2,
- ARRAY_3D_SLICE = 0x3,
-} SurfaceArray;
-typedef enum ColorArray {
- ARRAY_2D_ALT_COLOR = 0x0,
- ARRAY_2D_COLOR = 0x1,
- ARRAY_3D_SLICE_COLOR = 0x3,
-} ColorArray;
-typedef enum DepthArray {
- ARRAY_2D_ALT_DEPTH = 0x0,
- ARRAY_2D_DEPTH = 0x1,
-} DepthArray;
-typedef enum ENUM_NUM_SIMD_PER_CU {
- NUM_SIMD_PER_CU = 0x4,
-} ENUM_NUM_SIMD_PER_CU;
-
-#endif /* OSS_2_4_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_enum.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_enum.h
deleted file mode 100644
index 627cff10f..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_enum.h
+++ /dev/null
@@ -1,1464 +0,0 @@
-/*
- * OSS_3_0_1 Register documentation
- *
- * Copyright (C) 2014 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef OSS_3_0_1_ENUM_H
-#define OSS_3_0_1_ENUM_H
-
-typedef enum IH_CLIENT_ID {
- DC_IH_SRC_ID_START = 0x1,
- DC_IH_SRC_ID_END = 0x1f,
- VGA_IH_SRC_ID_START = 0x20,
- VGA_IH_SRC_ID_END = 0x27,
- CAP_IH_SRC_ID_START = 0x28,
- CAP_IH_SRC_ID_END = 0x2f,
- VIP_IH_SRC_ID_START = 0x30,
- VIP_IH_SRC_ID_END = 0x3f,
- ROM_IH_SRC_ID_START = 0x40,
- ROM_IH_SRC_ID_END = 0x5d,
- BIF_IH_SRC_ID_START = 0x5e,
- SAM_IH_SRC_ID_START = 0x5f,
- SRBM_IH_SRC_ID_START = 0x60,
- SRBM_IH_SRC_ID_END = 0x67,
- UVD_IH_SRC_ID_START = 0x72,
- UVD_IH_SRC_ID_END = 0x85,
- VMC_IH_SRC_ID_START = 0x86,
- VMC_IH_SRC_ID_END = 0x8f,
- RLC_IH_SRC_ID_START = 0x90,
- RLC_IH_SRC_ID_END = 0xf3,
- PDMA_IH_SRC_ID_START = 0xf4,
- PDMA_IH_SRC_ID_END = 0xf7,
- CG_IH_SRC_ID_START = 0xf8,
- CG_IH_SRC_ID_END = 0xff,
-} IH_CLIENT_ID;
-typedef enum IH_PERF_SEL {
- IH_PERF_SEL_CYCLE = 0x0,
- IH_PERF_SEL_IDLE = 0x1,
- IH_PERF_SEL_INPUT_IDLE = 0x2,
- IH_PERF_SEL_CLIENT0_IH_STALL = 0x3,
- IH_PERF_SEL_CLIENT1_IH_STALL = 0x4,
- IH_PERF_SEL_CLIENT2_IH_STALL = 0x5,
- IH_PERF_SEL_CLIENT3_IH_STALL = 0x6,
- IH_PERF_SEL_CLIENT4_IH_STALL = 0x7,
- IH_PERF_SEL_CLIENT5_IH_STALL = 0x8,
- IH_PERF_SEL_CLIENT6_IH_STALL = 0x9,
- IH_PERF_SEL_CLIENT7_IH_STALL = 0xa,
- IH_PERF_SEL_RB_IDLE = 0xb,
- IH_PERF_SEL_RB_FULL = 0xc,
- IH_PERF_SEL_RB_OVERFLOW = 0xd,
- IH_PERF_SEL_RB_WPTR_WRITEBACK = 0xe,
- IH_PERF_SEL_RB_WPTR_WRAP = 0xf,
- IH_PERF_SEL_RB_RPTR_WRAP = 0x10,
- IH_PERF_SEL_MC_WR_IDLE = 0x11,
- IH_PERF_SEL_MC_WR_COUNT = 0x12,
- IH_PERF_SEL_MC_WR_STALL = 0x13,
- IH_PERF_SEL_MC_WR_CLEAN_PENDING = 0x14,
- IH_PERF_SEL_MC_WR_CLEAN_STALL = 0x15,
- IH_PERF_SEL_BIF_RISING = 0x16,
- IH_PERF_SEL_BIF_FALLING = 0x17,
- IH_PERF_SEL_CLIENT8_IH_STALL = 0x18,
- IH_PERF_SEL_CLIENT9_IH_STALL = 0x19,
- IH_PERF_SEL_CLIENT10_IH_STALL = 0x1a,
- IH_PERF_SEL_CLIENT11_IH_STALL = 0x1b,
- IH_PERF_SEL_CLIENT12_IH_STALL = 0x1c,
- IH_PERF_SEL_CLIENT13_IH_STALL = 0x1d,
- IH_PERF_SEL_CLIENT14_IH_STALL = 0x1e,
- IH_PERF_SEL_CLIENT15_IH_STALL = 0x1f,
- IH_PERF_SEL_CLIENT16_IH_STALL = 0x20,
- IH_PERF_SEL_CLIENT17_IH_STALL = 0x21,
- IH_PERF_SEL_CLIENT18_IH_STALL = 0x22,
- IH_PERF_SEL_CLIENT19_IH_STALL = 0x23,
- IH_PERF_SEL_CLIENT20_IH_STALL = 0x24,
- IH_PERF_SEL_CLIENT21_IH_STALL = 0x25,
- IH_PERF_SEL_CLIENT22_IH_STALL = 0x26,
- IH_PERF_SEL_CLIENT23_IH_STALL = 0x27,
-} IH_PERF_SEL;
-typedef enum SEM_PERF_SEL {
- SEM_PERF_SEL_CYCLE = 0x0,
- SEM_PERF_SEL_IDLE = 0x1,
- SEM_PERF_SEL_SDMA0_REQ_SIGNAL = 0x2,
- SEM_PERF_SEL_SDMA1_REQ_SIGNAL = 0x3,
- SEM_PERF_SEL_UVD_REQ_SIGNAL = 0x4,
- SEM_PERF_SEL_VCE0_REQ_SIGNAL = 0x5,
- SEM_PERF_SEL_ACP_REQ_SIGNAL = 0x6,
- SEM_PERF_SEL_ISP_REQ_SIGNAL = 0x7,
- SEM_PERF_SEL_VCE1_REQ_SIGNAL = 0x8,
- SEM_PERF_SEL_VP8_REQ_SIGNAL = 0x9,
- SEM_PERF_SEL_CPG_E0_REQ_SIGNAL = 0xa,
- SEM_PERF_SEL_CPG_E1_REQ_SIGNAL = 0xb,
- SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL = 0xc,
- SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL = 0xd,
- SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL = 0xe,
- SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL = 0xf,
- SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL = 0x10,
- SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL = 0x11,
- SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL = 0x12,
- SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL = 0x13,
- SEM_PERF_SEL_SDMA0_REQ_WAIT = 0x14,
- SEM_PERF_SEL_SDMA1_REQ_WAIT = 0x15,
- SEM_PERF_SEL_UVD_REQ_WAIT = 0x16,
- SEM_PERF_SEL_VCE0_REQ_WAIT = 0x17,
- SEM_PERF_SEL_ACP_REQ_WAIT = 0x18,
- SEM_PERF_SEL_ISP_REQ_WAIT = 0x19,
- SEM_PERF_SEL_VCE1_REQ_WAIT = 0x1a,
- SEM_PERF_SEL_VP8_REQ_WAIT = 0x1b,
- SEM_PERF_SEL_CPG_E0_REQ_WAIT = 0x1c,
- SEM_PERF_SEL_CPG_E1_REQ_WAIT = 0x1d,
- SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT = 0x1e,
- SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT = 0x1f,
- SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT = 0x20,
- SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT = 0x21,
- SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT = 0x22,
- SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT = 0x23,
- SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT = 0x24,
- SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT = 0x25,
- SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT = 0x26,
- SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT = 0x27,
- SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT = 0x28,
- SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT = 0x29,
- SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT = 0x2a,
- SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT = 0x2b,
- SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT = 0x2c,
- SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT = 0x2d,
- SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT = 0x2e,
- SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT = 0x2f,
- SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT = 0x30,
- SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT = 0x31,
- SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT = 0x32,
- SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT = 0x33,
- SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT = 0x34,
- SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT = 0x35,
- SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT = 0x36,
- SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT = 0x37,
- SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT = 0x38,
- SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT = 0x39,
- SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT = 0x3a,
- SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT = 0x3b,
- SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT = 0x3c,
- SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT = 0x3d,
- SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT = 0x3e,
- SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT = 0x3f,
- SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT = 0x40,
- SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT = 0x41,
- SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT = 0x42,
- SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT = 0x43,
- SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT = 0x44,
- SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT = 0x45,
- SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT = 0x46,
- SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT = 0x47,
- SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT = 0x48,
- SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT = 0x49,
- SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT = 0x4a,
- SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT = 0x4b,
- SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT = 0x4c,
- SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT = 0x4d,
- SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT = 0x4e,
- SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT = 0x4f,
- SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT = 0x50,
- SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT = 0x51,
- SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT = 0x52,
- SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT = 0x53,
- SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT = 0x54,
- SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT = 0x55,
- SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT = 0x56,
- SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT = 0x57,
- SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT = 0x58,
- SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT = 0x59,
- SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT = 0x5a,
- SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT = 0x5b,
- SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT = 0x5c,
- SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT = 0x5d,
- SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT = 0x5e,
- SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT = 0x5f,
- SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT = 0x60,
- SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT = 0x61,
- SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT = 0x62,
- SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT = 0x63,
- SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT = 0x64,
- SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT = 0x65,
- SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT = 0x66,
- SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT = 0x67,
- SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT = 0x68,
- SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT = 0x69,
- SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT = 0x6a,
- SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT = 0x6b,
- SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT = 0x6c,
- SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT = 0x6d,
- SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT = 0x6e,
- SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT = 0x6f,
- SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT = 0x70,
- SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT = 0x71,
- SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT = 0x72,
- SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT = 0x73,
- SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT = 0x74,
- SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT = 0x75,
- SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT = 0x76,
- SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT = 0x77,
- SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT = 0x78,
- SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT = 0x79,
- SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT = 0x7a,
- SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT = 0x7b,
- SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT = 0x7c,
- SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT = 0x7d,
- SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT = 0x7e,
- SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT = 0x7f,
- SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT = 0x80,
- SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT = 0x81,
- SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT = 0x82,
- SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT = 0x83,
- SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT = 0x84,
- SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT = 0x85,
- SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT = 0x86,
- SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT = 0x87,
- SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT = 0x88,
- SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT = 0x89,
- SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT = 0x8a,
- SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT = 0x8b,
- SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT = 0x8c,
- SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT = 0x8d,
- SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT = 0x8e,
- SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT = 0x8f,
- SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT = 0x90,
- SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT = 0x91,
- SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT = 0x92,
- SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT = 0x93,
- SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT = 0x94,
- SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT = 0x95,
- SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT = 0x96,
- SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT = 0x97,
- SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT = 0x98,
- SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT = 0x99,
- SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT = 0x9a,
- SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT = 0x9b,
- SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT = 0x9c,
- SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT = 0x9d,
- SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT = 0x9e,
- SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT = 0x9f,
- SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT = 0xa0,
- SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT = 0xa1,
- SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT = 0xa2,
- SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT = 0xa3,
- SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT = 0xa4,
- SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT = 0xa5,
- SEM_PERF_SEL_MC_RD_REQ = 0xa6,
- SEM_PERF_SEL_MC_RD_RET = 0xa7,
- SEM_PERF_SEL_MC_WR_REQ = 0xa8,
- SEM_PERF_SEL_MC_WR_RET = 0xa9,
- SEM_PERF_SEL_ATC_REQ = 0xaa,
- SEM_PERF_SEL_ATC_RET = 0xab,
- SEM_PERF_SEL_ATC_XNACK = 0xac,
- SEM_PERF_SEL_ATC_INVALIDATION = 0xad,
-} SEM_PERF_SEL;
-typedef enum SRBM_PERFCOUNT1_SEL {
- SRBM_PERF_SEL_COUNT = 0x0,
- SRBM_PERF_SEL_BIF_BUSY = 0x1,
- SRBM_PERF_SEL_SDMA0_BUSY = 0x3,
- SRBM_PERF_SEL_IH_BUSY = 0x4,
- SRBM_PERF_SEL_MCB_BUSY = 0x5,
- SRBM_PERF_SEL_MCB_NON_DISPLAY_BUSY = 0x6,
- SRBM_PERF_SEL_MCC_BUSY = 0x7,
- SRBM_PERF_SEL_MCD_BUSY = 0x8,
- SRBM_PERF_SEL_CHUB_BUSY = 0x9,
- SRBM_PERF_SEL_SEM_BUSY = 0xa,
- SRBM_PERF_SEL_UVD_BUSY = 0xb,
- SRBM_PERF_SEL_VMC_BUSY = 0xc,
- SRBM_PERF_SEL_ODE_BUSY = 0xd,
- SRBM_PERF_SEL_SDMA1_BUSY = 0xe,
- SRBM_PERF_SEL_SAMMSP_BUSY = 0xf,
- SRBM_PERF_SEL_VCE0_BUSY = 0x10,
- SRBM_PERF_SEL_XDMA_BUSY = 0x11,
- SRBM_PERF_SEL_ACP_BUSY = 0x12,
- SRBM_PERF_SEL_SDMA2_BUSY = 0x13,
- SRBM_PERF_SEL_SDMA3_BUSY = 0x14,
- RESERVED0 = 0x15,
- SRBM_PERF_SEL_VMC1_BUSY = 0x16,
- SRBM_PERF_SEL_ISP_BUSY = 0x17,
- SRBM_PERF_SEL_VCE1_BUSY = 0x18,
- SRBM_PERF_SEL_GCATCL2_BUSY = 0x19,
- SRBM_PERF_SEL_OSATCL2_BUSY = 0x1a,
- SRBM_PERF_SEL_VP8_BUSY = 0x1b,
-} SRBM_PERFCOUNT1_SEL;
-typedef enum SYS_GRBM_GFX_INDEX_SEL {
- GRBM_GFX_INDEX_BIF = 0x0,
- GRBM_GFX_INDEX_SDMA0 = 0x1,
- GRBM_GFX_INDEX_SDMA1 = 0x2,
- RESEVERED0 = 0x3,
- GRBM_GFX_INDEX_UVD = 0x4,
- GRBM_GFX_INDEX_VCE0 = 0x5,
- GRBM_GFX_INDEX_VCE1 = 0x6,
- GRBM_GFX_INDEX_ACP = 0x7,
- GRBM_GFX_INDEX_SMU = 0x8,
- GRBM_GFX_INDEX_SAMMSP = 0x9,
- GRBM_GFX_INDEX_VP8 = 0xa,
- GRBM_GFX_INDEX_ISP = 0xb,
- GRBM_GFX_INDEX_TST = 0xc,
- GRBM_GFX_INDEX_SDMA2 = 0xd,
- GRBM_GFX_INDEX_SDMA3 = 0xe,
-} SYS_GRBM_GFX_INDEX_SEL;
-typedef enum SRBM_GFX_CNTL_SEL {
- SRBM_GFX_CNTL_BIF = 0x0,
- SRBM_GFX_CNTL_SDMA0 = 0x1,
- SRBM_GFX_CNTL_SDMA1 = 0x2,
- SRBM_GFX_CNTL_GRBM = 0x3,
- SRBM_GFX_CNTL_UVD = 0x4,
- SRBM_GFX_CNTL_VCE0 = 0x5,
- SRBM_GFX_CNTL_VCE1 = 0x6,
- SRBM_GFX_CNTL_ACP = 0x7,
- SRBM_GFX_CNTL_SMU = 0x8,
- SRBM_GFX_CNTL_SAMMSP = 0x9,
- SRBM_GFX_CNTL_VP8 = 0xa,
- SRBM_GFX_CNTL_ISP = 0xb,
- SRBM_GFX_CNTL_TST = 0xc,
- SRBM_GFX_CNTL_SDMA2 = 0xd,
- SRBM_GFX_CNTL_SDMA3 = 0xe,
-} SRBM_GFX_CNTL_SEL;
-typedef enum SDMA_PERF_SEL {
- SDMA_PERF_SEL_CYCLE = 0x0,
- SDMA_PERF_SEL_IDLE = 0x1,
- SDMA_PERF_SEL_REG_IDLE = 0x2,
- SDMA_PERF_SEL_RB_EMPTY = 0x3,
- SDMA_PERF_SEL_RB_FULL = 0x4,
- SDMA_PERF_SEL_RB_WPTR_WRAP = 0x5,
- SDMA_PERF_SEL_RB_RPTR_WRAP = 0x6,
- SDMA_PERF_SEL_RB_WPTR_POLL_READ = 0x7,
- SDMA_PERF_SEL_RB_RPTR_WB = 0x8,
- SDMA_PERF_SEL_RB_CMD_IDLE = 0x9,
- SDMA_PERF_SEL_RB_CMD_FULL = 0xa,
- SDMA_PERF_SEL_IB_CMD_IDLE = 0xb,
- SDMA_PERF_SEL_IB_CMD_FULL = 0xc,
- SDMA_PERF_SEL_EX_IDLE = 0xd,
- SDMA_PERF_SEL_SRBM_REG_SEND = 0xe,
- SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0xf,
- SDMA_PERF_SEL_MC_WR_IDLE = 0x10,
- SDMA_PERF_SEL_MC_WR_COUNT = 0x11,
- SDMA_PERF_SEL_MC_RD_IDLE = 0x12,
- SDMA_PERF_SEL_MC_RD_COUNT = 0x13,
- SDMA_PERF_SEL_MC_RD_RET_STALL = 0x14,
- SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 0x15,
- SDMA_PERF_SEL_SEM_IDLE = 0x18,
- SDMA_PERF_SEL_SEM_REQ_STALL = 0x19,
- SDMA_PERF_SEL_SEM_REQ_COUNT = 0x1a,
- SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 0x1b,
- SDMA_PERF_SEL_SEM_RESP_FAIL = 0x1c,
- SDMA_PERF_SEL_SEM_RESP_PASS = 0x1d,
- SDMA_PERF_SEL_INT_IDLE = 0x1e,
- SDMA_PERF_SEL_INT_REQ_STALL = 0x1f,
- SDMA_PERF_SEL_INT_REQ_COUNT = 0x20,
- SDMA_PERF_SEL_INT_RESP_ACCEPTED = 0x21,
- SDMA_PERF_SEL_INT_RESP_RETRY = 0x22,
- SDMA_PERF_SEL_NUM_PACKET = 0x23,
- SDMA_PERF_SEL_CE_WREQ_IDLE = 0x25,
- SDMA_PERF_SEL_CE_WR_IDLE = 0x26,
- SDMA_PERF_SEL_CE_SPLIT_IDLE = 0x27,
- SDMA_PERF_SEL_CE_RREQ_IDLE = 0x28,
- SDMA_PERF_SEL_CE_OUT_IDLE = 0x29,
- SDMA_PERF_SEL_CE_IN_IDLE = 0x2a,
- SDMA_PERF_SEL_CE_DST_IDLE = 0x2b,
- SDMA_PERF_SEL_CE_AFIFO_FULL = 0x2e,
- SDMA_PERF_SEL_CE_INFO_FULL = 0x31,
- SDMA_PERF_SEL_CE_INFO1_FULL = 0x32,
- SDMA_PERF_SEL_CE_RD_STALL = 0x33,
- SDMA_PERF_SEL_CE_WR_STALL = 0x34,
- SDMA_PERF_SEL_GFX_SELECT = 0x35,
- SDMA_PERF_SEL_RLC0_SELECT = 0x36,
- SDMA_PERF_SEL_RLC1_SELECT = 0x37,
- SDMA_PERF_SEL_CTX_CHANGE = 0x38,
- SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 0x39,
- SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 0x3a,
- SDMA_PERF_SEL_DOORBELL = 0x3b,
- SDMA_PERF_SEL_RD_BA_RTR = 0x3c,
- SDMA_PERF_SEL_WR_BA_RTR = 0x3d,
- SDMA_PERF_SEL_F32_L1_WR_VLD = 0x3e,
- SDMA_PERF_SEL_CE_L1_WR_VLD = 0x3f,
- SDMA_PERF_SEL_CE_L1_STALL = 0x40,
- SDMA_PERF_SEL_SDMA_INVACK_NFLUSH = 0x41,
- SDMA_PERF_SEL_SDMA_INVACK_FLUSH = 0x42,
- SDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH = 0x43,
- SDMA_PERF_SEL_ATCL2_INVREQ_FLUSH = 0x44,
- SDMA_PERF_SEL_ATCL2_RET_XNACK = 0x45,
- SDMA_PERF_SEL_ATCL2_RET_ACK = 0x46,
- SDMA_PERF_SEL_ATCL2_FREE = 0x47,
- SDMA_PERF_SEL_SDMA_ATCL2_SEND = 0x48,
- SDMA_PERF_SEL_DMA_L1_WR_SEND = 0x49,
- SDMA_PERF_SEL_DMA_L1_RD_SEND = 0x4a,
- SDMA_PERF_SEL_DMA_MC_WR_SEND = 0x4b,
- SDMA_PERF_SEL_DMA_MC_RD_SEND = 0x4c,
- SDMA_PERF_SEL_L1_WR_FIFO_IDLE = 0x4d,
- SDMA_PERF_SEL_L1_RD_FIFO_IDLE = 0x4e,
- SDMA_PERF_SEL_L1_WRL2_IDLE = 0x4f,
- SDMA_PERF_SEL_L1_RDL2_IDLE = 0x50,
- SDMA_PERF_SEL_L1_WRMC_IDLE = 0x51,
- SDMA_PERF_SEL_L1_RDMC_IDLE = 0x52,
- SDMA_PERF_SEL_L1_WR_INV_IDLE = 0x53,
- SDMA_PERF_SEL_L1_RD_INV_IDLE = 0x54,
- SDMA_PERF_SEL_L1_WR_INV_EN = 0x55,
- SDMA_PERF_SEL_L1_RD_INV_EN = 0x56,
- SDMA_PERF_SEL_L1_WR_WAIT_INVADR = 0x57,
- SDMA_PERF_SEL_L1_RD_WAIT_INVADR = 0x58,
- SDMA_PERF_SEL_IS_INVREQ_ADDR_WR = 0x59,
- SDMA_PERF_SEL_IS_INVREQ_ADDR_RD = 0x5a,
- SDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT = 0x5b,
- SDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT = 0x5c,
- SDMA_PERF_SEL_L1_INV_MIDDLE = 0x5d,
-} SDMA_PERF_SEL;
-typedef enum DebugBlockId {
- DBG_BLOCK_ID_RESERVED = 0x0,
- DBG_BLOCK_ID_DBG = 0x1,
- DBG_BLOCK_ID_VMC = 0x2,
- DBG_BLOCK_ID_PDMA = 0x3,
- DBG_BLOCK_ID_CG = 0x4,
- DBG_BLOCK_ID_SRBM = 0x5,
- DBG_BLOCK_ID_GRBM = 0x6,
- DBG_BLOCK_ID_RLC = 0x7,
- DBG_BLOCK_ID_CSC = 0x8,
- DBG_BLOCK_ID_SEM = 0x9,
- DBG_BLOCK_ID_IH = 0xa,
- DBG_BLOCK_ID_SC = 0xb,
- DBG_BLOCK_ID_SQ = 0xc,
- DBG_BLOCK_ID_UVDU = 0xd,
- DBG_BLOCK_ID_SQA = 0xe,
- DBG_BLOCK_ID_SDMA0 = 0xf,
- DBG_BLOCK_ID_SDMA1 = 0x10,
- DBG_BLOCK_ID_SPIM = 0x11,
- DBG_BLOCK_ID_GDS = 0x12,
- DBG_BLOCK_ID_VC0 = 0x13,
- DBG_BLOCK_ID_VC1 = 0x14,
- DBG_BLOCK_ID_PA0 = 0x15,
- DBG_BLOCK_ID_PA1 = 0x16,
- DBG_BLOCK_ID_CP0 = 0x17,
- DBG_BLOCK_ID_CP1 = 0x18,
- DBG_BLOCK_ID_CP2 = 0x19,
- DBG_BLOCK_ID_XBR = 0x1a,
- DBG_BLOCK_ID_UVDM = 0x1b,
- DBG_BLOCK_ID_VGT0 = 0x1c,
- DBG_BLOCK_ID_VGT1 = 0x1d,
- DBG_BLOCK_ID_IA = 0x1e,
- DBG_BLOCK_ID_SXM0 = 0x1f,
- DBG_BLOCK_ID_SXM1 = 0x20,
- DBG_BLOCK_ID_SCT0 = 0x21,
- DBG_BLOCK_ID_SCT1 = 0x22,
- DBG_BLOCK_ID_SPM0 = 0x23,
- DBG_BLOCK_ID_SPM1 = 0x24,
- DBG_BLOCK_ID_UNUSED0 = 0x25,
- DBG_BLOCK_ID_UNUSED1 = 0x26,
- DBG_BLOCK_ID_TCAA = 0x27,
- DBG_BLOCK_ID_TCAB = 0x28,
- DBG_BLOCK_ID_TCCA = 0x29,
- DBG_BLOCK_ID_TCCB = 0x2a,
- DBG_BLOCK_ID_MCC0 = 0x2b,
- DBG_BLOCK_ID_MCC1 = 0x2c,
- DBG_BLOCK_ID_MCC2 = 0x2d,
- DBG_BLOCK_ID_MCC3 = 0x2e,
- DBG_BLOCK_ID_SXS0 = 0x2f,
- DBG_BLOCK_ID_SXS1 = 0x30,
- DBG_BLOCK_ID_SXS2 = 0x31,
- DBG_BLOCK_ID_SXS3 = 0x32,
- DBG_BLOCK_ID_SXS4 = 0x33,
- DBG_BLOCK_ID_SXS5 = 0x34,
- DBG_BLOCK_ID_SXS6 = 0x35,
- DBG_BLOCK_ID_SXS7 = 0x36,
- DBG_BLOCK_ID_SXS8 = 0x37,
- DBG_BLOCK_ID_SXS9 = 0x38,
- DBG_BLOCK_ID_BCI0 = 0x39,
- DBG_BLOCK_ID_BCI1 = 0x3a,
- DBG_BLOCK_ID_BCI2 = 0x3b,
- DBG_BLOCK_ID_BCI3 = 0x3c,
- DBG_BLOCK_ID_MCB = 0x3d,
- DBG_BLOCK_ID_UNUSED6 = 0x3e,
- DBG_BLOCK_ID_SQA00 = 0x3f,
- DBG_BLOCK_ID_SQA01 = 0x40,
- DBG_BLOCK_ID_SQA02 = 0x41,
- DBG_BLOCK_ID_SQA10 = 0x42,
- DBG_BLOCK_ID_SQA11 = 0x43,
- DBG_BLOCK_ID_SQA12 = 0x44,
- DBG_BLOCK_ID_UNUSED7 = 0x45,
- DBG_BLOCK_ID_UNUSED8 = 0x46,
- DBG_BLOCK_ID_SQB00 = 0x47,
- DBG_BLOCK_ID_SQB01 = 0x48,
- DBG_BLOCK_ID_SQB10 = 0x49,
- DBG_BLOCK_ID_SQB11 = 0x4a,
- DBG_BLOCK_ID_SQ00 = 0x4b,
- DBG_BLOCK_ID_SQ01 = 0x4c,
- DBG_BLOCK_ID_SQ10 = 0x4d,
- DBG_BLOCK_ID_SQ11 = 0x4e,
- DBG_BLOCK_ID_CB00 = 0x4f,
- DBG_BLOCK_ID_CB01 = 0x50,
- DBG_BLOCK_ID_CB02 = 0x51,
- DBG_BLOCK_ID_CB03 = 0x52,
- DBG_BLOCK_ID_CB04 = 0x53,
- DBG_BLOCK_ID_UNUSED9 = 0x54,
- DBG_BLOCK_ID_UNUSED10 = 0x55,
- DBG_BLOCK_ID_UNUSED11 = 0x56,
- DBG_BLOCK_ID_CB10 = 0x57,
- DBG_BLOCK_ID_CB11 = 0x58,
- DBG_BLOCK_ID_CB12 = 0x59,
- DBG_BLOCK_ID_CB13 = 0x5a,
- DBG_BLOCK_ID_CB14 = 0x5b,
- DBG_BLOCK_ID_UNUSED12 = 0x5c,
- DBG_BLOCK_ID_UNUSED13 = 0x5d,
- DBG_BLOCK_ID_UNUSED14 = 0x5e,
- DBG_BLOCK_ID_TCP0 = 0x5f,
- DBG_BLOCK_ID_TCP1 = 0x60,
- DBG_BLOCK_ID_TCP2 = 0x61,
- DBG_BLOCK_ID_TCP3 = 0x62,
- DBG_BLOCK_ID_TCP4 = 0x63,
- DBG_BLOCK_ID_TCP5 = 0x64,
- DBG_BLOCK_ID_TCP6 = 0x65,
- DBG_BLOCK_ID_TCP7 = 0x66,
- DBG_BLOCK_ID_TCP8 = 0x67,
- DBG_BLOCK_ID_TCP9 = 0x68,
- DBG_BLOCK_ID_TCP10 = 0x69,
- DBG_BLOCK_ID_TCP11 = 0x6a,
- DBG_BLOCK_ID_TCP12 = 0x6b,
- DBG_BLOCK_ID_TCP13 = 0x6c,
- DBG_BLOCK_ID_TCP14 = 0x6d,
- DBG_BLOCK_ID_TCP15 = 0x6e,
- DBG_BLOCK_ID_TCP16 = 0x6f,
- DBG_BLOCK_ID_TCP17 = 0x70,
- DBG_BLOCK_ID_TCP18 = 0x71,
- DBG_BLOCK_ID_TCP19 = 0x72,
- DBG_BLOCK_ID_TCP20 = 0x73,
- DBG_BLOCK_ID_TCP21 = 0x74,
- DBG_BLOCK_ID_TCP22 = 0x75,
- DBG_BLOCK_ID_TCP23 = 0x76,
- DBG_BLOCK_ID_TCP_RESERVED0 = 0x77,
- DBG_BLOCK_ID_TCP_RESERVED1 = 0x78,
- DBG_BLOCK_ID_TCP_RESERVED2 = 0x79,
- DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a,
- DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b,
- DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c,
- DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d,
- DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e,
- DBG_BLOCK_ID_DB00 = 0x7f,
- DBG_BLOCK_ID_DB01 = 0x80,
- DBG_BLOCK_ID_DB02 = 0x81,
- DBG_BLOCK_ID_DB03 = 0x82,
- DBG_BLOCK_ID_DB04 = 0x83,
- DBG_BLOCK_ID_UNUSED15 = 0x84,
- DBG_BLOCK_ID_UNUSED16 = 0x85,
- DBG_BLOCK_ID_UNUSED17 = 0x86,
- DBG_BLOCK_ID_DB10 = 0x87,
- DBG_BLOCK_ID_DB11 = 0x88,
- DBG_BLOCK_ID_DB12 = 0x89,
- DBG_BLOCK_ID_DB13 = 0x8a,
- DBG_BLOCK_ID_DB14 = 0x8b,
- DBG_BLOCK_ID_UNUSED18 = 0x8c,
- DBG_BLOCK_ID_UNUSED19 = 0x8d,
- DBG_BLOCK_ID_UNUSED20 = 0x8e,
- DBG_BLOCK_ID_TCC0 = 0x8f,
- DBG_BLOCK_ID_TCC1 = 0x90,
- DBG_BLOCK_ID_TCC2 = 0x91,
- DBG_BLOCK_ID_TCC3 = 0x92,
- DBG_BLOCK_ID_TCC4 = 0x93,
- DBG_BLOCK_ID_TCC5 = 0x94,
- DBG_BLOCK_ID_TCC6 = 0x95,
- DBG_BLOCK_ID_TCC7 = 0x96,
- DBG_BLOCK_ID_SPS00 = 0x97,
- DBG_BLOCK_ID_SPS01 = 0x98,
- DBG_BLOCK_ID_SPS02 = 0x99,
- DBG_BLOCK_ID_SPS10 = 0x9a,
- DBG_BLOCK_ID_SPS11 = 0x9b,
- DBG_BLOCK_ID_SPS12 = 0x9c,
- DBG_BLOCK_ID_UNUSED21 = 0x9d,
- DBG_BLOCK_ID_UNUSED22 = 0x9e,
- DBG_BLOCK_ID_TA00 = 0x9f,
- DBG_BLOCK_ID_TA01 = 0xa0,
- DBG_BLOCK_ID_TA02 = 0xa1,
- DBG_BLOCK_ID_TA03 = 0xa2,
- DBG_BLOCK_ID_TA04 = 0xa3,
- DBG_BLOCK_ID_TA05 = 0xa4,
- DBG_BLOCK_ID_TA06 = 0xa5,
- DBG_BLOCK_ID_TA07 = 0xa6,
- DBG_BLOCK_ID_TA08 = 0xa7,
- DBG_BLOCK_ID_TA09 = 0xa8,
- DBG_BLOCK_ID_TA0A = 0xa9,
- DBG_BLOCK_ID_TA0B = 0xaa,
- DBG_BLOCK_ID_UNUSED23 = 0xab,
- DBG_BLOCK_ID_UNUSED24 = 0xac,
- DBG_BLOCK_ID_UNUSED25 = 0xad,
- DBG_BLOCK_ID_UNUSED26 = 0xae,
- DBG_BLOCK_ID_TA10 = 0xaf,
- DBG_BLOCK_ID_TA11 = 0xb0,
- DBG_BLOCK_ID_TA12 = 0xb1,
- DBG_BLOCK_ID_TA13 = 0xb2,
- DBG_BLOCK_ID_TA14 = 0xb3,
- DBG_BLOCK_ID_TA15 = 0xb4,
- DBG_BLOCK_ID_TA16 = 0xb5,
- DBG_BLOCK_ID_TA17 = 0xb6,
- DBG_BLOCK_ID_TA18 = 0xb7,
- DBG_BLOCK_ID_TA19 = 0xb8,
- DBG_BLOCK_ID_TA1A = 0xb9,
- DBG_BLOCK_ID_TA1B = 0xba,
- DBG_BLOCK_ID_UNUSED27 = 0xbb,
- DBG_BLOCK_ID_UNUSED28 = 0xbc,
- DBG_BLOCK_ID_UNUSED29 = 0xbd,
- DBG_BLOCK_ID_UNUSED30 = 0xbe,
- DBG_BLOCK_ID_TD00 = 0xbf,
- DBG_BLOCK_ID_TD01 = 0xc0,
- DBG_BLOCK_ID_TD02 = 0xc1,
- DBG_BLOCK_ID_TD03 = 0xc2,
- DBG_BLOCK_ID_TD04 = 0xc3,
- DBG_BLOCK_ID_TD05 = 0xc4,
- DBG_BLOCK_ID_TD06 = 0xc5,
- DBG_BLOCK_ID_TD07 = 0xc6,
- DBG_BLOCK_ID_TD08 = 0xc7,
- DBG_BLOCK_ID_TD09 = 0xc8,
- DBG_BLOCK_ID_TD0A = 0xc9,
- DBG_BLOCK_ID_TD0B = 0xca,
- DBG_BLOCK_ID_UNUSED31 = 0xcb,
- DBG_BLOCK_ID_UNUSED32 = 0xcc,
- DBG_BLOCK_ID_UNUSED33 = 0xcd,
- DBG_BLOCK_ID_UNUSED34 = 0xce,
- DBG_BLOCK_ID_TD10 = 0xcf,
- DBG_BLOCK_ID_TD11 = 0xd0,
- DBG_BLOCK_ID_TD12 = 0xd1,
- DBG_BLOCK_ID_TD13 = 0xd2,
- DBG_BLOCK_ID_TD14 = 0xd3,
- DBG_BLOCK_ID_TD15 = 0xd4,
- DBG_BLOCK_ID_TD16 = 0xd5,
- DBG_BLOCK_ID_TD17 = 0xd6,
- DBG_BLOCK_ID_TD18 = 0xd7,
- DBG_BLOCK_ID_TD19 = 0xd8,
- DBG_BLOCK_ID_TD1A = 0xd9,
- DBG_BLOCK_ID_TD1B = 0xda,
- DBG_BLOCK_ID_UNUSED35 = 0xdb,
- DBG_BLOCK_ID_UNUSED36 = 0xdc,
- DBG_BLOCK_ID_UNUSED37 = 0xdd,
- DBG_BLOCK_ID_UNUSED38 = 0xde,
- DBG_BLOCK_ID_LDS00 = 0xdf,
- DBG_BLOCK_ID_LDS01 = 0xe0,
- DBG_BLOCK_ID_LDS02 = 0xe1,
- DBG_BLOCK_ID_LDS03 = 0xe2,
- DBG_BLOCK_ID_LDS04 = 0xe3,
- DBG_BLOCK_ID_LDS05 = 0xe4,
- DBG_BLOCK_ID_LDS06 = 0xe5,
- DBG_BLOCK_ID_LDS07 = 0xe6,
- DBG_BLOCK_ID_LDS08 = 0xe7,
- DBG_BLOCK_ID_LDS09 = 0xe8,
- DBG_BLOCK_ID_LDS0A = 0xe9,
- DBG_BLOCK_ID_LDS0B = 0xea,
- DBG_BLOCK_ID_UNUSED39 = 0xeb,
- DBG_BLOCK_ID_UNUSED40 = 0xec,
- DBG_BLOCK_ID_UNUSED41 = 0xed,
- DBG_BLOCK_ID_UNUSED42 = 0xee,
- DBG_BLOCK_ID_LDS10 = 0xef,
- DBG_BLOCK_ID_LDS11 = 0xf0,
- DBG_BLOCK_ID_LDS12 = 0xf1,
- DBG_BLOCK_ID_LDS13 = 0xf2,
- DBG_BLOCK_ID_LDS14 = 0xf3,
- DBG_BLOCK_ID_LDS15 = 0xf4,
- DBG_BLOCK_ID_LDS16 = 0xf5,
- DBG_BLOCK_ID_LDS17 = 0xf6,
- DBG_BLOCK_ID_LDS18 = 0xf7,
- DBG_BLOCK_ID_LDS19 = 0xf8,
- DBG_BLOCK_ID_LDS1A = 0xf9,
- DBG_BLOCK_ID_LDS1B = 0xfa,
- DBG_BLOCK_ID_UNUSED43 = 0xfb,
- DBG_BLOCK_ID_UNUSED44 = 0xfc,
- DBG_BLOCK_ID_UNUSED45 = 0xfd,
- DBG_BLOCK_ID_UNUSED46 = 0xfe,
-} DebugBlockId;
-typedef enum DebugBlockId_BY2 {
- DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
- DBG_BLOCK_ID_VMC_BY2 = 0x1,
- DBG_BLOCK_ID_UNUSED0_BY2 = 0x2,
- DBG_BLOCK_ID_GRBM_BY2 = 0x3,
- DBG_BLOCK_ID_CSC_BY2 = 0x4,
- DBG_BLOCK_ID_IH_BY2 = 0x5,
- DBG_BLOCK_ID_SQ_BY2 = 0x6,
- DBG_BLOCK_ID_UVD_BY2 = 0x7,
- DBG_BLOCK_ID_SDMA0_BY2 = 0x8,
- DBG_BLOCK_ID_SPIM_BY2 = 0x9,
- DBG_BLOCK_ID_VC0_BY2 = 0xa,
- DBG_BLOCK_ID_PA_BY2 = 0xb,
- DBG_BLOCK_ID_CP0_BY2 = 0xc,
- DBG_BLOCK_ID_CP2_BY2 = 0xd,
- DBG_BLOCK_ID_PC0_BY2 = 0xe,
- DBG_BLOCK_ID_BCI0_BY2 = 0xf,
- DBG_BLOCK_ID_SXM0_BY2 = 0x10,
- DBG_BLOCK_ID_SCT0_BY2 = 0x11,
- DBG_BLOCK_ID_SPM0_BY2 = 0x12,
- DBG_BLOCK_ID_BCI2_BY2 = 0x13,
- DBG_BLOCK_ID_TCA_BY2 = 0x14,
- DBG_BLOCK_ID_TCCA_BY2 = 0x15,
- DBG_BLOCK_ID_MCC_BY2 = 0x16,
- DBG_BLOCK_ID_MCC2_BY2 = 0x17,
- DBG_BLOCK_ID_MCD_BY2 = 0x18,
- DBG_BLOCK_ID_MCD2_BY2 = 0x19,
- DBG_BLOCK_ID_MCD4_BY2 = 0x1a,
- DBG_BLOCK_ID_MCB_BY2 = 0x1b,
- DBG_BLOCK_ID_SQA_BY2 = 0x1c,
- DBG_BLOCK_ID_SQA02_BY2 = 0x1d,
- DBG_BLOCK_ID_SQA11_BY2 = 0x1e,
- DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f,
- DBG_BLOCK_ID_SQB_BY2 = 0x20,
- DBG_BLOCK_ID_SQB10_BY2 = 0x21,
- DBG_BLOCK_ID_UNUSED10_BY2 = 0x22,
- DBG_BLOCK_ID_UNUSED12_BY2 = 0x23,
- DBG_BLOCK_ID_CB_BY2 = 0x24,
- DBG_BLOCK_ID_CB02_BY2 = 0x25,
- DBG_BLOCK_ID_CB10_BY2 = 0x26,
- DBG_BLOCK_ID_CB12_BY2 = 0x27,
- DBG_BLOCK_ID_SXS_BY2 = 0x28,
- DBG_BLOCK_ID_SXS2_BY2 = 0x29,
- DBG_BLOCK_ID_SXS4_BY2 = 0x2a,
- DBG_BLOCK_ID_SXS6_BY2 = 0x2b,
- DBG_BLOCK_ID_DB_BY2 = 0x2c,
- DBG_BLOCK_ID_DB02_BY2 = 0x2d,
- DBG_BLOCK_ID_DB10_BY2 = 0x2e,
- DBG_BLOCK_ID_DB12_BY2 = 0x2f,
- DBG_BLOCK_ID_TCP_BY2 = 0x30,
- DBG_BLOCK_ID_TCP2_BY2 = 0x31,
- DBG_BLOCK_ID_TCP4_BY2 = 0x32,
- DBG_BLOCK_ID_TCP6_BY2 = 0x33,
- DBG_BLOCK_ID_TCP8_BY2 = 0x34,
- DBG_BLOCK_ID_TCP10_BY2 = 0x35,
- DBG_BLOCK_ID_TCP12_BY2 = 0x36,
- DBG_BLOCK_ID_TCP14_BY2 = 0x37,
- DBG_BLOCK_ID_TCP16_BY2 = 0x38,
- DBG_BLOCK_ID_TCP18_BY2 = 0x39,
- DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
- DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
- DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
- DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
- DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
- DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
- DBG_BLOCK_ID_TCC_BY2 = 0x40,
- DBG_BLOCK_ID_TCC2_BY2 = 0x41,
- DBG_BLOCK_ID_TCC4_BY2 = 0x42,
- DBG_BLOCK_ID_TCC6_BY2 = 0x43,
- DBG_BLOCK_ID_SPS_BY2 = 0x44,
- DBG_BLOCK_ID_SPS02_BY2 = 0x45,
- DBG_BLOCK_ID_SPS11_BY2 = 0x46,
- DBG_BLOCK_ID_UNUSED14_BY2 = 0x47,
- DBG_BLOCK_ID_TA_BY2 = 0x48,
- DBG_BLOCK_ID_TA02_BY2 = 0x49,
- DBG_BLOCK_ID_TA04_BY2 = 0x4a,
- DBG_BLOCK_ID_TA06_BY2 = 0x4b,
- DBG_BLOCK_ID_TA08_BY2 = 0x4c,
- DBG_BLOCK_ID_TA0A_BY2 = 0x4d,
- DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e,
- DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f,
- DBG_BLOCK_ID_TA10_BY2 = 0x50,
- DBG_BLOCK_ID_TA12_BY2 = 0x51,
- DBG_BLOCK_ID_TA14_BY2 = 0x52,
- DBG_BLOCK_ID_TA16_BY2 = 0x53,
- DBG_BLOCK_ID_TA18_BY2 = 0x54,
- DBG_BLOCK_ID_TA1A_BY2 = 0x55,
- DBG_BLOCK_ID_UNUSED24_BY2 = 0x56,
- DBG_BLOCK_ID_UNUSED26_BY2 = 0x57,
- DBG_BLOCK_ID_TD_BY2 = 0x58,
- DBG_BLOCK_ID_TD02_BY2 = 0x59,
- DBG_BLOCK_ID_TD04_BY2 = 0x5a,
- DBG_BLOCK_ID_TD06_BY2 = 0x5b,
- DBG_BLOCK_ID_TD08_BY2 = 0x5c,
- DBG_BLOCK_ID_TD0A_BY2 = 0x5d,
- DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e,
- DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f,
- DBG_BLOCK_ID_TD10_BY2 = 0x60,
- DBG_BLOCK_ID_TD12_BY2 = 0x61,
- DBG_BLOCK_ID_TD14_BY2 = 0x62,
- DBG_BLOCK_ID_TD16_BY2 = 0x63,
- DBG_BLOCK_ID_TD18_BY2 = 0x64,
- DBG_BLOCK_ID_TD1A_BY2 = 0x65,
- DBG_BLOCK_ID_UNUSED32_BY2 = 0x66,
- DBG_BLOCK_ID_UNUSED34_BY2 = 0x67,
- DBG_BLOCK_ID_LDS_BY2 = 0x68,
- DBG_BLOCK_ID_LDS02_BY2 = 0x69,
- DBG_BLOCK_ID_LDS04_BY2 = 0x6a,
- DBG_BLOCK_ID_LDS06_BY2 = 0x6b,
- DBG_BLOCK_ID_LDS08_BY2 = 0x6c,
- DBG_BLOCK_ID_LDS0A_BY2 = 0x6d,
- DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e,
- DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f,
- DBG_BLOCK_ID_LDS10_BY2 = 0x70,
- DBG_BLOCK_ID_LDS12_BY2 = 0x71,
- DBG_BLOCK_ID_LDS14_BY2 = 0x72,
- DBG_BLOCK_ID_LDS16_BY2 = 0x73,
- DBG_BLOCK_ID_LDS18_BY2 = 0x74,
- DBG_BLOCK_ID_LDS1A_BY2 = 0x75,
- DBG_BLOCK_ID_UNUSED40_BY2 = 0x76,
- DBG_BLOCK_ID_UNUSED42_BY2 = 0x77,
-} DebugBlockId_BY2;
-typedef enum DebugBlockId_BY4 {
- DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
- DBG_BLOCK_ID_UNUSED0_BY4 = 0x1,
- DBG_BLOCK_ID_CSC_BY4 = 0x2,
- DBG_BLOCK_ID_SQ_BY4 = 0x3,
- DBG_BLOCK_ID_SDMA0_BY4 = 0x4,
- DBG_BLOCK_ID_VC0_BY4 = 0x5,
- DBG_BLOCK_ID_CP0_BY4 = 0x6,
- DBG_BLOCK_ID_UNUSED1_BY4 = 0x7,
- DBG_BLOCK_ID_SXM0_BY4 = 0x8,
- DBG_BLOCK_ID_SPM0_BY4 = 0x9,
- DBG_BLOCK_ID_TCAA_BY4 = 0xa,
- DBG_BLOCK_ID_MCC_BY4 = 0xb,
- DBG_BLOCK_ID_MCD_BY4 = 0xc,
- DBG_BLOCK_ID_MCD4_BY4 = 0xd,
- DBG_BLOCK_ID_SQA_BY4 = 0xe,
- DBG_BLOCK_ID_SQA11_BY4 = 0xf,
- DBG_BLOCK_ID_SQB_BY4 = 0x10,
- DBG_BLOCK_ID_UNUSED10_BY4 = 0x11,
- DBG_BLOCK_ID_CB_BY4 = 0x12,
- DBG_BLOCK_ID_CB10_BY4 = 0x13,
- DBG_BLOCK_ID_SXS_BY4 = 0x14,
- DBG_BLOCK_ID_SXS4_BY4 = 0x15,
- DBG_BLOCK_ID_DB_BY4 = 0x16,
- DBG_BLOCK_ID_DB10_BY4 = 0x17,
- DBG_BLOCK_ID_TCP_BY4 = 0x18,
- DBG_BLOCK_ID_TCP4_BY4 = 0x19,
- DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
- DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
- DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
- DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
- DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
- DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
- DBG_BLOCK_ID_TCC_BY4 = 0x20,
- DBG_BLOCK_ID_TCC4_BY4 = 0x21,
- DBG_BLOCK_ID_SPS_BY4 = 0x22,
- DBG_BLOCK_ID_SPS11_BY4 = 0x23,
- DBG_BLOCK_ID_TA_BY4 = 0x24,
- DBG_BLOCK_ID_TA04_BY4 = 0x25,
- DBG_BLOCK_ID_TA08_BY4 = 0x26,
- DBG_BLOCK_ID_UNUSED20_BY4 = 0x27,
- DBG_BLOCK_ID_TA10_BY4 = 0x28,
- DBG_BLOCK_ID_TA14_BY4 = 0x29,
- DBG_BLOCK_ID_TA18_BY4 = 0x2a,
- DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b,
- DBG_BLOCK_ID_TD_BY4 = 0x2c,
- DBG_BLOCK_ID_TD04_BY4 = 0x2d,
- DBG_BLOCK_ID_TD08_BY4 = 0x2e,
- DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f,
- DBG_BLOCK_ID_TD10_BY4 = 0x30,
- DBG_BLOCK_ID_TD14_BY4 = 0x31,
- DBG_BLOCK_ID_TD18_BY4 = 0x32,
- DBG_BLOCK_ID_UNUSED32_BY4 = 0x33,
- DBG_BLOCK_ID_LDS_BY4 = 0x34,
- DBG_BLOCK_ID_LDS04_BY4 = 0x35,
- DBG_BLOCK_ID_LDS08_BY4 = 0x36,
- DBG_BLOCK_ID_UNUSED36_BY4 = 0x37,
- DBG_BLOCK_ID_LDS10_BY4 = 0x38,
- DBG_BLOCK_ID_LDS14_BY4 = 0x39,
- DBG_BLOCK_ID_LDS18_BY4 = 0x3a,
- DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b,
-} DebugBlockId_BY4;
-typedef enum DebugBlockId_BY8 {
- DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
- DBG_BLOCK_ID_CSC_BY8 = 0x1,
- DBG_BLOCK_ID_SDMA0_BY8 = 0x2,
- DBG_BLOCK_ID_CP0_BY8 = 0x3,
- DBG_BLOCK_ID_SXM0_BY8 = 0x4,
- DBG_BLOCK_ID_TCA_BY8 = 0x5,
- DBG_BLOCK_ID_MCD_BY8 = 0x6,
- DBG_BLOCK_ID_SQA_BY8 = 0x7,
- DBG_BLOCK_ID_SQB_BY8 = 0x8,
- DBG_BLOCK_ID_CB_BY8 = 0x9,
- DBG_BLOCK_ID_SXS_BY8 = 0xa,
- DBG_BLOCK_ID_DB_BY8 = 0xb,
- DBG_BLOCK_ID_TCP_BY8 = 0xc,
- DBG_BLOCK_ID_TCP8_BY8 = 0xd,
- DBG_BLOCK_ID_TCP16_BY8 = 0xe,
- DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
- DBG_BLOCK_ID_TCC_BY8 = 0x10,
- DBG_BLOCK_ID_SPS_BY8 = 0x11,
- DBG_BLOCK_ID_TA_BY8 = 0x12,
- DBG_BLOCK_ID_TA08_BY8 = 0x13,
- DBG_BLOCK_ID_TA10_BY8 = 0x14,
- DBG_BLOCK_ID_TA18_BY8 = 0x15,
- DBG_BLOCK_ID_TD_BY8 = 0x16,
- DBG_BLOCK_ID_TD08_BY8 = 0x17,
- DBG_BLOCK_ID_TD10_BY8 = 0x18,
- DBG_BLOCK_ID_TD18_BY8 = 0x19,
- DBG_BLOCK_ID_LDS_BY8 = 0x1a,
- DBG_BLOCK_ID_LDS08_BY8 = 0x1b,
- DBG_BLOCK_ID_LDS10_BY8 = 0x1c,
- DBG_BLOCK_ID_LDS18_BY8 = 0x1d,
-} DebugBlockId_BY8;
-typedef enum DebugBlockId_BY16 {
- DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
- DBG_BLOCK_ID_SDMA0_BY16 = 0x1,
- DBG_BLOCK_ID_SXM_BY16 = 0x2,
- DBG_BLOCK_ID_MCD_BY16 = 0x3,
- DBG_BLOCK_ID_SQB_BY16 = 0x4,
- DBG_BLOCK_ID_SXS_BY16 = 0x5,
- DBG_BLOCK_ID_TCP_BY16 = 0x6,
- DBG_BLOCK_ID_TCP16_BY16 = 0x7,
- DBG_BLOCK_ID_TCC_BY16 = 0x8,
- DBG_BLOCK_ID_TA_BY16 = 0x9,
- DBG_BLOCK_ID_TA10_BY16 = 0xa,
- DBG_BLOCK_ID_TD_BY16 = 0xb,
- DBG_BLOCK_ID_TD10_BY16 = 0xc,
- DBG_BLOCK_ID_LDS_BY16 = 0xd,
- DBG_BLOCK_ID_LDS10_BY16 = 0xe,
-} DebugBlockId_BY16;
-typedef enum SurfaceEndian {
- ENDIAN_NONE = 0x0,
- ENDIAN_8IN16 = 0x1,
- ENDIAN_8IN32 = 0x2,
- ENDIAN_8IN64 = 0x3,
-} SurfaceEndian;
-typedef enum ArrayMode {
- ARRAY_LINEAR_GENERAL = 0x0,
- ARRAY_LINEAR_ALIGNED = 0x1,
- ARRAY_1D_TILED_THIN1 = 0x2,
- ARRAY_1D_TILED_THICK = 0x3,
- ARRAY_2D_TILED_THIN1 = 0x4,
- ARRAY_PRT_TILED_THIN1 = 0x5,
- ARRAY_PRT_2D_TILED_THIN1 = 0x6,
- ARRAY_2D_TILED_THICK = 0x7,
- ARRAY_2D_TILED_XTHICK = 0x8,
- ARRAY_PRT_TILED_THICK = 0x9,
- ARRAY_PRT_2D_TILED_THICK = 0xa,
- ARRAY_PRT_3D_TILED_THIN1 = 0xb,
- ARRAY_3D_TILED_THIN1 = 0xc,
- ARRAY_3D_TILED_THICK = 0xd,
- ARRAY_3D_TILED_XTHICK = 0xe,
- ARRAY_PRT_3D_TILED_THICK = 0xf,
-} ArrayMode;
-typedef enum PipeTiling {
- CONFIG_1_PIPE = 0x0,
- CONFIG_2_PIPE = 0x1,
- CONFIG_4_PIPE = 0x2,
- CONFIG_8_PIPE = 0x3,
-} PipeTiling;
-typedef enum BankTiling {
- CONFIG_4_BANK = 0x0,
- CONFIG_8_BANK = 0x1,
-} BankTiling;
-typedef enum GroupInterleave {
- CONFIG_256B_GROUP = 0x0,
- CONFIG_512B_GROUP = 0x1,
-} GroupInterleave;
-typedef enum RowTiling {
- CONFIG_1KB_ROW = 0x0,
- CONFIG_2KB_ROW = 0x1,
- CONFIG_4KB_ROW = 0x2,
- CONFIG_8KB_ROW = 0x3,
- CONFIG_1KB_ROW_OPT = 0x4,
- CONFIG_2KB_ROW_OPT = 0x5,
- CONFIG_4KB_ROW_OPT = 0x6,
- CONFIG_8KB_ROW_OPT = 0x7,
-} RowTiling;
-typedef enum BankSwapBytes {
- CONFIG_128B_SWAPS = 0x0,
- CONFIG_256B_SWAPS = 0x1,
- CONFIG_512B_SWAPS = 0x2,
- CONFIG_1KB_SWAPS = 0x3,
-} BankSwapBytes;
-typedef enum SampleSplitBytes {
- CONFIG_1KB_SPLIT = 0x0,
- CONFIG_2KB_SPLIT = 0x1,
- CONFIG_4KB_SPLIT = 0x2,
- CONFIG_8KB_SPLIT = 0x3,
-} SampleSplitBytes;
-typedef enum NumPipes {
- ADDR_CONFIG_1_PIPE = 0x0,
- ADDR_CONFIG_2_PIPE = 0x1,
- ADDR_CONFIG_4_PIPE = 0x2,
- ADDR_CONFIG_8_PIPE = 0x3,
-} NumPipes;
-typedef enum PipeInterleaveSize {
- ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
- ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
-} PipeInterleaveSize;
-typedef enum BankInterleaveSize {
- ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
- ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
- ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
- ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
-} BankInterleaveSize;
-typedef enum NumShaderEngines {
- ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
- ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
-} NumShaderEngines;
-typedef enum ShaderEngineTileSize {
- ADDR_CONFIG_SE_TILE_16 = 0x0,
- ADDR_CONFIG_SE_TILE_32 = 0x1,
-} ShaderEngineTileSize;
-typedef enum NumGPUs {
- ADDR_CONFIG_1_GPU = 0x0,
- ADDR_CONFIG_2_GPU = 0x1,
- ADDR_CONFIG_4_GPU = 0x2,
-} NumGPUs;
-typedef enum MultiGPUTileSize {
- ADDR_CONFIG_GPU_TILE_16 = 0x0,
- ADDR_CONFIG_GPU_TILE_32 = 0x1,
- ADDR_CONFIG_GPU_TILE_64 = 0x2,
- ADDR_CONFIG_GPU_TILE_128 = 0x3,
-} MultiGPUTileSize;
-typedef enum RowSize {
- ADDR_CONFIG_1KB_ROW = 0x0,
- ADDR_CONFIG_2KB_ROW = 0x1,
- ADDR_CONFIG_4KB_ROW = 0x2,
-} RowSize;
-typedef enum NumLowerPipes {
- ADDR_CONFIG_1_LOWER_PIPES = 0x0,
- ADDR_CONFIG_2_LOWER_PIPES = 0x1,
-} NumLowerPipes;
-typedef enum ColorTransform {
- DCC_CT_AUTO = 0x0,
- DCC_CT_NONE = 0x1,
- ABGR_TO_A_BG_G_RB = 0x2,
- BGRA_TO_BG_G_RB_A = 0x3,
-} ColorTransform;
-typedef enum CompareRef {
- REF_NEVER = 0x0,
- REF_LESS = 0x1,
- REF_EQUAL = 0x2,
- REF_LEQUAL = 0x3,
- REF_GREATER = 0x4,
- REF_NOTEQUAL = 0x5,
- REF_GEQUAL = 0x6,
- REF_ALWAYS = 0x7,
-} CompareRef;
-typedef enum ReadSize {
- READ_256_BITS = 0x0,
- READ_512_BITS = 0x1,
-} ReadSize;
-typedef enum DepthFormat {
- DEPTH_INVALID = 0x0,
- DEPTH_16 = 0x1,
- DEPTH_X8_24 = 0x2,
- DEPTH_8_24 = 0x3,
- DEPTH_X8_24_FLOAT = 0x4,
- DEPTH_8_24_FLOAT = 0x5,
- DEPTH_32_FLOAT = 0x6,
- DEPTH_X24_8_32_FLOAT = 0x7,
-} DepthFormat;
-typedef enum ZFormat {
- Z_INVALID = 0x0,
- Z_16 = 0x1,
- Z_24 = 0x2,
- Z_32_FLOAT = 0x3,
-} ZFormat;
-typedef enum StencilFormat {
- STENCIL_INVALID = 0x0,
- STENCIL_8 = 0x1,
-} StencilFormat;
-typedef enum CmaskMode {
- CMASK_CLEAR_NONE = 0x0,
- CMASK_CLEAR_ONE = 0x1,
- CMASK_CLEAR_ALL = 0x2,
- CMASK_ANY_EXPANDED = 0x3,
- CMASK_ALPHA0_FRAG1 = 0x4,
- CMASK_ALPHA0_FRAG2 = 0x5,
- CMASK_ALPHA0_FRAG4 = 0x6,
- CMASK_ALPHA0_FRAGS = 0x7,
- CMASK_ALPHA1_FRAG1 = 0x8,
- CMASK_ALPHA1_FRAG2 = 0x9,
- CMASK_ALPHA1_FRAG4 = 0xa,
- CMASK_ALPHA1_FRAGS = 0xb,
- CMASK_ALPHAX_FRAG1 = 0xc,
- CMASK_ALPHAX_FRAG2 = 0xd,
- CMASK_ALPHAX_FRAG4 = 0xe,
- CMASK_ALPHAX_FRAGS = 0xf,
-} CmaskMode;
-typedef enum QuadExportFormat {
- EXPORT_UNUSED = 0x0,
- EXPORT_32_R = 0x1,
- EXPORT_32_GR = 0x2,
- EXPORT_32_AR = 0x3,
- EXPORT_FP16_ABGR = 0x4,
- EXPORT_UNSIGNED16_ABGR = 0x5,
- EXPORT_SIGNED16_ABGR = 0x6,
- EXPORT_32_ABGR = 0x7,
-} QuadExportFormat;
-typedef enum QuadExportFormatOld {
- EXPORT_4P_32BPC_ABGR = 0x0,
- EXPORT_4P_16BPC_ABGR = 0x1,
- EXPORT_4P_32BPC_GR = 0x2,
- EXPORT_4P_32BPC_AR = 0x3,
- EXPORT_2P_32BPC_ABGR = 0x4,
- EXPORT_8P_32BPC_R = 0x5,
-} QuadExportFormatOld;
-typedef enum ColorFormat {
- COLOR_INVALID = 0x0,
- COLOR_8 = 0x1,
- COLOR_16 = 0x2,
- COLOR_8_8 = 0x3,
- COLOR_32 = 0x4,
- COLOR_16_16 = 0x5,
- COLOR_10_11_11 = 0x6,
- COLOR_11_11_10 = 0x7,
- COLOR_10_10_10_2 = 0x8,
- COLOR_2_10_10_10 = 0x9,
- COLOR_8_8_8_8 = 0xa,
- COLOR_32_32 = 0xb,
- COLOR_16_16_16_16 = 0xc,
- COLOR_RESERVED_13 = 0xd,
- COLOR_32_32_32_32 = 0xe,
- COLOR_RESERVED_15 = 0xf,
- COLOR_5_6_5 = 0x10,
- COLOR_1_5_5_5 = 0x11,
- COLOR_5_5_5_1 = 0x12,
- COLOR_4_4_4_4 = 0x13,
- COLOR_8_24 = 0x14,
- COLOR_24_8 = 0x15,
- COLOR_X24_8_32_FLOAT = 0x16,
- COLOR_RESERVED_23 = 0x17,
-} ColorFormat;
-typedef enum SurfaceFormat {
- FMT_INVALID = 0x0,
- FMT_8 = 0x1,
- FMT_16 = 0x2,
- FMT_8_8 = 0x3,
- FMT_32 = 0x4,
- FMT_16_16 = 0x5,
- FMT_10_11_11 = 0x6,
- FMT_11_11_10 = 0x7,
- FMT_10_10_10_2 = 0x8,
- FMT_2_10_10_10 = 0x9,
- FMT_8_8_8_8 = 0xa,
- FMT_32_32 = 0xb,
- FMT_16_16_16_16 = 0xc,
- FMT_32_32_32 = 0xd,
- FMT_32_32_32_32 = 0xe,
- FMT_RESERVED_4 = 0xf,
- FMT_5_6_5 = 0x10,
- FMT_1_5_5_5 = 0x11,
- FMT_5_5_5_1 = 0x12,
- FMT_4_4_4_4 = 0x13,
- FMT_8_24 = 0x14,
- FMT_24_8 = 0x15,
- FMT_X24_8_32_FLOAT = 0x16,
- FMT_RESERVED_33 = 0x17,
- FMT_11_11_10_FLOAT = 0x18,
- FMT_16_FLOAT = 0x19,
- FMT_32_FLOAT = 0x1a,
- FMT_16_16_FLOAT = 0x1b,
- FMT_8_24_FLOAT = 0x1c,
- FMT_24_8_FLOAT = 0x1d,
- FMT_32_32_FLOAT = 0x1e,
- FMT_10_11_11_FLOAT = 0x1f,
- FMT_16_16_16_16_FLOAT = 0x20,
- FMT_3_3_2 = 0x21,
- FMT_6_5_5 = 0x22,
- FMT_32_32_32_32_FLOAT = 0x23,
- FMT_RESERVED_36 = 0x24,
- FMT_1 = 0x25,
- FMT_1_REVERSED = 0x26,
- FMT_GB_GR = 0x27,
- FMT_BG_RG = 0x28,
- FMT_32_AS_8 = 0x29,
- FMT_32_AS_8_8 = 0x2a,
- FMT_5_9_9_9_SHAREDEXP = 0x2b,
- FMT_8_8_8 = 0x2c,
- FMT_16_16_16 = 0x2d,
- FMT_16_16_16_FLOAT = 0x2e,
- FMT_4_4 = 0x2f,
- FMT_32_32_32_FLOAT = 0x30,
- FMT_BC1 = 0x31,
- FMT_BC2 = 0x32,
- FMT_BC3 = 0x33,
- FMT_BC4 = 0x34,
- FMT_BC5 = 0x35,
- FMT_BC6 = 0x36,
- FMT_BC7 = 0x37,
- FMT_32_AS_32_32_32_32 = 0x38,
- FMT_APC3 = 0x39,
- FMT_APC4 = 0x3a,
- FMT_APC5 = 0x3b,
- FMT_APC6 = 0x3c,
- FMT_APC7 = 0x3d,
- FMT_CTX1 = 0x3e,
- FMT_RESERVED_63 = 0x3f,
-} SurfaceFormat;
-typedef enum BUF_DATA_FORMAT {
- BUF_DATA_FORMAT_INVALID = 0x0,
- BUF_DATA_FORMAT_8 = 0x1,
- BUF_DATA_FORMAT_16 = 0x2,
- BUF_DATA_FORMAT_8_8 = 0x3,
- BUF_DATA_FORMAT_32 = 0x4,
- BUF_DATA_FORMAT_16_16 = 0x5,
- BUF_DATA_FORMAT_10_11_11 = 0x6,
- BUF_DATA_FORMAT_11_11_10 = 0x7,
- BUF_DATA_FORMAT_10_10_10_2 = 0x8,
- BUF_DATA_FORMAT_2_10_10_10 = 0x9,
- BUF_DATA_FORMAT_8_8_8_8 = 0xa,
- BUF_DATA_FORMAT_32_32 = 0xb,
- BUF_DATA_FORMAT_16_16_16_16 = 0xc,
- BUF_DATA_FORMAT_32_32_32 = 0xd,
- BUF_DATA_FORMAT_32_32_32_32 = 0xe,
- BUF_DATA_FORMAT_RESERVED_15 = 0xf,
-} BUF_DATA_FORMAT;
-typedef enum IMG_DATA_FORMAT {
- IMG_DATA_FORMAT_INVALID = 0x0,
- IMG_DATA_FORMAT_8 = 0x1,
- IMG_DATA_FORMAT_16 = 0x2,
- IMG_DATA_FORMAT_8_8 = 0x3,
- IMG_DATA_FORMAT_32 = 0x4,
- IMG_DATA_FORMAT_16_16 = 0x5,
- IMG_DATA_FORMAT_10_11_11 = 0x6,
- IMG_DATA_FORMAT_11_11_10 = 0x7,
- IMG_DATA_FORMAT_10_10_10_2 = 0x8,
- IMG_DATA_FORMAT_2_10_10_10 = 0x9,
- IMG_DATA_FORMAT_8_8_8_8 = 0xa,
- IMG_DATA_FORMAT_32_32 = 0xb,
- IMG_DATA_FORMAT_16_16_16_16 = 0xc,
- IMG_DATA_FORMAT_32_32_32 = 0xd,
- IMG_DATA_FORMAT_32_32_32_32 = 0xe,
- IMG_DATA_FORMAT_RESERVED_15 = 0xf,
- IMG_DATA_FORMAT_5_6_5 = 0x10,
- IMG_DATA_FORMAT_1_5_5_5 = 0x11,
- IMG_DATA_FORMAT_5_5_5_1 = 0x12,
- IMG_DATA_FORMAT_4_4_4_4 = 0x13,
- IMG_DATA_FORMAT_8_24 = 0x14,
- IMG_DATA_FORMAT_24_8 = 0x15,
- IMG_DATA_FORMAT_X24_8_32 = 0x16,
- IMG_DATA_FORMAT_RESERVED_23 = 0x17,
- IMG_DATA_FORMAT_RESERVED_24 = 0x18,
- IMG_DATA_FORMAT_RESERVED_25 = 0x19,
- IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
- IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
- IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
- IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
- IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
- IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
- IMG_DATA_FORMAT_GB_GR = 0x20,
- IMG_DATA_FORMAT_BG_RG = 0x21,
- IMG_DATA_FORMAT_5_9_9_9 = 0x22,
- IMG_DATA_FORMAT_BC1 = 0x23,
- IMG_DATA_FORMAT_BC2 = 0x24,
- IMG_DATA_FORMAT_BC3 = 0x25,
- IMG_DATA_FORMAT_BC4 = 0x26,
- IMG_DATA_FORMAT_BC5 = 0x27,
- IMG_DATA_FORMAT_BC6 = 0x28,
- IMG_DATA_FORMAT_BC7 = 0x29,
- IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
- IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
- IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
- IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
- IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
- IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
- IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
- IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
- IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
- IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
- IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
- IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
- IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
- IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
- IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
- IMG_DATA_FORMAT_4_4 = 0x39,
- IMG_DATA_FORMAT_6_5_5 = 0x3a,
- IMG_DATA_FORMAT_1 = 0x3b,
- IMG_DATA_FORMAT_1_REVERSED = 0x3c,
- IMG_DATA_FORMAT_32_AS_8 = 0x3d,
- IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
- IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
-} IMG_DATA_FORMAT;
-typedef enum BUF_NUM_FORMAT {
- BUF_NUM_FORMAT_UNORM = 0x0,
- BUF_NUM_FORMAT_SNORM = 0x1,
- BUF_NUM_FORMAT_USCALED = 0x2,
- BUF_NUM_FORMAT_SSCALED = 0x3,
- BUF_NUM_FORMAT_UINT = 0x4,
- BUF_NUM_FORMAT_SINT = 0x5,
- BUF_NUM_FORMAT_RESERVED_6 = 0x6,
- BUF_NUM_FORMAT_FLOAT = 0x7,
-} BUF_NUM_FORMAT;
-typedef enum IMG_NUM_FORMAT {
- IMG_NUM_FORMAT_UNORM = 0x0,
- IMG_NUM_FORMAT_SNORM = 0x1,
- IMG_NUM_FORMAT_USCALED = 0x2,
- IMG_NUM_FORMAT_SSCALED = 0x3,
- IMG_NUM_FORMAT_UINT = 0x4,
- IMG_NUM_FORMAT_SINT = 0x5,
- IMG_NUM_FORMAT_RESERVED_6 = 0x6,
- IMG_NUM_FORMAT_FLOAT = 0x7,
- IMG_NUM_FORMAT_RESERVED_8 = 0x8,
- IMG_NUM_FORMAT_SRGB = 0x9,
- IMG_NUM_FORMAT_RESERVED_10 = 0xa,
- IMG_NUM_FORMAT_RESERVED_11 = 0xb,
- IMG_NUM_FORMAT_RESERVED_12 = 0xc,
- IMG_NUM_FORMAT_RESERVED_13 = 0xd,
- IMG_NUM_FORMAT_RESERVED_14 = 0xe,
- IMG_NUM_FORMAT_RESERVED_15 = 0xf,
-} IMG_NUM_FORMAT;
-typedef enum TileType {
- ARRAY_COLOR_TILE = 0x0,
- ARRAY_DEPTH_TILE = 0x1,
-} TileType;
-typedef enum NonDispTilingOrder {
- ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
- ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
-} NonDispTilingOrder;
-typedef enum MicroTileMode {
- ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
- ADDR_SURF_THIN_MICRO_TILING = 0x1,
- ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
- ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
- ADDR_SURF_THICK_MICRO_TILING = 0x4,
-} MicroTileMode;
-typedef enum TileSplit {
- ADDR_SURF_TILE_SPLIT_64B = 0x0,
- ADDR_SURF_TILE_SPLIT_128B = 0x1,
- ADDR_SURF_TILE_SPLIT_256B = 0x2,
- ADDR_SURF_TILE_SPLIT_512B = 0x3,
- ADDR_SURF_TILE_SPLIT_1KB = 0x4,
- ADDR_SURF_TILE_SPLIT_2KB = 0x5,
- ADDR_SURF_TILE_SPLIT_4KB = 0x6,
-} TileSplit;
-typedef enum SampleSplit {
- ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
- ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
- ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
- ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
-} SampleSplit;
-typedef enum PipeConfig {
- ADDR_SURF_P2 = 0x0,
- ADDR_SURF_P2_RESERVED0 = 0x1,
- ADDR_SURF_P2_RESERVED1 = 0x2,
- ADDR_SURF_P2_RESERVED2 = 0x3,
- ADDR_SURF_P4_8x16 = 0x4,
- ADDR_SURF_P4_16x16 = 0x5,
- ADDR_SURF_P4_16x32 = 0x6,
- ADDR_SURF_P4_32x32 = 0x7,
- ADDR_SURF_P8_16x16_8x16 = 0x8,
- ADDR_SURF_P8_16x32_8x16 = 0x9,
- ADDR_SURF_P8_32x32_8x16 = 0xa,
- ADDR_SURF_P8_16x32_16x16 = 0xb,
- ADDR_SURF_P8_32x32_16x16 = 0xc,
- ADDR_SURF_P8_32x32_16x32 = 0xd,
- ADDR_SURF_P8_32x64_32x32 = 0xe,
- ADDR_SURF_P8_RESERVED0 = 0xf,
- ADDR_SURF_P16_32x32_8x16 = 0x10,
- ADDR_SURF_P16_32x32_16x16 = 0x11,
-} PipeConfig;
-typedef enum NumBanks {
- ADDR_SURF_2_BANK = 0x0,
- ADDR_SURF_4_BANK = 0x1,
- ADDR_SURF_8_BANK = 0x2,
- ADDR_SURF_16_BANK = 0x3,
-} NumBanks;
-typedef enum BankWidth {
- ADDR_SURF_BANK_WIDTH_1 = 0x0,
- ADDR_SURF_BANK_WIDTH_2 = 0x1,
- ADDR_SURF_BANK_WIDTH_4 = 0x2,
- ADDR_SURF_BANK_WIDTH_8 = 0x3,
-} BankWidth;
-typedef enum BankHeight {
- ADDR_SURF_BANK_HEIGHT_1 = 0x0,
- ADDR_SURF_BANK_HEIGHT_2 = 0x1,
- ADDR_SURF_BANK_HEIGHT_4 = 0x2,
- ADDR_SURF_BANK_HEIGHT_8 = 0x3,
-} BankHeight;
-typedef enum BankWidthHeight {
- ADDR_SURF_BANK_WH_1 = 0x0,
- ADDR_SURF_BANK_WH_2 = 0x1,
- ADDR_SURF_BANK_WH_4 = 0x2,
- ADDR_SURF_BANK_WH_8 = 0x3,
-} BankWidthHeight;
-typedef enum MacroTileAspect {
- ADDR_SURF_MACRO_ASPECT_1 = 0x0,
- ADDR_SURF_MACRO_ASPECT_2 = 0x1,
- ADDR_SURF_MACRO_ASPECT_4 = 0x2,
- ADDR_SURF_MACRO_ASPECT_8 = 0x3,
-} MacroTileAspect;
-typedef enum GATCL1RequestType {
- GATCL1_TYPE_NORMAL = 0x0,
- GATCL1_TYPE_SHOOTDOWN = 0x1,
- GATCL1_TYPE_BYPASS = 0x2,
-} GATCL1RequestType;
-typedef enum TCC_CACHE_POLICIES {
- TCC_CACHE_POLICY_LRU = 0x0,
- TCC_CACHE_POLICY_STREAM = 0x1,
-} TCC_CACHE_POLICIES;
-typedef enum MTYPE {
- MTYPE_NC_NV = 0x0,
- MTYPE_NC = 0x1,
- MTYPE_CC = 0x2,
- MTYPE_UC = 0x3,
-} MTYPE;
-typedef enum PERFMON_COUNTER_MODE {
- PERFMON_COUNTER_MODE_ACCUM = 0x0,
- PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
- PERFMON_COUNTER_MODE_MAX = 0x2,
- PERFMON_COUNTER_MODE_DIRTY = 0x3,
- PERFMON_COUNTER_MODE_SAMPLE = 0x4,
- PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
- PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
- PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
- PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
- PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
- PERFMON_COUNTER_MODE_RESERVED = 0xf,
-} PERFMON_COUNTER_MODE;
-typedef enum PERFMON_SPM_MODE {
- PERFMON_SPM_MODE_OFF = 0x0,
- PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
- PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
- PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
- PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
- PERFMON_SPM_MODE_RESERVED_5 = 0x5,
- PERFMON_SPM_MODE_RESERVED_6 = 0x6,
- PERFMON_SPM_MODE_RESERVED_7 = 0x7,
- PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
- PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
- PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
-} PERFMON_SPM_MODE;
-typedef enum SurfaceTiling {
- ARRAY_LINEAR = 0x0,
- ARRAY_TILED = 0x1,
-} SurfaceTiling;
-typedef enum SurfaceArray {
- ARRAY_1D = 0x0,
- ARRAY_2D = 0x1,
- ARRAY_3D = 0x2,
- ARRAY_3D_SLICE = 0x3,
-} SurfaceArray;
-typedef enum ColorArray {
- ARRAY_2D_ALT_COLOR = 0x0,
- ARRAY_2D_COLOR = 0x1,
- ARRAY_3D_SLICE_COLOR = 0x3,
-} ColorArray;
-typedef enum DepthArray {
- ARRAY_2D_ALT_DEPTH = 0x0,
- ARRAY_2D_DEPTH = 0x1,
-} DepthArray;
-typedef enum ENUM_NUM_SIMD_PER_CU {
- NUM_SIMD_PER_CU = 0x4,
-} ENUM_NUM_SIMD_PER_CU;
-typedef enum MEM_PWR_FORCE_CTRL {
- NO_FORCE_REQUEST = 0x0,
- FORCE_LIGHT_SLEEP_REQUEST = 0x1,
- FORCE_DEEP_SLEEP_REQUEST = 0x2,
- FORCE_SHUT_DOWN_REQUEST = 0x3,
-} MEM_PWR_FORCE_CTRL;
-typedef enum MEM_PWR_FORCE_CTRL2 {
- NO_FORCE_REQ = 0x0,
- FORCE_LIGHT_SLEEP_REQ = 0x1,
-} MEM_PWR_FORCE_CTRL2;
-typedef enum MEM_PWR_DIS_CTRL {
- ENABLE_MEM_PWR_CTRL = 0x0,
- DISABLE_MEM_PWR_CTRL = 0x1,
-} MEM_PWR_DIS_CTRL;
-typedef enum MEM_PWR_SEL_CTRL {
- DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
- DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
- DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
-} MEM_PWR_SEL_CTRL;
-typedef enum MEM_PWR_SEL_CTRL2 {
- DYNAMIC_DEEP_SLEEP_EN = 0x0,
- DYNAMIC_LIGHT_SLEEP_EN = 0x1,
-} MEM_PWR_SEL_CTRL2;
-
-#endif /* OSS_3_0_1_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_enum.h
deleted file mode 100644
index 09338d82a..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_enum.h
+++ /dev/null
@@ -1,1497 +0,0 @@
-/*
- * OSS_3_0 Register documentation
- *
- * Copyright (C) 2014 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef OSS_3_0_ENUM_H
-#define OSS_3_0_ENUM_H
-
-typedef enum IH_CLIENT_ID {
- DC_IH_SRC_ID_START = 0x1,
- DC_IH_SRC_ID_END = 0x1f,
- VGA_IH_SRC_ID_START = 0x20,
- VGA_IH_SRC_ID_END = 0x27,
- CAP_IH_SRC_ID_START = 0x28,
- CAP_IH_SRC_ID_END = 0x2f,
- VIP_IH_SRC_ID_START = 0x30,
- VIP_IH_SRC_ID_END = 0x3f,
- ROM_IH_SRC_ID_START = 0x40,
- ROM_IH_SRC_ID_END = 0x5d,
- BIF_IH_SRC_ID_START = 0x5e,
- SAM_IH_SRC_ID_START = 0x5f,
- SRBM_IH_SRC_ID_START = 0x60,
- SRBM_IH_SRC_ID_END = 0x67,
- UVD_IH_SRC_ID_START = 0x72,
- UVD_IH_SRC_ID_END = 0x85,
- VMC_IH_SRC_ID_START = 0x86,
- VMC_IH_SRC_ID_END = 0x8f,
- RLC_IH_SRC_ID_START = 0x90,
- RLC_IH_SRC_ID_END = 0xf3,
- PDMA_IH_SRC_ID_START = 0xf4,
- PDMA_IH_SRC_ID_END = 0xf7,
- CG_IH_SRC_ID_START = 0xf8,
- CG_IH_SRC_ID_END = 0xff,
-} IH_CLIENT_ID;
-typedef enum IH_PERF_SEL {
- IH_PERF_SEL_CYCLE = 0x0,
- IH_PERF_SEL_IDLE = 0x1,
- IH_PERF_SEL_INPUT_IDLE = 0x2,
- IH_PERF_SEL_CLIENT0_IH_STALL = 0x3,
- IH_PERF_SEL_CLIENT1_IH_STALL = 0x4,
- IH_PERF_SEL_CLIENT2_IH_STALL = 0x5,
- IH_PERF_SEL_CLIENT3_IH_STALL = 0x6,
- IH_PERF_SEL_CLIENT4_IH_STALL = 0x7,
- IH_PERF_SEL_CLIENT5_IH_STALL = 0x8,
- IH_PERF_SEL_CLIENT6_IH_STALL = 0x9,
- IH_PERF_SEL_CLIENT7_IH_STALL = 0xa,
- IH_PERF_SEL_RB_IDLE = 0xb,
- IH_PERF_SEL_RB_FULL = 0xc,
- IH_PERF_SEL_RB_OVERFLOW = 0xd,
- IH_PERF_SEL_RB_WPTR_WRITEBACK = 0xe,
- IH_PERF_SEL_RB_WPTR_WRAP = 0xf,
- IH_PERF_SEL_RB_RPTR_WRAP = 0x10,
- IH_PERF_SEL_MC_WR_IDLE = 0x11,
- IH_PERF_SEL_MC_WR_COUNT = 0x12,
- IH_PERF_SEL_MC_WR_STALL = 0x13,
- IH_PERF_SEL_MC_WR_CLEAN_PENDING = 0x14,
- IH_PERF_SEL_MC_WR_CLEAN_STALL = 0x15,
- IH_PERF_SEL_BIF_RISING = 0x16,
- IH_PERF_SEL_BIF_FALLING = 0x17,
- IH_PERF_SEL_CLIENT8_IH_STALL = 0x18,
- IH_PERF_SEL_CLIENT9_IH_STALL = 0x19,
- IH_PERF_SEL_CLIENT10_IH_STALL = 0x1a,
- IH_PERF_SEL_CLIENT11_IH_STALL = 0x1b,
- IH_PERF_SEL_CLIENT12_IH_STALL = 0x1c,
- IH_PERF_SEL_CLIENT13_IH_STALL = 0x1d,
- IH_PERF_SEL_CLIENT14_IH_STALL = 0x1e,
- IH_PERF_SEL_CLIENT15_IH_STALL = 0x1f,
- IH_PERF_SEL_CLIENT16_IH_STALL = 0x20,
- IH_PERF_SEL_CLIENT17_IH_STALL = 0x21,
- IH_PERF_SEL_CLIENT18_IH_STALL = 0x22,
- IH_PERF_SEL_CLIENT19_IH_STALL = 0x23,
- IH_PERF_SEL_CLIENT20_IH_STALL = 0x24,
- IH_PERF_SEL_CLIENT21_IH_STALL = 0x25,
- IH_PERF_SEL_CLIENT22_IH_STALL = 0x26,
- IH_PERF_SEL_RB_FULL_VF0 = 0x27,
- IH_PERF_SEL_RB_FULL_VF1 = 0x28,
- IH_PERF_SEL_RB_FULL_VF2 = 0x29,
- IH_PERF_SEL_RB_FULL_VF3 = 0x2a,
- IH_PERF_SEL_RB_FULL_VF4 = 0x2b,
- IH_PERF_SEL_RB_FULL_VF5 = 0x2c,
- IH_PERF_SEL_RB_FULL_VF6 = 0x2d,
- IH_PERF_SEL_RB_FULL_VF7 = 0x2e,
- IH_PERF_SEL_RB_FULL_VF8 = 0x2f,
- IH_PERF_SEL_RB_FULL_VF9 = 0x30,
- IH_PERF_SEL_RB_FULL_VF10 = 0x31,
- IH_PERF_SEL_RB_FULL_VF11 = 0x32,
- IH_PERF_SEL_RB_FULL_VF12 = 0x33,
- IH_PERF_SEL_RB_FULL_VF13 = 0x34,
- IH_PERF_SEL_RB_FULL_VF14 = 0x35,
- IH_PERF_SEL_RB_FULL_VF15 = 0x36,
- IH_PERF_SEL_RB_OVERFLOW_VF0 = 0x37,
- IH_PERF_SEL_RB_OVERFLOW_VF1 = 0x38,
- IH_PERF_SEL_RB_OVERFLOW_VF2 = 0x39,
- IH_PERF_SEL_RB_OVERFLOW_VF3 = 0x3a,
- IH_PERF_SEL_RB_OVERFLOW_VF4 = 0x3b,
- IH_PERF_SEL_RB_OVERFLOW_VF5 = 0x3c,
- IH_PERF_SEL_RB_OVERFLOW_VF6 = 0x3d,
- IH_PERF_SEL_RB_OVERFLOW_VF7 = 0x3e,
- IH_PERF_SEL_RB_OVERFLOW_VF8 = 0x3f,
- IH_PERF_SEL_RB_OVERFLOW_VF9 = 0x40,
- IH_PERF_SEL_RB_OVERFLOW_VF10 = 0x41,
- IH_PERF_SEL_RB_OVERFLOW_VF11 = 0x42,
- IH_PERF_SEL_RB_OVERFLOW_VF12 = 0x43,
- IH_PERF_SEL_RB_OVERFLOW_VF13 = 0x44,
- IH_PERF_SEL_RB_OVERFLOW_VF14 = 0x45,
- IH_PERF_SEL_RB_OVERFLOW_VF15 = 0x46,
- IH_PERF_SEL_RB_WPTR_WRITEBACK_VF0 = 0x47,
- IH_PERF_SEL_RB_WPTR_WRITEBACK_VF1 = 0x48,
- IH_PERF_SEL_RB_WPTR_WRITEBACK_VF2 = 0x49,
- IH_PERF_SEL_RB_WPTR_WRITEBACK_VF3 = 0x4a,
- IH_PERF_SEL_RB_WPTR_WRITEBACK_VF4 = 0x4b,
- IH_PERF_SEL_RB_WPTR_WRITEBACK_VF5 = 0x4c,
- IH_PERF_SEL_RB_WPTR_WRITEBACK_VF6 = 0x4d,
- IH_PERF_SEL_RB_WPTR_WRITEBACK_VF7 = 0x4e,
- IH_PERF_SEL_RB_WPTR_WRITEBACK_VF8 = 0x4f,
- IH_PERF_SEL_RB_WPTR_WRITEBACK_VF9 = 0x50,
- IH_PERF_SEL_RB_WPTR_WRITEBACK_VF10 = 0x51,
- IH_PERF_SEL_RB_WPTR_WRITEBACK_VF11 = 0x52,
- IH_PERF_SEL_RB_WPTR_WRITEBACK_VF12 = 0x53,
- IH_PERF_SEL_RB_WPTR_WRITEBACK_VF13 = 0x54,
- IH_PERF_SEL_RB_WPTR_WRITEBACK_VF14 = 0x55,
- IH_PERF_SEL_RB_WPTR_WRITEBACK_VF15 = 0x56,
- IH_PERF_SEL_RB_WPTR_WRAP_VF0 = 0x57,
- IH_PERF_SEL_RB_WPTR_WRAP_VF1 = 0x58,
- IH_PERF_SEL_RB_WPTR_WRAP_VF2 = 0x59,
- IH_PERF_SEL_RB_WPTR_WRAP_VF3 = 0x5a,
- IH_PERF_SEL_RB_WPTR_WRAP_VF4 = 0x5b,
- IH_PERF_SEL_RB_WPTR_WRAP_VF5 = 0x5c,
- IH_PERF_SEL_RB_WPTR_WRAP_VF6 = 0x5d,
- IH_PERF_SEL_RB_WPTR_WRAP_VF7 = 0x5e,
- IH_PERF_SEL_RB_WPTR_WRAP_VF8 = 0x5f,
- IH_PERF_SEL_RB_WPTR_WRAP_VF9 = 0x60,
- IH_PERF_SEL_RB_WPTR_WRAP_VF10 = 0x61,
- IH_PERF_SEL_RB_WPTR_WRAP_VF11 = 0x62,
- IH_PERF_SEL_RB_WPTR_WRAP_VF12 = 0x63,
- IH_PERF_SEL_RB_WPTR_WRAP_VF13 = 0x64,
- IH_PERF_SEL_RB_WPTR_WRAP_VF14 = 0x65,
- IH_PERF_SEL_RB_WPTR_WRAP_VF15 = 0x66,
- IH_PERF_SEL_RB_RPTR_WRAP_VF0 = 0x67,
- IH_PERF_SEL_RB_RPTR_WRAP_VF1 = 0x68,
- IH_PERF_SEL_RB_RPTR_WRAP_VF2 = 0x69,
- IH_PERF_SEL_RB_RPTR_WRAP_VF3 = 0x6a,
- IH_PERF_SEL_RB_RPTR_WRAP_VF4 = 0x6b,
- IH_PERF_SEL_RB_RPTR_WRAP_VF5 = 0x6c,
- IH_PERF_SEL_RB_RPTR_WRAP_VF6 = 0x6d,
- IH_PERF_SEL_RB_RPTR_WRAP_VF7 = 0x6e,
- IH_PERF_SEL_RB_RPTR_WRAP_VF8 = 0x6f,
- IH_PERF_SEL_RB_RPTR_WRAP_VF9 = 0x70,
- IH_PERF_SEL_RB_RPTR_WRAP_VF10 = 0x71,
- IH_PERF_SEL_RB_RPTR_WRAP_VF11 = 0x72,
- IH_PERF_SEL_RB_RPTR_WRAP_VF12 = 0x73,
- IH_PERF_SEL_RB_RPTR_WRAP_VF13 = 0x74,
- IH_PERF_SEL_RB_RPTR_WRAP_VF14 = 0x75,
- IH_PERF_SEL_RB_RPTR_WRAP_VF15 = 0x76,
- IH_PERF_SEL_BIF_RISING_VF0 = 0x77,
- IH_PERF_SEL_BIF_RISING_VF1 = 0x78,
- IH_PERF_SEL_BIF_RISING_VF2 = 0x79,
- IH_PERF_SEL_BIF_RISING_VF3 = 0x7a,
- IH_PERF_SEL_BIF_RISING_VF4 = 0x7b,
- IH_PERF_SEL_BIF_RISING_VF5 = 0x7c,
- IH_PERF_SEL_BIF_RISING_VF6 = 0x7d,
- IH_PERF_SEL_BIF_RISING_VF7 = 0x7e,
- IH_PERF_SEL_BIF_RISING_VF8 = 0x7f,
- IH_PERF_SEL_BIF_RISING_VF9 = 0x80,
- IH_PERF_SEL_BIF_RISING_VF10 = 0x81,
- IH_PERF_SEL_BIF_RISING_VF11 = 0x82,
- IH_PERF_SEL_BIF_RISING_VF12 = 0x83,
- IH_PERF_SEL_BIF_RISING_VF13 = 0x84,
- IH_PERF_SEL_BIF_RISING_VF14 = 0x85,
- IH_PERF_SEL_BIF_RISING_VF15 = 0x86,
- IH_PERF_SEL_BIF_FALLING_VF0 = 0x87,
- IH_PERF_SEL_BIF_FALLING_VF1 = 0x88,
- IH_PERF_SEL_BIF_FALLING_VF2 = 0x89,
- IH_PERF_SEL_BIF_FALLING_VF3 = 0x8a,
- IH_PERF_SEL_BIF_FALLING_VF4 = 0x8b,
- IH_PERF_SEL_BIF_FALLING_VF5 = 0x8c,
- IH_PERF_SEL_BIF_FALLING_VF6 = 0x8d,
- IH_PERF_SEL_BIF_FALLING_VF7 = 0x8e,
- IH_PERF_SEL_BIF_FALLING_VF8 = 0x8f,
- IH_PERF_SEL_BIF_FALLING_VF9 = 0x90,
- IH_PERF_SEL_BIF_FALLING_VF10 = 0x91,
- IH_PERF_SEL_BIF_FALLING_VF11 = 0x92,
- IH_PERF_SEL_BIF_FALLING_VF12 = 0x93,
- IH_PERF_SEL_BIF_FALLING_VF13 = 0x94,
- IH_PERF_SEL_BIF_FALLING_VF14 = 0x95,
- IH_PERF_SEL_BIF_FALLING_VF15 = 0x96,
-} IH_PERF_SEL;
-typedef enum SRBM_PERFCOUNT1_SEL {
- SRBM_PERF_SEL_COUNT = 0x0,
- SRBM_PERF_SEL_BIF_BUSY = 0x1,
- SRBM_PERF_SEL_SDMA0_BUSY = 0x3,
- SRBM_PERF_SEL_IH_BUSY = 0x4,
- SRBM_PERF_SEL_MCB_BUSY = 0x5,
- SRBM_PERF_SEL_MCB_NON_DISPLAY_BUSY = 0x6,
- SRBM_PERF_SEL_MCC_BUSY = 0x7,
- SRBM_PERF_SEL_MCD_BUSY = 0x8,
- SRBM_PERF_SEL_CHUB_BUSY = 0x9,
- SRBM_PERF_SEL_SEM_BUSY = 0xa,
- SRBM_PERF_SEL_UVD_BUSY = 0xb,
- SRBM_PERF_SEL_VMC_BUSY = 0xc,
- SRBM_PERF_SEL_ODE_BUSY = 0xd,
- SRBM_PERF_SEL_SDMA1_BUSY = 0xe,
- SRBM_PERF_SEL_SAMMSP_BUSY = 0xf,
- SRBM_PERF_SEL_VCE0_BUSY = 0x10,
- SRBM_PERF_SEL_XDMA_BUSY = 0x11,
- SRBM_PERF_SEL_ACP_BUSY = 0x12,
- SRBM_PERF_SEL_SDMA2_BUSY = 0x13,
- SRBM_PERF_SEL_SDMA3_BUSY = 0x14,
- SRBM_PERF_SEL_SAMSCP_BUSY = 0x15,
- SRBM_PERF_SEL_VMC1_BUSY = 0x16,
- SRBM_PERF_SEL_ISP_BUSY = 0x17,
- SRBM_PERF_SEL_VCE1_BUSY = 0x18,
- SRBM_PERF_SEL_GCATCL2_BUSY = 0x19,
- SRBM_PERF_SEL_OSATCL2_BUSY = 0x1a,
- SRBM_PERF_SEL_VP8_BUSY = 0x1b,
-} SRBM_PERFCOUNT1_SEL;
-typedef enum SYS_GRBM_GFX_INDEX_SEL {
- GRBM_GFX_INDEX_BIF = 0x0,
- GRBM_GFX_INDEX_SDMA0 = 0x1,
- GRBM_GFX_INDEX_SDMA1 = 0x2,
- RESEVERED0 = 0x3,
- GRBM_GFX_INDEX_UVD = 0x4,
- GRBM_GFX_INDEX_VCE0 = 0x5,
- GRBM_GFX_INDEX_VCE1 = 0x6,
- GRBM_GFX_INDEX_ACP = 0x7,
- GRBM_GFX_INDEX_SMU = 0x8,
- GRBM_GFX_INDEX_SAMMSP = 0x9,
- GRBM_GFX_INDEX_SAMSCP = 0xa,
- GRBM_GFX_INDEX_ISP = 0xb,
- GRBM_GFX_INDEX_TST = 0xc,
- GRBM_GFX_INDEX_SDMA2 = 0xd,
- GRBM_GFX_INDEX_SDMA3 = 0xe,
-} SYS_GRBM_GFX_INDEX_SEL;
-typedef enum SRBM_GFX_CNTL_SEL {
- SRBM_GFX_CNTL_BIF = 0x0,
- SRBM_GFX_CNTL_SDMA0 = 0x1,
- SRBM_GFX_CNTL_SDMA1 = 0x2,
- SRBM_GFX_CNTL_GRBM = 0x3,
- SRBM_GFX_CNTL_UVD = 0x4,
- SRBM_GFX_CNTL_VCE0 = 0x5,
- SRBM_GFX_CNTL_VCE1 = 0x6,
- SRBM_GFX_CNTL_ACP = 0x7,
- SRBM_GFX_CNTL_SMU = 0x8,
- SRBM_GFX_CNTL_SAMMSP = 0x9,
- SRBM_GFX_CNTL_SAMSCP = 0xa,
- SRBM_GFX_CNTL_ISP = 0xb,
- SRBM_GFX_CNTL_TST = 0xc,
- SRBM_GFX_CNTL_SDMA2 = 0xd,
- SRBM_GFX_CNTL_SDMA3 = 0xe,
-} SRBM_GFX_CNTL_SEL;
-typedef enum SDMA_PERF_SEL {
- SDMA_PERF_SEL_CYCLE = 0x0,
- SDMA_PERF_SEL_IDLE = 0x1,
- SDMA_PERF_SEL_REG_IDLE = 0x2,
- SDMA_PERF_SEL_RB_EMPTY = 0x3,
- SDMA_PERF_SEL_RB_FULL = 0x4,
- SDMA_PERF_SEL_RB_WPTR_WRAP = 0x5,
- SDMA_PERF_SEL_RB_RPTR_WRAP = 0x6,
- SDMA_PERF_SEL_RB_WPTR_POLL_READ = 0x7,
- SDMA_PERF_SEL_RB_RPTR_WB = 0x8,
- SDMA_PERF_SEL_RB_CMD_IDLE = 0x9,
- SDMA_PERF_SEL_RB_CMD_FULL = 0xa,
- SDMA_PERF_SEL_IB_CMD_IDLE = 0xb,
- SDMA_PERF_SEL_IB_CMD_FULL = 0xc,
- SDMA_PERF_SEL_EX_IDLE = 0xd,
- SDMA_PERF_SEL_SRBM_REG_SEND = 0xe,
- SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0xf,
- SDMA_PERF_SEL_MC_WR_IDLE = 0x10,
- SDMA_PERF_SEL_MC_WR_COUNT = 0x11,
- SDMA_PERF_SEL_MC_RD_IDLE = 0x12,
- SDMA_PERF_SEL_MC_RD_COUNT = 0x13,
- SDMA_PERF_SEL_MC_RD_RET_STALL = 0x14,
- SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 0x15,
- SDMA_PERF_SEL_SEM_IDLE = 0x18,
- SDMA_PERF_SEL_SEM_REQ_STALL = 0x19,
- SDMA_PERF_SEL_SEM_REQ_COUNT = 0x1a,
- SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 0x1b,
- SDMA_PERF_SEL_SEM_RESP_FAIL = 0x1c,
- SDMA_PERF_SEL_SEM_RESP_PASS = 0x1d,
- SDMA_PERF_SEL_INT_IDLE = 0x1e,
- SDMA_PERF_SEL_INT_REQ_STALL = 0x1f,
- SDMA_PERF_SEL_INT_REQ_COUNT = 0x20,
- SDMA_PERF_SEL_INT_RESP_ACCEPTED = 0x21,
- SDMA_PERF_SEL_INT_RESP_RETRY = 0x22,
- SDMA_PERF_SEL_NUM_PACKET = 0x23,
- SDMA_PERF_SEL_CE_WREQ_IDLE = 0x25,
- SDMA_PERF_SEL_CE_WR_IDLE = 0x26,
- SDMA_PERF_SEL_CE_SPLIT_IDLE = 0x27,
- SDMA_PERF_SEL_CE_RREQ_IDLE = 0x28,
- SDMA_PERF_SEL_CE_OUT_IDLE = 0x29,
- SDMA_PERF_SEL_CE_IN_IDLE = 0x2a,
- SDMA_PERF_SEL_CE_DST_IDLE = 0x2b,
- SDMA_PERF_SEL_CE_AFIFO_FULL = 0x2e,
- SDMA_PERF_SEL_CE_INFO_FULL = 0x31,
- SDMA_PERF_SEL_CE_INFO1_FULL = 0x32,
- SDMA_PERF_SEL_CE_RD_STALL = 0x33,
- SDMA_PERF_SEL_CE_WR_STALL = 0x34,
- SDMA_PERF_SEL_GFX_SELECT = 0x35,
- SDMA_PERF_SEL_RLC0_SELECT = 0x36,
- SDMA_PERF_SEL_RLC1_SELECT = 0x37,
- SDMA_PERF_SEL_CTX_CHANGE = 0x38,
- SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 0x39,
- SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 0x3a,
- SDMA_PERF_SEL_DOORBELL = 0x3b,
- SDMA_PERF_SEL_RD_BA_RTR = 0x3c,
- SDMA_PERF_SEL_WR_BA_RTR = 0x3d,
-} SDMA_PERF_SEL;
-typedef enum SurfaceEndian {
- ENDIAN_NONE = 0x0,
- ENDIAN_8IN16 = 0x1,
- ENDIAN_8IN32 = 0x2,
- ENDIAN_8IN64 = 0x3,
-} SurfaceEndian;
-typedef enum ArrayMode {
- ARRAY_LINEAR_GENERAL = 0x0,
- ARRAY_LINEAR_ALIGNED = 0x1,
- ARRAY_1D_TILED_THIN1 = 0x2,
- ARRAY_1D_TILED_THICK = 0x3,
- ARRAY_2D_TILED_THIN1 = 0x4,
- ARRAY_PRT_TILED_THIN1 = 0x5,
- ARRAY_PRT_2D_TILED_THIN1 = 0x6,
- ARRAY_2D_TILED_THICK = 0x7,
- ARRAY_2D_TILED_XTHICK = 0x8,
- ARRAY_PRT_TILED_THICK = 0x9,
- ARRAY_PRT_2D_TILED_THICK = 0xa,
- ARRAY_PRT_3D_TILED_THIN1 = 0xb,
- ARRAY_3D_TILED_THIN1 = 0xc,
- ARRAY_3D_TILED_THICK = 0xd,
- ARRAY_3D_TILED_XTHICK = 0xe,
- ARRAY_PRT_3D_TILED_THICK = 0xf,
-} ArrayMode;
-typedef enum PipeTiling {
- CONFIG_1_PIPE = 0x0,
- CONFIG_2_PIPE = 0x1,
- CONFIG_4_PIPE = 0x2,
- CONFIG_8_PIPE = 0x3,
-} PipeTiling;
-typedef enum BankTiling {
- CONFIG_4_BANK = 0x0,
- CONFIG_8_BANK = 0x1,
-} BankTiling;
-typedef enum GroupInterleave {
- CONFIG_256B_GROUP = 0x0,
- CONFIG_512B_GROUP = 0x1,
-} GroupInterleave;
-typedef enum RowTiling {
- CONFIG_1KB_ROW = 0x0,
- CONFIG_2KB_ROW = 0x1,
- CONFIG_4KB_ROW = 0x2,
- CONFIG_8KB_ROW = 0x3,
- CONFIG_1KB_ROW_OPT = 0x4,
- CONFIG_2KB_ROW_OPT = 0x5,
- CONFIG_4KB_ROW_OPT = 0x6,
- CONFIG_8KB_ROW_OPT = 0x7,
-} RowTiling;
-typedef enum BankSwapBytes {
- CONFIG_128B_SWAPS = 0x0,
- CONFIG_256B_SWAPS = 0x1,
- CONFIG_512B_SWAPS = 0x2,
- CONFIG_1KB_SWAPS = 0x3,
-} BankSwapBytes;
-typedef enum SampleSplitBytes {
- CONFIG_1KB_SPLIT = 0x0,
- CONFIG_2KB_SPLIT = 0x1,
- CONFIG_4KB_SPLIT = 0x2,
- CONFIG_8KB_SPLIT = 0x3,
-} SampleSplitBytes;
-typedef enum NumPipes {
- ADDR_CONFIG_1_PIPE = 0x0,
- ADDR_CONFIG_2_PIPE = 0x1,
- ADDR_CONFIG_4_PIPE = 0x2,
- ADDR_CONFIG_8_PIPE = 0x3,
-} NumPipes;
-typedef enum PipeInterleaveSize {
- ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
- ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
-} PipeInterleaveSize;
-typedef enum BankInterleaveSize {
- ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
- ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
- ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
- ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
-} BankInterleaveSize;
-typedef enum NumShaderEngines {
- ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
- ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
-} NumShaderEngines;
-typedef enum ShaderEngineTileSize {
- ADDR_CONFIG_SE_TILE_16 = 0x0,
- ADDR_CONFIG_SE_TILE_32 = 0x1,
-} ShaderEngineTileSize;
-typedef enum NumGPUs {
- ADDR_CONFIG_1_GPU = 0x0,
- ADDR_CONFIG_2_GPU = 0x1,
- ADDR_CONFIG_4_GPU = 0x2,
-} NumGPUs;
-typedef enum MultiGPUTileSize {
- ADDR_CONFIG_GPU_TILE_16 = 0x0,
- ADDR_CONFIG_GPU_TILE_32 = 0x1,
- ADDR_CONFIG_GPU_TILE_64 = 0x2,
- ADDR_CONFIG_GPU_TILE_128 = 0x3,
-} MultiGPUTileSize;
-typedef enum RowSize {
- ADDR_CONFIG_1KB_ROW = 0x0,
- ADDR_CONFIG_2KB_ROW = 0x1,
- ADDR_CONFIG_4KB_ROW = 0x2,
-} RowSize;
-typedef enum NumLowerPipes {
- ADDR_CONFIG_1_LOWER_PIPES = 0x0,
- ADDR_CONFIG_2_LOWER_PIPES = 0x1,
-} NumLowerPipes;
-typedef enum DebugBlockId {
- DBG_CLIENT_BLKID_RESERVED = 0x0,
- DBG_CLIENT_BLKID_dbg = 0x1,
- DBG_CLIENT_BLKID_scf2 = 0x2,
- DBG_CLIENT_BLKID_mcd5 = 0x3,
- DBG_CLIENT_BLKID_vmc = 0x4,
- DBG_CLIENT_BLKID_sx30 = 0x5,
- DBG_CLIENT_BLKID_mcd2 = 0x6,
- DBG_CLIENT_BLKID_bci1 = 0x7,
- DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0x8,
- DBG_CLIENT_BLKID_mcc0 = 0x9,
- DBG_CLIENT_BLKID_uvdf_0 = 0xa,
- DBG_CLIENT_BLKID_uvdf_1 = 0xb,
- DBG_CLIENT_BLKID_uvdf_2 = 0xc,
- DBG_CLIENT_BLKID_uvdi_0 = 0xd,
- DBG_CLIENT_BLKID_bci0 = 0xe,
- DBG_CLIENT_BLKID_vcec0_0 = 0xf,
- DBG_CLIENT_BLKID_cb100 = 0x10,
- DBG_CLIENT_BLKID_cb001 = 0x11,
- DBG_CLIENT_BLKID_mcd4 = 0x12,
- DBG_CLIENT_BLKID_tmonw00 = 0x13,
- DBG_CLIENT_BLKID_cb101 = 0x14,
- DBG_CLIENT_BLKID_sx10 = 0x15,
- DBG_CLIENT_BLKID_cb301 = 0x16,
- DBG_CLIENT_BLKID_tmonw01 = 0x17,
- DBG_CLIENT_BLKID_vcea0_0 = 0x18,
- DBG_CLIENT_BLKID_vcea0_1 = 0x19,
- DBG_CLIENT_BLKID_vcea0_2 = 0x1a,
- DBG_CLIENT_BLKID_vcea0_3 = 0x1b,
- DBG_CLIENT_BLKID_scf1 = 0x1c,
- DBG_CLIENT_BLKID_sx20 = 0x1d,
- DBG_CLIENT_BLKID_spim1 = 0x1e,
- DBG_CLIENT_BLKID_pa10 = 0x1f,
- DBG_CLIENT_BLKID_pa00 = 0x20,
- DBG_CLIENT_BLKID_gmcon = 0x21,
- DBG_CLIENT_BLKID_mcb = 0x22,
- DBG_CLIENT_BLKID_vgt0 = 0x23,
- DBG_CLIENT_BLKID_pc0 = 0x24,
- DBG_CLIENT_BLKID_bci2 = 0x25,
- DBG_CLIENT_BLKID_uvdb_0 = 0x26,
- DBG_CLIENT_BLKID_spim3 = 0x27,
- DBG_CLIENT_BLKID_cpc_0 = 0x28,
- DBG_CLIENT_BLKID_cpc_1 = 0x29,
- DBG_CLIENT_BLKID_uvdm_0 = 0x2a,
- DBG_CLIENT_BLKID_uvdm_1 = 0x2b,
- DBG_CLIENT_BLKID_uvdm_2 = 0x2c,
- DBG_CLIENT_BLKID_uvdm_3 = 0x2d,
- DBG_CLIENT_BLKID_cb000 = 0x2e,
- DBG_CLIENT_BLKID_spim0 = 0x2f,
- DBG_CLIENT_BLKID_mcc2 = 0x30,
- DBG_CLIENT_BLKID_ds0 = 0x31,
- DBG_CLIENT_BLKID_srbm = 0x32,
- DBG_CLIENT_BLKID_ih = 0x33,
- DBG_CLIENT_BLKID_sem = 0x34,
- DBG_CLIENT_BLKID_sdma_0 = 0x35,
- DBG_CLIENT_BLKID_sdma_1 = 0x36,
- DBG_CLIENT_BLKID_hdp = 0x37,
- DBG_CLIENT_BLKID_acp_0 = 0x38,
- DBG_CLIENT_BLKID_acp_1 = 0x39,
- DBG_CLIENT_BLKID_cb200 = 0x3a,
- DBG_CLIENT_BLKID_scf3 = 0x3b,
- DBG_CLIENT_BLKID_vceb1_0 = 0x3c,
- DBG_CLIENT_BLKID_vcea1_0 = 0x3d,
- DBG_CLIENT_BLKID_vcea1_1 = 0x3e,
- DBG_CLIENT_BLKID_vcea1_2 = 0x3f,
- DBG_CLIENT_BLKID_vcea1_3 = 0x40,
- DBG_CLIENT_BLKID_bci3 = 0x41,
- DBG_CLIENT_BLKID_mcd0 = 0x42,
- DBG_CLIENT_BLKID_pa11 = 0x43,
- DBG_CLIENT_BLKID_pa01 = 0x44,
- DBG_CLIENT_BLKID_cb201 = 0x45,
- DBG_CLIENT_BLKID_spim2 = 0x46,
- DBG_CLIENT_BLKID_vgt2 = 0x47,
- DBG_CLIENT_BLKID_pc2 = 0x48,
- DBG_CLIENT_BLKID_smu_0 = 0x49,
- DBG_CLIENT_BLKID_smu_1 = 0x4a,
- DBG_CLIENT_BLKID_smu_2 = 0x4b,
- DBG_CLIENT_BLKID_cb1 = 0x4c,
- DBG_CLIENT_BLKID_ia0 = 0x4d,
- DBG_CLIENT_BLKID_wd = 0x4e,
- DBG_CLIENT_BLKID_ia1 = 0x4f,
- DBG_CLIENT_BLKID_vcec1_0 = 0x50,
- DBG_CLIENT_BLKID_scf0 = 0x51,
- DBG_CLIENT_BLKID_vgt1 = 0x52,
- DBG_CLIENT_BLKID_pc1 = 0x53,
- DBG_CLIENT_BLKID_cb0 = 0x54,
- DBG_CLIENT_BLKID_gdc_one_0 = 0x55,
- DBG_CLIENT_BLKID_gdc_one_1 = 0x56,
- DBG_CLIENT_BLKID_gdc_one_2 = 0x57,
- DBG_CLIENT_BLKID_gdc_one_3 = 0x58,
- DBG_CLIENT_BLKID_gdc_one_4 = 0x59,
- DBG_CLIENT_BLKID_gdc_one_5 = 0x5a,
- DBG_CLIENT_BLKID_gdc_one_6 = 0x5b,
- DBG_CLIENT_BLKID_gdc_one_7 = 0x5c,
- DBG_CLIENT_BLKID_gdc_one_8 = 0x5d,
- DBG_CLIENT_BLKID_gdc_one_9 = 0x5e,
- DBG_CLIENT_BLKID_gdc_one_10 = 0x5f,
- DBG_CLIENT_BLKID_gdc_one_11 = 0x60,
- DBG_CLIENT_BLKID_gdc_one_12 = 0x61,
- DBG_CLIENT_BLKID_gdc_one_13 = 0x62,
- DBG_CLIENT_BLKID_gdc_one_14 = 0x63,
- DBG_CLIENT_BLKID_gdc_one_15 = 0x64,
- DBG_CLIENT_BLKID_gdc_one_16 = 0x65,
- DBG_CLIENT_BLKID_gdc_one_17 = 0x66,
- DBG_CLIENT_BLKID_gdc_one_18 = 0x67,
- DBG_CLIENT_BLKID_gdc_one_19 = 0x68,
- DBG_CLIENT_BLKID_gdc_one_20 = 0x69,
- DBG_CLIENT_BLKID_gdc_one_21 = 0x6a,
- DBG_CLIENT_BLKID_gdc_one_22 = 0x6b,
- DBG_CLIENT_BLKID_gdc_one_23 = 0x6c,
- DBG_CLIENT_BLKID_gdc_one_24 = 0x6d,
- DBG_CLIENT_BLKID_gdc_one_25 = 0x6e,
- DBG_CLIENT_BLKID_gdc_one_26 = 0x6f,
- DBG_CLIENT_BLKID_gdc_one_27 = 0x70,
- DBG_CLIENT_BLKID_gdc_one_28 = 0x71,
- DBG_CLIENT_BLKID_gdc_one_29 = 0x72,
- DBG_CLIENT_BLKID_gdc_one_30 = 0x73,
- DBG_CLIENT_BLKID_gdc_one_31 = 0x74,
- DBG_CLIENT_BLKID_gdc_one_32 = 0x75,
- DBG_CLIENT_BLKID_gdc_one_33 = 0x76,
- DBG_CLIENT_BLKID_gdc_one_34 = 0x77,
- DBG_CLIENT_BLKID_gdc_one_35 = 0x78,
- DBG_CLIENT_BLKID_vceb0_0 = 0x79,
- DBG_CLIENT_BLKID_vgt3 = 0x7a,
- DBG_CLIENT_BLKID_pc3 = 0x7b,
- DBG_CLIENT_BLKID_mcd3 = 0x7c,
- DBG_CLIENT_BLKID_uvdu_0 = 0x7d,
- DBG_CLIENT_BLKID_uvdu_1 = 0x7e,
- DBG_CLIENT_BLKID_uvdu_2 = 0x7f,
- DBG_CLIENT_BLKID_uvdu_3 = 0x80,
- DBG_CLIENT_BLKID_uvdu_4 = 0x81,
- DBG_CLIENT_BLKID_uvdu_5 = 0x82,
- DBG_CLIENT_BLKID_uvdu_6 = 0x83,
- DBG_CLIENT_BLKID_cb300 = 0x84,
- DBG_CLIENT_BLKID_mcd1 = 0x85,
- DBG_CLIENT_BLKID_sx00 = 0x86,
- DBG_CLIENT_BLKID_uvdc_0 = 0x87,
- DBG_CLIENT_BLKID_uvdc_1 = 0x88,
- DBG_CLIENT_BLKID_mcc3 = 0x89,
- DBG_CLIENT_BLKID_cpg_0 = 0x8a,
- DBG_CLIENT_BLKID_cpg_1 = 0x8b,
- DBG_CLIENT_BLKID_gck = 0x8c,
- DBG_CLIENT_BLKID_mcc1 = 0x8d,
- DBG_CLIENT_BLKID_cpf_0 = 0x8e,
- DBG_CLIENT_BLKID_cpf_1 = 0x8f,
- DBG_CLIENT_BLKID_rlc = 0x90,
- DBG_CLIENT_BLKID_grbm = 0x91,
- DBG_CLIENT_BLKID_sammsp = 0x92,
- DBG_CLIENT_BLKID_dci_pg = 0x93,
- DBG_CLIENT_BLKID_dci_0 = 0x94,
- DBG_CLIENT_BLKID_dccg0_0 = 0x95,
- DBG_CLIENT_BLKID_dccg0_1 = 0x96,
- DBG_CLIENT_BLKID_dcfe01_0 = 0x97,
- DBG_CLIENT_BLKID_dcfe02_0 = 0x98,
- DBG_CLIENT_BLKID_dcfe03_0 = 0x99,
- DBG_CLIENT_BLKID_dcfe04_0 = 0x9a,
- DBG_CLIENT_BLKID_dcfe05_0 = 0x9b,
- DBG_CLIENT_BLKID_dcfe06_0 = 0x9c,
- DBG_CLIENT_BLKID_RESERVED_LAST = 0x9d,
-} DebugBlockId;
-typedef enum DebugBlockId_OLD {
- DBG_BLOCK_ID_RESERVED = 0x0,
- DBG_BLOCK_ID_DBG = 0x1,
- DBG_BLOCK_ID_VMC = 0x2,
- DBG_BLOCK_ID_PDMA = 0x3,
- DBG_BLOCK_ID_CG = 0x4,
- DBG_BLOCK_ID_SRBM = 0x5,
- DBG_BLOCK_ID_GRBM = 0x6,
- DBG_BLOCK_ID_RLC = 0x7,
- DBG_BLOCK_ID_CSC = 0x8,
- DBG_BLOCK_ID_SEM = 0x9,
- DBG_BLOCK_ID_IH = 0xa,
- DBG_BLOCK_ID_SC = 0xb,
- DBG_BLOCK_ID_SQ = 0xc,
- DBG_BLOCK_ID_AVP = 0xd,
- DBG_BLOCK_ID_GMCON = 0xe,
- DBG_BLOCK_ID_SMU = 0xf,
- DBG_BLOCK_ID_DMA0 = 0x10,
- DBG_BLOCK_ID_DMA1 = 0x11,
- DBG_BLOCK_ID_SPIM = 0x12,
- DBG_BLOCK_ID_GDS = 0x13,
- DBG_BLOCK_ID_SPIS = 0x14,
- DBG_BLOCK_ID_UNUSED0 = 0x15,
- DBG_BLOCK_ID_PA0 = 0x16,
- DBG_BLOCK_ID_PA1 = 0x17,
- DBG_BLOCK_ID_CP0 = 0x18,
- DBG_BLOCK_ID_CP1 = 0x19,
- DBG_BLOCK_ID_CP2 = 0x1a,
- DBG_BLOCK_ID_UNUSED1 = 0x1b,
- DBG_BLOCK_ID_UVDU = 0x1c,
- DBG_BLOCK_ID_UVDM = 0x1d,
- DBG_BLOCK_ID_VCE = 0x1e,
- DBG_BLOCK_ID_UNUSED2 = 0x1f,
- DBG_BLOCK_ID_VGT0 = 0x20,
- DBG_BLOCK_ID_VGT1 = 0x21,
- DBG_BLOCK_ID_IA = 0x22,
- DBG_BLOCK_ID_UNUSED3 = 0x23,
- DBG_BLOCK_ID_SCT0 = 0x24,
- DBG_BLOCK_ID_SCT1 = 0x25,
- DBG_BLOCK_ID_SPM0 = 0x26,
- DBG_BLOCK_ID_SPM1 = 0x27,
- DBG_BLOCK_ID_TCAA = 0x28,
- DBG_BLOCK_ID_TCAB = 0x29,
- DBG_BLOCK_ID_TCCA = 0x2a,
- DBG_BLOCK_ID_TCCB = 0x2b,
- DBG_BLOCK_ID_MCC0 = 0x2c,
- DBG_BLOCK_ID_MCC1 = 0x2d,
- DBG_BLOCK_ID_MCC2 = 0x2e,
- DBG_BLOCK_ID_MCC3 = 0x2f,
- DBG_BLOCK_ID_SX0 = 0x30,
- DBG_BLOCK_ID_SX1 = 0x31,
- DBG_BLOCK_ID_SX2 = 0x32,
- DBG_BLOCK_ID_SX3 = 0x33,
- DBG_BLOCK_ID_UNUSED4 = 0x34,
- DBG_BLOCK_ID_UNUSED5 = 0x35,
- DBG_BLOCK_ID_UNUSED6 = 0x36,
- DBG_BLOCK_ID_UNUSED7 = 0x37,
- DBG_BLOCK_ID_PC0 = 0x38,
- DBG_BLOCK_ID_PC1 = 0x39,
- DBG_BLOCK_ID_UNUSED8 = 0x3a,
- DBG_BLOCK_ID_UNUSED9 = 0x3b,
- DBG_BLOCK_ID_UNUSED10 = 0x3c,
- DBG_BLOCK_ID_UNUSED11 = 0x3d,
- DBG_BLOCK_ID_MCB = 0x3e,
- DBG_BLOCK_ID_UNUSED12 = 0x3f,
- DBG_BLOCK_ID_SCB0 = 0x40,
- DBG_BLOCK_ID_SCB1 = 0x41,
- DBG_BLOCK_ID_UNUSED13 = 0x42,
- DBG_BLOCK_ID_UNUSED14 = 0x43,
- DBG_BLOCK_ID_SCF0 = 0x44,
- DBG_BLOCK_ID_SCF1 = 0x45,
- DBG_BLOCK_ID_UNUSED15 = 0x46,
- DBG_BLOCK_ID_UNUSED16 = 0x47,
- DBG_BLOCK_ID_BCI0 = 0x48,
- DBG_BLOCK_ID_BCI1 = 0x49,
- DBG_BLOCK_ID_BCI2 = 0x4a,
- DBG_BLOCK_ID_BCI3 = 0x4b,
- DBG_BLOCK_ID_UNUSED17 = 0x4c,
- DBG_BLOCK_ID_UNUSED18 = 0x4d,
- DBG_BLOCK_ID_UNUSED19 = 0x4e,
- DBG_BLOCK_ID_UNUSED20 = 0x4f,
- DBG_BLOCK_ID_CB00 = 0x50,
- DBG_BLOCK_ID_CB01 = 0x51,
- DBG_BLOCK_ID_CB02 = 0x52,
- DBG_BLOCK_ID_CB03 = 0x53,
- DBG_BLOCK_ID_CB04 = 0x54,
- DBG_BLOCK_ID_UNUSED21 = 0x55,
- DBG_BLOCK_ID_UNUSED22 = 0x56,
- DBG_BLOCK_ID_UNUSED23 = 0x57,
- DBG_BLOCK_ID_CB10 = 0x58,
- DBG_BLOCK_ID_CB11 = 0x59,
- DBG_BLOCK_ID_CB12 = 0x5a,
- DBG_BLOCK_ID_CB13 = 0x5b,
- DBG_BLOCK_ID_CB14 = 0x5c,
- DBG_BLOCK_ID_UNUSED24 = 0x5d,
- DBG_BLOCK_ID_UNUSED25 = 0x5e,
- DBG_BLOCK_ID_UNUSED26 = 0x5f,
- DBG_BLOCK_ID_TCP0 = 0x60,
- DBG_BLOCK_ID_TCP1 = 0x61,
- DBG_BLOCK_ID_TCP2 = 0x62,
- DBG_BLOCK_ID_TCP3 = 0x63,
- DBG_BLOCK_ID_TCP4 = 0x64,
- DBG_BLOCK_ID_TCP5 = 0x65,
- DBG_BLOCK_ID_TCP6 = 0x66,
- DBG_BLOCK_ID_TCP7 = 0x67,
- DBG_BLOCK_ID_TCP8 = 0x68,
- DBG_BLOCK_ID_TCP9 = 0x69,
- DBG_BLOCK_ID_TCP10 = 0x6a,
- DBG_BLOCK_ID_TCP11 = 0x6b,
- DBG_BLOCK_ID_TCP12 = 0x6c,
- DBG_BLOCK_ID_TCP13 = 0x6d,
- DBG_BLOCK_ID_TCP14 = 0x6e,
- DBG_BLOCK_ID_TCP15 = 0x6f,
- DBG_BLOCK_ID_TCP16 = 0x70,
- DBG_BLOCK_ID_TCP17 = 0x71,
- DBG_BLOCK_ID_TCP18 = 0x72,
- DBG_BLOCK_ID_TCP19 = 0x73,
- DBG_BLOCK_ID_TCP20 = 0x74,
- DBG_BLOCK_ID_TCP21 = 0x75,
- DBG_BLOCK_ID_TCP22 = 0x76,
- DBG_BLOCK_ID_TCP23 = 0x77,
- DBG_BLOCK_ID_TCP_RESERVED0 = 0x78,
- DBG_BLOCK_ID_TCP_RESERVED1 = 0x79,
- DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a,
- DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b,
- DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c,
- DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d,
- DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e,
- DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f,
- DBG_BLOCK_ID_DB00 = 0x80,
- DBG_BLOCK_ID_DB01 = 0x81,
- DBG_BLOCK_ID_DB02 = 0x82,
- DBG_BLOCK_ID_DB03 = 0x83,
- DBG_BLOCK_ID_DB04 = 0x84,
- DBG_BLOCK_ID_UNUSED27 = 0x85,
- DBG_BLOCK_ID_UNUSED28 = 0x86,
- DBG_BLOCK_ID_UNUSED29 = 0x87,
- DBG_BLOCK_ID_DB10 = 0x88,
- DBG_BLOCK_ID_DB11 = 0x89,
- DBG_BLOCK_ID_DB12 = 0x8a,
- DBG_BLOCK_ID_DB13 = 0x8b,
- DBG_BLOCK_ID_DB14 = 0x8c,
- DBG_BLOCK_ID_UNUSED30 = 0x8d,
- DBG_BLOCK_ID_UNUSED31 = 0x8e,
- DBG_BLOCK_ID_UNUSED32 = 0x8f,
- DBG_BLOCK_ID_TCC0 = 0x90,
- DBG_BLOCK_ID_TCC1 = 0x91,
- DBG_BLOCK_ID_TCC2 = 0x92,
- DBG_BLOCK_ID_TCC3 = 0x93,
- DBG_BLOCK_ID_TCC4 = 0x94,
- DBG_BLOCK_ID_TCC5 = 0x95,
- DBG_BLOCK_ID_TCC6 = 0x96,
- DBG_BLOCK_ID_TCC7 = 0x97,
- DBG_BLOCK_ID_SPS00 = 0x98,
- DBG_BLOCK_ID_SPS01 = 0x99,
- DBG_BLOCK_ID_SPS02 = 0x9a,
- DBG_BLOCK_ID_SPS10 = 0x9b,
- DBG_BLOCK_ID_SPS11 = 0x9c,
- DBG_BLOCK_ID_SPS12 = 0x9d,
- DBG_BLOCK_ID_UNUSED33 = 0x9e,
- DBG_BLOCK_ID_UNUSED34 = 0x9f,
- DBG_BLOCK_ID_TA00 = 0xa0,
- DBG_BLOCK_ID_TA01 = 0xa1,
- DBG_BLOCK_ID_TA02 = 0xa2,
- DBG_BLOCK_ID_TA03 = 0xa3,
- DBG_BLOCK_ID_TA04 = 0xa4,
- DBG_BLOCK_ID_TA05 = 0xa5,
- DBG_BLOCK_ID_TA06 = 0xa6,
- DBG_BLOCK_ID_TA07 = 0xa7,
- DBG_BLOCK_ID_TA08 = 0xa8,
- DBG_BLOCK_ID_TA09 = 0xa9,
- DBG_BLOCK_ID_TA0A = 0xaa,
- DBG_BLOCK_ID_TA0B = 0xab,
- DBG_BLOCK_ID_UNUSED35 = 0xac,
- DBG_BLOCK_ID_UNUSED36 = 0xad,
- DBG_BLOCK_ID_UNUSED37 = 0xae,
- DBG_BLOCK_ID_UNUSED38 = 0xaf,
- DBG_BLOCK_ID_TA10 = 0xb0,
- DBG_BLOCK_ID_TA11 = 0xb1,
- DBG_BLOCK_ID_TA12 = 0xb2,
- DBG_BLOCK_ID_TA13 = 0xb3,
- DBG_BLOCK_ID_TA14 = 0xb4,
- DBG_BLOCK_ID_TA15 = 0xb5,
- DBG_BLOCK_ID_TA16 = 0xb6,
- DBG_BLOCK_ID_TA17 = 0xb7,
- DBG_BLOCK_ID_TA18 = 0xb8,
- DBG_BLOCK_ID_TA19 = 0xb9,
- DBG_BLOCK_ID_TA1A = 0xba,
- DBG_BLOCK_ID_TA1B = 0xbb,
- DBG_BLOCK_ID_UNUSED39 = 0xbc,
- DBG_BLOCK_ID_UNUSED40 = 0xbd,
- DBG_BLOCK_ID_UNUSED41 = 0xbe,
- DBG_BLOCK_ID_UNUSED42 = 0xbf,
- DBG_BLOCK_ID_TD00 = 0xc0,
- DBG_BLOCK_ID_TD01 = 0xc1,
- DBG_BLOCK_ID_TD02 = 0xc2,
- DBG_BLOCK_ID_TD03 = 0xc3,
- DBG_BLOCK_ID_TD04 = 0xc4,
- DBG_BLOCK_ID_TD05 = 0xc5,
- DBG_BLOCK_ID_TD06 = 0xc6,
- DBG_BLOCK_ID_TD07 = 0xc7,
- DBG_BLOCK_ID_TD08 = 0xc8,
- DBG_BLOCK_ID_TD09 = 0xc9,
- DBG_BLOCK_ID_TD0A = 0xca,
- DBG_BLOCK_ID_TD0B = 0xcb,
- DBG_BLOCK_ID_UNUSED43 = 0xcc,
- DBG_BLOCK_ID_UNUSED44 = 0xcd,
- DBG_BLOCK_ID_UNUSED45 = 0xce,
- DBG_BLOCK_ID_UNUSED46 = 0xcf,
- DBG_BLOCK_ID_TD10 = 0xd0,
- DBG_BLOCK_ID_TD11 = 0xd1,
- DBG_BLOCK_ID_TD12 = 0xd2,
- DBG_BLOCK_ID_TD13 = 0xd3,
- DBG_BLOCK_ID_TD14 = 0xd4,
- DBG_BLOCK_ID_TD15 = 0xd5,
- DBG_BLOCK_ID_TD16 = 0xd6,
- DBG_BLOCK_ID_TD17 = 0xd7,
- DBG_BLOCK_ID_TD18 = 0xd8,
- DBG_BLOCK_ID_TD19 = 0xd9,
- DBG_BLOCK_ID_TD1A = 0xda,
- DBG_BLOCK_ID_TD1B = 0xdb,
- DBG_BLOCK_ID_UNUSED47 = 0xdc,
- DBG_BLOCK_ID_UNUSED48 = 0xdd,
- DBG_BLOCK_ID_UNUSED49 = 0xde,
- DBG_BLOCK_ID_UNUSED50 = 0xdf,
- DBG_BLOCK_ID_MCD0 = 0xe0,
- DBG_BLOCK_ID_MCD1 = 0xe1,
- DBG_BLOCK_ID_MCD2 = 0xe2,
- DBG_BLOCK_ID_MCD3 = 0xe3,
- DBG_BLOCK_ID_MCD4 = 0xe4,
- DBG_BLOCK_ID_MCD5 = 0xe5,
- DBG_BLOCK_ID_UNUSED51 = 0xe6,
- DBG_BLOCK_ID_UNUSED52 = 0xe7,
-} DebugBlockId_OLD;
-typedef enum DebugBlockId_BY2 {
- DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
- DBG_BLOCK_ID_VMC_BY2 = 0x1,
- DBG_BLOCK_ID_CG_BY2 = 0x2,
- DBG_BLOCK_ID_GRBM_BY2 = 0x3,
- DBG_BLOCK_ID_CSC_BY2 = 0x4,
- DBG_BLOCK_ID_IH_BY2 = 0x5,
- DBG_BLOCK_ID_SQ_BY2 = 0x6,
- DBG_BLOCK_ID_GMCON_BY2 = 0x7,
- DBG_BLOCK_ID_DMA0_BY2 = 0x8,
- DBG_BLOCK_ID_SPIM_BY2 = 0x9,
- DBG_BLOCK_ID_SPIS_BY2 = 0xa,
- DBG_BLOCK_ID_PA0_BY2 = 0xb,
- DBG_BLOCK_ID_CP0_BY2 = 0xc,
- DBG_BLOCK_ID_CP2_BY2 = 0xd,
- DBG_BLOCK_ID_UVDU_BY2 = 0xe,
- DBG_BLOCK_ID_VCE_BY2 = 0xf,
- DBG_BLOCK_ID_VGT0_BY2 = 0x10,
- DBG_BLOCK_ID_IA_BY2 = 0x11,
- DBG_BLOCK_ID_SCT0_BY2 = 0x12,
- DBG_BLOCK_ID_SPM0_BY2 = 0x13,
- DBG_BLOCK_ID_TCAA_BY2 = 0x14,
- DBG_BLOCK_ID_TCCA_BY2 = 0x15,
- DBG_BLOCK_ID_MCC0_BY2 = 0x16,
- DBG_BLOCK_ID_MCC2_BY2 = 0x17,
- DBG_BLOCK_ID_SX0_BY2 = 0x18,
- DBG_BLOCK_ID_SX2_BY2 = 0x19,
- DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a,
- DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b,
- DBG_BLOCK_ID_PC0_BY2 = 0x1c,
- DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d,
- DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e,
- DBG_BLOCK_ID_MCB_BY2 = 0x1f,
- DBG_BLOCK_ID_SCB0_BY2 = 0x20,
- DBG_BLOCK_ID_UNUSED13_BY2 = 0x21,
- DBG_BLOCK_ID_SCF0_BY2 = 0x22,
- DBG_BLOCK_ID_UNUSED15_BY2 = 0x23,
- DBG_BLOCK_ID_BCI0_BY2 = 0x24,
- DBG_BLOCK_ID_BCI2_BY2 = 0x25,
- DBG_BLOCK_ID_UNUSED17_BY2 = 0x26,
- DBG_BLOCK_ID_UNUSED19_BY2 = 0x27,
- DBG_BLOCK_ID_CB00_BY2 = 0x28,
- DBG_BLOCK_ID_CB02_BY2 = 0x29,
- DBG_BLOCK_ID_CB04_BY2 = 0x2a,
- DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b,
- DBG_BLOCK_ID_CB10_BY2 = 0x2c,
- DBG_BLOCK_ID_CB12_BY2 = 0x2d,
- DBG_BLOCK_ID_CB14_BY2 = 0x2e,
- DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f,
- DBG_BLOCK_ID_TCP0_BY2 = 0x30,
- DBG_BLOCK_ID_TCP2_BY2 = 0x31,
- DBG_BLOCK_ID_TCP4_BY2 = 0x32,
- DBG_BLOCK_ID_TCP6_BY2 = 0x33,
- DBG_BLOCK_ID_TCP8_BY2 = 0x34,
- DBG_BLOCK_ID_TCP10_BY2 = 0x35,
- DBG_BLOCK_ID_TCP12_BY2 = 0x36,
- DBG_BLOCK_ID_TCP14_BY2 = 0x37,
- DBG_BLOCK_ID_TCP16_BY2 = 0x38,
- DBG_BLOCK_ID_TCP18_BY2 = 0x39,
- DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
- DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
- DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
- DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
- DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
- DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
- DBG_BLOCK_ID_DB00_BY2 = 0x40,
- DBG_BLOCK_ID_DB02_BY2 = 0x41,
- DBG_BLOCK_ID_DB04_BY2 = 0x42,
- DBG_BLOCK_ID_UNUSED28_BY2 = 0x43,
- DBG_BLOCK_ID_DB10_BY2 = 0x44,
- DBG_BLOCK_ID_DB12_BY2 = 0x45,
- DBG_BLOCK_ID_DB14_BY2 = 0x46,
- DBG_BLOCK_ID_UNUSED31_BY2 = 0x47,
- DBG_BLOCK_ID_TCC0_BY2 = 0x48,
- DBG_BLOCK_ID_TCC2_BY2 = 0x49,
- DBG_BLOCK_ID_TCC4_BY2 = 0x4a,
- DBG_BLOCK_ID_TCC6_BY2 = 0x4b,
- DBG_BLOCK_ID_SPS00_BY2 = 0x4c,
- DBG_BLOCK_ID_SPS02_BY2 = 0x4d,
- DBG_BLOCK_ID_SPS11_BY2 = 0x4e,
- DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f,
- DBG_BLOCK_ID_TA00_BY2 = 0x50,
- DBG_BLOCK_ID_TA02_BY2 = 0x51,
- DBG_BLOCK_ID_TA04_BY2 = 0x52,
- DBG_BLOCK_ID_TA06_BY2 = 0x53,
- DBG_BLOCK_ID_TA08_BY2 = 0x54,
- DBG_BLOCK_ID_TA0A_BY2 = 0x55,
- DBG_BLOCK_ID_UNUSED35_BY2 = 0x56,
- DBG_BLOCK_ID_UNUSED37_BY2 = 0x57,
- DBG_BLOCK_ID_TA10_BY2 = 0x58,
- DBG_BLOCK_ID_TA12_BY2 = 0x59,
- DBG_BLOCK_ID_TA14_BY2 = 0x5a,
- DBG_BLOCK_ID_TA16_BY2 = 0x5b,
- DBG_BLOCK_ID_TA18_BY2 = 0x5c,
- DBG_BLOCK_ID_TA1A_BY2 = 0x5d,
- DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e,
- DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f,
- DBG_BLOCK_ID_TD00_BY2 = 0x60,
- DBG_BLOCK_ID_TD02_BY2 = 0x61,
- DBG_BLOCK_ID_TD04_BY2 = 0x62,
- DBG_BLOCK_ID_TD06_BY2 = 0x63,
- DBG_BLOCK_ID_TD08_BY2 = 0x64,
- DBG_BLOCK_ID_TD0A_BY2 = 0x65,
- DBG_BLOCK_ID_UNUSED43_BY2 = 0x66,
- DBG_BLOCK_ID_UNUSED45_BY2 = 0x67,
- DBG_BLOCK_ID_TD10_BY2 = 0x68,
- DBG_BLOCK_ID_TD12_BY2 = 0x69,
- DBG_BLOCK_ID_TD14_BY2 = 0x6a,
- DBG_BLOCK_ID_TD16_BY2 = 0x6b,
- DBG_BLOCK_ID_TD18_BY2 = 0x6c,
- DBG_BLOCK_ID_TD1A_BY2 = 0x6d,
- DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e,
- DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f,
- DBG_BLOCK_ID_MCD0_BY2 = 0x70,
- DBG_BLOCK_ID_MCD2_BY2 = 0x71,
- DBG_BLOCK_ID_MCD4_BY2 = 0x72,
- DBG_BLOCK_ID_UNUSED51_BY2 = 0x73,
-} DebugBlockId_BY2;
-typedef enum DebugBlockId_BY4 {
- DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
- DBG_BLOCK_ID_CG_BY4 = 0x1,
- DBG_BLOCK_ID_CSC_BY4 = 0x2,
- DBG_BLOCK_ID_SQ_BY4 = 0x3,
- DBG_BLOCK_ID_DMA0_BY4 = 0x4,
- DBG_BLOCK_ID_SPIS_BY4 = 0x5,
- DBG_BLOCK_ID_CP0_BY4 = 0x6,
- DBG_BLOCK_ID_UVDU_BY4 = 0x7,
- DBG_BLOCK_ID_VGT0_BY4 = 0x8,
- DBG_BLOCK_ID_SCT0_BY4 = 0x9,
- DBG_BLOCK_ID_TCAA_BY4 = 0xa,
- DBG_BLOCK_ID_MCC0_BY4 = 0xb,
- DBG_BLOCK_ID_SX0_BY4 = 0xc,
- DBG_BLOCK_ID_UNUSED4_BY4 = 0xd,
- DBG_BLOCK_ID_PC0_BY4 = 0xe,
- DBG_BLOCK_ID_UNUSED10_BY4 = 0xf,
- DBG_BLOCK_ID_SCB0_BY4 = 0x10,
- DBG_BLOCK_ID_SCF0_BY4 = 0x11,
- DBG_BLOCK_ID_BCI0_BY4 = 0x12,
- DBG_BLOCK_ID_UNUSED17_BY4 = 0x13,
- DBG_BLOCK_ID_CB00_BY4 = 0x14,
- DBG_BLOCK_ID_CB04_BY4 = 0x15,
- DBG_BLOCK_ID_CB10_BY4 = 0x16,
- DBG_BLOCK_ID_CB14_BY4 = 0x17,
- DBG_BLOCK_ID_TCP0_BY4 = 0x18,
- DBG_BLOCK_ID_TCP4_BY4 = 0x19,
- DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
- DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
- DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
- DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
- DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
- DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
- DBG_BLOCK_ID_DB_BY4 = 0x20,
- DBG_BLOCK_ID_DB04_BY4 = 0x21,
- DBG_BLOCK_ID_DB10_BY4 = 0x22,
- DBG_BLOCK_ID_DB14_BY4 = 0x23,
- DBG_BLOCK_ID_TCC0_BY4 = 0x24,
- DBG_BLOCK_ID_TCC4_BY4 = 0x25,
- DBG_BLOCK_ID_SPS00_BY4 = 0x26,
- DBG_BLOCK_ID_SPS11_BY4 = 0x27,
- DBG_BLOCK_ID_TA00_BY4 = 0x28,
- DBG_BLOCK_ID_TA04_BY4 = 0x29,
- DBG_BLOCK_ID_TA08_BY4 = 0x2a,
- DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b,
- DBG_BLOCK_ID_TA10_BY4 = 0x2c,
- DBG_BLOCK_ID_TA14_BY4 = 0x2d,
- DBG_BLOCK_ID_TA18_BY4 = 0x2e,
- DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f,
- DBG_BLOCK_ID_TD00_BY4 = 0x30,
- DBG_BLOCK_ID_TD04_BY4 = 0x31,
- DBG_BLOCK_ID_TD08_BY4 = 0x32,
- DBG_BLOCK_ID_UNUSED43_BY4 = 0x33,
- DBG_BLOCK_ID_TD10_BY4 = 0x34,
- DBG_BLOCK_ID_TD14_BY4 = 0x35,
- DBG_BLOCK_ID_TD18_BY4 = 0x36,
- DBG_BLOCK_ID_UNUSED47_BY4 = 0x37,
- DBG_BLOCK_ID_MCD0_BY4 = 0x38,
- DBG_BLOCK_ID_MCD4_BY4 = 0x39,
-} DebugBlockId_BY4;
-typedef enum DebugBlockId_BY8 {
- DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
- DBG_BLOCK_ID_CSC_BY8 = 0x1,
- DBG_BLOCK_ID_DMA0_BY8 = 0x2,
- DBG_BLOCK_ID_CP0_BY8 = 0x3,
- DBG_BLOCK_ID_VGT0_BY8 = 0x4,
- DBG_BLOCK_ID_TCAA_BY8 = 0x5,
- DBG_BLOCK_ID_SX0_BY8 = 0x6,
- DBG_BLOCK_ID_PC0_BY8 = 0x7,
- DBG_BLOCK_ID_SCB0_BY8 = 0x8,
- DBG_BLOCK_ID_BCI0_BY8 = 0x9,
- DBG_BLOCK_ID_CB00_BY8 = 0xa,
- DBG_BLOCK_ID_CB10_BY8 = 0xb,
- DBG_BLOCK_ID_TCP0_BY8 = 0xc,
- DBG_BLOCK_ID_TCP8_BY8 = 0xd,
- DBG_BLOCK_ID_TCP16_BY8 = 0xe,
- DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
- DBG_BLOCK_ID_DB00_BY8 = 0x10,
- DBG_BLOCK_ID_DB10_BY8 = 0x11,
- DBG_BLOCK_ID_TCC0_BY8 = 0x12,
- DBG_BLOCK_ID_SPS00_BY8 = 0x13,
- DBG_BLOCK_ID_TA00_BY8 = 0x14,
- DBG_BLOCK_ID_TA08_BY8 = 0x15,
- DBG_BLOCK_ID_TA10_BY8 = 0x16,
- DBG_BLOCK_ID_TA18_BY8 = 0x17,
- DBG_BLOCK_ID_TD00_BY8 = 0x18,
- DBG_BLOCK_ID_TD08_BY8 = 0x19,
- DBG_BLOCK_ID_TD10_BY8 = 0x1a,
- DBG_BLOCK_ID_TD18_BY8 = 0x1b,
- DBG_BLOCK_ID_MCD0_BY8 = 0x1c,
-} DebugBlockId_BY8;
-typedef enum DebugBlockId_BY16 {
- DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
- DBG_BLOCK_ID_DMA0_BY16 = 0x1,
- DBG_BLOCK_ID_VGT0_BY16 = 0x2,
- DBG_BLOCK_ID_SX0_BY16 = 0x3,
- DBG_BLOCK_ID_SCB0_BY16 = 0x4,
- DBG_BLOCK_ID_CB00_BY16 = 0x5,
- DBG_BLOCK_ID_TCP0_BY16 = 0x6,
- DBG_BLOCK_ID_TCP16_BY16 = 0x7,
- DBG_BLOCK_ID_DB00_BY16 = 0x8,
- DBG_BLOCK_ID_TCC0_BY16 = 0x9,
- DBG_BLOCK_ID_TA00_BY16 = 0xa,
- DBG_BLOCK_ID_TA10_BY16 = 0xb,
- DBG_BLOCK_ID_TD00_BY16 = 0xc,
- DBG_BLOCK_ID_TD10_BY16 = 0xd,
- DBG_BLOCK_ID_MCD0_BY16 = 0xe,
-} DebugBlockId_BY16;
-typedef enum ColorTransform {
- DCC_CT_AUTO = 0x0,
- DCC_CT_NONE = 0x1,
- ABGR_TO_A_BG_G_RB = 0x2,
- BGRA_TO_BG_G_RB_A = 0x3,
-} ColorTransform;
-typedef enum CompareRef {
- REF_NEVER = 0x0,
- REF_LESS = 0x1,
- REF_EQUAL = 0x2,
- REF_LEQUAL = 0x3,
- REF_GREATER = 0x4,
- REF_NOTEQUAL = 0x5,
- REF_GEQUAL = 0x6,
- REF_ALWAYS = 0x7,
-} CompareRef;
-typedef enum ReadSize {
- READ_256_BITS = 0x0,
- READ_512_BITS = 0x1,
-} ReadSize;
-typedef enum DepthFormat {
- DEPTH_INVALID = 0x0,
- DEPTH_16 = 0x1,
- DEPTH_X8_24 = 0x2,
- DEPTH_8_24 = 0x3,
- DEPTH_X8_24_FLOAT = 0x4,
- DEPTH_8_24_FLOAT = 0x5,
- DEPTH_32_FLOAT = 0x6,
- DEPTH_X24_8_32_FLOAT = 0x7,
-} DepthFormat;
-typedef enum ZFormat {
- Z_INVALID = 0x0,
- Z_16 = 0x1,
- Z_24 = 0x2,
- Z_32_FLOAT = 0x3,
-} ZFormat;
-typedef enum StencilFormat {
- STENCIL_INVALID = 0x0,
- STENCIL_8 = 0x1,
-} StencilFormat;
-typedef enum CmaskMode {
- CMASK_CLEAR_NONE = 0x0,
- CMASK_CLEAR_ONE = 0x1,
- CMASK_CLEAR_ALL = 0x2,
- CMASK_ANY_EXPANDED = 0x3,
- CMASK_ALPHA0_FRAG1 = 0x4,
- CMASK_ALPHA0_FRAG2 = 0x5,
- CMASK_ALPHA0_FRAG4 = 0x6,
- CMASK_ALPHA0_FRAGS = 0x7,
- CMASK_ALPHA1_FRAG1 = 0x8,
- CMASK_ALPHA1_FRAG2 = 0x9,
- CMASK_ALPHA1_FRAG4 = 0xa,
- CMASK_ALPHA1_FRAGS = 0xb,
- CMASK_ALPHAX_FRAG1 = 0xc,
- CMASK_ALPHAX_FRAG2 = 0xd,
- CMASK_ALPHAX_FRAG4 = 0xe,
- CMASK_ALPHAX_FRAGS = 0xf,
-} CmaskMode;
-typedef enum QuadExportFormat {
- EXPORT_UNUSED = 0x0,
- EXPORT_32_R = 0x1,
- EXPORT_32_GR = 0x2,
- EXPORT_32_AR = 0x3,
- EXPORT_FP16_ABGR = 0x4,
- EXPORT_UNSIGNED16_ABGR = 0x5,
- EXPORT_SIGNED16_ABGR = 0x6,
- EXPORT_32_ABGR = 0x7,
-} QuadExportFormat;
-typedef enum QuadExportFormatOld {
- EXPORT_4P_32BPC_ABGR = 0x0,
- EXPORT_4P_16BPC_ABGR = 0x1,
- EXPORT_4P_32BPC_GR = 0x2,
- EXPORT_4P_32BPC_AR = 0x3,
- EXPORT_2P_32BPC_ABGR = 0x4,
- EXPORT_8P_32BPC_R = 0x5,
-} QuadExportFormatOld;
-typedef enum ColorFormat {
- COLOR_INVALID = 0x0,
- COLOR_8 = 0x1,
- COLOR_16 = 0x2,
- COLOR_8_8 = 0x3,
- COLOR_32 = 0x4,
- COLOR_16_16 = 0x5,
- COLOR_10_11_11 = 0x6,
- COLOR_11_11_10 = 0x7,
- COLOR_10_10_10_2 = 0x8,
- COLOR_2_10_10_10 = 0x9,
- COLOR_8_8_8_8 = 0xa,
- COLOR_32_32 = 0xb,
- COLOR_16_16_16_16 = 0xc,
- COLOR_RESERVED_13 = 0xd,
- COLOR_32_32_32_32 = 0xe,
- COLOR_RESERVED_15 = 0xf,
- COLOR_5_6_5 = 0x10,
- COLOR_1_5_5_5 = 0x11,
- COLOR_5_5_5_1 = 0x12,
- COLOR_4_4_4_4 = 0x13,
- COLOR_8_24 = 0x14,
- COLOR_24_8 = 0x15,
- COLOR_X24_8_32_FLOAT = 0x16,
- COLOR_RESERVED_23 = 0x17,
-} ColorFormat;
-typedef enum SurfaceFormat {
- FMT_INVALID = 0x0,
- FMT_8 = 0x1,
- FMT_16 = 0x2,
- FMT_8_8 = 0x3,
- FMT_32 = 0x4,
- FMT_16_16 = 0x5,
- FMT_10_11_11 = 0x6,
- FMT_11_11_10 = 0x7,
- FMT_10_10_10_2 = 0x8,
- FMT_2_10_10_10 = 0x9,
- FMT_8_8_8_8 = 0xa,
- FMT_32_32 = 0xb,
- FMT_16_16_16_16 = 0xc,
- FMT_32_32_32 = 0xd,
- FMT_32_32_32_32 = 0xe,
- FMT_RESERVED_4 = 0xf,
- FMT_5_6_5 = 0x10,
- FMT_1_5_5_5 = 0x11,
- FMT_5_5_5_1 = 0x12,
- FMT_4_4_4_4 = 0x13,
- FMT_8_24 = 0x14,
- FMT_24_8 = 0x15,
- FMT_X24_8_32_FLOAT = 0x16,
- FMT_RESERVED_33 = 0x17,
- FMT_11_11_10_FLOAT = 0x18,
- FMT_16_FLOAT = 0x19,
- FMT_32_FLOAT = 0x1a,
- FMT_16_16_FLOAT = 0x1b,
- FMT_8_24_FLOAT = 0x1c,
- FMT_24_8_FLOAT = 0x1d,
- FMT_32_32_FLOAT = 0x1e,
- FMT_10_11_11_FLOAT = 0x1f,
- FMT_16_16_16_16_FLOAT = 0x20,
- FMT_3_3_2 = 0x21,
- FMT_6_5_5 = 0x22,
- FMT_32_32_32_32_FLOAT = 0x23,
- FMT_RESERVED_36 = 0x24,
- FMT_1 = 0x25,
- FMT_1_REVERSED = 0x26,
- FMT_GB_GR = 0x27,
- FMT_BG_RG = 0x28,
- FMT_32_AS_8 = 0x29,
- FMT_32_AS_8_8 = 0x2a,
- FMT_5_9_9_9_SHAREDEXP = 0x2b,
- FMT_8_8_8 = 0x2c,
- FMT_16_16_16 = 0x2d,
- FMT_16_16_16_FLOAT = 0x2e,
- FMT_4_4 = 0x2f,
- FMT_32_32_32_FLOAT = 0x30,
- FMT_BC1 = 0x31,
- FMT_BC2 = 0x32,
- FMT_BC3 = 0x33,
- FMT_BC4 = 0x34,
- FMT_BC5 = 0x35,
- FMT_BC6 = 0x36,
- FMT_BC7 = 0x37,
- FMT_32_AS_32_32_32_32 = 0x38,
- FMT_APC3 = 0x39,
- FMT_APC4 = 0x3a,
- FMT_APC5 = 0x3b,
- FMT_APC6 = 0x3c,
- FMT_APC7 = 0x3d,
- FMT_CTX1 = 0x3e,
- FMT_RESERVED_63 = 0x3f,
-} SurfaceFormat;
-typedef enum BUF_DATA_FORMAT {
- BUF_DATA_FORMAT_INVALID = 0x0,
- BUF_DATA_FORMAT_8 = 0x1,
- BUF_DATA_FORMAT_16 = 0x2,
- BUF_DATA_FORMAT_8_8 = 0x3,
- BUF_DATA_FORMAT_32 = 0x4,
- BUF_DATA_FORMAT_16_16 = 0x5,
- BUF_DATA_FORMAT_10_11_11 = 0x6,
- BUF_DATA_FORMAT_11_11_10 = 0x7,
- BUF_DATA_FORMAT_10_10_10_2 = 0x8,
- BUF_DATA_FORMAT_2_10_10_10 = 0x9,
- BUF_DATA_FORMAT_8_8_8_8 = 0xa,
- BUF_DATA_FORMAT_32_32 = 0xb,
- BUF_DATA_FORMAT_16_16_16_16 = 0xc,
- BUF_DATA_FORMAT_32_32_32 = 0xd,
- BUF_DATA_FORMAT_32_32_32_32 = 0xe,
- BUF_DATA_FORMAT_RESERVED_15 = 0xf,
-} BUF_DATA_FORMAT;
-typedef enum IMG_DATA_FORMAT {
- IMG_DATA_FORMAT_INVALID = 0x0,
- IMG_DATA_FORMAT_8 = 0x1,
- IMG_DATA_FORMAT_16 = 0x2,
- IMG_DATA_FORMAT_8_8 = 0x3,
- IMG_DATA_FORMAT_32 = 0x4,
- IMG_DATA_FORMAT_16_16 = 0x5,
- IMG_DATA_FORMAT_10_11_11 = 0x6,
- IMG_DATA_FORMAT_11_11_10 = 0x7,
- IMG_DATA_FORMAT_10_10_10_2 = 0x8,
- IMG_DATA_FORMAT_2_10_10_10 = 0x9,
- IMG_DATA_FORMAT_8_8_8_8 = 0xa,
- IMG_DATA_FORMAT_32_32 = 0xb,
- IMG_DATA_FORMAT_16_16_16_16 = 0xc,
- IMG_DATA_FORMAT_32_32_32 = 0xd,
- IMG_DATA_FORMAT_32_32_32_32 = 0xe,
- IMG_DATA_FORMAT_RESERVED_15 = 0xf,
- IMG_DATA_FORMAT_5_6_5 = 0x10,
- IMG_DATA_FORMAT_1_5_5_5 = 0x11,
- IMG_DATA_FORMAT_5_5_5_1 = 0x12,
- IMG_DATA_FORMAT_4_4_4_4 = 0x13,
- IMG_DATA_FORMAT_8_24 = 0x14,
- IMG_DATA_FORMAT_24_8 = 0x15,
- IMG_DATA_FORMAT_X24_8_32 = 0x16,
- IMG_DATA_FORMAT_RESERVED_23 = 0x17,
- IMG_DATA_FORMAT_RESERVED_24 = 0x18,
- IMG_DATA_FORMAT_RESERVED_25 = 0x19,
- IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
- IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
- IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
- IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
- IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
- IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
- IMG_DATA_FORMAT_GB_GR = 0x20,
- IMG_DATA_FORMAT_BG_RG = 0x21,
- IMG_DATA_FORMAT_5_9_9_9 = 0x22,
- IMG_DATA_FORMAT_BC1 = 0x23,
- IMG_DATA_FORMAT_BC2 = 0x24,
- IMG_DATA_FORMAT_BC3 = 0x25,
- IMG_DATA_FORMAT_BC4 = 0x26,
- IMG_DATA_FORMAT_BC5 = 0x27,
- IMG_DATA_FORMAT_BC6 = 0x28,
- IMG_DATA_FORMAT_BC7 = 0x29,
- IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
- IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
- IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
- IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
- IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
- IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
- IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
- IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
- IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
- IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
- IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
- IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
- IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
- IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
- IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
- IMG_DATA_FORMAT_4_4 = 0x39,
- IMG_DATA_FORMAT_6_5_5 = 0x3a,
- IMG_DATA_FORMAT_1 = 0x3b,
- IMG_DATA_FORMAT_1_REVERSED = 0x3c,
- IMG_DATA_FORMAT_32_AS_8 = 0x3d,
- IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
- IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
-} IMG_DATA_FORMAT;
-typedef enum BUF_NUM_FORMAT {
- BUF_NUM_FORMAT_UNORM = 0x0,
- BUF_NUM_FORMAT_SNORM = 0x1,
- BUF_NUM_FORMAT_USCALED = 0x2,
- BUF_NUM_FORMAT_SSCALED = 0x3,
- BUF_NUM_FORMAT_UINT = 0x4,
- BUF_NUM_FORMAT_SINT = 0x5,
- BUF_NUM_FORMAT_RESERVED_6 = 0x6,
- BUF_NUM_FORMAT_FLOAT = 0x7,
-} BUF_NUM_FORMAT;
-typedef enum IMG_NUM_FORMAT {
- IMG_NUM_FORMAT_UNORM = 0x0,
- IMG_NUM_FORMAT_SNORM = 0x1,
- IMG_NUM_FORMAT_USCALED = 0x2,
- IMG_NUM_FORMAT_SSCALED = 0x3,
- IMG_NUM_FORMAT_UINT = 0x4,
- IMG_NUM_FORMAT_SINT = 0x5,
- IMG_NUM_FORMAT_RESERVED_6 = 0x6,
- IMG_NUM_FORMAT_FLOAT = 0x7,
- IMG_NUM_FORMAT_RESERVED_8 = 0x8,
- IMG_NUM_FORMAT_SRGB = 0x9,
- IMG_NUM_FORMAT_RESERVED_10 = 0xa,
- IMG_NUM_FORMAT_RESERVED_11 = 0xb,
- IMG_NUM_FORMAT_RESERVED_12 = 0xc,
- IMG_NUM_FORMAT_RESERVED_13 = 0xd,
- IMG_NUM_FORMAT_RESERVED_14 = 0xe,
- IMG_NUM_FORMAT_RESERVED_15 = 0xf,
-} IMG_NUM_FORMAT;
-typedef enum TileType {
- ARRAY_COLOR_TILE = 0x0,
- ARRAY_DEPTH_TILE = 0x1,
-} TileType;
-typedef enum NonDispTilingOrder {
- ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
- ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
-} NonDispTilingOrder;
-typedef enum MicroTileMode {
- ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
- ADDR_SURF_THIN_MICRO_TILING = 0x1,
- ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
- ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
- ADDR_SURF_THICK_MICRO_TILING = 0x4,
-} MicroTileMode;
-typedef enum TileSplit {
- ADDR_SURF_TILE_SPLIT_64B = 0x0,
- ADDR_SURF_TILE_SPLIT_128B = 0x1,
- ADDR_SURF_TILE_SPLIT_256B = 0x2,
- ADDR_SURF_TILE_SPLIT_512B = 0x3,
- ADDR_SURF_TILE_SPLIT_1KB = 0x4,
- ADDR_SURF_TILE_SPLIT_2KB = 0x5,
- ADDR_SURF_TILE_SPLIT_4KB = 0x6,
-} TileSplit;
-typedef enum SampleSplit {
- ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
- ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
- ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
- ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
-} SampleSplit;
-typedef enum PipeConfig {
- ADDR_SURF_P2 = 0x0,
- ADDR_SURF_P2_RESERVED0 = 0x1,
- ADDR_SURF_P2_RESERVED1 = 0x2,
- ADDR_SURF_P2_RESERVED2 = 0x3,
- ADDR_SURF_P4_8x16 = 0x4,
- ADDR_SURF_P4_16x16 = 0x5,
- ADDR_SURF_P4_16x32 = 0x6,
- ADDR_SURF_P4_32x32 = 0x7,
- ADDR_SURF_P8_16x16_8x16 = 0x8,
- ADDR_SURF_P8_16x32_8x16 = 0x9,
- ADDR_SURF_P8_32x32_8x16 = 0xa,
- ADDR_SURF_P8_16x32_16x16 = 0xb,
- ADDR_SURF_P8_32x32_16x16 = 0xc,
- ADDR_SURF_P8_32x32_16x32 = 0xd,
- ADDR_SURF_P8_32x64_32x32 = 0xe,
- ADDR_SURF_P8_RESERVED0 = 0xf,
- ADDR_SURF_P16_32x32_8x16 = 0x10,
- ADDR_SURF_P16_32x32_16x16 = 0x11,
-} PipeConfig;
-typedef enum NumBanks {
- ADDR_SURF_2_BANK = 0x0,
- ADDR_SURF_4_BANK = 0x1,
- ADDR_SURF_8_BANK = 0x2,
- ADDR_SURF_16_BANK = 0x3,
-} NumBanks;
-typedef enum BankWidth {
- ADDR_SURF_BANK_WIDTH_1 = 0x0,
- ADDR_SURF_BANK_WIDTH_2 = 0x1,
- ADDR_SURF_BANK_WIDTH_4 = 0x2,
- ADDR_SURF_BANK_WIDTH_8 = 0x3,
-} BankWidth;
-typedef enum BankHeight {
- ADDR_SURF_BANK_HEIGHT_1 = 0x0,
- ADDR_SURF_BANK_HEIGHT_2 = 0x1,
- ADDR_SURF_BANK_HEIGHT_4 = 0x2,
- ADDR_SURF_BANK_HEIGHT_8 = 0x3,
-} BankHeight;
-typedef enum BankWidthHeight {
- ADDR_SURF_BANK_WH_1 = 0x0,
- ADDR_SURF_BANK_WH_2 = 0x1,
- ADDR_SURF_BANK_WH_4 = 0x2,
- ADDR_SURF_BANK_WH_8 = 0x3,
-} BankWidthHeight;
-typedef enum MacroTileAspect {
- ADDR_SURF_MACRO_ASPECT_1 = 0x0,
- ADDR_SURF_MACRO_ASPECT_2 = 0x1,
- ADDR_SURF_MACRO_ASPECT_4 = 0x2,
- ADDR_SURF_MACRO_ASPECT_8 = 0x3,
-} MacroTileAspect;
-typedef enum GATCL1RequestType {
- GATCL1_TYPE_NORMAL = 0x0,
- GATCL1_TYPE_SHOOTDOWN = 0x1,
- GATCL1_TYPE_BYPASS = 0x2,
-} GATCL1RequestType;
-typedef enum TCC_CACHE_POLICIES {
- TCC_CACHE_POLICY_LRU = 0x0,
- TCC_CACHE_POLICY_STREAM = 0x1,
-} TCC_CACHE_POLICIES;
-typedef enum MTYPE {
- MTYPE_NC_NV = 0x0,
- MTYPE_NC = 0x1,
- MTYPE_CC = 0x2,
- MTYPE_UC = 0x3,
-} MTYPE;
-typedef enum PERFMON_COUNTER_MODE {
- PERFMON_COUNTER_MODE_ACCUM = 0x0,
- PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
- PERFMON_COUNTER_MODE_MAX = 0x2,
- PERFMON_COUNTER_MODE_DIRTY = 0x3,
- PERFMON_COUNTER_MODE_SAMPLE = 0x4,
- PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
- PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
- PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
- PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
- PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
- PERFMON_COUNTER_MODE_RESERVED = 0xf,
-} PERFMON_COUNTER_MODE;
-typedef enum PERFMON_SPM_MODE {
- PERFMON_SPM_MODE_OFF = 0x0,
- PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
- PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
- PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
- PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
- PERFMON_SPM_MODE_RESERVED_5 = 0x5,
- PERFMON_SPM_MODE_RESERVED_6 = 0x6,
- PERFMON_SPM_MODE_RESERVED_7 = 0x7,
- PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
- PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
- PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
-} PERFMON_SPM_MODE;
-typedef enum SurfaceTiling {
- ARRAY_LINEAR = 0x0,
- ARRAY_TILED = 0x1,
-} SurfaceTiling;
-typedef enum SurfaceArray {
- ARRAY_1D = 0x0,
- ARRAY_2D = 0x1,
- ARRAY_3D = 0x2,
- ARRAY_3D_SLICE = 0x3,
-} SurfaceArray;
-typedef enum ColorArray {
- ARRAY_2D_ALT_COLOR = 0x0,
- ARRAY_2D_COLOR = 0x1,
- ARRAY_3D_SLICE_COLOR = 0x3,
-} ColorArray;
-typedef enum DepthArray {
- ARRAY_2D_ALT_DEPTH = 0x0,
- ARRAY_2D_DEPTH = 0x1,
-} DepthArray;
-typedef enum ENUM_NUM_SIMD_PER_CU {
- NUM_SIMD_PER_CU = 0x4,
-} ENUM_NUM_SIMD_PER_CU;
-typedef enum MEM_PWR_FORCE_CTRL {
- NO_FORCE_REQUEST = 0x0,
- FORCE_LIGHT_SLEEP_REQUEST = 0x1,
- FORCE_DEEP_SLEEP_REQUEST = 0x2,
- FORCE_SHUT_DOWN_REQUEST = 0x3,
-} MEM_PWR_FORCE_CTRL;
-typedef enum MEM_PWR_FORCE_CTRL2 {
- NO_FORCE_REQ = 0x0,
- FORCE_LIGHT_SLEEP_REQ = 0x1,
-} MEM_PWR_FORCE_CTRL2;
-typedef enum MEM_PWR_DIS_CTRL {
- ENABLE_MEM_PWR_CTRL = 0x0,
- DISABLE_MEM_PWR_CTRL = 0x1,
-} MEM_PWR_DIS_CTRL;
-typedef enum MEM_PWR_SEL_CTRL {
- DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
- DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
- DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
-} MEM_PWR_SEL_CTRL;
-typedef enum MEM_PWR_SEL_CTRL2 {
- DYNAMIC_DEEP_SLEEP_EN = 0x0,
- DYNAMIC_LIGHT_SLEEP_EN = 0x1,
-} MEM_PWR_SEL_CTRL2;
-
-#endif /* OSS_3_0_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_1_offset.h
deleted file mode 100644
index 54503d2bc..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_1_offset.h
+++ /dev/null
@@ -1,337 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _osssys_4_0_1_OFFSET_HEADER
-#define _osssys_4_0_1_OFFSET_HEADER
-
-
-
-// addressBlock: osssys_osssysdec
-// base address: 0x4280
-#define mmIH_VMID_0_LUT 0x0000
-#define mmIH_VMID_0_LUT_BASE_IDX 0
-#define mmIH_VMID_1_LUT 0x0001
-#define mmIH_VMID_1_LUT_BASE_IDX 0
-#define mmIH_VMID_2_LUT 0x0002
-#define mmIH_VMID_2_LUT_BASE_IDX 0
-#define mmIH_VMID_3_LUT 0x0003
-#define mmIH_VMID_3_LUT_BASE_IDX 0
-#define mmIH_VMID_4_LUT 0x0004
-#define mmIH_VMID_4_LUT_BASE_IDX 0
-#define mmIH_VMID_5_LUT 0x0005
-#define mmIH_VMID_5_LUT_BASE_IDX 0
-#define mmIH_VMID_6_LUT 0x0006
-#define mmIH_VMID_6_LUT_BASE_IDX 0
-#define mmIH_VMID_7_LUT 0x0007
-#define mmIH_VMID_7_LUT_BASE_IDX 0
-#define mmIH_VMID_8_LUT 0x0008
-#define mmIH_VMID_8_LUT_BASE_IDX 0
-#define mmIH_VMID_9_LUT 0x0009
-#define mmIH_VMID_9_LUT_BASE_IDX 0
-#define mmIH_VMID_10_LUT 0x000a
-#define mmIH_VMID_10_LUT_BASE_IDX 0
-#define mmIH_VMID_11_LUT 0x000b
-#define mmIH_VMID_11_LUT_BASE_IDX 0
-#define mmIH_VMID_12_LUT 0x000c
-#define mmIH_VMID_12_LUT_BASE_IDX 0
-#define mmIH_VMID_13_LUT 0x000d
-#define mmIH_VMID_13_LUT_BASE_IDX 0
-#define mmIH_VMID_14_LUT 0x000e
-#define mmIH_VMID_14_LUT_BASE_IDX 0
-#define mmIH_VMID_15_LUT 0x000f
-#define mmIH_VMID_15_LUT_BASE_IDX 0
-#define mmIH_VMID_0_LUT_MM 0x0010
-#define mmIH_VMID_0_LUT_MM_BASE_IDX 0
-#define mmIH_VMID_1_LUT_MM 0x0011
-#define mmIH_VMID_1_LUT_MM_BASE_IDX 0
-#define mmIH_VMID_2_LUT_MM 0x0012
-#define mmIH_VMID_2_LUT_MM_BASE_IDX 0
-#define mmIH_VMID_3_LUT_MM 0x0013
-#define mmIH_VMID_3_LUT_MM_BASE_IDX 0
-#define mmIH_VMID_4_LUT_MM 0x0014
-#define mmIH_VMID_4_LUT_MM_BASE_IDX 0
-#define mmIH_VMID_5_LUT_MM 0x0015
-#define mmIH_VMID_5_LUT_MM_BASE_IDX 0
-#define mmIH_VMID_6_LUT_MM 0x0016
-#define mmIH_VMID_6_LUT_MM_BASE_IDX 0
-#define mmIH_VMID_7_LUT_MM 0x0017
-#define mmIH_VMID_7_LUT_MM_BASE_IDX 0
-#define mmIH_VMID_8_LUT_MM 0x0018
-#define mmIH_VMID_8_LUT_MM_BASE_IDX 0
-#define mmIH_VMID_9_LUT_MM 0x0019
-#define mmIH_VMID_9_LUT_MM_BASE_IDX 0
-#define mmIH_VMID_10_LUT_MM 0x001a
-#define mmIH_VMID_10_LUT_MM_BASE_IDX 0
-#define mmIH_VMID_11_LUT_MM 0x001b
-#define mmIH_VMID_11_LUT_MM_BASE_IDX 0
-#define mmIH_VMID_12_LUT_MM 0x001c
-#define mmIH_VMID_12_LUT_MM_BASE_IDX 0
-#define mmIH_VMID_13_LUT_MM 0x001d
-#define mmIH_VMID_13_LUT_MM_BASE_IDX 0
-#define mmIH_VMID_14_LUT_MM 0x001e
-#define mmIH_VMID_14_LUT_MM_BASE_IDX 0
-#define mmIH_VMID_15_LUT_MM 0x001f
-#define mmIH_VMID_15_LUT_MM_BASE_IDX 0
-#define mmIH_COOKIE_0 0x0020
-#define mmIH_COOKIE_0_BASE_IDX 0
-#define mmIH_COOKIE_1 0x0021
-#define mmIH_COOKIE_1_BASE_IDX 0
-#define mmIH_COOKIE_2 0x0022
-#define mmIH_COOKIE_2_BASE_IDX 0
-#define mmIH_COOKIE_3 0x0023
-#define mmIH_COOKIE_3_BASE_IDX 0
-#define mmIH_COOKIE_4 0x0024
-#define mmIH_COOKIE_4_BASE_IDX 0
-#define mmIH_COOKIE_5 0x0025
-#define mmIH_COOKIE_5_BASE_IDX 0
-#define mmIH_COOKIE_6 0x0026
-#define mmIH_COOKIE_6_BASE_IDX 0
-#define mmIH_COOKIE_7 0x0027
-#define mmIH_COOKIE_7_BASE_IDX 0
-#define mmIH_REGISTER_LAST_PART0 0x003f
-#define mmIH_REGISTER_LAST_PART0_BASE_IDX 0
-#define mmSEM_REQ_INPUT_0 0x0040
-#define mmSEM_REQ_INPUT_0_BASE_IDX 0
-#define mmSEM_REQ_INPUT_1 0x0041
-#define mmSEM_REQ_INPUT_1_BASE_IDX 0
-#define mmSEM_REQ_INPUT_2 0x0042
-#define mmSEM_REQ_INPUT_2_BASE_IDX 0
-#define mmSEM_REQ_INPUT_3 0x0043
-#define mmSEM_REQ_INPUT_3_BASE_IDX 0
-#define mmSEM_REGISTER_LAST_PART0 0x007f
-#define mmSEM_REGISTER_LAST_PART0_BASE_IDX 0
-#define mmIH_RB_CNTL 0x0080
-#define mmIH_RB_CNTL_BASE_IDX 0
-#define mmIH_RB_BASE 0x0081
-#define mmIH_RB_BASE_BASE_IDX 0
-#define mmIH_RB_BASE_HI 0x0082
-#define mmIH_RB_BASE_HI_BASE_IDX 0
-#define mmIH_RB_RPTR 0x0083
-#define mmIH_RB_RPTR_BASE_IDX 0
-#define mmIH_RB_WPTR 0x0084
-#define mmIH_RB_WPTR_BASE_IDX 0
-#define mmIH_RB_WPTR_ADDR_HI 0x0085
-#define mmIH_RB_WPTR_ADDR_HI_BASE_IDX 0
-#define mmIH_RB_WPTR_ADDR_LO 0x0086
-#define mmIH_RB_WPTR_ADDR_LO_BASE_IDX 0
-#define mmIH_DOORBELL_RPTR 0x0087
-#define mmIH_DOORBELL_RPTR_BASE_IDX 0
-#define mmIH_RB_CNTL_RING1 0x0088
-#define mmIH_RB_CNTL_RING1_BASE_IDX 0
-#define mmIH_RB_BASE_RING1 0x0089
-#define mmIH_RB_BASE_RING1_BASE_IDX 0
-#define mmIH_RB_BASE_HI_RING1 0x008a
-#define mmIH_RB_BASE_HI_RING1_BASE_IDX 0
-#define mmIH_RB_RPTR_RING1 0x008b
-#define mmIH_RB_RPTR_RING1_BASE_IDX 0
-#define mmIH_RB_WPTR_RING1 0x008c
-#define mmIH_RB_WPTR_RING1_BASE_IDX 0
-#define mmIH_DOORBELL_RPTR_RING1 0x008f
-#define mmIH_DOORBELL_RPTR_RING1_BASE_IDX 0
-#define mmIH_RB_CNTL_RING2 0x0090
-#define mmIH_RB_CNTL_RING2_BASE_IDX 0
-#define mmIH_RB_BASE_RING2 0x0091
-#define mmIH_RB_BASE_RING2_BASE_IDX 0
-#define mmIH_RB_BASE_HI_RING2 0x0092
-#define mmIH_RB_BASE_HI_RING2_BASE_IDX 0
-#define mmIH_RB_RPTR_RING2 0x0093
-#define mmIH_RB_RPTR_RING2_BASE_IDX 0
-#define mmIH_RB_WPTR_RING2 0x0094
-#define mmIH_RB_WPTR_RING2_BASE_IDX 0
-#define mmIH_DOORBELL_RPTR_RING2 0x0097
-#define mmIH_DOORBELL_RPTR_RING2_BASE_IDX 0
-#define mmIH_VERSION 0x0098
-#define mmIH_VERSION_BASE_IDX 0
-#define mmIH_CNTL 0x00c0
-#define mmIH_CNTL_BASE_IDX 0
-#define mmIH_CNTL2 0x00c1
-#define mmIH_CNTL2_BASE_IDX 0
-#define mmIH_STATUS 0x00c2
-#define mmIH_STATUS_BASE_IDX 0
-#define mmIH_PERFMON_CNTL 0x00c3
-#define mmIH_PERFMON_CNTL_BASE_IDX 0
-#define mmIH_PERFCOUNTER0_RESULT 0x00c4
-#define mmIH_PERFCOUNTER0_RESULT_BASE_IDX 0
-#define mmIH_PERFCOUNTER1_RESULT 0x00c5
-#define mmIH_PERFCOUNTER1_RESULT_BASE_IDX 0
-#define mmIH_DSM_MATCH_VALUE_BIT_31_0 0x00c7
-#define mmIH_DSM_MATCH_VALUE_BIT_31_0_BASE_IDX 0
-#define mmIH_DSM_MATCH_VALUE_BIT_63_32 0x00c8
-#define mmIH_DSM_MATCH_VALUE_BIT_63_32_BASE_IDX 0
-#define mmIH_DSM_MATCH_VALUE_BIT_95_64 0x00c9
-#define mmIH_DSM_MATCH_VALUE_BIT_95_64_BASE_IDX 0
-#define mmIH_DSM_MATCH_FIELD_CONTROL 0x00ca
-#define mmIH_DSM_MATCH_FIELD_CONTROL_BASE_IDX 0
-#define mmIH_DSM_MATCH_DATA_CONTROL 0x00cb
-#define mmIH_DSM_MATCH_DATA_CONTROL_BASE_IDX 0
-#define mmIH_DSM_MATCH_FCN_ID 0x00cc
-#define mmIH_DSM_MATCH_FCN_ID_BASE_IDX 0
-#define mmIH_LIMIT_INT_RATE_CNTL 0x00cd
-#define mmIH_LIMIT_INT_RATE_CNTL_BASE_IDX 0
-#define mmIH_VF_RB_STATUS 0x00ce
-#define mmIH_VF_RB_STATUS_BASE_IDX 0
-#define mmIH_VF_RB_STATUS2 0x00cf
-#define mmIH_VF_RB_STATUS2_BASE_IDX 0
-#define mmIH_VF_RB1_STATUS 0x00d0
-#define mmIH_VF_RB1_STATUS_BASE_IDX 0
-#define mmIH_VF_RB1_STATUS2 0x00d1
-#define mmIH_VF_RB1_STATUS2_BASE_IDX 0
-#define mmIH_VF_RB2_STATUS 0x00d2
-#define mmIH_VF_RB2_STATUS_BASE_IDX 0
-#define mmIH_VF_RB2_STATUS2 0x00d3
-#define mmIH_VF_RB2_STATUS2_BASE_IDX 0
-#define mmIH_INT_FLOOD_CNTL 0x00d5
-#define mmIH_INT_FLOOD_CNTL_BASE_IDX 0
-#define mmIH_RB0_INT_FLOOD_STATUS 0x00d6
-#define mmIH_RB0_INT_FLOOD_STATUS_BASE_IDX 0
-#define mmIH_RB1_INT_FLOOD_STATUS 0x00d7
-#define mmIH_RB1_INT_FLOOD_STATUS_BASE_IDX 0
-#define mmIH_RB2_INT_FLOOD_STATUS 0x00d8
-#define mmIH_RB2_INT_FLOOD_STATUS_BASE_IDX 0
-#define mmIH_INT_FLOOD_STATUS 0x00d9
-#define mmIH_INT_FLOOD_STATUS_BASE_IDX 0
-#define mmIH_STORM_CLIENT_LIST_CNTL 0x00da
-#define mmIH_STORM_CLIENT_LIST_CNTL_BASE_IDX 0
-#define mmIH_CLK_CTRL 0x00db
-#define mmIH_CLK_CTRL_BASE_IDX 0
-#define mmIH_INT_FLAGS 0x00dc
-#define mmIH_INT_FLAGS_BASE_IDX 0
-#define mmIH_LAST_INT_INFO0 0x00dd
-#define mmIH_LAST_INT_INFO0_BASE_IDX 0
-#define mmIH_LAST_INT_INFO1 0x00de
-#define mmIH_LAST_INT_INFO1_BASE_IDX 0
-#define mmIH_LAST_INT_INFO2 0x00df
-#define mmIH_LAST_INT_INFO2_BASE_IDX 0
-#define mmIH_SCRATCH 0x00e0
-#define mmIH_SCRATCH_BASE_IDX 0
-#define mmIH_CLIENT_CREDIT_ERROR 0x00e1
-#define mmIH_CLIENT_CREDIT_ERROR_BASE_IDX 0
-#define mmIH_GPU_IOV_VIOLATION_LOG 0x00e2
-#define mmIH_GPU_IOV_VIOLATION_LOG_BASE_IDX 0
-#define mmIH_COOKIE_REC_VIOLATION_LOG 0x00e3
-#define mmIH_COOKIE_REC_VIOLATION_LOG_BASE_IDX 0
-#define mmIH_CREDIT_STATUS 0x00e4
-#define mmIH_CREDIT_STATUS_BASE_IDX 0
-#define mmIH_MMHUB_ERROR 0x00e5
-#define mmIH_MMHUB_ERROR_BASE_IDX 0
-#define mmIH_REGISTER_LAST_PART2 0x00ff
-#define mmIH_REGISTER_LAST_PART2_BASE_IDX 0
-#define mmSEM_CLK_CTRL 0x0100
-#define mmSEM_CLK_CTRL_BASE_IDX 0
-#define mmSEM_UTC_CREDIT 0x0101
-#define mmSEM_UTC_CREDIT_BASE_IDX 0
-#define mmSEM_UTC_CONFIG 0x0102
-#define mmSEM_UTC_CONFIG_BASE_IDX 0
-#define mmSEM_UTCL2_TRAN_EN_LUT 0x0103
-#define mmSEM_UTCL2_TRAN_EN_LUT_BASE_IDX 0
-#define mmSEM_MCIF_CONFIG 0x0104
-#define mmSEM_MCIF_CONFIG_BASE_IDX 0
-#define mmSEM_PERFMON_CNTL 0x0105
-#define mmSEM_PERFMON_CNTL_BASE_IDX 0
-#define mmSEM_PERFCOUNTER0_RESULT 0x0106
-#define mmSEM_PERFCOUNTER0_RESULT_BASE_IDX 0
-#define mmSEM_PERFCOUNTER1_RESULT 0x0107
-#define mmSEM_PERFCOUNTER1_RESULT_BASE_IDX 0
-#define mmSEM_STATUS 0x0108
-#define mmSEM_STATUS_BASE_IDX 0
-#define mmSEM_MAILBOX_CLIENTCONFIG 0x0109
-#define mmSEM_MAILBOX_CLIENTCONFIG_BASE_IDX 0
-#define mmSEM_MAILBOX 0x010a
-#define mmSEM_MAILBOX_BASE_IDX 0
-#define mmSEM_MAILBOX_CONTROL 0x010b
-#define mmSEM_MAILBOX_CONTROL_BASE_IDX 0
-#define mmSEM_CHICKEN_BITS 0x010c
-#define mmSEM_CHICKEN_BITS_BASE_IDX 0
-#define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA 0x010d
-#define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA_BASE_IDX 0
-#define mmSEM_GPU_IOV_VIOLATION_LOG 0x010e
-#define mmSEM_GPU_IOV_VIOLATION_LOG_BASE_IDX 0
-#define mmSEM_OUTSTANDING_THRESHOLD 0x010f
-#define mmSEM_OUTSTANDING_THRESHOLD_BASE_IDX 0
-#define mmSEM_REGISTER_LAST_PART2 0x017f
-#define mmSEM_REGISTER_LAST_PART2_BASE_IDX 0
-#define mmIH_ACTIVE_FCN_ID 0x0180
-#define mmIH_ACTIVE_FCN_ID_BASE_IDX 0
-#define mmIH_VIRT_RESET_REQ 0x0181
-#define mmIH_VIRT_RESET_REQ_BASE_IDX 0
-#define mmIH_CLIENT_CFG 0x0184
-#define mmIH_CLIENT_CFG_BASE_IDX 0
-#define mmIH_CLIENT_CFG_INDEX 0x0188
-#define mmIH_CLIENT_CFG_INDEX_BASE_IDX 0
-#define mmIH_CLIENT_CFG_DATA 0x0189
-#define mmIH_CLIENT_CFG_DATA_BASE_IDX 0
-#define mmIH_CID_REMAP_INDEX 0x018a
-#define mmIH_CID_REMAP_INDEX_BASE_IDX 0
-#define mmIH_CID_REMAP_DATA 0x018b
-#define mmIH_CID_REMAP_DATA_BASE_IDX 0
-#define mmIH_CHICKEN 0x018c
-#define mmIH_CHICKEN_BASE_IDX 0
-#define mmIH_MMHUB_CNTL 0x018d
-#define mmIH_MMHUB_CNTL_BASE_IDX 0
-#define mmIH_INT_DROP_CNTL 0x018e
-#define mmIH_INT_DROP_CNTL_BASE_IDX 0
-#define mmIH_INT_DROP_MATCH_VALUE0 0x018f
-#define mmIH_INT_DROP_MATCH_VALUE0_BASE_IDX 0
-#define mmIH_INT_DROP_MATCH_VALUE1 0x0190
-#define mmIH_INT_DROP_MATCH_VALUE1_BASE_IDX 0
-#define mmIH_INT_DROP_MATCH_MASK0 0x0191
-#define mmIH_INT_DROP_MATCH_MASK0_BASE_IDX 0
-#define mmIH_INT_DROP_MATCH_MASK1 0x0192
-#define mmIH_INT_DROP_MATCH_MASK1_BASE_IDX 0
-#define mmIH_REGISTER_LAST_PART1 0x019f
-#define mmIH_REGISTER_LAST_PART1_BASE_IDX 0
-#define mmSEM_ACTIVE_FCN_ID 0x01a0
-#define mmSEM_ACTIVE_FCN_ID_BASE_IDX 0
-#define mmSEM_VIRT_RESET_REQ 0x01a1
-#define mmSEM_VIRT_RESET_REQ_BASE_IDX 0
-#define mmSEM_RESP_SDMA0 0x01a4
-#define mmSEM_RESP_SDMA0_BASE_IDX 0
-#define mmSEM_RESP_SDMA1 0x01a5
-#define mmSEM_RESP_SDMA1_BASE_IDX 0
-#define mmSEM_RESP_UVD 0x01a6
-#define mmSEM_RESP_UVD_BASE_IDX 0
-#define mmSEM_RESP_VCE_0 0x01a7
-#define mmSEM_RESP_VCE_0_BASE_IDX 0
-#define mmSEM_RESP_ACP 0x01a8
-#define mmSEM_RESP_ACP_BASE_IDX 0
-#define mmSEM_RESP_ISP 0x01a9
-#define mmSEM_RESP_ISP_BASE_IDX 0
-#define mmSEM_RESP_VCE_1 0x01aa
-#define mmSEM_RESP_VCE_1_BASE_IDX 0
-#define mmSEM_RESP_VP8 0x01ab
-#define mmSEM_RESP_VP8_BASE_IDX 0
-#define mmSEM_RESP_GC 0x01ac
-#define mmSEM_RESP_GC_BASE_IDX 0
-#define mmSEM_CID_REMAP_INDEX 0x01b0
-#define mmSEM_CID_REMAP_INDEX_BASE_IDX 0
-#define mmSEM_CID_REMAP_DATA 0x01b1
-#define mmSEM_CID_REMAP_DATA_BASE_IDX 0
-#define mmSEM_ATOMIC_OP_LUT 0x01b2
-#define mmSEM_ATOMIC_OP_LUT_BASE_IDX 0
-#define mmSEM_EDC_CONFIG 0x01b3
-#define mmSEM_EDC_CONFIG_BASE_IDX 0
-#define mmSEM_CHICKEN_BITS2 0x01b4
-#define mmSEM_CHICKEN_BITS2_BASE_IDX 0
-#define mmSEM_MMHUB_CNTL 0x01b5
-#define mmSEM_MMHUB_CNTL_BASE_IDX 0
-#define mmSEM_REGISTER_LAST_PART1 0x01bf
-#define mmSEM_REGISTER_LAST_PART1_BASE_IDX 0
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_1_sh_mask.h
deleted file mode 100644
index 19c4a4014..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_1_sh_mask.h
+++ /dev/null
@@ -1,1249 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _osssys_4_0_1_SH_MASK_HEADER
-#define _osssys_4_0_1_SH_MASK_HEADER
-
-
-// addressBlock: osssys_osssysdec
-//IH_VMID_0_LUT
-#define IH_VMID_0_LUT__PASID__SHIFT 0x0
-#define IH_VMID_0_LUT__PASID_MASK 0x0000FFFFL
-//IH_VMID_1_LUT
-#define IH_VMID_1_LUT__PASID__SHIFT 0x0
-#define IH_VMID_1_LUT__PASID_MASK 0x0000FFFFL
-//IH_VMID_2_LUT
-#define IH_VMID_2_LUT__PASID__SHIFT 0x0
-#define IH_VMID_2_LUT__PASID_MASK 0x0000FFFFL
-//IH_VMID_3_LUT
-#define IH_VMID_3_LUT__PASID__SHIFT 0x0
-#define IH_VMID_3_LUT__PASID_MASK 0x0000FFFFL
-//IH_VMID_4_LUT
-#define IH_VMID_4_LUT__PASID__SHIFT 0x0
-#define IH_VMID_4_LUT__PASID_MASK 0x0000FFFFL
-//IH_VMID_5_LUT
-#define IH_VMID_5_LUT__PASID__SHIFT 0x0
-#define IH_VMID_5_LUT__PASID_MASK 0x0000FFFFL
-//IH_VMID_6_LUT
-#define IH_VMID_6_LUT__PASID__SHIFT 0x0
-#define IH_VMID_6_LUT__PASID_MASK 0x0000FFFFL
-//IH_VMID_7_LUT
-#define IH_VMID_7_LUT__PASID__SHIFT 0x0
-#define IH_VMID_7_LUT__PASID_MASK 0x0000FFFFL
-//IH_VMID_8_LUT
-#define IH_VMID_8_LUT__PASID__SHIFT 0x0
-#define IH_VMID_8_LUT__PASID_MASK 0x0000FFFFL
-//IH_VMID_9_LUT
-#define IH_VMID_9_LUT__PASID__SHIFT 0x0
-#define IH_VMID_9_LUT__PASID_MASK 0x0000FFFFL
-//IH_VMID_10_LUT
-#define IH_VMID_10_LUT__PASID__SHIFT 0x0
-#define IH_VMID_10_LUT__PASID_MASK 0x0000FFFFL
-//IH_VMID_11_LUT
-#define IH_VMID_11_LUT__PASID__SHIFT 0x0
-#define IH_VMID_11_LUT__PASID_MASK 0x0000FFFFL
-//IH_VMID_12_LUT
-#define IH_VMID_12_LUT__PASID__SHIFT 0x0
-#define IH_VMID_12_LUT__PASID_MASK 0x0000FFFFL
-//IH_VMID_13_LUT
-#define IH_VMID_13_LUT__PASID__SHIFT 0x0
-#define IH_VMID_13_LUT__PASID_MASK 0x0000FFFFL
-//IH_VMID_14_LUT
-#define IH_VMID_14_LUT__PASID__SHIFT 0x0
-#define IH_VMID_14_LUT__PASID_MASK 0x0000FFFFL
-//IH_VMID_15_LUT
-#define IH_VMID_15_LUT__PASID__SHIFT 0x0
-#define IH_VMID_15_LUT__PASID_MASK 0x0000FFFFL
-//IH_VMID_0_LUT_MM
-#define IH_VMID_0_LUT_MM__PASID__SHIFT 0x0
-#define IH_VMID_0_LUT_MM__PASID_MASK 0x0000FFFFL
-//IH_VMID_1_LUT_MM
-#define IH_VMID_1_LUT_MM__PASID__SHIFT 0x0
-#define IH_VMID_1_LUT_MM__PASID_MASK 0x0000FFFFL
-//IH_VMID_2_LUT_MM
-#define IH_VMID_2_LUT_MM__PASID__SHIFT 0x0
-#define IH_VMID_2_LUT_MM__PASID_MASK 0x0000FFFFL
-//IH_VMID_3_LUT_MM
-#define IH_VMID_3_LUT_MM__PASID__SHIFT 0x0
-#define IH_VMID_3_LUT_MM__PASID_MASK 0x0000FFFFL
-//IH_VMID_4_LUT_MM
-#define IH_VMID_4_LUT_MM__PASID__SHIFT 0x0
-#define IH_VMID_4_LUT_MM__PASID_MASK 0x0000FFFFL
-//IH_VMID_5_LUT_MM
-#define IH_VMID_5_LUT_MM__PASID__SHIFT 0x0
-#define IH_VMID_5_LUT_MM__PASID_MASK 0x0000FFFFL
-//IH_VMID_6_LUT_MM
-#define IH_VMID_6_LUT_MM__PASID__SHIFT 0x0
-#define IH_VMID_6_LUT_MM__PASID_MASK 0x0000FFFFL
-//IH_VMID_7_LUT_MM
-#define IH_VMID_7_LUT_MM__PASID__SHIFT 0x0
-#define IH_VMID_7_LUT_MM__PASID_MASK 0x0000FFFFL
-//IH_VMID_8_LUT_MM
-#define IH_VMID_8_LUT_MM__PASID__SHIFT 0x0
-#define IH_VMID_8_LUT_MM__PASID_MASK 0x0000FFFFL
-//IH_VMID_9_LUT_MM
-#define IH_VMID_9_LUT_MM__PASID__SHIFT 0x0
-#define IH_VMID_9_LUT_MM__PASID_MASK 0x0000FFFFL
-//IH_VMID_10_LUT_MM
-#define IH_VMID_10_LUT_MM__PASID__SHIFT 0x0
-#define IH_VMID_10_LUT_MM__PASID_MASK 0x0000FFFFL
-//IH_VMID_11_LUT_MM
-#define IH_VMID_11_LUT_MM__PASID__SHIFT 0x0
-#define IH_VMID_11_LUT_MM__PASID_MASK 0x0000FFFFL
-//IH_VMID_12_LUT_MM
-#define IH_VMID_12_LUT_MM__PASID__SHIFT 0x0
-#define IH_VMID_12_LUT_MM__PASID_MASK 0x0000FFFFL
-//IH_VMID_13_LUT_MM
-#define IH_VMID_13_LUT_MM__PASID__SHIFT 0x0
-#define IH_VMID_13_LUT_MM__PASID_MASK 0x0000FFFFL
-//IH_VMID_14_LUT_MM
-#define IH_VMID_14_LUT_MM__PASID__SHIFT 0x0
-#define IH_VMID_14_LUT_MM__PASID_MASK 0x0000FFFFL
-//IH_VMID_15_LUT_MM
-#define IH_VMID_15_LUT_MM__PASID__SHIFT 0x0
-#define IH_VMID_15_LUT_MM__PASID_MASK 0x0000FFFFL
-//IH_COOKIE_0
-#define IH_COOKIE_0__CLIENT_ID__SHIFT 0x0
-#define IH_COOKIE_0__SOURCE_ID__SHIFT 0x8
-#define IH_COOKIE_0__RING_ID__SHIFT 0x10
-#define IH_COOKIE_0__VM_ID__SHIFT 0x18
-#define IH_COOKIE_0__RESERVED__SHIFT 0x1c
-#define IH_COOKIE_0__VMID_TYPE__SHIFT 0x1f
-#define IH_COOKIE_0__CLIENT_ID_MASK 0x000000FFL
-#define IH_COOKIE_0__SOURCE_ID_MASK 0x0000FF00L
-#define IH_COOKIE_0__RING_ID_MASK 0x00FF0000L
-#define IH_COOKIE_0__VM_ID_MASK 0x0F000000L
-#define IH_COOKIE_0__RESERVED_MASK 0x70000000L
-#define IH_COOKIE_0__VMID_TYPE_MASK 0x80000000L
-//IH_COOKIE_1
-#define IH_COOKIE_1__TIMESTAMP_31_0__SHIFT 0x0
-#define IH_COOKIE_1__TIMESTAMP_31_0_MASK 0xFFFFFFFFL
-//IH_COOKIE_2
-#define IH_COOKIE_2__TIMESTAMP_47_32__SHIFT 0x0
-#define IH_COOKIE_2__RESERVED__SHIFT 0x10
-#define IH_COOKIE_2__TIMESTAMP_SRC__SHIFT 0x1f
-#define IH_COOKIE_2__TIMESTAMP_47_32_MASK 0x0000FFFFL
-#define IH_COOKIE_2__RESERVED_MASK 0x7FFF0000L
-#define IH_COOKIE_2__TIMESTAMP_SRC_MASK 0x80000000L
-//IH_COOKIE_3
-#define IH_COOKIE_3__PAS_ID__SHIFT 0x0
-#define IH_COOKIE_3__RESERVED__SHIFT 0x10
-#define IH_COOKIE_3__PASID_SRC__SHIFT 0x1f
-#define IH_COOKIE_3__PAS_ID_MASK 0x0000FFFFL
-#define IH_COOKIE_3__RESERVED_MASK 0x7FFF0000L
-#define IH_COOKIE_3__PASID_SRC_MASK 0x80000000L
-//IH_COOKIE_4
-#define IH_COOKIE_4__CONTEXT_ID_31_0__SHIFT 0x0
-#define IH_COOKIE_4__CONTEXT_ID_31_0_MASK 0xFFFFFFFFL
-//IH_COOKIE_5
-#define IH_COOKIE_5__CONTEXT_ID_63_32__SHIFT 0x0
-#define IH_COOKIE_5__CONTEXT_ID_63_32_MASK 0xFFFFFFFFL
-//IH_COOKIE_6
-#define IH_COOKIE_6__CONTEXT_ID_95_64__SHIFT 0x0
-#define IH_COOKIE_6__CONTEXT_ID_95_64_MASK 0xFFFFFFFFL
-//IH_COOKIE_7
-#define IH_COOKIE_7__CONTEXT_ID_128_96__SHIFT 0x0
-#define IH_COOKIE_7__CONTEXT_ID_128_96_MASK 0xFFFFFFFFL
-//IH_REGISTER_LAST_PART0
-#define IH_REGISTER_LAST_PART0__RESERVED__SHIFT 0x0
-#define IH_REGISTER_LAST_PART0__RESERVED_MASK 0xFFFFFFFFL
-//SEM_REQ_INPUT_0
-#define SEM_REQ_INPUT_0__DATA__SHIFT 0x0
-#define SEM_REQ_INPUT_0__DATA_MASK 0xFFFFFFFFL
-//SEM_REQ_INPUT_1
-#define SEM_REQ_INPUT_1__DATA__SHIFT 0x0
-#define SEM_REQ_INPUT_1__DATA_MASK 0xFFFFFFFFL
-//SEM_REQ_INPUT_2
-#define SEM_REQ_INPUT_2__DATA__SHIFT 0x0
-#define SEM_REQ_INPUT_2__DATA_MASK 0xFFFFFFFFL
-//SEM_REQ_INPUT_3
-#define SEM_REQ_INPUT_3__DATA__SHIFT 0x0
-#define SEM_REQ_INPUT_3__DATA_MASK 0xFFFFFFFFL
-//SEM_REGISTER_LAST_PART0
-#define SEM_REGISTER_LAST_PART0__RESERVED__SHIFT 0x0
-#define SEM_REGISTER_LAST_PART0__RESERVED_MASK 0xFFFFFFFFL
-//IH_RB_CNTL
-#define IH_RB_CNTL__RB_ENABLE__SHIFT 0x0
-#define IH_RB_CNTL__RB_SIZE__SHIFT 0x1
-#define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x7
-#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
-#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT 0x9
-#define IH_RB_CNTL__FULL_DRAIN_CLEAR__SHIFT 0xa
-#define IH_RB_CNTL__PAGE_RB_CLEAR__SHIFT 0xb
-#define IH_RB_CNTL__RB_USED_INT_THRESHOLD__SHIFT 0xc
-#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT 0x10
-#define IH_RB_CNTL__ENABLE_INTR__SHIFT 0x11
-#define IH_RB_CNTL__MC_SWAP__SHIFT 0x12
-#define IH_RB_CNTL__MC_SNOOP__SHIFT 0x14
-#define IH_RB_CNTL__RPTR_REARM__SHIFT 0x15
-#define IH_RB_CNTL__MC_RO__SHIFT 0x16
-#define IH_RB_CNTL__MC_VMID__SHIFT 0x18
-#define IH_RB_CNTL__MC_SPACE__SHIFT 0x1c
-#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
-#define IH_RB_CNTL__RB_ENABLE_MASK 0x00000001L
-#define IH_RB_CNTL__RB_SIZE_MASK 0x0000003EL
-#define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x00000080L
-#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L
-#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L
-#define IH_RB_CNTL__FULL_DRAIN_CLEAR_MASK 0x00000400L
-#define IH_RB_CNTL__PAGE_RB_CLEAR_MASK 0x00000800L
-#define IH_RB_CNTL__RB_USED_INT_THRESHOLD_MASK 0x0000F000L
-#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L
-#define IH_RB_CNTL__ENABLE_INTR_MASK 0x00020000L
-#define IH_RB_CNTL__MC_SWAP_MASK 0x000C0000L
-#define IH_RB_CNTL__MC_SNOOP_MASK 0x00100000L
-#define IH_RB_CNTL__RPTR_REARM_MASK 0x00200000L
-#define IH_RB_CNTL__MC_RO_MASK 0x00400000L
-#define IH_RB_CNTL__MC_VMID_MASK 0x0F000000L
-#define IH_RB_CNTL__MC_SPACE_MASK 0x70000000L
-#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L
-//IH_RB_BASE
-#define IH_RB_BASE__ADDR__SHIFT 0x0
-#define IH_RB_BASE__ADDR_MASK 0xFFFFFFFFL
-//IH_RB_BASE_HI
-#define IH_RB_BASE_HI__ADDR__SHIFT 0x0
-#define IH_RB_BASE_HI__ADDR_MASK 0x000000FFL
-//IH_RB_RPTR
-#define IH_RB_RPTR__OFFSET__SHIFT 0x2
-#define IH_RB_RPTR__OFFSET_MASK 0x0003FFFCL
-//IH_RB_WPTR
-#define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x0
-#define IH_RB_WPTR__OFFSET__SHIFT 0x2
-#define IH_RB_WPTR__RB_LEFT_NONE__SHIFT 0x12
-#define IH_RB_WPTR__RB_MAY_OVERFLOW__SHIFT 0x13
-#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x00000001L
-#define IH_RB_WPTR__OFFSET_MASK 0x0003FFFCL
-#define IH_RB_WPTR__RB_LEFT_NONE_MASK 0x00040000L
-#define IH_RB_WPTR__RB_MAY_OVERFLOW_MASK 0x00080000L
-//IH_RB_WPTR_ADDR_HI
-#define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0
-#define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0x0000FFFFL
-//IH_RB_WPTR_ADDR_LO
-#define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
-#define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//IH_DOORBELL_RPTR
-#define IH_DOORBELL_RPTR__OFFSET__SHIFT 0x0
-#define IH_DOORBELL_RPTR__ENABLE__SHIFT 0x1c
-#define IH_DOORBELL_RPTR__OFFSET_MASK 0x03FFFFFFL
-#define IH_DOORBELL_RPTR__ENABLE_MASK 0x10000000L
-//IH_RB_CNTL_RING1
-#define IH_RB_CNTL_RING1__RB_ENABLE__SHIFT 0x0
-#define IH_RB_CNTL_RING1__RB_SIZE__SHIFT 0x1
-#define IH_RB_CNTL_RING1__RB_GPU_TS_ENABLE__SHIFT 0x7
-#define IH_RB_CNTL_RING1__RB_FULL_DRAIN_ENABLE__SHIFT 0x9
-#define IH_RB_CNTL_RING1__FULL_DRAIN_CLEAR__SHIFT 0xa
-#define IH_RB_CNTL_RING1__PAGE_RB_CLEAR__SHIFT 0xb
-#define IH_RB_CNTL_RING1__RB_USED_INT_THRESHOLD__SHIFT 0xc
-#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_ENABLE__SHIFT 0x10
-#define IH_RB_CNTL_RING1__MC_SWAP__SHIFT 0x12
-#define IH_RB_CNTL_RING1__MC_SNOOP__SHIFT 0x14
-#define IH_RB_CNTL_RING1__MC_RO__SHIFT 0x16
-#define IH_RB_CNTL_RING1__MC_VMID__SHIFT 0x18
-#define IH_RB_CNTL_RING1__MC_SPACE__SHIFT 0x1c
-#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
-#define IH_RB_CNTL_RING1__RB_ENABLE_MASK 0x00000001L
-#define IH_RB_CNTL_RING1__RB_SIZE_MASK 0x0000003EL
-#define IH_RB_CNTL_RING1__RB_GPU_TS_ENABLE_MASK 0x00000080L
-#define IH_RB_CNTL_RING1__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L
-#define IH_RB_CNTL_RING1__FULL_DRAIN_CLEAR_MASK 0x00000400L
-#define IH_RB_CNTL_RING1__PAGE_RB_CLEAR_MASK 0x00000800L
-#define IH_RB_CNTL_RING1__RB_USED_INT_THRESHOLD_MASK 0x0000F000L
-#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L
-#define IH_RB_CNTL_RING1__MC_SWAP_MASK 0x000C0000L
-#define IH_RB_CNTL_RING1__MC_SNOOP_MASK 0x00100000L
-#define IH_RB_CNTL_RING1__MC_RO_MASK 0x00400000L
-#define IH_RB_CNTL_RING1__MC_VMID_MASK 0x0F000000L
-#define IH_RB_CNTL_RING1__MC_SPACE_MASK 0x70000000L
-#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L
-//IH_RB_BASE_RING1
-#define IH_RB_BASE_RING1__ADDR__SHIFT 0x0
-#define IH_RB_BASE_RING1__ADDR_MASK 0xFFFFFFFFL
-//IH_RB_BASE_HI_RING1
-#define IH_RB_BASE_HI_RING1__ADDR__SHIFT 0x0
-#define IH_RB_BASE_HI_RING1__ADDR_MASK 0x000000FFL
-//IH_RB_RPTR_RING1
-#define IH_RB_RPTR_RING1__OFFSET__SHIFT 0x2
-#define IH_RB_RPTR_RING1__OFFSET_MASK 0x0003FFFCL
-//IH_RB_WPTR_RING1
-#define IH_RB_WPTR_RING1__RB_OVERFLOW__SHIFT 0x0
-#define IH_RB_WPTR_RING1__OFFSET__SHIFT 0x2
-#define IH_RB_WPTR_RING1__RB_LEFT_NONE__SHIFT 0x12
-#define IH_RB_WPTR_RING1__RB_MAY_OVERFLOW__SHIFT 0x13
-#define IH_RB_WPTR_RING1__RB_OVERFLOW_MASK 0x00000001L
-#define IH_RB_WPTR_RING1__OFFSET_MASK 0x0003FFFCL
-#define IH_RB_WPTR_RING1__RB_LEFT_NONE_MASK 0x00040000L
-#define IH_RB_WPTR_RING1__RB_MAY_OVERFLOW_MASK 0x00080000L
-//IH_DOORBELL_RPTR_RING1
-#define IH_DOORBELL_RPTR_RING1__OFFSET__SHIFT 0x0
-#define IH_DOORBELL_RPTR_RING1__ENABLE__SHIFT 0x1c
-#define IH_DOORBELL_RPTR_RING1__OFFSET_MASK 0x03FFFFFFL
-#define IH_DOORBELL_RPTR_RING1__ENABLE_MASK 0x10000000L
-//IH_RB_CNTL_RING2
-#define IH_RB_CNTL_RING2__RB_ENABLE__SHIFT 0x0
-#define IH_RB_CNTL_RING2__RB_SIZE__SHIFT 0x1
-#define IH_RB_CNTL_RING2__RB_GPU_TS_ENABLE__SHIFT 0x7
-#define IH_RB_CNTL_RING2__RB_FULL_DRAIN_ENABLE__SHIFT 0x9
-#define IH_RB_CNTL_RING2__FULL_DRAIN_CLEAR__SHIFT 0xa
-#define IH_RB_CNTL_RING2__PAGE_RB_CLEAR__SHIFT 0xb
-#define IH_RB_CNTL_RING2__RB_USED_INT_THRESHOLD__SHIFT 0xc
-#define IH_RB_CNTL_RING2__WPTR_OVERFLOW_ENABLE__SHIFT 0x10
-#define IH_RB_CNTL_RING2__MC_SWAP__SHIFT 0x12
-#define IH_RB_CNTL_RING2__MC_SNOOP__SHIFT 0x14
-#define IH_RB_CNTL_RING2__MC_RO__SHIFT 0x16
-#define IH_RB_CNTL_RING2__MC_VMID__SHIFT 0x18
-#define IH_RB_CNTL_RING2__MC_SPACE__SHIFT 0x1c
-#define IH_RB_CNTL_RING2__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
-#define IH_RB_CNTL_RING2__RB_ENABLE_MASK 0x00000001L
-#define IH_RB_CNTL_RING2__RB_SIZE_MASK 0x0000003EL
-#define IH_RB_CNTL_RING2__RB_GPU_TS_ENABLE_MASK 0x00000080L
-#define IH_RB_CNTL_RING2__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L
-#define IH_RB_CNTL_RING2__FULL_DRAIN_CLEAR_MASK 0x00000400L
-#define IH_RB_CNTL_RING2__PAGE_RB_CLEAR_MASK 0x00000800L
-#define IH_RB_CNTL_RING2__RB_USED_INT_THRESHOLD_MASK 0x0000F000L
-#define IH_RB_CNTL_RING2__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L
-#define IH_RB_CNTL_RING2__MC_SWAP_MASK 0x000C0000L
-#define IH_RB_CNTL_RING2__MC_SNOOP_MASK 0x00100000L
-#define IH_RB_CNTL_RING2__MC_RO_MASK 0x00400000L
-#define IH_RB_CNTL_RING2__MC_VMID_MASK 0x0F000000L
-#define IH_RB_CNTL_RING2__MC_SPACE_MASK 0x70000000L
-#define IH_RB_CNTL_RING2__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L
-//IH_RB_BASE_RING2
-#define IH_RB_BASE_RING2__ADDR__SHIFT 0x0
-#define IH_RB_BASE_RING2__ADDR_MASK 0xFFFFFFFFL
-//IH_RB_BASE_HI_RING2
-#define IH_RB_BASE_HI_RING2__ADDR__SHIFT 0x0
-#define IH_RB_BASE_HI_RING2__ADDR_MASK 0x000000FFL
-//IH_RB_RPTR_RING2
-#define IH_RB_RPTR_RING2__OFFSET__SHIFT 0x2
-#define IH_RB_RPTR_RING2__OFFSET_MASK 0x0003FFFCL
-//IH_RB_WPTR_RING2
-#define IH_RB_WPTR_RING2__RB_OVERFLOW__SHIFT 0x0
-#define IH_RB_WPTR_RING2__OFFSET__SHIFT 0x2
-#define IH_RB_WPTR_RING2__RB_LEFT_NONE__SHIFT 0x12
-#define IH_RB_WPTR_RING2__RB_MAY_OVERFLOW__SHIFT 0x13
-#define IH_RB_WPTR_RING2__RB_OVERFLOW_MASK 0x00000001L
-#define IH_RB_WPTR_RING2__OFFSET_MASK 0x0003FFFCL
-#define IH_RB_WPTR_RING2__RB_LEFT_NONE_MASK 0x00040000L
-#define IH_RB_WPTR_RING2__RB_MAY_OVERFLOW_MASK 0x00080000L
-//IH_DOORBELL_RPTR_RING2
-#define IH_DOORBELL_RPTR_RING2__OFFSET__SHIFT 0x0
-#define IH_DOORBELL_RPTR_RING2__ENABLE__SHIFT 0x1c
-#define IH_DOORBELL_RPTR_RING2__OFFSET_MASK 0x03FFFFFFL
-#define IH_DOORBELL_RPTR_RING2__ENABLE_MASK 0x10000000L
-//IH_VERSION
-#define IH_VERSION__MINVER__SHIFT 0x0
-#define IH_VERSION__MAJVER__SHIFT 0x8
-#define IH_VERSION__REV__SHIFT 0x10
-#define IH_VERSION__MINVER_MASK 0x0000007FL
-#define IH_VERSION__MAJVER_MASK 0x00007F00L
-#define IH_VERSION__REV_MASK 0x003F0000L
-//IH_CNTL
-#define IH_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x0
-#define IH_CNTL__IH_IDLE_HYSTERESIS_CNTL__SHIFT 0x6
-#define IH_CNTL__IH_FIFO_HIGHWATER__SHIFT 0x8
-#define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x14
-#define IH_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x0000001FL
-#define IH_CNTL__IH_IDLE_HYSTERESIS_CNTL_MASK 0x000000C0L
-#define IH_CNTL__IH_FIFO_HIGHWATER_MASK 0x00007F00L
-#define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x01F00000L
-//IH_CNTL2
-#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT__SHIFT 0x0
-#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_ENABLE__SHIFT 0x8
-#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT_MASK 0x0000001FL
-#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_ENABLE_MASK 0x00000100L
-//IH_STATUS
-#define IH_STATUS__IDLE__SHIFT 0x0
-#define IH_STATUS__INPUT_IDLE__SHIFT 0x1
-#define IH_STATUS__BUFFER_IDLE__SHIFT 0x2
-#define IH_STATUS__RB_FULL__SHIFT 0x3
-#define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x4
-#define IH_STATUS__RB_OVERFLOW__SHIFT 0x5
-#define IH_STATUS__MC_WR_IDLE__SHIFT 0x6
-#define IH_STATUS__MC_WR_STALL__SHIFT 0x7
-#define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x8
-#define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x9
-#define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa
-#define IH_STATUS__SWITCH_READY__SHIFT 0xb
-#define IH_STATUS__RB1_FULL__SHIFT 0xc
-#define IH_STATUS__RB1_FULL_DRAIN__SHIFT 0xd
-#define IH_STATUS__RB1_OVERFLOW__SHIFT 0xe
-#define IH_STATUS__RB2_FULL__SHIFT 0xf
-#define IH_STATUS__RB2_FULL_DRAIN__SHIFT 0x10
-#define IH_STATUS__RB2_OVERFLOW__SHIFT 0x11
-#define IH_STATUS__SELF_INT_GEN_IDLE__SHIFT 0x12
-#define IH_STATUS__IDLE_MASK 0x00000001L
-#define IH_STATUS__INPUT_IDLE_MASK 0x00000002L
-#define IH_STATUS__BUFFER_IDLE_MASK 0x00000004L
-#define IH_STATUS__RB_FULL_MASK 0x00000008L
-#define IH_STATUS__RB_FULL_DRAIN_MASK 0x00000010L
-#define IH_STATUS__RB_OVERFLOW_MASK 0x00000020L
-#define IH_STATUS__MC_WR_IDLE_MASK 0x00000040L
-#define IH_STATUS__MC_WR_STALL_MASK 0x00000080L
-#define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x00000100L
-#define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x00000200L
-#define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x00000400L
-#define IH_STATUS__SWITCH_READY_MASK 0x00000800L
-#define IH_STATUS__RB1_FULL_MASK 0x00001000L
-#define IH_STATUS__RB1_FULL_DRAIN_MASK 0x00002000L
-#define IH_STATUS__RB1_OVERFLOW_MASK 0x00004000L
-#define IH_STATUS__RB2_FULL_MASK 0x00008000L
-#define IH_STATUS__RB2_FULL_DRAIN_MASK 0x00010000L
-#define IH_STATUS__RB2_OVERFLOW_MASK 0x00020000L
-#define IH_STATUS__SELF_INT_GEN_IDLE_MASK 0x00040000L
-//IH_PERFMON_CNTL
-#define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x0
-#define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1
-#define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
-#define IH_PERFMON_CNTL__ENABLE1__SHIFT 0x10
-#define IH_PERFMON_CNTL__CLEAR1__SHIFT 0x11
-#define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0x12
-#define IH_PERFMON_CNTL__ENABLE0_MASK 0x00000001L
-#define IH_PERFMON_CNTL__CLEAR0_MASK 0x00000002L
-#define IH_PERFMON_CNTL__PERF_SEL0_MASK 0x000007FCL
-#define IH_PERFMON_CNTL__ENABLE1_MASK 0x00010000L
-#define IH_PERFMON_CNTL__CLEAR1_MASK 0x00020000L
-#define IH_PERFMON_CNTL__PERF_SEL1_MASK 0x07FC0000L
-//IH_PERFCOUNTER0_RESULT
-#define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
-#define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
-//IH_PERFCOUNTER1_RESULT
-#define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
-#define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
-//IH_DSM_MATCH_VALUE_BIT_31_0
-#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE__SHIFT 0x0
-#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE_MASK 0xFFFFFFFFL
-//IH_DSM_MATCH_VALUE_BIT_63_32
-#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE__SHIFT 0x0
-#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE_MASK 0xFFFFFFFFL
-//IH_DSM_MATCH_VALUE_BIT_95_64
-#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE__SHIFT 0x0
-#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE_MASK 0xFFFFFFFFL
-//IH_DSM_MATCH_FIELD_CONTROL
-#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN__SHIFT 0x0
-#define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN__SHIFT 0x1
-#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT 0x2
-#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT 0x3
-#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN__SHIFT 0x4
-#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN__SHIFT 0x5
-#define IH_DSM_MATCH_FIELD_CONTROL__CLIENT_ID_EN__SHIFT 0x6
-#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN_MASK 0x00000001L
-#define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN_MASK 0x00000002L
-#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN_MASK 0x00000004L
-#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN_MASK 0x00000008L
-#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN_MASK 0x00000010L
-#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN_MASK 0x00000020L
-#define IH_DSM_MATCH_FIELD_CONTROL__CLIENT_ID_EN_MASK 0x00000040L
-//IH_DSM_MATCH_DATA_CONTROL
-#define IH_DSM_MATCH_DATA_CONTROL__VALUE__SHIFT 0x0
-#define IH_DSM_MATCH_DATA_CONTROL__VALUE_MASK 0x0FFFFFFFL
-//IH_DSM_MATCH_FCN_ID
-#define IH_DSM_MATCH_FCN_ID__PF_VF__SHIFT 0x0
-#define IH_DSM_MATCH_FCN_ID__VF_ID__SHIFT 0x1
-#define IH_DSM_MATCH_FCN_ID__PF_VF_MASK 0x00000001L
-#define IH_DSM_MATCH_FCN_ID__VF_ID_MASK 0x0000001EL
-//IH_LIMIT_INT_RATE_CNTL
-#define IH_LIMIT_INT_RATE_CNTL__LIMIT_ENABLE__SHIFT 0x0
-#define IH_LIMIT_INT_RATE_CNTL__PERF_INTERVAL__SHIFT 0x1
-#define IH_LIMIT_INT_RATE_CNTL__PERF_THRESHOLD__SHIFT 0x5
-#define IH_LIMIT_INT_RATE_CNTL__RETURN_DELAY__SHIFT 0x11
-#define IH_LIMIT_INT_RATE_CNTL__PERF_RESULT__SHIFT 0x15
-#define IH_LIMIT_INT_RATE_CNTL__LIMIT_ENABLE_MASK 0x00000001L
-#define IH_LIMIT_INT_RATE_CNTL__PERF_INTERVAL_MASK 0x0000001EL
-#define IH_LIMIT_INT_RATE_CNTL__PERF_THRESHOLD_MASK 0x0000FFE0L
-#define IH_LIMIT_INT_RATE_CNTL__RETURN_DELAY_MASK 0x001E0000L
-#define IH_LIMIT_INT_RATE_CNTL__PERF_RESULT_MASK 0xFFE00000L
-//IH_VF_RB_STATUS
-#define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0
-#define IH_VF_RB_STATUS__RB_OVERFLOW_VF__SHIFT 0x10
-#define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF_MASK 0x0000FFFFL
-#define IH_VF_RB_STATUS__RB_OVERFLOW_VF_MASK 0xFFFF0000L
-//IH_VF_RB_STATUS2
-#define IH_VF_RB_STATUS2__RB_FULL_VF__SHIFT 0x0
-#define IH_VF_RB_STATUS2__BIF_INTERRUPT_LINE_VF__SHIFT 0x10
-#define IH_VF_RB_STATUS2__RB_FULL_VF_MASK 0x0000FFFFL
-#define IH_VF_RB_STATUS2__BIF_INTERRUPT_LINE_VF_MASK 0xFFFF0000L
-//IH_VF_RB1_STATUS
-#define IH_VF_RB1_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0
-#define IH_VF_RB1_STATUS__RB_OVERFLOW_VF__SHIFT 0x10
-#define IH_VF_RB1_STATUS__RB_FULL_DRAIN_VF_MASK 0x0000FFFFL
-#define IH_VF_RB1_STATUS__RB_OVERFLOW_VF_MASK 0xFFFF0000L
-//IH_VF_RB1_STATUS2
-#define IH_VF_RB1_STATUS2__RB_FULL_VF__SHIFT 0x0
-#define IH_VF_RB1_STATUS2__RB_FULL_VF_MASK 0x0000FFFFL
-//IH_VF_RB2_STATUS
-#define IH_VF_RB2_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0
-#define IH_VF_RB2_STATUS__RB_OVERFLOW_VF__SHIFT 0x10
-#define IH_VF_RB2_STATUS__RB_FULL_DRAIN_VF_MASK 0x0000FFFFL
-#define IH_VF_RB2_STATUS__RB_OVERFLOW_VF_MASK 0xFFFF0000L
-//IH_VF_RB2_STATUS2
-#define IH_VF_RB2_STATUS2__RB_FULL_VF__SHIFT 0x0
-#define IH_VF_RB2_STATUS2__RB_FULL_VF_MASK 0x0000FFFFL
-//IH_INT_FLOOD_CNTL
-#define IH_INT_FLOOD_CNTL__HIGHWATER__SHIFT 0x0
-#define IH_INT_FLOOD_CNTL__FLOOD_CNTL_ENABLE__SHIFT 0x3
-#define IH_INT_FLOOD_CNTL__CLEAR_INT_FLOOD_STATUS__SHIFT 0x4
-#define IH_INT_FLOOD_CNTL__HIGHWATER_MASK 0x00000007L
-#define IH_INT_FLOOD_CNTL__FLOOD_CNTL_ENABLE_MASK 0x00000008L
-#define IH_INT_FLOOD_CNTL__CLEAR_INT_FLOOD_STATUS_MASK 0x00000010L
-//IH_RB0_INT_FLOOD_STATUS
-#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x0
-#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x1f
-#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x0000FFFFL
-#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L
-//IH_RB1_INT_FLOOD_STATUS
-#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x0
-#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x1f
-#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x0000FFFFL
-#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L
-//IH_RB2_INT_FLOOD_STATUS
-#define IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x0
-#define IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x1f
-#define IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x0000FFFFL
-#define IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L
-//IH_INT_FLOOD_STATUS
-#define IH_INT_FLOOD_STATUS__INT_DROP_CNT__SHIFT 0x0
-#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_CLIENT_ID__SHIFT 0x8
-#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_SOURCE_ID__SHIFT 0x10
-#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_ID__SHIFT 0x18
-#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF__SHIFT 0x1c
-#define IH_INT_FLOOD_STATUS__INT_DROPPED__SHIFT 0x1e
-#define IH_INT_FLOOD_STATUS__INT_DROP_CNT_MASK 0x000000FFL
-#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_CLIENT_ID_MASK 0x0000FF00L
-#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_SOURCE_ID_MASK 0x00FF0000L
-#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_ID_MASK 0x0F000000L
-#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_MASK 0x10000000L
-#define IH_INT_FLOOD_STATUS__INT_DROPPED_MASK 0x40000000L
-//IH_STORM_CLIENT_LIST_CNTL
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT1_IS_STORM_CLIENT__SHIFT 0x1
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT2_IS_STORM_CLIENT__SHIFT 0x2
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT3_IS_STORM_CLIENT__SHIFT 0x3
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT4_IS_STORM_CLIENT__SHIFT 0x4
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT5_IS_STORM_CLIENT__SHIFT 0x5
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT6_IS_STORM_CLIENT__SHIFT 0x6
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT7_IS_STORM_CLIENT__SHIFT 0x7
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT8_IS_STORM_CLIENT__SHIFT 0x8
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT9_IS_STORM_CLIENT__SHIFT 0x9
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT10_IS_STORM_CLIENT__SHIFT 0xa
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT11_IS_STORM_CLIENT__SHIFT 0xb
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT12_IS_STORM_CLIENT__SHIFT 0xc
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT13_IS_STORM_CLIENT__SHIFT 0xd
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT14_IS_STORM_CLIENT__SHIFT 0xe
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT15_IS_STORM_CLIENT__SHIFT 0xf
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT16_IS_STORM_CLIENT__SHIFT 0x10
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT17_IS_STORM_CLIENT__SHIFT 0x11
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT18_IS_STORM_CLIENT__SHIFT 0x12
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT19_IS_STORM_CLIENT__SHIFT 0x13
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT20_IS_STORM_CLIENT__SHIFT 0x14
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT21_IS_STORM_CLIENT__SHIFT 0x15
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT22_IS_STORM_CLIENT__SHIFT 0x16
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT23_IS_STORM_CLIENT__SHIFT 0x17
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT24_IS_STORM_CLIENT__SHIFT 0x18
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT25_IS_STORM_CLIENT__SHIFT 0x19
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT26_IS_STORM_CLIENT__SHIFT 0x1a
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT27_IS_STORM_CLIENT__SHIFT 0x1b
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT28_IS_STORM_CLIENT__SHIFT 0x1c
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT29_IS_STORM_CLIENT__SHIFT 0x1d
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT__SHIFT 0x1e
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT__SHIFT 0x1f
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT1_IS_STORM_CLIENT_MASK 0x00000002L
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT2_IS_STORM_CLIENT_MASK 0x00000004L
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT3_IS_STORM_CLIENT_MASK 0x00000008L
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT4_IS_STORM_CLIENT_MASK 0x00000010L
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT5_IS_STORM_CLIENT_MASK 0x00000020L
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT6_IS_STORM_CLIENT_MASK 0x00000040L
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT7_IS_STORM_CLIENT_MASK 0x00000080L
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT8_IS_STORM_CLIENT_MASK 0x00000100L
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT9_IS_STORM_CLIENT_MASK 0x00000200L
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT10_IS_STORM_CLIENT_MASK 0x00000400L
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT11_IS_STORM_CLIENT_MASK 0x00000800L
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT12_IS_STORM_CLIENT_MASK 0x00001000L
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT13_IS_STORM_CLIENT_MASK 0x00002000L
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT14_IS_STORM_CLIENT_MASK 0x00004000L
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT15_IS_STORM_CLIENT_MASK 0x00008000L
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT16_IS_STORM_CLIENT_MASK 0x00010000L
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT17_IS_STORM_CLIENT_MASK 0x00020000L
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT18_IS_STORM_CLIENT_MASK 0x00040000L
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT19_IS_STORM_CLIENT_MASK 0x00080000L
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT20_IS_STORM_CLIENT_MASK 0x00100000L
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT21_IS_STORM_CLIENT_MASK 0x00200000L
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT22_IS_STORM_CLIENT_MASK 0x00400000L
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT23_IS_STORM_CLIENT_MASK 0x00800000L
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT24_IS_STORM_CLIENT_MASK 0x01000000L
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT25_IS_STORM_CLIENT_MASK 0x02000000L
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT26_IS_STORM_CLIENT_MASK 0x04000000L
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT27_IS_STORM_CLIENT_MASK 0x08000000L
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT28_IS_STORM_CLIENT_MASK 0x10000000L
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT29_IS_STORM_CLIENT_MASK 0x20000000L
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT_MASK 0x40000000L
-#define IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT_MASK 0x80000000L
-//IH_CLK_CTRL
-#define IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE__SHIFT 0x1b
-#define IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE__SHIFT 0x1c
-#define IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE__SHIFT 0x1d
-#define IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1e
-#define IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE__SHIFT 0x1f
-#define IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE_MASK 0x08000000L
-#define IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE_MASK 0x10000000L
-#define IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE_MASK 0x20000000L
-#define IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE_MASK 0x40000000L
-#define IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE_MASK 0x80000000L
-//IH_INT_FLAGS
-#define IH_INT_FLAGS__CLIENT_0_FLAG__SHIFT 0x0
-#define IH_INT_FLAGS__CLIENT_1_FLAG__SHIFT 0x1
-#define IH_INT_FLAGS__CLIENT_2_FLAG__SHIFT 0x2
-#define IH_INT_FLAGS__CLIENT_3_FLAG__SHIFT 0x3
-#define IH_INT_FLAGS__CLIENT_4_FLAG__SHIFT 0x4
-#define IH_INT_FLAGS__CLIENT_5_FLAG__SHIFT 0x5
-#define IH_INT_FLAGS__CLIENT_6_FLAG__SHIFT 0x6
-#define IH_INT_FLAGS__CLIENT_7_FLAG__SHIFT 0x7
-#define IH_INT_FLAGS__CLIENT_8_FLAG__SHIFT 0x8
-#define IH_INT_FLAGS__CLIENT_9_FLAG__SHIFT 0x9
-#define IH_INT_FLAGS__CLIENT_10_FLAG__SHIFT 0xa
-#define IH_INT_FLAGS__CLIENT_11_FLAG__SHIFT 0xb
-#define IH_INT_FLAGS__CLIENT_12_FLAG__SHIFT 0xc
-#define IH_INT_FLAGS__CLIENT_13_FLAG__SHIFT 0xd
-#define IH_INT_FLAGS__CLIENT_14_FLAG__SHIFT 0xe
-#define IH_INT_FLAGS__CLIENT_15_FLAG__SHIFT 0xf
-#define IH_INT_FLAGS__CLIENT_16_FLAG__SHIFT 0x10
-#define IH_INT_FLAGS__CLIENT_17_FLAG__SHIFT 0x11
-#define IH_INT_FLAGS__CLIENT_18_FLAG__SHIFT 0x12
-#define IH_INT_FLAGS__CLIENT_19_FLAG__SHIFT 0x13
-#define IH_INT_FLAGS__CLIENT_20_FLAG__SHIFT 0x14
-#define IH_INT_FLAGS__CLIENT_21_FLAG__SHIFT 0x15
-#define IH_INT_FLAGS__CLIENT_22_FLAG__SHIFT 0x16
-#define IH_INT_FLAGS__CLIENT_23_FLAG__SHIFT 0x17
-#define IH_INT_FLAGS__CLIENT_24_FLAG__SHIFT 0x18
-#define IH_INT_FLAGS__CLIENT_25_FLAG__SHIFT 0x19
-#define IH_INT_FLAGS__CLIENT_26_FLAG__SHIFT 0x1a
-#define IH_INT_FLAGS__CLIENT_27_FLAG__SHIFT 0x1b
-#define IH_INT_FLAGS__CLIENT_28_FLAG__SHIFT 0x1c
-#define IH_INT_FLAGS__CLIENT_29_FLAG__SHIFT 0x1d
-#define IH_INT_FLAGS__CLIENT_30_FLAG__SHIFT 0x1e
-#define IH_INT_FLAGS__CLIENT_31_FLAG__SHIFT 0x1f
-#define IH_INT_FLAGS__CLIENT_0_FLAG_MASK 0x00000001L
-#define IH_INT_FLAGS__CLIENT_1_FLAG_MASK 0x00000002L
-#define IH_INT_FLAGS__CLIENT_2_FLAG_MASK 0x00000004L
-#define IH_INT_FLAGS__CLIENT_3_FLAG_MASK 0x00000008L
-#define IH_INT_FLAGS__CLIENT_4_FLAG_MASK 0x00000010L
-#define IH_INT_FLAGS__CLIENT_5_FLAG_MASK 0x00000020L
-#define IH_INT_FLAGS__CLIENT_6_FLAG_MASK 0x00000040L
-#define IH_INT_FLAGS__CLIENT_7_FLAG_MASK 0x00000080L
-#define IH_INT_FLAGS__CLIENT_8_FLAG_MASK 0x00000100L
-#define IH_INT_FLAGS__CLIENT_9_FLAG_MASK 0x00000200L
-#define IH_INT_FLAGS__CLIENT_10_FLAG_MASK 0x00000400L
-#define IH_INT_FLAGS__CLIENT_11_FLAG_MASK 0x00000800L
-#define IH_INT_FLAGS__CLIENT_12_FLAG_MASK 0x00001000L
-#define IH_INT_FLAGS__CLIENT_13_FLAG_MASK 0x00002000L
-#define IH_INT_FLAGS__CLIENT_14_FLAG_MASK 0x00004000L
-#define IH_INT_FLAGS__CLIENT_15_FLAG_MASK 0x00008000L
-#define IH_INT_FLAGS__CLIENT_16_FLAG_MASK 0x00010000L
-#define IH_INT_FLAGS__CLIENT_17_FLAG_MASK 0x00020000L
-#define IH_INT_FLAGS__CLIENT_18_FLAG_MASK 0x00040000L
-#define IH_INT_FLAGS__CLIENT_19_FLAG_MASK 0x00080000L
-#define IH_INT_FLAGS__CLIENT_20_FLAG_MASK 0x00100000L
-#define IH_INT_FLAGS__CLIENT_21_FLAG_MASK 0x00200000L
-#define IH_INT_FLAGS__CLIENT_22_FLAG_MASK 0x00400000L
-#define IH_INT_FLAGS__CLIENT_23_FLAG_MASK 0x00800000L
-#define IH_INT_FLAGS__CLIENT_24_FLAG_MASK 0x01000000L
-#define IH_INT_FLAGS__CLIENT_25_FLAG_MASK 0x02000000L
-#define IH_INT_FLAGS__CLIENT_26_FLAG_MASK 0x04000000L
-#define IH_INT_FLAGS__CLIENT_27_FLAG_MASK 0x08000000L
-#define IH_INT_FLAGS__CLIENT_28_FLAG_MASK 0x10000000L
-#define IH_INT_FLAGS__CLIENT_29_FLAG_MASK 0x20000000L
-#define IH_INT_FLAGS__CLIENT_30_FLAG_MASK 0x40000000L
-#define IH_INT_FLAGS__CLIENT_31_FLAG_MASK 0x80000000L
-//IH_LAST_INT_INFO0
-#define IH_LAST_INT_INFO0__CLIENT_ID__SHIFT 0x0
-#define IH_LAST_INT_INFO0__SOURCE_ID__SHIFT 0x8
-#define IH_LAST_INT_INFO0__RING_ID__SHIFT 0x10
-#define IH_LAST_INT_INFO0__VM_ID__SHIFT 0x18
-#define IH_LAST_INT_INFO0__VMID_TYPE__SHIFT 0x1f
-#define IH_LAST_INT_INFO0__CLIENT_ID_MASK 0x000000FFL
-#define IH_LAST_INT_INFO0__SOURCE_ID_MASK 0x0000FF00L
-#define IH_LAST_INT_INFO0__RING_ID_MASK 0x00FF0000L
-#define IH_LAST_INT_INFO0__VM_ID_MASK 0x0F000000L
-#define IH_LAST_INT_INFO0__VMID_TYPE_MASK 0x80000000L
-//IH_LAST_INT_INFO1
-#define IH_LAST_INT_INFO1__CONTEXT_ID__SHIFT 0x0
-#define IH_LAST_INT_INFO1__CONTEXT_ID_MASK 0xFFFFFFFFL
-//IH_LAST_INT_INFO2
-#define IH_LAST_INT_INFO2__PAS_ID__SHIFT 0x0
-#define IH_LAST_INT_INFO2__VF_ID__SHIFT 0x10
-#define IH_LAST_INT_INFO2__VF__SHIFT 0x14
-#define IH_LAST_INT_INFO2__PAS_ID_MASK 0x0000FFFFL
-#define IH_LAST_INT_INFO2__VF_ID_MASK 0x000F0000L
-#define IH_LAST_INT_INFO2__VF_MASK 0x00100000L
-//IH_SCRATCH
-#define IH_SCRATCH__DATA__SHIFT 0x0
-#define IH_SCRATCH__DATA_MASK 0xFFFFFFFFL
-//IH_CLIENT_CREDIT_ERROR
-#define IH_CLIENT_CREDIT_ERROR__CLEAR__SHIFT 0x0
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_1_ERROR__SHIFT 0x1
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_2_ERROR__SHIFT 0x2
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_3_ERROR__SHIFT 0x3
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_4_ERROR__SHIFT 0x4
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_5_ERROR__SHIFT 0x5
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_6_ERROR__SHIFT 0x6
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_7_ERROR__SHIFT 0x7
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_8_ERROR__SHIFT 0x8
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_9_ERROR__SHIFT 0x9
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_10_ERROR__SHIFT 0xa
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_11_ERROR__SHIFT 0xb
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_12_ERROR__SHIFT 0xc
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_13_ERROR__SHIFT 0xd
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_14_ERROR__SHIFT 0xe
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_15_ERROR__SHIFT 0xf
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_16_ERROR__SHIFT 0x10
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_17_ERROR__SHIFT 0x11
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_18_ERROR__SHIFT 0x12
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_19_ERROR__SHIFT 0x13
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_20_ERROR__SHIFT 0x14
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_21_ERROR__SHIFT 0x15
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_22_ERROR__SHIFT 0x16
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_23_ERROR__SHIFT 0x17
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_24_ERROR__SHIFT 0x18
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_25_ERROR__SHIFT 0x19
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_26_ERROR__SHIFT 0x1a
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_27_ERROR__SHIFT 0x1b
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_28_ERROR__SHIFT 0x1c
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_29_ERROR__SHIFT 0x1d
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_30_ERROR__SHIFT 0x1e
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_31_ERROR__SHIFT 0x1f
-#define IH_CLIENT_CREDIT_ERROR__CLEAR_MASK 0x00000001L
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_1_ERROR_MASK 0x00000002L
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_2_ERROR_MASK 0x00000004L
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_3_ERROR_MASK 0x00000008L
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_4_ERROR_MASK 0x00000010L
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_5_ERROR_MASK 0x00000020L
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_6_ERROR_MASK 0x00000040L
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_7_ERROR_MASK 0x00000080L
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_8_ERROR_MASK 0x00000100L
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_9_ERROR_MASK 0x00000200L
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_10_ERROR_MASK 0x00000400L
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_11_ERROR_MASK 0x00000800L
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_12_ERROR_MASK 0x00001000L
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_13_ERROR_MASK 0x00002000L
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_14_ERROR_MASK 0x00004000L
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_15_ERROR_MASK 0x00008000L
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_16_ERROR_MASK 0x00010000L
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_17_ERROR_MASK 0x00020000L
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_18_ERROR_MASK 0x00040000L
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_19_ERROR_MASK 0x00080000L
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_20_ERROR_MASK 0x00100000L
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_21_ERROR_MASK 0x00200000L
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_22_ERROR_MASK 0x00400000L
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_23_ERROR_MASK 0x00800000L
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_24_ERROR_MASK 0x01000000L
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_25_ERROR_MASK 0x02000000L
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_26_ERROR_MASK 0x04000000L
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_27_ERROR_MASK 0x08000000L
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_28_ERROR_MASK 0x10000000L
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_29_ERROR_MASK 0x20000000L
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_30_ERROR_MASK 0x40000000L
-#define IH_CLIENT_CREDIT_ERROR__CLIENT_31_ERROR_MASK 0x80000000L
-//IH_GPU_IOV_VIOLATION_LOG
-#define IH_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0
-#define IH_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1
-#define IH_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2
-#define IH_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x12
-#define IH_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13
-#define IH_GPU_IOV_VIOLATION_LOG__VF_ID__SHIFT 0x14
-#define IH_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18
-#define IH_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L
-#define IH_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L
-#define IH_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL
-#define IH_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00040000L
-#define IH_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L
-#define IH_GPU_IOV_VIOLATION_LOG__VF_ID_MASK 0x00F00000L
-#define IH_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L
-//IH_COOKIE_REC_VIOLATION_LOG
-#define IH_COOKIE_REC_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0
-#define IH_COOKIE_REC_VIOLATION_LOG__CLIENT_ID__SHIFT 0x10
-#define IH_COOKIE_REC_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18
-#define IH_COOKIE_REC_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L
-#define IH_COOKIE_REC_VIOLATION_LOG__CLIENT_ID_MASK 0x00FF0000L
-#define IH_COOKIE_REC_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L
-//IH_CREDIT_STATUS
-#define IH_CREDIT_STATUS__CLIENT_1_CREDIT_RETURNED__SHIFT 0x1
-#define IH_CREDIT_STATUS__CLIENT_2_CREDIT_RETURNED__SHIFT 0x2
-#define IH_CREDIT_STATUS__CLIENT_3_CREDIT_RETURNED__SHIFT 0x3
-#define IH_CREDIT_STATUS__CLIENT_4_CREDIT_RETURNED__SHIFT 0x4
-#define IH_CREDIT_STATUS__CLIENT_5_CREDIT_RETURNED__SHIFT 0x5
-#define IH_CREDIT_STATUS__CLIENT_6_CREDIT_RETURNED__SHIFT 0x6
-#define IH_CREDIT_STATUS__CLIENT_7_CREDIT_RETURNED__SHIFT 0x7
-#define IH_CREDIT_STATUS__CLIENT_8_CREDIT_RETURNED__SHIFT 0x8
-#define IH_CREDIT_STATUS__CLIENT_9_CREDIT_RETURNED__SHIFT 0x9
-#define IH_CREDIT_STATUS__CLIENT_10_CREDIT_RETURNED__SHIFT 0xa
-#define IH_CREDIT_STATUS__CLIENT_11_CREDIT_RETURNED__SHIFT 0xb
-#define IH_CREDIT_STATUS__CLIENT_12_CREDIT_RETURNED__SHIFT 0xc
-#define IH_CREDIT_STATUS__CLIENT_13_CREDIT_RETURNED__SHIFT 0xd
-#define IH_CREDIT_STATUS__CLIENT_14_CREDIT_RETURNED__SHIFT 0xe
-#define IH_CREDIT_STATUS__CLIENT_15_CREDIT_RETURNED__SHIFT 0xf
-#define IH_CREDIT_STATUS__CLIENT_16_CREDIT_RETURNED__SHIFT 0x10
-#define IH_CREDIT_STATUS__CLIENT_17_CREDIT_RETURNED__SHIFT 0x11
-#define IH_CREDIT_STATUS__CLIENT_18_CREDIT_RETURNED__SHIFT 0x12
-#define IH_CREDIT_STATUS__CLIENT_19_CREDIT_RETURNED__SHIFT 0x13
-#define IH_CREDIT_STATUS__CLIENT_20_CREDIT_RETURNED__SHIFT 0x14
-#define IH_CREDIT_STATUS__CLIENT_21_CREDIT_RETURNED__SHIFT 0x15
-#define IH_CREDIT_STATUS__CLIENT_22_CREDIT_RETURNED__SHIFT 0x16
-#define IH_CREDIT_STATUS__CLIENT_23_CREDIT_RETURNED__SHIFT 0x17
-#define IH_CREDIT_STATUS__CLIENT_24_CREDIT_RETURNED__SHIFT 0x18
-#define IH_CREDIT_STATUS__CLIENT_25_CREDIT_RETURNED__SHIFT 0x19
-#define IH_CREDIT_STATUS__CLIENT_26_CREDIT_RETURNED__SHIFT 0x1a
-#define IH_CREDIT_STATUS__CLIENT_27_CREDIT_RETURNED__SHIFT 0x1b
-#define IH_CREDIT_STATUS__CLIENT_28_CREDIT_RETURNED__SHIFT 0x1c
-#define IH_CREDIT_STATUS__CLIENT_29_CREDIT_RETURNED__SHIFT 0x1d
-#define IH_CREDIT_STATUS__CLIENT_30_CREDIT_RETURNED__SHIFT 0x1e
-#define IH_CREDIT_STATUS__CLIENT_31_CREDIT_RETURNED__SHIFT 0x1f
-#define IH_CREDIT_STATUS__CLIENT_1_CREDIT_RETURNED_MASK 0x00000002L
-#define IH_CREDIT_STATUS__CLIENT_2_CREDIT_RETURNED_MASK 0x00000004L
-#define IH_CREDIT_STATUS__CLIENT_3_CREDIT_RETURNED_MASK 0x00000008L
-#define IH_CREDIT_STATUS__CLIENT_4_CREDIT_RETURNED_MASK 0x00000010L
-#define IH_CREDIT_STATUS__CLIENT_5_CREDIT_RETURNED_MASK 0x00000020L
-#define IH_CREDIT_STATUS__CLIENT_6_CREDIT_RETURNED_MASK 0x00000040L
-#define IH_CREDIT_STATUS__CLIENT_7_CREDIT_RETURNED_MASK 0x00000080L
-#define IH_CREDIT_STATUS__CLIENT_8_CREDIT_RETURNED_MASK 0x00000100L
-#define IH_CREDIT_STATUS__CLIENT_9_CREDIT_RETURNED_MASK 0x00000200L
-#define IH_CREDIT_STATUS__CLIENT_10_CREDIT_RETURNED_MASK 0x00000400L
-#define IH_CREDIT_STATUS__CLIENT_11_CREDIT_RETURNED_MASK 0x00000800L
-#define IH_CREDIT_STATUS__CLIENT_12_CREDIT_RETURNED_MASK 0x00001000L
-#define IH_CREDIT_STATUS__CLIENT_13_CREDIT_RETURNED_MASK 0x00002000L
-#define IH_CREDIT_STATUS__CLIENT_14_CREDIT_RETURNED_MASK 0x00004000L
-#define IH_CREDIT_STATUS__CLIENT_15_CREDIT_RETURNED_MASK 0x00008000L
-#define IH_CREDIT_STATUS__CLIENT_16_CREDIT_RETURNED_MASK 0x00010000L
-#define IH_CREDIT_STATUS__CLIENT_17_CREDIT_RETURNED_MASK 0x00020000L
-#define IH_CREDIT_STATUS__CLIENT_18_CREDIT_RETURNED_MASK 0x00040000L
-#define IH_CREDIT_STATUS__CLIENT_19_CREDIT_RETURNED_MASK 0x00080000L
-#define IH_CREDIT_STATUS__CLIENT_20_CREDIT_RETURNED_MASK 0x00100000L
-#define IH_CREDIT_STATUS__CLIENT_21_CREDIT_RETURNED_MASK 0x00200000L
-#define IH_CREDIT_STATUS__CLIENT_22_CREDIT_RETURNED_MASK 0x00400000L
-#define IH_CREDIT_STATUS__CLIENT_23_CREDIT_RETURNED_MASK 0x00800000L
-#define IH_CREDIT_STATUS__CLIENT_24_CREDIT_RETURNED_MASK 0x01000000L
-#define IH_CREDIT_STATUS__CLIENT_25_CREDIT_RETURNED_MASK 0x02000000L
-#define IH_CREDIT_STATUS__CLIENT_26_CREDIT_RETURNED_MASK 0x04000000L
-#define IH_CREDIT_STATUS__CLIENT_27_CREDIT_RETURNED_MASK 0x08000000L
-#define IH_CREDIT_STATUS__CLIENT_28_CREDIT_RETURNED_MASK 0x10000000L
-#define IH_CREDIT_STATUS__CLIENT_29_CREDIT_RETURNED_MASK 0x20000000L
-#define IH_CREDIT_STATUS__CLIENT_30_CREDIT_RETURNED_MASK 0x40000000L
-#define IH_CREDIT_STATUS__CLIENT_31_CREDIT_RETURNED_MASK 0x80000000L
-//IH_MMHUB_ERROR
-#define IH_MMHUB_ERROR__IH_BRESP_01__SHIFT 0x1
-#define IH_MMHUB_ERROR__IH_BRESP_10__SHIFT 0x2
-#define IH_MMHUB_ERROR__IH_BRESP_11__SHIFT 0x3
-#define IH_MMHUB_ERROR__IH_BUSER_NACK_01__SHIFT 0x5
-#define IH_MMHUB_ERROR__IH_BUSER_NACK_10__SHIFT 0x6
-#define IH_MMHUB_ERROR__IH_BUSER_NACK_11__SHIFT 0x7
-#define IH_MMHUB_ERROR__IH_BRESP_01_MASK 0x00000002L
-#define IH_MMHUB_ERROR__IH_BRESP_10_MASK 0x00000004L
-#define IH_MMHUB_ERROR__IH_BRESP_11_MASK 0x00000008L
-#define IH_MMHUB_ERROR__IH_BUSER_NACK_01_MASK 0x00000020L
-#define IH_MMHUB_ERROR__IH_BUSER_NACK_10_MASK 0x00000040L
-#define IH_MMHUB_ERROR__IH_BUSER_NACK_11_MASK 0x00000080L
-//IH_REGISTER_LAST_PART2
-#define IH_REGISTER_LAST_PART2__RESERVED__SHIFT 0x0
-#define IH_REGISTER_LAST_PART2__RESERVED_MASK 0xFFFFFFFFL
-//SEM_CLK_CTRL
-#define SEM_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define SEM_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define SEM_CLK_CTRL__RESERVED__SHIFT 0xc
-#define SEM_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define SEM_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define SEM_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define SEM_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define SEM_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define SEM_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define SEM_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
-#define SEM_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
-#define SEM_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define SEM_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define SEM_CLK_CTRL__RESERVED_MASK 0x00FFF000L
-#define SEM_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
-#define SEM_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
-#define SEM_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
-#define SEM_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
-#define SEM_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
-#define SEM_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
-#define SEM_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
-#define SEM_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
-//SEM_UTC_CREDIT
-#define SEM_UTC_CREDIT__UTCL2_CREDIT__SHIFT 0x0
-#define SEM_UTC_CREDIT__WATERMARK__SHIFT 0x8
-#define SEM_UTC_CREDIT__UTCL2_CREDIT_MASK 0x0000001FL
-#define SEM_UTC_CREDIT__WATERMARK_MASK 0x00000F00L
-//SEM_UTC_CONFIG
-#define SEM_UTC_CONFIG__USE_MTYPE__SHIFT 0x0
-#define SEM_UTC_CONFIG__FORCE_SNOOP__SHIFT 0x3
-#define SEM_UTC_CONFIG__FORCE_GCC__SHIFT 0x4
-#define SEM_UTC_CONFIG__USE_PT_SNOOP__SHIFT 0x5
-#define SEM_UTC_CONFIG__USE_MTYPE_MASK 0x00000007L
-#define SEM_UTC_CONFIG__FORCE_SNOOP_MASK 0x00000008L
-#define SEM_UTC_CONFIG__FORCE_GCC_MASK 0x00000010L
-#define SEM_UTC_CONFIG__USE_PT_SNOOP_MASK 0x00000020L
-//SEM_UTCL2_TRAN_EN_LUT
-#define SEM_UTCL2_TRAN_EN_LUT__SDMA0_UTCL2_EN__SHIFT 0x0
-#define SEM_UTCL2_TRAN_EN_LUT__SDMA1_UTCL2_EN__SHIFT 0x1
-#define SEM_UTCL2_TRAN_EN_LUT__UVD_UTCL2_EN__SHIFT 0x2
-#define SEM_UTCL2_TRAN_EN_LUT__VCE0_UTCL2_EN__SHIFT 0x3
-#define SEM_UTCL2_TRAN_EN_LUT__ACP_UTCL2_EN__SHIFT 0x4
-#define SEM_UTCL2_TRAN_EN_LUT__ISP_UTCL2_EN__SHIFT 0x5
-#define SEM_UTCL2_TRAN_EN_LUT__VCE1_UTCL2_EN__SHIFT 0x6
-#define SEM_UTCL2_TRAN_EN_LUT__VP8_UTCL2_EN__SHIFT 0x7
-#define SEM_UTCL2_TRAN_EN_LUT__RESERVED__SHIFT 0x8
-#define SEM_UTCL2_TRAN_EN_LUT__CP_UTCL2_EN__SHIFT 0x1f
-#define SEM_UTCL2_TRAN_EN_LUT__SDMA0_UTCL2_EN_MASK 0x00000001L
-#define SEM_UTCL2_TRAN_EN_LUT__SDMA1_UTCL2_EN_MASK 0x00000002L
-#define SEM_UTCL2_TRAN_EN_LUT__UVD_UTCL2_EN_MASK 0x00000004L
-#define SEM_UTCL2_TRAN_EN_LUT__VCE0_UTCL2_EN_MASK 0x00000008L
-#define SEM_UTCL2_TRAN_EN_LUT__ACP_UTCL2_EN_MASK 0x00000010L
-#define SEM_UTCL2_TRAN_EN_LUT__ISP_UTCL2_EN_MASK 0x00000020L
-#define SEM_UTCL2_TRAN_EN_LUT__VCE1_UTCL2_EN_MASK 0x00000040L
-#define SEM_UTCL2_TRAN_EN_LUT__VP8_UTCL2_EN_MASK 0x00000080L
-#define SEM_UTCL2_TRAN_EN_LUT__RESERVED_MASK 0x7FFFFF00L
-#define SEM_UTCL2_TRAN_EN_LUT__CP_UTCL2_EN_MASK 0x80000000L
-//SEM_MCIF_CONFIG
-#define SEM_MCIF_CONFIG__MC_REQ_SWAP__SHIFT 0x0
-#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT__SHIFT 0x2
-#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT__SHIFT 0x8
-#define SEM_MCIF_CONFIG__MC_REQ_SWAP_MASK 0x00000003L
-#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT_MASK 0x000000FCL
-#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT_MASK 0x00003F00L
-//SEM_PERFMON_CNTL
-#define SEM_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
-#define SEM_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
-#define SEM_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
-#define SEM_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa
-#define SEM_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb
-#define SEM_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc
-#define SEM_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L
-#define SEM_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L
-#define SEM_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL
-#define SEM_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L
-#define SEM_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L
-#define SEM_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L
-//SEM_PERFCOUNTER0_RESULT
-#define SEM_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
-#define SEM_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
-//SEM_PERFCOUNTER1_RESULT
-#define SEM_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
-#define SEM_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
-//SEM_STATUS
-#define SEM_STATUS__SEM_IDLE__SHIFT 0x0
-#define SEM_STATUS__SEM_INTERNAL_IDLE__SHIFT 0x1
-#define SEM_STATUS__MC_RDREQ_FIFO_FULL__SHIFT 0x2
-#define SEM_STATUS__MC_WRREQ_FIFO_FULL__SHIFT 0x3
-#define SEM_STATUS__WRITE1_FIFO_FULL__SHIFT 0x4
-#define SEM_STATUS__CHECK0_FIFO_FULL__SHIFT 0x5
-#define SEM_STATUS__MC_RDREQ_PENDING__SHIFT 0x6
-#define SEM_STATUS__MC_WRREQ_PENDING__SHIFT 0x7
-#define SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT 0x8
-#define SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT 0x9
-#define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0xa
-#define SEM_STATUS__VCE_MAILBOX_PENDING__SHIFT 0xb
-#define SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT 0xc
-#define SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT 0xd
-#define SEM_STATUS__VCE1_MAILBOX_PENDING__SHIFT 0xe
-#define SEM_STATUS__ATC_REQ_PENDING__SHIFT 0xf
-#define SEM_STATUS__OUTSTANDING_CLEAN__SHIFT 0x10
-#define SEM_STATUS__INVREQ_FLUSH_VF_MISMATCH__SHIFT 0x11
-#define SEM_STATUS__INVREQ_NONFLUSH_VF_MISMATCH__SHIFT 0x12
-#define SEM_STATUS__INVREQ_CNT_IDLE__SHIFT 0x13
-#define SEM_STATUS__ENTRYLIST_IDLE__SHIFT 0x14
-#define SEM_STATUS__MIF_IDLE__SHIFT 0x15
-#define SEM_STATUS__REGISTER_IDLE__SHIFT 0x16
-#define SEM_STATUS__ATCL2_INVREQ_IDLE__SHIFT 0x17
-#define SEM_STATUS__SWITCH_READY__SHIFT 0x1f
-#define SEM_STATUS__SEM_IDLE_MASK 0x00000001L
-#define SEM_STATUS__SEM_INTERNAL_IDLE_MASK 0x00000002L
-#define SEM_STATUS__MC_RDREQ_FIFO_FULL_MASK 0x00000004L
-#define SEM_STATUS__MC_WRREQ_FIFO_FULL_MASK 0x00000008L
-#define SEM_STATUS__WRITE1_FIFO_FULL_MASK 0x00000010L
-#define SEM_STATUS__CHECK0_FIFO_FULL_MASK 0x00000020L
-#define SEM_STATUS__MC_RDREQ_PENDING_MASK 0x00000040L
-#define SEM_STATUS__MC_WRREQ_PENDING_MASK 0x00000080L
-#define SEM_STATUS__SDMA0_MAILBOX_PENDING_MASK 0x00000100L
-#define SEM_STATUS__SDMA1_MAILBOX_PENDING_MASK 0x00000200L
-#define SEM_STATUS__UVD_MAILBOX_PENDING_MASK 0x00000400L
-#define SEM_STATUS__VCE_MAILBOX_PENDING_MASK 0x00000800L
-#define SEM_STATUS__CPG1_MAILBOX_PENDING_MASK 0x00001000L
-#define SEM_STATUS__CPG2_MAILBOX_PENDING_MASK 0x00002000L
-#define SEM_STATUS__VCE1_MAILBOX_PENDING_MASK 0x00004000L
-#define SEM_STATUS__ATC_REQ_PENDING_MASK 0x00008000L
-#define SEM_STATUS__OUTSTANDING_CLEAN_MASK 0x00010000L
-#define SEM_STATUS__INVREQ_FLUSH_VF_MISMATCH_MASK 0x00020000L
-#define SEM_STATUS__INVREQ_NONFLUSH_VF_MISMATCH_MASK 0x00040000L
-#define SEM_STATUS__INVREQ_CNT_IDLE_MASK 0x00080000L
-#define SEM_STATUS__ENTRYLIST_IDLE_MASK 0x00100000L
-#define SEM_STATUS__MIF_IDLE_MASK 0x00200000L
-#define SEM_STATUS__REGISTER_IDLE_MASK 0x00400000L
-#define SEM_STATUS__ATCL2_INVREQ_IDLE_MASK 0x00800000L
-#define SEM_STATUS__SWITCH_READY_MASK 0x80000000L
-//SEM_MAILBOX_CLIENTCONFIG
-#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0__SHIFT 0x0
-#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1__SHIFT 0x3
-#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2__SHIFT 0x6
-#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3__SHIFT 0x9
-#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT 0xc
-#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0xf
-#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT 0x12
-#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0__SHIFT 0x15
-#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0_MASK 0x00000007L
-#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1_MASK 0x00000038L
-#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2_MASK 0x000001C0L
-#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3_MASK 0x00000E00L
-#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0_MASK 0x00007000L
-#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0_MASK 0x00038000L
-#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0_MASK 0x001C0000L
-#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0_MASK 0x00E00000L
-//SEM_MAILBOX
-#define SEM_MAILBOX__HOSTPORT__SHIFT 0x0
-#define SEM_MAILBOX__RESERVED__SHIFT 0x10
-#define SEM_MAILBOX__HOSTPORT_MASK 0x0000FFFFL
-#define SEM_MAILBOX__RESERVED_MASK 0xFFFF0000L
-//SEM_MAILBOX_CONTROL
-#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x0
-#define SEM_MAILBOX_CONTROL__RESERVED__SHIFT 0x10
-#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_MASK 0x0000FFFFL
-#define SEM_MAILBOX_CONTROL__RESERVED_MASK 0xFFFF0000L
-//SEM_CHICKEN_BITS
-#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN__SHIFT 0x0
-#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN__SHIFT 0x1
-#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN__SHIFT 0x2
-#define SEM_CHICKEN_BITS__ECC_BEHAVIOR__SHIFT 0x3
-#define SEM_CHICKEN_BITS__PHY_TRAN_EN__SHIFT 0x6
-#define SEM_CHICKEN_BITS__ADDR_CMP_UNTRAN_EN__SHIFT 0x7
-#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX__SHIFT 0x8
-#define SEM_CHICKEN_BITS__OUTSTANDING_CLEAN_COUNTER_INDEX__SHIFT 0xa
-#define SEM_CHICKEN_BITS__ATCL2_BUS_ID__SHIFT 0xc
-#define SEM_CHICKEN_BITS__ATOMIC_EN__SHIFT 0xe
-#define SEM_CHICKEN_BITS__EXTERNAL_ATOMIC_CHECK__SHIFT 0xf
-#define SEM_CHICKEN_BITS__CLEAR_MAILBOX__SHIFT 0x10
-#define SEM_CHICKEN_BITS__INVACK_AFTER_OUTSTANDING_CLEAN__SHIFT 0x12
-#define SEM_CHICKEN_BITS__UTC_TAG_CONFLICT_CHECK__SHIFT 0x13
-#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN_MASK 0x00000001L
-#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN_MASK 0x00000002L
-#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN_MASK 0x00000004L
-#define SEM_CHICKEN_BITS__ECC_BEHAVIOR_MASK 0x00000018L
-#define SEM_CHICKEN_BITS__PHY_TRAN_EN_MASK 0x00000040L
-#define SEM_CHICKEN_BITS__ADDR_CMP_UNTRAN_EN_MASK 0x00000080L
-#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX_MASK 0x00000300L
-#define SEM_CHICKEN_BITS__OUTSTANDING_CLEAN_COUNTER_INDEX_MASK 0x00000C00L
-#define SEM_CHICKEN_BITS__ATCL2_BUS_ID_MASK 0x00003000L
-#define SEM_CHICKEN_BITS__ATOMIC_EN_MASK 0x00004000L
-#define SEM_CHICKEN_BITS__EXTERNAL_ATOMIC_CHECK_MASK 0x00008000L
-#define SEM_CHICKEN_BITS__CLEAR_MAILBOX_MASK 0x00030000L
-#define SEM_CHICKEN_BITS__INVACK_AFTER_OUTSTANDING_CLEAN_MASK 0x00040000L
-#define SEM_CHICKEN_BITS__UTC_TAG_CONFLICT_CHECK_MASK 0x00080000L
-//SEM_MAILBOX_CLIENTCONFIG_EXTRA
-#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0__SHIFT 0x0
-#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0_MASK 0x0000000FL
-//SEM_GPU_IOV_VIOLATION_LOG
-#define SEM_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0
-#define SEM_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1
-#define SEM_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2
-#define SEM_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x12
-#define SEM_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13
-#define SEM_GPU_IOV_VIOLATION_LOG__VF_ID__SHIFT 0x14
-#define SEM_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18
-#define SEM_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L
-#define SEM_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L
-#define SEM_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL
-#define SEM_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00040000L
-#define SEM_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L
-#define SEM_GPU_IOV_VIOLATION_LOG__VF_ID_MASK 0x00F00000L
-#define SEM_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L
-//SEM_OUTSTANDING_THRESHOLD
-#define SEM_OUTSTANDING_THRESHOLD__VALUE__SHIFT 0x0
-#define SEM_OUTSTANDING_THRESHOLD__VALUE_MASK 0x000000FFL
-//SEM_REGISTER_LAST_PART2
-#define SEM_REGISTER_LAST_PART2__RESERVED__SHIFT 0x0
-#define SEM_REGISTER_LAST_PART2__RESERVED_MASK 0xFFFFFFFFL
-//IH_ACTIVE_FCN_ID
-#define IH_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0
-#define IH_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4
-#define IH_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f
-#define IH_ACTIVE_FCN_ID__VF_ID_MASK 0x0000000FL
-#define IH_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L
-#define IH_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L
-//IH_VIRT_RESET_REQ
-#define IH_VIRT_RESET_REQ__VF__SHIFT 0x0
-#define IH_VIRT_RESET_REQ__PF__SHIFT 0x1f
-#define IH_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL
-#define IH_VIRT_RESET_REQ__PF_MASK 0x80000000L
-//IH_CLIENT_CFG
-#define IH_CLIENT_CFG__TOTAL_CLIENT_NUM__SHIFT 0x0
-#define IH_CLIENT_CFG__TOTAL_CLIENT_NUM_MASK 0x0000001FL
-//IH_CLIENT_CFG_INDEX
-#define IH_CLIENT_CFG_INDEX__INDEX__SHIFT 0x0
-#define IH_CLIENT_CFG_INDEX__INDEX_MASK 0x0000001FL
-//IH_CLIENT_CFG_DATA
-#define IH_CLIENT_CFG_DATA__CREDIT_RETURN_ADDR__SHIFT 0x0
-#define IH_CLIENT_CFG_DATA__CLIENT_TYPE__SHIFT 0x12
-#define IH_CLIENT_CFG_DATA__RING_ID__SHIFT 0x14
-#define IH_CLIENT_CFG_DATA__VF_RB_SELECT__SHIFT 0x16
-#define IH_CLIENT_CFG_DATA__OVERWRITE_RING_ID_WITH_ACTIVE_FCN_ID__SHIFT 0x18
-#define IH_CLIENT_CFG_DATA__CREDIT_RETURN_ADDR_MASK 0x0001FFFFL
-#define IH_CLIENT_CFG_DATA__CLIENT_TYPE_MASK 0x000C0000L
-#define IH_CLIENT_CFG_DATA__RING_ID_MASK 0x00300000L
-#define IH_CLIENT_CFG_DATA__VF_RB_SELECT_MASK 0x00C00000L
-#define IH_CLIENT_CFG_DATA__OVERWRITE_RING_ID_WITH_ACTIVE_FCN_ID_MASK 0x01000000L
-//IH_CID_REMAP_INDEX
-#define IH_CID_REMAP_INDEX__INDEX__SHIFT 0x0
-#define IH_CID_REMAP_INDEX__INDEX_MASK 0x00000003L
-//IH_CID_REMAP_DATA
-#define IH_CID_REMAP_DATA__CLIENT_ID__SHIFT 0x0
-#define IH_CID_REMAP_DATA__INITIATOR_ID__SHIFT 0x8
-#define IH_CID_REMAP_DATA__CLIENT_ID_REMAP__SHIFT 0x10
-#define IH_CID_REMAP_DATA__CLIENT_ID_MASK 0x000000FFL
-#define IH_CID_REMAP_DATA__INITIATOR_ID_MASK 0x0000FF00L
-#define IH_CID_REMAP_DATA__CLIENT_ID_REMAP_MASK 0x00FF0000L
-//IH_CHICKEN
-#define IH_CHICKEN__ACTIVE_FCN_ID_PROT_ENABLE__SHIFT 0x0
-#define IH_CHICKEN__ACTIVE_FCN_ID_PROT_ENABLE_MASK 0x00000001L
-//IH_MMHUB_CNTL
-#define IH_MMHUB_CNTL__UNITID__SHIFT 0x0
-#define IH_MMHUB_CNTL__IV_TLVL__SHIFT 0x8
-#define IH_MMHUB_CNTL__WPTR_WB_TLVL__SHIFT 0xc
-#define IH_MMHUB_CNTL__UNITID_MASK 0x0000003FL
-#define IH_MMHUB_CNTL__IV_TLVL_MASK 0x00000700L
-#define IH_MMHUB_CNTL__WPTR_WB_TLVL_MASK 0x00007000L
-//IH_INT_DROP_CNTL
-#define IH_INT_DROP_CNTL__INT_DROP_EN__SHIFT 0x0
-#define IH_INT_DROP_CNTL__CLIENT_ID_MATCH_EN__SHIFT 0x1
-#define IH_INT_DROP_CNTL__SOURCE_ID_MATCH_EN__SHIFT 0x2
-#define IH_INT_DROP_CNTL__VF_ID_MATCH_EN__SHIFT 0x3
-#define IH_INT_DROP_CNTL__VF_MATCH_EN__SHIFT 0x4
-#define IH_INT_DROP_CNTL__CONTEXT_ID_MATCH_EN__SHIFT 0x5
-#define IH_INT_DROP_CNTL__INT_DROP_MODE__SHIFT 0x6
-#define IH_INT_DROP_CNTL__UTCL2_RETRY_INT_DROP_EN__SHIFT 0x8
-#define IH_INT_DROP_CNTL__INT_DROPPED__SHIFT 0x10
-#define IH_INT_DROP_CNTL__INT_DROP_EN_MASK 0x00000001L
-#define IH_INT_DROP_CNTL__CLIENT_ID_MATCH_EN_MASK 0x00000002L
-#define IH_INT_DROP_CNTL__SOURCE_ID_MATCH_EN_MASK 0x00000004L
-#define IH_INT_DROP_CNTL__VF_ID_MATCH_EN_MASK 0x00000008L
-#define IH_INT_DROP_CNTL__VF_MATCH_EN_MASK 0x00000010L
-#define IH_INT_DROP_CNTL__CONTEXT_ID_MATCH_EN_MASK 0x00000020L
-#define IH_INT_DROP_CNTL__INT_DROP_MODE_MASK 0x000000C0L
-#define IH_INT_DROP_CNTL__UTCL2_RETRY_INT_DROP_EN_MASK 0x00000100L
-#define IH_INT_DROP_CNTL__INT_DROPPED_MASK 0x00010000L
-//IH_INT_DROP_MATCH_VALUE0
-#define IH_INT_DROP_MATCH_VALUE0__CLIENT_ID_MATCH_VALUE__SHIFT 0x0
-#define IH_INT_DROP_MATCH_VALUE0__SOURCE_ID_MATCH_VALUE__SHIFT 0x8
-#define IH_INT_DROP_MATCH_VALUE0__VF_ID_MATCH_VALUE__SHIFT 0x10
-#define IH_INT_DROP_MATCH_VALUE0__VF_MATCH_VALUE__SHIFT 0x17
-#define IH_INT_DROP_MATCH_VALUE0__CONTEXT_ID_39_32_MATCH_VALUE__SHIFT 0x18
-#define IH_INT_DROP_MATCH_VALUE0__CLIENT_ID_MATCH_VALUE_MASK 0x000000FFL
-#define IH_INT_DROP_MATCH_VALUE0__SOURCE_ID_MATCH_VALUE_MASK 0x0000FF00L
-#define IH_INT_DROP_MATCH_VALUE0__VF_ID_MATCH_VALUE_MASK 0x000F0000L
-#define IH_INT_DROP_MATCH_VALUE0__VF_MATCH_VALUE_MASK 0x00800000L
-#define IH_INT_DROP_MATCH_VALUE0__CONTEXT_ID_39_32_MATCH_VALUE_MASK 0xFF000000L
-//IH_INT_DROP_MATCH_VALUE1
-#define IH_INT_DROP_MATCH_VALUE1__CONTEXT_ID_31_0_MATCH_VALUE__SHIFT 0x0
-#define IH_INT_DROP_MATCH_VALUE1__CONTEXT_ID_31_0_MATCH_VALUE_MASK 0xFFFFFFFFL
-//IH_INT_DROP_MATCH_MASK0
-#define IH_INT_DROP_MATCH_MASK0__CLIENT_ID_MATCH_MASK__SHIFT 0x0
-#define IH_INT_DROP_MATCH_MASK0__SOURCE_ID_MATCH_MASK__SHIFT 0x8
-#define IH_INT_DROP_MATCH_MASK0__VF_ID_MATCH_MASK__SHIFT 0x10
-#define IH_INT_DROP_MATCH_MASK0__VF_MATCH_MASK__SHIFT 0x17
-#define IH_INT_DROP_MATCH_MASK0__CONTEXT_ID_39_32_MATCH_MASK__SHIFT 0x18
-#define IH_INT_DROP_MATCH_MASK0__CLIENT_ID_MATCH_MASK_MASK 0x000000FFL
-#define IH_INT_DROP_MATCH_MASK0__SOURCE_ID_MATCH_MASK_MASK 0x0000FF00L
-#define IH_INT_DROP_MATCH_MASK0__VF_ID_MATCH_MASK_MASK 0x000F0000L
-#define IH_INT_DROP_MATCH_MASK0__VF_MATCH_MASK_MASK 0x00800000L
-#define IH_INT_DROP_MATCH_MASK0__CONTEXT_ID_39_32_MATCH_MASK_MASK 0xFF000000L
-//IH_INT_DROP_MATCH_MASK1
-#define IH_INT_DROP_MATCH_MASK1__CONTEXT_ID_31_0_MATCH_MASK__SHIFT 0x0
-#define IH_INT_DROP_MATCH_MASK1__CONTEXT_ID_31_0_MATCH_MASK_MASK 0xFFFFFFFFL
-//IH_REGISTER_LAST_PART1
-#define IH_REGISTER_LAST_PART1__RESERVED__SHIFT 0x0
-#define IH_REGISTER_LAST_PART1__RESERVED_MASK 0xFFFFFFFFL
-//SEM_ACTIVE_FCN_ID
-#define SEM_ACTIVE_FCN_ID__VFID__SHIFT 0x0
-#define SEM_ACTIVE_FCN_ID__VF__SHIFT 0x1f
-#define SEM_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
-#define SEM_ACTIVE_FCN_ID__VF_MASK 0x80000000L
-//SEM_VIRT_RESET_REQ
-#define SEM_VIRT_RESET_REQ__VF__SHIFT 0x0
-#define SEM_VIRT_RESET_REQ__PF__SHIFT 0x1f
-#define SEM_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL
-#define SEM_VIRT_RESET_REQ__PF_MASK 0x80000000L
-//SEM_RESP_SDMA0
-#define SEM_RESP_SDMA0__ADDR__SHIFT 0x2
-#define SEM_RESP_SDMA0__ADDR_MASK 0x000FFFFCL
-//SEM_RESP_SDMA1
-#define SEM_RESP_SDMA1__ADDR__SHIFT 0x2
-#define SEM_RESP_SDMA1__ADDR_MASK 0x000FFFFCL
-//SEM_RESP_UVD
-#define SEM_RESP_UVD__ADDR__SHIFT 0x2
-#define SEM_RESP_UVD__ADDR_MASK 0x000FFFFCL
-//SEM_RESP_VCE_0
-#define SEM_RESP_VCE_0__ADDR__SHIFT 0x2
-#define SEM_RESP_VCE_0__ADDR_MASK 0x000FFFFCL
-//SEM_RESP_ACP
-#define SEM_RESP_ACP__ADDR__SHIFT 0x2
-#define SEM_RESP_ACP__ADDR_MASK 0x000FFFFCL
-//SEM_RESP_ISP
-#define SEM_RESP_ISP__ADDR__SHIFT 0x2
-#define SEM_RESP_ISP__ADDR_MASK 0x000FFFFCL
-//SEM_RESP_VCE_1
-#define SEM_RESP_VCE_1__ADDR__SHIFT 0x2
-#define SEM_RESP_VCE_1__ADDR_MASK 0x000FFFFCL
-//SEM_RESP_VP8
-#define SEM_RESP_VP8__ADDR__SHIFT 0x2
-#define SEM_RESP_VP8__ADDR_MASK 0x000FFFFCL
-//SEM_RESP_GC
-#define SEM_RESP_GC__ADDR__SHIFT 0x2
-#define SEM_RESP_GC__ADDR_MASK 0x000FFFFCL
-//SEM_CID_REMAP_INDEX
-#define SEM_CID_REMAP_INDEX__INDEX__SHIFT 0x0
-#define SEM_CID_REMAP_INDEX__INDEX_MASK 0x00000003L
-//SEM_CID_REMAP_DATA
-#define SEM_CID_REMAP_DATA__CLIENT_ID__SHIFT 0x0
-#define SEM_CID_REMAP_DATA__INITIATOR_ID__SHIFT 0x8
-#define SEM_CID_REMAP_DATA__CLIENT_ID_REMAP__SHIFT 0x10
-#define SEM_CID_REMAP_DATA__CLIENT_ID_MASK 0x000000FFL
-#define SEM_CID_REMAP_DATA__INITIATOR_ID_MASK 0x0000FF00L
-#define SEM_CID_REMAP_DATA__CLIENT_ID_REMAP_MASK 0x00FF0000L
-//SEM_ATOMIC_OP_LUT
-#define SEM_ATOMIC_OP_LUT__SIGNAL_NORMAL__SHIFT 0x0
-#define SEM_ATOMIC_OP_LUT__SIGNAL_WRITE1__SHIFT 0x7
-#define SEM_ATOMIC_OP_LUT__WAIT_NORMAL__SHIFT 0xe
-#define SEM_ATOMIC_OP_LUT__WAIT_CHECK0__SHIFT 0x15
-#define SEM_ATOMIC_OP_LUT__SIGNAL_NORMAL_MASK 0x0000007FL
-#define SEM_ATOMIC_OP_LUT__SIGNAL_WRITE1_MASK 0x00003F80L
-#define SEM_ATOMIC_OP_LUT__WAIT_NORMAL_MASK 0x001FC000L
-#define SEM_ATOMIC_OP_LUT__WAIT_CHECK0_MASK 0x0FE00000L
-//SEM_EDC_CONFIG
-#define SEM_EDC_CONFIG__DIS_EDC__SHIFT 0x1
-#define SEM_EDC_CONFIG__DIS_EDC_MASK 0x00000002L
-//SEM_CHICKEN_BITS2
-#define SEM_CHICKEN_BITS2__ACTIVE_FCN_ID_PROT_ENABLE__SHIFT 0x0
-#define SEM_CHICKEN_BITS2__MM_CLIENT_USE_CONFIG_VFID__SHIFT 0x1
-#define SEM_CHICKEN_BITS2__ACTIVE_FCN_ID_PROT_ENABLE_MASK 0x00000001L
-#define SEM_CHICKEN_BITS2__MM_CLIENT_USE_CONFIG_VFID_MASK 0x00000002L
-//SEM_MMHUB_CNTL
-#define SEM_MMHUB_CNTL__UNIT_ID__SHIFT 0x0
-#define SEM_MMHUB_CNTL__TLVL_VALUE__SHIFT 0x8
-#define SEM_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL
-#define SEM_MMHUB_CNTL__TLVL_VALUE_MASK 0x00000700L
-//SEM_REGISTER_LAST_PART1
-#define SEM_REGISTER_LAST_PART1__RESERVED__SHIFT 0x0
-#define SEM_REGISTER_LAST_PART1__RESERVED_MASK 0xFFFFFFFFL
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_default.h
deleted file mode 100644
index 4be3cb5c4..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_default.h
+++ /dev/null
@@ -1,286 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _sdma0_4_0_DEFAULT_HEADER
-#define _sdma0_4_0_DEFAULT_HEADER
-
-
-// addressBlock: sdma0_sdma0dec
-#define mmSDMA0_UCODE_ADDR_DEFAULT 0x00000000
-#define mmSDMA0_UCODE_DATA_DEFAULT 0x00000000
-#define mmSDMA0_VM_CNTL_DEFAULT 0x00000000
-#define mmSDMA0_VM_CTX_LO_DEFAULT 0x00000000
-#define mmSDMA0_VM_CTX_HI_DEFAULT 0x00000000
-#define mmSDMA0_ACTIVE_FCN_ID_DEFAULT 0x00000000
-#define mmSDMA0_VM_CTX_CNTL_DEFAULT 0x00000000
-#define mmSDMA0_VIRT_RESET_REQ_DEFAULT 0x00000000
-#define mmSDMA0_VF_ENABLE_DEFAULT 0x00000000
-#define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
-#define mmSDMA0_CONTEXT_REG_TYPE1_DEFAULT 0x003fbcff
-#define mmSDMA0_CONTEXT_REG_TYPE2_DEFAULT 0x000003ff
-#define mmSDMA0_CONTEXT_REG_TYPE3_DEFAULT 0x00000000
-#define mmSDMA0_PUB_REG_TYPE0_DEFAULT 0x3c000000
-#define mmSDMA0_PUB_REG_TYPE1_DEFAULT 0x30003882
-#define mmSDMA0_PUB_REG_TYPE2_DEFAULT 0x0fc6e880
-#define mmSDMA0_PUB_REG_TYPE3_DEFAULT 0x00000000
-#define mmSDMA0_MMHUB_CNTL_DEFAULT 0x00000000
-#define mmSDMA0_CONTEXT_GROUP_BOUNDARY_DEFAULT 0x00000000
-#define mmSDMA0_POWER_CNTL_DEFAULT 0x0003c000
-#define mmSDMA0_CLK_CTRL_DEFAULT 0xff000100
-#define mmSDMA0_CNTL_DEFAULT 0x00000002
-#define mmSDMA0_CHICKEN_BITS_DEFAULT 0x00831f07
-#define mmSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00100012
-#define mmSDMA0_GB_ADDR_CONFIG_READ_DEFAULT 0x00100012
-#define mmSDMA0_RB_RPTR_FETCH_HI_DEFAULT 0x00000000
-#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_DEFAULT 0x00000000
-#define mmSDMA0_RB_RPTR_FETCH_DEFAULT 0x00000000
-#define mmSDMA0_IB_OFFSET_FETCH_DEFAULT 0x00000000
-#define mmSDMA0_PROGRAM_DEFAULT 0x00000000
-#define mmSDMA0_STATUS_REG_DEFAULT 0x46dee557
-#define mmSDMA0_STATUS1_REG_DEFAULT 0x000003ff
-#define mmSDMA0_RD_BURST_CNTL_DEFAULT 0x00000003
-#define mmSDMA0_HBM_PAGE_CONFIG_DEFAULT 0x00000000
-#define mmSDMA0_UCODE_CHECKSUM_DEFAULT 0x00000000
-#define mmSDMA0_F32_CNTL_DEFAULT 0x00000001
-#define mmSDMA0_FREEZE_DEFAULT 0x00000000
-#define mmSDMA0_PHASE0_QUANTUM_DEFAULT 0x00010002
-#define mmSDMA0_PHASE1_QUANTUM_DEFAULT 0x00010002
-#define mmSDMA_POWER_GATING_DEFAULT 0x00000000
-#define mmSDMA_PGFSM_CONFIG_DEFAULT 0x00000000
-#define mmSDMA_PGFSM_WRITE_DEFAULT 0x00000000
-#define mmSDMA_PGFSM_READ_DEFAULT 0x00000000
-#define mmSDMA0_EDC_CONFIG_DEFAULT 0x00000002
-#define mmSDMA0_BA_THRESHOLD_DEFAULT 0x03ff03ff
-#define mmSDMA0_ID_DEFAULT 0x00000001
-#define mmSDMA0_VERSION_DEFAULT 0x00000400
-#define mmSDMA0_EDC_COUNTER_DEFAULT 0x00000000
-#define mmSDMA0_EDC_COUNTER_CLEAR_DEFAULT 0x00000000
-#define mmSDMA0_STATUS2_REG_DEFAULT 0x00000000
-#define mmSDMA0_ATOMIC_CNTL_DEFAULT 0x00000200
-#define mmSDMA0_ATOMIC_PREOP_LO_DEFAULT 0x00000000
-#define mmSDMA0_ATOMIC_PREOP_HI_DEFAULT 0x00000000
-#define mmSDMA0_UTCL1_CNTL_DEFAULT 0xd0003019
-#define mmSDMA0_UTCL1_WATERMK_DEFAULT 0xfffbe1fe
-#define mmSDMA0_UTCL1_RD_STATUS_DEFAULT 0x201001ff
-#define mmSDMA0_UTCL1_WR_STATUS_DEFAULT 0x503001ff
-#define mmSDMA0_UTCL1_INV0_DEFAULT 0x00000600
-#define mmSDMA0_UTCL1_INV1_DEFAULT 0x00000000
-#define mmSDMA0_UTCL1_INV2_DEFAULT 0x00000000
-#define mmSDMA0_UTCL1_RD_XNACK0_DEFAULT 0x00000000
-#define mmSDMA0_UTCL1_RD_XNACK1_DEFAULT 0x00000000
-#define mmSDMA0_UTCL1_WR_XNACK0_DEFAULT 0x00000000
-#define mmSDMA0_UTCL1_WR_XNACK1_DEFAULT 0x00000000
-#define mmSDMA0_UTCL1_TIMEOUT_DEFAULT 0x00010001
-#define mmSDMA0_UTCL1_PAGE_DEFAULT 0x000003e0
-#define mmSDMA0_POWER_CNTL_IDLE_DEFAULT 0x06060200
-#define mmSDMA0_RELAX_ORDERING_LUT_DEFAULT 0xc0000006
-#define mmSDMA0_CHICKEN_BITS_2_DEFAULT 0x00000005
-#define mmSDMA0_STATUS3_REG_DEFAULT 0x00100000
-#define mmSDMA0_PHYSICAL_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA0_PHYSICAL_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA0_PHASE2_QUANTUM_DEFAULT 0x00010002
-#define mmSDMA0_ERROR_LOG_DEFAULT 0x0000000f
-#define mmSDMA0_PUB_DUMMY_REG0_DEFAULT 0x00000000
-#define mmSDMA0_PUB_DUMMY_REG1_DEFAULT 0x00000000
-#define mmSDMA0_PUB_DUMMY_REG2_DEFAULT 0x00000000
-#define mmSDMA0_PUB_DUMMY_REG3_DEFAULT 0x00000000
-#define mmSDMA0_F32_COUNTER_DEFAULT 0x00000000
-#define mmSDMA0_UNBREAKABLE_DEFAULT 0x00000000
-#define mmSDMA0_PERFMON_CNTL_DEFAULT 0x000ff7fd
-#define mmSDMA0_PERFCOUNTER0_RESULT_DEFAULT 0x00000000
-#define mmSDMA0_PERFCOUNTER1_RESULT_DEFAULT 0x00000000
-#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_DEFAULT 0x00640000
-#define mmSDMA0_CRD_CNTL_DEFAULT 0x000085c0
-#define mmSDMA0_MMHUB_TRUSTLVL_DEFAULT 0x00000000
-#define mmSDMA0_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000
-#define mmSDMA0_ULV_CNTL_DEFAULT 0x00000000
-#define mmSDMA0_EA_DBIT_ADDR_DATA_DEFAULT 0x00000000
-#define mmSDMA0_EA_DBIT_ADDR_INDEX_DEFAULT 0x00000000
-#define mmSDMA0_GFX_RB_CNTL_DEFAULT 0x00040000
-#define mmSDMA0_GFX_RB_BASE_DEFAULT 0x00000000
-#define mmSDMA0_GFX_RB_BASE_HI_DEFAULT 0x00000000
-#define mmSDMA0_GFX_RB_RPTR_DEFAULT 0x00000000
-#define mmSDMA0_GFX_RB_RPTR_HI_DEFAULT 0x00000000
-#define mmSDMA0_GFX_RB_WPTR_DEFAULT 0x00000000
-#define mmSDMA0_GFX_RB_WPTR_HI_DEFAULT 0x00000000
-#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
-#define mmSDMA0_GFX_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA0_GFX_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA0_GFX_IB_CNTL_DEFAULT 0x00000100
-#define mmSDMA0_GFX_IB_RPTR_DEFAULT 0x00000000
-#define mmSDMA0_GFX_IB_OFFSET_DEFAULT 0x00000000
-#define mmSDMA0_GFX_IB_BASE_LO_DEFAULT 0x00000000
-#define mmSDMA0_GFX_IB_BASE_HI_DEFAULT 0x00000000
-#define mmSDMA0_GFX_IB_SIZE_DEFAULT 0x00000000
-#define mmSDMA0_GFX_SKIP_CNTL_DEFAULT 0x00000000
-#define mmSDMA0_GFX_CONTEXT_STATUS_DEFAULT 0x00000005
-#define mmSDMA0_GFX_DOORBELL_DEFAULT 0x00000000
-#define mmSDMA0_GFX_CONTEXT_CNTL_DEFAULT 0x00000000
-#define mmSDMA0_GFX_STATUS_DEFAULT 0x00000000
-#define mmSDMA0_GFX_DOORBELL_LOG_DEFAULT 0x00000000
-#define mmSDMA0_GFX_WATERMARK_DEFAULT 0x00000000
-#define mmSDMA0_GFX_DOORBELL_OFFSET_DEFAULT 0x00000000
-#define mmSDMA0_GFX_CSA_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA0_GFX_CSA_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA0_GFX_IB_SUB_REMAIN_DEFAULT 0x00000000
-#define mmSDMA0_GFX_PREEMPT_DEFAULT 0x00000000
-#define mmSDMA0_GFX_DUMMY_REG_DEFAULT 0x0000000f
-#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA0_GFX_RB_AQL_CNTL_DEFAULT 0x00004000
-#define mmSDMA0_GFX_MINOR_PTR_UPDATE_DEFAULT 0x00000000
-#define mmSDMA0_GFX_MIDCMD_DATA0_DEFAULT 0x00000000
-#define mmSDMA0_GFX_MIDCMD_DATA1_DEFAULT 0x00000000
-#define mmSDMA0_GFX_MIDCMD_DATA2_DEFAULT 0x00000000
-#define mmSDMA0_GFX_MIDCMD_DATA3_DEFAULT 0x00000000
-#define mmSDMA0_GFX_MIDCMD_DATA4_DEFAULT 0x00000000
-#define mmSDMA0_GFX_MIDCMD_DATA5_DEFAULT 0x00000000
-#define mmSDMA0_GFX_MIDCMD_DATA6_DEFAULT 0x00000000
-#define mmSDMA0_GFX_MIDCMD_DATA7_DEFAULT 0x00000000
-#define mmSDMA0_GFX_MIDCMD_DATA8_DEFAULT 0x00000000
-#define mmSDMA0_GFX_MIDCMD_CNTL_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_RB_CNTL_DEFAULT 0x00040000
-#define mmSDMA0_PAGE_RB_BASE_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_RB_BASE_HI_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_RB_RPTR_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_RB_RPTR_HI_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_RB_WPTR_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_RB_WPTR_HI_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
-#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_IB_CNTL_DEFAULT 0x00000100
-#define mmSDMA0_PAGE_IB_RPTR_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_IB_OFFSET_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_IB_BASE_LO_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_IB_BASE_HI_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_IB_SIZE_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_SKIP_CNTL_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_CONTEXT_STATUS_DEFAULT 0x00000004
-#define mmSDMA0_PAGE_DOORBELL_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_STATUS_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_DOORBELL_LOG_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_WATERMARK_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_DOORBELL_OFFSET_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_CSA_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_CSA_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_IB_SUB_REMAIN_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_PREEMPT_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_DUMMY_REG_DEFAULT 0x0000000f
-#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_RB_AQL_CNTL_DEFAULT 0x00004000
-#define mmSDMA0_PAGE_MINOR_PTR_UPDATE_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_MIDCMD_DATA0_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_MIDCMD_DATA1_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_MIDCMD_DATA2_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_MIDCMD_DATA3_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_MIDCMD_DATA4_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_MIDCMD_DATA5_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_MIDCMD_DATA6_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_MIDCMD_DATA7_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_MIDCMD_DATA8_DEFAULT 0x00000000
-#define mmSDMA0_PAGE_MIDCMD_CNTL_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_RB_CNTL_DEFAULT 0x00040000
-#define mmSDMA0_RLC0_RB_BASE_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_RB_BASE_HI_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_RB_RPTR_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_RB_RPTR_HI_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_RB_WPTR_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_RB_WPTR_HI_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
-#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_IB_CNTL_DEFAULT 0x00000100
-#define mmSDMA0_RLC0_IB_RPTR_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_IB_OFFSET_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_IB_BASE_LO_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_IB_BASE_HI_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_IB_SIZE_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_SKIP_CNTL_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_CONTEXT_STATUS_DEFAULT 0x00000004
-#define mmSDMA0_RLC0_DOORBELL_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_STATUS_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_DOORBELL_LOG_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_WATERMARK_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_DOORBELL_OFFSET_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_CSA_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_CSA_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_IB_SUB_REMAIN_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_PREEMPT_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_DUMMY_REG_DEFAULT 0x0000000f
-#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_RB_AQL_CNTL_DEFAULT 0x00004000
-#define mmSDMA0_RLC0_MINOR_PTR_UPDATE_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_MIDCMD_DATA0_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_MIDCMD_DATA1_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_MIDCMD_DATA2_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_MIDCMD_DATA3_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_MIDCMD_DATA4_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_MIDCMD_DATA5_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_MIDCMD_DATA6_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_MIDCMD_DATA7_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_MIDCMD_DATA8_DEFAULT 0x00000000
-#define mmSDMA0_RLC0_MIDCMD_CNTL_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_RB_CNTL_DEFAULT 0x00040000
-#define mmSDMA0_RLC1_RB_BASE_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_RB_BASE_HI_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_RB_RPTR_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_RB_RPTR_HI_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_RB_WPTR_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_RB_WPTR_HI_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
-#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_IB_CNTL_DEFAULT 0x00000100
-#define mmSDMA0_RLC1_IB_RPTR_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_IB_OFFSET_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_IB_BASE_LO_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_IB_BASE_HI_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_IB_SIZE_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_SKIP_CNTL_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_CONTEXT_STATUS_DEFAULT 0x00000004
-#define mmSDMA0_RLC1_DOORBELL_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_STATUS_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_DOORBELL_LOG_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_WATERMARK_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_DOORBELL_OFFSET_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_CSA_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_CSA_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_IB_SUB_REMAIN_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_PREEMPT_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_DUMMY_REG_DEFAULT 0x0000000f
-#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_RB_AQL_CNTL_DEFAULT 0x00004000
-#define mmSDMA0_RLC1_MINOR_PTR_UPDATE_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_MIDCMD_DATA0_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_MIDCMD_DATA1_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_MIDCMD_DATA2_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_MIDCMD_DATA3_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_MIDCMD_DATA4_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_MIDCMD_DATA5_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_MIDCMD_DATA6_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_MIDCMD_DATA7_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_MIDCMD_DATA8_DEFAULT 0x00000000
-#define mmSDMA0_RLC1_MIDCMD_CNTL_DEFAULT 0x00000000
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h
deleted file mode 100644
index 1445bba8f..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h
+++ /dev/null
@@ -1,1658 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _sdma0_4_1_SH_MASK_HEADER
-#define _sdma0_4_1_SH_MASK_HEADER
-
-
-// addressBlock: sdma0_sdma0dec
-//SDMA0_UCODE_ADDR
-#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0
-#define SDMA0_UCODE_ADDR__VALUE_MASK 0x00001FFFL
-//SDMA0_UCODE_DATA
-#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0
-#define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL
-//SDMA0_VM_CNTL
-#define SDMA0_VM_CNTL__CMD__SHIFT 0x0
-#define SDMA0_VM_CNTL__CMD_MASK 0x0000000FL
-//SDMA0_VM_CTX_LO
-#define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2
-#define SDMA0_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA0_VM_CTX_HI
-#define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0
-#define SDMA0_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_ACTIVE_FCN_ID
-#define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0
-#define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4
-#define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f
-#define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
-#define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L
-#define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000L
-//SDMA0_VM_CTX_CNTL
-#define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0
-#define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4
-#define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x00000001L
-#define SDMA0_VM_CTX_CNTL__VMID_MASK 0x000000F0L
-//SDMA0_VIRT_RESET_REQ
-#define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0
-#define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f
-#define SDMA0_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL
-#define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000L
-//SDMA0_CONTEXT_REG_TYPE0
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT 0x4
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x5
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT 0x6
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x00000001L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x00000002L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x00000004L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x00000008L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK 0x00000010L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x00000020L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK 0x00000040L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x00000400L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x00000800L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x00001000L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x00002000L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x00004000L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x00008000L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x00010000L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x00020000L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x00040000L
-#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x00080000L
-//SDMA0_CONTEXT_REG_TYPE1
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT 0x8
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT 0xb
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd
-#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL__SHIFT 0x14
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE__SHIFT 0x15
-#define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS_MASK 0x00000100L
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x00000200L
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x00000400L
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET_MASK 0x00000800L
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x00001000L
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x00002000L
-#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x00008000L
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x00010000L
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x00020000L
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL_MASK 0x00100000L
-#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L
-#define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L
-//SDMA0_CONTEXT_REG_TYPE2
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x6
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x7
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x8
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x9
-#define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x00000001L
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x00000002L
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x00000004L
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x00000008L
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x00000010L
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x00000020L
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x00000040L
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x00000080L
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x00000100L
-#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x00000200L
-#define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L
-//SDMA0_CONTEXT_REG_TYPE3
-#define SDMA0_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0
-#define SDMA0_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL
-//SDMA0_PUB_REG_TYPE0
-#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0
-#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1
-#define SDMA0_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3
-#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL__SHIFT 0x4
-#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO__SHIFT 0x5
-#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI__SHIFT 0x6
-#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID__SHIFT 0x7
-#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL__SHIFT 0x8
-#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ__SHIFT 0x9
-#define SDMA0_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0__SHIFT 0xb
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1__SHIFT 0xc
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2__SHIFT 0xd
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3__SHIFT 0xe
-#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0__SHIFT 0xf
-#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1__SHIFT 0x10
-#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2__SHIFT 0x11
-#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3__SHIFT 0x12
-#define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL__SHIFT 0x13
-#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19
-#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x1a
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x1b
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x1c
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d
-#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG__SHIFT 0x1e
-#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ__SHIFT 0x1f
-#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x00000001L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x00000002L
-#define SDMA0_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL_MASK 0x00000010L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO_MASK 0x00000020L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI_MASK 0x00000040L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID_MASK 0x00000080L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL_MASK 0x00000100L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ_MASK 0x00000200L
-#define SDMA0_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0_MASK 0x00000800L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1_MASK 0x00001000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2_MASK 0x00002000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3_MASK 0x00004000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0_MASK 0x00008000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1_MASK 0x00010000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2_MASK 0x00020000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3_MASK 0x00040000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL_MASK 0x00080000L
-#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x04000000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x08000000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10000000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20000000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_MASK 0x40000000L
-#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ_MASK 0x80000000L
-//SDMA0_PUB_REG_TYPE1
-#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI__SHIFT 0x0
-#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1
-#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH__SHIFT 0x2
-#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH__SHIFT 0x3
-#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM__SHIFT 0x4
-#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG__SHIFT 0x5
-#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG__SHIFT 0x6
-#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL__SHIFT 0x7
-#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG__SHIFT 0x8
-#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM__SHIFT 0x9
-#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT 0xa
-#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE__SHIFT 0xb
-#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM__SHIFT 0xc
-#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM__SHIFT 0xd
-#define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe
-#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf
-#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10
-#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11
-#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG__SHIFT 0x12
-#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD__SHIFT 0x13
-#define SDMA0_PUB_REG_TYPE1__SDMA0_ID__SHIFT 0x14
-#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION__SHIFT 0x15
-#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER__SHIFT 0x16
-#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR__SHIFT 0x17
-#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x18
-#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x19
-#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x1a
-#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0x1b
-#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL__SHIFT 0x1c
-#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d
-#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS__SHIFT 0x1e
-#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT 0x1f
-#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI_MASK 0x00000001L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_MASK 0x00000004L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH_MASK 0x00000008L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM_MASK 0x00000010L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG_MASK 0x00000020L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG_MASK 0x00000040L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL_MASK 0x00000080L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG_MASK 0x00000100L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM_MASK 0x00000200L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL_MASK 0x00000400L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE_MASK 0x00000800L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM_MASK 0x00001000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM_MASK 0x00002000L
-#define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L
-#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L
-#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L
-#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG_MASK 0x00040000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD_MASK 0x00080000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_ID_MASK 0x00100000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION_MASK 0x00200000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_MASK 0x00400000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR_MASK 0x00800000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x01000000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x02000000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x04000000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x08000000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL_MASK 0x10000000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK_MASK 0x20000000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS_MASK 0x40000000L
-#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS_MASK 0x80000000L
-//SDMA0_PUB_REG_TYPE2
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0__SHIFT 0x0
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1__SHIFT 0x1
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2__SHIFT 0x2
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0__SHIFT 0x3
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1__SHIFT 0x4
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0__SHIFT 0x5
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1__SHIFT 0x6
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT__SHIFT 0x7
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE__SHIFT 0x8
-#define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE__SHIFT 0x9
-#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0xa
-#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2__SHIFT 0xb
-#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG__SHIFT 0xc
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO__SHIFT 0xd
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI__SHIFT 0xe
-#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG__SHIFT 0x10
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0__SHIFT 0x11
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1__SHIFT 0x12
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2__SHIFT 0x13
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3__SHIFT 0x14
-#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER__SHIFT 0x15
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE__SHIFT 0x16
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL__SHIFT 0x17
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x18
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x19
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a
-#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL__SHIFT 0x1b
-#define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL__SHIFT 0x1c
-#define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
-#define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL__SHIFT 0x1e
-#define SDMA0_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0_MASK 0x00000001L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1_MASK 0x00000002L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2_MASK 0x00000004L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0_MASK 0x00000008L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1_MASK 0x00000010L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0_MASK 0x00000020L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1_MASK 0x00000040L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT_MASK 0x00000080L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE_MASK 0x00000100L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE_MASK 0x00000200L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT_MASK 0x00000400L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2_MASK 0x00000800L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG_MASK 0x00001000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO_MASK 0x00002000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI_MASK 0x00004000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG_MASK 0x00010000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0_MASK 0x00020000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1_MASK 0x00040000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2_MASK 0x00080000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3_MASK 0x00100000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER_MASK 0x00200000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE_MASK 0x00400000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL_MASK 0x00800000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT_MASK 0x01000000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT_MASK 0x02000000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL_MASK 0x08000000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL_MASK 0x10000000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L
-#define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL_MASK 0x40000000L
-#define SDMA0_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L
-//SDMA0_PUB_REG_TYPE3
-#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA__SHIFT 0x0
-#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX__SHIFT 0x1
-#define SDMA0_PUB_REG_TYPE3__RESERVED__SHIFT 0x2
-#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA_MASK 0x00000001L
-#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX_MASK 0x00000002L
-#define SDMA0_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL
-//SDMA0_MMHUB_CNTL
-#define SDMA0_MMHUB_CNTL__UNIT_ID__SHIFT 0x0
-#define SDMA0_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL
-//SDMA0_CONTEXT_GROUP_BOUNDARY
-#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0
-#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL
-//SDMA0_POWER_CNTL
-#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0
-#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1
-#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2
-#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3
-#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
-#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9
-#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
-#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb
-#define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc
-#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a
-#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L
-#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L
-#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L
-#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L
-#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L
-#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L
-#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L
-#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L
-#define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L
-#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
-//SDMA0_CLK_CTRL
-#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0
-#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
-#define SDMA0_CLK_CTRL__RESERVED__SHIFT 0xc
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
-#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
-#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
-#define SDMA0_CLK_CTRL__RESERVED_MASK 0x00FFF000L
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
-#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
-//SDMA0_CNTL
-#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0
-#define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1
-#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
-#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
-#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
-#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5
-#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11
-#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
-#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
-#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
-#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e
-#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L
-#define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L
-#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L
-#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L
-#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L
-#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L
-#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L
-#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L
-#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L
-#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L
-#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L
-//SDMA0_CHICKEN_BITS
-#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
-#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
-#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
-#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8
-#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
-#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
-#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11
-#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
-#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
-#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19
-#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a
-#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c
-#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e
-#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L
-#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L
-#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L
-#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L
-#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L
-#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L
-#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L
-#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L
-#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L
-#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L
-#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L
-#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L
-#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L
-//SDMA0_GB_ADDR_CONFIG
-#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
-#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
-#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
-#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
-#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
-#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
-#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
-#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
-#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
-#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
-//SDMA0_GB_ADDR_CONFIG_READ
-#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0
-#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
-#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8
-#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc
-#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13
-#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L
-#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
-#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
-#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L
-#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L
-//SDMA0_RB_RPTR_FETCH_HI
-#define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0
-#define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_SEM_WAIT_FAIL_TIMER_CNTL
-#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
-#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL
-//SDMA0_RB_RPTR_FETCH
-#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
-#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL
-//SDMA0_IB_OFFSET_FETCH
-#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
-#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL
-//SDMA0_PROGRAM
-#define SDMA0_PROGRAM__STREAM__SHIFT 0x0
-#define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL
-//SDMA0_STATUS_REG
-#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0
-#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1
-#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2
-#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3
-#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
-#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
-#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
-#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
-#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
-#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9
-#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa
-#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
-#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc
-#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
-#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe
-#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
-#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10
-#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
-#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
-#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
-#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14
-#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
-#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
-#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
-#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a
-#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
-#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
-#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e
-#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
-#define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L
-#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L
-#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L
-#define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L
-#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L
-#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L
-#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L
-#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L
-#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L
-#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L
-#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L
-#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L
-#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L
-#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L
-#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L
-#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L
-#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L
-#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L
-#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L
-#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L
-#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L
-#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L
-#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L
-#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L
-#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L
-#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L
-#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L
-#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L
-#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L
-//SDMA0_STATUS1_REG
-#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
-#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
-#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
-#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
-#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
-#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
-#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
-#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9
-#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
-#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
-#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
-#define SDMA0_STATUS1_REG__EX_START__SHIFT 0xf
-#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
-#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
-#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L
-#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L
-#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L
-#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L
-#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L
-#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L
-#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L
-#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L
-#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L
-#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L
-#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L
-#define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L
-#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L
-#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L
-//SDMA0_RD_BURST_CNTL
-#define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0
-#define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L
-//SDMA0_HBM_PAGE_CONFIG
-#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0
-#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L
-//SDMA0_UCODE_CHECKSUM
-#define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0
-#define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL
-//SDMA0_F32_CNTL
-#define SDMA0_F32_CNTL__HALT__SHIFT 0x0
-#define SDMA0_F32_CNTL__STEP__SHIFT 0x1
-#define SDMA0_F32_CNTL__HALT_MASK 0x00000001L
-#define SDMA0_F32_CNTL__STEP_MASK 0x00000002L
-//SDMA0_FREEZE
-#define SDMA0_FREEZE__PREEMPT__SHIFT 0x0
-#define SDMA0_FREEZE__FREEZE__SHIFT 0x4
-#define SDMA0_FREEZE__FROZEN__SHIFT 0x5
-#define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6
-#define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L
-#define SDMA0_FREEZE__FREEZE_MASK 0x00000010L
-#define SDMA0_FREEZE__FROZEN_MASK 0x00000020L
-#define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L
-//SDMA0_PHASE0_QUANTUM
-#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0
-#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8
-#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
-#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL
-#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L
-#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L
-//SDMA0_PHASE1_QUANTUM
-#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0
-#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8
-#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
-#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL
-#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L
-#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L
-//SDMA_POWER_GATING
-#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT 0x0
-#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT 0x1
-#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT 0x2
-#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT 0x3
-#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4
-#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK 0x00000001L
-#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK 0x00000002L
-#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK 0x00000004L
-#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK 0x00000008L
-#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L
-//SDMA_PGFSM_CONFIG
-#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0
-#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8
-#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9
-#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
-#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb
-#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc
-#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd
-#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b
-#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c
-#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL
-#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L
-#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L
-#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L
-#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L
-#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L
-#define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L
-#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L
-#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L
-//SDMA_PGFSM_WRITE
-#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0
-#define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL
-//SDMA_PGFSM_READ
-#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0
-#define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL
-//SDMA0_EDC_CONFIG
-#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1
-#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
-#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L
-#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L
-//SDMA0_BA_THRESHOLD
-#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0
-#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10
-#define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL
-#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L
-//SDMA0_ID
-#define SDMA0_ID__DEVICE_ID__SHIFT 0x0
-#define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL
-//SDMA0_VERSION
-#define SDMA0_VERSION__MINVER__SHIFT 0x0
-#define SDMA0_VERSION__MAJVER__SHIFT 0x8
-#define SDMA0_VERSION__REV__SHIFT 0x10
-#define SDMA0_VERSION__MINVER_MASK 0x0000007FL
-#define SDMA0_VERSION__MAJVER_MASK 0x00007F00L
-#define SDMA0_VERSION__REV_MASK 0x003F0000L
-//SDMA0_EDC_COUNTER
-#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0
-#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1
-#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2
-#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3
-#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4
-#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5
-#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe
-#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf
-#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10
-#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L
-#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L
-#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L
-#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L
-#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L
-#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L
-#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L
-#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L
-#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L
-#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L
-//SDMA0_EDC_COUNTER_CLEAR
-#define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0
-#define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L
-//SDMA0_STATUS2_REG
-#define SDMA0_STATUS2_REG__ID__SHIFT 0x0
-#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2
-#define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10
-#define SDMA0_STATUS2_REG__ID_MASK 0x00000003L
-#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL
-#define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L
-//SDMA0_ATOMIC_CNTL
-#define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0
-#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f
-#define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL
-#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L
-//SDMA0_ATOMIC_PREOP_LO
-#define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0
-#define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL
-//SDMA0_ATOMIC_PREOP_HI
-#define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0
-#define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL
-//SDMA0_UTCL1_CNTL
-#define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0
-#define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1
-#define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb
-#define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe
-#define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18
-#define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
-#define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L
-#define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL
-#define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L
-#define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L
-#define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L
-#define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L
-//SDMA0_UTCL1_WATERMK
-#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0
-#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa
-#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12
-#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a
-#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL
-#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L
-#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L
-#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L
-//SDMA0_UTCL1_RD_STATUS
-#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
-#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
-#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
-#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
-#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
-#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
-#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
-#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
-#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
-#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
-#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
-#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
-#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
-#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
-#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
-#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
-#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
-#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
-#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12
-#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13
-#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14
-#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15
-#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16
-#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a
-#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
-#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e
-#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f
-#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
-#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L
-#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L
-#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L
-#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L
-#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L
-#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L
-#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L
-#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L
-#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L
-#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L
-#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L
-#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L
-#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L
-#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L
-#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L
-#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L
-#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L
-#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L
-#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L
-#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L
-#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L
-#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L
-#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L
-#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L
-#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L
-#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L
-//SDMA0_UTCL1_WR_STATUS
-#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
-#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
-#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
-#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
-#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
-#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
-#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
-#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
-#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
-#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
-#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
-#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
-#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
-#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
-#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
-#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
-#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
-#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
-#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12
-#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13
-#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14
-#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15
-#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16
-#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19
-#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c
-#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
-#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e
-#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f
-#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
-#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L
-#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L
-#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L
-#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L
-#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L
-#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L
-#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L
-#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L
-#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L
-#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L
-#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L
-#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L
-#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L
-#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L
-#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L
-#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L
-#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L
-#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L
-#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L
-#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L
-#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L
-#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L
-#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L
-#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L
-#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L
-#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L
-#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L
-//SDMA0_UTCL1_INV0
-#define SDMA0_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0
-#define SDMA0_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1
-#define SDMA0_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2
-#define SDMA0_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3
-#define SDMA0_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4
-#define SDMA0_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5
-#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6
-#define SDMA0_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7
-#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8
-#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9
-#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa
-#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb
-#define SDMA0_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc
-#define SDMA0_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c
-#define SDMA0_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L
-#define SDMA0_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L
-#define SDMA0_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L
-#define SDMA0_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L
-#define SDMA0_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L
-#define SDMA0_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L
-#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L
-#define SDMA0_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L
-#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L
-#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L
-#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L
-#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L
-#define SDMA0_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L
-#define SDMA0_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L
-//SDMA0_UTCL1_INV1
-#define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0
-#define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL
-//SDMA0_UTCL1_INV2
-#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0
-#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL
-//SDMA0_UTCL1_RD_XNACK0
-#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
-#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
-//SDMA0_UTCL1_RD_XNACK1
-#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
-#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4
-#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8
-#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a
-#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
-#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L
-#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
-#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L
-//SDMA0_UTCL1_WR_XNACK0
-#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
-#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
-//SDMA0_UTCL1_WR_XNACK1
-#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
-#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4
-#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8
-#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a
-#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
-#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L
-#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
-#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L
-//SDMA0_UTCL1_TIMEOUT
-#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0
-#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10
-#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL
-#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L
-//SDMA0_UTCL1_PAGE
-#define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0
-#define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1
-#define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6
-#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9
-#define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L
-#define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL
-#define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L
-#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L
-//SDMA0_POWER_CNTL_IDLE
-#define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0
-#define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10
-#define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18
-#define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL
-#define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L
-#define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L
-//SDMA0_RELAX_ORDERING_LUT
-#define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0
-#define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1
-#define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2
-#define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3
-#define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4
-#define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5
-#define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6
-#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8
-#define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9
-#define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa
-#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb
-#define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc
-#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd
-#define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe
-#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b
-#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c
-#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
-#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e
-#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f
-#define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L
-#define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L
-#define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L
-#define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L
-#define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L
-#define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L
-#define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L
-#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L
-#define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L
-#define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L
-#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L
-#define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L
-#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L
-#define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L
-#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L
-#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L
-#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L
-#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L
-#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L
-//SDMA0_CHICKEN_BITS_2
-#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0
-#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL
-//SDMA0_STATUS3_REG
-#define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0
-#define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10
-#define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14
-#define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL
-#define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L
-#define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L
-//SDMA0_PHYSICAL_ADDR_LO
-#define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0
-#define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1
-#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2
-#define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc
-#define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L
-#define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L
-#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L
-#define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L
-//SDMA0_PHYSICAL_ADDR_HI
-#define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL
-//SDMA0_ERROR_LOG
-#define SDMA0_ERROR_LOG__OVERRIDE__SHIFT 0x0
-#define SDMA0_ERROR_LOG__STATUS__SHIFT 0x10
-#define SDMA0_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL
-#define SDMA0_ERROR_LOG__STATUS_MASK 0xFFFF0000L
-//SDMA0_PUB_DUMMY_REG0
-#define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT 0x0
-#define SDMA0_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL
-//SDMA0_PUB_DUMMY_REG1
-#define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT 0x0
-#define SDMA0_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL
-//SDMA0_PUB_DUMMY_REG2
-#define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT 0x0
-#define SDMA0_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL
-//SDMA0_PUB_DUMMY_REG3
-#define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT 0x0
-#define SDMA0_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL
-//SDMA0_F32_COUNTER
-#define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0
-#define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL
-//SDMA0_UNBREAKABLE
-#define SDMA0_UNBREAKABLE__VALUE__SHIFT 0x0
-#define SDMA0_UNBREAKABLE__VALUE_MASK 0x00000001L
-//SDMA0_PERFMON_CNTL
-#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
-#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
-#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
-#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa
-#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb
-#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc
-#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L
-#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L
-#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL
-#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L
-#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L
-#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L
-//SDMA0_PERFCOUNTER0_RESULT
-#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
-#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
-//SDMA0_PERFCOUNTER1_RESULT
-#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
-#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
-//SDMA0_PERFCOUNTER_TAG_DELAY_RANGE
-#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0
-#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe
-#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c
-#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL
-#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L
-#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L
-//SDMA0_CRD_CNTL
-#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7
-#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd
-#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L
-#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L
-//SDMA0_MMHUB_TRUSTLVL
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG0__SHIFT 0x0
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG1__SHIFT 0x3
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG2__SHIFT 0x6
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG3__SHIFT 0x9
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG4__SHIFT 0xc
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG5__SHIFT 0xf
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG6__SHIFT 0x12
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG7__SHIFT 0x15
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG0_MASK 0x00000007L
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG1_MASK 0x00000038L
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG2_MASK 0x000001C0L
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG3_MASK 0x00000E00L
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG4_MASK 0x00007000L
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG5_MASK 0x00038000L
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG6_MASK 0x001C0000L
-#define SDMA0_MMHUB_TRUSTLVL__SECFLAG7_MASK 0x00E00000L
-//SDMA0_GPU_IOV_VIOLATION_LOG
-#define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0
-#define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1
-#define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2
-#define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12
-#define SDMA0_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13
-#define SDMA0_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14
-#define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18
-#define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L
-#define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L
-#define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL
-#define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L
-#define SDMA0_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L
-#define SDMA0_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L
-#define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L
-//SDMA0_ULV_CNTL
-#define SDMA0_ULV_CNTL__HYSTERESIS__SHIFT 0x0
-#define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
-#define SDMA0_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e
-#define SDMA0_ULV_CNTL__ULV_STATUS__SHIFT 0x1f
-#define SDMA0_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL
-#define SDMA0_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L
-#define SDMA0_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L
-#define SDMA0_ULV_CNTL__ULV_STATUS_MASK 0x80000000L
-//SDMA0_EA_DBIT_ADDR_DATA
-#define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0
-#define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL
-//SDMA0_EA_DBIT_ADDR_INDEX
-#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0
-#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L
-//SDMA0_GFX_RB_CNTL
-#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
-#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
-#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
-#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
-#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
-#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
-#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
-#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
-#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L
-#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000007EL
-#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
-#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
-#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
-#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
-#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L
-#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L
-//SDMA0_GFX_RB_BASE
-#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0
-#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_GFX_RB_BASE_HI
-#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
-#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
-//SDMA0_GFX_RB_RPTR
-#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x0
-#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_GFX_RB_RPTR_HI
-#define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0
-#define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_GFX_RB_WPTR
-#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x0
-#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_GFX_RB_WPTR_HI
-#define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0
-#define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_GFX_RB_WPTR_POLL_CNTL
-#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
-#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
-#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
-#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
-#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
-#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
-#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
-#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
-#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
-#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
-//SDMA0_GFX_RB_RPTR_ADDR_HI
-#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_GFX_RB_RPTR_ADDR_LO
-#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA0_GFX_IB_CNTL
-#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
-#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
-#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
-#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
-#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L
-#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
-#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
-#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L
-//SDMA0_GFX_IB_RPTR
-#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2
-#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL
-//SDMA0_GFX_IB_OFFSET
-#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
-#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
-//SDMA0_GFX_IB_BASE_LO
-#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
-#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
-//SDMA0_GFX_IB_BASE_HI
-#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
-#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_GFX_IB_SIZE
-#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0
-#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL
-//SDMA0_GFX_SKIP_CNTL
-#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
-#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL
-//SDMA0_GFX_CONTEXT_STATUS
-#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
-#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
-#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
-#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
-#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
-#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
-#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
-#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
-#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
-#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L
-#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
-#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
-#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
-#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
-#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
-#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
-//SDMA0_GFX_DOORBELL
-#define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c
-#define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e
-#define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L
-#define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L
-//SDMA0_GFX_CONTEXT_CNTL
-#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
-#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L
-//SDMA0_GFX_STATUS
-#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
-#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
-#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
-#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
-//SDMA0_GFX_DOORBELL_LOG
-#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
-#define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2
-#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
-#define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
-//SDMA0_GFX_WATERMARK
-#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
-#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
-#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
-#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
-//SDMA0_GFX_DOORBELL_OFFSET
-#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
-#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
-//SDMA0_GFX_CSA_ADDR_LO
-#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA0_GFX_CSA_ADDR_HI
-#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_GFX_IB_SUB_REMAIN
-#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0
-#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
-//SDMA0_GFX_PREEMPT
-#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0
-#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L
-//SDMA0_GFX_DUMMY_REG
-#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0
-#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
-//SDMA0_GFX_RB_WPTR_POLL_ADDR_HI
-#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_GFX_RB_WPTR_POLL_ADDR_LO
-#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA0_GFX_RB_AQL_CNTL
-#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
-#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
-#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
-#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
-#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
-#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
-//SDMA0_GFX_MINOR_PTR_UPDATE
-#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
-#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
-//SDMA0_GFX_MIDCMD_DATA0
-#define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0
-#define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
-//SDMA0_GFX_MIDCMD_DATA1
-#define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0
-#define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
-//SDMA0_GFX_MIDCMD_DATA2
-#define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0
-#define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
-//SDMA0_GFX_MIDCMD_DATA3
-#define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0
-#define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
-//SDMA0_GFX_MIDCMD_DATA4
-#define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0
-#define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
-//SDMA0_GFX_MIDCMD_DATA5
-#define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0
-#define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
-//SDMA0_GFX_MIDCMD_DATA6
-#define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0
-#define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
-//SDMA0_GFX_MIDCMD_DATA7
-#define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0
-#define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
-//SDMA0_GFX_MIDCMD_DATA8
-#define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0
-#define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
-//SDMA0_GFX_MIDCMD_CNTL
-#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
-#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
-#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
-#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
-#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
-#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
-#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
-#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
-//SDMA0_RLC0_RB_CNTL
-#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
-#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
-#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
-#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
-#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
-#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
-#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
-#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
-#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L
-#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000007EL
-#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
-#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
-#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
-#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
-#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L
-#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L
-//SDMA0_RLC0_RB_BASE
-#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0
-#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_RB_BASE_HI
-#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
-#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
-//SDMA0_RLC0_RB_RPTR
-#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x0
-#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_RB_RPTR_HI
-#define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0
-#define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_RB_WPTR
-#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x0
-#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_RB_WPTR_HI
-#define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0
-#define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_RB_WPTR_POLL_CNTL
-#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
-#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
-#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
-#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
-#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
-#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
-#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
-#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
-#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
-#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
-//SDMA0_RLC0_RB_RPTR_ADDR_HI
-#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_RB_RPTR_ADDR_LO
-#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA0_RLC0_IB_CNTL
-#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
-#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
-#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
-#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
-#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L
-#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
-#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
-#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L
-//SDMA0_RLC0_IB_RPTR
-#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
-#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL
-//SDMA0_RLC0_IB_OFFSET
-#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
-#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
-//SDMA0_RLC0_IB_BASE_LO
-#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
-#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
-//SDMA0_RLC0_IB_BASE_HI
-#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
-#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_IB_SIZE
-#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0
-#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL
-//SDMA0_RLC0_SKIP_CNTL
-#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
-#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL
-//SDMA0_RLC0_CONTEXT_STATUS
-#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
-#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
-#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
-#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
-#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
-#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
-#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
-#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
-#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
-#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L
-#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
-#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
-#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
-#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
-#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
-#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
-//SDMA0_RLC0_DOORBELL
-#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
-#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
-#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L
-#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L
-//SDMA0_RLC0_STATUS
-#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
-#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
-#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
-#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
-//SDMA0_RLC0_DOORBELL_LOG
-#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
-#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
-#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
-#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
-//SDMA0_RLC0_WATERMARK
-#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
-#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
-#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
-#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
-//SDMA0_RLC0_DOORBELL_OFFSET
-#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
-#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
-//SDMA0_RLC0_CSA_ADDR_LO
-#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA0_RLC0_CSA_ADDR_HI
-#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_IB_SUB_REMAIN
-#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0
-#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
-//SDMA0_RLC0_PREEMPT
-#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0
-#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L
-//SDMA0_RLC0_DUMMY_REG
-#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0
-#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI
-#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO
-#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA0_RLC0_RB_AQL_CNTL
-#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
-#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
-#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
-#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
-#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
-#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
-//SDMA0_RLC0_MINOR_PTR_UPDATE
-#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
-#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
-//SDMA0_RLC0_MIDCMD_DATA0
-#define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0
-#define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_MIDCMD_DATA1
-#define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0
-#define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_MIDCMD_DATA2
-#define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0
-#define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_MIDCMD_DATA3
-#define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0
-#define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_MIDCMD_DATA4
-#define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0
-#define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_MIDCMD_DATA5
-#define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0
-#define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_MIDCMD_DATA6
-#define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0
-#define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_MIDCMD_DATA7
-#define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0
-#define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_MIDCMD_DATA8
-#define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0
-#define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
-//SDMA0_RLC0_MIDCMD_CNTL
-#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
-#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
-#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
-#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
-#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
-#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
-#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
-#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
-//SDMA0_RLC1_RB_CNTL
-#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
-#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
-#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
-#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
-#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
-#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
-#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
-#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
-#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L
-#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000007EL
-#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
-#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
-#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
-#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
-#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L
-#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L
-//SDMA0_RLC1_RB_BASE
-#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0
-#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_RB_BASE_HI
-#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
-#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
-//SDMA0_RLC1_RB_RPTR
-#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x0
-#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_RB_RPTR_HI
-#define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0
-#define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_RB_WPTR
-#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x0
-#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_RB_WPTR_HI
-#define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0
-#define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_RB_WPTR_POLL_CNTL
-#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
-#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
-#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
-#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
-#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
-#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
-#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
-#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
-#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
-#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
-//SDMA0_RLC1_RB_RPTR_ADDR_HI
-#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_RB_RPTR_ADDR_LO
-#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA0_RLC1_IB_CNTL
-#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
-#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
-#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
-#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
-#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L
-#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
-#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
-#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L
-//SDMA0_RLC1_IB_RPTR
-#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
-#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL
-//SDMA0_RLC1_IB_OFFSET
-#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
-#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
-//SDMA0_RLC1_IB_BASE_LO
-#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
-#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
-//SDMA0_RLC1_IB_BASE_HI
-#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
-#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_IB_SIZE
-#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0
-#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL
-//SDMA0_RLC1_SKIP_CNTL
-#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
-#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL
-//SDMA0_RLC1_CONTEXT_STATUS
-#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
-#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
-#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
-#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
-#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
-#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
-#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
-#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
-#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
-#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L
-#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
-#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
-#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
-#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
-#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
-#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
-//SDMA0_RLC1_DOORBELL
-#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
-#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
-#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L
-#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L
-//SDMA0_RLC1_STATUS
-#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
-#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
-#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
-#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
-//SDMA0_RLC1_DOORBELL_LOG
-#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
-#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
-#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
-#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
-//SDMA0_RLC1_WATERMARK
-#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
-#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
-#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
-#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
-//SDMA0_RLC1_DOORBELL_OFFSET
-#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
-#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
-//SDMA0_RLC1_CSA_ADDR_LO
-#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA0_RLC1_CSA_ADDR_HI
-#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_IB_SUB_REMAIN
-#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0
-#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL
-//SDMA0_RLC1_PREEMPT
-#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0
-#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L
-//SDMA0_RLC1_DUMMY_REG
-#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0
-#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI
-#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
-#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO
-#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
-#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
-//SDMA0_RLC1_RB_AQL_CNTL
-#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
-#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
-#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
-#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
-#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
-#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
-//SDMA0_RLC1_MINOR_PTR_UPDATE
-#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
-#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
-//SDMA0_RLC1_MIDCMD_DATA0
-#define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0
-#define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_MIDCMD_DATA1
-#define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0
-#define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_MIDCMD_DATA2
-#define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0
-#define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_MIDCMD_DATA3
-#define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0
-#define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_MIDCMD_DATA4
-#define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0
-#define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_MIDCMD_DATA5
-#define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0
-#define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_MIDCMD_DATA6
-#define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0
-#define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_MIDCMD_DATA7
-#define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0
-#define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_MIDCMD_DATA8
-#define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0
-#define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
-//SDMA0_RLC1_MIDCMD_CNTL
-#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
-#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
-#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
-#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
-#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
-#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
-#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
-#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_default.h
deleted file mode 100644
index 934733762..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_default.h
+++ /dev/null
@@ -1,282 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _sdma1_4_0_DEFAULT_HEADER
-#define _sdma1_4_0_DEFAULT_HEADER
-
-
-// addressBlock: sdma1_sdma1dec
-#define mmSDMA1_UCODE_ADDR_DEFAULT 0x00000000
-#define mmSDMA1_UCODE_DATA_DEFAULT 0x00000000
-#define mmSDMA1_VM_CNTL_DEFAULT 0x00000000
-#define mmSDMA1_VM_CTX_LO_DEFAULT 0x00000000
-#define mmSDMA1_VM_CTX_HI_DEFAULT 0x00000000
-#define mmSDMA1_ACTIVE_FCN_ID_DEFAULT 0x00000000
-#define mmSDMA1_VM_CTX_CNTL_DEFAULT 0x00000000
-#define mmSDMA1_VIRT_RESET_REQ_DEFAULT 0x00000000
-#define mmSDMA1_VF_ENABLE_DEFAULT 0x00000000
-#define mmSDMA1_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
-#define mmSDMA1_CONTEXT_REG_TYPE1_DEFAULT 0x003fbcff
-#define mmSDMA1_CONTEXT_REG_TYPE2_DEFAULT 0x000003ff
-#define mmSDMA1_CONTEXT_REG_TYPE3_DEFAULT 0x00000000
-#define mmSDMA1_PUB_REG_TYPE0_DEFAULT 0x3c000000
-#define mmSDMA1_PUB_REG_TYPE1_DEFAULT 0x30003882
-#define mmSDMA1_PUB_REG_TYPE2_DEFAULT 0x0fc6e880
-#define mmSDMA1_PUB_REG_TYPE3_DEFAULT 0x00000000
-#define mmSDMA1_MMHUB_CNTL_DEFAULT 0x00000000
-#define mmSDMA1_CONTEXT_GROUP_BOUNDARY_DEFAULT 0x00000000
-#define mmSDMA1_POWER_CNTL_DEFAULT 0x0003c000
-#define mmSDMA1_CLK_CTRL_DEFAULT 0xff000100
-#define mmSDMA1_CNTL_DEFAULT 0x00000002
-#define mmSDMA1_CHICKEN_BITS_DEFAULT 0x00831f07
-#define mmSDMA1_GB_ADDR_CONFIG_DEFAULT 0x00100012
-#define mmSDMA1_GB_ADDR_CONFIG_READ_DEFAULT 0x00100012
-#define mmSDMA1_RB_RPTR_FETCH_HI_DEFAULT 0x00000000
-#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_DEFAULT 0x00000000
-#define mmSDMA1_RB_RPTR_FETCH_DEFAULT 0x00000000
-#define mmSDMA1_IB_OFFSET_FETCH_DEFAULT 0x00000000
-#define mmSDMA1_PROGRAM_DEFAULT 0x00000000
-#define mmSDMA1_STATUS_REG_DEFAULT 0x46dee557
-#define mmSDMA1_STATUS1_REG_DEFAULT 0x000003ff
-#define mmSDMA1_RD_BURST_CNTL_DEFAULT 0x00000003
-#define mmSDMA1_HBM_PAGE_CONFIG_DEFAULT 0x00000000
-#define mmSDMA1_UCODE_CHECKSUM_DEFAULT 0x00000000
-#define mmSDMA1_F32_CNTL_DEFAULT 0x00000001
-#define mmSDMA1_FREEZE_DEFAULT 0x00000000
-#define mmSDMA1_PHASE0_QUANTUM_DEFAULT 0x00010002
-#define mmSDMA1_PHASE1_QUANTUM_DEFAULT 0x00010002
-#define mmSDMA1_EDC_CONFIG_DEFAULT 0x00000002
-#define mmSDMA1_BA_THRESHOLD_DEFAULT 0x03ff03ff
-#define mmSDMA1_ID_DEFAULT 0x00000001
-#define mmSDMA1_VERSION_DEFAULT 0x00000400
-#define mmSDMA1_EDC_COUNTER_DEFAULT 0x00000000
-#define mmSDMA1_EDC_COUNTER_CLEAR_DEFAULT 0x00000000
-#define mmSDMA1_STATUS2_REG_DEFAULT 0x00000001
-#define mmSDMA1_ATOMIC_CNTL_DEFAULT 0x00000200
-#define mmSDMA1_ATOMIC_PREOP_LO_DEFAULT 0x00000000
-#define mmSDMA1_ATOMIC_PREOP_HI_DEFAULT 0x00000000
-#define mmSDMA1_UTCL1_CNTL_DEFAULT 0xd0003019
-#define mmSDMA1_UTCL1_WATERMK_DEFAULT 0xfffbe1fe
-#define mmSDMA1_UTCL1_RD_STATUS_DEFAULT 0x201001ff
-#define mmSDMA1_UTCL1_WR_STATUS_DEFAULT 0x503001ff
-#define mmSDMA1_UTCL1_INV0_DEFAULT 0x00000600
-#define mmSDMA1_UTCL1_INV1_DEFAULT 0x00000000
-#define mmSDMA1_UTCL1_INV2_DEFAULT 0x00000000
-#define mmSDMA1_UTCL1_RD_XNACK0_DEFAULT 0x00000000
-#define mmSDMA1_UTCL1_RD_XNACK1_DEFAULT 0x00000000
-#define mmSDMA1_UTCL1_WR_XNACK0_DEFAULT 0x00000000
-#define mmSDMA1_UTCL1_WR_XNACK1_DEFAULT 0x00000000
-#define mmSDMA1_UTCL1_TIMEOUT_DEFAULT 0x00010001
-#define mmSDMA1_UTCL1_PAGE_DEFAULT 0x000003e0
-#define mmSDMA1_POWER_CNTL_IDLE_DEFAULT 0x06060200
-#define mmSDMA1_RELAX_ORDERING_LUT_DEFAULT 0xc0000006
-#define mmSDMA1_CHICKEN_BITS_2_DEFAULT 0x00000005
-#define mmSDMA1_STATUS3_REG_DEFAULT 0x00100000
-#define mmSDMA1_PHYSICAL_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA1_PHYSICAL_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA1_PHASE2_QUANTUM_DEFAULT 0x00010002
-#define mmSDMA1_ERROR_LOG_DEFAULT 0x0000000f
-#define mmSDMA1_PUB_DUMMY_REG0_DEFAULT 0x00000000
-#define mmSDMA1_PUB_DUMMY_REG1_DEFAULT 0x00000000
-#define mmSDMA1_PUB_DUMMY_REG2_DEFAULT 0x00000000
-#define mmSDMA1_PUB_DUMMY_REG3_DEFAULT 0x00000000
-#define mmSDMA1_F32_COUNTER_DEFAULT 0x00000000
-#define mmSDMA1_UNBREAKABLE_DEFAULT 0x00000000
-#define mmSDMA1_PERFMON_CNTL_DEFAULT 0x000ff7fd
-#define mmSDMA1_PERFCOUNTER0_RESULT_DEFAULT 0x00000000
-#define mmSDMA1_PERFCOUNTER1_RESULT_DEFAULT 0x00000000
-#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE_DEFAULT 0x00640000
-#define mmSDMA1_CRD_CNTL_DEFAULT 0x000085c0
-#define mmSDMA1_MMHUB_TRUSTLVL_DEFAULT 0x00000000
-#define mmSDMA1_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000
-#define mmSDMA1_ULV_CNTL_DEFAULT 0x00000000
-#define mmSDMA1_EA_DBIT_ADDR_DATA_DEFAULT 0x00000000
-#define mmSDMA1_EA_DBIT_ADDR_INDEX_DEFAULT 0x00000000
-#define mmSDMA1_GFX_RB_CNTL_DEFAULT 0x00040000
-#define mmSDMA1_GFX_RB_BASE_DEFAULT 0x00000000
-#define mmSDMA1_GFX_RB_BASE_HI_DEFAULT 0x00000000
-#define mmSDMA1_GFX_RB_RPTR_DEFAULT 0x00000000
-#define mmSDMA1_GFX_RB_RPTR_HI_DEFAULT 0x00000000
-#define mmSDMA1_GFX_RB_WPTR_DEFAULT 0x00000000
-#define mmSDMA1_GFX_RB_WPTR_HI_DEFAULT 0x00000000
-#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
-#define mmSDMA1_GFX_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA1_GFX_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA1_GFX_IB_CNTL_DEFAULT 0x00000100
-#define mmSDMA1_GFX_IB_RPTR_DEFAULT 0x00000000
-#define mmSDMA1_GFX_IB_OFFSET_DEFAULT 0x00000000
-#define mmSDMA1_GFX_IB_BASE_LO_DEFAULT 0x00000000
-#define mmSDMA1_GFX_IB_BASE_HI_DEFAULT 0x00000000
-#define mmSDMA1_GFX_IB_SIZE_DEFAULT 0x00000000
-#define mmSDMA1_GFX_SKIP_CNTL_DEFAULT 0x00000000
-#define mmSDMA1_GFX_CONTEXT_STATUS_DEFAULT 0x00000005
-#define mmSDMA1_GFX_DOORBELL_DEFAULT 0x00000000
-#define mmSDMA1_GFX_CONTEXT_CNTL_DEFAULT 0x00000000
-#define mmSDMA1_GFX_STATUS_DEFAULT 0x00000000
-#define mmSDMA1_GFX_DOORBELL_LOG_DEFAULT 0x00000000
-#define mmSDMA1_GFX_WATERMARK_DEFAULT 0x00000000
-#define mmSDMA1_GFX_DOORBELL_OFFSET_DEFAULT 0x00000000
-#define mmSDMA1_GFX_CSA_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA1_GFX_CSA_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA1_GFX_IB_SUB_REMAIN_DEFAULT 0x00000000
-#define mmSDMA1_GFX_PREEMPT_DEFAULT 0x00000000
-#define mmSDMA1_GFX_DUMMY_REG_DEFAULT 0x0000000f
-#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA1_GFX_RB_AQL_CNTL_DEFAULT 0x00004000
-#define mmSDMA1_GFX_MINOR_PTR_UPDATE_DEFAULT 0x00000000
-#define mmSDMA1_GFX_MIDCMD_DATA0_DEFAULT 0x00000000
-#define mmSDMA1_GFX_MIDCMD_DATA1_DEFAULT 0x00000000
-#define mmSDMA1_GFX_MIDCMD_DATA2_DEFAULT 0x00000000
-#define mmSDMA1_GFX_MIDCMD_DATA3_DEFAULT 0x00000000
-#define mmSDMA1_GFX_MIDCMD_DATA4_DEFAULT 0x00000000
-#define mmSDMA1_GFX_MIDCMD_DATA5_DEFAULT 0x00000000
-#define mmSDMA1_GFX_MIDCMD_DATA6_DEFAULT 0x00000000
-#define mmSDMA1_GFX_MIDCMD_DATA7_DEFAULT 0x00000000
-#define mmSDMA1_GFX_MIDCMD_DATA8_DEFAULT 0x00000000
-#define mmSDMA1_GFX_MIDCMD_CNTL_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_RB_CNTL_DEFAULT 0x00040000
-#define mmSDMA1_PAGE_RB_BASE_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_RB_BASE_HI_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_RB_RPTR_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_RB_RPTR_HI_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_RB_WPTR_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_RB_WPTR_HI_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
-#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_IB_CNTL_DEFAULT 0x00000100
-#define mmSDMA1_PAGE_IB_RPTR_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_IB_OFFSET_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_IB_BASE_LO_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_IB_BASE_HI_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_IB_SIZE_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_SKIP_CNTL_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_CONTEXT_STATUS_DEFAULT 0x00000004
-#define mmSDMA1_PAGE_DOORBELL_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_STATUS_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_DOORBELL_LOG_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_WATERMARK_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_DOORBELL_OFFSET_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_CSA_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_CSA_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_IB_SUB_REMAIN_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_PREEMPT_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_DUMMY_REG_DEFAULT 0x0000000f
-#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_RB_AQL_CNTL_DEFAULT 0x00004000
-#define mmSDMA1_PAGE_MINOR_PTR_UPDATE_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_MIDCMD_DATA0_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_MIDCMD_DATA1_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_MIDCMD_DATA2_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_MIDCMD_DATA3_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_MIDCMD_DATA4_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_MIDCMD_DATA5_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_MIDCMD_DATA6_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_MIDCMD_DATA7_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_MIDCMD_DATA8_DEFAULT 0x00000000
-#define mmSDMA1_PAGE_MIDCMD_CNTL_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_RB_CNTL_DEFAULT 0x00040000
-#define mmSDMA1_RLC0_RB_BASE_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_RB_BASE_HI_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_RB_RPTR_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_RB_RPTR_HI_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_RB_WPTR_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_RB_WPTR_HI_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
-#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_IB_CNTL_DEFAULT 0x00000100
-#define mmSDMA1_RLC0_IB_RPTR_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_IB_OFFSET_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_IB_BASE_LO_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_IB_BASE_HI_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_IB_SIZE_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_SKIP_CNTL_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_CONTEXT_STATUS_DEFAULT 0x00000004
-#define mmSDMA1_RLC0_DOORBELL_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_STATUS_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_DOORBELL_LOG_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_WATERMARK_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_DOORBELL_OFFSET_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_CSA_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_CSA_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_IB_SUB_REMAIN_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_PREEMPT_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_DUMMY_REG_DEFAULT 0x0000000f
-#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_RB_AQL_CNTL_DEFAULT 0x00004000
-#define mmSDMA1_RLC0_MINOR_PTR_UPDATE_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_MIDCMD_DATA0_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_MIDCMD_DATA1_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_MIDCMD_DATA2_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_MIDCMD_DATA3_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_MIDCMD_DATA4_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_MIDCMD_DATA5_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_MIDCMD_DATA6_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_MIDCMD_DATA7_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_MIDCMD_DATA8_DEFAULT 0x00000000
-#define mmSDMA1_RLC0_MIDCMD_CNTL_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_RB_CNTL_DEFAULT 0x00040000
-#define mmSDMA1_RLC1_RB_BASE_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_RB_BASE_HI_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_RB_RPTR_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_RB_RPTR_HI_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_RB_WPTR_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_RB_WPTR_HI_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
-#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_IB_CNTL_DEFAULT 0x00000100
-#define mmSDMA1_RLC1_IB_RPTR_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_IB_OFFSET_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_IB_BASE_LO_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_IB_BASE_HI_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_IB_SIZE_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_SKIP_CNTL_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_CONTEXT_STATUS_DEFAULT 0x00000004
-#define mmSDMA1_RLC1_DOORBELL_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_STATUS_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_DOORBELL_LOG_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_WATERMARK_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_DOORBELL_OFFSET_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_CSA_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_CSA_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_IB_SUB_REMAIN_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_PREEMPT_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_DUMMY_REG_DEFAULT 0x0000000f
-#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_RB_AQL_CNTL_DEFAULT 0x00004000
-#define mmSDMA1_RLC1_MINOR_PTR_UPDATE_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_MIDCMD_DATA0_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_MIDCMD_DATA1_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_MIDCMD_DATA2_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_MIDCMD_DATA3_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_MIDCMD_DATA4_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_MIDCMD_DATA5_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_MIDCMD_DATA6_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_MIDCMD_DATA7_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_MIDCMD_DATA8_DEFAULT 0x00000000
-#define mmSDMA1_RLC1_MIDCMD_CNTL_DEFAULT 0x00000000
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_d.h
deleted file mode 100644
index 57588b11f..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_d.h
+++ /dev/null
@@ -1,1344 +0,0 @@
-/*
- * SMU_7_1_0 Register documentation
- *
- * Copyright (C) 2014 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef SMU_7_1_0_D_H
-#define SMU_7_1_0_D_H
-
-#define mmGCK_SMC_IND_INDEX 0x80
-#define mmGCK0_GCK_SMC_IND_INDEX 0x80
-#define mmGCK1_GCK_SMC_IND_INDEX 0x82
-#define mmGCK2_GCK_SMC_IND_INDEX 0x84
-#define mmGCK3_GCK_SMC_IND_INDEX 0x86
-#define mmGCK_SMC_IND_DATA 0x81
-#define mmGCK0_GCK_SMC_IND_DATA 0x81
-#define mmGCK1_GCK_SMC_IND_DATA 0x83
-#define mmGCK2_GCK_SMC_IND_DATA 0x85
-#define mmGCK3_GCK_SMC_IND_DATA 0x87
-#define ixCG_DCLK_CNTL 0xc050009c
-#define ixCG_DCLK_STATUS 0xc05000a0
-#define ixCG_VCLK_CNTL 0xc05000a4
-#define ixCG_VCLK_STATUS 0xc05000a8
-#define ixCG_ECLK_CNTL 0xc05000ac
-#define ixCG_ECLK_STATUS 0xc05000b0
-#define ixCG_ACLK_CNTL 0xc05000dc
-#define ixGCK_DFS_BYPASS_CNTL 0xc0500118
-#define ixCG_SPLL_FUNC_CNTL 0xc0500140
-#define ixCG_SPLL_FUNC_CNTL_2 0xc0500144
-#define ixCG_SPLL_FUNC_CNTL_3 0xc0500148
-#define ixCG_SPLL_FUNC_CNTL_4 0xc050014c
-#define ixCG_SPLL_FUNC_CNTL_5 0xc0500150
-#define ixCG_SPLL_FUNC_CNTL_6 0xc0500154
-#define ixCG_SPLL_FUNC_CNTL_7 0xc0500158
-#define ixSPLL_CNTL_MODE 0xc0500160
-#define ixCG_SPLL_SPREAD_SPECTRUM 0xc0500164
-#define ixCG_SPLL_SPREAD_SPECTRUM_2 0xc0500168
-#define ixMPLL_BYPASSCLK_SEL 0xc050019c
-#define ixCG_CLKPIN_CNTL 0xc05001a0
-#define ixCG_CLKPIN_CNTL_2 0xc05001a4
-#define ixCG_CLKPIN_CNTL_DC 0xc0500204
-#define ixTHM_CLK_CNTL 0xc05001a8
-#define ixMISC_CLK_CTRL 0xc05001ac
-#define ixGCK_PLL_TEST_CNTL 0xc05001c0
-#define ixGCK_PLL_TEST_CNTL_2 0xc05001c4
-#define ixGCK_ADFS_CLK_BYPASS_CNTL1 0xc05001c8
-#define mmSMC_IND_INDEX 0x80
-#define mmSMC0_SMC_IND_INDEX 0x80
-#define mmSMC1_SMC_IND_INDEX 0x82
-#define mmSMC2_SMC_IND_INDEX 0x84
-#define mmSMC3_SMC_IND_INDEX 0x86
-#define mmSMC_IND_DATA 0x81
-#define mmSMC0_SMC_IND_DATA 0x81
-#define mmSMC1_SMC_IND_DATA 0x83
-#define mmSMC2_SMC_IND_DATA 0x85
-#define mmSMC3_SMC_IND_DATA 0x87
-#define mmSMC_IND_INDEX_0 0x80
-#define mmSMC_IND_DATA_0 0x81
-#define mmSMC_IND_INDEX_1 0x82
-#define mmSMC_IND_DATA_1 0x83
-#define mmSMC_IND_INDEX_2 0x84
-#define mmSMC_IND_DATA_2 0x85
-#define mmSMC_IND_INDEX_3 0x86
-#define mmSMC_IND_DATA_3 0x87
-#define mmSMC_IND_INDEX_4 0x88
-#define mmSMC_IND_DATA_4 0x89
-#define mmSMC_IND_INDEX_5 0x8a
-#define mmSMC_IND_DATA_5 0x8b
-#define mmSMC_IND_INDEX_6 0x8c
-#define mmSMC_IND_DATA_6 0x8d
-#define mmSMC_IND_INDEX_7 0x8e
-#define mmSMC_IND_DATA_7 0x8f
-#define mmSMC_IND_ACCESS_CNTL 0x90
-#define mmSMC_MESSAGE_0 0x94
-#define mmSMC_RESP_0 0x95
-#define mmSMC_MESSAGE_1 0x96
-#define mmSMC_RESP_1 0x97
-#define mmSMC_MESSAGE_2 0x98
-#define mmSMC_RESP_2 0x99
-#define mmSMC_MESSAGE_3 0x9a
-#define mmSMC_RESP_3 0x9b
-#define mmSMC_MESSAGE_4 0x9c
-#define mmSMC_RESP_4 0x9d
-#define mmSMC_MESSAGE_5 0x9e
-#define mmSMC_RESP_5 0x9f
-#define mmSMC_MESSAGE_6 0xa0
-#define mmSMC_RESP_6 0xa1
-#define mmSMC_MESSAGE_7 0xa2
-#define mmSMC_RESP_7 0xa3
-#define mmSMC_MSG_ARG_0 0xa4
-#define mmSMC_MSG_ARG_1 0xa5
-#define mmSMC_MSG_ARG_2 0xa6
-#define mmSMC_MSG_ARG_3 0xa7
-#define mmSMC_MSG_ARG_4 0xa8
-#define mmSMC_MSG_ARG_5 0xa9
-#define mmSMC_MSG_ARG_6 0xaa
-#define mmSMC_MSG_ARG_7 0xab
-#define mmSMC_MESSAGE_8 0xb5
-#define mmSMC_RESP_8 0xb6
-#define mmSMC_MESSAGE_9 0xb7
-#define mmSMC_RESP_9 0xb8
-#define mmSMC_MESSAGE_10 0xb9
-#define mmSMC_RESP_10 0xba
-#define mmSMC_MESSAGE_11 0xbb
-#define mmSMC_RESP_11 0xbc
-#define mmSMC_MSG_ARG_8 0xbd
-#define mmSMC_MSG_ARG_9 0xbe
-#define mmSMC_MSG_ARG_10 0xbf
-#define mmSMC_MSG_ARG_11 0x91
-#define ixSMC_SYSCON_RESET_CNTL 0x80000000
-#define ixSMC_SYSCON_CLOCK_CNTL_0 0x80000004
-#define ixSMC_SYSCON_CLOCK_CNTL_1 0x80000008
-#define ixSMC_SYSCON_CLOCK_CNTL_2 0x8000000c
-#define ixSMC_SYSCON_MISC_CNTL 0x80000010
-#define ixSMC_SYSCON_MSG_ARG_0 0x80000068
-#define ixSMC_PC_C 0x80000370
-#define ixSMC_SCRATCH9 0x80000424
-#define mmGPIOPAD_SW_INT_STAT 0x180
-#define mmGPIOPAD_STRENGTH 0x181
-#define mmGPIOPAD_MASK 0x182
-#define mmGPIOPAD_A 0x183
-#define mmGPIOPAD_EN 0x184
-#define mmGPIOPAD_Y 0x185
-#define mmGPIOPAD_PINSTRAPS 0x186
-#define mmGPIOPAD_INT_STAT_EN 0x187
-#define mmGPIOPAD_INT_STAT 0x188
-#define mmGPIOPAD_INT_STAT_AK 0x189
-#define mmGPIOPAD_INT_EN 0x18a
-#define mmGPIOPAD_INT_TYPE 0x18b
-#define mmGPIOPAD_INT_POLARITY 0x18c
-#define mmGPIOPAD_EXTERN_TRIG_CNTL 0x18d
-#define mmGPIOPAD_RCVR_SEL 0x191
-#define mmGPIOPAD_PU_EN 0x192
-#define mmGPIOPAD_PD_EN 0x193
-#define mmCG_FPS_CNT 0x1a4
-#define mmSMU_SMC_IND_INDEX 0x80
-#define mmSMU0_SMU_SMC_IND_INDEX 0x80
-#define mmSMU1_SMU_SMC_IND_INDEX 0x82
-#define mmSMU2_SMU_SMC_IND_INDEX 0x84
-#define mmSMU3_SMU_SMC_IND_INDEX 0x86
-#define mmSMU_SMC_IND_DATA 0x81
-#define mmSMU0_SMU_SMC_IND_DATA 0x81
-#define mmSMU1_SMU_SMC_IND_DATA 0x83
-#define mmSMU2_SMU_SMC_IND_DATA 0x85
-#define mmSMU3_SMU_SMC_IND_DATA 0x87
-#define ixRCU_UC_EVENTS 0xc0000004
-#define ixRCU_MISC_CTRL 0xc0000010
-#define ixCC_RCU_FUSES 0xc00c0000
-#define ixCC_SMU_MISC_FUSES 0xc00c0004
-#define ixCC_SCLK_VID_FUSES 0xc00c0008
-#define ixCC_GIO_IOCCFG_FUSES 0xc00c000c
-#define ixCC_GIO_IOC_FUSES 0xc00c0010
-#define ixCC_SMU_TST_EFUSE1_MISC 0xc00c001c
-#define ixCC_TST_ID_STRAPS 0xc00c0020
-#define ixCC_FCTRL_FUSES 0xc00c0024
-#define ixSMU_MAIN_PLL_OP_FREQ 0xe0003020
-#define ixSMU_STATUS 0xe0003088
-#define ixSMU_FIRMWARE 0xe00030a4
-#define ixSMU_INPUT_DATA 0xe00030b8
-#define ixSMU_EFUSE_0 0xc0100000
-#define ixDPM_TABLE_1 0x3f000
-#define ixDPM_TABLE_2 0x3f004
-#define ixDPM_TABLE_3 0x3f008
-#define ixDPM_TABLE_4 0x3f00c
-#define ixDPM_TABLE_5 0x3f010
-#define ixDPM_TABLE_6 0x3f014
-#define ixDPM_TABLE_7 0x3f018
-#define ixDPM_TABLE_8 0x3f01c
-#define ixDPM_TABLE_9 0x3f020
-#define ixDPM_TABLE_10 0x3f024
-#define ixDPM_TABLE_11 0x3f028
-#define ixDPM_TABLE_12 0x3f02c
-#define ixDPM_TABLE_13 0x3f030
-#define ixDPM_TABLE_14 0x3f034
-#define ixDPM_TABLE_15 0x3f038
-#define ixDPM_TABLE_16 0x3f03c
-#define ixDPM_TABLE_17 0x3f040
-#define ixDPM_TABLE_18 0x3f044
-#define ixDPM_TABLE_19 0x3f048
-#define ixDPM_TABLE_20 0x3f04c
-#define ixDPM_TABLE_21 0x3f050
-#define ixDPM_TABLE_22 0x3f054
-#define ixDPM_TABLE_23 0x3f058
-#define ixDPM_TABLE_24 0x3f05c
-#define ixDPM_TABLE_25 0x3f060
-#define ixDPM_TABLE_26 0x3f064
-#define ixDPM_TABLE_27 0x3f068
-#define ixDPM_TABLE_28 0x3f06c
-#define ixDPM_TABLE_29 0x3f070
-#define ixDPM_TABLE_30 0x3f074
-#define ixDPM_TABLE_31 0x3f078
-#define ixDPM_TABLE_32 0x3f07c
-#define ixDPM_TABLE_33 0x3f080
-#define ixDPM_TABLE_34 0x3f084
-#define ixDPM_TABLE_35 0x3f088
-#define ixDPM_TABLE_36 0x3f08c
-#define ixDPM_TABLE_37 0x3f090
-#define ixDPM_TABLE_38 0x3f094
-#define ixDPM_TABLE_39 0x3f098
-#define ixDPM_TABLE_40 0x3f09c
-#define ixDPM_TABLE_41 0x3f0a0
-#define ixDPM_TABLE_42 0x3f0a4
-#define ixDPM_TABLE_43 0x3f0a8
-#define ixDPM_TABLE_44 0x3f0ac
-#define ixDPM_TABLE_45 0x3f0b0
-#define ixDPM_TABLE_46 0x3f0b4
-#define ixDPM_TABLE_47 0x3f0b8
-#define ixDPM_TABLE_48 0x3f0bc
-#define ixDPM_TABLE_49 0x3f0c0
-#define ixDPM_TABLE_50 0x3f0c4
-#define ixDPM_TABLE_51 0x3f0c8
-#define ixDPM_TABLE_52 0x3f0cc
-#define ixDPM_TABLE_53 0x3f0d0
-#define ixDPM_TABLE_54 0x3f0d4
-#define ixDPM_TABLE_55 0x3f0d8
-#define ixDPM_TABLE_56 0x3f0dc
-#define ixDPM_TABLE_57 0x3f0e0
-#define ixDPM_TABLE_58 0x3f0e4
-#define ixDPM_TABLE_59 0x3f0e8
-#define ixDPM_TABLE_60 0x3f0ec
-#define ixDPM_TABLE_61 0x3f0f0
-#define ixDPM_TABLE_62 0x3f0f4
-#define ixDPM_TABLE_63 0x3f0f8
-#define ixDPM_TABLE_64 0x3f0fc
-#define ixDPM_TABLE_65 0x3f100
-#define ixDPM_TABLE_66 0x3f104
-#define ixDPM_TABLE_67 0x3f108
-#define ixDPM_TABLE_68 0x3f10c
-#define ixDPM_TABLE_69 0x3f110
-#define ixDPM_TABLE_70 0x3f114
-#define ixDPM_TABLE_71 0x3f118
-#define ixDPM_TABLE_72 0x3f11c
-#define ixDPM_TABLE_73 0x3f120
-#define ixDPM_TABLE_74 0x3f124
-#define ixDPM_TABLE_75 0x3f128
-#define ixDPM_TABLE_76 0x3f12c
-#define ixDPM_TABLE_77 0x3f130
-#define ixDPM_TABLE_78 0x3f134
-#define ixDPM_TABLE_79 0x3f138
-#define ixDPM_TABLE_80 0x3f13c
-#define ixDPM_TABLE_81 0x3f140
-#define ixDPM_TABLE_82 0x3f144
-#define ixDPM_TABLE_83 0x3f148
-#define ixDPM_TABLE_84 0x3f14c
-#define ixDPM_TABLE_85 0x3f150
-#define ixDPM_TABLE_86 0x3f154
-#define ixDPM_TABLE_87 0x3f158
-#define ixDPM_TABLE_88 0x3f15c
-#define ixDPM_TABLE_89 0x3f160
-#define ixDPM_TABLE_90 0x3f164
-#define ixDPM_TABLE_91 0x3f168
-#define ixDPM_TABLE_92 0x3f16c
-#define ixDPM_TABLE_93 0x3f170
-#define ixDPM_TABLE_94 0x3f174
-#define ixDPM_TABLE_95 0x3f178
-#define ixDPM_TABLE_96 0x3f17c
-#define ixDPM_TABLE_97 0x3f180
-#define ixDPM_TABLE_98 0x3f184
-#define ixDPM_TABLE_99 0x3f188
-#define ixDPM_TABLE_100 0x3f18c
-#define ixDPM_TABLE_101 0x3f190
-#define ixDPM_TABLE_102 0x3f194
-#define ixDPM_TABLE_103 0x3f198
-#define ixDPM_TABLE_104 0x3f19c
-#define ixDPM_TABLE_105 0x3f1a0
-#define ixDPM_TABLE_106 0x3f1a4
-#define ixDPM_TABLE_107 0x3f1a8
-#define ixDPM_TABLE_108 0x3f1ac
-#define ixDPM_TABLE_109 0x3f1b0
-#define ixDPM_TABLE_110 0x3f1b4
-#define ixDPM_TABLE_111 0x3f1b8
-#define ixDPM_TABLE_112 0x3f1bc
-#define ixDPM_TABLE_113 0x3f1c0
-#define ixDPM_TABLE_114 0x3f1c4
-#define ixDPM_TABLE_115 0x3f1c8
-#define ixDPM_TABLE_116 0x3f1cc
-#define ixDPM_TABLE_117 0x3f1d0
-#define ixDPM_TABLE_118 0x3f1d4
-#define ixDPM_TABLE_119 0x3f1d8
-#define ixDPM_TABLE_120 0x3f1dc
-#define ixDPM_TABLE_121 0x3f1e0
-#define ixDPM_TABLE_122 0x3f1e4
-#define ixDPM_TABLE_123 0x3f1e8
-#define ixDPM_TABLE_124 0x3f1ec
-#define ixDPM_TABLE_125 0x3f1f0
-#define ixDPM_TABLE_126 0x3f1f4
-#define ixDPM_TABLE_127 0x3f1f8
-#define ixDPM_TABLE_128 0x3f1fc
-#define ixDPM_TABLE_129 0x3f200
-#define ixDPM_TABLE_130 0x3f204
-#define ixDPM_TABLE_131 0x3f208
-#define ixDPM_TABLE_132 0x3f20c
-#define ixDPM_TABLE_133 0x3f210
-#define ixDPM_TABLE_134 0x3f214
-#define ixDPM_TABLE_135 0x3f218
-#define ixDPM_TABLE_136 0x3f21c
-#define ixDPM_TABLE_137 0x3f220
-#define ixDPM_TABLE_138 0x3f224
-#define ixDPM_TABLE_139 0x3f228
-#define ixDPM_TABLE_140 0x3f22c
-#define ixDPM_TABLE_141 0x3f230
-#define ixDPM_TABLE_142 0x3f234
-#define ixDPM_TABLE_143 0x3f238
-#define ixDPM_TABLE_144 0x3f23c
-#define ixDPM_TABLE_145 0x3f240
-#define ixDPM_TABLE_146 0x3f244
-#define ixDPM_TABLE_147 0x3f248
-#define ixDPM_TABLE_148 0x3f24c
-#define ixDPM_TABLE_149 0x3f250
-#define ixDPM_TABLE_150 0x3f254
-#define ixDPM_TABLE_151 0x3f258
-#define ixDPM_TABLE_152 0x3f25c
-#define ixDPM_TABLE_153 0x3f260
-#define ixDPM_TABLE_154 0x3f264
-#define ixDPM_TABLE_155 0x3f268
-#define ixDPM_TABLE_156 0x3f26c
-#define ixDPM_TABLE_157 0x3f270
-#define ixDPM_TABLE_158 0x3f274
-#define ixDPM_TABLE_159 0x3f278
-#define ixDPM_TABLE_160 0x3f27c
-#define ixDPM_TABLE_161 0x3f280
-#define ixDPM_TABLE_162 0x3f284
-#define ixDPM_TABLE_163 0x3f288
-#define ixDPM_TABLE_164 0x3f28c
-#define ixDPM_TABLE_165 0x3f290
-#define ixDPM_TABLE_166 0x3f294
-#define ixDPM_TABLE_167 0x3f298
-#define ixDPM_TABLE_168 0x3f29c
-#define ixDPM_TABLE_169 0x3f2a0
-#define ixDPM_TABLE_170 0x3f2a4
-#define ixDPM_TABLE_171 0x3f2a8
-#define ixDPM_TABLE_172 0x3f2ac
-#define ixDPM_TABLE_173 0x3f2b0
-#define ixDPM_TABLE_174 0x3f2b4
-#define ixDPM_TABLE_175 0x3f2b8
-#define ixDPM_TABLE_176 0x3f2bc
-#define ixDPM_TABLE_177 0x3f2c0
-#define ixDPM_TABLE_178 0x3f2c4
-#define ixDPM_TABLE_179 0x3f2c8
-#define ixDPM_TABLE_180 0x3f2cc
-#define ixDPM_TABLE_181 0x3f2d0
-#define ixDPM_TABLE_182 0x3f2d4
-#define ixDPM_TABLE_183 0x3f2d8
-#define ixDPM_TABLE_184 0x3f2dc
-#define ixDPM_TABLE_185 0x3f2e0
-#define ixDPM_TABLE_186 0x3f2e4
-#define ixDPM_TABLE_187 0x3f2e8
-#define ixDPM_TABLE_188 0x3f2ec
-#define ixDPM_TABLE_189 0x3f2f0
-#define ixDPM_TABLE_190 0x3f2f4
-#define ixDPM_TABLE_191 0x3f2f8
-#define ixDPM_TABLE_192 0x3f2fc
-#define ixDPM_TABLE_193 0x3f300
-#define ixDPM_TABLE_194 0x3f304
-#define ixDPM_TABLE_195 0x3f308
-#define ixDPM_TABLE_196 0x3f30c
-#define ixDPM_TABLE_197 0x3f310
-#define ixDPM_TABLE_198 0x3f314
-#define ixDPM_TABLE_199 0x3f318
-#define ixDPM_TABLE_200 0x3f31c
-#define ixDPM_TABLE_201 0x3f320
-#define ixDPM_TABLE_202 0x3f324
-#define ixDPM_TABLE_203 0x3f328
-#define ixDPM_TABLE_204 0x3f32c
-#define ixDPM_TABLE_205 0x3f330
-#define ixDPM_TABLE_206 0x3f334
-#define ixDPM_TABLE_207 0x3f338
-#define ixDPM_TABLE_208 0x3f33c
-#define ixDPM_TABLE_209 0x3f340
-#define ixDPM_TABLE_210 0x3f344
-#define ixDPM_TABLE_211 0x3f348
-#define ixDPM_TABLE_212 0x3f34c
-#define ixDPM_TABLE_213 0x3f350
-#define ixDPM_TABLE_214 0x3f354
-#define ixDPM_TABLE_215 0x3f358
-#define ixDPM_TABLE_216 0x3f35c
-#define ixDPM_TABLE_217 0x3f360
-#define ixDPM_TABLE_218 0x3f364
-#define ixDPM_TABLE_219 0x3f368
-#define ixDPM_TABLE_220 0x3f36c
-#define ixDPM_TABLE_221 0x3f370
-#define ixDPM_TABLE_222 0x3f374
-#define ixDPM_TABLE_223 0x3f378
-#define ixDPM_TABLE_224 0x3f37c
-#define ixDPM_TABLE_225 0x3f380
-#define ixDPM_TABLE_226 0x3f384
-#define ixDPM_TABLE_227 0x3f388
-#define ixDPM_TABLE_228 0x3f38c
-#define ixDPM_TABLE_229 0x3f390
-#define ixDPM_TABLE_230 0x3f394
-#define ixDPM_TABLE_231 0x3f398
-#define ixDPM_TABLE_232 0x3f39c
-#define ixDPM_TABLE_233 0x3f3a0
-#define ixDPM_TABLE_234 0x3f3a4
-#define ixDPM_TABLE_235 0x3f3a8
-#define ixDPM_TABLE_236 0x3f3ac
-#define ixDPM_TABLE_237 0x3f3b0
-#define ixDPM_TABLE_238 0x3f3b4
-#define ixDPM_TABLE_239 0x3f3b8
-#define ixDPM_TABLE_240 0x3f3bc
-#define ixDPM_TABLE_241 0x3f3c0
-#define ixDPM_TABLE_242 0x3f3c4
-#define ixDPM_TABLE_243 0x3f3c8
-#define ixDPM_TABLE_244 0x3f3cc
-#define ixDPM_TABLE_245 0x3f3d0
-#define ixDPM_TABLE_246 0x3f3d4
-#define ixDPM_TABLE_247 0x3f3d8
-#define ixDPM_TABLE_248 0x3f3dc
-#define ixDPM_TABLE_249 0x3f3e0
-#define ixDPM_TABLE_250 0x3f3e4
-#define ixDPM_TABLE_251 0x3f3e8
-#define ixDPM_TABLE_252 0x3f3ec
-#define ixDPM_TABLE_253 0x3f3f0
-#define ixDPM_TABLE_254 0x3f3f4
-#define ixDPM_TABLE_255 0x3f3f8
-#define ixDPM_TABLE_256 0x3f3fc
-#define ixDPM_TABLE_257 0x3f400
-#define ixDPM_TABLE_258 0x3f404
-#define ixDPM_TABLE_259 0x3f408
-#define ixDPM_TABLE_260 0x3f40c
-#define ixDPM_TABLE_261 0x3f410
-#define ixDPM_TABLE_262 0x3f414
-#define ixDPM_TABLE_263 0x3f418
-#define ixDPM_TABLE_264 0x3f41c
-#define ixDPM_TABLE_265 0x3f420
-#define ixDPM_TABLE_266 0x3f424
-#define ixDPM_TABLE_267 0x3f428
-#define ixDPM_TABLE_268 0x3f42c
-#define ixDPM_TABLE_269 0x3f430
-#define ixDPM_TABLE_270 0x3f434
-#define ixDPM_TABLE_271 0x3f438
-#define ixDPM_TABLE_272 0x3f43c
-#define ixDPM_TABLE_273 0x3f440
-#define ixDPM_TABLE_274 0x3f444
-#define ixDPM_TABLE_275 0x3f448
-#define ixDPM_TABLE_276 0x3f44c
-#define ixDPM_TABLE_277 0x3f450
-#define ixDPM_TABLE_278 0x3f454
-#define ixDPM_TABLE_279 0x3f458
-#define ixDPM_TABLE_280 0x3f45c
-#define ixDPM_TABLE_281 0x3f460
-#define ixDPM_TABLE_282 0x3f464
-#define ixDPM_TABLE_283 0x3f468
-#define ixDPM_TABLE_284 0x3f46c
-#define ixDPM_TABLE_285 0x3f470
-#define ixDPM_TABLE_286 0x3f474
-#define ixDPM_TABLE_287 0x3f478
-#define ixDPM_TABLE_288 0x3f47c
-#define ixDPM_TABLE_289 0x3f480
-#define ixDPM_TABLE_290 0x3f484
-#define ixDPM_TABLE_291 0x3f488
-#define ixDPM_TABLE_292 0x3f48c
-#define ixDPM_TABLE_293 0x3f490
-#define ixDPM_TABLE_294 0x3f494
-#define ixDPM_TABLE_295 0x3f498
-#define ixDPM_TABLE_296 0x3f49c
-#define ixDPM_TABLE_297 0x3f4a0
-#define ixDPM_TABLE_298 0x3f4a4
-#define ixDPM_TABLE_299 0x3f4a8
-#define ixDPM_TABLE_300 0x3f4ac
-#define ixDPM_TABLE_301 0x3f4b0
-#define ixDPM_TABLE_302 0x3f4b4
-#define ixDPM_TABLE_303 0x3f4b8
-#define ixDPM_TABLE_304 0x3f4bc
-#define ixDPM_TABLE_305 0x3f4c0
-#define ixDPM_TABLE_306 0x3f4c4
-#define ixDPM_TABLE_307 0x3f4c8
-#define ixDPM_TABLE_308 0x3f4cc
-#define ixDPM_TABLE_309 0x3f4d0
-#define ixDPM_TABLE_310 0x3f4d4
-#define ixDPM_TABLE_311 0x3f4d8
-#define ixDPM_TABLE_312 0x3f4dc
-#define ixDPM_TABLE_313 0x3f4e0
-#define ixDPM_TABLE_314 0x3f4e4
-#define ixDPM_TABLE_315 0x3f4e8
-#define ixDPM_TABLE_316 0x3f4ec
-#define ixDPM_TABLE_317 0x3f4f0
-#define ixDPM_TABLE_318 0x3f4f4
-#define ixDPM_TABLE_319 0x3f4f8
-#define ixDPM_TABLE_320 0x3f4fc
-#define ixDPM_TABLE_321 0x3f500
-#define ixDPM_TABLE_322 0x3f504
-#define ixDPM_TABLE_323 0x3f508
-#define ixDPM_TABLE_324 0x3f50c
-#define ixDPM_TABLE_325 0x3f510
-#define ixDPM_TABLE_326 0x3f514
-#define ixDPM_TABLE_327 0x3f518
-#define ixDPM_TABLE_328 0x3f51c
-#define ixDPM_TABLE_329 0x3f520
-#define ixDPM_TABLE_330 0x3f524
-#define ixDPM_TABLE_331 0x3f528
-#define ixDPM_TABLE_332 0x3f52c
-#define ixDPM_TABLE_333 0x3f530
-#define ixDPM_TABLE_334 0x3f534
-#define ixDPM_TABLE_335 0x3f538
-#define ixDPM_TABLE_336 0x3f53c
-#define ixDPM_TABLE_337 0x3f540
-#define ixDPM_TABLE_338 0x3f544
-#define ixDPM_TABLE_339 0x3f548
-#define ixDPM_TABLE_340 0x3f54c
-#define ixDPM_TABLE_341 0x3f550
-#define ixDPM_TABLE_342 0x3f554
-#define ixDPM_TABLE_343 0x3f558
-#define ixDPM_TABLE_344 0x3f55c
-#define ixDPM_TABLE_345 0x3f560
-#define ixDPM_TABLE_346 0x3f564
-#define ixDPM_TABLE_347 0x3f568
-#define ixDPM_TABLE_348 0x3f56c
-#define ixDPM_TABLE_349 0x3f570
-#define ixDPM_TABLE_350 0x3f574
-#define ixDPM_TABLE_351 0x3f578
-#define ixDPM_TABLE_352 0x3f57c
-#define ixDPM_TABLE_353 0x3f580
-#define ixDPM_TABLE_354 0x3f584
-#define ixDPM_TABLE_355 0x3f588
-#define ixDPM_TABLE_356 0x3f58c
-#define ixDPM_TABLE_357 0x3f590
-#define ixDPM_TABLE_358 0x3f594
-#define ixDPM_TABLE_359 0x3f598
-#define ixDPM_TABLE_360 0x3f59c
-#define ixDPM_TABLE_361 0x3f5a0
-#define ixDPM_TABLE_362 0x3f5a4
-#define ixDPM_TABLE_363 0x3f5a8
-#define ixDPM_TABLE_364 0x3f5ac
-#define ixDPM_TABLE_365 0x3f5b0
-#define ixDPM_TABLE_366 0x3f5b4
-#define ixDPM_TABLE_367 0x3f5b8
-#define ixDPM_TABLE_368 0x3f5bc
-#define ixDPM_TABLE_369 0x3f5c0
-#define ixDPM_TABLE_370 0x3f5c4
-#define ixDPM_TABLE_371 0x3f5c8
-#define ixDPM_TABLE_372 0x3f5cc
-#define ixDPM_TABLE_373 0x3f5d0
-#define ixDPM_TABLE_374 0x3f5d4
-#define ixDPM_TABLE_375 0x3f5d8
-#define ixDPM_TABLE_376 0x3f5dc
-#define ixDPM_TABLE_377 0x3f5e0
-#define ixDPM_TABLE_378 0x3f5e4
-#define ixDPM_TABLE_379 0x3f5e8
-#define ixDPM_TABLE_380 0x3f5ec
-#define ixDPM_TABLE_381 0x3f5f0
-#define ixDPM_TABLE_382 0x3f5f4
-#define ixDPM_TABLE_383 0x3f5f8
-#define ixDPM_TABLE_384 0x3f5fc
-#define ixDPM_TABLE_385 0x3f600
-#define ixDPM_TABLE_386 0x3f604
-#define ixDPM_TABLE_387 0x3f608
-#define ixDPM_TABLE_388 0x3f60c
-#define ixDPM_TABLE_389 0x3f610
-#define ixDPM_TABLE_390 0x3f614
-#define ixDPM_TABLE_391 0x3f618
-#define ixDPM_TABLE_392 0x3f61c
-#define ixDPM_TABLE_393 0x3f620
-#define ixDPM_TABLE_394 0x3f624
-#define ixDPM_TABLE_395 0x3f628
-#define ixDPM_TABLE_396 0x3f62c
-#define ixDPM_TABLE_397 0x3f630
-#define ixDPM_TABLE_398 0x3f634
-#define ixDPM_TABLE_399 0x3f638
-#define ixDPM_TABLE_400 0x3f63c
-#define ixDPM_TABLE_401 0x3f640
-#define ixDPM_TABLE_402 0x3f644
-#define ixDPM_TABLE_403 0x3f648
-#define ixDPM_TABLE_404 0x3f64c
-#define ixDPM_TABLE_405 0x3f650
-#define ixDPM_TABLE_406 0x3f654
-#define ixDPM_TABLE_407 0x3f658
-#define ixDPM_TABLE_408 0x3f65c
-#define ixDPM_TABLE_409 0x3f660
-#define ixDPM_TABLE_410 0x3f664
-#define ixDPM_TABLE_411 0x3f668
-#define ixDPM_TABLE_412 0x3f66c
-#define ixDPM_TABLE_413 0x3f670
-#define ixDPM_TABLE_414 0x3f674
-#define ixDPM_TABLE_415 0x3f678
-#define ixDPM_TABLE_416 0x3f67c
-#define ixDPM_TABLE_417 0x3f680
-#define ixDPM_TABLE_418 0x3f684
-#define ixDPM_TABLE_419 0x3f688
-#define ixDPM_TABLE_420 0x3f68c
-#define ixDPM_TABLE_421 0x3f690
-#define ixDPM_TABLE_422 0x3f694
-#define ixDPM_TABLE_423 0x3f698
-#define ixDPM_TABLE_424 0x3f69c
-#define ixDPM_TABLE_425 0x3f6a0
-#define ixDPM_TABLE_426 0x3f6a4
-#define ixDPM_TABLE_427 0x3f6a8
-#define ixDPM_TABLE_428 0x3f6ac
-#define ixDPM_TABLE_429 0x3f6b0
-#define ixDPM_TABLE_430 0x3f6b4
-#define ixDPM_TABLE_431 0x3f6b8
-#define ixDPM_TABLE_432 0x3f6bc
-#define ixDPM_TABLE_433 0x3f6c0
-#define ixDPM_TABLE_434 0x3f6c4
-#define ixDPM_TABLE_435 0x3f6c8
-#define ixDPM_TABLE_436 0x3f6cc
-#define ixDPM_TABLE_437 0x3f6d0
-#define ixDPM_TABLE_438 0x3f6d4
-#define ixDPM_TABLE_439 0x3f6d8
-#define ixDPM_TABLE_440 0x3f6dc
-#define ixDPM_TABLE_441 0x3f6e0
-#define ixDPM_TABLE_442 0x3f6e4
-#define ixDPM_TABLE_443 0x3f6e8
-#define ixDPM_TABLE_444 0x3f6ec
-#define ixDPM_TABLE_445 0x3f6f0
-#define ixDPM_TABLE_446 0x3f6f4
-#define ixDPM_TABLE_447 0x3f6f8
-#define ixDPM_TABLE_448 0x3f6fc
-#define ixDPM_TABLE_449 0x3f700
-#define ixDPM_TABLE_450 0x3f704
-#define ixDPM_TABLE_451 0x3f708
-#define ixDPM_TABLE_452 0x3f70c
-#define ixDPM_TABLE_453 0x3f710
-#define ixDPM_TABLE_454 0x3f714
-#define ixDPM_TABLE_455 0x3f718
-#define ixDPM_TABLE_456 0x3f71c
-#define ixDPM_TABLE_457 0x3f720
-#define ixDPM_TABLE_458 0x3f724
-#define ixDPM_TABLE_459 0x3f728
-#define ixDPM_TABLE_460 0x3f72c
-#define ixDPM_TABLE_461 0x3f730
-#define ixDPM_TABLE_462 0x3f734
-#define ixDPM_TABLE_463 0x3f738
-#define ixDPM_TABLE_464 0x3f73c
-#define ixDPM_TABLE_465 0x3f740
-#define ixDPM_TABLE_466 0x3f744
-#define ixDPM_TABLE_467 0x3f748
-#define ixDPM_TABLE_468 0x3f74c
-#define ixDPM_TABLE_469 0x3f750
-#define ixDPM_TABLE_470 0x3f754
-#define ixDPM_TABLE_471 0x3f758
-#define ixDPM_TABLE_472 0x3f75c
-#define ixDPM_TABLE_473 0x3f760
-#define ixDPM_TABLE_474 0x3f764
-#define ixDPM_TABLE_475 0x3f768
-#define ixDPM_TABLE_476 0x3f76c
-#define ixDPM_TABLE_477 0x3f770
-#define ixDPM_TABLE_478 0x3f774
-#define ixDPM_TABLE_479 0x3f778
-#define ixDPM_TABLE_480 0x3f77c
-#define ixDPM_TABLE_481 0x3f780
-#define ixDPM_TABLE_482 0x3f784
-#define ixDPM_TABLE_483 0x3f788
-#define ixDPM_TABLE_484 0x3f78c
-#define ixDPM_TABLE_485 0x3f790
-#define ixDPM_TABLE_486 0x3f794
-#define ixDPM_TABLE_487 0x3f798
-#define ixDPM_TABLE_488 0x3f79c
-#define ixDPM_TABLE_489 0x3f7a0
-#define ixDPM_TABLE_490 0x3f7a4
-#define ixDPM_TABLE_491 0x3f7a8
-#define ixDPM_TABLE_492 0x3f7ac
-#define ixDPM_TABLE_493 0x3f7b0
-#define ixDPM_TABLE_494 0x3f7b4
-#define ixDPM_TABLE_495 0x3f7b8
-#define ixDPM_TABLE_496 0x3f7bc
-#define ixDPM_TABLE_497 0x3f7c0
-#define ixDPM_TABLE_498 0x3f7c4
-#define ixDPM_TABLE_499 0x3f7c8
-#define ixDPM_TABLE_500 0x3f7cc
-#define ixDPM_TABLE_501 0x3f7d0
-#define ixDPM_TABLE_502 0x3f7d4
-#define ixDPM_TABLE_503 0x3f7d8
-#define ixDPM_TABLE_504 0x3f7dc
-#define ixDPM_TABLE_505 0x3f7e0
-#define ixDPM_TABLE_506 0x3f7e4
-#define ixFIRMWARE_FLAGS 0x3f800
-#define ixTDC_STATUS 0x3f808
-#define ixTDC_MV_AVERAGE 0x3f80c
-#define ixTDC_VRM_LIMIT 0x3f810
-#define ixFEATURE_STATUS 0x3f818
-#define ixENTITY_TEMPERATURES_1 0x3f81c
-#define ixMCARB_DRAM_TIMING_TABLE_1 0x3f900
-#define ixMCARB_DRAM_TIMING_TABLE_2 0x3f904
-#define ixMCARB_DRAM_TIMING_TABLE_3 0x3f908
-#define ixMCARB_DRAM_TIMING_TABLE_4 0x3f90c
-#define ixMCARB_DRAM_TIMING_TABLE_5 0x3f910
-#define ixMCARB_DRAM_TIMING_TABLE_6 0x3f914
-#define ixMCARB_DRAM_TIMING_TABLE_7 0x3f918
-#define ixMCARB_DRAM_TIMING_TABLE_8 0x3f91c
-#define ixMCARB_DRAM_TIMING_TABLE_9 0x3f920
-#define ixMCARB_DRAM_TIMING_TABLE_10 0x3f924
-#define ixMCARB_DRAM_TIMING_TABLE_11 0x3f928
-#define ixMCARB_DRAM_TIMING_TABLE_12 0x3f92c
-#define ixMCARB_DRAM_TIMING_TABLE_13 0x3f930
-#define ixMCARB_DRAM_TIMING_TABLE_14 0x3f934
-#define ixMCARB_DRAM_TIMING_TABLE_15 0x3f938
-#define ixMCARB_DRAM_TIMING_TABLE_16 0x3f93c
-#define ixMCARB_DRAM_TIMING_TABLE_17 0x3f940
-#define ixMCARB_DRAM_TIMING_TABLE_18 0x3f944
-#define ixMCARB_DRAM_TIMING_TABLE_19 0x3f948
-#define ixMCARB_DRAM_TIMING_TABLE_20 0x3f94c
-#define ixMCARB_DRAM_TIMING_TABLE_21 0x3f950
-#define ixMCARB_DRAM_TIMING_TABLE_22 0x3f954
-#define ixMCARB_DRAM_TIMING_TABLE_23 0x3f958
-#define ixMCARB_DRAM_TIMING_TABLE_24 0x3f95c
-#define ixMCARB_DRAM_TIMING_TABLE_25 0x3f960
-#define ixMCARB_DRAM_TIMING_TABLE_26 0x3f964
-#define ixMCARB_DRAM_TIMING_TABLE_27 0x3f968
-#define ixMCARB_DRAM_TIMING_TABLE_28 0x3f96c
-#define ixMCARB_DRAM_TIMING_TABLE_29 0x3f970
-#define ixMCARB_DRAM_TIMING_TABLE_30 0x3f974
-#define ixMCARB_DRAM_TIMING_TABLE_31 0x3f978
-#define ixMCARB_DRAM_TIMING_TABLE_32 0x3f97c
-#define ixMCARB_DRAM_TIMING_TABLE_33 0x3f980
-#define ixMCARB_DRAM_TIMING_TABLE_34 0x3f984
-#define ixMCARB_DRAM_TIMING_TABLE_35 0x3f988
-#define ixMCARB_DRAM_TIMING_TABLE_36 0x3f98c
-#define ixMCARB_DRAM_TIMING_TABLE_37 0x3f990
-#define ixMCARB_DRAM_TIMING_TABLE_38 0x3f994
-#define ixMCARB_DRAM_TIMING_TABLE_39 0x3f998
-#define ixMCARB_DRAM_TIMING_TABLE_40 0x3f99c
-#define ixMCARB_DRAM_TIMING_TABLE_41 0x3f9a0
-#define ixMCARB_DRAM_TIMING_TABLE_42 0x3f9a4
-#define ixMCARB_DRAM_TIMING_TABLE_43 0x3f9a8
-#define ixMCARB_DRAM_TIMING_TABLE_44 0x3f9ac
-#define ixMCARB_DRAM_TIMING_TABLE_45 0x3f9b0
-#define ixMCARB_DRAM_TIMING_TABLE_46 0x3f9b4
-#define ixMCARB_DRAM_TIMING_TABLE_47 0x3f9b8
-#define ixMCARB_DRAM_TIMING_TABLE_48 0x3f9bc
-#define ixMCARB_DRAM_TIMING_TABLE_49 0x3f9c0
-#define ixMCARB_DRAM_TIMING_TABLE_50 0x3f9c4
-#define ixMCARB_DRAM_TIMING_TABLE_51 0x3f9c8
-#define ixMCARB_DRAM_TIMING_TABLE_52 0x3f9cc
-#define ixMCARB_DRAM_TIMING_TABLE_53 0x3f9d0
-#define ixMCARB_DRAM_TIMING_TABLE_54 0x3f9d4
-#define ixMCARB_DRAM_TIMING_TABLE_55 0x3f9d8
-#define ixMCARB_DRAM_TIMING_TABLE_56 0x3f9dc
-#define ixMCARB_DRAM_TIMING_TABLE_57 0x3f9e0
-#define ixMCARB_DRAM_TIMING_TABLE_58 0x3f9e4
-#define ixMCARB_DRAM_TIMING_TABLE_59 0x3f9e8
-#define ixMCARB_DRAM_TIMING_TABLE_60 0x3f9ec
-#define ixMCARB_DRAM_TIMING_TABLE_61 0x3f9f0
-#define ixMCARB_DRAM_TIMING_TABLE_62 0x3f9f4
-#define ixMCARB_DRAM_TIMING_TABLE_63 0x3f9f8
-#define ixMCARB_DRAM_TIMING_TABLE_64 0x3f9fc
-#define ixMCARB_DRAM_TIMING_TABLE_65 0x3fa00
-#define ixMCARB_DRAM_TIMING_TABLE_66 0x3fa04
-#define ixMCARB_DRAM_TIMING_TABLE_67 0x3fa08
-#define ixMCARB_DRAM_TIMING_TABLE_68 0x3fa0c
-#define ixMCARB_DRAM_TIMING_TABLE_69 0x3fa10
-#define ixMCARB_DRAM_TIMING_TABLE_70 0x3fa14
-#define ixMCARB_DRAM_TIMING_TABLE_71 0x3fa18
-#define ixMCARB_DRAM_TIMING_TABLE_72 0x3fa1c
-#define ixMCARB_DRAM_TIMING_TABLE_73 0x3fa20
-#define ixMCARB_DRAM_TIMING_TABLE_74 0x3fa24
-#define ixMCARB_DRAM_TIMING_TABLE_75 0x3fa28
-#define ixMCARB_DRAM_TIMING_TABLE_76 0x3fa2c
-#define ixMCARB_DRAM_TIMING_TABLE_77 0x3fa30
-#define ixMCARB_DRAM_TIMING_TABLE_78 0x3fa34
-#define ixMCARB_DRAM_TIMING_TABLE_79 0x3fa38
-#define ixMCARB_DRAM_TIMING_TABLE_80 0x3fa3c
-#define ixMCARB_DRAM_TIMING_TABLE_81 0x3fa40
-#define ixMCARB_DRAM_TIMING_TABLE_82 0x3fa44
-#define ixMCARB_DRAM_TIMING_TABLE_83 0x3fa48
-#define ixMCARB_DRAM_TIMING_TABLE_84 0x3fa4c
-#define ixMCARB_DRAM_TIMING_TABLE_85 0x3fa50
-#define ixMCARB_DRAM_TIMING_TABLE_86 0x3fa54
-#define ixMCARB_DRAM_TIMING_TABLE_87 0x3fa58
-#define ixMCARB_DRAM_TIMING_TABLE_88 0x3fa5c
-#define ixMCARB_DRAM_TIMING_TABLE_89 0x3fa60
-#define ixMCARB_DRAM_TIMING_TABLE_90 0x3fa64
-#define ixMCARB_DRAM_TIMING_TABLE_91 0x3fa68
-#define ixMCARB_DRAM_TIMING_TABLE_92 0x3fa6c
-#define ixMCARB_DRAM_TIMING_TABLE_93 0x3fa70
-#define ixMCARB_DRAM_TIMING_TABLE_94 0x3fa74
-#define ixMCARB_DRAM_TIMING_TABLE_95 0x3fa78
-#define ixMCARB_DRAM_TIMING_TABLE_96 0x3fa7c
-#define ixMCARB_DRAM_TIMING_TABLE_97 0x3fa80
-#define ixMCARB_DRAM_TIMING_TABLE_98 0x3fa84
-#define ixMCARB_DRAM_TIMING_TABLE_99 0x3fa88
-#define ixMCARB_DRAM_TIMING_TABLE_100 0x3fa8c
-#define ixMCARB_DRAM_TIMING_TABLE_101 0x3fa90
-#define ixMCARB_DRAM_TIMING_TABLE_102 0x3fa94
-#define ixMCARB_DRAM_TIMING_TABLE_103 0x3fa98
-#define ixMCARB_DRAM_TIMING_TABLE_104 0x3fa9c
-#define ixMCARB_DRAM_TIMING_TABLE_105 0x3faa0
-#define ixMCARB_DRAM_TIMING_TABLE_106 0x3faa4
-#define ixMCARB_DRAM_TIMING_TABLE_107 0x3faa8
-#define ixMCARB_DRAM_TIMING_TABLE_108 0x3faac
-#define ixMCARB_DRAM_TIMING_TABLE_109 0x3fab0
-#define ixMCARB_DRAM_TIMING_TABLE_110 0x3fab4
-#define ixMCARB_DRAM_TIMING_TABLE_111 0x3fab8
-#define ixMCARB_DRAM_TIMING_TABLE_112 0x3fabc
-#define ixMCARB_DRAM_TIMING_TABLE_113 0x3fac0
-#define ixMCARB_DRAM_TIMING_TABLE_114 0x3fac4
-#define ixMCARB_DRAM_TIMING_TABLE_115 0x3fac8
-#define ixMCARB_DRAM_TIMING_TABLE_116 0x3facc
-#define ixMCARB_DRAM_TIMING_TABLE_117 0x3fad0
-#define ixMCARB_DRAM_TIMING_TABLE_118 0x3fad4
-#define ixMCARB_DRAM_TIMING_TABLE_119 0x3fad8
-#define ixMCARB_DRAM_TIMING_TABLE_120 0x3fadc
-#define ixMCARB_DRAM_TIMING_TABLE_121 0x3fae0
-#define ixMCARB_DRAM_TIMING_TABLE_122 0x3fae4
-#define ixMCARB_DRAM_TIMING_TABLE_123 0x3fae8
-#define ixMCARB_DRAM_TIMING_TABLE_124 0x3faec
-#define ixMCARB_DRAM_TIMING_TABLE_125 0x3faf0
-#define ixMCARB_DRAM_TIMING_TABLE_126 0x3faf4
-#define ixMCARB_DRAM_TIMING_TABLE_127 0x3faf8
-#define ixMCARB_DRAM_TIMING_TABLE_128 0x3fafc
-#define ixMCARB_DRAM_TIMING_TABLE_129 0x3fb00
-#define ixMCARB_DRAM_TIMING_TABLE_130 0x3fb04
-#define ixMCARB_DRAM_TIMING_TABLE_131 0x3fb08
-#define ixMCARB_DRAM_TIMING_TABLE_132 0x3fb0c
-#define ixMCARB_DRAM_TIMING_TABLE_133 0x3fb10
-#define ixMCARB_DRAM_TIMING_TABLE_134 0x3fb14
-#define ixMCARB_DRAM_TIMING_TABLE_135 0x3fb18
-#define ixMCARB_DRAM_TIMING_TABLE_136 0x3fb1c
-#define ixMCARB_DRAM_TIMING_TABLE_137 0x3fb20
-#define ixMCARB_DRAM_TIMING_TABLE_138 0x3fb24
-#define ixMCARB_DRAM_TIMING_TABLE_139 0x3fb28
-#define ixMCARB_DRAM_TIMING_TABLE_140 0x3fb2c
-#define ixMCARB_DRAM_TIMING_TABLE_141 0x3fb30
-#define ixMCARB_DRAM_TIMING_TABLE_142 0x3fb34
-#define ixMCARB_DRAM_TIMING_TABLE_143 0x3fb38
-#define ixMCARB_DRAM_TIMING_TABLE_144 0x3fb3c
-#define ixMC_REGISTERS_TABLE_1 0x3fb40
-#define ixMC_REGISTERS_TABLE_2 0x3fb44
-#define ixMC_REGISTERS_TABLE_3 0x3fb48
-#define ixMC_REGISTERS_TABLE_4 0x3fb4c
-#define ixMC_REGISTERS_TABLE_5 0x3fb50
-#define ixMC_REGISTERS_TABLE_6 0x3fb54
-#define ixMC_REGISTERS_TABLE_7 0x3fb58
-#define ixMC_REGISTERS_TABLE_8 0x3fb5c
-#define ixMC_REGISTERS_TABLE_9 0x3fb60
-#define ixMC_REGISTERS_TABLE_10 0x3fb64
-#define ixMC_REGISTERS_TABLE_11 0x3fb68
-#define ixMC_REGISTERS_TABLE_12 0x3fb6c
-#define ixMC_REGISTERS_TABLE_13 0x3fb70
-#define ixMC_REGISTERS_TABLE_14 0x3fb74
-#define ixMC_REGISTERS_TABLE_15 0x3fb78
-#define ixMC_REGISTERS_TABLE_16 0x3fb7c
-#define ixMC_REGISTERS_TABLE_17 0x3fb80
-#define ixMC_REGISTERS_TABLE_18 0x3fb84
-#define ixMC_REGISTERS_TABLE_19 0x3fb88
-#define ixMC_REGISTERS_TABLE_20 0x3fb8c
-#define ixMC_REGISTERS_TABLE_21 0x3fb90
-#define ixMC_REGISTERS_TABLE_22 0x3fb94
-#define ixMC_REGISTERS_TABLE_23 0x3fb98
-#define ixMC_REGISTERS_TABLE_24 0x3fb9c
-#define ixMC_REGISTERS_TABLE_25 0x3fba0
-#define ixMC_REGISTERS_TABLE_26 0x3fba4
-#define ixMC_REGISTERS_TABLE_27 0x3fba8
-#define ixMC_REGISTERS_TABLE_28 0x3fbac
-#define ixMC_REGISTERS_TABLE_29 0x3fbb0
-#define ixMC_REGISTERS_TABLE_30 0x3fbb4
-#define ixMC_REGISTERS_TABLE_31 0x3fbb8
-#define ixMC_REGISTERS_TABLE_32 0x3fbbc
-#define ixMC_REGISTERS_TABLE_33 0x3fbc0
-#define ixMC_REGISTERS_TABLE_34 0x3fbc4
-#define ixMC_REGISTERS_TABLE_35 0x3fbc8
-#define ixMC_REGISTERS_TABLE_36 0x3fbcc
-#define ixMC_REGISTERS_TABLE_37 0x3fbd0
-#define ixMC_REGISTERS_TABLE_38 0x3fbd4
-#define ixMC_REGISTERS_TABLE_39 0x3fbd8
-#define ixMC_REGISTERS_TABLE_40 0x3fbdc
-#define ixMC_REGISTERS_TABLE_41 0x3fbe0
-#define ixMC_REGISTERS_TABLE_42 0x3fbe4
-#define ixMC_REGISTERS_TABLE_43 0x3fbe8
-#define ixMC_REGISTERS_TABLE_44 0x3fbec
-#define ixMC_REGISTERS_TABLE_45 0x3fbf0
-#define ixMC_REGISTERS_TABLE_46 0x3fbf4
-#define ixMC_REGISTERS_TABLE_47 0x3fbf8
-#define ixMC_REGISTERS_TABLE_48 0x3fbfc
-#define ixMC_REGISTERS_TABLE_49 0x3fc00
-#define ixMC_REGISTERS_TABLE_50 0x3fc04
-#define ixMC_REGISTERS_TABLE_51 0x3fc08
-#define ixMC_REGISTERS_TABLE_52 0x3fc0c
-#define ixMC_REGISTERS_TABLE_53 0x3fc10
-#define ixMC_REGISTERS_TABLE_54 0x3fc14
-#define ixMC_REGISTERS_TABLE_55 0x3fc18
-#define ixMC_REGISTERS_TABLE_56 0x3fc1c
-#define ixMC_REGISTERS_TABLE_57 0x3fc20
-#define ixMC_REGISTERS_TABLE_58 0x3fc24
-#define ixMC_REGISTERS_TABLE_59 0x3fc28
-#define ixMC_REGISTERS_TABLE_60 0x3fc2c
-#define ixMC_REGISTERS_TABLE_61 0x3fc30
-#define ixMC_REGISTERS_TABLE_62 0x3fc34
-#define ixMC_REGISTERS_TABLE_63 0x3fc38
-#define ixMC_REGISTERS_TABLE_64 0x3fc3c
-#define ixMC_REGISTERS_TABLE_65 0x3fc40
-#define ixMC_REGISTERS_TABLE_66 0x3fc44
-#define ixMC_REGISTERS_TABLE_67 0x3fc48
-#define ixMC_REGISTERS_TABLE_68 0x3fc4c
-#define ixMC_REGISTERS_TABLE_69 0x3fc50
-#define ixMC_REGISTERS_TABLE_70 0x3fc54
-#define ixMC_REGISTERS_TABLE_71 0x3fc58
-#define ixMC_REGISTERS_TABLE_72 0x3fc5c
-#define ixMC_REGISTERS_TABLE_73 0x3fc60
-#define ixMC_REGISTERS_TABLE_74 0x3fc64
-#define ixMC_REGISTERS_TABLE_75 0x3fc68
-#define ixMC_REGISTERS_TABLE_76 0x3fc6c
-#define ixMC_REGISTERS_TABLE_77 0x3fc70
-#define ixMC_REGISTERS_TABLE_78 0x3fc74
-#define ixMC_REGISTERS_TABLE_79 0x3fc78
-#define ixMC_REGISTERS_TABLE_80 0x3fc7c
-#define ixMC_REGISTERS_TABLE_81 0x3fc80
-#define ixMC_REGISTERS_TABLE_82 0x3fc84
-#define ixMC_REGISTERS_TABLE_83 0x3fc88
-#define ixMC_REGISTERS_TABLE_84 0x3fc8c
-#define ixMC_REGISTERS_TABLE_85 0x3fc90
-#define ixMC_REGISTERS_TABLE_86 0x3fc94
-#define ixMC_REGISTERS_TABLE_87 0x3fc98
-#define ixMC_REGISTERS_TABLE_88 0x3fc9c
-#define ixMC_REGISTERS_TABLE_89 0x3fca0
-#define ixMC_REGISTERS_TABLE_90 0x3fca4
-#define ixMC_REGISTERS_TABLE_91 0x3fca8
-#define ixMC_REGISTERS_TABLE_92 0x3fcac
-#define ixMC_REGISTERS_TABLE_93 0x3fcb0
-#define ixMC_REGISTERS_TABLE_94 0x3fcb4
-#define ixMC_REGISTERS_TABLE_95 0x3fcb8
-#define ixMC_REGISTERS_TABLE_96 0x3fcbc
-#define ixMC_REGISTERS_TABLE_97 0x3fcc0
-#define ixMC_REGISTERS_TABLE_98 0x3fcc4
-#define ixMC_REGISTERS_TABLE_99 0x3fcc8
-#define ixMC_REGISTERS_TABLE_100 0x3fccc
-#define ixMC_REGISTERS_TABLE_101 0x3fcd0
-#define ixMC_REGISTERS_TABLE_102 0x3fcd4
-#define ixMC_REGISTERS_TABLE_103 0x3fcd8
-#define ixMC_REGISTERS_TABLE_104 0x3fcdc
-#define ixMC_REGISTERS_TABLE_105 0x3fce0
-#define ixMC_REGISTERS_TABLE_106 0x3fce4
-#define ixMC_REGISTERS_TABLE_107 0x3fce8
-#define ixMC_REGISTERS_TABLE_108 0x3fcec
-#define ixMC_REGISTERS_TABLE_109 0x3fcf0
-#define ixMC_REGISTERS_TABLE_110 0x3fcf4
-#define ixMC_REGISTERS_TABLE_111 0x3fcf8
-#define ixMC_REGISTERS_TABLE_112 0x3fcfc
-#define ixMC_REGISTERS_TABLE_113 0x3fd00
-#define ixFAN_TABLE_1 0x3fd04
-#define ixFAN_TABLE_2 0x3fd08
-#define ixFAN_TABLE_3 0x3fd0c
-#define ixFAN_TABLE_4 0x3fd10
-#define ixFAN_TABLE_5 0x3fd14
-#define ixFAN_TABLE_6 0x3fd18
-#define ixFAN_TABLE_7 0x3fd1c
-#define ixFAN_TABLE_8 0x3fd20
-#define ixFAN_TABLE_9 0x3fd24
-#define ixSOFT_REGISTERS_TABLE_1 0x3fd28
-#define ixSOFT_REGISTERS_TABLE_2 0x3fd2c
-#define ixSOFT_REGISTERS_TABLE_3 0x3fd30
-#define ixSOFT_REGISTERS_TABLE_4 0x3fd34
-#define ixSOFT_REGISTERS_TABLE_5 0x3fd38
-#define ixSOFT_REGISTERS_TABLE_6 0x3fd3c
-#define ixSOFT_REGISTERS_TABLE_7 0x3fd40
-#define ixSOFT_REGISTERS_TABLE_8 0x3fd44
-#define ixSOFT_REGISTERS_TABLE_9 0x3fd48
-#define ixSOFT_REGISTERS_TABLE_10 0x3fd4c
-#define ixSOFT_REGISTERS_TABLE_11 0x3fd50
-#define ixSOFT_REGISTERS_TABLE_12 0x3fd54
-#define ixSOFT_REGISTERS_TABLE_13 0x3fd58
-#define ixSOFT_REGISTERS_TABLE_14 0x3fd5c
-#define ixSOFT_REGISTERS_TABLE_15 0x3fd60
-#define ixSOFT_REGISTERS_TABLE_16 0x3fd64
-#define ixSOFT_REGISTERS_TABLE_17 0x3fd68
-#define ixSOFT_REGISTERS_TABLE_18 0x3fd6c
-#define ixSOFT_REGISTERS_TABLE_19 0x3fd70
-#define ixSOFT_REGISTERS_TABLE_20 0x3fd74
-#define ixSOFT_REGISTERS_TABLE_21 0x3fd78
-#define ixSOFT_REGISTERS_TABLE_22 0x3fd7c
-#define ixSOFT_REGISTERS_TABLE_23 0x3fd80
-#define ixSOFT_REGISTERS_TABLE_24 0x3fd84
-#define ixSOFT_REGISTERS_TABLE_25 0x3fd88
-#define ixSOFT_REGISTERS_TABLE_26 0x3fd8c
-#define ixSOFT_REGISTERS_TABLE_27 0x3fd90
-#define ixSOFT_REGISTERS_TABLE_28 0x3fd94
-#define ixSOFT_REGISTERS_TABLE_29 0x3fd98
-#define ixSOFT_REGISTERS_TABLE_30 0x3fd9c
-#define ixPM_FUSES_1 0x3fda0
-#define ixPM_FUSES_2 0x3fda4
-#define ixPM_FUSES_3 0x3fda8
-#define ixPM_FUSES_4 0x3fdac
-#define ixPM_FUSES_5 0x3fdb0
-#define ixPM_FUSES_6 0x3fdb4
-#define ixPM_FUSES_7 0x3fdb8
-#define ixPM_FUSES_8 0x3fdbc
-#define ixPM_FUSES_9 0x3fdc0
-#define ixPM_FUSES_10 0x3fdc4
-#define ixPM_FUSES_11 0x3fdc8
-#define ixPM_FUSES_12 0x3fdcc
-#define ixPM_FUSES_13 0x3fdd0
-#define ixPM_FUSES_14 0x3fdd4
-#define ixPM_FUSES_15 0x3fdd8
-#define ixPM_FUSES_16 0x3fddc
-#define ixPM_FUSES_17 0x3fde0
-#define ixPM_FUSES_18 0x3fde4
-#define ixPM_FUSES_19 0x3fde8
-#define ixSMU_PM_STATUS_0 0x3fe00
-#define ixSMU_PM_STATUS_1 0x3fe04
-#define ixSMU_PM_STATUS_2 0x3fe08
-#define ixSMU_PM_STATUS_3 0x3fe0c
-#define ixSMU_PM_STATUS_4 0x3fe10
-#define ixSMU_PM_STATUS_5 0x3fe14
-#define ixSMU_PM_STATUS_6 0x3fe18
-#define ixSMU_PM_STATUS_7 0x3fe1c
-#define ixSMU_PM_STATUS_8 0x3fe20
-#define ixSMU_PM_STATUS_9 0x3fe24
-#define ixSMU_PM_STATUS_10 0x3fe28
-#define ixSMU_PM_STATUS_11 0x3fe2c
-#define ixSMU_PM_STATUS_12 0x3fe30
-#define ixSMU_PM_STATUS_13 0x3fe34
-#define ixSMU_PM_STATUS_14 0x3fe38
-#define ixSMU_PM_STATUS_15 0x3fe3c
-#define ixSMU_PM_STATUS_16 0x3fe40
-#define ixSMU_PM_STATUS_17 0x3fe44
-#define ixSMU_PM_STATUS_18 0x3fe48
-#define ixSMU_PM_STATUS_19 0x3fe4c
-#define ixSMU_PM_STATUS_20 0x3fe50
-#define ixSMU_PM_STATUS_21 0x3fe54
-#define ixSMU_PM_STATUS_22 0x3fe58
-#define ixSMU_PM_STATUS_23 0x3fe5c
-#define ixSMU_PM_STATUS_24 0x3fe60
-#define ixSMU_PM_STATUS_25 0x3fe64
-#define ixSMU_PM_STATUS_26 0x3fe68
-#define ixSMU_PM_STATUS_27 0x3fe6c
-#define ixSMU_PM_STATUS_28 0x3fe70
-#define ixSMU_PM_STATUS_29 0x3fe74
-#define ixSMU_PM_STATUS_30 0x3fe78
-#define ixSMU_PM_STATUS_31 0x3fe7c
-#define ixSMU_PM_STATUS_32 0x3fe80
-#define ixSMU_PM_STATUS_33 0x3fe84
-#define ixSMU_PM_STATUS_34 0x3fe88
-#define ixSMU_PM_STATUS_35 0x3fe8c
-#define ixSMU_PM_STATUS_36 0x3fe90
-#define ixSMU_PM_STATUS_37 0x3fe94
-#define ixSMU_PM_STATUS_38 0x3fe98
-#define ixSMU_PM_STATUS_39 0x3fe9c
-#define ixSMU_PM_STATUS_40 0x3fea0
-#define ixSMU_PM_STATUS_41 0x3fea4
-#define ixSMU_PM_STATUS_42 0x3fea8
-#define ixSMU_PM_STATUS_43 0x3feac
-#define ixSMU_PM_STATUS_44 0x3feb0
-#define ixSMU_PM_STATUS_45 0x3feb4
-#define ixSMU_PM_STATUS_46 0x3feb8
-#define ixSMU_PM_STATUS_47 0x3febc
-#define ixSMU_PM_STATUS_48 0x3fec0
-#define ixSMU_PM_STATUS_49 0x3fec4
-#define ixSMU_PM_STATUS_50 0x3fec8
-#define ixSMU_PM_STATUS_51 0x3fecc
-#define ixSMU_PM_STATUS_52 0x3fed0
-#define ixSMU_PM_STATUS_53 0x3fed4
-#define ixSMU_PM_STATUS_54 0x3fed8
-#define ixSMU_PM_STATUS_55 0x3fedc
-#define ixSMU_PM_STATUS_56 0x3fee0
-#define ixSMU_PM_STATUS_57 0x3fee4
-#define ixSMU_PM_STATUS_58 0x3fee8
-#define ixSMU_PM_STATUS_59 0x3feec
-#define ixSMU_PM_STATUS_60 0x3fef0
-#define ixSMU_PM_STATUS_61 0x3fef4
-#define ixSMU_PM_STATUS_62 0x3fef8
-#define ixSMU_PM_STATUS_63 0x3fefc
-#define ixSMU_PM_STATUS_64 0x3ff00
-#define ixSMU_PM_STATUS_65 0x3ff04
-#define ixSMU_PM_STATUS_66 0x3ff08
-#define ixSMU_PM_STATUS_67 0x3ff0c
-#define ixSMU_PM_STATUS_68 0x3ff10
-#define ixSMU_PM_STATUS_69 0x3ff14
-#define ixSMU_PM_STATUS_70 0x3ff18
-#define ixSMU_PM_STATUS_71 0x3ff1c
-#define ixSMU_PM_STATUS_72 0x3ff20
-#define ixSMU_PM_STATUS_73 0x3ff24
-#define ixSMU_PM_STATUS_74 0x3ff28
-#define ixSMU_PM_STATUS_75 0x3ff2c
-#define ixSMU_PM_STATUS_76 0x3ff30
-#define ixSMU_PM_STATUS_77 0x3ff34
-#define ixSMU_PM_STATUS_78 0x3ff38
-#define ixSMU_PM_STATUS_79 0x3ff3c
-#define ixSMU_PM_STATUS_80 0x3ff40
-#define ixSMU_PM_STATUS_81 0x3ff44
-#define ixSMU_PM_STATUS_82 0x3ff48
-#define ixSMU_PM_STATUS_83 0x3ff4c
-#define ixSMU_PM_STATUS_84 0x3ff50
-#define ixSMU_PM_STATUS_85 0x3ff54
-#define ixSMU_PM_STATUS_86 0x3ff58
-#define ixSMU_PM_STATUS_87 0x3ff5c
-#define ixSMU_PM_STATUS_88 0x3ff60
-#define ixSMU_PM_STATUS_89 0x3ff64
-#define ixSMU_PM_STATUS_90 0x3ff68
-#define ixSMU_PM_STATUS_91 0x3ff6c
-#define ixSMU_PM_STATUS_92 0x3ff70
-#define ixSMU_PM_STATUS_93 0x3ff74
-#define ixSMU_PM_STATUS_94 0x3ff78
-#define ixSMU_PM_STATUS_95 0x3ff7c
-#define ixSMU_PM_STATUS_96 0x3ff80
-#define ixSMU_PM_STATUS_97 0x3ff84
-#define ixSMU_PM_STATUS_98 0x3ff88
-#define ixSMU_PM_STATUS_99 0x3ff8c
-#define ixSMU_PM_STATUS_100 0x3ff90
-#define ixSMU_PM_STATUS_101 0x3ff94
-#define ixSMU_PM_STATUS_102 0x3ff98
-#define ixSMU_PM_STATUS_103 0x3ff9c
-#define ixSMU_PM_STATUS_104 0x3ffa0
-#define ixSMU_PM_STATUS_105 0x3ffa4
-#define ixSMU_PM_STATUS_106 0x3ffa8
-#define ixSMU_PM_STATUS_107 0x3ffac
-#define ixSMU_PM_STATUS_108 0x3ffb0
-#define ixSMU_PM_STATUS_109 0x3ffb4
-#define ixSMU_PM_STATUS_110 0x3ffb8
-#define ixSMU_PM_STATUS_111 0x3ffbc
-#define ixSMU_PM_STATUS_112 0x3ffc0
-#define ixSMU_PM_STATUS_113 0x3ffc4
-#define ixSMU_PM_STATUS_114 0x3ffc8
-#define ixSMU_PM_STATUS_115 0x3ffcc
-#define ixSMU_PM_STATUS_116 0x3ffd0
-#define ixSMU_PM_STATUS_117 0x3ffd4
-#define ixSMU_PM_STATUS_118 0x3ffd8
-#define ixSMU_PM_STATUS_119 0x3ffdc
-#define ixSMU_PM_STATUS_120 0x3ffe0
-#define ixSMU_PM_STATUS_121 0x3ffe4
-#define ixSMU_PM_STATUS_122 0x3ffe8
-#define ixSMU_PM_STATUS_123 0x3ffec
-#define ixSMU_PM_STATUS_124 0x3fff0
-#define ixSMU_PM_STATUS_125 0x3fff4
-#define ixSMU_PM_STATUS_126 0x3fff8
-#define ixSMU_PM_STATUS_127 0x3fffc
-#define ixCG_THERMAL_INT_ENA 0xc2100024
-#define ixCG_THERMAL_INT_CTRL 0xc2100028
-#define ixCG_THERMAL_INT_STATUS 0xc210002c
-#define ixCG_THERMAL_CTRL 0xc0300004
-#define ixCG_THERMAL_STATUS 0xc0300008
-#define ixCG_THERMAL_INT 0xc030000c
-#define ixCG_MULT_THERMAL_CTRL 0xc0300010
-#define ixCG_MULT_THERMAL_STATUS 0xc0300014
-#define ixCG_FDO_CTRL0 0xc0300064
-#define ixCG_FDO_CTRL1 0xc0300068
-#define ixCG_FDO_CTRL2 0xc030006c
-#define ixCG_TACH_CTRL 0xc0300070
-#define ixCG_TACH_STATUS 0xc0300074
-#define ixCC_THM_STRAPS0 0xc0300080
-#define ixTHM_TMON0_RDIL0_DATA 0xc0300100
-#define ixTHM_TMON0_RDIL1_DATA 0xc0300104
-#define ixTHM_TMON0_RDIL2_DATA 0xc0300108
-#define ixTHM_TMON0_RDIL3_DATA 0xc030010c
-#define ixTHM_TMON0_RDIL4_DATA 0xc0300110
-#define ixTHM_TMON0_RDIL5_DATA 0xc0300114
-#define ixTHM_TMON0_RDIL6_DATA 0xc0300118
-#define ixTHM_TMON0_RDIL7_DATA 0xc030011c
-#define ixTHM_TMON0_RDIL8_DATA 0xc0300120
-#define ixTHM_TMON0_RDIL9_DATA 0xc0300124
-#define ixTHM_TMON0_RDIL10_DATA 0xc0300128
-#define ixTHM_TMON0_RDIL11_DATA 0xc030012c
-#define ixTHM_TMON0_RDIL12_DATA 0xc0300130
-#define ixTHM_TMON0_RDIL13_DATA 0xc0300134
-#define ixTHM_TMON0_RDIL14_DATA 0xc0300138
-#define ixTHM_TMON0_RDIL15_DATA 0xc030013c
-#define ixTHM_TMON0_RDIR0_DATA 0xc0300140
-#define ixTHM_TMON0_RDIR1_DATA 0xc0300144
-#define ixTHM_TMON0_RDIR2_DATA 0xc0300148
-#define ixTHM_TMON0_RDIR3_DATA 0xc030014c
-#define ixTHM_TMON0_RDIR4_DATA 0xc0300150
-#define ixTHM_TMON0_RDIR5_DATA 0xc0300154
-#define ixTHM_TMON0_RDIR6_DATA 0xc0300158
-#define ixTHM_TMON0_RDIR7_DATA 0xc030015c
-#define ixTHM_TMON0_RDIR8_DATA 0xc0300160
-#define ixTHM_TMON0_RDIR9_DATA 0xc0300164
-#define ixTHM_TMON0_RDIR10_DATA 0xc0300168
-#define ixTHM_TMON0_RDIR11_DATA 0xc030016c
-#define ixTHM_TMON0_RDIR12_DATA 0xc0300170
-#define ixTHM_TMON0_RDIR13_DATA 0xc0300174
-#define ixTHM_TMON0_RDIR14_DATA 0xc0300178
-#define ixTHM_TMON0_RDIR15_DATA 0xc030017c
-#define ixTHM_TMON1_RDIL0_DATA 0xc0300180
-#define ixTHM_TMON1_RDIL1_DATA 0xc0300184
-#define ixTHM_TMON1_RDIL2_DATA 0xc0300188
-#define ixTHM_TMON1_RDIL3_DATA 0xc030018c
-#define ixTHM_TMON1_RDIL4_DATA 0xc0300190
-#define ixTHM_TMON1_RDIL5_DATA 0xc0300194
-#define ixTHM_TMON1_RDIL6_DATA 0xc0300198
-#define ixTHM_TMON1_RDIL7_DATA 0xc030019c
-#define ixTHM_TMON1_RDIL8_DATA 0xc03001a0
-#define ixTHM_TMON1_RDIL9_DATA 0xc03001a4
-#define ixTHM_TMON1_RDIL10_DATA 0xc03001a8
-#define ixTHM_TMON1_RDIL11_DATA 0xc03001ac
-#define ixTHM_TMON1_RDIL12_DATA 0xc03001b0
-#define ixTHM_TMON1_RDIL13_DATA 0xc03001b4
-#define ixTHM_TMON1_RDIL14_DATA 0xc03001b8
-#define ixTHM_TMON1_RDIL15_DATA 0xc03001bc
-#define ixTHM_TMON1_RDIR0_DATA 0xc03001c0
-#define ixTHM_TMON1_RDIR1_DATA 0xc03001c4
-#define ixTHM_TMON1_RDIR2_DATA 0xc03001c8
-#define ixTHM_TMON1_RDIR3_DATA 0xc03001cc
-#define ixTHM_TMON1_RDIR4_DATA 0xc03001d0
-#define ixTHM_TMON1_RDIR5_DATA 0xc03001d4
-#define ixTHM_TMON1_RDIR6_DATA 0xc03001d8
-#define ixTHM_TMON1_RDIR7_DATA 0xc03001dc
-#define ixTHM_TMON1_RDIR8_DATA 0xc03001e0
-#define ixTHM_TMON1_RDIR9_DATA 0xc03001e4
-#define ixTHM_TMON1_RDIR10_DATA 0xc03001e8
-#define ixTHM_TMON1_RDIR11_DATA 0xc03001ec
-#define ixTHM_TMON1_RDIR12_DATA 0xc03001f0
-#define ixTHM_TMON1_RDIR13_DATA 0xc03001f4
-#define ixTHM_TMON1_RDIR14_DATA 0xc03001f8
-#define ixTHM_TMON1_RDIR15_DATA 0xc03001fc
-#define ixTHM_TMON0_INT_DATA 0xc0300300
-#define ixTHM_TMON1_INT_DATA 0xc0300304
-#define ixTHM_TMON0_DEBUG 0xc0300310
-#define ixTHM_TMON1_DEBUG 0xc0300314
-#define ixGENERAL_PWRMGT 0xc0200000
-#define ixCNB_PWRMGT_CNTL 0xc0200004
-#define ixSCLK_PWRMGT_CNTL 0xc0200008
-#define ixTARGET_AND_CURRENT_PROFILE_INDEX 0xc0200014
-#define ixCG_FREQ_TRAN_VOTING_0 0xc02001a8
-#define ixCG_FREQ_TRAN_VOTING_1 0xc02001ac
-#define ixCG_FREQ_TRAN_VOTING_2 0xc02001b0
-#define ixCG_FREQ_TRAN_VOTING_3 0xc02001b4
-#define ixCG_FREQ_TRAN_VOTING_4 0xc02001b8
-#define ixCG_FREQ_TRAN_VOTING_5 0xc02001bc
-#define ixCG_FREQ_TRAN_VOTING_6 0xc02001c0
-#define ixCG_FREQ_TRAN_VOTING_7 0xc02001c4
-#define ixPLL_TEST_CNTL 0xc020003c
-#define ixCG_STATIC_SCREEN_PARAMETER 0xc0200044
-#define ixCG_DISPLAY_GAP_CNTL 0xc0200060
-#define ixCG_DISPLAY_GAP_CNTL2 0xc0200230
-#define ixCG_ACPI_CNTL 0xc0200064
-#define ixSCLK_DEEP_SLEEP_CNTL 0xc0200080
-#define ixSCLK_DEEP_SLEEP_CNTL2 0xc0200084
-#define ixSCLK_DEEP_SLEEP_CNTL3 0xc020009c
-#define ixSCLK_DEEP_SLEEP_MISC_CNTL 0xc0200088
-#define ixLCLK_DEEP_SLEEP_CNTL 0xc020008c
-#define ixLCLK_DEEP_SLEEP_CNTL2 0xc0200310
-#define ixTARGET_AND_CURRENT_PROFILE_INDEX_1 0xc02000f0
-#define ixCG_ULV_PARAMETER 0xc020015c
-#define ixSCLK_MIN_DIV 0xc0200308
-#define ixLCAC_SX0_CNTL 0xc0400d00
-#define ixLCAC_SX0_OVR_SEL 0xc0400d04
-#define ixLCAC_SX0_OVR_VAL 0xc0400d08
-#define ixLCAC_MC0_CNTL 0xc0400d30
-#define ixLCAC_MC0_OVR_SEL 0xc0400d34
-#define ixLCAC_MC0_OVR_VAL 0xc0400d38
-#define ixLCAC_MC1_CNTL 0xc0400d3c
-#define ixLCAC_MC1_OVR_SEL 0xc0400d40
-#define ixLCAC_MC1_OVR_VAL 0xc0400d44
-#define ixLCAC_MC2_CNTL 0xc0400d48
-#define ixLCAC_MC2_OVR_SEL 0xc0400d4c
-#define ixLCAC_MC2_OVR_VAL 0xc0400d50
-#define ixLCAC_MC3_CNTL 0xc0400d54
-#define ixLCAC_MC3_OVR_SEL 0xc0400d58
-#define ixLCAC_MC3_OVR_VAL 0xc0400d5c
-#define ixLCAC_CPL_CNTL 0xc0400d80
-#define ixLCAC_CPL_OVR_SEL 0xc0400d84
-#define ixLCAC_CPL_OVR_VAL 0xc0400d88
-#define mmROM_SMC_IND_INDEX 0x80
-#define mmROM0_ROM_SMC_IND_INDEX 0x80
-#define mmROM1_ROM_SMC_IND_INDEX 0x82
-#define mmROM2_ROM_SMC_IND_INDEX 0x84
-#define mmROM3_ROM_SMC_IND_INDEX 0x86
-#define mmROM_SMC_IND_DATA 0x81
-#define mmROM0_ROM_SMC_IND_DATA 0x81
-#define mmROM1_ROM_SMC_IND_DATA 0x83
-#define mmROM2_ROM_SMC_IND_DATA 0x85
-#define mmROM3_ROM_SMC_IND_DATA 0x87
-#define ixROM_CNTL 0xc0600000
-#define ixPAGE_MIRROR_CNTL 0xc0600004
-#define ixROM_STATUS 0xc0600008
-#define ixCGTT_ROM_CLK_CTRL0 0xc060000c
-#define ixROM_INDEX 0xc0600010
-#define ixROM_DATA 0xc0600014
-#define ixROM_START 0xc0600018
-#define ixROM_SW_CNTL 0xc060001c
-#define ixROM_SW_STATUS 0xc0600020
-#define ixROM_SW_COMMAND 0xc0600024
-#define ixROM_SW_DATA_1 0xc0600028
-#define ixROM_SW_DATA_2 0xc060002c
-#define ixROM_SW_DATA_3 0xc0600030
-#define ixROM_SW_DATA_4 0xc0600034
-#define ixROM_SW_DATA_5 0xc0600038
-#define ixROM_SW_DATA_6 0xc060003c
-#define ixROM_SW_DATA_7 0xc0600040
-#define ixROM_SW_DATA_8 0xc0600044
-#define ixROM_SW_DATA_9 0xc0600048
-#define ixROM_SW_DATA_10 0xc060004c
-#define ixROM_SW_DATA_11 0xc0600050
-#define ixROM_SW_DATA_12 0xc0600054
-#define ixROM_SW_DATA_13 0xc0600058
-#define ixROM_SW_DATA_14 0xc060005c
-#define ixROM_SW_DATA_15 0xc0600060
-#define ixROM_SW_DATA_16 0xc0600064
-#define ixROM_SW_DATA_17 0xc0600068
-#define ixROM_SW_DATA_18 0xc060006c
-#define ixROM_SW_DATA_19 0xc0600070
-#define ixROM_SW_DATA_20 0xc0600074
-#define ixROM_SW_DATA_21 0xc0600078
-#define ixROM_SW_DATA_22 0xc060007c
-#define ixROM_SW_DATA_23 0xc0600080
-#define ixROM_SW_DATA_24 0xc0600084
-#define ixROM_SW_DATA_25 0xc0600088
-#define ixROM_SW_DATA_26 0xc060008c
-#define ixROM_SW_DATA_27 0xc0600090
-#define ixROM_SW_DATA_28 0xc0600094
-#define ixROM_SW_DATA_29 0xc0600098
-#define ixROM_SW_DATA_30 0xc060009c
-#define ixROM_SW_DATA_31 0xc06000a0
-#define ixROM_SW_DATA_32 0xc06000a4
-#define ixROM_SW_DATA_33 0xc06000a8
-#define ixROM_SW_DATA_34 0xc06000ac
-#define ixROM_SW_DATA_35 0xc06000b0
-#define ixROM_SW_DATA_36 0xc06000b4
-#define ixROM_SW_DATA_37 0xc06000b8
-#define ixROM_SW_DATA_38 0xc06000bc
-#define ixROM_SW_DATA_39 0xc06000c0
-#define ixROM_SW_DATA_40 0xc06000c4
-#define ixROM_SW_DATA_41 0xc06000c8
-#define ixROM_SW_DATA_42 0xc06000cc
-#define ixROM_SW_DATA_43 0xc06000d0
-#define ixROM_SW_DATA_44 0xc06000d4
-#define ixROM_SW_DATA_45 0xc06000d8
-#define ixROM_SW_DATA_46 0xc06000dc
-#define ixROM_SW_DATA_47 0xc06000e0
-#define ixROM_SW_DATA_48 0xc06000e4
-#define ixROM_SW_DATA_49 0xc06000e8
-#define ixROM_SW_DATA_50 0xc06000ec
-#define ixROM_SW_DATA_51 0xc06000f0
-#define ixROM_SW_DATA_52 0xc06000f4
-#define ixROM_SW_DATA_53 0xc06000f8
-#define ixROM_SW_DATA_54 0xc06000fc
-#define ixROM_SW_DATA_55 0xc0600100
-#define ixROM_SW_DATA_56 0xc0600104
-#define ixROM_SW_DATA_57 0xc0600108
-#define ixROM_SW_DATA_58 0xc060010c
-#define ixROM_SW_DATA_59 0xc0600110
-#define ixROM_SW_DATA_60 0xc0600114
-#define ixROM_SW_DATA_61 0xc0600118
-#define ixROM_SW_DATA_62 0xc060011c
-#define ixROM_SW_DATA_63 0xc0600120
-#define ixROM_SW_DATA_64 0xc0600124
-
-#endif /* SMU_7_1_0_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_enum.h
deleted file mode 100644
index 61face1d0..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_enum.h
+++ /dev/null
@@ -1,1191 +0,0 @@
-/*
- * SMU_7_1_0 Register documentation
- *
- * Copyright (C) 2014 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef SMU_7_1_0_ENUM_H
-#define SMU_7_1_0_ENUM_H
-
-#define CG_SRBM_START_ADDR 0x600
-#define CG_SRBM_END_ADDR 0x8ff
-#define RCU_CCF_DWORDS0 0x28
-#define RCU_CCF_BITS0 0x500
-#define RCU_CCF_DWORDS1 0x7f
-#define RCU_CCF_BITS1 0x1000
-#define RCU_SAM_BYTES 0x40
-#define RCU_SAM_RTL_BYTES 0x40
-#define KEYS_CHAIN_ADR 0x0
-#define SAMU_KEY_SADR 0xa0
-#define SAMU_KEY_EADR 0xdf
-#define RCU_SMU_BYTES 0x11
-#define RCU_SMU_RTL_BYTES 0x11
-#define SMC_MSG_TEST 0x1
-#define SMC_MSG_PHY_LN_OFF 0x2
-#define SMC_MSG_PHY_LN_ON 0x3
-#define SMC_MSG_DDI_PHY_OFF 0x4
-#define SMC_MSG_DDI_PHY_ON 0x5
-#define SMC_MSG_CASCADE_PLL_OFF 0x6
-#define SMC_MSG_CASCADE_PLL_ON 0x7
-#define SMC_MSG_PWR_OFF_x16 0x8
-#define SMC_MSG_CONFIG_LCLK_DPM 0x9
-#define SMC_MSG_FLUSH_DATA_CACHE 0xa
-#define SMC_MSG_FLUSH_INSTRUCTION_CACHE 0xb
-#define SMC_MSG_CONFIG_VPC_ACCUMULATOR 0xc
-#define SMC_MSG_CONFIG_BAPM 0xd
-#define SMC_MSG_CONFIG_TDC_LIMIT 0xe
-#define SMC_MSG_CONFIG_LPMx 0xf
-#define SMC_MSG_CONFIG_HTC_LIMIT 0x10
-#define SMC_MSG_CONFIG_THERMAL_CNTL 0x11
-#define SMC_MSG_CONFIG_VOLTAGE_CNTL 0x12
-#define SMC_MSG_CONFIG_TDP_CNTL 0x13
-#define SMC_MSG_EN_PM_CNTL 0x14
-#define SMC_MSG_DIS_PM_CNTL 0x15
-#define SMC_MSG_CONFIG_NBDPM 0x16
-#define SMC_MSG_CONFIG_LOADLINE 0x17
-#define SMC_MSG_ADJUST_LOADLINE 0x18
-#define SMC_MSG_RESET 0x20
-#define SMC_MSG_VOLTAGE 0x25
-#define SMC_VERSION_MAJOR 0x7
-#define SMC_VERSION_MINOR 0x0
-#define SMC_HEADER_SIZE 0x40
-#define ROM_SIGNATURE 0xaa55
-typedef enum SurfaceEndian {
- ENDIAN_NONE = 0x0,
- ENDIAN_8IN16 = 0x1,
- ENDIAN_8IN32 = 0x2,
- ENDIAN_8IN64 = 0x3,
-} SurfaceEndian;
-typedef enum ArrayMode {
- ARRAY_LINEAR_GENERAL = 0x0,
- ARRAY_LINEAR_ALIGNED = 0x1,
- ARRAY_1D_TILED_THIN1 = 0x2,
- ARRAY_1D_TILED_THICK = 0x3,
- ARRAY_2D_TILED_THIN1 = 0x4,
- ARRAY_PRT_TILED_THIN1 = 0x5,
- ARRAY_PRT_2D_TILED_THIN1 = 0x6,
- ARRAY_2D_TILED_THICK = 0x7,
- ARRAY_2D_TILED_XTHICK = 0x8,
- ARRAY_PRT_TILED_THICK = 0x9,
- ARRAY_PRT_2D_TILED_THICK = 0xa,
- ARRAY_PRT_3D_TILED_THIN1 = 0xb,
- ARRAY_3D_TILED_THIN1 = 0xc,
- ARRAY_3D_TILED_THICK = 0xd,
- ARRAY_3D_TILED_XTHICK = 0xe,
- ARRAY_PRT_3D_TILED_THICK = 0xf,
-} ArrayMode;
-typedef enum PipeTiling {
- CONFIG_1_PIPE = 0x0,
- CONFIG_2_PIPE = 0x1,
- CONFIG_4_PIPE = 0x2,
- CONFIG_8_PIPE = 0x3,
-} PipeTiling;
-typedef enum BankTiling {
- CONFIG_4_BANK = 0x0,
- CONFIG_8_BANK = 0x1,
-} BankTiling;
-typedef enum GroupInterleave {
- CONFIG_256B_GROUP = 0x0,
- CONFIG_512B_GROUP = 0x1,
-} GroupInterleave;
-typedef enum RowTiling {
- CONFIG_1KB_ROW = 0x0,
- CONFIG_2KB_ROW = 0x1,
- CONFIG_4KB_ROW = 0x2,
- CONFIG_8KB_ROW = 0x3,
- CONFIG_1KB_ROW_OPT = 0x4,
- CONFIG_2KB_ROW_OPT = 0x5,
- CONFIG_4KB_ROW_OPT = 0x6,
- CONFIG_8KB_ROW_OPT = 0x7,
-} RowTiling;
-typedef enum BankSwapBytes {
- CONFIG_128B_SWAPS = 0x0,
- CONFIG_256B_SWAPS = 0x1,
- CONFIG_512B_SWAPS = 0x2,
- CONFIG_1KB_SWAPS = 0x3,
-} BankSwapBytes;
-typedef enum SampleSplitBytes {
- CONFIG_1KB_SPLIT = 0x0,
- CONFIG_2KB_SPLIT = 0x1,
- CONFIG_4KB_SPLIT = 0x2,
- CONFIG_8KB_SPLIT = 0x3,
-} SampleSplitBytes;
-typedef enum NumPipes {
- ADDR_CONFIG_1_PIPE = 0x0,
- ADDR_CONFIG_2_PIPE = 0x1,
- ADDR_CONFIG_4_PIPE = 0x2,
- ADDR_CONFIG_8_PIPE = 0x3,
- ADDR_CONFIG_16_PIPE = 0x4,
-} NumPipes;
-typedef enum PipeInterleaveSize {
- ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
- ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
-} PipeInterleaveSize;
-typedef enum BankInterleaveSize {
- ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
- ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
- ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
- ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
-} BankInterleaveSize;
-typedef enum NumShaderEngines {
- ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
- ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
-} NumShaderEngines;
-typedef enum ShaderEngineTileSize {
- ADDR_CONFIG_SE_TILE_16 = 0x0,
- ADDR_CONFIG_SE_TILE_32 = 0x1,
-} ShaderEngineTileSize;
-typedef enum NumGPUs {
- ADDR_CONFIG_1_GPU = 0x0,
- ADDR_CONFIG_2_GPU = 0x1,
- ADDR_CONFIG_4_GPU = 0x2,
-} NumGPUs;
-typedef enum MultiGPUTileSize {
- ADDR_CONFIG_GPU_TILE_16 = 0x0,
- ADDR_CONFIG_GPU_TILE_32 = 0x1,
- ADDR_CONFIG_GPU_TILE_64 = 0x2,
- ADDR_CONFIG_GPU_TILE_128 = 0x3,
-} MultiGPUTileSize;
-typedef enum RowSize {
- ADDR_CONFIG_1KB_ROW = 0x0,
- ADDR_CONFIG_2KB_ROW = 0x1,
- ADDR_CONFIG_4KB_ROW = 0x2,
-} RowSize;
-typedef enum NumLowerPipes {
- ADDR_CONFIG_1_LOWER_PIPES = 0x0,
- ADDR_CONFIG_2_LOWER_PIPES = 0x1,
-} NumLowerPipes;
-typedef enum DebugBlockId {
- DBG_CLIENT_BLKID_RESERVED = 0x0,
- DBG_CLIENT_BLKID_dbg = 0x1,
- DBG_CLIENT_BLKID_dco0 = 0x2,
- DBG_CLIENT_BLKID_wd = 0x3,
- DBG_CLIENT_BLKID_vmc = 0x4,
- DBG_CLIENT_BLKID_scf2 = 0x5,
- DBG_CLIENT_BLKID_spim3 = 0x6,
- DBG_CLIENT_BLKID_cb3 = 0x7,
- DBG_CLIENT_BLKID_sx0 = 0x8,
- DBG_CLIENT_BLKID_cb2 = 0x9,
- DBG_CLIENT_BLKID_bci1 = 0xa,
- DBG_CLIENT_BLKID_xdma = 0xb,
- DBG_CLIENT_BLKID_bci0 = 0xc,
- DBG_CLIENT_BLKID_spim0 = 0xd,
- DBG_CLIENT_BLKID_mcd0 = 0xe,
- DBG_CLIENT_BLKID_mcc0 = 0xf,
- DBG_CLIENT_BLKID_cb0 = 0x10,
- DBG_CLIENT_BLKID_cb1 = 0x11,
- DBG_CLIENT_BLKID_cpc_0 = 0x12,
- DBG_CLIENT_BLKID_cpc_1 = 0x13,
- DBG_CLIENT_BLKID_cpf = 0x14,
- DBG_CLIENT_BLKID_rlc = 0x15,
- DBG_CLIENT_BLKID_grbm = 0x16,
- DBG_CLIENT_BLKID_bif = 0x17,
- DBG_CLIENT_BLKID_scf1 = 0x18,
- DBG_CLIENT_BLKID_sam = 0x19,
- DBG_CLIENT_BLKID_mcd4 = 0x1a,
- DBG_CLIENT_BLKID_mcc4 = 0x1b,
- DBG_CLIENT_BLKID_gmcon = 0x1c,
- DBG_CLIENT_BLKID_mcb = 0x1d,
- DBG_CLIENT_BLKID_vgt0 = 0x1e,
- DBG_CLIENT_BLKID_pc0 = 0x1f,
- DBG_CLIENT_BLKID_spim1 = 0x20,
- DBG_CLIENT_BLKID_bci2 = 0x21,
- DBG_CLIENT_BLKID_mcd6 = 0x22,
- DBG_CLIENT_BLKID_mcc6 = 0x23,
- DBG_CLIENT_BLKID_mcd3 = 0x24,
- DBG_CLIENT_BLKID_mcc3 = 0x25,
- DBG_CLIENT_BLKID_uvdm_0 = 0x26,
- DBG_CLIENT_BLKID_uvdm_1 = 0x27,
- DBG_CLIENT_BLKID_uvdm_2 = 0x28,
- DBG_CLIENT_BLKID_uvdm_3 = 0x29,
- DBG_CLIENT_BLKID_spim2 = 0x2a,
- DBG_CLIENT_BLKID_ds = 0x2b,
- DBG_CLIENT_BLKID_srbm = 0x2c,
- DBG_CLIENT_BLKID_ih = 0x2d,
- DBG_CLIENT_BLKID_sem = 0x2e,
- DBG_CLIENT_BLKID_sdma_0 = 0x2f,
- DBG_CLIENT_BLKID_sdma_1 = 0x30,
- DBG_CLIENT_BLKID_hdp = 0x31,
- DBG_CLIENT_BLKID_acp_0 = 0x32,
- DBG_CLIENT_BLKID_acp_1 = 0x33,
- DBG_CLIENT_BLKID_vceb_0 = 0x34,
- DBG_CLIENT_BLKID_vceb_1 = 0x35,
- DBG_CLIENT_BLKID_vceb_2 = 0x36,
- DBG_CLIENT_BLKID_mcd2 = 0x37,
- DBG_CLIENT_BLKID_mcc2 = 0x38,
- DBG_CLIENT_BLKID_scf3 = 0x39,
- DBG_CLIENT_BLKID_bci3 = 0x3a,
- DBG_CLIENT_BLKID_mcd5 = 0x3b,
- DBG_CLIENT_BLKID_mcc5 = 0x3c,
- DBG_CLIENT_BLKID_vgt2 = 0x3d,
- DBG_CLIENT_BLKID_pc2 = 0x3e,
- DBG_CLIENT_BLKID_smu_0 = 0x3f,
- DBG_CLIENT_BLKID_smu_1 = 0x40,
- DBG_CLIENT_BLKID_smu_2 = 0x41,
- DBG_CLIENT_BLKID_vcea_0 = 0x42,
- DBG_CLIENT_BLKID_vcea_1 = 0x43,
- DBG_CLIENT_BLKID_vcea_2 = 0x44,
- DBG_CLIENT_BLKID_vcea_3 = 0x45,
- DBG_CLIENT_BLKID_vcea_4 = 0x46,
- DBG_CLIENT_BLKID_vcea_5 = 0x47,
- DBG_CLIENT_BLKID_vcea_6 = 0x48,
- DBG_CLIENT_BLKID_scf0 = 0x49,
- DBG_CLIENT_BLKID_vgt1 = 0x4a,
- DBG_CLIENT_BLKID_pc1 = 0x4b,
- DBG_CLIENT_BLKID_gdc_0 = 0x4c,
- DBG_CLIENT_BLKID_gdc_1 = 0x4d,
- DBG_CLIENT_BLKID_gdc_2 = 0x4e,
- DBG_CLIENT_BLKID_gdc_3 = 0x4f,
- DBG_CLIENT_BLKID_gdc_4 = 0x50,
- DBG_CLIENT_BLKID_gdc_5 = 0x51,
- DBG_CLIENT_BLKID_gdc_6 = 0x52,
- DBG_CLIENT_BLKID_gdc_7 = 0x53,
- DBG_CLIENT_BLKID_gdc_8 = 0x54,
- DBG_CLIENT_BLKID_gdc_9 = 0x55,
- DBG_CLIENT_BLKID_gdc_10 = 0x56,
- DBG_CLIENT_BLKID_gdc_11 = 0x57,
- DBG_CLIENT_BLKID_gdc_12 = 0x58,
- DBG_CLIENT_BLKID_gdc_13 = 0x59,
- DBG_CLIENT_BLKID_gdc_14 = 0x5a,
- DBG_CLIENT_BLKID_gdc_15 = 0x5b,
- DBG_CLIENT_BLKID_gdc_16 = 0x5c,
- DBG_CLIENT_BLKID_gdc_17 = 0x5d,
- DBG_CLIENT_BLKID_gdc_18 = 0x5e,
- DBG_CLIENT_BLKID_gdc_19 = 0x5f,
- DBG_CLIENT_BLKID_gdc_20 = 0x60,
- DBG_CLIENT_BLKID_gdc_21 = 0x61,
- DBG_CLIENT_BLKID_gdc_22 = 0x62,
- DBG_CLIENT_BLKID_vgt3 = 0x63,
- DBG_CLIENT_BLKID_pc3 = 0x64,
- DBG_CLIENT_BLKID_uvdu_0 = 0x65,
- DBG_CLIENT_BLKID_uvdu_1 = 0x66,
- DBG_CLIENT_BLKID_uvdu_2 = 0x67,
- DBG_CLIENT_BLKID_uvdu_3 = 0x68,
- DBG_CLIENT_BLKID_uvdu_4 = 0x69,
- DBG_CLIENT_BLKID_uvdu_5 = 0x6a,
- DBG_CLIENT_BLKID_uvdu_6 = 0x6b,
- DBG_CLIENT_BLKID_mcd7 = 0x6c,
- DBG_CLIENT_BLKID_mcc7 = 0x6d,
- DBG_CLIENT_BLKID_cpg_0 = 0x6e,
- DBG_CLIENT_BLKID_cpg_1 = 0x6f,
- DBG_CLIENT_BLKID_gck = 0x70,
- DBG_CLIENT_BLKID_mcd1 = 0x71,
- DBG_CLIENT_BLKID_mcc1 = 0x72,
- DBG_CLIENT_BLKID_cb101 = 0x73,
- DBG_CLIENT_BLKID_cb103 = 0x74,
- DBG_CLIENT_BLKID_sx10 = 0x75,
- DBG_CLIENT_BLKID_cb102 = 0x76,
- DBG_CLIENT_BLKID_cb002 = 0x77,
- DBG_CLIENT_BLKID_cb100 = 0x78,
- DBG_CLIENT_BLKID_cb000 = 0x79,
- DBG_CLIENT_BLKID_pa00 = 0x7a,
- DBG_CLIENT_BLKID_pa10 = 0x7b,
- DBG_CLIENT_BLKID_ia0 = 0x7c,
- DBG_CLIENT_BLKID_ia1 = 0x7d,
- DBG_CLIENT_BLKID_tmonw00 = 0x7e,
- DBG_CLIENT_BLKID_cb001 = 0x7f,
- DBG_CLIENT_BLKID_cb003 = 0x80,
- DBG_CLIENT_BLKID_sx00 = 0x81,
- DBG_CLIENT_BLKID_sx20 = 0x82,
- DBG_CLIENT_BLKID_cb203 = 0x83,
- DBG_CLIENT_BLKID_cb201 = 0x84,
- DBG_CLIENT_BLKID_cb302 = 0x85,
- DBG_CLIENT_BLKID_cb202 = 0x86,
- DBG_CLIENT_BLKID_cb300 = 0x87,
- DBG_CLIENT_BLKID_cb200 = 0x88,
- DBG_CLIENT_BLKID_pa01 = 0x89,
- DBG_CLIENT_BLKID_pa11 = 0x8a,
- DBG_CLIENT_BLKID_sx30 = 0x8b,
- DBG_CLIENT_BLKID_cb303 = 0x8c,
- DBG_CLIENT_BLKID_cb301 = 0x8d,
- DBG_CLIENT_BLKID_dco = 0x8e,
- DBG_CLIENT_BLKID_scb0 = 0x8f,
- DBG_CLIENT_BLKID_scb1 = 0x90,
- DBG_CLIENT_BLKID_scb2 = 0x91,
- DBG_CLIENT_BLKID_scb3 = 0x92,
- DBG_CLIENT_BLKID_tmonw01 = 0x93,
- DBG_CLIENT_BLKID_RESERVED_LAST = 0x94,
-} DebugBlockId;
-typedef enum DebugBlockId_OLD {
- DBG_BLOCK_ID_RESERVED = 0x0,
- DBG_BLOCK_ID_DBG = 0x1,
- DBG_BLOCK_ID_VMC = 0x2,
- DBG_BLOCK_ID_PDMA = 0x3,
- DBG_BLOCK_ID_CG = 0x4,
- DBG_BLOCK_ID_SRBM = 0x5,
- DBG_BLOCK_ID_GRBM = 0x6,
- DBG_BLOCK_ID_RLC = 0x7,
- DBG_BLOCK_ID_CSC = 0x8,
- DBG_BLOCK_ID_SEM = 0x9,
- DBG_BLOCK_ID_IH = 0xa,
- DBG_BLOCK_ID_SC = 0xb,
- DBG_BLOCK_ID_SQ = 0xc,
- DBG_BLOCK_ID_AVP = 0xd,
- DBG_BLOCK_ID_GMCON = 0xe,
- DBG_BLOCK_ID_SMU = 0xf,
- DBG_BLOCK_ID_DMA0 = 0x10,
- DBG_BLOCK_ID_DMA1 = 0x11,
- DBG_BLOCK_ID_SPIM = 0x12,
- DBG_BLOCK_ID_GDS = 0x13,
- DBG_BLOCK_ID_SPIS = 0x14,
- DBG_BLOCK_ID_UNUSED0 = 0x15,
- DBG_BLOCK_ID_PA0 = 0x16,
- DBG_BLOCK_ID_PA1 = 0x17,
- DBG_BLOCK_ID_CP0 = 0x18,
- DBG_BLOCK_ID_CP1 = 0x19,
- DBG_BLOCK_ID_CP2 = 0x1a,
- DBG_BLOCK_ID_UNUSED1 = 0x1b,
- DBG_BLOCK_ID_UVDU = 0x1c,
- DBG_BLOCK_ID_UVDM = 0x1d,
- DBG_BLOCK_ID_VCE = 0x1e,
- DBG_BLOCK_ID_UNUSED2 = 0x1f,
- DBG_BLOCK_ID_VGT0 = 0x20,
- DBG_BLOCK_ID_VGT1 = 0x21,
- DBG_BLOCK_ID_IA = 0x22,
- DBG_BLOCK_ID_UNUSED3 = 0x23,
- DBG_BLOCK_ID_SCT0 = 0x24,
- DBG_BLOCK_ID_SCT1 = 0x25,
- DBG_BLOCK_ID_SPM0 = 0x26,
- DBG_BLOCK_ID_SPM1 = 0x27,
- DBG_BLOCK_ID_TCAA = 0x28,
- DBG_BLOCK_ID_TCAB = 0x29,
- DBG_BLOCK_ID_TCCA = 0x2a,
- DBG_BLOCK_ID_TCCB = 0x2b,
- DBG_BLOCK_ID_MCC0 = 0x2c,
- DBG_BLOCK_ID_MCC1 = 0x2d,
- DBG_BLOCK_ID_MCC2 = 0x2e,
- DBG_BLOCK_ID_MCC3 = 0x2f,
- DBG_BLOCK_ID_SX0 = 0x30,
- DBG_BLOCK_ID_SX1 = 0x31,
- DBG_BLOCK_ID_SX2 = 0x32,
- DBG_BLOCK_ID_SX3 = 0x33,
- DBG_BLOCK_ID_UNUSED4 = 0x34,
- DBG_BLOCK_ID_UNUSED5 = 0x35,
- DBG_BLOCK_ID_UNUSED6 = 0x36,
- DBG_BLOCK_ID_UNUSED7 = 0x37,
- DBG_BLOCK_ID_PC0 = 0x38,
- DBG_BLOCK_ID_PC1 = 0x39,
- DBG_BLOCK_ID_UNUSED8 = 0x3a,
- DBG_BLOCK_ID_UNUSED9 = 0x3b,
- DBG_BLOCK_ID_UNUSED10 = 0x3c,
- DBG_BLOCK_ID_UNUSED11 = 0x3d,
- DBG_BLOCK_ID_MCB = 0x3e,
- DBG_BLOCK_ID_UNUSED12 = 0x3f,
- DBG_BLOCK_ID_SCB0 = 0x40,
- DBG_BLOCK_ID_SCB1 = 0x41,
- DBG_BLOCK_ID_UNUSED13 = 0x42,
- DBG_BLOCK_ID_UNUSED14 = 0x43,
- DBG_BLOCK_ID_SCF0 = 0x44,
- DBG_BLOCK_ID_SCF1 = 0x45,
- DBG_BLOCK_ID_UNUSED15 = 0x46,
- DBG_BLOCK_ID_UNUSED16 = 0x47,
- DBG_BLOCK_ID_BCI0 = 0x48,
- DBG_BLOCK_ID_BCI1 = 0x49,
- DBG_BLOCK_ID_BCI2 = 0x4a,
- DBG_BLOCK_ID_BCI3 = 0x4b,
- DBG_BLOCK_ID_UNUSED17 = 0x4c,
- DBG_BLOCK_ID_UNUSED18 = 0x4d,
- DBG_BLOCK_ID_UNUSED19 = 0x4e,
- DBG_BLOCK_ID_UNUSED20 = 0x4f,
- DBG_BLOCK_ID_CB00 = 0x50,
- DBG_BLOCK_ID_CB01 = 0x51,
- DBG_BLOCK_ID_CB02 = 0x52,
- DBG_BLOCK_ID_CB03 = 0x53,
- DBG_BLOCK_ID_CB04 = 0x54,
- DBG_BLOCK_ID_UNUSED21 = 0x55,
- DBG_BLOCK_ID_UNUSED22 = 0x56,
- DBG_BLOCK_ID_UNUSED23 = 0x57,
- DBG_BLOCK_ID_CB10 = 0x58,
- DBG_BLOCK_ID_CB11 = 0x59,
- DBG_BLOCK_ID_CB12 = 0x5a,
- DBG_BLOCK_ID_CB13 = 0x5b,
- DBG_BLOCK_ID_CB14 = 0x5c,
- DBG_BLOCK_ID_UNUSED24 = 0x5d,
- DBG_BLOCK_ID_UNUSED25 = 0x5e,
- DBG_BLOCK_ID_UNUSED26 = 0x5f,
- DBG_BLOCK_ID_TCP0 = 0x60,
- DBG_BLOCK_ID_TCP1 = 0x61,
- DBG_BLOCK_ID_TCP2 = 0x62,
- DBG_BLOCK_ID_TCP3 = 0x63,
- DBG_BLOCK_ID_TCP4 = 0x64,
- DBG_BLOCK_ID_TCP5 = 0x65,
- DBG_BLOCK_ID_TCP6 = 0x66,
- DBG_BLOCK_ID_TCP7 = 0x67,
- DBG_BLOCK_ID_TCP8 = 0x68,
- DBG_BLOCK_ID_TCP9 = 0x69,
- DBG_BLOCK_ID_TCP10 = 0x6a,
- DBG_BLOCK_ID_TCP11 = 0x6b,
- DBG_BLOCK_ID_TCP12 = 0x6c,
- DBG_BLOCK_ID_TCP13 = 0x6d,
- DBG_BLOCK_ID_TCP14 = 0x6e,
- DBG_BLOCK_ID_TCP15 = 0x6f,
- DBG_BLOCK_ID_TCP16 = 0x70,
- DBG_BLOCK_ID_TCP17 = 0x71,
- DBG_BLOCK_ID_TCP18 = 0x72,
- DBG_BLOCK_ID_TCP19 = 0x73,
- DBG_BLOCK_ID_TCP20 = 0x74,
- DBG_BLOCK_ID_TCP21 = 0x75,
- DBG_BLOCK_ID_TCP22 = 0x76,
- DBG_BLOCK_ID_TCP23 = 0x77,
- DBG_BLOCK_ID_TCP_RESERVED0 = 0x78,
- DBG_BLOCK_ID_TCP_RESERVED1 = 0x79,
- DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a,
- DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b,
- DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c,
- DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d,
- DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e,
- DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f,
- DBG_BLOCK_ID_DB00 = 0x80,
- DBG_BLOCK_ID_DB01 = 0x81,
- DBG_BLOCK_ID_DB02 = 0x82,
- DBG_BLOCK_ID_DB03 = 0x83,
- DBG_BLOCK_ID_DB04 = 0x84,
- DBG_BLOCK_ID_UNUSED27 = 0x85,
- DBG_BLOCK_ID_UNUSED28 = 0x86,
- DBG_BLOCK_ID_UNUSED29 = 0x87,
- DBG_BLOCK_ID_DB10 = 0x88,
- DBG_BLOCK_ID_DB11 = 0x89,
- DBG_BLOCK_ID_DB12 = 0x8a,
- DBG_BLOCK_ID_DB13 = 0x8b,
- DBG_BLOCK_ID_DB14 = 0x8c,
- DBG_BLOCK_ID_UNUSED30 = 0x8d,
- DBG_BLOCK_ID_UNUSED31 = 0x8e,
- DBG_BLOCK_ID_UNUSED32 = 0x8f,
- DBG_BLOCK_ID_TCC0 = 0x90,
- DBG_BLOCK_ID_TCC1 = 0x91,
- DBG_BLOCK_ID_TCC2 = 0x92,
- DBG_BLOCK_ID_TCC3 = 0x93,
- DBG_BLOCK_ID_TCC4 = 0x94,
- DBG_BLOCK_ID_TCC5 = 0x95,
- DBG_BLOCK_ID_TCC6 = 0x96,
- DBG_BLOCK_ID_TCC7 = 0x97,
- DBG_BLOCK_ID_SPS00 = 0x98,
- DBG_BLOCK_ID_SPS01 = 0x99,
- DBG_BLOCK_ID_SPS02 = 0x9a,
- DBG_BLOCK_ID_SPS10 = 0x9b,
- DBG_BLOCK_ID_SPS11 = 0x9c,
- DBG_BLOCK_ID_SPS12 = 0x9d,
- DBG_BLOCK_ID_UNUSED33 = 0x9e,
- DBG_BLOCK_ID_UNUSED34 = 0x9f,
- DBG_BLOCK_ID_TA00 = 0xa0,
- DBG_BLOCK_ID_TA01 = 0xa1,
- DBG_BLOCK_ID_TA02 = 0xa2,
- DBG_BLOCK_ID_TA03 = 0xa3,
- DBG_BLOCK_ID_TA04 = 0xa4,
- DBG_BLOCK_ID_TA05 = 0xa5,
- DBG_BLOCK_ID_TA06 = 0xa6,
- DBG_BLOCK_ID_TA07 = 0xa7,
- DBG_BLOCK_ID_TA08 = 0xa8,
- DBG_BLOCK_ID_TA09 = 0xa9,
- DBG_BLOCK_ID_TA0A = 0xaa,
- DBG_BLOCK_ID_TA0B = 0xab,
- DBG_BLOCK_ID_UNUSED35 = 0xac,
- DBG_BLOCK_ID_UNUSED36 = 0xad,
- DBG_BLOCK_ID_UNUSED37 = 0xae,
- DBG_BLOCK_ID_UNUSED38 = 0xaf,
- DBG_BLOCK_ID_TA10 = 0xb0,
- DBG_BLOCK_ID_TA11 = 0xb1,
- DBG_BLOCK_ID_TA12 = 0xb2,
- DBG_BLOCK_ID_TA13 = 0xb3,
- DBG_BLOCK_ID_TA14 = 0xb4,
- DBG_BLOCK_ID_TA15 = 0xb5,
- DBG_BLOCK_ID_TA16 = 0xb6,
- DBG_BLOCK_ID_TA17 = 0xb7,
- DBG_BLOCK_ID_TA18 = 0xb8,
- DBG_BLOCK_ID_TA19 = 0xb9,
- DBG_BLOCK_ID_TA1A = 0xba,
- DBG_BLOCK_ID_TA1B = 0xbb,
- DBG_BLOCK_ID_UNUSED39 = 0xbc,
- DBG_BLOCK_ID_UNUSED40 = 0xbd,
- DBG_BLOCK_ID_UNUSED41 = 0xbe,
- DBG_BLOCK_ID_UNUSED42 = 0xbf,
- DBG_BLOCK_ID_TD00 = 0xc0,
- DBG_BLOCK_ID_TD01 = 0xc1,
- DBG_BLOCK_ID_TD02 = 0xc2,
- DBG_BLOCK_ID_TD03 = 0xc3,
- DBG_BLOCK_ID_TD04 = 0xc4,
- DBG_BLOCK_ID_TD05 = 0xc5,
- DBG_BLOCK_ID_TD06 = 0xc6,
- DBG_BLOCK_ID_TD07 = 0xc7,
- DBG_BLOCK_ID_TD08 = 0xc8,
- DBG_BLOCK_ID_TD09 = 0xc9,
- DBG_BLOCK_ID_TD0A = 0xca,
- DBG_BLOCK_ID_TD0B = 0xcb,
- DBG_BLOCK_ID_UNUSED43 = 0xcc,
- DBG_BLOCK_ID_UNUSED44 = 0xcd,
- DBG_BLOCK_ID_UNUSED45 = 0xce,
- DBG_BLOCK_ID_UNUSED46 = 0xcf,
- DBG_BLOCK_ID_TD10 = 0xd0,
- DBG_BLOCK_ID_TD11 = 0xd1,
- DBG_BLOCK_ID_TD12 = 0xd2,
- DBG_BLOCK_ID_TD13 = 0xd3,
- DBG_BLOCK_ID_TD14 = 0xd4,
- DBG_BLOCK_ID_TD15 = 0xd5,
- DBG_BLOCK_ID_TD16 = 0xd6,
- DBG_BLOCK_ID_TD17 = 0xd7,
- DBG_BLOCK_ID_TD18 = 0xd8,
- DBG_BLOCK_ID_TD19 = 0xd9,
- DBG_BLOCK_ID_TD1A = 0xda,
- DBG_BLOCK_ID_TD1B = 0xdb,
- DBG_BLOCK_ID_UNUSED47 = 0xdc,
- DBG_BLOCK_ID_UNUSED48 = 0xdd,
- DBG_BLOCK_ID_UNUSED49 = 0xde,
- DBG_BLOCK_ID_UNUSED50 = 0xdf,
- DBG_BLOCK_ID_MCD0 = 0xe0,
- DBG_BLOCK_ID_MCD1 = 0xe1,
- DBG_BLOCK_ID_MCD2 = 0xe2,
- DBG_BLOCK_ID_MCD3 = 0xe3,
- DBG_BLOCK_ID_MCD4 = 0xe4,
- DBG_BLOCK_ID_MCD5 = 0xe5,
- DBG_BLOCK_ID_UNUSED51 = 0xe6,
- DBG_BLOCK_ID_UNUSED52 = 0xe7,
-} DebugBlockId_OLD;
-typedef enum DebugBlockId_BY2 {
- DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
- DBG_BLOCK_ID_VMC_BY2 = 0x1,
- DBG_BLOCK_ID_CG_BY2 = 0x2,
- DBG_BLOCK_ID_GRBM_BY2 = 0x3,
- DBG_BLOCK_ID_CSC_BY2 = 0x4,
- DBG_BLOCK_ID_IH_BY2 = 0x5,
- DBG_BLOCK_ID_SQ_BY2 = 0x6,
- DBG_BLOCK_ID_GMCON_BY2 = 0x7,
- DBG_BLOCK_ID_DMA0_BY2 = 0x8,
- DBG_BLOCK_ID_SPIM_BY2 = 0x9,
- DBG_BLOCK_ID_SPIS_BY2 = 0xa,
- DBG_BLOCK_ID_PA0_BY2 = 0xb,
- DBG_BLOCK_ID_CP0_BY2 = 0xc,
- DBG_BLOCK_ID_CP2_BY2 = 0xd,
- DBG_BLOCK_ID_UVDU_BY2 = 0xe,
- DBG_BLOCK_ID_VCE_BY2 = 0xf,
- DBG_BLOCK_ID_VGT0_BY2 = 0x10,
- DBG_BLOCK_ID_IA_BY2 = 0x11,
- DBG_BLOCK_ID_SCT0_BY2 = 0x12,
- DBG_BLOCK_ID_SPM0_BY2 = 0x13,
- DBG_BLOCK_ID_TCAA_BY2 = 0x14,
- DBG_BLOCK_ID_TCCA_BY2 = 0x15,
- DBG_BLOCK_ID_MCC0_BY2 = 0x16,
- DBG_BLOCK_ID_MCC2_BY2 = 0x17,
- DBG_BLOCK_ID_SX0_BY2 = 0x18,
- DBG_BLOCK_ID_SX2_BY2 = 0x19,
- DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a,
- DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b,
- DBG_BLOCK_ID_PC0_BY2 = 0x1c,
- DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d,
- DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e,
- DBG_BLOCK_ID_MCB_BY2 = 0x1f,
- DBG_BLOCK_ID_SCB0_BY2 = 0x20,
- DBG_BLOCK_ID_UNUSED13_BY2 = 0x21,
- DBG_BLOCK_ID_SCF0_BY2 = 0x22,
- DBG_BLOCK_ID_UNUSED15_BY2 = 0x23,
- DBG_BLOCK_ID_BCI0_BY2 = 0x24,
- DBG_BLOCK_ID_BCI2_BY2 = 0x25,
- DBG_BLOCK_ID_UNUSED17_BY2 = 0x26,
- DBG_BLOCK_ID_UNUSED19_BY2 = 0x27,
- DBG_BLOCK_ID_CB00_BY2 = 0x28,
- DBG_BLOCK_ID_CB02_BY2 = 0x29,
- DBG_BLOCK_ID_CB04_BY2 = 0x2a,
- DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b,
- DBG_BLOCK_ID_CB10_BY2 = 0x2c,
- DBG_BLOCK_ID_CB12_BY2 = 0x2d,
- DBG_BLOCK_ID_CB14_BY2 = 0x2e,
- DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f,
- DBG_BLOCK_ID_TCP0_BY2 = 0x30,
- DBG_BLOCK_ID_TCP2_BY2 = 0x31,
- DBG_BLOCK_ID_TCP4_BY2 = 0x32,
- DBG_BLOCK_ID_TCP6_BY2 = 0x33,
- DBG_BLOCK_ID_TCP8_BY2 = 0x34,
- DBG_BLOCK_ID_TCP10_BY2 = 0x35,
- DBG_BLOCK_ID_TCP12_BY2 = 0x36,
- DBG_BLOCK_ID_TCP14_BY2 = 0x37,
- DBG_BLOCK_ID_TCP16_BY2 = 0x38,
- DBG_BLOCK_ID_TCP18_BY2 = 0x39,
- DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
- DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
- DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
- DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
- DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
- DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
- DBG_BLOCK_ID_DB00_BY2 = 0x40,
- DBG_BLOCK_ID_DB02_BY2 = 0x41,
- DBG_BLOCK_ID_DB04_BY2 = 0x42,
- DBG_BLOCK_ID_UNUSED28_BY2 = 0x43,
- DBG_BLOCK_ID_DB10_BY2 = 0x44,
- DBG_BLOCK_ID_DB12_BY2 = 0x45,
- DBG_BLOCK_ID_DB14_BY2 = 0x46,
- DBG_BLOCK_ID_UNUSED31_BY2 = 0x47,
- DBG_BLOCK_ID_TCC0_BY2 = 0x48,
- DBG_BLOCK_ID_TCC2_BY2 = 0x49,
- DBG_BLOCK_ID_TCC4_BY2 = 0x4a,
- DBG_BLOCK_ID_TCC6_BY2 = 0x4b,
- DBG_BLOCK_ID_SPS00_BY2 = 0x4c,
- DBG_BLOCK_ID_SPS02_BY2 = 0x4d,
- DBG_BLOCK_ID_SPS11_BY2 = 0x4e,
- DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f,
- DBG_BLOCK_ID_TA00_BY2 = 0x50,
- DBG_BLOCK_ID_TA02_BY2 = 0x51,
- DBG_BLOCK_ID_TA04_BY2 = 0x52,
- DBG_BLOCK_ID_TA06_BY2 = 0x53,
- DBG_BLOCK_ID_TA08_BY2 = 0x54,
- DBG_BLOCK_ID_TA0A_BY2 = 0x55,
- DBG_BLOCK_ID_UNUSED35_BY2 = 0x56,
- DBG_BLOCK_ID_UNUSED37_BY2 = 0x57,
- DBG_BLOCK_ID_TA10_BY2 = 0x58,
- DBG_BLOCK_ID_TA12_BY2 = 0x59,
- DBG_BLOCK_ID_TA14_BY2 = 0x5a,
- DBG_BLOCK_ID_TA16_BY2 = 0x5b,
- DBG_BLOCK_ID_TA18_BY2 = 0x5c,
- DBG_BLOCK_ID_TA1A_BY2 = 0x5d,
- DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e,
- DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f,
- DBG_BLOCK_ID_TD00_BY2 = 0x60,
- DBG_BLOCK_ID_TD02_BY2 = 0x61,
- DBG_BLOCK_ID_TD04_BY2 = 0x62,
- DBG_BLOCK_ID_TD06_BY2 = 0x63,
- DBG_BLOCK_ID_TD08_BY2 = 0x64,
- DBG_BLOCK_ID_TD0A_BY2 = 0x65,
- DBG_BLOCK_ID_UNUSED43_BY2 = 0x66,
- DBG_BLOCK_ID_UNUSED45_BY2 = 0x67,
- DBG_BLOCK_ID_TD10_BY2 = 0x68,
- DBG_BLOCK_ID_TD12_BY2 = 0x69,
- DBG_BLOCK_ID_TD14_BY2 = 0x6a,
- DBG_BLOCK_ID_TD16_BY2 = 0x6b,
- DBG_BLOCK_ID_TD18_BY2 = 0x6c,
- DBG_BLOCK_ID_TD1A_BY2 = 0x6d,
- DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e,
- DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f,
- DBG_BLOCK_ID_MCD0_BY2 = 0x70,
- DBG_BLOCK_ID_MCD2_BY2 = 0x71,
- DBG_BLOCK_ID_MCD4_BY2 = 0x72,
- DBG_BLOCK_ID_UNUSED51_BY2 = 0x73,
-} DebugBlockId_BY2;
-typedef enum DebugBlockId_BY4 {
- DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
- DBG_BLOCK_ID_CG_BY4 = 0x1,
- DBG_BLOCK_ID_CSC_BY4 = 0x2,
- DBG_BLOCK_ID_SQ_BY4 = 0x3,
- DBG_BLOCK_ID_DMA0_BY4 = 0x4,
- DBG_BLOCK_ID_SPIS_BY4 = 0x5,
- DBG_BLOCK_ID_CP0_BY4 = 0x6,
- DBG_BLOCK_ID_UVDU_BY4 = 0x7,
- DBG_BLOCK_ID_VGT0_BY4 = 0x8,
- DBG_BLOCK_ID_SCT0_BY4 = 0x9,
- DBG_BLOCK_ID_TCAA_BY4 = 0xa,
- DBG_BLOCK_ID_MCC0_BY4 = 0xb,
- DBG_BLOCK_ID_SX0_BY4 = 0xc,
- DBG_BLOCK_ID_UNUSED4_BY4 = 0xd,
- DBG_BLOCK_ID_PC0_BY4 = 0xe,
- DBG_BLOCK_ID_UNUSED10_BY4 = 0xf,
- DBG_BLOCK_ID_SCB0_BY4 = 0x10,
- DBG_BLOCK_ID_SCF0_BY4 = 0x11,
- DBG_BLOCK_ID_BCI0_BY4 = 0x12,
- DBG_BLOCK_ID_UNUSED17_BY4 = 0x13,
- DBG_BLOCK_ID_CB00_BY4 = 0x14,
- DBG_BLOCK_ID_CB04_BY4 = 0x15,
- DBG_BLOCK_ID_CB10_BY4 = 0x16,
- DBG_BLOCK_ID_CB14_BY4 = 0x17,
- DBG_BLOCK_ID_TCP0_BY4 = 0x18,
- DBG_BLOCK_ID_TCP4_BY4 = 0x19,
- DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
- DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
- DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
- DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
- DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
- DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
- DBG_BLOCK_ID_DB_BY4 = 0x20,
- DBG_BLOCK_ID_DB04_BY4 = 0x21,
- DBG_BLOCK_ID_DB10_BY4 = 0x22,
- DBG_BLOCK_ID_DB14_BY4 = 0x23,
- DBG_BLOCK_ID_TCC0_BY4 = 0x24,
- DBG_BLOCK_ID_TCC4_BY4 = 0x25,
- DBG_BLOCK_ID_SPS00_BY4 = 0x26,
- DBG_BLOCK_ID_SPS11_BY4 = 0x27,
- DBG_BLOCK_ID_TA00_BY4 = 0x28,
- DBG_BLOCK_ID_TA04_BY4 = 0x29,
- DBG_BLOCK_ID_TA08_BY4 = 0x2a,
- DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b,
- DBG_BLOCK_ID_TA10_BY4 = 0x2c,
- DBG_BLOCK_ID_TA14_BY4 = 0x2d,
- DBG_BLOCK_ID_TA18_BY4 = 0x2e,
- DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f,
- DBG_BLOCK_ID_TD00_BY4 = 0x30,
- DBG_BLOCK_ID_TD04_BY4 = 0x31,
- DBG_BLOCK_ID_TD08_BY4 = 0x32,
- DBG_BLOCK_ID_UNUSED43_BY4 = 0x33,
- DBG_BLOCK_ID_TD10_BY4 = 0x34,
- DBG_BLOCK_ID_TD14_BY4 = 0x35,
- DBG_BLOCK_ID_TD18_BY4 = 0x36,
- DBG_BLOCK_ID_UNUSED47_BY4 = 0x37,
- DBG_BLOCK_ID_MCD0_BY4 = 0x38,
- DBG_BLOCK_ID_MCD4_BY4 = 0x39,
-} DebugBlockId_BY4;
-typedef enum DebugBlockId_BY8 {
- DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
- DBG_BLOCK_ID_CSC_BY8 = 0x1,
- DBG_BLOCK_ID_DMA0_BY8 = 0x2,
- DBG_BLOCK_ID_CP0_BY8 = 0x3,
- DBG_BLOCK_ID_VGT0_BY8 = 0x4,
- DBG_BLOCK_ID_TCAA_BY8 = 0x5,
- DBG_BLOCK_ID_SX0_BY8 = 0x6,
- DBG_BLOCK_ID_PC0_BY8 = 0x7,
- DBG_BLOCK_ID_SCB0_BY8 = 0x8,
- DBG_BLOCK_ID_BCI0_BY8 = 0x9,
- DBG_BLOCK_ID_CB00_BY8 = 0xa,
- DBG_BLOCK_ID_CB10_BY8 = 0xb,
- DBG_BLOCK_ID_TCP0_BY8 = 0xc,
- DBG_BLOCK_ID_TCP8_BY8 = 0xd,
- DBG_BLOCK_ID_TCP16_BY8 = 0xe,
- DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
- DBG_BLOCK_ID_DB00_BY8 = 0x10,
- DBG_BLOCK_ID_DB10_BY8 = 0x11,
- DBG_BLOCK_ID_TCC0_BY8 = 0x12,
- DBG_BLOCK_ID_SPS00_BY8 = 0x13,
- DBG_BLOCK_ID_TA00_BY8 = 0x14,
- DBG_BLOCK_ID_TA08_BY8 = 0x15,
- DBG_BLOCK_ID_TA10_BY8 = 0x16,
- DBG_BLOCK_ID_TA18_BY8 = 0x17,
- DBG_BLOCK_ID_TD00_BY8 = 0x18,
- DBG_BLOCK_ID_TD08_BY8 = 0x19,
- DBG_BLOCK_ID_TD10_BY8 = 0x1a,
- DBG_BLOCK_ID_TD18_BY8 = 0x1b,
- DBG_BLOCK_ID_MCD0_BY8 = 0x1c,
-} DebugBlockId_BY8;
-typedef enum DebugBlockId_BY16 {
- DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
- DBG_BLOCK_ID_DMA0_BY16 = 0x1,
- DBG_BLOCK_ID_VGT0_BY16 = 0x2,
- DBG_BLOCK_ID_SX0_BY16 = 0x3,
- DBG_BLOCK_ID_SCB0_BY16 = 0x4,
- DBG_BLOCK_ID_CB00_BY16 = 0x5,
- DBG_BLOCK_ID_TCP0_BY16 = 0x6,
- DBG_BLOCK_ID_TCP16_BY16 = 0x7,
- DBG_BLOCK_ID_DB00_BY16 = 0x8,
- DBG_BLOCK_ID_TCC0_BY16 = 0x9,
- DBG_BLOCK_ID_TA00_BY16 = 0xa,
- DBG_BLOCK_ID_TA10_BY16 = 0xb,
- DBG_BLOCK_ID_TD00_BY16 = 0xc,
- DBG_BLOCK_ID_TD10_BY16 = 0xd,
- DBG_BLOCK_ID_MCD0_BY16 = 0xe,
-} DebugBlockId_BY16;
-typedef enum CompareRef {
- REF_NEVER = 0x0,
- REF_LESS = 0x1,
- REF_EQUAL = 0x2,
- REF_LEQUAL = 0x3,
- REF_GREATER = 0x4,
- REF_NOTEQUAL = 0x5,
- REF_GEQUAL = 0x6,
- REF_ALWAYS = 0x7,
-} CompareRef;
-typedef enum ReadSize {
- READ_256_BITS = 0x0,
- READ_512_BITS = 0x1,
-} ReadSize;
-typedef enum DepthFormat {
- DEPTH_INVALID = 0x0,
- DEPTH_16 = 0x1,
- DEPTH_X8_24 = 0x2,
- DEPTH_8_24 = 0x3,
- DEPTH_X8_24_FLOAT = 0x4,
- DEPTH_8_24_FLOAT = 0x5,
- DEPTH_32_FLOAT = 0x6,
- DEPTH_X24_8_32_FLOAT = 0x7,
-} DepthFormat;
-typedef enum ZFormat {
- Z_INVALID = 0x0,
- Z_16 = 0x1,
- Z_24 = 0x2,
- Z_32_FLOAT = 0x3,
-} ZFormat;
-typedef enum StencilFormat {
- STENCIL_INVALID = 0x0,
- STENCIL_8 = 0x1,
-} StencilFormat;
-typedef enum CmaskMode {
- CMASK_CLEAR_NONE = 0x0,
- CMASK_CLEAR_ONE = 0x1,
- CMASK_CLEAR_ALL = 0x2,
- CMASK_ANY_EXPANDED = 0x3,
- CMASK_ALPHA0_FRAG1 = 0x4,
- CMASK_ALPHA0_FRAG2 = 0x5,
- CMASK_ALPHA0_FRAG4 = 0x6,
- CMASK_ALPHA0_FRAGS = 0x7,
- CMASK_ALPHA1_FRAG1 = 0x8,
- CMASK_ALPHA1_FRAG2 = 0x9,
- CMASK_ALPHA1_FRAG4 = 0xa,
- CMASK_ALPHA1_FRAGS = 0xb,
- CMASK_ALPHAX_FRAG1 = 0xc,
- CMASK_ALPHAX_FRAG2 = 0xd,
- CMASK_ALPHAX_FRAG4 = 0xe,
- CMASK_ALPHAX_FRAGS = 0xf,
-} CmaskMode;
-typedef enum QuadExportFormat {
- EXPORT_UNUSED = 0x0,
- EXPORT_32_R = 0x1,
- EXPORT_32_GR = 0x2,
- EXPORT_32_AR = 0x3,
- EXPORT_FP16_ABGR = 0x4,
- EXPORT_UNSIGNED16_ABGR = 0x5,
- EXPORT_SIGNED16_ABGR = 0x6,
- EXPORT_32_ABGR = 0x7,
-} QuadExportFormat;
-typedef enum QuadExportFormatOld {
- EXPORT_4P_32BPC_ABGR = 0x0,
- EXPORT_4P_16BPC_ABGR = 0x1,
- EXPORT_4P_32BPC_GR = 0x2,
- EXPORT_4P_32BPC_AR = 0x3,
- EXPORT_2P_32BPC_ABGR = 0x4,
- EXPORT_8P_32BPC_R = 0x5,
-} QuadExportFormatOld;
-typedef enum ColorFormat {
- COLOR_INVALID = 0x0,
- COLOR_8 = 0x1,
- COLOR_16 = 0x2,
- COLOR_8_8 = 0x3,
- COLOR_32 = 0x4,
- COLOR_16_16 = 0x5,
- COLOR_10_11_11 = 0x6,
- COLOR_11_11_10 = 0x7,
- COLOR_10_10_10_2 = 0x8,
- COLOR_2_10_10_10 = 0x9,
- COLOR_8_8_8_8 = 0xa,
- COLOR_32_32 = 0xb,
- COLOR_16_16_16_16 = 0xc,
- COLOR_RESERVED_13 = 0xd,
- COLOR_32_32_32_32 = 0xe,
- COLOR_RESERVED_15 = 0xf,
- COLOR_5_6_5 = 0x10,
- COLOR_1_5_5_5 = 0x11,
- COLOR_5_5_5_1 = 0x12,
- COLOR_4_4_4_4 = 0x13,
- COLOR_8_24 = 0x14,
- COLOR_24_8 = 0x15,
- COLOR_X24_8_32_FLOAT = 0x16,
- COLOR_RESERVED_23 = 0x17,
-} ColorFormat;
-typedef enum SurfaceFormat {
- FMT_INVALID = 0x0,
- FMT_8 = 0x1,
- FMT_16 = 0x2,
- FMT_8_8 = 0x3,
- FMT_32 = 0x4,
- FMT_16_16 = 0x5,
- FMT_10_11_11 = 0x6,
- FMT_11_11_10 = 0x7,
- FMT_10_10_10_2 = 0x8,
- FMT_2_10_10_10 = 0x9,
- FMT_8_8_8_8 = 0xa,
- FMT_32_32 = 0xb,
- FMT_16_16_16_16 = 0xc,
- FMT_32_32_32 = 0xd,
- FMT_32_32_32_32 = 0xe,
- FMT_RESERVED_4 = 0xf,
- FMT_5_6_5 = 0x10,
- FMT_1_5_5_5 = 0x11,
- FMT_5_5_5_1 = 0x12,
- FMT_4_4_4_4 = 0x13,
- FMT_8_24 = 0x14,
- FMT_24_8 = 0x15,
- FMT_X24_8_32_FLOAT = 0x16,
- FMT_RESERVED_33 = 0x17,
- FMT_11_11_10_FLOAT = 0x18,
- FMT_16_FLOAT = 0x19,
- FMT_32_FLOAT = 0x1a,
- FMT_16_16_FLOAT = 0x1b,
- FMT_8_24_FLOAT = 0x1c,
- FMT_24_8_FLOAT = 0x1d,
- FMT_32_32_FLOAT = 0x1e,
- FMT_10_11_11_FLOAT = 0x1f,
- FMT_16_16_16_16_FLOAT = 0x20,
- FMT_3_3_2 = 0x21,
- FMT_6_5_5 = 0x22,
- FMT_32_32_32_32_FLOAT = 0x23,
- FMT_RESERVED_36 = 0x24,
- FMT_1 = 0x25,
- FMT_1_REVERSED = 0x26,
- FMT_GB_GR = 0x27,
- FMT_BG_RG = 0x28,
- FMT_32_AS_8 = 0x29,
- FMT_32_AS_8_8 = 0x2a,
- FMT_5_9_9_9_SHAREDEXP = 0x2b,
- FMT_8_8_8 = 0x2c,
- FMT_16_16_16 = 0x2d,
- FMT_16_16_16_FLOAT = 0x2e,
- FMT_4_4 = 0x2f,
- FMT_32_32_32_FLOAT = 0x30,
- FMT_BC1 = 0x31,
- FMT_BC2 = 0x32,
- FMT_BC3 = 0x33,
- FMT_BC4 = 0x34,
- FMT_BC5 = 0x35,
- FMT_BC6 = 0x36,
- FMT_BC7 = 0x37,
- FMT_32_AS_32_32_32_32 = 0x38,
- FMT_APC3 = 0x39,
- FMT_APC4 = 0x3a,
- FMT_APC5 = 0x3b,
- FMT_APC6 = 0x3c,
- FMT_APC7 = 0x3d,
- FMT_CTX1 = 0x3e,
- FMT_RESERVED_63 = 0x3f,
-} SurfaceFormat;
-typedef enum BUF_DATA_FORMAT {
- BUF_DATA_FORMAT_INVALID = 0x0,
- BUF_DATA_FORMAT_8 = 0x1,
- BUF_DATA_FORMAT_16 = 0x2,
- BUF_DATA_FORMAT_8_8 = 0x3,
- BUF_DATA_FORMAT_32 = 0x4,
- BUF_DATA_FORMAT_16_16 = 0x5,
- BUF_DATA_FORMAT_10_11_11 = 0x6,
- BUF_DATA_FORMAT_11_11_10 = 0x7,
- BUF_DATA_FORMAT_10_10_10_2 = 0x8,
- BUF_DATA_FORMAT_2_10_10_10 = 0x9,
- BUF_DATA_FORMAT_8_8_8_8 = 0xa,
- BUF_DATA_FORMAT_32_32 = 0xb,
- BUF_DATA_FORMAT_16_16_16_16 = 0xc,
- BUF_DATA_FORMAT_32_32_32 = 0xd,
- BUF_DATA_FORMAT_32_32_32_32 = 0xe,
- BUF_DATA_FORMAT_RESERVED_15 = 0xf,
-} BUF_DATA_FORMAT;
-typedef enum IMG_DATA_FORMAT {
- IMG_DATA_FORMAT_INVALID = 0x0,
- IMG_DATA_FORMAT_8 = 0x1,
- IMG_DATA_FORMAT_16 = 0x2,
- IMG_DATA_FORMAT_8_8 = 0x3,
- IMG_DATA_FORMAT_32 = 0x4,
- IMG_DATA_FORMAT_16_16 = 0x5,
- IMG_DATA_FORMAT_10_11_11 = 0x6,
- IMG_DATA_FORMAT_11_11_10 = 0x7,
- IMG_DATA_FORMAT_10_10_10_2 = 0x8,
- IMG_DATA_FORMAT_2_10_10_10 = 0x9,
- IMG_DATA_FORMAT_8_8_8_8 = 0xa,
- IMG_DATA_FORMAT_32_32 = 0xb,
- IMG_DATA_FORMAT_16_16_16_16 = 0xc,
- IMG_DATA_FORMAT_32_32_32 = 0xd,
- IMG_DATA_FORMAT_32_32_32_32 = 0xe,
- IMG_DATA_FORMAT_RESERVED_15 = 0xf,
- IMG_DATA_FORMAT_5_6_5 = 0x10,
- IMG_DATA_FORMAT_1_5_5_5 = 0x11,
- IMG_DATA_FORMAT_5_5_5_1 = 0x12,
- IMG_DATA_FORMAT_4_4_4_4 = 0x13,
- IMG_DATA_FORMAT_8_24 = 0x14,
- IMG_DATA_FORMAT_24_8 = 0x15,
- IMG_DATA_FORMAT_X24_8_32 = 0x16,
- IMG_DATA_FORMAT_RESERVED_23 = 0x17,
- IMG_DATA_FORMAT_RESERVED_24 = 0x18,
- IMG_DATA_FORMAT_RESERVED_25 = 0x19,
- IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
- IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
- IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
- IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
- IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
- IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
- IMG_DATA_FORMAT_GB_GR = 0x20,
- IMG_DATA_FORMAT_BG_RG = 0x21,
- IMG_DATA_FORMAT_5_9_9_9 = 0x22,
- IMG_DATA_FORMAT_BC1 = 0x23,
- IMG_DATA_FORMAT_BC2 = 0x24,
- IMG_DATA_FORMAT_BC3 = 0x25,
- IMG_DATA_FORMAT_BC4 = 0x26,
- IMG_DATA_FORMAT_BC5 = 0x27,
- IMG_DATA_FORMAT_BC6 = 0x28,
- IMG_DATA_FORMAT_BC7 = 0x29,
- IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
- IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
- IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
- IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
- IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
- IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
- IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
- IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
- IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
- IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
- IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
- IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
- IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
- IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
- IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
- IMG_DATA_FORMAT_4_4 = 0x39,
- IMG_DATA_FORMAT_6_5_5 = 0x3a,
- IMG_DATA_FORMAT_1 = 0x3b,
- IMG_DATA_FORMAT_1_REVERSED = 0x3c,
- IMG_DATA_FORMAT_32_AS_8 = 0x3d,
- IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
- IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
-} IMG_DATA_FORMAT;
-typedef enum BUF_NUM_FORMAT {
- BUF_NUM_FORMAT_UNORM = 0x0,
- BUF_NUM_FORMAT_SNORM = 0x1,
- BUF_NUM_FORMAT_USCALED = 0x2,
- BUF_NUM_FORMAT_SSCALED = 0x3,
- BUF_NUM_FORMAT_UINT = 0x4,
- BUF_NUM_FORMAT_SINT = 0x5,
- BUF_NUM_FORMAT_SNORM_OGL = 0x6,
- BUF_NUM_FORMAT_FLOAT = 0x7,
-} BUF_NUM_FORMAT;
-typedef enum IMG_NUM_FORMAT {
- IMG_NUM_FORMAT_UNORM = 0x0,
- IMG_NUM_FORMAT_SNORM = 0x1,
- IMG_NUM_FORMAT_USCALED = 0x2,
- IMG_NUM_FORMAT_SSCALED = 0x3,
- IMG_NUM_FORMAT_UINT = 0x4,
- IMG_NUM_FORMAT_SINT = 0x5,
- IMG_NUM_FORMAT_SNORM_OGL = 0x6,
- IMG_NUM_FORMAT_FLOAT = 0x7,
- IMG_NUM_FORMAT_RESERVED_8 = 0x8,
- IMG_NUM_FORMAT_SRGB = 0x9,
- IMG_NUM_FORMAT_UBNORM = 0xa,
- IMG_NUM_FORMAT_UBNORM_OGL = 0xb,
- IMG_NUM_FORMAT_UBINT = 0xc,
- IMG_NUM_FORMAT_UBSCALED = 0xd,
- IMG_NUM_FORMAT_RESERVED_14 = 0xe,
- IMG_NUM_FORMAT_RESERVED_15 = 0xf,
-} IMG_NUM_FORMAT;
-typedef enum TileType {
- ARRAY_COLOR_TILE = 0x0,
- ARRAY_DEPTH_TILE = 0x1,
-} TileType;
-typedef enum NonDispTilingOrder {
- ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
- ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
-} NonDispTilingOrder;
-typedef enum MicroTileMode {
- ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
- ADDR_SURF_THIN_MICRO_TILING = 0x1,
- ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
- ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
- ADDR_SURF_THICK_MICRO_TILING = 0x4,
-} MicroTileMode;
-typedef enum TileSplit {
- ADDR_SURF_TILE_SPLIT_64B = 0x0,
- ADDR_SURF_TILE_SPLIT_128B = 0x1,
- ADDR_SURF_TILE_SPLIT_256B = 0x2,
- ADDR_SURF_TILE_SPLIT_512B = 0x3,
- ADDR_SURF_TILE_SPLIT_1KB = 0x4,
- ADDR_SURF_TILE_SPLIT_2KB = 0x5,
- ADDR_SURF_TILE_SPLIT_4KB = 0x6,
-} TileSplit;
-typedef enum SampleSplit {
- ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
- ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
- ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
- ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
-} SampleSplit;
-typedef enum PipeConfig {
- ADDR_SURF_P2 = 0x0,
- ADDR_SURF_P2_RESERVED0 = 0x1,
- ADDR_SURF_P2_RESERVED1 = 0x2,
- ADDR_SURF_P2_RESERVED2 = 0x3,
- ADDR_SURF_P4_8x16 = 0x4,
- ADDR_SURF_P4_16x16 = 0x5,
- ADDR_SURF_P4_16x32 = 0x6,
- ADDR_SURF_P4_32x32 = 0x7,
- ADDR_SURF_P8_16x16_8x16 = 0x8,
- ADDR_SURF_P8_16x32_8x16 = 0x9,
- ADDR_SURF_P8_32x32_8x16 = 0xa,
- ADDR_SURF_P8_16x32_16x16 = 0xb,
- ADDR_SURF_P8_32x32_16x16 = 0xc,
- ADDR_SURF_P8_32x32_16x32 = 0xd,
- ADDR_SURF_P8_32x64_32x32 = 0xe,
- ADDR_SURF_P8_RESERVED0 = 0xf,
- ADDR_SURF_P16_32x32_8x16 = 0x10,
- ADDR_SURF_P16_32x32_16x16 = 0x11,
-} PipeConfig;
-typedef enum NumBanks {
- ADDR_SURF_2_BANK = 0x0,
- ADDR_SURF_4_BANK = 0x1,
- ADDR_SURF_8_BANK = 0x2,
- ADDR_SURF_16_BANK = 0x3,
-} NumBanks;
-typedef enum BankWidth {
- ADDR_SURF_BANK_WIDTH_1 = 0x0,
- ADDR_SURF_BANK_WIDTH_2 = 0x1,
- ADDR_SURF_BANK_WIDTH_4 = 0x2,
- ADDR_SURF_BANK_WIDTH_8 = 0x3,
-} BankWidth;
-typedef enum BankHeight {
- ADDR_SURF_BANK_HEIGHT_1 = 0x0,
- ADDR_SURF_BANK_HEIGHT_2 = 0x1,
- ADDR_SURF_BANK_HEIGHT_4 = 0x2,
- ADDR_SURF_BANK_HEIGHT_8 = 0x3,
-} BankHeight;
-typedef enum BankWidthHeight {
- ADDR_SURF_BANK_WH_1 = 0x0,
- ADDR_SURF_BANK_WH_2 = 0x1,
- ADDR_SURF_BANK_WH_4 = 0x2,
- ADDR_SURF_BANK_WH_8 = 0x3,
-} BankWidthHeight;
-typedef enum MacroTileAspect {
- ADDR_SURF_MACRO_ASPECT_1 = 0x0,
- ADDR_SURF_MACRO_ASPECT_2 = 0x1,
- ADDR_SURF_MACRO_ASPECT_4 = 0x2,
- ADDR_SURF_MACRO_ASPECT_8 = 0x3,
-} MacroTileAspect;
-typedef enum TCC_CACHE_POLICIES {
- TCC_CACHE_POLICY_LRU = 0x0,
- TCC_CACHE_POLICY_STREAM = 0x1,
- TCC_CACHE_POLICY_BYPASS = 0x2,
-} TCC_CACHE_POLICIES;
-typedef enum PERFMON_COUNTER_MODE {
- PERFMON_COUNTER_MODE_ACCUM = 0x0,
- PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
- PERFMON_COUNTER_MODE_MAX = 0x2,
- PERFMON_COUNTER_MODE_DIRTY = 0x3,
- PERFMON_COUNTER_MODE_SAMPLE = 0x4,
- PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
- PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
- PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
- PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
- PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
- PERFMON_COUNTER_MODE_RESERVED = 0xf,
-} PERFMON_COUNTER_MODE;
-typedef enum PERFMON_SPM_MODE {
- PERFMON_SPM_MODE_OFF = 0x0,
- PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
- PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
- PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
- PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
- PERFMON_SPM_MODE_RESERVED_5 = 0x5,
- PERFMON_SPM_MODE_RESERVED_6 = 0x6,
- PERFMON_SPM_MODE_RESERVED_7 = 0x7,
- PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
- PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
- PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
-} PERFMON_SPM_MODE;
-typedef enum SurfaceTiling {
- ARRAY_LINEAR = 0x0,
- ARRAY_TILED = 0x1,
-} SurfaceTiling;
-typedef enum SurfaceArray {
- ARRAY_1D = 0x0,
- ARRAY_2D = 0x1,
- ARRAY_3D = 0x2,
- ARRAY_3D_SLICE = 0x3,
-} SurfaceArray;
-typedef enum ColorArray {
- ARRAY_2D_ALT_COLOR = 0x0,
- ARRAY_2D_COLOR = 0x1,
- ARRAY_3D_SLICE_COLOR = 0x3,
-} ColorArray;
-typedef enum DepthArray {
- ARRAY_2D_ALT_DEPTH = 0x0,
- ARRAY_2D_DEPTH = 0x1,
-} DepthArray;
-
-#endif /* SMU_7_1_0_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h
deleted file mode 100644
index cd7893065..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h
+++ /dev/null
@@ -1,5648 +0,0 @@
-/*
- * SMU_7_1_0 Register documentation
- *
- * Copyright (C) 2014 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef SMU_7_1_0_SH_MASK_H
-#define SMU_7_1_0_SH_MASK_H
-
-#define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
-#define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
-#define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
-#define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
-#define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
-#define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
-#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
-#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
-#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
-#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
-#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
-#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER__SHIFT 0xa
-#define CG_DCLK_STATUS__DCLK_STATUS_MASK 0x1
-#define CG_DCLK_STATUS__DCLK_STATUS__SHIFT 0x0
-#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG_MASK 0x2
-#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG__SHIFT 0x1
-#define CG_VCLK_CNTL__VCLK_DIVIDER_MASK 0x7f
-#define CG_VCLK_CNTL__VCLK_DIVIDER__SHIFT 0x0
-#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK 0x100
-#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8
-#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG_MASK 0x200
-#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG__SHIFT 0x9
-#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
-#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER__SHIFT 0xa
-#define CG_VCLK_STATUS__VCLK_STATUS_MASK 0x1
-#define CG_VCLK_STATUS__VCLK_STATUS__SHIFT 0x0
-#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG_MASK 0x2
-#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG__SHIFT 0x1
-#define CG_ECLK_CNTL__ECLK_DIVIDER_MASK 0x7f
-#define CG_ECLK_CNTL__ECLK_DIVIDER__SHIFT 0x0
-#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100
-#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8
-#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG_MASK 0x200
-#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG__SHIFT 0x9
-#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
-#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER__SHIFT 0xa
-#define CG_ECLK_STATUS__ECLK_STATUS_MASK 0x1
-#define CG_ECLK_STATUS__ECLK_STATUS__SHIFT 0x0
-#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG_MASK 0x2
-#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG__SHIFT 0x1
-#define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x7f
-#define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x0
-#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK 0x100
-#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8
-#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG_MASK 0x200
-#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG__SHIFT 0x9
-#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
-#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER__SHIFT 0xa
-#define GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK 0x1
-#define GCK_DFS_BYPASS_CNTL__BYPASSECLK__SHIFT 0x0
-#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK_MASK 0x2
-#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK__SHIFT 0x1
-#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK_MASK 0x4
-#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK__SHIFT 0x2
-#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8
-#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK__SHIFT 0x3
-#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK 0x10
-#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK__SHIFT 0x4
-#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK_MASK 0x20
-#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK__SHIFT 0x5
-#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK_MASK 0x40
-#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK__SHIFT 0x6
-#define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK 0x80
-#define GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT 0x7
-#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK 0x100
-#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8
-#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK_MASK 0x200
-#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK__SHIFT 0x9
-#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK_MASK 0x400
-#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK__SHIFT 0xa
-#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK 0x800
-#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK__SHIFT 0xb
-#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN_MASK 0x1000
-#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN__SHIFT 0xc
-#define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1
-#define CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT 0x0
-#define CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK 0x2
-#define CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT 0x1
-#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN_MASK 0x4
-#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN__SHIFT 0x2
-#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8
-#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT 0x3
-#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS_MASK 0x10
-#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS__SHIFT 0x4
-#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x7e0
-#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x5
-#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE_MASK 0x800
-#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE__SHIFT 0xb
-#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN_MASK 0x1000
-#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN__SHIFT 0xc
-#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK 0x7f00000
-#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT 0x14
-#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK_MASK 0x8000000
-#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK__SHIFT 0x1b
-#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN_MASK 0x10000000
-#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN__SHIFT 0x1c
-#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK 0x1ff
-#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT 0x0
-#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_MASK 0x800
-#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ__SHIFT 0xb
-#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK 0x400000
-#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT 0x16
-#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK 0x800000
-#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT 0x17
-#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG_MASK 0x1000000
-#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG__SHIFT 0x18
-#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG_MASK 0x2000000
-#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG__SHIFT 0x19
-#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK 0x4000000
-#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE__SHIFT 0x1a
-#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR_MASK 0x8000000
-#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR__SHIFT 0x1b
-#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE_MASK 0x10000000
-#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE__SHIFT 0x1c
-#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR_MASK 0x40000000
-#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR__SHIFT 0x1e
-#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x3ffffff
-#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x0
-#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK 0x10000000
-#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN__SHIFT 0x1c
-#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL_MASK 0xf
-#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL__SHIFT 0x0
-#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL_MASK 0x60
-#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL__SHIFT 0x5
-#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN_MASK 0x180
-#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN__SHIFT 0x7
-#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK 0x7fe00
-#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE__SHIFT 0x9
-#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS_MASK 0x200000
-#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS__SHIFT 0x15
-#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK_MASK 0x800000
-#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK__SHIFT 0x17
-#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL_MASK 0x1000000
-#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL__SHIFT 0x18
-#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN_MASK 0x2000000
-#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN__SHIFT 0x19
-#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_MASK 0xc000000
-#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT__SHIFT 0x1a
-#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT_MASK 0x70000000
-#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT__SHIFT 0x1c
-#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL_MASK 0x80000000
-#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL__SHIFT 0x1f
-#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS_MASK 0x1
-#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS__SHIFT 0x0
-#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x2
-#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN__SHIFT 0x1
-#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL_MASK 0xc
-#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL__SHIFT 0x2
-#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER_MASK 0x30
-#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER__SHIFT 0x4
-#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL_MASK 0xc0
-#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL__SHIFT 0x6
-#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x100
-#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x8
-#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX_MASK 0x200
-#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX__SHIFT 0x9
-#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT_MASK 0xff
-#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT__SHIFT 0x0
-#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT_MASK 0xff00
-#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT 0x8
-#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN_MASK 0x10000
-#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN__SHIFT 0x10
-#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN_MASK 0x1e0000
-#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN__SHIFT 0x11
-#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT_MASK 0x1e00000
-#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT__SHIFT 0x15
-#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR_MASK 0xfe000000
-#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19
-#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff
-#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0
-#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1
-#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0
-#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2
-#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT 0x1
-#define SPLL_CNTL_MODE__SPLL_TEST_MASK 0x4
-#define SPLL_CNTL_MODE__SPLL_TEST__SHIFT 0x2
-#define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x8
-#define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT 0x3
-#define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10
-#define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT 0x4
-#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK 0xc00
-#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0xa
-#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK 0xff000
-#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT 0xc
-#define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK 0x10000000
-#define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT 0x1c
-#define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK 0x60000000
-#define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x1d
-#define CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK 0x1
-#define CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT 0x0
-#define CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK 0xfff0
-#define CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT 0x4
-#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK 0x3ffffff
-#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT 0x0
-#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0xff00
-#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT 0x8
-#define CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK 0x2
-#define CG_CLKPIN_CNTL__XTALIN_DIVIDE__SHIFT 0x1
-#define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x4
-#define CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT 0x2
-#define CG_CLKPIN_CNTL_2__ENABLE_XCLK_MASK 0x1
-#define CG_CLKPIN_CNTL_2__ENABLE_XCLK__SHIFT 0x0
-#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK 0x8
-#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT 0x3
-#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x100
-#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK__SHIFT 0x8
-#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN_MASK 0x4000
-#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN__SHIFT 0xe
-#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE_MASK 0x8000
-#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE__SHIFT 0xf
-#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN_MASK 0x10000
-#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN__SHIFT 0x10
-#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE_MASK 0x20000
-#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE__SHIFT 0x11
-#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN_MASK 0x40000
-#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN__SHIFT 0x12
-#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE_MASK 0x80000
-#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE__SHIFT 0x13
-#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN_MASK 0x100000
-#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN__SHIFT 0x14
-#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE_MASK 0x200000
-#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE__SHIFT 0x15
-#define CG_CLKPIN_CNTL_2__CML_CTRL_MASK 0xc00000
-#define CG_CLKPIN_CNTL_2__CML_CTRL__SHIFT 0x16
-#define CG_CLKPIN_CNTL_2__CLK_SPARE_MASK 0xff000000
-#define CG_CLKPIN_CNTL_2__CLK_SPARE__SHIFT 0x18
-#define CG_CLKPIN_CNTL_DC__OSC_EN_MASK 0x1
-#define CG_CLKPIN_CNTL_DC__OSC_EN__SHIFT 0x0
-#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN_MASK 0x6
-#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN__SHIFT 0x1
-#define CG_CLKPIN_CNTL_DC__XTALIN_SEL_MASK 0x1c00
-#define CG_CLKPIN_CNTL_DC__XTALIN_SEL__SHIFT 0xa
-#define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0xff
-#define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x0
-#define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0xff00
-#define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x8
-#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN_MASK 0x10000
-#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN__SHIFT 0x10
-#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK 0xff
-#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT 0x0
-#define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00
-#define MISC_CLK_CTRL__ZCLK_SEL__SHIFT 0x8
-#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK 0xff0000
-#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10
-#define GCK_PLL_TEST_CNTL__TST_SRC_SEL_MASK 0x1f
-#define GCK_PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0
-#define GCK_PLL_TEST_CNTL__TST_REF_SEL_MASK 0x3e0
-#define GCK_PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x5
-#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x1fc00
-#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0xa
-#define GCK_PLL_TEST_CNTL__TST_RESET_MASK 0x20000
-#define GCK_PLL_TEST_CNTL__TST_RESET__SHIFT 0x11
-#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE_MASK 0x40000
-#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT 0x12
-#define GCK_PLL_TEST_CNTL_2__TEST_COUNT_MASK 0xfffe0000
-#define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT 0x11
-#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL_MASK 0x7
-#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL__SHIFT 0x0
-#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL_MASK 0x38
-#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL__SHIFT 0x3
-#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL_MASK 0x1c0
-#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL__SHIFT 0x6
-#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL_MASK 0xe00
-#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL__SHIFT 0x9
-#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL_MASK 0x7000
-#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL__SHIFT 0xc
-#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL_MASK 0x38000
-#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL__SHIFT 0xf
-#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL_MASK 0x1c0000
-#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL__SHIFT 0x12
-#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL_MASK 0xe00000
-#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL__SHIFT 0x15
-#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL_MASK 0x7000000
-#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL__SHIFT 0x18
-#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL_MASK 0x38000000
-#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL__SHIFT 0x1b
-#define SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
-#define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
-#define SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
-#define SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
-#define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff
-#define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0
-#define SMC_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff
-#define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0
-#define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff
-#define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0
-#define SMC_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff
-#define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0
-#define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff
-#define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0
-#define SMC_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff
-#define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0
-#define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff
-#define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0
-#define SMC_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff
-#define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0
-#define SMC_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff
-#define SMC_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0
-#define SMC_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff
-#define SMC_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0
-#define SMC_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff
-#define SMC_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0
-#define SMC_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff
-#define SMC_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0
-#define SMC_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff
-#define SMC_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0
-#define SMC_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff
-#define SMC_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0
-#define SMC_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff
-#define SMC_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0
-#define SMC_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff
-#define SMC_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0
-#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x1
-#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x0
-#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x2
-#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x1
-#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x4
-#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x2
-#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x8
-#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3
-#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK 0x10
-#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT 0x4
-#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK 0x20
-#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT 0x5
-#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK 0x40
-#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT 0x6
-#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK 0x80
-#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT 0x7
-#define SMC_MESSAGE_0__SMC_MSG_MASK 0xffff
-#define SMC_MESSAGE_0__SMC_MSG__SHIFT 0x0
-#define SMC_RESP_0__SMC_RESP_MASK 0xffff
-#define SMC_RESP_0__SMC_RESP__SHIFT 0x0
-#define SMC_MESSAGE_1__SMC_MSG_MASK 0xffff
-#define SMC_MESSAGE_1__SMC_MSG__SHIFT 0x0
-#define SMC_RESP_1__SMC_RESP_MASK 0xffff
-#define SMC_RESP_1__SMC_RESP__SHIFT 0x0
-#define SMC_MESSAGE_2__SMC_MSG_MASK 0xffff
-#define SMC_MESSAGE_2__SMC_MSG__SHIFT 0x0
-#define SMC_RESP_2__SMC_RESP_MASK 0xffff
-#define SMC_RESP_2__SMC_RESP__SHIFT 0x0
-#define SMC_MESSAGE_3__SMC_MSG_MASK 0xffff
-#define SMC_MESSAGE_3__SMC_MSG__SHIFT 0x0
-#define SMC_RESP_3__SMC_RESP_MASK 0xffff
-#define SMC_RESP_3__SMC_RESP__SHIFT 0x0
-#define SMC_MESSAGE_4__SMC_MSG_MASK 0xffff
-#define SMC_MESSAGE_4__SMC_MSG__SHIFT 0x0
-#define SMC_RESP_4__SMC_RESP_MASK 0xffff
-#define SMC_RESP_4__SMC_RESP__SHIFT 0x0
-#define SMC_MESSAGE_5__SMC_MSG_MASK 0xffff
-#define SMC_MESSAGE_5__SMC_MSG__SHIFT 0x0
-#define SMC_RESP_5__SMC_RESP_MASK 0xffff
-#define SMC_RESP_5__SMC_RESP__SHIFT 0x0
-#define SMC_MESSAGE_6__SMC_MSG_MASK 0xffff
-#define SMC_MESSAGE_6__SMC_MSG__SHIFT 0x0
-#define SMC_RESP_6__SMC_RESP_MASK 0xffff
-#define SMC_RESP_6__SMC_RESP__SHIFT 0x0
-#define SMC_MESSAGE_7__SMC_MSG_MASK 0xffff
-#define SMC_MESSAGE_7__SMC_MSG__SHIFT 0x0
-#define SMC_RESP_7__SMC_RESP_MASK 0xffff
-#define SMC_RESP_7__SMC_RESP__SHIFT 0x0
-#define SMC_MSG_ARG_0__SMC_MSG_ARG_MASK 0xffffffff
-#define SMC_MSG_ARG_0__SMC_MSG_ARG__SHIFT 0x0
-#define SMC_MSG_ARG_1__SMC_MSG_ARG_MASK 0xffffffff
-#define SMC_MSG_ARG_1__SMC_MSG_ARG__SHIFT 0x0
-#define SMC_MSG_ARG_2__SMC_MSG_ARG_MASK 0xffffffff
-#define SMC_MSG_ARG_2__SMC_MSG_ARG__SHIFT 0x0
-#define SMC_MSG_ARG_3__SMC_MSG_ARG_MASK 0xffffffff
-#define SMC_MSG_ARG_3__SMC_MSG_ARG__SHIFT 0x0
-#define SMC_MSG_ARG_4__SMC_MSG_ARG_MASK 0xffffffff
-#define SMC_MSG_ARG_4__SMC_MSG_ARG__SHIFT 0x0
-#define SMC_MSG_ARG_5__SMC_MSG_ARG_MASK 0xffffffff
-#define SMC_MSG_ARG_5__SMC_MSG_ARG__SHIFT 0x0
-#define SMC_MSG_ARG_6__SMC_MSG_ARG_MASK 0xffffffff
-#define SMC_MSG_ARG_6__SMC_MSG_ARG__SHIFT 0x0
-#define SMC_MSG_ARG_7__SMC_MSG_ARG_MASK 0xffffffff
-#define SMC_MSG_ARG_7__SMC_MSG_ARG__SHIFT 0x0
-#define SMC_MESSAGE_8__SMC_MSG_MASK 0xffff
-#define SMC_MESSAGE_8__SMC_MSG__SHIFT 0x0
-#define SMC_RESP_8__SMC_RESP_MASK 0xffff
-#define SMC_RESP_8__SMC_RESP__SHIFT 0x0
-#define SMC_MESSAGE_9__SMC_MSG_MASK 0xffff
-#define SMC_MESSAGE_9__SMC_MSG__SHIFT 0x0
-#define SMC_RESP_9__SMC_RESP_MASK 0xffff
-#define SMC_RESP_9__SMC_RESP__SHIFT 0x0
-#define SMC_MESSAGE_10__SMC_MSG_MASK 0xffff
-#define SMC_MESSAGE_10__SMC_MSG__SHIFT 0x0
-#define SMC_RESP_10__SMC_RESP_MASK 0xffff
-#define SMC_RESP_10__SMC_RESP__SHIFT 0x0
-#define SMC_MESSAGE_11__SMC_MSG_MASK 0xffff
-#define SMC_MESSAGE_11__SMC_MSG__SHIFT 0x0
-#define SMC_RESP_11__SMC_RESP_MASK 0xffff
-#define SMC_RESP_11__SMC_RESP__SHIFT 0x0
-#define SMC_MSG_ARG_8__SMC_MSG_ARG_MASK 0xffffffff
-#define SMC_MSG_ARG_8__SMC_MSG_ARG__SHIFT 0x0
-#define SMC_MSG_ARG_9__SMC_MSG_ARG_MASK 0xffffffff
-#define SMC_MSG_ARG_9__SMC_MSG_ARG__SHIFT 0x0
-#define SMC_MSG_ARG_10__SMC_MSG_ARG_MASK 0xffffffff
-#define SMC_MSG_ARG_10__SMC_MSG_ARG__SHIFT 0x0
-#define SMC_MSG_ARG_11__SMC_MSG_ARG_MASK 0xffffffff
-#define SMC_MSG_ARG_11__SMC_MSG_ARG__SHIFT 0x0
-#define SMC_SYSCON_RESET_CNTL__rst_reg_MASK 0x1
-#define SMC_SYSCON_RESET_CNTL__rst_reg__SHIFT 0x0
-#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override_MASK 0x2
-#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override__SHIFT 0x1
-#define SMC_SYSCON_RESET_CNTL__RegReset_MASK 0x40000000
-#define SMC_SYSCON_RESET_CNTL__RegReset__SHIFT 0x1e
-#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK 0x1
-#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable__SHIFT 0x0
-#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en_MASK 0x2
-#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en__SHIFT 0x1
-#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout_MASK 0xffff00
-#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout__SHIFT 0x8
-#define SMC_SYSCON_CLOCK_CNTL_0__cken_MASK 0x1000000
-#define SMC_SYSCON_CLOCK_CNTL_0__cken__SHIFT 0x18
-#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable_MASK 0x1
-#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable__SHIFT 0x0
-#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq_MASK 0xffffffff
-#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq__SHIFT 0x0
-#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg_MASK 0xffffffff
-#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg__SHIFT 0x0
-#define SMC_PC_C__smc_pc_c_MASK 0xffffffff
-#define SMC_PC_C__smc_pc_c__SHIFT 0x0
-#define SMC_SCRATCH9__SCRATCH_VALUE_MASK 0xffffffff
-#define SMC_SCRATCH9__SCRATCH_VALUE__SHIFT 0x0
-#define GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x1
-#define GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0
-#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN_MASK 0xf
-#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN__SHIFT 0x0
-#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP_MASK 0xf0
-#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP__SHIFT 0x4
-#define GPIOPAD_MASK__GPIO_MASK_MASK 0x7fffffff
-#define GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0
-#define GPIOPAD_A__GPIO_A_MASK 0x7fffffff
-#define GPIOPAD_A__GPIO_A__SHIFT 0x0
-#define GPIOPAD_EN__GPIO_EN_MASK 0x7fffffff
-#define GPIOPAD_EN__GPIO_EN__SHIFT 0x0
-#define GPIOPAD_Y__GPIO_Y_MASK 0x7fffffff
-#define GPIOPAD_Y__GPIO_Y__SHIFT 0x0
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x1
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x2
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x4
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x8
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x10
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x20
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x40
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x80
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x100
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x200
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x400
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x800
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x1000
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x2000
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x4000
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x8000
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x10000
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x20000
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x40000
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x80000
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x100000
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x200000
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x400000
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x800000
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x1000000
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x2000000
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x4000000
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x8000000
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000
-#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e
-#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1fffffff
-#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0
-#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000
-#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f
-#define GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1fffffff
-#define GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0
-#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000
-#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x1
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x2
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x4
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x8
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x10
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x20
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x40
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x80
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x100
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x200
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x400
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x800
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x1000
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x2000
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x4000
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x8000
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x10000
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x20000
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x40000
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x80000
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x100000
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x200000
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x400000
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x800000
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x1000000
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x2000000
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x4000000
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x8000000
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000
-#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c
-#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000
-#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f
-#define GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1fffffff
-#define GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0
-#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000
-#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f
-#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1fffffff
-#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0
-#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000
-#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f
-#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1fffffff
-#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0
-#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000
-#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f
-#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL_MASK 0x1f
-#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL__SHIFT 0x0
-#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK 0x20
-#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT 0x5
-#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ_MASK 0x40
-#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ__SHIFT 0x6
-#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL_MASK 0x7fffffff
-#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL__SHIFT 0x0
-#define GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7fffffff
-#define GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0
-#define GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7fffffff
-#define GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0
-#define CG_FPS_CNT__FPS_CNT_MASK 0xff
-#define CG_FPS_CNT__FPS_CNT__SHIFT 0x0
-#define SMU_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
-#define SMU_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
-#define SMU_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
-#define SMU_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
-#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req_MASK 0x1
-#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req__SHIFT 0x0
-#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done_MASK 0x2
-#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done__SHIFT 0x1
-#define RCU_UC_EVENTS__drv_rst_mode_MASK 0x4
-#define RCU_UC_EVENTS__drv_rst_mode__SHIFT 0x2
-#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid_MASK 0x8
-#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid__SHIFT 0x3
-#define RCU_UC_EVENTS__TP_Tester_MASK 0x40
-#define RCU_UC_EVENTS__TP_Tester__SHIFT 0x6
-#define RCU_UC_EVENTS__boot_seq_done_MASK 0x80
-#define RCU_UC_EVENTS__boot_seq_done__SHIFT 0x7
-#define RCU_UC_EVENTS__sclk_deep_sleep_exit_MASK 0x100
-#define RCU_UC_EVENTS__sclk_deep_sleep_exit__SHIFT 0x8
-#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE_MASK 0x200
-#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE__SHIFT 0x9
-#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE_MASK 0x400
-#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE__SHIFT 0xa
-#define RCU_UC_EVENTS__FCH_HALT_MASK 0x800
-#define RCU_UC_EVENTS__FCH_HALT__SHIFT 0xb
-#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown_MASK 0x2000
-#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown__SHIFT 0xd
-#define RCU_UC_EVENTS__INTERRUPTS_ENABLED_MASK 0x10000
-#define RCU_UC_EVENTS__INTERRUPTS_ENABLED__SHIFT 0x10
-#define RCU_UC_EVENTS__RCU_DtmCnt0_Done_MASK 0x20000
-#define RCU_UC_EVENTS__RCU_DtmCnt0_Done__SHIFT 0x11
-#define RCU_UC_EVENTS__RCU_DtmCnt1_Done_MASK 0x40000
-#define RCU_UC_EVENTS__RCU_DtmCnt1_Done__SHIFT 0x12
-#define RCU_UC_EVENTS__RCU_DtmCnt2_Done_MASK 0x80000
-#define RCU_UC_EVENTS__RCU_DtmCnt2_Done__SHIFT 0x13
-#define RCU_UC_EVENTS__irq31_sel_MASK 0x3000000
-#define RCU_UC_EVENTS__irq31_sel__SHIFT 0x18
-#define RCU_MISC_CTRL__REG_DRV_RST_MODE_MASK 0x2
-#define RCU_MISC_CTRL__REG_DRV_RST_MODE__SHIFT 0x1
-#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS_MASK 0x8
-#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS__SHIFT 0x3
-#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE_MASK 0x10
-#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE__SHIFT 0x4
-#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE_MASK 0x20
-#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE__SHIFT 0x5
-#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE_MASK 0x100
-#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE__SHIFT 0x8
-#define RCU_MISC_CTRL__BREAK_PT1_DONE_MASK 0x10000
-#define RCU_MISC_CTRL__BREAK_PT1_DONE__SHIFT 0x10
-#define RCU_MISC_CTRL__BREAK_PT2_DONE_MASK 0x20000
-#define RCU_MISC_CTRL__BREAK_PT2_DONE__SHIFT 0x11
-#define RCU_MISC_CTRL__SAMU_START_MASK 0x400000
-#define RCU_MISC_CTRL__SAMU_START__SHIFT 0x16
-#define RCU_MISC_CTRL__RST_PULSE_WIDTH_MASK 0xff800000
-#define RCU_MISC_CTRL__RST_PULSE_WIDTH__SHIFT 0x17
-#define CC_RCU_FUSES__GPU_DIS_MASK 0x2
-#define CC_RCU_FUSES__GPU_DIS__SHIFT 0x1
-#define CC_RCU_FUSES__DEBUG_DISABLE_MASK 0x4
-#define CC_RCU_FUSES__DEBUG_DISABLE__SHIFT 0x2
-#define CC_RCU_FUSES__EFUSE_RD_DISABLE_MASK 0x10
-#define CC_RCU_FUSES__EFUSE_RD_DISABLE__SHIFT 0x4
-#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS_MASK 0x20
-#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS__SHIFT 0x5
-#define CC_RCU_FUSES__DRV_RST_MODE_MASK 0x40
-#define CC_RCU_FUSES__DRV_RST_MODE__SHIFT 0x6
-#define CC_RCU_FUSES__ROM_DIS_MASK 0x80
-#define CC_RCU_FUSES__ROM_DIS__SHIFT 0x7
-#define CC_RCU_FUSES__JPC_REP_DISABLE_MASK 0x100
-#define CC_RCU_FUSES__JPC_REP_DISABLE__SHIFT 0x8
-#define CC_RCU_FUSES__RCU_BREAK_POINT1_MASK 0x200
-#define CC_RCU_FUSES__RCU_BREAK_POINT1__SHIFT 0x9
-#define CC_RCU_FUSES__RCU_BREAK_POINT2_MASK 0x400
-#define CC_RCU_FUSES__RCU_BREAK_POINT2__SHIFT 0xa
-#define CC_RCU_FUSES__PHY_FUSE_VALID_MASK 0x4000
-#define CC_RCU_FUSES__PHY_FUSE_VALID__SHIFT 0xe
-#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE_MASK 0x8000
-#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE__SHIFT 0xf
-#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE_MASK 0x10000
-#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE__SHIFT 0x10
-#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE_MASK 0x20000
-#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE__SHIFT 0x11
-#define CC_RCU_FUSES__XFIRE_DISABLE_MASK 0x40000
-#define CC_RCU_FUSES__XFIRE_DISABLE__SHIFT 0x12
-#define CC_RCU_FUSES__SAMU_FUSE_DISABLE_MASK 0x80000
-#define CC_RCU_FUSES__SAMU_FUSE_DISABLE__SHIFT 0x13
-#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE_MASK 0x100000
-#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE__SHIFT 0x14
-#define CC_RCU_FUSES__MEM_HARDREP_EN_MASK 0x400000
-#define CC_RCU_FUSES__MEM_HARDREP_EN__SHIFT 0x16
-#define CC_RCU_FUSES__PCIE_INIT_DISABLE_MASK 0x800000
-#define CC_RCU_FUSES__PCIE_INIT_DISABLE__SHIFT 0x17
-#define CC_RCU_FUSES__DSMU_DISABLE_MASK 0x1000000
-#define CC_RCU_FUSES__DSMU_DISABLE__SHIFT 0x18
-#define CC_RCU_FUSES__RCU_SPARE_MASK 0xfe000000
-#define CC_RCU_FUSES__RCU_SPARE__SHIFT 0x19
-#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE_MASK 0x2
-#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE__SHIFT 0x1
-#define CC_SMU_MISC_FUSES__MinSClkDid_MASK 0x1fc
-#define CC_SMU_MISC_FUSES__MinSClkDid__SHIFT 0x2
-#define CC_SMU_MISC_FUSES__MISC_SPARE_MASK 0x600
-#define CC_SMU_MISC_FUSES__MISC_SPARE__SHIFT 0x9
-#define CC_SMU_MISC_FUSES__PostResetGnbClkDid_MASK 0x3f800
-#define CC_SMU_MISC_FUSES__PostResetGnbClkDid__SHIFT 0xb
-#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half_MASK 0x40000
-#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half__SHIFT 0x12
-#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half_MASK 0x80000
-#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half__SHIFT 0x13
-#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half_MASK 0x100000
-#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half__SHIFT 0x14
-#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half_MASK 0x200000
-#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half__SHIFT 0x15
-#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis_MASK 0x400000
-#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis__SHIFT 0x16
-#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis_MASK 0x800000
-#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis__SHIFT 0x17
-#define CC_SMU_MISC_FUSES__VCE_DISABLE_MASK 0x8000000
-#define CC_SMU_MISC_FUSES__VCE_DISABLE__SHIFT 0x1b
-#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE_MASK 0x10000000
-#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE__SHIFT 0x1c
-#define CC_SMU_MISC_FUSES__GNB_SPARE_MASK 0x60000000
-#define CC_SMU_MISC_FUSES__GNB_SPARE__SHIFT 0x1d
-#define CC_SCLK_VID_FUSES__SClkVid0_MASK 0xff
-#define CC_SCLK_VID_FUSES__SClkVid0__SHIFT 0x0
-#define CC_SCLK_VID_FUSES__SClkVid1_MASK 0xff00
-#define CC_SCLK_VID_FUSES__SClkVid1__SHIFT 0x8
-#define CC_SCLK_VID_FUSES__SClkVid2_MASK 0xff0000
-#define CC_SCLK_VID_FUSES__SClkVid2__SHIFT 0x10
-#define CC_SCLK_VID_FUSES__SClkVid3_MASK 0xff000000
-#define CC_SCLK_VID_FUSES__SClkVid3__SHIFT 0x18
-#define CC_GIO_IOCCFG_FUSES__NB_REV_ID_MASK 0x7fe
-#define CC_GIO_IOCCFG_FUSES__NB_REV_ID__SHIFT 0x1
-#define CC_GIO_IOC_FUSES__IOC_FUSES_MASK 0x3e
-#define CC_GIO_IOC_FUSES__IOC_FUSES__SHIFT 0x1
-#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2_MASK 0x3e
-#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2__SHIFT 0x1
-#define CC_SMU_TST_EFUSE1_MISC__RME_MASK 0x40
-#define CC_SMU_TST_EFUSE1_MISC__RME__SHIFT 0x6
-#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE_MASK 0x80
-#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE__SHIFT 0x7
-#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE_MASK 0x100
-#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE__SHIFT 0x8
-#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE_MASK 0x200
-#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE__SHIFT 0x9
-#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS_MASK 0x400
-#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS__SHIFT 0xa
-#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE_MASK 0x800
-#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE__SHIFT 0xb
-#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA_MASK 0x1000
-#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA__SHIFT 0xc
-#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB_MASK 0x2000
-#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB__SHIFT 0xd
-#define CC_SMU_TST_EFUSE1_MISC__RM_RF8_MASK 0x4000
-#define CC_SMU_TST_EFUSE1_MISC__RM_RF8__SHIFT 0xe
-#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1_MASK 0x400000
-#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1__SHIFT 0x16
-#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2_MASK 0x800000
-#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2__SHIFT 0x17
-#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3_MASK 0x1000000
-#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3__SHIFT 0x18
-#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE_MASK 0x2000000
-#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE__SHIFT 0x19
-#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE_MASK 0x4000000
-#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE__SHIFT 0x1a
-#define CC_TST_ID_STRAPS__DEVICE_ID_MASK 0xffff0
-#define CC_TST_ID_STRAPS__DEVICE_ID__SHIFT 0x4
-#define CC_TST_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000
-#define CC_TST_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14
-#define CC_TST_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000
-#define CC_TST_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18
-#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT_MASK 0x2
-#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT__SHIFT 0x1
-#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ_MASK 0xffffffff
-#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ__SHIFT 0x0
-#define SMU_STATUS__SMU_DONE_MASK 0x1
-#define SMU_STATUS__SMU_DONE__SHIFT 0x0
-#define SMU_STATUS__SMU_PASS_MASK 0x2
-#define SMU_STATUS__SMU_PASS__SHIFT 0x1
-#define SMU_FIRMWARE__SMU_IN_PROG_MASK 0x1
-#define SMU_FIRMWARE__SMU_IN_PROG__SHIFT 0x0
-#define SMU_FIRMWARE__SMU_RD_DONE_MASK 0x6
-#define SMU_FIRMWARE__SMU_RD_DONE__SHIFT 0x1
-#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN_MASK 0x8
-#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN__SHIFT 0x3
-#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN_MASK 0x10
-#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN__SHIFT 0x4
-#define SMU_FIRMWARE__SMU_counter_MASK 0xf00
-#define SMU_FIRMWARE__SMU_counter__SHIFT 0x8
-#define SMU_FIRMWARE__SMU_MODE_MASK 0x10000
-#define SMU_FIRMWARE__SMU_MODE__SHIFT 0x10
-#define SMU_FIRMWARE__SMU_SEL_MASK 0x20000
-#define SMU_FIRMWARE__SMU_SEL__SHIFT 0x11
-#define SMU_INPUT_DATA__START_ADDR_MASK 0x7fffffff
-#define SMU_INPUT_DATA__START_ADDR__SHIFT 0x0
-#define SMU_INPUT_DATA__AUTO_START_MASK 0x80000000
-#define SMU_INPUT_DATA__AUTO_START__SHIFT 0x1f
-#define SMU_EFUSE_0__EFUSE_DATA_MASK 0xffffffff
-#define SMU_EFUSE_0__EFUSE_DATA__SHIFT 0x0
-#define DPM_TABLE_1__GraphicsPIDController_Ki_MASK 0xffffffff
-#define DPM_TABLE_1__GraphicsPIDController_Ki__SHIFT 0x0
-#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim_MASK 0xffffffff
-#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim__SHIFT 0x0
-#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim_MASK 0xffffffff
-#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim__SHIFT 0x0
-#define DPM_TABLE_4__GraphicsPIDController_StatePrecision_MASK 0xffffffff
-#define DPM_TABLE_4__GraphicsPIDController_StatePrecision__SHIFT 0x0
-#define DPM_TABLE_5__GraphicsPIDController_LfPrecision_MASK 0xffffffff
-#define DPM_TABLE_5__GraphicsPIDController_LfPrecision__SHIFT 0x0
-#define DPM_TABLE_6__GraphicsPIDController_LfOffset_MASK 0xffffffff
-#define DPM_TABLE_6__GraphicsPIDController_LfOffset__SHIFT 0x0
-#define DPM_TABLE_7__GraphicsPIDController_MaxState_MASK 0xffffffff
-#define DPM_TABLE_7__GraphicsPIDController_MaxState__SHIFT 0x0
-#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction_MASK 0xffffffff
-#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction__SHIFT 0x0
-#define DPM_TABLE_9__GraphicsPIDController_StateShift_MASK 0xffffffff
-#define DPM_TABLE_9__GraphicsPIDController_StateShift__SHIFT 0x0
-#define DPM_TABLE_10__MemoryPIDController_Ki_MASK 0xffffffff
-#define DPM_TABLE_10__MemoryPIDController_Ki__SHIFT 0x0
-#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim_MASK 0xffffffff
-#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim__SHIFT 0x0
-#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim_MASK 0xffffffff
-#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim__SHIFT 0x0
-#define DPM_TABLE_13__MemoryPIDController_StatePrecision_MASK 0xffffffff
-#define DPM_TABLE_13__MemoryPIDController_StatePrecision__SHIFT 0x0
-#define DPM_TABLE_14__MemoryPIDController_LfPrecision_MASK 0xffffffff
-#define DPM_TABLE_14__MemoryPIDController_LfPrecision__SHIFT 0x0
-#define DPM_TABLE_15__MemoryPIDController_LfOffset_MASK 0xffffffff
-#define DPM_TABLE_15__MemoryPIDController_LfOffset__SHIFT 0x0
-#define DPM_TABLE_16__MemoryPIDController_MaxState_MASK 0xffffffff
-#define DPM_TABLE_16__MemoryPIDController_MaxState__SHIFT 0x0
-#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction_MASK 0xffffffff
-#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction__SHIFT 0x0
-#define DPM_TABLE_18__MemoryPIDController_StateShift_MASK 0xffffffff
-#define DPM_TABLE_18__MemoryPIDController_StateShift__SHIFT 0x0
-#define DPM_TABLE_19__LinkPIDController_Ki_MASK 0xffffffff
-#define DPM_TABLE_19__LinkPIDController_Ki__SHIFT 0x0
-#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim_MASK 0xffffffff
-#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim__SHIFT 0x0
-#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim_MASK 0xffffffff
-#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim__SHIFT 0x0
-#define DPM_TABLE_22__LinkPIDController_StatePrecision_MASK 0xffffffff
-#define DPM_TABLE_22__LinkPIDController_StatePrecision__SHIFT 0x0
-#define DPM_TABLE_23__LinkPIDController_LfPrecision_MASK 0xffffffff
-#define DPM_TABLE_23__LinkPIDController_LfPrecision__SHIFT 0x0
-#define DPM_TABLE_24__LinkPIDController_LfOffset_MASK 0xffffffff
-#define DPM_TABLE_24__LinkPIDController_LfOffset__SHIFT 0x0
-#define DPM_TABLE_25__LinkPIDController_MaxState_MASK 0xffffffff
-#define DPM_TABLE_25__LinkPIDController_MaxState__SHIFT 0x0
-#define DPM_TABLE_26__LinkPIDController_MaxLfFraction_MASK 0xffffffff
-#define DPM_TABLE_26__LinkPIDController_MaxLfFraction__SHIFT 0x0
-#define DPM_TABLE_27__LinkPIDController_StateShift_MASK 0xffffffff
-#define DPM_TABLE_27__LinkPIDController_StateShift__SHIFT 0x0
-#define DPM_TABLE_28__SystemFlags_MASK 0xffffffff
-#define DPM_TABLE_28__SystemFlags__SHIFT 0x0
-#define DPM_TABLE_29__SmioMaskVddcVid_MASK 0xffffffff
-#define DPM_TABLE_29__SmioMaskVddcVid__SHIFT 0x0
-#define DPM_TABLE_30__SmioMaskVddcPhase_MASK 0xffffffff
-#define DPM_TABLE_30__SmioMaskVddcPhase__SHIFT 0x0
-#define DPM_TABLE_31__SmioMaskVddciVid_MASK 0xffffffff
-#define DPM_TABLE_31__SmioMaskVddciVid__SHIFT 0x0
-#define DPM_TABLE_32__SmioMaskMvddVid_MASK 0xffffffff
-#define DPM_TABLE_32__SmioMaskMvddVid__SHIFT 0x0
-#define DPM_TABLE_33__VddcLevelCount_MASK 0xffffffff
-#define DPM_TABLE_33__VddcLevelCount__SHIFT 0x0
-#define DPM_TABLE_34__VddciLevelCount_MASK 0xffffffff
-#define DPM_TABLE_34__VddciLevelCount__SHIFT 0x0
-#define DPM_TABLE_35__MvddLevelCount_MASK 0xffffffff
-#define DPM_TABLE_35__MvddLevelCount__SHIFT 0x0
-#define DPM_TABLE_36__VddcLevel_0_StdVoltageHiSidd_MASK 0xffff
-#define DPM_TABLE_36__VddcLevel_0_StdVoltageHiSidd__SHIFT 0x0
-#define DPM_TABLE_36__VddcLevel_0_Voltage_MASK 0xffff0000
-#define DPM_TABLE_36__VddcLevel_0_Voltage__SHIFT 0x10
-#define DPM_TABLE_37__VddcLevel_0_padding_MASK 0xff
-#define DPM_TABLE_37__VddcLevel_0_padding__SHIFT 0x0
-#define DPM_TABLE_37__VddcLevel_0_Smio_MASK 0xff00
-#define DPM_TABLE_37__VddcLevel_0_Smio__SHIFT 0x8
-#define DPM_TABLE_37__VddcLevel_0_StdVoltageLoSidd_MASK 0xffff0000
-#define DPM_TABLE_37__VddcLevel_0_StdVoltageLoSidd__SHIFT 0x10
-#define DPM_TABLE_38__VddcLevel_1_StdVoltageHiSidd_MASK 0xffff
-#define DPM_TABLE_38__VddcLevel_1_StdVoltageHiSidd__SHIFT 0x0
-#define DPM_TABLE_38__VddcLevel_1_Voltage_MASK 0xffff0000
-#define DPM_TABLE_38__VddcLevel_1_Voltage__SHIFT 0x10
-#define DPM_TABLE_39__VddcLevel_1_padding_MASK 0xff
-#define DPM_TABLE_39__VddcLevel_1_padding__SHIFT 0x0
-#define DPM_TABLE_39__VddcLevel_1_Smio_MASK 0xff00
-#define DPM_TABLE_39__VddcLevel_1_Smio__SHIFT 0x8
-#define DPM_TABLE_39__VddcLevel_1_StdVoltageLoSidd_MASK 0xffff0000
-#define DPM_TABLE_39__VddcLevel_1_StdVoltageLoSidd__SHIFT 0x10
-#define DPM_TABLE_40__VddcLevel_2_StdVoltageHiSidd_MASK 0xffff
-#define DPM_TABLE_40__VddcLevel_2_StdVoltageHiSidd__SHIFT 0x0
-#define DPM_TABLE_40__VddcLevel_2_Voltage_MASK 0xffff0000
-#define DPM_TABLE_40__VddcLevel_2_Voltage__SHIFT 0x10
-#define DPM_TABLE_41__VddcLevel_2_padding_MASK 0xff
-#define DPM_TABLE_41__VddcLevel_2_padding__SHIFT 0x0
-#define DPM_TABLE_41__VddcLevel_2_Smio_MASK 0xff00
-#define DPM_TABLE_41__VddcLevel_2_Smio__SHIFT 0x8
-#define DPM_TABLE_41__VddcLevel_2_StdVoltageLoSidd_MASK 0xffff0000
-#define DPM_TABLE_41__VddcLevel_2_StdVoltageLoSidd__SHIFT 0x10
-#define DPM_TABLE_42__VddcLevel_3_StdVoltageHiSidd_MASK 0xffff
-#define DPM_TABLE_42__VddcLevel_3_StdVoltageHiSidd__SHIFT 0x0
-#define DPM_TABLE_42__VddcLevel_3_Voltage_MASK 0xffff0000
-#define DPM_TABLE_42__VddcLevel_3_Voltage__SHIFT 0x10
-#define DPM_TABLE_43__VddcLevel_3_padding_MASK 0xff
-#define DPM_TABLE_43__VddcLevel_3_padding__SHIFT 0x0
-#define DPM_TABLE_43__VddcLevel_3_Smio_MASK 0xff00
-#define DPM_TABLE_43__VddcLevel_3_Smio__SHIFT 0x8
-#define DPM_TABLE_43__VddcLevel_3_StdVoltageLoSidd_MASK 0xffff0000
-#define DPM_TABLE_43__VddcLevel_3_StdVoltageLoSidd__SHIFT 0x10
-#define DPM_TABLE_44__VddcLevel_4_StdVoltageHiSidd_MASK 0xffff
-#define DPM_TABLE_44__VddcLevel_4_StdVoltageHiSidd__SHIFT 0x0
-#define DPM_TABLE_44__VddcLevel_4_Voltage_MASK 0xffff0000
-#define DPM_TABLE_44__VddcLevel_4_Voltage__SHIFT 0x10
-#define DPM_TABLE_45__VddcLevel_4_padding_MASK 0xff
-#define DPM_TABLE_45__VddcLevel_4_padding__SHIFT 0x0
-#define DPM_TABLE_45__VddcLevel_4_Smio_MASK 0xff00
-#define DPM_TABLE_45__VddcLevel_4_Smio__SHIFT 0x8
-#define DPM_TABLE_45__VddcLevel_4_StdVoltageLoSidd_MASK 0xffff0000
-#define DPM_TABLE_45__VddcLevel_4_StdVoltageLoSidd__SHIFT 0x10
-#define DPM_TABLE_46__VddcLevel_5_StdVoltageHiSidd_MASK 0xffff
-#define DPM_TABLE_46__VddcLevel_5_StdVoltageHiSidd__SHIFT 0x0
-#define DPM_TABLE_46__VddcLevel_5_Voltage_MASK 0xffff0000
-#define DPM_TABLE_46__VddcLevel_5_Voltage__SHIFT 0x10
-#define DPM_TABLE_47__VddcLevel_5_padding_MASK 0xff
-#define DPM_TABLE_47__VddcLevel_5_padding__SHIFT 0x0
-#define DPM_TABLE_47__VddcLevel_5_Smio_MASK 0xff00
-#define DPM_TABLE_47__VddcLevel_5_Smio__SHIFT 0x8
-#define DPM_TABLE_47__VddcLevel_5_StdVoltageLoSidd_MASK 0xffff0000
-#define DPM_TABLE_47__VddcLevel_5_StdVoltageLoSidd__SHIFT 0x10
-#define DPM_TABLE_48__VddcLevel_6_StdVoltageHiSidd_MASK 0xffff
-#define DPM_TABLE_48__VddcLevel_6_StdVoltageHiSidd__SHIFT 0x0
-#define DPM_TABLE_48__VddcLevel_6_Voltage_MASK 0xffff0000
-#define DPM_TABLE_48__VddcLevel_6_Voltage__SHIFT 0x10
-#define DPM_TABLE_49__VddcLevel_6_padding_MASK 0xff
-#define DPM_TABLE_49__VddcLevel_6_padding__SHIFT 0x0
-#define DPM_TABLE_49__VddcLevel_6_Smio_MASK 0xff00
-#define DPM_TABLE_49__VddcLevel_6_Smio__SHIFT 0x8
-#define DPM_TABLE_49__VddcLevel_6_StdVoltageLoSidd_MASK 0xffff0000
-#define DPM_TABLE_49__VddcLevel_6_StdVoltageLoSidd__SHIFT 0x10
-#define DPM_TABLE_50__VddcLevel_7_StdVoltageHiSidd_MASK 0xffff
-#define DPM_TABLE_50__VddcLevel_7_StdVoltageHiSidd__SHIFT 0x0
-#define DPM_TABLE_50__VddcLevel_7_Voltage_MASK 0xffff0000
-#define DPM_TABLE_50__VddcLevel_7_Voltage__SHIFT 0x10
-#define DPM_TABLE_51__VddcLevel_7_padding_MASK 0xff
-#define DPM_TABLE_51__VddcLevel_7_padding__SHIFT 0x0
-#define DPM_TABLE_51__VddcLevel_7_Smio_MASK 0xff00
-#define DPM_TABLE_51__VddcLevel_7_Smio__SHIFT 0x8
-#define DPM_TABLE_51__VddcLevel_7_StdVoltageLoSidd_MASK 0xffff0000
-#define DPM_TABLE_51__VddcLevel_7_StdVoltageLoSidd__SHIFT 0x10
-#define DPM_TABLE_52__VddciLevel_0_StdVoltageHiSidd_MASK 0xffff
-#define DPM_TABLE_52__VddciLevel_0_StdVoltageHiSidd__SHIFT 0x0
-#define DPM_TABLE_52__VddciLevel_0_Voltage_MASK 0xffff0000
-#define DPM_TABLE_52__VddciLevel_0_Voltage__SHIFT 0x10
-#define DPM_TABLE_53__VddciLevel_0_padding_MASK 0xff
-#define DPM_TABLE_53__VddciLevel_0_padding__SHIFT 0x0
-#define DPM_TABLE_53__VddciLevel_0_Smio_MASK 0xff00
-#define DPM_TABLE_53__VddciLevel_0_Smio__SHIFT 0x8
-#define DPM_TABLE_53__VddciLevel_0_StdVoltageLoSidd_MASK 0xffff0000
-#define DPM_TABLE_53__VddciLevel_0_StdVoltageLoSidd__SHIFT 0x10
-#define DPM_TABLE_54__VddciLevel_1_StdVoltageHiSidd_MASK 0xffff
-#define DPM_TABLE_54__VddciLevel_1_StdVoltageHiSidd__SHIFT 0x0
-#define DPM_TABLE_54__VddciLevel_1_Voltage_MASK 0xffff0000
-#define DPM_TABLE_54__VddciLevel_1_Voltage__SHIFT 0x10
-#define DPM_TABLE_55__VddciLevel_1_padding_MASK 0xff
-#define DPM_TABLE_55__VddciLevel_1_padding__SHIFT 0x0
-#define DPM_TABLE_55__VddciLevel_1_Smio_MASK 0xff00
-#define DPM_TABLE_55__VddciLevel_1_Smio__SHIFT 0x8
-#define DPM_TABLE_55__VddciLevel_1_StdVoltageLoSidd_MASK 0xffff0000
-#define DPM_TABLE_55__VddciLevel_1_StdVoltageLoSidd__SHIFT 0x10
-#define DPM_TABLE_56__VddciLevel_2_StdVoltageHiSidd_MASK 0xffff
-#define DPM_TABLE_56__VddciLevel_2_StdVoltageHiSidd__SHIFT 0x0
-#define DPM_TABLE_56__VddciLevel_2_Voltage_MASK 0xffff0000
-#define DPM_TABLE_56__VddciLevel_2_Voltage__SHIFT 0x10
-#define DPM_TABLE_57__VddciLevel_2_padding_MASK 0xff
-#define DPM_TABLE_57__VddciLevel_2_padding__SHIFT 0x0
-#define DPM_TABLE_57__VddciLevel_2_Smio_MASK 0xff00
-#define DPM_TABLE_57__VddciLevel_2_Smio__SHIFT 0x8
-#define DPM_TABLE_57__VddciLevel_2_StdVoltageLoSidd_MASK 0xffff0000
-#define DPM_TABLE_57__VddciLevel_2_StdVoltageLoSidd__SHIFT 0x10
-#define DPM_TABLE_58__VddciLevel_3_StdVoltageHiSidd_MASK 0xffff
-#define DPM_TABLE_58__VddciLevel_3_StdVoltageHiSidd__SHIFT 0x0
-#define DPM_TABLE_58__VddciLevel_3_Voltage_MASK 0xffff0000
-#define DPM_TABLE_58__VddciLevel_3_Voltage__SHIFT 0x10
-#define DPM_TABLE_59__VddciLevel_3_padding_MASK 0xff
-#define DPM_TABLE_59__VddciLevel_3_padding__SHIFT 0x0
-#define DPM_TABLE_59__VddciLevel_3_Smio_MASK 0xff00
-#define DPM_TABLE_59__VddciLevel_3_Smio__SHIFT 0x8
-#define DPM_TABLE_59__VddciLevel_3_StdVoltageLoSidd_MASK 0xffff0000
-#define DPM_TABLE_59__VddciLevel_3_StdVoltageLoSidd__SHIFT 0x10
-#define DPM_TABLE_60__MvddLevel_0_StdVoltageHiSidd_MASK 0xffff
-#define DPM_TABLE_60__MvddLevel_0_StdVoltageHiSidd__SHIFT 0x0
-#define DPM_TABLE_60__MvddLevel_0_Voltage_MASK 0xffff0000
-#define DPM_TABLE_60__MvddLevel_0_Voltage__SHIFT 0x10
-#define DPM_TABLE_61__MvddLevel_0_padding_MASK 0xff
-#define DPM_TABLE_61__MvddLevel_0_padding__SHIFT 0x0
-#define DPM_TABLE_61__MvddLevel_0_Smio_MASK 0xff00
-#define DPM_TABLE_61__MvddLevel_0_Smio__SHIFT 0x8
-#define DPM_TABLE_61__MvddLevel_0_StdVoltageLoSidd_MASK 0xffff0000
-#define DPM_TABLE_61__MvddLevel_0_StdVoltageLoSidd__SHIFT 0x10
-#define DPM_TABLE_62__MvddLevel_1_StdVoltageHiSidd_MASK 0xffff
-#define DPM_TABLE_62__MvddLevel_1_StdVoltageHiSidd__SHIFT 0x0
-#define DPM_TABLE_62__MvddLevel_1_Voltage_MASK 0xffff0000
-#define DPM_TABLE_62__MvddLevel_1_Voltage__SHIFT 0x10
-#define DPM_TABLE_63__MvddLevel_1_padding_MASK 0xff
-#define DPM_TABLE_63__MvddLevel_1_padding__SHIFT 0x0
-#define DPM_TABLE_63__MvddLevel_1_Smio_MASK 0xff00
-#define DPM_TABLE_63__MvddLevel_1_Smio__SHIFT 0x8
-#define DPM_TABLE_63__MvddLevel_1_StdVoltageLoSidd_MASK 0xffff0000
-#define DPM_TABLE_63__MvddLevel_1_StdVoltageLoSidd__SHIFT 0x10
-#define DPM_TABLE_64__MvddLevel_2_StdVoltageHiSidd_MASK 0xffff
-#define DPM_TABLE_64__MvddLevel_2_StdVoltageHiSidd__SHIFT 0x0
-#define DPM_TABLE_64__MvddLevel_2_Voltage_MASK 0xffff0000
-#define DPM_TABLE_64__MvddLevel_2_Voltage__SHIFT 0x10
-#define DPM_TABLE_65__MvddLevel_2_padding_MASK 0xff
-#define DPM_TABLE_65__MvddLevel_2_padding__SHIFT 0x0
-#define DPM_TABLE_65__MvddLevel_2_Smio_MASK 0xff00
-#define DPM_TABLE_65__MvddLevel_2_Smio__SHIFT 0x8
-#define DPM_TABLE_65__MvddLevel_2_StdVoltageLoSidd_MASK 0xffff0000
-#define DPM_TABLE_65__MvddLevel_2_StdVoltageLoSidd__SHIFT 0x10
-#define DPM_TABLE_66__MvddLevel_3_StdVoltageHiSidd_MASK 0xffff
-#define DPM_TABLE_66__MvddLevel_3_StdVoltageHiSidd__SHIFT 0x0
-#define DPM_TABLE_66__MvddLevel_3_Voltage_MASK 0xffff0000
-#define DPM_TABLE_66__MvddLevel_3_Voltage__SHIFT 0x10
-#define DPM_TABLE_67__MvddLevel_3_padding_MASK 0xff
-#define DPM_TABLE_67__MvddLevel_3_padding__SHIFT 0x0
-#define DPM_TABLE_67__MvddLevel_3_Smio_MASK 0xff00
-#define DPM_TABLE_67__MvddLevel_3_Smio__SHIFT 0x8
-#define DPM_TABLE_67__MvddLevel_3_StdVoltageLoSidd_MASK 0xffff0000
-#define DPM_TABLE_67__MvddLevel_3_StdVoltageLoSidd__SHIFT 0x10
-#define DPM_TABLE_68__UvdLevelCount_MASK 0xff
-#define DPM_TABLE_68__UvdLevelCount__SHIFT 0x0
-#define DPM_TABLE_68__LinkLevelCount_MASK 0xff00
-#define DPM_TABLE_68__LinkLevelCount__SHIFT 0x8
-#define DPM_TABLE_68__MemoryDpmLevelCount_MASK 0xff0000
-#define DPM_TABLE_68__MemoryDpmLevelCount__SHIFT 0x10
-#define DPM_TABLE_68__GraphicsDpmLevelCount_MASK 0xff000000
-#define DPM_TABLE_68__GraphicsDpmLevelCount__SHIFT 0x18
-#define DPM_TABLE_69__MasterDeepSleepControl_MASK 0xff
-#define DPM_TABLE_69__MasterDeepSleepControl__SHIFT 0x0
-#define DPM_TABLE_69__SamuLevelCount_MASK 0xff00
-#define DPM_TABLE_69__SamuLevelCount__SHIFT 0x8
-#define DPM_TABLE_69__AcpLevelCount_MASK 0xff0000
-#define DPM_TABLE_69__AcpLevelCount__SHIFT 0x10
-#define DPM_TABLE_69__VceLevelCount_MASK 0xff000000
-#define DPM_TABLE_69__VceLevelCount__SHIFT 0x18
-#define DPM_TABLE_70__DefaultTdp_MASK 0xffff
-#define DPM_TABLE_70__DefaultTdp__SHIFT 0x0
-#define DPM_TABLE_70__TargetTdp_MASK 0xffff0000
-#define DPM_TABLE_70__TargetTdp__SHIFT 0x10
-#define DPM_TABLE_71__Reserved_1_MASK 0xffffffff
-#define DPM_TABLE_71__Reserved_1__SHIFT 0x0
-#define DPM_TABLE_72__Reserved_2_MASK 0xffffffff
-#define DPM_TABLE_72__Reserved_2__SHIFT 0x0
-#define DPM_TABLE_73__Reserved_3_MASK 0xffffffff
-#define DPM_TABLE_73__Reserved_3__SHIFT 0x0
-#define DPM_TABLE_74__Reserved_4_MASK 0xffffffff
-#define DPM_TABLE_74__Reserved_4__SHIFT 0x0
-#define DPM_TABLE_75__GraphicsLevel_0_Flags_MASK 0xffffffff
-#define DPM_TABLE_75__GraphicsLevel_0_Flags__SHIFT 0x0
-#define DPM_TABLE_76__GraphicsLevel_0_MinVddc_MASK 0xffffffff
-#define DPM_TABLE_76__GraphicsLevel_0_MinVddc__SHIFT 0x0
-#define DPM_TABLE_77__GraphicsLevel_0_MinVddcPhases_MASK 0xffffffff
-#define DPM_TABLE_77__GraphicsLevel_0_MinVddcPhases__SHIFT 0x0
-#define DPM_TABLE_78__GraphicsLevel_0_SclkFrequency_MASK 0xffffffff
-#define DPM_TABLE_78__GraphicsLevel_0_SclkFrequency__SHIFT 0x0
-#define DPM_TABLE_79__GraphicsLevel_0_ActivityLevel_MASK 0xffff
-#define DPM_TABLE_79__GraphicsLevel_0_ActivityLevel__SHIFT 0x0
-#define DPM_TABLE_79__GraphicsLevel_0_padding1_MASK 0xff0000
-#define DPM_TABLE_79__GraphicsLevel_0_padding1__SHIFT 0x10
-#define DPM_TABLE_79__GraphicsLevel_0_pcieDpmLevel_MASK 0xff000000
-#define DPM_TABLE_79__GraphicsLevel_0_pcieDpmLevel__SHIFT 0x18
-#define DPM_TABLE_80__GraphicsLevel_0_CgSpllFuncCntl3_MASK 0xffffffff
-#define DPM_TABLE_80__GraphicsLevel_0_CgSpllFuncCntl3__SHIFT 0x0
-#define DPM_TABLE_81__GraphicsLevel_0_CgSpllFuncCntl4_MASK 0xffffffff
-#define DPM_TABLE_81__GraphicsLevel_0_CgSpllFuncCntl4__SHIFT 0x0
-#define DPM_TABLE_82__GraphicsLevel_0_SpllSpreadSpectrum_MASK 0xffffffff
-#define DPM_TABLE_82__GraphicsLevel_0_SpllSpreadSpectrum__SHIFT 0x0
-#define DPM_TABLE_83__GraphicsLevel_0_SpllSpreadSpectrum2_MASK 0xffffffff
-#define DPM_TABLE_83__GraphicsLevel_0_SpllSpreadSpectrum2__SHIFT 0x0
-#define DPM_TABLE_84__GraphicsLevel_0_CcPwrDynRm_MASK 0xffffffff
-#define DPM_TABLE_84__GraphicsLevel_0_CcPwrDynRm__SHIFT 0x0
-#define DPM_TABLE_85__GraphicsLevel_0_CcPwrDynRm1_MASK 0xffffffff
-#define DPM_TABLE_85__GraphicsLevel_0_CcPwrDynRm1__SHIFT 0x0
-#define DPM_TABLE_86__GraphicsLevel_0_EnabledForThrottle_MASK 0xff
-#define DPM_TABLE_86__GraphicsLevel_0_EnabledForThrottle__SHIFT 0x0
-#define DPM_TABLE_86__GraphicsLevel_0_EnabledForActivity_MASK 0xff00
-#define DPM_TABLE_86__GraphicsLevel_0_EnabledForActivity__SHIFT 0x8
-#define DPM_TABLE_86__GraphicsLevel_0_DisplayWatermark_MASK 0xff0000
-#define DPM_TABLE_86__GraphicsLevel_0_DisplayWatermark__SHIFT 0x10
-#define DPM_TABLE_86__GraphicsLevel_0_SclkDid_MASK 0xff000000
-#define DPM_TABLE_86__GraphicsLevel_0_SclkDid__SHIFT 0x18
-#define DPM_TABLE_87__GraphicsLevel_0_PowerThrottle_MASK 0xff
-#define DPM_TABLE_87__GraphicsLevel_0_PowerThrottle__SHIFT 0x0
-#define DPM_TABLE_87__GraphicsLevel_0_VoltageDownHyst_MASK 0xff00
-#define DPM_TABLE_87__GraphicsLevel_0_VoltageDownHyst__SHIFT 0x8
-#define DPM_TABLE_87__GraphicsLevel_0_DownHyst_MASK 0xff0000
-#define DPM_TABLE_87__GraphicsLevel_0_DownHyst__SHIFT 0x10
-#define DPM_TABLE_87__GraphicsLevel_0_UpHyst_MASK 0xff000000
-#define DPM_TABLE_87__GraphicsLevel_0_UpHyst__SHIFT 0x18
-#define DPM_TABLE_88__GraphicsLevel_0_padding_2_MASK 0xff
-#define DPM_TABLE_88__GraphicsLevel_0_padding_2__SHIFT 0x0
-#define DPM_TABLE_88__GraphicsLevel_0_padding_1_MASK 0xff00
-#define DPM_TABLE_88__GraphicsLevel_0_padding_1__SHIFT 0x8
-#define DPM_TABLE_88__GraphicsLevel_0_padding_0_MASK 0xff0000
-#define DPM_TABLE_88__GraphicsLevel_0_padding_0__SHIFT 0x10
-#define DPM_TABLE_88__GraphicsLevel_0_DeepSleepDivId_MASK 0xff000000
-#define DPM_TABLE_88__GraphicsLevel_0_DeepSleepDivId__SHIFT 0x18
-#define DPM_TABLE_89__GraphicsLevel_1_Flags_MASK 0xffffffff
-#define DPM_TABLE_89__GraphicsLevel_1_Flags__SHIFT 0x0
-#define DPM_TABLE_90__GraphicsLevel_1_MinVddc_MASK 0xffffffff
-#define DPM_TABLE_90__GraphicsLevel_1_MinVddc__SHIFT 0x0
-#define DPM_TABLE_91__GraphicsLevel_1_MinVddcPhases_MASK 0xffffffff
-#define DPM_TABLE_91__GraphicsLevel_1_MinVddcPhases__SHIFT 0x0
-#define DPM_TABLE_92__GraphicsLevel_1_SclkFrequency_MASK 0xffffffff
-#define DPM_TABLE_92__GraphicsLevel_1_SclkFrequency__SHIFT 0x0
-#define DPM_TABLE_93__GraphicsLevel_1_ActivityLevel_MASK 0xffff
-#define DPM_TABLE_93__GraphicsLevel_1_ActivityLevel__SHIFT 0x0
-#define DPM_TABLE_93__GraphicsLevel_1_padding1_MASK 0xff0000
-#define DPM_TABLE_93__GraphicsLevel_1_padding1__SHIFT 0x10
-#define DPM_TABLE_93__GraphicsLevel_1_pcieDpmLevel_MASK 0xff000000
-#define DPM_TABLE_93__GraphicsLevel_1_pcieDpmLevel__SHIFT 0x18
-#define DPM_TABLE_94__GraphicsLevel_1_CgSpllFuncCntl3_MASK 0xffffffff
-#define DPM_TABLE_94__GraphicsLevel_1_CgSpllFuncCntl3__SHIFT 0x0
-#define DPM_TABLE_95__GraphicsLevel_1_CgSpllFuncCntl4_MASK 0xffffffff
-#define DPM_TABLE_95__GraphicsLevel_1_CgSpllFuncCntl4__SHIFT 0x0
-#define DPM_TABLE_96__GraphicsLevel_1_SpllSpreadSpectrum_MASK 0xffffffff
-#define DPM_TABLE_96__GraphicsLevel_1_SpllSpreadSpectrum__SHIFT 0x0
-#define DPM_TABLE_97__GraphicsLevel_1_SpllSpreadSpectrum2_MASK 0xffffffff
-#define DPM_TABLE_97__GraphicsLevel_1_SpllSpreadSpectrum2__SHIFT 0x0
-#define DPM_TABLE_98__GraphicsLevel_1_CcPwrDynRm_MASK 0xffffffff
-#define DPM_TABLE_98__GraphicsLevel_1_CcPwrDynRm__SHIFT 0x0
-#define DPM_TABLE_99__GraphicsLevel_1_CcPwrDynRm1_MASK 0xffffffff
-#define DPM_TABLE_99__GraphicsLevel_1_CcPwrDynRm1__SHIFT 0x0
-#define DPM_TABLE_100__GraphicsLevel_1_EnabledForThrottle_MASK 0xff
-#define DPM_TABLE_100__GraphicsLevel_1_EnabledForThrottle__SHIFT 0x0
-#define DPM_TABLE_100__GraphicsLevel_1_EnabledForActivity_MASK 0xff00
-#define DPM_TABLE_100__GraphicsLevel_1_EnabledForActivity__SHIFT 0x8
-#define DPM_TABLE_100__GraphicsLevel_1_DisplayWatermark_MASK 0xff0000
-#define DPM_TABLE_100__GraphicsLevel_1_DisplayWatermark__SHIFT 0x10
-#define DPM_TABLE_100__GraphicsLevel_1_SclkDid_MASK 0xff000000
-#define DPM_TABLE_100__GraphicsLevel_1_SclkDid__SHIFT 0x18
-#define DPM_TABLE_101__GraphicsLevel_1_PowerThrottle_MASK 0xff
-#define DPM_TABLE_101__GraphicsLevel_1_PowerThrottle__SHIFT 0x0
-#define DPM_TABLE_101__GraphicsLevel_1_VoltageDownHyst_MASK 0xff00
-#define DPM_TABLE_101__GraphicsLevel_1_VoltageDownHyst__SHIFT 0x8
-#define DPM_TABLE_101__GraphicsLevel_1_DownHyst_MASK 0xff0000
-#define DPM_TABLE_101__GraphicsLevel_1_DownHyst__SHIFT 0x10
-#define DPM_TABLE_101__GraphicsLevel_1_UpHyst_MASK 0xff000000
-#define DPM_TABLE_101__GraphicsLevel_1_UpHyst__SHIFT 0x18
-#define DPM_TABLE_102__GraphicsLevel_1_padding_2_MASK 0xff
-#define DPM_TABLE_102__GraphicsLevel_1_padding_2__SHIFT 0x0
-#define DPM_TABLE_102__GraphicsLevel_1_padding_1_MASK 0xff00
-#define DPM_TABLE_102__GraphicsLevel_1_padding_1__SHIFT 0x8
-#define DPM_TABLE_102__GraphicsLevel_1_padding_0_MASK 0xff0000
-#define DPM_TABLE_102__GraphicsLevel_1_padding_0__SHIFT 0x10
-#define DPM_TABLE_102__GraphicsLevel_1_DeepSleepDivId_MASK 0xff000000
-#define DPM_TABLE_102__GraphicsLevel_1_DeepSleepDivId__SHIFT 0x18
-#define DPM_TABLE_103__GraphicsLevel_2_Flags_MASK 0xffffffff
-#define DPM_TABLE_103__GraphicsLevel_2_Flags__SHIFT 0x0
-#define DPM_TABLE_104__GraphicsLevel_2_MinVddc_MASK 0xffffffff
-#define DPM_TABLE_104__GraphicsLevel_2_MinVddc__SHIFT 0x0
-#define DPM_TABLE_105__GraphicsLevel_2_MinVddcPhases_MASK 0xffffffff
-#define DPM_TABLE_105__GraphicsLevel_2_MinVddcPhases__SHIFT 0x0
-#define DPM_TABLE_106__GraphicsLevel_2_SclkFrequency_MASK 0xffffffff
-#define DPM_TABLE_106__GraphicsLevel_2_SclkFrequency__SHIFT 0x0
-#define DPM_TABLE_107__GraphicsLevel_2_ActivityLevel_MASK 0xffff
-#define DPM_TABLE_107__GraphicsLevel_2_ActivityLevel__SHIFT 0x0
-#define DPM_TABLE_107__GraphicsLevel_2_padding1_MASK 0xff0000
-#define DPM_TABLE_107__GraphicsLevel_2_padding1__SHIFT 0x10
-#define DPM_TABLE_107__GraphicsLevel_2_pcieDpmLevel_MASK 0xff000000
-#define DPM_TABLE_107__GraphicsLevel_2_pcieDpmLevel__SHIFT 0x18
-#define DPM_TABLE_108__GraphicsLevel_2_CgSpllFuncCntl3_MASK 0xffffffff
-#define DPM_TABLE_108__GraphicsLevel_2_CgSpllFuncCntl3__SHIFT 0x0
-#define DPM_TABLE_109__GraphicsLevel_2_CgSpllFuncCntl4_MASK 0xffffffff
-#define DPM_TABLE_109__GraphicsLevel_2_CgSpllFuncCntl4__SHIFT 0x0
-#define DPM_TABLE_110__GraphicsLevel_2_SpllSpreadSpectrum_MASK 0xffffffff
-#define DPM_TABLE_110__GraphicsLevel_2_SpllSpreadSpectrum__SHIFT 0x0
-#define DPM_TABLE_111__GraphicsLevel_2_SpllSpreadSpectrum2_MASK 0xffffffff
-#define DPM_TABLE_111__GraphicsLevel_2_SpllSpreadSpectrum2__SHIFT 0x0
-#define DPM_TABLE_112__GraphicsLevel_2_CcPwrDynRm_MASK 0xffffffff
-#define DPM_TABLE_112__GraphicsLevel_2_CcPwrDynRm__SHIFT 0x0
-#define DPM_TABLE_113__GraphicsLevel_2_CcPwrDynRm1_MASK 0xffffffff
-#define DPM_TABLE_113__GraphicsLevel_2_CcPwrDynRm1__SHIFT 0x0
-#define DPM_TABLE_114__GraphicsLevel_2_EnabledForThrottle_MASK 0xff
-#define DPM_TABLE_114__GraphicsLevel_2_EnabledForThrottle__SHIFT 0x0
-#define DPM_TABLE_114__GraphicsLevel_2_EnabledForActivity_MASK 0xff00
-#define DPM_TABLE_114__GraphicsLevel_2_EnabledForActivity__SHIFT 0x8
-#define DPM_TABLE_114__GraphicsLevel_2_DisplayWatermark_MASK 0xff0000
-#define DPM_TABLE_114__GraphicsLevel_2_DisplayWatermark__SHIFT 0x10
-#define DPM_TABLE_114__GraphicsLevel_2_SclkDid_MASK 0xff000000
-#define DPM_TABLE_114__GraphicsLevel_2_SclkDid__SHIFT 0x18
-#define DPM_TABLE_115__GraphicsLevel_2_PowerThrottle_MASK 0xff
-#define DPM_TABLE_115__GraphicsLevel_2_PowerThrottle__SHIFT 0x0
-#define DPM_TABLE_115__GraphicsLevel_2_VoltageDownHyst_MASK 0xff00
-#define DPM_TABLE_115__GraphicsLevel_2_VoltageDownHyst__SHIFT 0x8
-#define DPM_TABLE_115__GraphicsLevel_2_DownHyst_MASK 0xff0000
-#define DPM_TABLE_115__GraphicsLevel_2_DownHyst__SHIFT 0x10
-#define DPM_TABLE_115__GraphicsLevel_2_UpHyst_MASK 0xff000000
-#define DPM_TABLE_115__GraphicsLevel_2_UpHyst__SHIFT 0x18
-#define DPM_TABLE_116__GraphicsLevel_2_padding_2_MASK 0xff
-#define DPM_TABLE_116__GraphicsLevel_2_padding_2__SHIFT 0x0
-#define DPM_TABLE_116__GraphicsLevel_2_padding_1_MASK 0xff00
-#define DPM_TABLE_116__GraphicsLevel_2_padding_1__SHIFT 0x8
-#define DPM_TABLE_116__GraphicsLevel_2_padding_0_MASK 0xff0000
-#define DPM_TABLE_116__GraphicsLevel_2_padding_0__SHIFT 0x10
-#define DPM_TABLE_116__GraphicsLevel_2_DeepSleepDivId_MASK 0xff000000
-#define DPM_TABLE_116__GraphicsLevel_2_DeepSleepDivId__SHIFT 0x18
-#define DPM_TABLE_117__GraphicsLevel_3_Flags_MASK 0xffffffff
-#define DPM_TABLE_117__GraphicsLevel_3_Flags__SHIFT 0x0
-#define DPM_TABLE_118__GraphicsLevel_3_MinVddc_MASK 0xffffffff
-#define DPM_TABLE_118__GraphicsLevel_3_MinVddc__SHIFT 0x0
-#define DPM_TABLE_119__GraphicsLevel_3_MinVddcPhases_MASK 0xffffffff
-#define DPM_TABLE_119__GraphicsLevel_3_MinVddcPhases__SHIFT 0x0
-#define DPM_TABLE_120__GraphicsLevel_3_SclkFrequency_MASK 0xffffffff
-#define DPM_TABLE_120__GraphicsLevel_3_SclkFrequency__SHIFT 0x0
-#define DPM_TABLE_121__GraphicsLevel_3_ActivityLevel_MASK 0xffff
-#define DPM_TABLE_121__GraphicsLevel_3_ActivityLevel__SHIFT 0x0
-#define DPM_TABLE_121__GraphicsLevel_3_padding1_MASK 0xff0000
-#define DPM_TABLE_121__GraphicsLevel_3_padding1__SHIFT 0x10
-#define DPM_TABLE_121__GraphicsLevel_3_pcieDpmLevel_MASK 0xff000000
-#define DPM_TABLE_121__GraphicsLevel_3_pcieDpmLevel__SHIFT 0x18
-#define DPM_TABLE_122__GraphicsLevel_3_CgSpllFuncCntl3_MASK 0xffffffff
-#define DPM_TABLE_122__GraphicsLevel_3_CgSpllFuncCntl3__SHIFT 0x0
-#define DPM_TABLE_123__GraphicsLevel_3_CgSpllFuncCntl4_MASK 0xffffffff
-#define DPM_TABLE_123__GraphicsLevel_3_CgSpllFuncCntl4__SHIFT 0x0
-#define DPM_TABLE_124__GraphicsLevel_3_SpllSpreadSpectrum_MASK 0xffffffff
-#define DPM_TABLE_124__GraphicsLevel_3_SpllSpreadSpectrum__SHIFT 0x0
-#define DPM_TABLE_125__GraphicsLevel_3_SpllSpreadSpectrum2_MASK 0xffffffff
-#define DPM_TABLE_125__GraphicsLevel_3_SpllSpreadSpectrum2__SHIFT 0x0
-#define DPM_TABLE_126__GraphicsLevel_3_CcPwrDynRm_MASK 0xffffffff
-#define DPM_TABLE_126__GraphicsLevel_3_CcPwrDynRm__SHIFT 0x0
-#define DPM_TABLE_127__GraphicsLevel_3_CcPwrDynRm1_MASK 0xffffffff
-#define DPM_TABLE_127__GraphicsLevel_3_CcPwrDynRm1__SHIFT 0x0
-#define DPM_TABLE_128__GraphicsLevel_3_EnabledForThrottle_MASK 0xff
-#define DPM_TABLE_128__GraphicsLevel_3_EnabledForThrottle__SHIFT 0x0
-#define DPM_TABLE_128__GraphicsLevel_3_EnabledForActivity_MASK 0xff00
-#define DPM_TABLE_128__GraphicsLevel_3_EnabledForActivity__SHIFT 0x8
-#define DPM_TABLE_128__GraphicsLevel_3_DisplayWatermark_MASK 0xff0000
-#define DPM_TABLE_128__GraphicsLevel_3_DisplayWatermark__SHIFT 0x10
-#define DPM_TABLE_128__GraphicsLevel_3_SclkDid_MASK 0xff000000
-#define DPM_TABLE_128__GraphicsLevel_3_SclkDid__SHIFT 0x18
-#define DPM_TABLE_129__GraphicsLevel_3_PowerThrottle_MASK 0xff
-#define DPM_TABLE_129__GraphicsLevel_3_PowerThrottle__SHIFT 0x0
-#define DPM_TABLE_129__GraphicsLevel_3_VoltageDownHyst_MASK 0xff00
-#define DPM_TABLE_129__GraphicsLevel_3_VoltageDownHyst__SHIFT 0x8
-#define DPM_TABLE_129__GraphicsLevel_3_DownHyst_MASK 0xff0000
-#define DPM_TABLE_129__GraphicsLevel_3_DownHyst__SHIFT 0x10
-#define DPM_TABLE_129__GraphicsLevel_3_UpHyst_MASK 0xff000000
-#define DPM_TABLE_129__GraphicsLevel_3_UpHyst__SHIFT 0x18
-#define DPM_TABLE_130__GraphicsLevel_3_padding_2_MASK 0xff
-#define DPM_TABLE_130__GraphicsLevel_3_padding_2__SHIFT 0x0
-#define DPM_TABLE_130__GraphicsLevel_3_padding_1_MASK 0xff00
-#define DPM_TABLE_130__GraphicsLevel_3_padding_1__SHIFT 0x8
-#define DPM_TABLE_130__GraphicsLevel_3_padding_0_MASK 0xff0000
-#define DPM_TABLE_130__GraphicsLevel_3_padding_0__SHIFT 0x10
-#define DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId_MASK 0xff000000
-#define DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId__SHIFT 0x18
-#define DPM_TABLE_131__GraphicsLevel_4_Flags_MASK 0xffffffff
-#define DPM_TABLE_131__GraphicsLevel_4_Flags__SHIFT 0x0
-#define DPM_TABLE_132__GraphicsLevel_4_MinVddc_MASK 0xffffffff
-#define DPM_TABLE_132__GraphicsLevel_4_MinVddc__SHIFT 0x0
-#define DPM_TABLE_133__GraphicsLevel_4_MinVddcPhases_MASK 0xffffffff
-#define DPM_TABLE_133__GraphicsLevel_4_MinVddcPhases__SHIFT 0x0
-#define DPM_TABLE_134__GraphicsLevel_4_SclkFrequency_MASK 0xffffffff
-#define DPM_TABLE_134__GraphicsLevel_4_SclkFrequency__SHIFT 0x0
-#define DPM_TABLE_135__GraphicsLevel_4_ActivityLevel_MASK 0xffff
-#define DPM_TABLE_135__GraphicsLevel_4_ActivityLevel__SHIFT 0x0
-#define DPM_TABLE_135__GraphicsLevel_4_padding1_MASK 0xff0000
-#define DPM_TABLE_135__GraphicsLevel_4_padding1__SHIFT 0x10
-#define DPM_TABLE_135__GraphicsLevel_4_pcieDpmLevel_MASK 0xff000000
-#define DPM_TABLE_135__GraphicsLevel_4_pcieDpmLevel__SHIFT 0x18
-#define DPM_TABLE_136__GraphicsLevel_4_CgSpllFuncCntl3_MASK 0xffffffff
-#define DPM_TABLE_136__GraphicsLevel_4_CgSpllFuncCntl3__SHIFT 0x0
-#define DPM_TABLE_137__GraphicsLevel_4_CgSpllFuncCntl4_MASK 0xffffffff
-#define DPM_TABLE_137__GraphicsLevel_4_CgSpllFuncCntl4__SHIFT 0x0
-#define DPM_TABLE_138__GraphicsLevel_4_SpllSpreadSpectrum_MASK 0xffffffff
-#define DPM_TABLE_138__GraphicsLevel_4_SpllSpreadSpectrum__SHIFT 0x0
-#define DPM_TABLE_139__GraphicsLevel_4_SpllSpreadSpectrum2_MASK 0xffffffff
-#define DPM_TABLE_139__GraphicsLevel_4_SpllSpreadSpectrum2__SHIFT 0x0
-#define DPM_TABLE_140__GraphicsLevel_4_CcPwrDynRm_MASK 0xffffffff
-#define DPM_TABLE_140__GraphicsLevel_4_CcPwrDynRm__SHIFT 0x0
-#define DPM_TABLE_141__GraphicsLevel_4_CcPwrDynRm1_MASK 0xffffffff
-#define DPM_TABLE_141__GraphicsLevel_4_CcPwrDynRm1__SHIFT 0x0
-#define DPM_TABLE_142__GraphicsLevel_4_EnabledForThrottle_MASK 0xff
-#define DPM_TABLE_142__GraphicsLevel_4_EnabledForThrottle__SHIFT 0x0
-#define DPM_TABLE_142__GraphicsLevel_4_EnabledForActivity_MASK 0xff00
-#define DPM_TABLE_142__GraphicsLevel_4_EnabledForActivity__SHIFT 0x8
-#define DPM_TABLE_142__GraphicsLevel_4_DisplayWatermark_MASK 0xff0000
-#define DPM_TABLE_142__GraphicsLevel_4_DisplayWatermark__SHIFT 0x10
-#define DPM_TABLE_142__GraphicsLevel_4_SclkDid_MASK 0xff000000
-#define DPM_TABLE_142__GraphicsLevel_4_SclkDid__SHIFT 0x18
-#define DPM_TABLE_143__GraphicsLevel_4_PowerThrottle_MASK 0xff
-#define DPM_TABLE_143__GraphicsLevel_4_PowerThrottle__SHIFT 0x0
-#define DPM_TABLE_143__GraphicsLevel_4_VoltageDownHyst_MASK 0xff00
-#define DPM_TABLE_143__GraphicsLevel_4_VoltageDownHyst__SHIFT 0x8
-#define DPM_TABLE_143__GraphicsLevel_4_DownHyst_MASK 0xff0000
-#define DPM_TABLE_143__GraphicsLevel_4_DownHyst__SHIFT 0x10
-#define DPM_TABLE_143__GraphicsLevel_4_UpHyst_MASK 0xff000000
-#define DPM_TABLE_143__GraphicsLevel_4_UpHyst__SHIFT 0x18
-#define DPM_TABLE_144__GraphicsLevel_4_padding_2_MASK 0xff
-#define DPM_TABLE_144__GraphicsLevel_4_padding_2__SHIFT 0x0
-#define DPM_TABLE_144__GraphicsLevel_4_padding_1_MASK 0xff00
-#define DPM_TABLE_144__GraphicsLevel_4_padding_1__SHIFT 0x8
-#define DPM_TABLE_144__GraphicsLevel_4_padding_0_MASK 0xff0000
-#define DPM_TABLE_144__GraphicsLevel_4_padding_0__SHIFT 0x10
-#define DPM_TABLE_144__GraphicsLevel_4_DeepSleepDivId_MASK 0xff000000
-#define DPM_TABLE_144__GraphicsLevel_4_DeepSleepDivId__SHIFT 0x18
-#define DPM_TABLE_145__GraphicsLevel_5_Flags_MASK 0xffffffff
-#define DPM_TABLE_145__GraphicsLevel_5_Flags__SHIFT 0x0
-#define DPM_TABLE_146__GraphicsLevel_5_MinVddc_MASK 0xffffffff
-#define DPM_TABLE_146__GraphicsLevel_5_MinVddc__SHIFT 0x0
-#define DPM_TABLE_147__GraphicsLevel_5_MinVddcPhases_MASK 0xffffffff
-#define DPM_TABLE_147__GraphicsLevel_5_MinVddcPhases__SHIFT 0x0
-#define DPM_TABLE_148__GraphicsLevel_5_SclkFrequency_MASK 0xffffffff
-#define DPM_TABLE_148__GraphicsLevel_5_SclkFrequency__SHIFT 0x0
-#define DPM_TABLE_149__GraphicsLevel_5_ActivityLevel_MASK 0xffff
-#define DPM_TABLE_149__GraphicsLevel_5_ActivityLevel__SHIFT 0x0
-#define DPM_TABLE_149__GraphicsLevel_5_padding1_MASK 0xff0000
-#define DPM_TABLE_149__GraphicsLevel_5_padding1__SHIFT 0x10
-#define DPM_TABLE_149__GraphicsLevel_5_pcieDpmLevel_MASK 0xff000000
-#define DPM_TABLE_149__GraphicsLevel_5_pcieDpmLevel__SHIFT 0x18
-#define DPM_TABLE_150__GraphicsLevel_5_CgSpllFuncCntl3_MASK 0xffffffff
-#define DPM_TABLE_150__GraphicsLevel_5_CgSpllFuncCntl3__SHIFT 0x0
-#define DPM_TABLE_151__GraphicsLevel_5_CgSpllFuncCntl4_MASK 0xffffffff
-#define DPM_TABLE_151__GraphicsLevel_5_CgSpllFuncCntl4__SHIFT 0x0
-#define DPM_TABLE_152__GraphicsLevel_5_SpllSpreadSpectrum_MASK 0xffffffff
-#define DPM_TABLE_152__GraphicsLevel_5_SpllSpreadSpectrum__SHIFT 0x0
-#define DPM_TABLE_153__GraphicsLevel_5_SpllSpreadSpectrum2_MASK 0xffffffff
-#define DPM_TABLE_153__GraphicsLevel_5_SpllSpreadSpectrum2__SHIFT 0x0
-#define DPM_TABLE_154__GraphicsLevel_5_CcPwrDynRm_MASK 0xffffffff
-#define DPM_TABLE_154__GraphicsLevel_5_CcPwrDynRm__SHIFT 0x0
-#define DPM_TABLE_155__GraphicsLevel_5_CcPwrDynRm1_MASK 0xffffffff
-#define DPM_TABLE_155__GraphicsLevel_5_CcPwrDynRm1__SHIFT 0x0
-#define DPM_TABLE_156__GraphicsLevel_5_EnabledForThrottle_MASK 0xff
-#define DPM_TABLE_156__GraphicsLevel_5_EnabledForThrottle__SHIFT 0x0
-#define DPM_TABLE_156__GraphicsLevel_5_EnabledForActivity_MASK 0xff00
-#define DPM_TABLE_156__GraphicsLevel_5_EnabledForActivity__SHIFT 0x8
-#define DPM_TABLE_156__GraphicsLevel_5_DisplayWatermark_MASK 0xff0000
-#define DPM_TABLE_156__GraphicsLevel_5_DisplayWatermark__SHIFT 0x10
-#define DPM_TABLE_156__GraphicsLevel_5_SclkDid_MASK 0xff000000
-#define DPM_TABLE_156__GraphicsLevel_5_SclkDid__SHIFT 0x18
-#define DPM_TABLE_157__GraphicsLevel_5_PowerThrottle_MASK 0xff
-#define DPM_TABLE_157__GraphicsLevel_5_PowerThrottle__SHIFT 0x0
-#define DPM_TABLE_157__GraphicsLevel_5_VoltageDownHyst_MASK 0xff00
-#define DPM_TABLE_157__GraphicsLevel_5_VoltageDownHyst__SHIFT 0x8
-#define DPM_TABLE_157__GraphicsLevel_5_DownHyst_MASK 0xff0000
-#define DPM_TABLE_157__GraphicsLevel_5_DownHyst__SHIFT 0x10
-#define DPM_TABLE_157__GraphicsLevel_5_UpHyst_MASK 0xff000000
-#define DPM_TABLE_157__GraphicsLevel_5_UpHyst__SHIFT 0x18
-#define DPM_TABLE_158__GraphicsLevel_5_padding_2_MASK 0xff
-#define DPM_TABLE_158__GraphicsLevel_5_padding_2__SHIFT 0x0
-#define DPM_TABLE_158__GraphicsLevel_5_padding_1_MASK 0xff00
-#define DPM_TABLE_158__GraphicsLevel_5_padding_1__SHIFT 0x8
-#define DPM_TABLE_158__GraphicsLevel_5_padding_0_MASK 0xff0000
-#define DPM_TABLE_158__GraphicsLevel_5_padding_0__SHIFT 0x10
-#define DPM_TABLE_158__GraphicsLevel_5_DeepSleepDivId_MASK 0xff000000
-#define DPM_TABLE_158__GraphicsLevel_5_DeepSleepDivId__SHIFT 0x18
-#define DPM_TABLE_159__GraphicsLevel_6_Flags_MASK 0xffffffff
-#define DPM_TABLE_159__GraphicsLevel_6_Flags__SHIFT 0x0
-#define DPM_TABLE_160__GraphicsLevel_6_MinVddc_MASK 0xffffffff
-#define DPM_TABLE_160__GraphicsLevel_6_MinVddc__SHIFT 0x0
-#define DPM_TABLE_161__GraphicsLevel_6_MinVddcPhases_MASK 0xffffffff
-#define DPM_TABLE_161__GraphicsLevel_6_MinVddcPhases__SHIFT 0x0
-#define DPM_TABLE_162__GraphicsLevel_6_SclkFrequency_MASK 0xffffffff
-#define DPM_TABLE_162__GraphicsLevel_6_SclkFrequency__SHIFT 0x0
-#define DPM_TABLE_163__GraphicsLevel_6_ActivityLevel_MASK 0xffff
-#define DPM_TABLE_163__GraphicsLevel_6_ActivityLevel__SHIFT 0x0
-#define DPM_TABLE_163__GraphicsLevel_6_padding1_MASK 0xff0000
-#define DPM_TABLE_163__GraphicsLevel_6_padding1__SHIFT 0x10
-#define DPM_TABLE_163__GraphicsLevel_6_pcieDpmLevel_MASK 0xff000000
-#define DPM_TABLE_163__GraphicsLevel_6_pcieDpmLevel__SHIFT 0x18
-#define DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3_MASK 0xffffffff
-#define DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3__SHIFT 0x0
-#define DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4_MASK 0xffffffff
-#define DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4__SHIFT 0x0
-#define DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum_MASK 0xffffffff
-#define DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum__SHIFT 0x0
-#define DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2_MASK 0xffffffff
-#define DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2__SHIFT 0x0
-#define DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm_MASK 0xffffffff
-#define DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm__SHIFT 0x0
-#define DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1_MASK 0xffffffff
-#define DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1__SHIFT 0x0
-#define DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle_MASK 0xff
-#define DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle__SHIFT 0x0
-#define DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity_MASK 0xff00
-#define DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity__SHIFT 0x8
-#define DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark_MASK 0xff0000
-#define DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark__SHIFT 0x10
-#define DPM_TABLE_170__GraphicsLevel_6_SclkDid_MASK 0xff000000
-#define DPM_TABLE_170__GraphicsLevel_6_SclkDid__SHIFT 0x18
-#define DPM_TABLE_171__GraphicsLevel_6_PowerThrottle_MASK 0xff
-#define DPM_TABLE_171__GraphicsLevel_6_PowerThrottle__SHIFT 0x0
-#define DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst_MASK 0xff00
-#define DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst__SHIFT 0x8
-#define DPM_TABLE_171__GraphicsLevel_6_DownHyst_MASK 0xff0000
-#define DPM_TABLE_171__GraphicsLevel_6_DownHyst__SHIFT 0x10
-#define DPM_TABLE_171__GraphicsLevel_6_UpHyst_MASK 0xff000000
-#define DPM_TABLE_171__GraphicsLevel_6_UpHyst__SHIFT 0x18
-#define DPM_TABLE_172__GraphicsLevel_6_padding_2_MASK 0xff
-#define DPM_TABLE_172__GraphicsLevel_6_padding_2__SHIFT 0x0
-#define DPM_TABLE_172__GraphicsLevel_6_padding_1_MASK 0xff00
-#define DPM_TABLE_172__GraphicsLevel_6_padding_1__SHIFT 0x8
-#define DPM_TABLE_172__GraphicsLevel_6_padding_0_MASK 0xff0000
-#define DPM_TABLE_172__GraphicsLevel_6_padding_0__SHIFT 0x10
-#define DPM_TABLE_172__GraphicsLevel_6_DeepSleepDivId_MASK 0xff000000
-#define DPM_TABLE_172__GraphicsLevel_6_DeepSleepDivId__SHIFT 0x18
-#define DPM_TABLE_173__GraphicsLevel_7_Flags_MASK 0xffffffff
-#define DPM_TABLE_173__GraphicsLevel_7_Flags__SHIFT 0x0
-#define DPM_TABLE_174__GraphicsLevel_7_MinVddc_MASK 0xffffffff
-#define DPM_TABLE_174__GraphicsLevel_7_MinVddc__SHIFT 0x0
-#define DPM_TABLE_175__GraphicsLevel_7_MinVddcPhases_MASK 0xffffffff
-#define DPM_TABLE_175__GraphicsLevel_7_MinVddcPhases__SHIFT 0x0
-#define DPM_TABLE_176__GraphicsLevel_7_SclkFrequency_MASK 0xffffffff
-#define DPM_TABLE_176__GraphicsLevel_7_SclkFrequency__SHIFT 0x0
-#define DPM_TABLE_177__GraphicsLevel_7_ActivityLevel_MASK 0xffff
-#define DPM_TABLE_177__GraphicsLevel_7_ActivityLevel__SHIFT 0x0
-#define DPM_TABLE_177__GraphicsLevel_7_padding1_MASK 0xff0000
-#define DPM_TABLE_177__GraphicsLevel_7_padding1__SHIFT 0x10
-#define DPM_TABLE_177__GraphicsLevel_7_pcieDpmLevel_MASK 0xff000000
-#define DPM_TABLE_177__GraphicsLevel_7_pcieDpmLevel__SHIFT 0x18
-#define DPM_TABLE_178__GraphicsLevel_7_CgSpllFuncCntl3_MASK 0xffffffff
-#define DPM_TABLE_178__GraphicsLevel_7_CgSpllFuncCntl3__SHIFT 0x0
-#define DPM_TABLE_179__GraphicsLevel_7_CgSpllFuncCntl4_MASK 0xffffffff
-#define DPM_TABLE_179__GraphicsLevel_7_CgSpllFuncCntl4__SHIFT 0x0
-#define DPM_TABLE_180__GraphicsLevel_7_SpllSpreadSpectrum_MASK 0xffffffff
-#define DPM_TABLE_180__GraphicsLevel_7_SpllSpreadSpectrum__SHIFT 0x0
-#define DPM_TABLE_181__GraphicsLevel_7_SpllSpreadSpectrum2_MASK 0xffffffff
-#define DPM_TABLE_181__GraphicsLevel_7_SpllSpreadSpectrum2__SHIFT 0x0
-#define DPM_TABLE_182__GraphicsLevel_7_CcPwrDynRm_MASK 0xffffffff
-#define DPM_TABLE_182__GraphicsLevel_7_CcPwrDynRm__SHIFT 0x0
-#define DPM_TABLE_183__GraphicsLevel_7_CcPwrDynRm1_MASK 0xffffffff
-#define DPM_TABLE_183__GraphicsLevel_7_CcPwrDynRm1__SHIFT 0x0
-#define DPM_TABLE_184__GraphicsLevel_7_EnabledForThrottle_MASK 0xff
-#define DPM_TABLE_184__GraphicsLevel_7_EnabledForThrottle__SHIFT 0x0
-#define DPM_TABLE_184__GraphicsLevel_7_EnabledForActivity_MASK 0xff00
-#define DPM_TABLE_184__GraphicsLevel_7_EnabledForActivity__SHIFT 0x8
-#define DPM_TABLE_184__GraphicsLevel_7_DisplayWatermark_MASK 0xff0000
-#define DPM_TABLE_184__GraphicsLevel_7_DisplayWatermark__SHIFT 0x10
-#define DPM_TABLE_184__GraphicsLevel_7_SclkDid_MASK 0xff000000
-#define DPM_TABLE_184__GraphicsLevel_7_SclkDid__SHIFT 0x18
-#define DPM_TABLE_185__GraphicsLevel_7_PowerThrottle_MASK 0xff
-#define DPM_TABLE_185__GraphicsLevel_7_PowerThrottle__SHIFT 0x0
-#define DPM_TABLE_185__GraphicsLevel_7_VoltageDownHyst_MASK 0xff00
-#define DPM_TABLE_185__GraphicsLevel_7_VoltageDownHyst__SHIFT 0x8
-#define DPM_TABLE_185__GraphicsLevel_7_DownHyst_MASK 0xff0000
-#define DPM_TABLE_185__GraphicsLevel_7_DownHyst__SHIFT 0x10
-#define DPM_TABLE_185__GraphicsLevel_7_UpHyst_MASK 0xff000000
-#define DPM_TABLE_185__GraphicsLevel_7_UpHyst__SHIFT 0x18
-#define DPM_TABLE_186__GraphicsLevel_7_padding_2_MASK 0xff
-#define DPM_TABLE_186__GraphicsLevel_7_padding_2__SHIFT 0x0
-#define DPM_TABLE_186__GraphicsLevel_7_padding_1_MASK 0xff00
-#define DPM_TABLE_186__GraphicsLevel_7_padding_1__SHIFT 0x8
-#define DPM_TABLE_186__GraphicsLevel_7_padding_0_MASK 0xff0000
-#define DPM_TABLE_186__GraphicsLevel_7_padding_0__SHIFT 0x10
-#define DPM_TABLE_186__GraphicsLevel_7_DeepSleepDivId_MASK 0xff000000
-#define DPM_TABLE_186__GraphicsLevel_7_DeepSleepDivId__SHIFT 0x18
-#define DPM_TABLE_187__MemoryACPILevel_MinVddc_MASK 0xffffffff
-#define DPM_TABLE_187__MemoryACPILevel_MinVddc__SHIFT 0x0
-#define DPM_TABLE_188__MemoryACPILevel_MinVddcPhases_MASK 0xffffffff
-#define DPM_TABLE_188__MemoryACPILevel_MinVddcPhases__SHIFT 0x0
-#define DPM_TABLE_189__MemoryACPILevel_MinVddci_MASK 0xffffffff
-#define DPM_TABLE_189__MemoryACPILevel_MinVddci__SHIFT 0x0
-#define DPM_TABLE_190__MemoryACPILevel_MinMvdd_MASK 0xffffffff
-#define DPM_TABLE_190__MemoryACPILevel_MinMvdd__SHIFT 0x0
-#define DPM_TABLE_191__MemoryACPILevel_MclkFrequency_MASK 0xffffffff
-#define DPM_TABLE_191__MemoryACPILevel_MclkFrequency__SHIFT 0x0
-#define DPM_TABLE_192__MemoryACPILevel_StutterEnable_MASK 0xff
-#define DPM_TABLE_192__MemoryACPILevel_StutterEnable__SHIFT 0x0
-#define DPM_TABLE_192__MemoryACPILevel_RttEnable_MASK 0xff00
-#define DPM_TABLE_192__MemoryACPILevel_RttEnable__SHIFT 0x8
-#define DPM_TABLE_192__MemoryACPILevel_EdcWriteEnable_MASK 0xff0000
-#define DPM_TABLE_192__MemoryACPILevel_EdcWriteEnable__SHIFT 0x10
-#define DPM_TABLE_192__MemoryACPILevel_EdcReadEnable_MASK 0xff000000
-#define DPM_TABLE_192__MemoryACPILevel_EdcReadEnable__SHIFT 0x18
-#define DPM_TABLE_193__MemoryACPILevel_EnabledForActivity_MASK 0xff
-#define DPM_TABLE_193__MemoryACPILevel_EnabledForActivity__SHIFT 0x0
-#define DPM_TABLE_193__MemoryACPILevel_EnabledForThrottle_MASK 0xff00
-#define DPM_TABLE_193__MemoryACPILevel_EnabledForThrottle__SHIFT 0x8
-#define DPM_TABLE_193__MemoryACPILevel_StrobeRatio_MASK 0xff0000
-#define DPM_TABLE_193__MemoryACPILevel_StrobeRatio__SHIFT 0x10
-#define DPM_TABLE_193__MemoryACPILevel_StrobeEnable_MASK 0xff000000
-#define DPM_TABLE_193__MemoryACPILevel_StrobeEnable__SHIFT 0x18
-#define DPM_TABLE_194__MemoryACPILevel_padding_MASK 0xff
-#define DPM_TABLE_194__MemoryACPILevel_padding__SHIFT 0x0
-#define DPM_TABLE_194__MemoryACPILevel_VoltageDownHyst_MASK 0xff00
-#define DPM_TABLE_194__MemoryACPILevel_VoltageDownHyst__SHIFT 0x8
-#define DPM_TABLE_194__MemoryACPILevel_DownHyst_MASK 0xff0000
-#define DPM_TABLE_194__MemoryACPILevel_DownHyst__SHIFT 0x10
-#define DPM_TABLE_194__MemoryACPILevel_UpHyst_MASK 0xff000000
-#define DPM_TABLE_194__MemoryACPILevel_UpHyst__SHIFT 0x18
-#define DPM_TABLE_195__MemoryACPILevel_padding1_MASK 0xff
-#define DPM_TABLE_195__MemoryACPILevel_padding1__SHIFT 0x0
-#define DPM_TABLE_195__MemoryACPILevel_DisplayWatermark_MASK 0xff00
-#define DPM_TABLE_195__MemoryACPILevel_DisplayWatermark__SHIFT 0x8
-#define DPM_TABLE_195__MemoryACPILevel_ActivityLevel_MASK 0xffff0000
-#define DPM_TABLE_195__MemoryACPILevel_ActivityLevel__SHIFT 0x10
-#define DPM_TABLE_196__MemoryACPILevel_MpllFuncCntl_MASK 0xffffffff
-#define DPM_TABLE_196__MemoryACPILevel_MpllFuncCntl__SHIFT 0x0
-#define DPM_TABLE_197__MemoryACPILevel_MpllFuncCntl_1_MASK 0xffffffff
-#define DPM_TABLE_197__MemoryACPILevel_MpllFuncCntl_1__SHIFT 0x0
-#define DPM_TABLE_198__MemoryACPILevel_MpllFuncCntl_2_MASK 0xffffffff
-#define DPM_TABLE_198__MemoryACPILevel_MpllFuncCntl_2__SHIFT 0x0
-#define DPM_TABLE_199__MemoryACPILevel_MpllAdFuncCntl_MASK 0xffffffff
-#define DPM_TABLE_199__MemoryACPILevel_MpllAdFuncCntl__SHIFT 0x0
-#define DPM_TABLE_200__MemoryACPILevel_MpllDqFuncCntl_MASK 0xffffffff
-#define DPM_TABLE_200__MemoryACPILevel_MpllDqFuncCntl__SHIFT 0x0
-#define DPM_TABLE_201__MemoryACPILevel_MclkPwrmgtCntl_MASK 0xffffffff
-#define DPM_TABLE_201__MemoryACPILevel_MclkPwrmgtCntl__SHIFT 0x0
-#define DPM_TABLE_202__MemoryACPILevel_DllCntl_MASK 0xffffffff
-#define DPM_TABLE_202__MemoryACPILevel_DllCntl__SHIFT 0x0
-#define DPM_TABLE_203__MemoryACPILevel_MpllSs1_MASK 0xffffffff
-#define DPM_TABLE_203__MemoryACPILevel_MpllSs1__SHIFT 0x0
-#define DPM_TABLE_204__MemoryACPILevel_MpllSs2_MASK 0xffffffff
-#define DPM_TABLE_204__MemoryACPILevel_MpllSs2__SHIFT 0x0
-#define DPM_TABLE_205__MemoryLevel_0_MinVddc_MASK 0xffffffff
-#define DPM_TABLE_205__MemoryLevel_0_MinVddc__SHIFT 0x0
-#define DPM_TABLE_206__MemoryLevel_0_MinVddcPhases_MASK 0xffffffff
-#define DPM_TABLE_206__MemoryLevel_0_MinVddcPhases__SHIFT 0x0
-#define DPM_TABLE_207__MemoryLevel_0_MinVddci_MASK 0xffffffff
-#define DPM_TABLE_207__MemoryLevel_0_MinVddci__SHIFT 0x0
-#define DPM_TABLE_208__MemoryLevel_0_MinMvdd_MASK 0xffffffff
-#define DPM_TABLE_208__MemoryLevel_0_MinMvdd__SHIFT 0x0
-#define DPM_TABLE_209__MemoryLevel_0_MclkFrequency_MASK 0xffffffff
-#define DPM_TABLE_209__MemoryLevel_0_MclkFrequency__SHIFT 0x0
-#define DPM_TABLE_210__MemoryLevel_0_StutterEnable_MASK 0xff
-#define DPM_TABLE_210__MemoryLevel_0_StutterEnable__SHIFT 0x0
-#define DPM_TABLE_210__MemoryLevel_0_RttEnable_MASK 0xff00
-#define DPM_TABLE_210__MemoryLevel_0_RttEnable__SHIFT 0x8
-#define DPM_TABLE_210__MemoryLevel_0_EdcWriteEnable_MASK 0xff0000
-#define DPM_TABLE_210__MemoryLevel_0_EdcWriteEnable__SHIFT 0x10
-#define DPM_TABLE_210__MemoryLevel_0_EdcReadEnable_MASK 0xff000000
-#define DPM_TABLE_210__MemoryLevel_0_EdcReadEnable__SHIFT 0x18
-#define DPM_TABLE_211__MemoryLevel_0_EnabledForActivity_MASK 0xff
-#define DPM_TABLE_211__MemoryLevel_0_EnabledForActivity__SHIFT 0x0
-#define DPM_TABLE_211__MemoryLevel_0_EnabledForThrottle_MASK 0xff00
-#define DPM_TABLE_211__MemoryLevel_0_EnabledForThrottle__SHIFT 0x8
-#define DPM_TABLE_211__MemoryLevel_0_StrobeRatio_MASK 0xff0000
-#define DPM_TABLE_211__MemoryLevel_0_StrobeRatio__SHIFT 0x10
-#define DPM_TABLE_211__MemoryLevel_0_StrobeEnable_MASK 0xff000000
-#define DPM_TABLE_211__MemoryLevel_0_StrobeEnable__SHIFT 0x18
-#define DPM_TABLE_212__MemoryLevel_0_padding_MASK 0xff
-#define DPM_TABLE_212__MemoryLevel_0_padding__SHIFT 0x0
-#define DPM_TABLE_212__MemoryLevel_0_VoltageDownHyst_MASK 0xff00
-#define DPM_TABLE_212__MemoryLevel_0_VoltageDownHyst__SHIFT 0x8
-#define DPM_TABLE_212__MemoryLevel_0_DownHyst_MASK 0xff0000
-#define DPM_TABLE_212__MemoryLevel_0_DownHyst__SHIFT 0x10
-#define DPM_TABLE_212__MemoryLevel_0_UpHyst_MASK 0xff000000
-#define DPM_TABLE_212__MemoryLevel_0_UpHyst__SHIFT 0x18
-#define DPM_TABLE_213__MemoryLevel_0_padding1_MASK 0xff
-#define DPM_TABLE_213__MemoryLevel_0_padding1__SHIFT 0x0
-#define DPM_TABLE_213__MemoryLevel_0_DisplayWatermark_MASK 0xff00
-#define DPM_TABLE_213__MemoryLevel_0_DisplayWatermark__SHIFT 0x8
-#define DPM_TABLE_213__MemoryLevel_0_ActivityLevel_MASK 0xffff0000
-#define DPM_TABLE_213__MemoryLevel_0_ActivityLevel__SHIFT 0x10
-#define DPM_TABLE_214__MemoryLevel_0_MpllFuncCntl_MASK 0xffffffff
-#define DPM_TABLE_214__MemoryLevel_0_MpllFuncCntl__SHIFT 0x0
-#define DPM_TABLE_215__MemoryLevel_0_MpllFuncCntl_1_MASK 0xffffffff
-#define DPM_TABLE_215__MemoryLevel_0_MpllFuncCntl_1__SHIFT 0x0
-#define DPM_TABLE_216__MemoryLevel_0_MpllFuncCntl_2_MASK 0xffffffff
-#define DPM_TABLE_216__MemoryLevel_0_MpllFuncCntl_2__SHIFT 0x0
-#define DPM_TABLE_217__MemoryLevel_0_MpllAdFuncCntl_MASK 0xffffffff
-#define DPM_TABLE_217__MemoryLevel_0_MpllAdFuncCntl__SHIFT 0x0
-#define DPM_TABLE_218__MemoryLevel_0_MpllDqFuncCntl_MASK 0xffffffff
-#define DPM_TABLE_218__MemoryLevel_0_MpllDqFuncCntl__SHIFT 0x0
-#define DPM_TABLE_219__MemoryLevel_0_MclkPwrmgtCntl_MASK 0xffffffff
-#define DPM_TABLE_219__MemoryLevel_0_MclkPwrmgtCntl__SHIFT 0x0
-#define DPM_TABLE_220__MemoryLevel_0_DllCntl_MASK 0xffffffff
-#define DPM_TABLE_220__MemoryLevel_0_DllCntl__SHIFT 0x0
-#define DPM_TABLE_221__MemoryLevel_0_MpllSs1_MASK 0xffffffff
-#define DPM_TABLE_221__MemoryLevel_0_MpllSs1__SHIFT 0x0
-#define DPM_TABLE_222__MemoryLevel_0_MpllSs2_MASK 0xffffffff
-#define DPM_TABLE_222__MemoryLevel_0_MpllSs2__SHIFT 0x0
-#define DPM_TABLE_223__MemoryLevel_1_MinVddc_MASK 0xffffffff
-#define DPM_TABLE_223__MemoryLevel_1_MinVddc__SHIFT 0x0
-#define DPM_TABLE_224__MemoryLevel_1_MinVddcPhases_MASK 0xffffffff
-#define DPM_TABLE_224__MemoryLevel_1_MinVddcPhases__SHIFT 0x0
-#define DPM_TABLE_225__MemoryLevel_1_MinVddci_MASK 0xffffffff
-#define DPM_TABLE_225__MemoryLevel_1_MinVddci__SHIFT 0x0
-#define DPM_TABLE_226__MemoryLevel_1_MinMvdd_MASK 0xffffffff
-#define DPM_TABLE_226__MemoryLevel_1_MinMvdd__SHIFT 0x0
-#define DPM_TABLE_227__MemoryLevel_1_MclkFrequency_MASK 0xffffffff
-#define DPM_TABLE_227__MemoryLevel_1_MclkFrequency__SHIFT 0x0
-#define DPM_TABLE_228__MemoryLevel_1_StutterEnable_MASK 0xff
-#define DPM_TABLE_228__MemoryLevel_1_StutterEnable__SHIFT 0x0
-#define DPM_TABLE_228__MemoryLevel_1_RttEnable_MASK 0xff00
-#define DPM_TABLE_228__MemoryLevel_1_RttEnable__SHIFT 0x8
-#define DPM_TABLE_228__MemoryLevel_1_EdcWriteEnable_MASK 0xff0000
-#define DPM_TABLE_228__MemoryLevel_1_EdcWriteEnable__SHIFT 0x10
-#define DPM_TABLE_228__MemoryLevel_1_EdcReadEnable_MASK 0xff000000
-#define DPM_TABLE_228__MemoryLevel_1_EdcReadEnable__SHIFT 0x18
-#define DPM_TABLE_229__MemoryLevel_1_EnabledForActivity_MASK 0xff
-#define DPM_TABLE_229__MemoryLevel_1_EnabledForActivity__SHIFT 0x0
-#define DPM_TABLE_229__MemoryLevel_1_EnabledForThrottle_MASK 0xff00
-#define DPM_TABLE_229__MemoryLevel_1_EnabledForThrottle__SHIFT 0x8
-#define DPM_TABLE_229__MemoryLevel_1_StrobeRatio_MASK 0xff0000
-#define DPM_TABLE_229__MemoryLevel_1_StrobeRatio__SHIFT 0x10
-#define DPM_TABLE_229__MemoryLevel_1_StrobeEnable_MASK 0xff000000
-#define DPM_TABLE_229__MemoryLevel_1_StrobeEnable__SHIFT 0x18
-#define DPM_TABLE_230__MemoryLevel_1_padding_MASK 0xff
-#define DPM_TABLE_230__MemoryLevel_1_padding__SHIFT 0x0
-#define DPM_TABLE_230__MemoryLevel_1_VoltageDownHyst_MASK 0xff00
-#define DPM_TABLE_230__MemoryLevel_1_VoltageDownHyst__SHIFT 0x8
-#define DPM_TABLE_230__MemoryLevel_1_DownHyst_MASK 0xff0000
-#define DPM_TABLE_230__MemoryLevel_1_DownHyst__SHIFT 0x10
-#define DPM_TABLE_230__MemoryLevel_1_UpHyst_MASK 0xff000000
-#define DPM_TABLE_230__MemoryLevel_1_UpHyst__SHIFT 0x18
-#define DPM_TABLE_231__MemoryLevel_1_padding1_MASK 0xff
-#define DPM_TABLE_231__MemoryLevel_1_padding1__SHIFT 0x0
-#define DPM_TABLE_231__MemoryLevel_1_DisplayWatermark_MASK 0xff00
-#define DPM_TABLE_231__MemoryLevel_1_DisplayWatermark__SHIFT 0x8
-#define DPM_TABLE_231__MemoryLevel_1_ActivityLevel_MASK 0xffff0000
-#define DPM_TABLE_231__MemoryLevel_1_ActivityLevel__SHIFT 0x10
-#define DPM_TABLE_232__MemoryLevel_1_MpllFuncCntl_MASK 0xffffffff
-#define DPM_TABLE_232__MemoryLevel_1_MpllFuncCntl__SHIFT 0x0
-#define DPM_TABLE_233__MemoryLevel_1_MpllFuncCntl_1_MASK 0xffffffff
-#define DPM_TABLE_233__MemoryLevel_1_MpllFuncCntl_1__SHIFT 0x0
-#define DPM_TABLE_234__MemoryLevel_1_MpllFuncCntl_2_MASK 0xffffffff
-#define DPM_TABLE_234__MemoryLevel_1_MpllFuncCntl_2__SHIFT 0x0
-#define DPM_TABLE_235__MemoryLevel_1_MpllAdFuncCntl_MASK 0xffffffff
-#define DPM_TABLE_235__MemoryLevel_1_MpllAdFuncCntl__SHIFT 0x0
-#define DPM_TABLE_236__MemoryLevel_1_MpllDqFuncCntl_MASK 0xffffffff
-#define DPM_TABLE_236__MemoryLevel_1_MpllDqFuncCntl__SHIFT 0x0
-#define DPM_TABLE_237__MemoryLevel_1_MclkPwrmgtCntl_MASK 0xffffffff
-#define DPM_TABLE_237__MemoryLevel_1_MclkPwrmgtCntl__SHIFT 0x0
-#define DPM_TABLE_238__MemoryLevel_1_DllCntl_MASK 0xffffffff
-#define DPM_TABLE_238__MemoryLevel_1_DllCntl__SHIFT 0x0
-#define DPM_TABLE_239__MemoryLevel_1_MpllSs1_MASK 0xffffffff
-#define DPM_TABLE_239__MemoryLevel_1_MpllSs1__SHIFT 0x0
-#define DPM_TABLE_240__MemoryLevel_1_MpllSs2_MASK 0xffffffff
-#define DPM_TABLE_240__MemoryLevel_1_MpllSs2__SHIFT 0x0
-#define DPM_TABLE_241__MemoryLevel_2_MinVddc_MASK 0xffffffff
-#define DPM_TABLE_241__MemoryLevel_2_MinVddc__SHIFT 0x0
-#define DPM_TABLE_242__MemoryLevel_2_MinVddcPhases_MASK 0xffffffff
-#define DPM_TABLE_242__MemoryLevel_2_MinVddcPhases__SHIFT 0x0
-#define DPM_TABLE_243__MemoryLevel_2_MinVddci_MASK 0xffffffff
-#define DPM_TABLE_243__MemoryLevel_2_MinVddci__SHIFT 0x0
-#define DPM_TABLE_244__MemoryLevel_2_MinMvdd_MASK 0xffffffff
-#define DPM_TABLE_244__MemoryLevel_2_MinMvdd__SHIFT 0x0
-#define DPM_TABLE_245__MemoryLevel_2_MclkFrequency_MASK 0xffffffff
-#define DPM_TABLE_245__MemoryLevel_2_MclkFrequency__SHIFT 0x0
-#define DPM_TABLE_246__MemoryLevel_2_StutterEnable_MASK 0xff
-#define DPM_TABLE_246__MemoryLevel_2_StutterEnable__SHIFT 0x0
-#define DPM_TABLE_246__MemoryLevel_2_RttEnable_MASK 0xff00
-#define DPM_TABLE_246__MemoryLevel_2_RttEnable__SHIFT 0x8
-#define DPM_TABLE_246__MemoryLevel_2_EdcWriteEnable_MASK 0xff0000
-#define DPM_TABLE_246__MemoryLevel_2_EdcWriteEnable__SHIFT 0x10
-#define DPM_TABLE_246__MemoryLevel_2_EdcReadEnable_MASK 0xff000000
-#define DPM_TABLE_246__MemoryLevel_2_EdcReadEnable__SHIFT 0x18
-#define DPM_TABLE_247__MemoryLevel_2_EnabledForActivity_MASK 0xff
-#define DPM_TABLE_247__MemoryLevel_2_EnabledForActivity__SHIFT 0x0
-#define DPM_TABLE_247__MemoryLevel_2_EnabledForThrottle_MASK 0xff00
-#define DPM_TABLE_247__MemoryLevel_2_EnabledForThrottle__SHIFT 0x8
-#define DPM_TABLE_247__MemoryLevel_2_StrobeRatio_MASK 0xff0000
-#define DPM_TABLE_247__MemoryLevel_2_StrobeRatio__SHIFT 0x10
-#define DPM_TABLE_247__MemoryLevel_2_StrobeEnable_MASK 0xff000000
-#define DPM_TABLE_247__MemoryLevel_2_StrobeEnable__SHIFT 0x18
-#define DPM_TABLE_248__MemoryLevel_2_padding_MASK 0xff
-#define DPM_TABLE_248__MemoryLevel_2_padding__SHIFT 0x0
-#define DPM_TABLE_248__MemoryLevel_2_VoltageDownHyst_MASK 0xff00
-#define DPM_TABLE_248__MemoryLevel_2_VoltageDownHyst__SHIFT 0x8
-#define DPM_TABLE_248__MemoryLevel_2_DownHyst_MASK 0xff0000
-#define DPM_TABLE_248__MemoryLevel_2_DownHyst__SHIFT 0x10
-#define DPM_TABLE_248__MemoryLevel_2_UpHyst_MASK 0xff000000
-#define DPM_TABLE_248__MemoryLevel_2_UpHyst__SHIFT 0x18
-#define DPM_TABLE_249__MemoryLevel_2_padding1_MASK 0xff
-#define DPM_TABLE_249__MemoryLevel_2_padding1__SHIFT 0x0
-#define DPM_TABLE_249__MemoryLevel_2_DisplayWatermark_MASK 0xff00
-#define DPM_TABLE_249__MemoryLevel_2_DisplayWatermark__SHIFT 0x8
-#define DPM_TABLE_249__MemoryLevel_2_ActivityLevel_MASK 0xffff0000
-#define DPM_TABLE_249__MemoryLevel_2_ActivityLevel__SHIFT 0x10
-#define DPM_TABLE_250__MemoryLevel_2_MpllFuncCntl_MASK 0xffffffff
-#define DPM_TABLE_250__MemoryLevel_2_MpllFuncCntl__SHIFT 0x0
-#define DPM_TABLE_251__MemoryLevel_2_MpllFuncCntl_1_MASK 0xffffffff
-#define DPM_TABLE_251__MemoryLevel_2_MpllFuncCntl_1__SHIFT 0x0
-#define DPM_TABLE_252__MemoryLevel_2_MpllFuncCntl_2_MASK 0xffffffff
-#define DPM_TABLE_252__MemoryLevel_2_MpllFuncCntl_2__SHIFT 0x0
-#define DPM_TABLE_253__MemoryLevel_2_MpllAdFuncCntl_MASK 0xffffffff
-#define DPM_TABLE_253__MemoryLevel_2_MpllAdFuncCntl__SHIFT 0x0
-#define DPM_TABLE_254__MemoryLevel_2_MpllDqFuncCntl_MASK 0xffffffff
-#define DPM_TABLE_254__MemoryLevel_2_MpllDqFuncCntl__SHIFT 0x0
-#define DPM_TABLE_255__MemoryLevel_2_MclkPwrmgtCntl_MASK 0xffffffff
-#define DPM_TABLE_255__MemoryLevel_2_MclkPwrmgtCntl__SHIFT 0x0
-#define DPM_TABLE_256__MemoryLevel_2_DllCntl_MASK 0xffffffff
-#define DPM_TABLE_256__MemoryLevel_2_DllCntl__SHIFT 0x0
-#define DPM_TABLE_257__MemoryLevel_2_MpllSs1_MASK 0xffffffff
-#define DPM_TABLE_257__MemoryLevel_2_MpllSs1__SHIFT 0x0
-#define DPM_TABLE_258__MemoryLevel_2_MpllSs2_MASK 0xffffffff
-#define DPM_TABLE_258__MemoryLevel_2_MpllSs2__SHIFT 0x0
-#define DPM_TABLE_259__MemoryLevel_3_MinVddc_MASK 0xffffffff
-#define DPM_TABLE_259__MemoryLevel_3_MinVddc__SHIFT 0x0
-#define DPM_TABLE_260__MemoryLevel_3_MinVddcPhases_MASK 0xffffffff
-#define DPM_TABLE_260__MemoryLevel_3_MinVddcPhases__SHIFT 0x0
-#define DPM_TABLE_261__MemoryLevel_3_MinVddci_MASK 0xffffffff
-#define DPM_TABLE_261__MemoryLevel_3_MinVddci__SHIFT 0x0
-#define DPM_TABLE_262__MemoryLevel_3_MinMvdd_MASK 0xffffffff
-#define DPM_TABLE_262__MemoryLevel_3_MinMvdd__SHIFT 0x0
-#define DPM_TABLE_263__MemoryLevel_3_MclkFrequency_MASK 0xffffffff
-#define DPM_TABLE_263__MemoryLevel_3_MclkFrequency__SHIFT 0x0
-#define DPM_TABLE_264__MemoryLevel_3_StutterEnable_MASK 0xff
-#define DPM_TABLE_264__MemoryLevel_3_StutterEnable__SHIFT 0x0
-#define DPM_TABLE_264__MemoryLevel_3_RttEnable_MASK 0xff00
-#define DPM_TABLE_264__MemoryLevel_3_RttEnable__SHIFT 0x8
-#define DPM_TABLE_264__MemoryLevel_3_EdcWriteEnable_MASK 0xff0000
-#define DPM_TABLE_264__MemoryLevel_3_EdcWriteEnable__SHIFT 0x10
-#define DPM_TABLE_264__MemoryLevel_3_EdcReadEnable_MASK 0xff000000
-#define DPM_TABLE_264__MemoryLevel_3_EdcReadEnable__SHIFT 0x18
-#define DPM_TABLE_265__MemoryLevel_3_EnabledForActivity_MASK 0xff
-#define DPM_TABLE_265__MemoryLevel_3_EnabledForActivity__SHIFT 0x0
-#define DPM_TABLE_265__MemoryLevel_3_EnabledForThrottle_MASK 0xff00
-#define DPM_TABLE_265__MemoryLevel_3_EnabledForThrottle__SHIFT 0x8
-#define DPM_TABLE_265__MemoryLevel_3_StrobeRatio_MASK 0xff0000
-#define DPM_TABLE_265__MemoryLevel_3_StrobeRatio__SHIFT 0x10
-#define DPM_TABLE_265__MemoryLevel_3_StrobeEnable_MASK 0xff000000
-#define DPM_TABLE_265__MemoryLevel_3_StrobeEnable__SHIFT 0x18
-#define DPM_TABLE_266__MemoryLevel_3_padding_MASK 0xff
-#define DPM_TABLE_266__MemoryLevel_3_padding__SHIFT 0x0
-#define DPM_TABLE_266__MemoryLevel_3_VoltageDownHyst_MASK 0xff00
-#define DPM_TABLE_266__MemoryLevel_3_VoltageDownHyst__SHIFT 0x8
-#define DPM_TABLE_266__MemoryLevel_3_DownHyst_MASK 0xff0000
-#define DPM_TABLE_266__MemoryLevel_3_DownHyst__SHIFT 0x10
-#define DPM_TABLE_266__MemoryLevel_3_UpHyst_MASK 0xff000000
-#define DPM_TABLE_266__MemoryLevel_3_UpHyst__SHIFT 0x18
-#define DPM_TABLE_267__MemoryLevel_3_padding1_MASK 0xff
-#define DPM_TABLE_267__MemoryLevel_3_padding1__SHIFT 0x0
-#define DPM_TABLE_267__MemoryLevel_3_DisplayWatermark_MASK 0xff00
-#define DPM_TABLE_267__MemoryLevel_3_DisplayWatermark__SHIFT 0x8
-#define DPM_TABLE_267__MemoryLevel_3_ActivityLevel_MASK 0xffff0000
-#define DPM_TABLE_267__MemoryLevel_3_ActivityLevel__SHIFT 0x10
-#define DPM_TABLE_268__MemoryLevel_3_MpllFuncCntl_MASK 0xffffffff
-#define DPM_TABLE_268__MemoryLevel_3_MpllFuncCntl__SHIFT 0x0
-#define DPM_TABLE_269__MemoryLevel_3_MpllFuncCntl_1_MASK 0xffffffff
-#define DPM_TABLE_269__MemoryLevel_3_MpllFuncCntl_1__SHIFT 0x0
-#define DPM_TABLE_270__MemoryLevel_3_MpllFuncCntl_2_MASK 0xffffffff
-#define DPM_TABLE_270__MemoryLevel_3_MpllFuncCntl_2__SHIFT 0x0
-#define DPM_TABLE_271__MemoryLevel_3_MpllAdFuncCntl_MASK 0xffffffff
-#define DPM_TABLE_271__MemoryLevel_3_MpllAdFuncCntl__SHIFT 0x0
-#define DPM_TABLE_272__MemoryLevel_3_MpllDqFuncCntl_MASK 0xffffffff
-#define DPM_TABLE_272__MemoryLevel_3_MpllDqFuncCntl__SHIFT 0x0
-#define DPM_TABLE_273__MemoryLevel_3_MclkPwrmgtCntl_MASK 0xffffffff
-#define DPM_TABLE_273__MemoryLevel_3_MclkPwrmgtCntl__SHIFT 0x0
-#define DPM_TABLE_274__MemoryLevel_3_DllCntl_MASK 0xffffffff
-#define DPM_TABLE_274__MemoryLevel_3_DllCntl__SHIFT 0x0
-#define DPM_TABLE_275__MemoryLevel_3_MpllSs1_MASK 0xffffffff
-#define DPM_TABLE_275__MemoryLevel_3_MpllSs1__SHIFT 0x0
-#define DPM_TABLE_276__MemoryLevel_3_MpllSs2_MASK 0xffffffff
-#define DPM_TABLE_276__MemoryLevel_3_MpllSs2__SHIFT 0x0
-#define DPM_TABLE_277__MemoryLevel_4_MinVddc_MASK 0xffffffff
-#define DPM_TABLE_277__MemoryLevel_4_MinVddc__SHIFT 0x0
-#define DPM_TABLE_278__MemoryLevel_4_MinVddcPhases_MASK 0xffffffff
-#define DPM_TABLE_278__MemoryLevel_4_MinVddcPhases__SHIFT 0x0
-#define DPM_TABLE_279__MemoryLevel_4_MinVddci_MASK 0xffffffff
-#define DPM_TABLE_279__MemoryLevel_4_MinVddci__SHIFT 0x0
-#define DPM_TABLE_280__MemoryLevel_4_MinMvdd_MASK 0xffffffff
-#define DPM_TABLE_280__MemoryLevel_4_MinMvdd__SHIFT 0x0
-#define DPM_TABLE_281__MemoryLevel_4_MclkFrequency_MASK 0xffffffff
-#define DPM_TABLE_281__MemoryLevel_4_MclkFrequency__SHIFT 0x0
-#define DPM_TABLE_282__MemoryLevel_4_StutterEnable_MASK 0xff
-#define DPM_TABLE_282__MemoryLevel_4_StutterEnable__SHIFT 0x0
-#define DPM_TABLE_282__MemoryLevel_4_RttEnable_MASK 0xff00
-#define DPM_TABLE_282__MemoryLevel_4_RttEnable__SHIFT 0x8
-#define DPM_TABLE_282__MemoryLevel_4_EdcWriteEnable_MASK 0xff0000
-#define DPM_TABLE_282__MemoryLevel_4_EdcWriteEnable__SHIFT 0x10
-#define DPM_TABLE_282__MemoryLevel_4_EdcReadEnable_MASK 0xff000000
-#define DPM_TABLE_282__MemoryLevel_4_EdcReadEnable__SHIFT 0x18
-#define DPM_TABLE_283__MemoryLevel_4_EnabledForActivity_MASK 0xff
-#define DPM_TABLE_283__MemoryLevel_4_EnabledForActivity__SHIFT 0x0
-#define DPM_TABLE_283__MemoryLevel_4_EnabledForThrottle_MASK 0xff00
-#define DPM_TABLE_283__MemoryLevel_4_EnabledForThrottle__SHIFT 0x8
-#define DPM_TABLE_283__MemoryLevel_4_StrobeRatio_MASK 0xff0000
-#define DPM_TABLE_283__MemoryLevel_4_StrobeRatio__SHIFT 0x10
-#define DPM_TABLE_283__MemoryLevel_4_StrobeEnable_MASK 0xff000000
-#define DPM_TABLE_283__MemoryLevel_4_StrobeEnable__SHIFT 0x18
-#define DPM_TABLE_284__MemoryLevel_4_padding_MASK 0xff
-#define DPM_TABLE_284__MemoryLevel_4_padding__SHIFT 0x0
-#define DPM_TABLE_284__MemoryLevel_4_VoltageDownHyst_MASK 0xff00
-#define DPM_TABLE_284__MemoryLevel_4_VoltageDownHyst__SHIFT 0x8
-#define DPM_TABLE_284__MemoryLevel_4_DownHyst_MASK 0xff0000
-#define DPM_TABLE_284__MemoryLevel_4_DownHyst__SHIFT 0x10
-#define DPM_TABLE_284__MemoryLevel_4_UpHyst_MASK 0xff000000
-#define DPM_TABLE_284__MemoryLevel_4_UpHyst__SHIFT 0x18
-#define DPM_TABLE_285__MemoryLevel_4_padding1_MASK 0xff
-#define DPM_TABLE_285__MemoryLevel_4_padding1__SHIFT 0x0
-#define DPM_TABLE_285__MemoryLevel_4_DisplayWatermark_MASK 0xff00
-#define DPM_TABLE_285__MemoryLevel_4_DisplayWatermark__SHIFT 0x8
-#define DPM_TABLE_285__MemoryLevel_4_ActivityLevel_MASK 0xffff0000
-#define DPM_TABLE_285__MemoryLevel_4_ActivityLevel__SHIFT 0x10
-#define DPM_TABLE_286__MemoryLevel_4_MpllFuncCntl_MASK 0xffffffff
-#define DPM_TABLE_286__MemoryLevel_4_MpllFuncCntl__SHIFT 0x0
-#define DPM_TABLE_287__MemoryLevel_4_MpllFuncCntl_1_MASK 0xffffffff
-#define DPM_TABLE_287__MemoryLevel_4_MpllFuncCntl_1__SHIFT 0x0
-#define DPM_TABLE_288__MemoryLevel_4_MpllFuncCntl_2_MASK 0xffffffff
-#define DPM_TABLE_288__MemoryLevel_4_MpllFuncCntl_2__SHIFT 0x0
-#define DPM_TABLE_289__MemoryLevel_4_MpllAdFuncCntl_MASK 0xffffffff
-#define DPM_TABLE_289__MemoryLevel_4_MpllAdFuncCntl__SHIFT 0x0
-#define DPM_TABLE_290__MemoryLevel_4_MpllDqFuncCntl_MASK 0xffffffff
-#define DPM_TABLE_290__MemoryLevel_4_MpllDqFuncCntl__SHIFT 0x0
-#define DPM_TABLE_291__MemoryLevel_4_MclkPwrmgtCntl_MASK 0xffffffff
-#define DPM_TABLE_291__MemoryLevel_4_MclkPwrmgtCntl__SHIFT 0x0
-#define DPM_TABLE_292__MemoryLevel_4_DllCntl_MASK 0xffffffff
-#define DPM_TABLE_292__MemoryLevel_4_DllCntl__SHIFT 0x0
-#define DPM_TABLE_293__MemoryLevel_4_MpllSs1_MASK 0xffffffff
-#define DPM_TABLE_293__MemoryLevel_4_MpllSs1__SHIFT 0x0
-#define DPM_TABLE_294__MemoryLevel_4_MpllSs2_MASK 0xffffffff
-#define DPM_TABLE_294__MemoryLevel_4_MpllSs2__SHIFT 0x0
-#define DPM_TABLE_295__MemoryLevel_5_MinVddc_MASK 0xffffffff
-#define DPM_TABLE_295__MemoryLevel_5_MinVddc__SHIFT 0x0
-#define DPM_TABLE_296__MemoryLevel_5_MinVddcPhases_MASK 0xffffffff
-#define DPM_TABLE_296__MemoryLevel_5_MinVddcPhases__SHIFT 0x0
-#define DPM_TABLE_297__MemoryLevel_5_MinVddci_MASK 0xffffffff
-#define DPM_TABLE_297__MemoryLevel_5_MinVddci__SHIFT 0x0
-#define DPM_TABLE_298__MemoryLevel_5_MinMvdd_MASK 0xffffffff
-#define DPM_TABLE_298__MemoryLevel_5_MinMvdd__SHIFT 0x0
-#define DPM_TABLE_299__MemoryLevel_5_MclkFrequency_MASK 0xffffffff
-#define DPM_TABLE_299__MemoryLevel_5_MclkFrequency__SHIFT 0x0
-#define DPM_TABLE_300__MemoryLevel_5_StutterEnable_MASK 0xff
-#define DPM_TABLE_300__MemoryLevel_5_StutterEnable__SHIFT 0x0
-#define DPM_TABLE_300__MemoryLevel_5_RttEnable_MASK 0xff00
-#define DPM_TABLE_300__MemoryLevel_5_RttEnable__SHIFT 0x8
-#define DPM_TABLE_300__MemoryLevel_5_EdcWriteEnable_MASK 0xff0000
-#define DPM_TABLE_300__MemoryLevel_5_EdcWriteEnable__SHIFT 0x10
-#define DPM_TABLE_300__MemoryLevel_5_EdcReadEnable_MASK 0xff000000
-#define DPM_TABLE_300__MemoryLevel_5_EdcReadEnable__SHIFT 0x18
-#define DPM_TABLE_301__MemoryLevel_5_EnabledForActivity_MASK 0xff
-#define DPM_TABLE_301__MemoryLevel_5_EnabledForActivity__SHIFT 0x0
-#define DPM_TABLE_301__MemoryLevel_5_EnabledForThrottle_MASK 0xff00
-#define DPM_TABLE_301__MemoryLevel_5_EnabledForThrottle__SHIFT 0x8
-#define DPM_TABLE_301__MemoryLevel_5_StrobeRatio_MASK 0xff0000
-#define DPM_TABLE_301__MemoryLevel_5_StrobeRatio__SHIFT 0x10
-#define DPM_TABLE_301__MemoryLevel_5_StrobeEnable_MASK 0xff000000
-#define DPM_TABLE_301__MemoryLevel_5_StrobeEnable__SHIFT 0x18
-#define DPM_TABLE_302__MemoryLevel_5_padding_MASK 0xff
-#define DPM_TABLE_302__MemoryLevel_5_padding__SHIFT 0x0
-#define DPM_TABLE_302__MemoryLevel_5_VoltageDownHyst_MASK 0xff00
-#define DPM_TABLE_302__MemoryLevel_5_VoltageDownHyst__SHIFT 0x8
-#define DPM_TABLE_302__MemoryLevel_5_DownHyst_MASK 0xff0000
-#define DPM_TABLE_302__MemoryLevel_5_DownHyst__SHIFT 0x10
-#define DPM_TABLE_302__MemoryLevel_5_UpHyst_MASK 0xff000000
-#define DPM_TABLE_302__MemoryLevel_5_UpHyst__SHIFT 0x18
-#define DPM_TABLE_303__MemoryLevel_5_padding1_MASK 0xff
-#define DPM_TABLE_303__MemoryLevel_5_padding1__SHIFT 0x0
-#define DPM_TABLE_303__MemoryLevel_5_DisplayWatermark_MASK 0xff00
-#define DPM_TABLE_303__MemoryLevel_5_DisplayWatermark__SHIFT 0x8
-#define DPM_TABLE_303__MemoryLevel_5_ActivityLevel_MASK 0xffff0000
-#define DPM_TABLE_303__MemoryLevel_5_ActivityLevel__SHIFT 0x10
-#define DPM_TABLE_304__MemoryLevel_5_MpllFuncCntl_MASK 0xffffffff
-#define DPM_TABLE_304__MemoryLevel_5_MpllFuncCntl__SHIFT 0x0
-#define DPM_TABLE_305__MemoryLevel_5_MpllFuncCntl_1_MASK 0xffffffff
-#define DPM_TABLE_305__MemoryLevel_5_MpllFuncCntl_1__SHIFT 0x0
-#define DPM_TABLE_306__MemoryLevel_5_MpllFuncCntl_2_MASK 0xffffffff
-#define DPM_TABLE_306__MemoryLevel_5_MpllFuncCntl_2__SHIFT 0x0
-#define DPM_TABLE_307__MemoryLevel_5_MpllAdFuncCntl_MASK 0xffffffff
-#define DPM_TABLE_307__MemoryLevel_5_MpllAdFuncCntl__SHIFT 0x0
-#define DPM_TABLE_308__MemoryLevel_5_MpllDqFuncCntl_MASK 0xffffffff
-#define DPM_TABLE_308__MemoryLevel_5_MpllDqFuncCntl__SHIFT 0x0
-#define DPM_TABLE_309__MemoryLevel_5_MclkPwrmgtCntl_MASK 0xffffffff
-#define DPM_TABLE_309__MemoryLevel_5_MclkPwrmgtCntl__SHIFT 0x0
-#define DPM_TABLE_310__MemoryLevel_5_DllCntl_MASK 0xffffffff
-#define DPM_TABLE_310__MemoryLevel_5_DllCntl__SHIFT 0x0
-#define DPM_TABLE_311__MemoryLevel_5_MpllSs1_MASK 0xffffffff
-#define DPM_TABLE_311__MemoryLevel_5_MpllSs1__SHIFT 0x0
-#define DPM_TABLE_312__MemoryLevel_5_MpllSs2_MASK 0xffffffff
-#define DPM_TABLE_312__MemoryLevel_5_MpllSs2__SHIFT 0x0
-#define DPM_TABLE_313__LinkLevel_0_Padding_MASK 0xff
-#define DPM_TABLE_313__LinkLevel_0_Padding__SHIFT 0x0
-#define DPM_TABLE_313__LinkLevel_0_EnabledForActivity_MASK 0xff00
-#define DPM_TABLE_313__LinkLevel_0_EnabledForActivity__SHIFT 0x8
-#define DPM_TABLE_313__LinkLevel_0_PcieLaneCount_MASK 0xff0000
-#define DPM_TABLE_313__LinkLevel_0_PcieLaneCount__SHIFT 0x10
-#define DPM_TABLE_313__LinkLevel_0_PcieGenSpeed_MASK 0xff000000
-#define DPM_TABLE_313__LinkLevel_0_PcieGenSpeed__SHIFT 0x18
-#define DPM_TABLE_314__LinkLevel_0_DownThreshold_MASK 0xffffffff
-#define DPM_TABLE_314__LinkLevel_0_DownThreshold__SHIFT 0x0
-#define DPM_TABLE_315__LinkLevel_0_UpThreshold_MASK 0xffffffff
-#define DPM_TABLE_315__LinkLevel_0_UpThreshold__SHIFT 0x0
-#define DPM_TABLE_316__LinkLevel_0_Reserved_MASK 0xffffffff
-#define DPM_TABLE_316__LinkLevel_0_Reserved__SHIFT 0x0
-#define DPM_TABLE_317__LinkLevel_1_Padding_MASK 0xff
-#define DPM_TABLE_317__LinkLevel_1_Padding__SHIFT 0x0
-#define DPM_TABLE_317__LinkLevel_1_EnabledForActivity_MASK 0xff00
-#define DPM_TABLE_317__LinkLevel_1_EnabledForActivity__SHIFT 0x8
-#define DPM_TABLE_317__LinkLevel_1_PcieLaneCount_MASK 0xff0000
-#define DPM_TABLE_317__LinkLevel_1_PcieLaneCount__SHIFT 0x10
-#define DPM_TABLE_317__LinkLevel_1_PcieGenSpeed_MASK 0xff000000
-#define DPM_TABLE_317__LinkLevel_1_PcieGenSpeed__SHIFT 0x18
-#define DPM_TABLE_318__LinkLevel_1_DownThreshold_MASK 0xffffffff
-#define DPM_TABLE_318__LinkLevel_1_DownThreshold__SHIFT 0x0
-#define DPM_TABLE_319__LinkLevel_1_UpThreshold_MASK 0xffffffff
-#define DPM_TABLE_319__LinkLevel_1_UpThreshold__SHIFT 0x0
-#define DPM_TABLE_320__LinkLevel_1_Reserved_MASK 0xffffffff
-#define DPM_TABLE_320__LinkLevel_1_Reserved__SHIFT 0x0
-#define DPM_TABLE_321__LinkLevel_2_Padding_MASK 0xff
-#define DPM_TABLE_321__LinkLevel_2_Padding__SHIFT 0x0
-#define DPM_TABLE_321__LinkLevel_2_EnabledForActivity_MASK 0xff00
-#define DPM_TABLE_321__LinkLevel_2_EnabledForActivity__SHIFT 0x8
-#define DPM_TABLE_321__LinkLevel_2_PcieLaneCount_MASK 0xff0000
-#define DPM_TABLE_321__LinkLevel_2_PcieLaneCount__SHIFT 0x10
-#define DPM_TABLE_321__LinkLevel_2_PcieGenSpeed_MASK 0xff000000
-#define DPM_TABLE_321__LinkLevel_2_PcieGenSpeed__SHIFT 0x18
-#define DPM_TABLE_322__LinkLevel_2_DownThreshold_MASK 0xffffffff
-#define DPM_TABLE_322__LinkLevel_2_DownThreshold__SHIFT 0x0
-#define DPM_TABLE_323__LinkLevel_2_UpThreshold_MASK 0xffffffff
-#define DPM_TABLE_323__LinkLevel_2_UpThreshold__SHIFT 0x0
-#define DPM_TABLE_324__LinkLevel_2_Reserved_MASK 0xffffffff
-#define DPM_TABLE_324__LinkLevel_2_Reserved__SHIFT 0x0
-#define DPM_TABLE_325__LinkLevel_3_Padding_MASK 0xff
-#define DPM_TABLE_325__LinkLevel_3_Padding__SHIFT 0x0
-#define DPM_TABLE_325__LinkLevel_3_EnabledForActivity_MASK 0xff00
-#define DPM_TABLE_325__LinkLevel_3_EnabledForActivity__SHIFT 0x8
-#define DPM_TABLE_325__LinkLevel_3_PcieLaneCount_MASK 0xff0000
-#define DPM_TABLE_325__LinkLevel_3_PcieLaneCount__SHIFT 0x10
-#define DPM_TABLE_325__LinkLevel_3_PcieGenSpeed_MASK 0xff000000
-#define DPM_TABLE_325__LinkLevel_3_PcieGenSpeed__SHIFT 0x18
-#define DPM_TABLE_326__LinkLevel_3_DownThreshold_MASK 0xffffffff
-#define DPM_TABLE_326__LinkLevel_3_DownThreshold__SHIFT 0x0
-#define DPM_TABLE_327__LinkLevel_3_UpThreshold_MASK 0xffffffff
-#define DPM_TABLE_327__LinkLevel_3_UpThreshold__SHIFT 0x0
-#define DPM_TABLE_328__LinkLevel_3_Reserved_MASK 0xffffffff
-#define DPM_TABLE_328__LinkLevel_3_Reserved__SHIFT 0x0
-#define DPM_TABLE_329__LinkLevel_4_Padding_MASK 0xff
-#define DPM_TABLE_329__LinkLevel_4_Padding__SHIFT 0x0
-#define DPM_TABLE_329__LinkLevel_4_EnabledForActivity_MASK 0xff00
-#define DPM_TABLE_329__LinkLevel_4_EnabledForActivity__SHIFT 0x8
-#define DPM_TABLE_329__LinkLevel_4_PcieLaneCount_MASK 0xff0000
-#define DPM_TABLE_329__LinkLevel_4_PcieLaneCount__SHIFT 0x10
-#define DPM_TABLE_329__LinkLevel_4_PcieGenSpeed_MASK 0xff000000
-#define DPM_TABLE_329__LinkLevel_4_PcieGenSpeed__SHIFT 0x18
-#define DPM_TABLE_330__LinkLevel_4_DownThreshold_MASK 0xffffffff
-#define DPM_TABLE_330__LinkLevel_4_DownThreshold__SHIFT 0x0
-#define DPM_TABLE_331__LinkLevel_4_UpThreshold_MASK 0xffffffff
-#define DPM_TABLE_331__LinkLevel_4_UpThreshold__SHIFT 0x0
-#define DPM_TABLE_332__LinkLevel_4_Reserved_MASK 0xffffffff
-#define DPM_TABLE_332__LinkLevel_4_Reserved__SHIFT 0x0
-#define DPM_TABLE_333__LinkLevel_5_Padding_MASK 0xff
-#define DPM_TABLE_333__LinkLevel_5_Padding__SHIFT 0x0
-#define DPM_TABLE_333__LinkLevel_5_EnabledForActivity_MASK 0xff00
-#define DPM_TABLE_333__LinkLevel_5_EnabledForActivity__SHIFT 0x8
-#define DPM_TABLE_333__LinkLevel_5_PcieLaneCount_MASK 0xff0000
-#define DPM_TABLE_333__LinkLevel_5_PcieLaneCount__SHIFT 0x10
-#define DPM_TABLE_333__LinkLevel_5_PcieGenSpeed_MASK 0xff000000
-#define DPM_TABLE_333__LinkLevel_5_PcieGenSpeed__SHIFT 0x18
-#define DPM_TABLE_334__LinkLevel_5_DownThreshold_MASK 0xffffffff
-#define DPM_TABLE_334__LinkLevel_5_DownThreshold__SHIFT 0x0
-#define DPM_TABLE_335__LinkLevel_5_UpThreshold_MASK 0xffffffff
-#define DPM_TABLE_335__LinkLevel_5_UpThreshold__SHIFT 0x0
-#define DPM_TABLE_336__LinkLevel_5_Reserved_MASK 0xffffffff
-#define DPM_TABLE_336__LinkLevel_5_Reserved__SHIFT 0x0
-#define DPM_TABLE_337__LinkLevel_6_Padding_MASK 0xff
-#define DPM_TABLE_337__LinkLevel_6_Padding__SHIFT 0x0
-#define DPM_TABLE_337__LinkLevel_6_EnabledForActivity_MASK 0xff00
-#define DPM_TABLE_337__LinkLevel_6_EnabledForActivity__SHIFT 0x8
-#define DPM_TABLE_337__LinkLevel_6_PcieLaneCount_MASK 0xff0000
-#define DPM_TABLE_337__LinkLevel_6_PcieLaneCount__SHIFT 0x10
-#define DPM_TABLE_337__LinkLevel_6_PcieGenSpeed_MASK 0xff000000
-#define DPM_TABLE_337__LinkLevel_6_PcieGenSpeed__SHIFT 0x18
-#define DPM_TABLE_338__LinkLevel_6_DownThreshold_MASK 0xffffffff
-#define DPM_TABLE_338__LinkLevel_6_DownThreshold__SHIFT 0x0
-#define DPM_TABLE_339__LinkLevel_6_UpThreshold_MASK 0xffffffff
-#define DPM_TABLE_339__LinkLevel_6_UpThreshold__SHIFT 0x0
-#define DPM_TABLE_340__LinkLevel_6_Reserved_MASK 0xffffffff
-#define DPM_TABLE_340__LinkLevel_6_Reserved__SHIFT 0x0
-#define DPM_TABLE_341__LinkLevel_7_Padding_MASK 0xff
-#define DPM_TABLE_341__LinkLevel_7_Padding__SHIFT 0x0
-#define DPM_TABLE_341__LinkLevel_7_EnabledForActivity_MASK 0xff00
-#define DPM_TABLE_341__LinkLevel_7_EnabledForActivity__SHIFT 0x8
-#define DPM_TABLE_341__LinkLevel_7_PcieLaneCount_MASK 0xff0000
-#define DPM_TABLE_341__LinkLevel_7_PcieLaneCount__SHIFT 0x10
-#define DPM_TABLE_341__LinkLevel_7_PcieGenSpeed_MASK 0xff000000
-#define DPM_TABLE_341__LinkLevel_7_PcieGenSpeed__SHIFT 0x18
-#define DPM_TABLE_342__LinkLevel_7_DownThreshold_MASK 0xffffffff
-#define DPM_TABLE_342__LinkLevel_7_DownThreshold__SHIFT 0x0
-#define DPM_TABLE_343__LinkLevel_7_UpThreshold_MASK 0xffffffff
-#define DPM_TABLE_343__LinkLevel_7_UpThreshold__SHIFT 0x0
-#define DPM_TABLE_344__LinkLevel_7_Reserved_MASK 0xffffffff
-#define DPM_TABLE_344__LinkLevel_7_Reserved__SHIFT 0x0
-#define DPM_TABLE_345__ACPILevel_Flags_MASK 0xffffffff
-#define DPM_TABLE_345__ACPILevel_Flags__SHIFT 0x0
-#define DPM_TABLE_346__ACPILevel_MinVddc_MASK 0xffffffff
-#define DPM_TABLE_346__ACPILevel_MinVddc__SHIFT 0x0
-#define DPM_TABLE_347__ACPILevel_MinVddcPhases_MASK 0xffffffff
-#define DPM_TABLE_347__ACPILevel_MinVddcPhases__SHIFT 0x0
-#define DPM_TABLE_348__ACPILevel_SclkFrequency_MASK 0xffffffff
-#define DPM_TABLE_348__ACPILevel_SclkFrequency__SHIFT 0x0
-#define DPM_TABLE_349__ACPILevel_padding_MASK 0xff
-#define DPM_TABLE_349__ACPILevel_padding__SHIFT 0x0
-#define DPM_TABLE_349__ACPILevel_DeepSleepDivId_MASK 0xff00
-#define DPM_TABLE_349__ACPILevel_DeepSleepDivId__SHIFT 0x8
-#define DPM_TABLE_349__ACPILevel_DisplayWatermark_MASK 0xff0000
-#define DPM_TABLE_349__ACPILevel_DisplayWatermark__SHIFT 0x10
-#define DPM_TABLE_349__ACPILevel_SclkDid_MASK 0xff000000
-#define DPM_TABLE_349__ACPILevel_SclkDid__SHIFT 0x18
-#define DPM_TABLE_350__ACPILevel_CgSpllFuncCntl_MASK 0xffffffff
-#define DPM_TABLE_350__ACPILevel_CgSpllFuncCntl__SHIFT 0x0
-#define DPM_TABLE_351__ACPILevel_CgSpllFuncCntl2_MASK 0xffffffff
-#define DPM_TABLE_351__ACPILevel_CgSpllFuncCntl2__SHIFT 0x0
-#define DPM_TABLE_352__ACPILevel_CgSpllFuncCntl3_MASK 0xffffffff
-#define DPM_TABLE_352__ACPILevel_CgSpllFuncCntl3__SHIFT 0x0
-#define DPM_TABLE_353__ACPILevel_CgSpllFuncCntl4_MASK 0xffffffff
-#define DPM_TABLE_353__ACPILevel_CgSpllFuncCntl4__SHIFT 0x0
-#define DPM_TABLE_354__ACPILevel_SpllSpreadSpectrum_MASK 0xffffffff
-#define DPM_TABLE_354__ACPILevel_SpllSpreadSpectrum__SHIFT 0x0
-#define DPM_TABLE_355__ACPILevel_SpllSpreadSpectrum2_MASK 0xffffffff
-#define DPM_TABLE_355__ACPILevel_SpllSpreadSpectrum2__SHIFT 0x0
-#define DPM_TABLE_356__ACPILevel_CcPwrDynRm_MASK 0xffffffff
-#define DPM_TABLE_356__ACPILevel_CcPwrDynRm__SHIFT 0x0
-#define DPM_TABLE_357__ACPILevel_CcPwrDynRm1_MASK 0xffffffff
-#define DPM_TABLE_357__ACPILevel_CcPwrDynRm1__SHIFT 0x0
-#define DPM_TABLE_358__UvdLevel_0_VclkFrequency_MASK 0xffffffff
-#define DPM_TABLE_358__UvdLevel_0_VclkFrequency__SHIFT 0x0
-#define DPM_TABLE_359__UvdLevel_0_DclkFrequency_MASK 0xffffffff
-#define DPM_TABLE_359__UvdLevel_0_DclkFrequency__SHIFT 0x0
-#define DPM_TABLE_360__UvdLevel_0_VclkDivider_MASK 0xff
-#define DPM_TABLE_360__UvdLevel_0_VclkDivider__SHIFT 0x0
-#define DPM_TABLE_360__UvdLevel_0_MinVddcPhases_MASK 0xff00
-#define DPM_TABLE_360__UvdLevel_0_MinVddcPhases__SHIFT 0x8
-#define DPM_TABLE_360__UvdLevel_0_MinVddc_MASK 0xffff0000
-#define DPM_TABLE_360__UvdLevel_0_MinVddc__SHIFT 0x10
-#define DPM_TABLE_361__UvdLevel_0_padding_2_MASK 0xff
-#define DPM_TABLE_361__UvdLevel_0_padding_2__SHIFT 0x0
-#define DPM_TABLE_361__UvdLevel_0_padding_1_MASK 0xff00
-#define DPM_TABLE_361__UvdLevel_0_padding_1__SHIFT 0x8
-#define DPM_TABLE_361__UvdLevel_0_padding_0_MASK 0xff0000
-#define DPM_TABLE_361__UvdLevel_0_padding_0__SHIFT 0x10
-#define DPM_TABLE_361__UvdLevel_0_DclkDivider_MASK 0xff000000
-#define DPM_TABLE_361__UvdLevel_0_DclkDivider__SHIFT 0x18
-#define DPM_TABLE_362__UvdLevel_1_VclkFrequency_MASK 0xffffffff
-#define DPM_TABLE_362__UvdLevel_1_VclkFrequency__SHIFT 0x0
-#define DPM_TABLE_363__UvdLevel_1_DclkFrequency_MASK 0xffffffff
-#define DPM_TABLE_363__UvdLevel_1_DclkFrequency__SHIFT 0x0
-#define DPM_TABLE_364__UvdLevel_1_VclkDivider_MASK 0xff
-#define DPM_TABLE_364__UvdLevel_1_VclkDivider__SHIFT 0x0
-#define DPM_TABLE_364__UvdLevel_1_MinVddcPhases_MASK 0xff00
-#define DPM_TABLE_364__UvdLevel_1_MinVddcPhases__SHIFT 0x8
-#define DPM_TABLE_364__UvdLevel_1_MinVddc_MASK 0xffff0000
-#define DPM_TABLE_364__UvdLevel_1_MinVddc__SHIFT 0x10
-#define DPM_TABLE_365__UvdLevel_1_padding_2_MASK 0xff
-#define DPM_TABLE_365__UvdLevel_1_padding_2__SHIFT 0x0
-#define DPM_TABLE_365__UvdLevel_1_padding_1_MASK 0xff00
-#define DPM_TABLE_365__UvdLevel_1_padding_1__SHIFT 0x8
-#define DPM_TABLE_365__UvdLevel_1_padding_0_MASK 0xff0000
-#define DPM_TABLE_365__UvdLevel_1_padding_0__SHIFT 0x10
-#define DPM_TABLE_365__UvdLevel_1_DclkDivider_MASK 0xff000000
-#define DPM_TABLE_365__UvdLevel_1_DclkDivider__SHIFT 0x18
-#define DPM_TABLE_366__UvdLevel_2_VclkFrequency_MASK 0xffffffff
-#define DPM_TABLE_366__UvdLevel_2_VclkFrequency__SHIFT 0x0
-#define DPM_TABLE_367__UvdLevel_2_DclkFrequency_MASK 0xffffffff
-#define DPM_TABLE_367__UvdLevel_2_DclkFrequency__SHIFT 0x0
-#define DPM_TABLE_368__UvdLevel_2_VclkDivider_MASK 0xff
-#define DPM_TABLE_368__UvdLevel_2_VclkDivider__SHIFT 0x0
-#define DPM_TABLE_368__UvdLevel_2_MinVddcPhases_MASK 0xff00
-#define DPM_TABLE_368__UvdLevel_2_MinVddcPhases__SHIFT 0x8
-#define DPM_TABLE_368__UvdLevel_2_MinVddc_MASK 0xffff0000
-#define DPM_TABLE_368__UvdLevel_2_MinVddc__SHIFT 0x10
-#define DPM_TABLE_369__UvdLevel_2_padding_2_MASK 0xff
-#define DPM_TABLE_369__UvdLevel_2_padding_2__SHIFT 0x0
-#define DPM_TABLE_369__UvdLevel_2_padding_1_MASK 0xff00
-#define DPM_TABLE_369__UvdLevel_2_padding_1__SHIFT 0x8
-#define DPM_TABLE_369__UvdLevel_2_padding_0_MASK 0xff0000
-#define DPM_TABLE_369__UvdLevel_2_padding_0__SHIFT 0x10
-#define DPM_TABLE_369__UvdLevel_2_DclkDivider_MASK 0xff000000
-#define DPM_TABLE_369__UvdLevel_2_DclkDivider__SHIFT 0x18
-#define DPM_TABLE_370__UvdLevel_3_VclkFrequency_MASK 0xffffffff
-#define DPM_TABLE_370__UvdLevel_3_VclkFrequency__SHIFT 0x0
-#define DPM_TABLE_371__UvdLevel_3_DclkFrequency_MASK 0xffffffff
-#define DPM_TABLE_371__UvdLevel_3_DclkFrequency__SHIFT 0x0
-#define DPM_TABLE_372__UvdLevel_3_VclkDivider_MASK 0xff
-#define DPM_TABLE_372__UvdLevel_3_VclkDivider__SHIFT 0x0
-#define DPM_TABLE_372__UvdLevel_3_MinVddcPhases_MASK 0xff00
-#define DPM_TABLE_372__UvdLevel_3_MinVddcPhases__SHIFT 0x8
-#define DPM_TABLE_372__UvdLevel_3_MinVddc_MASK 0xffff0000
-#define DPM_TABLE_372__UvdLevel_3_MinVddc__SHIFT 0x10
-#define DPM_TABLE_373__UvdLevel_3_padding_2_MASK 0xff
-#define DPM_TABLE_373__UvdLevel_3_padding_2__SHIFT 0x0
-#define DPM_TABLE_373__UvdLevel_3_padding_1_MASK 0xff00
-#define DPM_TABLE_373__UvdLevel_3_padding_1__SHIFT 0x8
-#define DPM_TABLE_373__UvdLevel_3_padding_0_MASK 0xff0000
-#define DPM_TABLE_373__UvdLevel_3_padding_0__SHIFT 0x10
-#define DPM_TABLE_373__UvdLevel_3_DclkDivider_MASK 0xff000000
-#define DPM_TABLE_373__UvdLevel_3_DclkDivider__SHIFT 0x18
-#define DPM_TABLE_374__UvdLevel_4_VclkFrequency_MASK 0xffffffff
-#define DPM_TABLE_374__UvdLevel_4_VclkFrequency__SHIFT 0x0
-#define DPM_TABLE_375__UvdLevel_4_DclkFrequency_MASK 0xffffffff
-#define DPM_TABLE_375__UvdLevel_4_DclkFrequency__SHIFT 0x0
-#define DPM_TABLE_376__UvdLevel_4_VclkDivider_MASK 0xff
-#define DPM_TABLE_376__UvdLevel_4_VclkDivider__SHIFT 0x0
-#define DPM_TABLE_376__UvdLevel_4_MinVddcPhases_MASK 0xff00
-#define DPM_TABLE_376__UvdLevel_4_MinVddcPhases__SHIFT 0x8
-#define DPM_TABLE_376__UvdLevel_4_MinVddc_MASK 0xffff0000
-#define DPM_TABLE_376__UvdLevel_4_MinVddc__SHIFT 0x10
-#define DPM_TABLE_377__UvdLevel_4_padding_2_MASK 0xff
-#define DPM_TABLE_377__UvdLevel_4_padding_2__SHIFT 0x0
-#define DPM_TABLE_377__UvdLevel_4_padding_1_MASK 0xff00
-#define DPM_TABLE_377__UvdLevel_4_padding_1__SHIFT 0x8
-#define DPM_TABLE_377__UvdLevel_4_padding_0_MASK 0xff0000
-#define DPM_TABLE_377__UvdLevel_4_padding_0__SHIFT 0x10
-#define DPM_TABLE_377__UvdLevel_4_DclkDivider_MASK 0xff000000
-#define DPM_TABLE_377__UvdLevel_4_DclkDivider__SHIFT 0x18
-#define DPM_TABLE_378__UvdLevel_5_VclkFrequency_MASK 0xffffffff
-#define DPM_TABLE_378__UvdLevel_5_VclkFrequency__SHIFT 0x0
-#define DPM_TABLE_379__UvdLevel_5_DclkFrequency_MASK 0xffffffff
-#define DPM_TABLE_379__UvdLevel_5_DclkFrequency__SHIFT 0x0
-#define DPM_TABLE_380__UvdLevel_5_VclkDivider_MASK 0xff
-#define DPM_TABLE_380__UvdLevel_5_VclkDivider__SHIFT 0x0
-#define DPM_TABLE_380__UvdLevel_5_MinVddcPhases_MASK 0xff00
-#define DPM_TABLE_380__UvdLevel_5_MinVddcPhases__SHIFT 0x8
-#define DPM_TABLE_380__UvdLevel_5_MinVddc_MASK 0xffff0000
-#define DPM_TABLE_380__UvdLevel_5_MinVddc__SHIFT 0x10
-#define DPM_TABLE_381__UvdLevel_5_padding_2_MASK 0xff
-#define DPM_TABLE_381__UvdLevel_5_padding_2__SHIFT 0x0
-#define DPM_TABLE_381__UvdLevel_5_padding_1_MASK 0xff00
-#define DPM_TABLE_381__UvdLevel_5_padding_1__SHIFT 0x8
-#define DPM_TABLE_381__UvdLevel_5_padding_0_MASK 0xff0000
-#define DPM_TABLE_381__UvdLevel_5_padding_0__SHIFT 0x10
-#define DPM_TABLE_381__UvdLevel_5_DclkDivider_MASK 0xff000000
-#define DPM_TABLE_381__UvdLevel_5_DclkDivider__SHIFT 0x18
-#define DPM_TABLE_382__UvdLevel_6_VclkFrequency_MASK 0xffffffff
-#define DPM_TABLE_382__UvdLevel_6_VclkFrequency__SHIFT 0x0
-#define DPM_TABLE_383__UvdLevel_6_DclkFrequency_MASK 0xffffffff
-#define DPM_TABLE_383__UvdLevel_6_DclkFrequency__SHIFT 0x0
-#define DPM_TABLE_384__UvdLevel_6_VclkDivider_MASK 0xff
-#define DPM_TABLE_384__UvdLevel_6_VclkDivider__SHIFT 0x0
-#define DPM_TABLE_384__UvdLevel_6_MinVddcPhases_MASK 0xff00
-#define DPM_TABLE_384__UvdLevel_6_MinVddcPhases__SHIFT 0x8
-#define DPM_TABLE_384__UvdLevel_6_MinVddc_MASK 0xffff0000
-#define DPM_TABLE_384__UvdLevel_6_MinVddc__SHIFT 0x10
-#define DPM_TABLE_385__UvdLevel_6_padding_2_MASK 0xff
-#define DPM_TABLE_385__UvdLevel_6_padding_2__SHIFT 0x0
-#define DPM_TABLE_385__UvdLevel_6_padding_1_MASK 0xff00
-#define DPM_TABLE_385__UvdLevel_6_padding_1__SHIFT 0x8
-#define DPM_TABLE_385__UvdLevel_6_padding_0_MASK 0xff0000
-#define DPM_TABLE_385__UvdLevel_6_padding_0__SHIFT 0x10
-#define DPM_TABLE_385__UvdLevel_6_DclkDivider_MASK 0xff000000
-#define DPM_TABLE_385__UvdLevel_6_DclkDivider__SHIFT 0x18
-#define DPM_TABLE_386__UvdLevel_7_VclkFrequency_MASK 0xffffffff
-#define DPM_TABLE_386__UvdLevel_7_VclkFrequency__SHIFT 0x0
-#define DPM_TABLE_387__UvdLevel_7_DclkFrequency_MASK 0xffffffff
-#define DPM_TABLE_387__UvdLevel_7_DclkFrequency__SHIFT 0x0
-#define DPM_TABLE_388__UvdLevel_7_VclkDivider_MASK 0xff
-#define DPM_TABLE_388__UvdLevel_7_VclkDivider__SHIFT 0x0
-#define DPM_TABLE_388__UvdLevel_7_MinVddcPhases_MASK 0xff00
-#define DPM_TABLE_388__UvdLevel_7_MinVddcPhases__SHIFT 0x8
-#define DPM_TABLE_388__UvdLevel_7_MinVddc_MASK 0xffff0000
-#define DPM_TABLE_388__UvdLevel_7_MinVddc__SHIFT 0x10
-#define DPM_TABLE_389__UvdLevel_7_padding_2_MASK 0xff
-#define DPM_TABLE_389__UvdLevel_7_padding_2__SHIFT 0x0
-#define DPM_TABLE_389__UvdLevel_7_padding_1_MASK 0xff00
-#define DPM_TABLE_389__UvdLevel_7_padding_1__SHIFT 0x8
-#define DPM_TABLE_389__UvdLevel_7_padding_0_MASK 0xff0000
-#define DPM_TABLE_389__UvdLevel_7_padding_0__SHIFT 0x10
-#define DPM_TABLE_389__UvdLevel_7_DclkDivider_MASK 0xff000000
-#define DPM_TABLE_389__UvdLevel_7_DclkDivider__SHIFT 0x18
-#define DPM_TABLE_390__VceLevel_0_Frequency_MASK 0xffffffff
-#define DPM_TABLE_390__VceLevel_0_Frequency__SHIFT 0x0
-#define DPM_TABLE_391__VceLevel_0_Divider_MASK 0xff
-#define DPM_TABLE_391__VceLevel_0_Divider__SHIFT 0x0
-#define DPM_TABLE_391__VceLevel_0_MinPhases_MASK 0xff00
-#define DPM_TABLE_391__VceLevel_0_MinPhases__SHIFT 0x8
-#define DPM_TABLE_391__VceLevel_0_MinVoltage_MASK 0xffff0000
-#define DPM_TABLE_391__VceLevel_0_MinVoltage__SHIFT 0x10
-#define DPM_TABLE_392__VceLevel_1_Frequency_MASK 0xffffffff
-#define DPM_TABLE_392__VceLevel_1_Frequency__SHIFT 0x0
-#define DPM_TABLE_393__VceLevel_1_Divider_MASK 0xff
-#define DPM_TABLE_393__VceLevel_1_Divider__SHIFT 0x0
-#define DPM_TABLE_393__VceLevel_1_MinPhases_MASK 0xff00
-#define DPM_TABLE_393__VceLevel_1_MinPhases__SHIFT 0x8
-#define DPM_TABLE_393__VceLevel_1_MinVoltage_MASK 0xffff0000
-#define DPM_TABLE_393__VceLevel_1_MinVoltage__SHIFT 0x10
-#define DPM_TABLE_394__VceLevel_2_Frequency_MASK 0xffffffff
-#define DPM_TABLE_394__VceLevel_2_Frequency__SHIFT 0x0
-#define DPM_TABLE_395__VceLevel_2_Divider_MASK 0xff
-#define DPM_TABLE_395__VceLevel_2_Divider__SHIFT 0x0
-#define DPM_TABLE_395__VceLevel_2_MinPhases_MASK 0xff00
-#define DPM_TABLE_395__VceLevel_2_MinPhases__SHIFT 0x8
-#define DPM_TABLE_395__VceLevel_2_MinVoltage_MASK 0xffff0000
-#define DPM_TABLE_395__VceLevel_2_MinVoltage__SHIFT 0x10
-#define DPM_TABLE_396__VceLevel_3_Frequency_MASK 0xffffffff
-#define DPM_TABLE_396__VceLevel_3_Frequency__SHIFT 0x0
-#define DPM_TABLE_397__VceLevel_3_Divider_MASK 0xff
-#define DPM_TABLE_397__VceLevel_3_Divider__SHIFT 0x0
-#define DPM_TABLE_397__VceLevel_3_MinPhases_MASK 0xff00
-#define DPM_TABLE_397__VceLevel_3_MinPhases__SHIFT 0x8
-#define DPM_TABLE_397__VceLevel_3_MinVoltage_MASK 0xffff0000
-#define DPM_TABLE_397__VceLevel_3_MinVoltage__SHIFT 0x10
-#define DPM_TABLE_398__VceLevel_4_Frequency_MASK 0xffffffff
-#define DPM_TABLE_398__VceLevel_4_Frequency__SHIFT 0x0
-#define DPM_TABLE_399__VceLevel_4_Divider_MASK 0xff
-#define DPM_TABLE_399__VceLevel_4_Divider__SHIFT 0x0
-#define DPM_TABLE_399__VceLevel_4_MinPhases_MASK 0xff00
-#define DPM_TABLE_399__VceLevel_4_MinPhases__SHIFT 0x8
-#define DPM_TABLE_399__VceLevel_4_MinVoltage_MASK 0xffff0000
-#define DPM_TABLE_399__VceLevel_4_MinVoltage__SHIFT 0x10
-#define DPM_TABLE_400__VceLevel_5_Frequency_MASK 0xffffffff
-#define DPM_TABLE_400__VceLevel_5_Frequency__SHIFT 0x0
-#define DPM_TABLE_401__VceLevel_5_Divider_MASK 0xff
-#define DPM_TABLE_401__VceLevel_5_Divider__SHIFT 0x0
-#define DPM_TABLE_401__VceLevel_5_MinPhases_MASK 0xff00
-#define DPM_TABLE_401__VceLevel_5_MinPhases__SHIFT 0x8
-#define DPM_TABLE_401__VceLevel_5_MinVoltage_MASK 0xffff0000
-#define DPM_TABLE_401__VceLevel_5_MinVoltage__SHIFT 0x10
-#define DPM_TABLE_402__VceLevel_6_Frequency_MASK 0xffffffff
-#define DPM_TABLE_402__VceLevel_6_Frequency__SHIFT 0x0
-#define DPM_TABLE_403__VceLevel_6_Divider_MASK 0xff
-#define DPM_TABLE_403__VceLevel_6_Divider__SHIFT 0x0
-#define DPM_TABLE_403__VceLevel_6_MinPhases_MASK 0xff00
-#define DPM_TABLE_403__VceLevel_6_MinPhases__SHIFT 0x8
-#define DPM_TABLE_403__VceLevel_6_MinVoltage_MASK 0xffff0000
-#define DPM_TABLE_403__VceLevel_6_MinVoltage__SHIFT 0x10
-#define DPM_TABLE_404__VceLevel_7_Frequency_MASK 0xffffffff
-#define DPM_TABLE_404__VceLevel_7_Frequency__SHIFT 0x0
-#define DPM_TABLE_405__VceLevel_7_Divider_MASK 0xff
-#define DPM_TABLE_405__VceLevel_7_Divider__SHIFT 0x0
-#define DPM_TABLE_405__VceLevel_7_MinPhases_MASK 0xff00
-#define DPM_TABLE_405__VceLevel_7_MinPhases__SHIFT 0x8
-#define DPM_TABLE_405__VceLevel_7_MinVoltage_MASK 0xffff0000
-#define DPM_TABLE_405__VceLevel_7_MinVoltage__SHIFT 0x10
-#define DPM_TABLE_406__AcpLevel_0_Frequency_MASK 0xffffffff
-#define DPM_TABLE_406__AcpLevel_0_Frequency__SHIFT 0x0
-#define DPM_TABLE_407__AcpLevel_0_Divider_MASK 0xff
-#define DPM_TABLE_407__AcpLevel_0_Divider__SHIFT 0x0
-#define DPM_TABLE_407__AcpLevel_0_MinPhases_MASK 0xff00
-#define DPM_TABLE_407__AcpLevel_0_MinPhases__SHIFT 0x8
-#define DPM_TABLE_407__AcpLevel_0_MinVoltage_MASK 0xffff0000
-#define DPM_TABLE_407__AcpLevel_0_MinVoltage__SHIFT 0x10
-#define DPM_TABLE_408__AcpLevel_1_Frequency_MASK 0xffffffff
-#define DPM_TABLE_408__AcpLevel_1_Frequency__SHIFT 0x0
-#define DPM_TABLE_409__AcpLevel_1_Divider_MASK 0xff
-#define DPM_TABLE_409__AcpLevel_1_Divider__SHIFT 0x0
-#define DPM_TABLE_409__AcpLevel_1_MinPhases_MASK 0xff00
-#define DPM_TABLE_409__AcpLevel_1_MinPhases__SHIFT 0x8
-#define DPM_TABLE_409__AcpLevel_1_MinVoltage_MASK 0xffff0000
-#define DPM_TABLE_409__AcpLevel_1_MinVoltage__SHIFT 0x10
-#define DPM_TABLE_410__AcpLevel_2_Frequency_MASK 0xffffffff
-#define DPM_TABLE_410__AcpLevel_2_Frequency__SHIFT 0x0
-#define DPM_TABLE_411__AcpLevel_2_Divider_MASK 0xff
-#define DPM_TABLE_411__AcpLevel_2_Divider__SHIFT 0x0
-#define DPM_TABLE_411__AcpLevel_2_MinPhases_MASK 0xff00
-#define DPM_TABLE_411__AcpLevel_2_MinPhases__SHIFT 0x8
-#define DPM_TABLE_411__AcpLevel_2_MinVoltage_MASK 0xffff0000
-#define DPM_TABLE_411__AcpLevel_2_MinVoltage__SHIFT 0x10
-#define DPM_TABLE_412__AcpLevel_3_Frequency_MASK 0xffffffff
-#define DPM_TABLE_412__AcpLevel_3_Frequency__SHIFT 0x0
-#define DPM_TABLE_413__AcpLevel_3_Divider_MASK 0xff
-#define DPM_TABLE_413__AcpLevel_3_Divider__SHIFT 0x0
-#define DPM_TABLE_413__AcpLevel_3_MinPhases_MASK 0xff00
-#define DPM_TABLE_413__AcpLevel_3_MinPhases__SHIFT 0x8
-#define DPM_TABLE_413__AcpLevel_3_MinVoltage_MASK 0xffff0000
-#define DPM_TABLE_413__AcpLevel_3_MinVoltage__SHIFT 0x10
-#define DPM_TABLE_414__AcpLevel_4_Frequency_MASK 0xffffffff
-#define DPM_TABLE_414__AcpLevel_4_Frequency__SHIFT 0x0
-#define DPM_TABLE_415__AcpLevel_4_Divider_MASK 0xff
-#define DPM_TABLE_415__AcpLevel_4_Divider__SHIFT 0x0
-#define DPM_TABLE_415__AcpLevel_4_MinPhases_MASK 0xff00
-#define DPM_TABLE_415__AcpLevel_4_MinPhases__SHIFT 0x8
-#define DPM_TABLE_415__AcpLevel_4_MinVoltage_MASK 0xffff0000
-#define DPM_TABLE_415__AcpLevel_4_MinVoltage__SHIFT 0x10
-#define DPM_TABLE_416__AcpLevel_5_Frequency_MASK 0xffffffff
-#define DPM_TABLE_416__AcpLevel_5_Frequency__SHIFT 0x0
-#define DPM_TABLE_417__AcpLevel_5_Divider_MASK 0xff
-#define DPM_TABLE_417__AcpLevel_5_Divider__SHIFT 0x0
-#define DPM_TABLE_417__AcpLevel_5_MinPhases_MASK 0xff00
-#define DPM_TABLE_417__AcpLevel_5_MinPhases__SHIFT 0x8
-#define DPM_TABLE_417__AcpLevel_5_MinVoltage_MASK 0xffff0000
-#define DPM_TABLE_417__AcpLevel_5_MinVoltage__SHIFT 0x10
-#define DPM_TABLE_418__AcpLevel_6_Frequency_MASK 0xffffffff
-#define DPM_TABLE_418__AcpLevel_6_Frequency__SHIFT 0x0
-#define DPM_TABLE_419__AcpLevel_6_Divider_MASK 0xff
-#define DPM_TABLE_419__AcpLevel_6_Divider__SHIFT 0x0
-#define DPM_TABLE_419__AcpLevel_6_MinPhases_MASK 0xff00
-#define DPM_TABLE_419__AcpLevel_6_MinPhases__SHIFT 0x8
-#define DPM_TABLE_419__AcpLevel_6_MinVoltage_MASK 0xffff0000
-#define DPM_TABLE_419__AcpLevel_6_MinVoltage__SHIFT 0x10
-#define DPM_TABLE_420__AcpLevel_7_Frequency_MASK 0xffffffff
-#define DPM_TABLE_420__AcpLevel_7_Frequency__SHIFT 0x0
-#define DPM_TABLE_421__AcpLevel_7_Divider_MASK 0xff
-#define DPM_TABLE_421__AcpLevel_7_Divider__SHIFT 0x0
-#define DPM_TABLE_421__AcpLevel_7_MinPhases_MASK 0xff00
-#define DPM_TABLE_421__AcpLevel_7_MinPhases__SHIFT 0x8
-#define DPM_TABLE_421__AcpLevel_7_MinVoltage_MASK 0xffff0000
-#define DPM_TABLE_421__AcpLevel_7_MinVoltage__SHIFT 0x10
-#define DPM_TABLE_422__SamuLevel_0_Frequency_MASK 0xffffffff
-#define DPM_TABLE_422__SamuLevel_0_Frequency__SHIFT 0x0
-#define DPM_TABLE_423__SamuLevel_0_Divider_MASK 0xff
-#define DPM_TABLE_423__SamuLevel_0_Divider__SHIFT 0x0
-#define DPM_TABLE_423__SamuLevel_0_MinPhases_MASK 0xff00
-#define DPM_TABLE_423__SamuLevel_0_MinPhases__SHIFT 0x8
-#define DPM_TABLE_423__SamuLevel_0_MinVoltage_MASK 0xffff0000
-#define DPM_TABLE_423__SamuLevel_0_MinVoltage__SHIFT 0x10
-#define DPM_TABLE_424__SamuLevel_1_Frequency_MASK 0xffffffff
-#define DPM_TABLE_424__SamuLevel_1_Frequency__SHIFT 0x0
-#define DPM_TABLE_425__SamuLevel_1_Divider_MASK 0xff
-#define DPM_TABLE_425__SamuLevel_1_Divider__SHIFT 0x0
-#define DPM_TABLE_425__SamuLevel_1_MinPhases_MASK 0xff00
-#define DPM_TABLE_425__SamuLevel_1_MinPhases__SHIFT 0x8
-#define DPM_TABLE_425__SamuLevel_1_MinVoltage_MASK 0xffff0000
-#define DPM_TABLE_425__SamuLevel_1_MinVoltage__SHIFT 0x10
-#define DPM_TABLE_426__SamuLevel_2_Frequency_MASK 0xffffffff
-#define DPM_TABLE_426__SamuLevel_2_Frequency__SHIFT 0x0
-#define DPM_TABLE_427__SamuLevel_2_Divider_MASK 0xff
-#define DPM_TABLE_427__SamuLevel_2_Divider__SHIFT 0x0
-#define DPM_TABLE_427__SamuLevel_2_MinPhases_MASK 0xff00
-#define DPM_TABLE_427__SamuLevel_2_MinPhases__SHIFT 0x8
-#define DPM_TABLE_427__SamuLevel_2_MinVoltage_MASK 0xffff0000
-#define DPM_TABLE_427__SamuLevel_2_MinVoltage__SHIFT 0x10
-#define DPM_TABLE_428__SamuLevel_3_Frequency_MASK 0xffffffff
-#define DPM_TABLE_428__SamuLevel_3_Frequency__SHIFT 0x0
-#define DPM_TABLE_429__SamuLevel_3_Divider_MASK 0xff
-#define DPM_TABLE_429__SamuLevel_3_Divider__SHIFT 0x0
-#define DPM_TABLE_429__SamuLevel_3_MinPhases_MASK 0xff00
-#define DPM_TABLE_429__SamuLevel_3_MinPhases__SHIFT 0x8
-#define DPM_TABLE_429__SamuLevel_3_MinVoltage_MASK 0xffff0000
-#define DPM_TABLE_429__SamuLevel_3_MinVoltage__SHIFT 0x10
-#define DPM_TABLE_430__SamuLevel_4_Frequency_MASK 0xffffffff
-#define DPM_TABLE_430__SamuLevel_4_Frequency__SHIFT 0x0
-#define DPM_TABLE_431__SamuLevel_4_Divider_MASK 0xff
-#define DPM_TABLE_431__SamuLevel_4_Divider__SHIFT 0x0
-#define DPM_TABLE_431__SamuLevel_4_MinPhases_MASK 0xff00
-#define DPM_TABLE_431__SamuLevel_4_MinPhases__SHIFT 0x8
-#define DPM_TABLE_431__SamuLevel_4_MinVoltage_MASK 0xffff0000
-#define DPM_TABLE_431__SamuLevel_4_MinVoltage__SHIFT 0x10
-#define DPM_TABLE_432__SamuLevel_5_Frequency_MASK 0xffffffff
-#define DPM_TABLE_432__SamuLevel_5_Frequency__SHIFT 0x0
-#define DPM_TABLE_433__SamuLevel_5_Divider_MASK 0xff
-#define DPM_TABLE_433__SamuLevel_5_Divider__SHIFT 0x0
-#define DPM_TABLE_433__SamuLevel_5_MinPhases_MASK 0xff00
-#define DPM_TABLE_433__SamuLevel_5_MinPhases__SHIFT 0x8
-#define DPM_TABLE_433__SamuLevel_5_MinVoltage_MASK 0xffff0000
-#define DPM_TABLE_433__SamuLevel_5_MinVoltage__SHIFT 0x10
-#define DPM_TABLE_434__SamuLevel_6_Frequency_MASK 0xffffffff
-#define DPM_TABLE_434__SamuLevel_6_Frequency__SHIFT 0x0
-#define DPM_TABLE_435__SamuLevel_6_Divider_MASK 0xff
-#define DPM_TABLE_435__SamuLevel_6_Divider__SHIFT 0x0
-#define DPM_TABLE_435__SamuLevel_6_MinPhases_MASK 0xff00
-#define DPM_TABLE_435__SamuLevel_6_MinPhases__SHIFT 0x8
-#define DPM_TABLE_435__SamuLevel_6_MinVoltage_MASK 0xffff0000
-#define DPM_TABLE_435__SamuLevel_6_MinVoltage__SHIFT 0x10
-#define DPM_TABLE_436__SamuLevel_7_Frequency_MASK 0xffffffff
-#define DPM_TABLE_436__SamuLevel_7_Frequency__SHIFT 0x0
-#define DPM_TABLE_437__SamuLevel_7_Divider_MASK 0xff
-#define DPM_TABLE_437__SamuLevel_7_Divider__SHIFT 0x0
-#define DPM_TABLE_437__SamuLevel_7_MinPhases_MASK 0xff00
-#define DPM_TABLE_437__SamuLevel_7_MinPhases__SHIFT 0x8
-#define DPM_TABLE_437__SamuLevel_7_MinVoltage_MASK 0xffff0000
-#define DPM_TABLE_437__SamuLevel_7_MinVoltage__SHIFT 0x10
-#define DPM_TABLE_438__Ulv_CcPwrDynRm_MASK 0xffffffff
-#define DPM_TABLE_438__Ulv_CcPwrDynRm__SHIFT 0x0
-#define DPM_TABLE_439__Ulv_CcPwrDynRm1_MASK 0xffffffff
-#define DPM_TABLE_439__Ulv_CcPwrDynRm1__SHIFT 0x0
-#define DPM_TABLE_440__Ulv_VddcPhase_MASK 0xff
-#define DPM_TABLE_440__Ulv_VddcPhase__SHIFT 0x0
-#define DPM_TABLE_440__Ulv_VddcOffsetVid_MASK 0xff00
-#define DPM_TABLE_440__Ulv_VddcOffsetVid__SHIFT 0x8
-#define DPM_TABLE_440__Ulv_VddcOffset_MASK 0xffff0000
-#define DPM_TABLE_440__Ulv_VddcOffset__SHIFT 0x10
-#define DPM_TABLE_441__Ulv_Reserved_MASK 0xffffffff
-#define DPM_TABLE_441__Ulv_Reserved__SHIFT 0x0
-#define DPM_TABLE_442__SclkStepSize_MASK 0xffffffff
-#define DPM_TABLE_442__SclkStepSize__SHIFT 0x0
-#define DPM_TABLE_443__Smio_0_MASK 0xffffffff
-#define DPM_TABLE_443__Smio_0__SHIFT 0x0
-#define DPM_TABLE_444__Smio_1_MASK 0xffffffff
-#define DPM_TABLE_444__Smio_1__SHIFT 0x0
-#define DPM_TABLE_445__Smio_2_MASK 0xffffffff
-#define DPM_TABLE_445__Smio_2__SHIFT 0x0
-#define DPM_TABLE_446__Smio_3_MASK 0xffffffff
-#define DPM_TABLE_446__Smio_3__SHIFT 0x0
-#define DPM_TABLE_447__Smio_4_MASK 0xffffffff
-#define DPM_TABLE_447__Smio_4__SHIFT 0x0
-#define DPM_TABLE_448__Smio_5_MASK 0xffffffff
-#define DPM_TABLE_448__Smio_5__SHIFT 0x0
-#define DPM_TABLE_449__Smio_6_MASK 0xffffffff
-#define DPM_TABLE_449__Smio_6__SHIFT 0x0
-#define DPM_TABLE_450__Smio_7_MASK 0xffffffff
-#define DPM_TABLE_450__Smio_7__SHIFT 0x0
-#define DPM_TABLE_451__Smio_8_MASK 0xffffffff
-#define DPM_TABLE_451__Smio_8__SHIFT 0x0
-#define DPM_TABLE_452__Smio_9_MASK 0xffffffff
-#define DPM_TABLE_452__Smio_9__SHIFT 0x0
-#define DPM_TABLE_453__Smio_10_MASK 0xffffffff
-#define DPM_TABLE_453__Smio_10__SHIFT 0x0
-#define DPM_TABLE_454__Smio_11_MASK 0xffffffff
-#define DPM_TABLE_454__Smio_11__SHIFT 0x0
-#define DPM_TABLE_455__Smio_12_MASK 0xffffffff
-#define DPM_TABLE_455__Smio_12__SHIFT 0x0
-#define DPM_TABLE_456__Smio_13_MASK 0xffffffff
-#define DPM_TABLE_456__Smio_13__SHIFT 0x0
-#define DPM_TABLE_457__Smio_14_MASK 0xffffffff
-#define DPM_TABLE_457__Smio_14__SHIFT 0x0
-#define DPM_TABLE_458__Smio_15_MASK 0xffffffff
-#define DPM_TABLE_458__Smio_15__SHIFT 0x0
-#define DPM_TABLE_459__Smio_16_MASK 0xffffffff
-#define DPM_TABLE_459__Smio_16__SHIFT 0x0
-#define DPM_TABLE_460__Smio_17_MASK 0xffffffff
-#define DPM_TABLE_460__Smio_17__SHIFT 0x0
-#define DPM_TABLE_461__Smio_18_MASK 0xffffffff
-#define DPM_TABLE_461__Smio_18__SHIFT 0x0
-#define DPM_TABLE_462__Smio_19_MASK 0xffffffff
-#define DPM_TABLE_462__Smio_19__SHIFT 0x0
-#define DPM_TABLE_463__Smio_20_MASK 0xffffffff
-#define DPM_TABLE_463__Smio_20__SHIFT 0x0
-#define DPM_TABLE_464__Smio_21_MASK 0xffffffff
-#define DPM_TABLE_464__Smio_21__SHIFT 0x0
-#define DPM_TABLE_465__Smio_22_MASK 0xffffffff
-#define DPM_TABLE_465__Smio_22__SHIFT 0x0
-#define DPM_TABLE_466__Smio_23_MASK 0xffffffff
-#define DPM_TABLE_466__Smio_23__SHIFT 0x0
-#define DPM_TABLE_467__Smio_24_MASK 0xffffffff
-#define DPM_TABLE_467__Smio_24__SHIFT 0x0
-#define DPM_TABLE_468__Smio_25_MASK 0xffffffff
-#define DPM_TABLE_468__Smio_25__SHIFT 0x0
-#define DPM_TABLE_469__Smio_26_MASK 0xffffffff
-#define DPM_TABLE_469__Smio_26__SHIFT 0x0
-#define DPM_TABLE_470__Smio_27_MASK 0xffffffff
-#define DPM_TABLE_470__Smio_27__SHIFT 0x0
-#define DPM_TABLE_471__Smio_28_MASK 0xffffffff
-#define DPM_TABLE_471__Smio_28__SHIFT 0x0
-#define DPM_TABLE_472__Smio_29_MASK 0xffffffff
-#define DPM_TABLE_472__Smio_29__SHIFT 0x0
-#define DPM_TABLE_473__Smio_30_MASK 0xffffffff
-#define DPM_TABLE_473__Smio_30__SHIFT 0x0
-#define DPM_TABLE_474__Smio_31_MASK 0xffffffff
-#define DPM_TABLE_474__Smio_31__SHIFT 0x0
-#define DPM_TABLE_475__SamuBootLevel_MASK 0xff
-#define DPM_TABLE_475__SamuBootLevel__SHIFT 0x0
-#define DPM_TABLE_475__AcpBootLevel_MASK 0xff00
-#define DPM_TABLE_475__AcpBootLevel__SHIFT 0x8
-#define DPM_TABLE_475__VceBootLevel_MASK 0xff0000
-#define DPM_TABLE_475__VceBootLevel__SHIFT 0x10
-#define DPM_TABLE_475__UvdBootLevel_MASK 0xff000000
-#define DPM_TABLE_475__UvdBootLevel__SHIFT 0x18
-#define DPM_TABLE_476__SAMUInterval_MASK 0xff
-#define DPM_TABLE_476__SAMUInterval__SHIFT 0x0
-#define DPM_TABLE_476__ACPInterval_MASK 0xff00
-#define DPM_TABLE_476__ACPInterval__SHIFT 0x8
-#define DPM_TABLE_476__VCEInterval_MASK 0xff0000
-#define DPM_TABLE_476__VCEInterval__SHIFT 0x10
-#define DPM_TABLE_476__UVDInterval_MASK 0xff000000
-#define DPM_TABLE_476__UVDInterval__SHIFT 0x18
-#define DPM_TABLE_477__GraphicsInterval_MASK 0xff
-#define DPM_TABLE_477__GraphicsInterval__SHIFT 0x0
-#define DPM_TABLE_477__GraphicsThermThrottleEnable_MASK 0xff00
-#define DPM_TABLE_477__GraphicsThermThrottleEnable__SHIFT 0x8
-#define DPM_TABLE_477__GraphicsVoltageChangeEnable_MASK 0xff0000
-#define DPM_TABLE_477__GraphicsVoltageChangeEnable__SHIFT 0x10
-#define DPM_TABLE_477__GraphicsBootLevel_MASK 0xff000000
-#define DPM_TABLE_477__GraphicsBootLevel__SHIFT 0x18
-#define DPM_TABLE_478__TemperatureLimitHigh_MASK 0xffff
-#define DPM_TABLE_478__TemperatureLimitHigh__SHIFT 0x0
-#define DPM_TABLE_478__ThermalInterval_MASK 0xff0000
-#define DPM_TABLE_478__ThermalInterval__SHIFT 0x10
-#define DPM_TABLE_478__VoltageInterval_MASK 0xff000000
-#define DPM_TABLE_478__VoltageInterval__SHIFT 0x18
-#define DPM_TABLE_479__MemoryVoltageChangeEnable_MASK 0xff
-#define DPM_TABLE_479__MemoryVoltageChangeEnable__SHIFT 0x0
-#define DPM_TABLE_479__MemoryBootLevel_MASK 0xff00
-#define DPM_TABLE_479__MemoryBootLevel__SHIFT 0x8
-#define DPM_TABLE_479__TemperatureLimitLow_MASK 0xffff0000
-#define DPM_TABLE_479__TemperatureLimitLow__SHIFT 0x10
-#define DPM_TABLE_480__VddcVddciDelta_MASK 0xffff
-#define DPM_TABLE_480__VddcVddciDelta__SHIFT 0x0
-#define DPM_TABLE_480__MemoryThermThrottleEnable_MASK 0xff0000
-#define DPM_TABLE_480__MemoryThermThrottleEnable__SHIFT 0x10
-#define DPM_TABLE_480__MemoryInterval_MASK 0xff000000
-#define DPM_TABLE_480__MemoryInterval__SHIFT 0x18
-#define DPM_TABLE_481__PhaseResponseTime_MASK 0xffff
-#define DPM_TABLE_481__PhaseResponseTime__SHIFT 0x0
-#define DPM_TABLE_481__VoltageResponseTime_MASK 0xffff0000
-#define DPM_TABLE_481__VoltageResponseTime__SHIFT 0x10
-#define DPM_TABLE_482__DTEMode_MASK 0xff
-#define DPM_TABLE_482__DTEMode__SHIFT 0x0
-#define DPM_TABLE_482__DTEInterval_MASK 0xff00
-#define DPM_TABLE_482__DTEInterval__SHIFT 0x8
-#define DPM_TABLE_482__PCIeGenInterval_MASK 0xff0000
-#define DPM_TABLE_482__PCIeGenInterval__SHIFT 0x10
-#define DPM_TABLE_482__PCIeBootLinkLevel_MASK 0xff000000
-#define DPM_TABLE_482__PCIeBootLinkLevel__SHIFT 0x18
-#define DPM_TABLE_483__ThermGpio_MASK 0xff
-#define DPM_TABLE_483__ThermGpio__SHIFT 0x0
-#define DPM_TABLE_483__AcDcGpio_MASK 0xff00
-#define DPM_TABLE_483__AcDcGpio__SHIFT 0x8
-#define DPM_TABLE_483__VRHotGpio_MASK 0xff0000
-#define DPM_TABLE_483__VRHotGpio__SHIFT 0x10
-#define DPM_TABLE_483__SVI2Enable_MASK 0xff000000
-#define DPM_TABLE_483__SVI2Enable__SHIFT 0x18
-#define DPM_TABLE_484__PPM_TemperatureLimit_MASK 0xffff
-#define DPM_TABLE_484__PPM_TemperatureLimit__SHIFT 0x0
-#define DPM_TABLE_484__PPM_PkgPwrLimit_MASK 0xffff0000
-#define DPM_TABLE_484__PPM_PkgPwrLimit__SHIFT 0x10
-#define DPM_TABLE_485__TargetTdp_MASK 0xffff
-#define DPM_TABLE_485__TargetTdp__SHIFT 0x0
-#define DPM_TABLE_485__DefaultTdp_MASK 0xffff0000
-#define DPM_TABLE_485__DefaultTdp__SHIFT 0x10
-#define DPM_TABLE_486__FpsLowThreshold_MASK 0xffff
-#define DPM_TABLE_486__FpsLowThreshold__SHIFT 0x0
-#define DPM_TABLE_486__FpsHighThreshold_MASK 0xffff0000
-#define DPM_TABLE_486__FpsHighThreshold__SHIFT 0x10
-#define DPM_TABLE_487__BAPMTI_R_0_1_0_MASK 0xffff
-#define DPM_TABLE_487__BAPMTI_R_0_1_0__SHIFT 0x0
-#define DPM_TABLE_487__BAPMTI_R_0_0_0_MASK 0xffff0000
-#define DPM_TABLE_487__BAPMTI_R_0_0_0__SHIFT 0x10
-#define DPM_TABLE_488__BAPMTI_R_1_0_0_MASK 0xffff
-#define DPM_TABLE_488__BAPMTI_R_1_0_0__SHIFT 0x0
-#define DPM_TABLE_488__BAPMTI_R_0_2_0_MASK 0xffff0000
-#define DPM_TABLE_488__BAPMTI_R_0_2_0__SHIFT 0x10
-#define DPM_TABLE_489__BAPMTI_R_1_2_0_MASK 0xffff
-#define DPM_TABLE_489__BAPMTI_R_1_2_0__SHIFT 0x0
-#define DPM_TABLE_489__BAPMTI_R_1_1_0_MASK 0xffff0000
-#define DPM_TABLE_489__BAPMTI_R_1_1_0__SHIFT 0x10
-#define DPM_TABLE_490__BAPMTI_R_2_1_0_MASK 0xffff
-#define DPM_TABLE_490__BAPMTI_R_2_1_0__SHIFT 0x0
-#define DPM_TABLE_490__BAPMTI_R_2_0_0_MASK 0xffff0000
-#define DPM_TABLE_490__BAPMTI_R_2_0_0__SHIFT 0x10
-#define DPM_TABLE_491__BAPMTI_R_3_0_0_MASK 0xffff
-#define DPM_TABLE_491__BAPMTI_R_3_0_0__SHIFT 0x0
-#define DPM_TABLE_491__BAPMTI_R_2_2_0_MASK 0xffff0000
-#define DPM_TABLE_491__BAPMTI_R_2_2_0__SHIFT 0x10
-#define DPM_TABLE_492__BAPMTI_R_3_2_0_MASK 0xffff
-#define DPM_TABLE_492__BAPMTI_R_3_2_0__SHIFT 0x0
-#define DPM_TABLE_492__BAPMTI_R_3_1_0_MASK 0xffff0000
-#define DPM_TABLE_492__BAPMTI_R_3_1_0__SHIFT 0x10
-#define DPM_TABLE_493__BAPMTI_R_4_1_0_MASK 0xffff
-#define DPM_TABLE_493__BAPMTI_R_4_1_0__SHIFT 0x0
-#define DPM_TABLE_493__BAPMTI_R_4_0_0_MASK 0xffff0000
-#define DPM_TABLE_493__BAPMTI_R_4_0_0__SHIFT 0x10
-#define DPM_TABLE_494__BAPMTI_RC_0_0_0_MASK 0xffff
-#define DPM_TABLE_494__BAPMTI_RC_0_0_0__SHIFT 0x0
-#define DPM_TABLE_494__BAPMTI_R_4_2_0_MASK 0xffff0000
-#define DPM_TABLE_494__BAPMTI_R_4_2_0__SHIFT 0x10
-#define DPM_TABLE_495__BAPMTI_RC_0_2_0_MASK 0xffff
-#define DPM_TABLE_495__BAPMTI_RC_0_2_0__SHIFT 0x0
-#define DPM_TABLE_495__BAPMTI_RC_0_1_0_MASK 0xffff0000
-#define DPM_TABLE_495__BAPMTI_RC_0_1_0__SHIFT 0x10
-#define DPM_TABLE_496__BAPMTI_RC_1_1_0_MASK 0xffff
-#define DPM_TABLE_496__BAPMTI_RC_1_1_0__SHIFT 0x0
-#define DPM_TABLE_496__BAPMTI_RC_1_0_0_MASK 0xffff0000
-#define DPM_TABLE_496__BAPMTI_RC_1_0_0__SHIFT 0x10
-#define DPM_TABLE_497__BAPMTI_RC_2_0_0_MASK 0xffff
-#define DPM_TABLE_497__BAPMTI_RC_2_0_0__SHIFT 0x0
-#define DPM_TABLE_497__BAPMTI_RC_1_2_0_MASK 0xffff0000
-#define DPM_TABLE_497__BAPMTI_RC_1_2_0__SHIFT 0x10
-#define DPM_TABLE_498__BAPMTI_RC_2_2_0_MASK 0xffff
-#define DPM_TABLE_498__BAPMTI_RC_2_2_0__SHIFT 0x0
-#define DPM_TABLE_498__BAPMTI_RC_2_1_0_MASK 0xffff0000
-#define DPM_TABLE_498__BAPMTI_RC_2_1_0__SHIFT 0x10
-#define DPM_TABLE_499__BAPMTI_RC_3_1_0_MASK 0xffff
-#define DPM_TABLE_499__BAPMTI_RC_3_1_0__SHIFT 0x0
-#define DPM_TABLE_499__BAPMTI_RC_3_0_0_MASK 0xffff0000
-#define DPM_TABLE_499__BAPMTI_RC_3_0_0__SHIFT 0x10
-#define DPM_TABLE_500__BAPMTI_RC_4_0_0_MASK 0xffff
-#define DPM_TABLE_500__BAPMTI_RC_4_0_0__SHIFT 0x0
-#define DPM_TABLE_500__BAPMTI_RC_3_2_0_MASK 0xffff0000
-#define DPM_TABLE_500__BAPMTI_RC_3_2_0__SHIFT 0x10
-#define DPM_TABLE_501__BAPMTI_RC_4_2_0_MASK 0xffff
-#define DPM_TABLE_501__BAPMTI_RC_4_2_0__SHIFT 0x0
-#define DPM_TABLE_501__BAPMTI_RC_4_1_0_MASK 0xffff0000
-#define DPM_TABLE_501__BAPMTI_RC_4_1_0__SHIFT 0x10
-#define DPM_TABLE_502__GpuTjHyst_MASK 0xff
-#define DPM_TABLE_502__GpuTjHyst__SHIFT 0x0
-#define DPM_TABLE_502__GpuTjMax_MASK 0xff00
-#define DPM_TABLE_502__GpuTjMax__SHIFT 0x8
-#define DPM_TABLE_502__DTETjOffset_MASK 0xff0000
-#define DPM_TABLE_502__DTETjOffset__SHIFT 0x10
-#define DPM_TABLE_502__DTEAmbientTempBase_MASK 0xff000000
-#define DPM_TABLE_502__DTEAmbientTempBase__SHIFT 0x18
-#define DPM_TABLE_503__BootVddci_MASK 0xffff
-#define DPM_TABLE_503__BootVddci__SHIFT 0x0
-#define DPM_TABLE_503__BootVddc_MASK 0xffff0000
-#define DPM_TABLE_503__BootVddc__SHIFT 0x10
-#define DPM_TABLE_504__padding_MASK 0xff
-#define DPM_TABLE_504__padding__SHIFT 0x0
-#define DPM_TABLE_504__PccGpio_MASK 0xff00
-#define DPM_TABLE_504__PccGpio__SHIFT 0x8
-#define DPM_TABLE_504__BootMVdd_MASK 0xffff0000
-#define DPM_TABLE_504__BootMVdd__SHIFT 0x10
-#define DPM_TABLE_505__BAPM_TEMP_GRADIENT_MASK 0xffffffff
-#define DPM_TABLE_505__BAPM_TEMP_GRADIENT__SHIFT 0x0
-#define DPM_TABLE_506__LowSclkInterruptThreshold_MASK 0xffffffff
-#define DPM_TABLE_506__LowSclkInterruptThreshold__SHIFT 0x0
-#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x1
-#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0
-#define FIRMWARE_FLAGS__RESERVED_MASK 0xfffffe
-#define FIRMWARE_FLAGS__RESERVED__SHIFT 0x1
-#define FIRMWARE_FLAGS__TEST_COUNT_MASK 0xff000000
-#define FIRMWARE_FLAGS__TEST_COUNT__SHIFT 0x18
-#define TDC_STATUS__VDD_Boost_MASK 0xff
-#define TDC_STATUS__VDD_Boost__SHIFT 0x0
-#define TDC_STATUS__VDD_Throttle_MASK 0xff00
-#define TDC_STATUS__VDD_Throttle__SHIFT 0x8
-#define TDC_STATUS__VDDC_Boost_MASK 0xff0000
-#define TDC_STATUS__VDDC_Boost__SHIFT 0x10
-#define TDC_STATUS__VDDC_Throttle_MASK 0xff000000
-#define TDC_STATUS__VDDC_Throttle__SHIFT 0x18
-#define TDC_MV_AVERAGE__IDD_MASK 0xffff
-#define TDC_MV_AVERAGE__IDD__SHIFT 0x0
-#define TDC_MV_AVERAGE__IDDC_MASK 0xffff0000
-#define TDC_MV_AVERAGE__IDDC__SHIFT 0x10
-#define TDC_VRM_LIMIT__IDD_MASK 0xffff
-#define TDC_VRM_LIMIT__IDD__SHIFT 0x0
-#define TDC_VRM_LIMIT__IDDC_MASK 0xffff0000
-#define TDC_VRM_LIMIT__IDDC__SHIFT 0x10
-#define FEATURE_STATUS__SCLK_DPM_ON_MASK 0x1
-#define FEATURE_STATUS__SCLK_DPM_ON__SHIFT 0x0
-#define FEATURE_STATUS__MCLK_DPM_ON_MASK 0x2
-#define FEATURE_STATUS__MCLK_DPM_ON__SHIFT 0x1
-#define FEATURE_STATUS__LCLK_DPM_ON_MASK 0x4
-#define FEATURE_STATUS__LCLK_DPM_ON__SHIFT 0x2
-#define FEATURE_STATUS__UVD_DPM_ON_MASK 0x8
-#define FEATURE_STATUS__UVD_DPM_ON__SHIFT 0x3
-#define FEATURE_STATUS__VCE_DPM_ON_MASK 0x10
-#define FEATURE_STATUS__VCE_DPM_ON__SHIFT 0x4
-#define FEATURE_STATUS__ACP_DPM_ON_MASK 0x20
-#define FEATURE_STATUS__ACP_DPM_ON__SHIFT 0x5
-#define FEATURE_STATUS__SAMU_DPM_ON_MASK 0x40
-#define FEATURE_STATUS__SAMU_DPM_ON__SHIFT 0x6
-#define FEATURE_STATUS__PCIE_DPM_ON_MASK 0x80
-#define FEATURE_STATUS__PCIE_DPM_ON__SHIFT 0x7
-#define FEATURE_STATUS__BAPM_ON_MASK 0x100
-#define FEATURE_STATUS__BAPM_ON__SHIFT 0x8
-#define FEATURE_STATUS__LPMX_ON_MASK 0x200
-#define FEATURE_STATUS__LPMX_ON__SHIFT 0x9
-#define FEATURE_STATUS__NBDPM_ON_MASK 0x400
-#define FEATURE_STATUS__NBDPM_ON__SHIFT 0xa
-#define FEATURE_STATUS__LHTC_ON_MASK 0x800
-#define FEATURE_STATUS__LHTC_ON__SHIFT 0xb
-#define FEATURE_STATUS__VPC_ON_MASK 0x1000
-#define FEATURE_STATUS__VPC_ON__SHIFT 0xc
-#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON_MASK 0x2000
-#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON__SHIFT 0xd
-#define FEATURE_STATUS__TDC_LIMIT_ON_MASK 0x4000
-#define FEATURE_STATUS__TDC_LIMIT_ON__SHIFT 0xe
-#define FEATURE_STATUS__GPU_CAC_ON_MASK 0x8000
-#define FEATURE_STATUS__GPU_CAC_ON__SHIFT 0xf
-#define FEATURE_STATUS__AVS_ON_MASK 0x10000
-#define FEATURE_STATUS__AVS_ON__SHIFT 0x10
-#define FEATURE_STATUS__SPMI_ON_MASK 0x20000
-#define FEATURE_STATUS__SPMI_ON__SHIFT 0x11
-#define FEATURE_STATUS__SCLK_DPM_FORCED_MASK 0x40000
-#define FEATURE_STATUS__SCLK_DPM_FORCED__SHIFT 0x12
-#define FEATURE_STATUS__MCLK_DPM_FORCED_MASK 0x80000
-#define FEATURE_STATUS__MCLK_DPM_FORCED__SHIFT 0x13
-#define FEATURE_STATUS__LCLK_DPM_FORCED_MASK 0x100000
-#define FEATURE_STATUS__LCLK_DPM_FORCED__SHIFT 0x14
-#define FEATURE_STATUS__PCIE_DPM_FORCED_MASK 0x200000
-#define FEATURE_STATUS__PCIE_DPM_FORCED__SHIFT 0x15
-#define FEATURE_STATUS__RESERVED_MASK 0xffc00000
-#define FEATURE_STATUS__RESERVED__SHIFT 0x16
-#define ENTITY_TEMPERATURES_1__GPU_MASK 0xffffffff
-#define ENTITY_TEMPERATURES_1__GPU__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_13__entries_0_4_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_13__entries_0_4_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_14__entries_0_4_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_14__entries_0_4_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_16__entries_0_5_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_16__entries_0_5_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_17__entries_0_5_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_17__entries_0_5_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_19__entries_1_0_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_19__entries_1_0_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_20__entries_1_0_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_20__entries_1_0_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_22__entries_1_1_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_22__entries_1_1_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_23__entries_1_1_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_23__entries_1_1_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_25__entries_1_2_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_25__entries_1_2_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_26__entries_1_2_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_26__entries_1_2_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_28__entries_1_3_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_28__entries_1_3_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_29__entries_1_3_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_29__entries_1_3_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_31__entries_1_4_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_31__entries_1_4_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_32__entries_1_4_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_32__entries_1_4_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_34__entries_1_5_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_34__entries_1_5_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_35__entries_1_5_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_35__entries_1_5_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_37__entries_2_0_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_37__entries_2_0_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_38__entries_2_0_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_38__entries_2_0_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_40__entries_2_1_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_40__entries_2_1_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_41__entries_2_1_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_41__entries_2_1_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_43__entries_2_2_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_43__entries_2_2_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_44__entries_2_2_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_44__entries_2_2_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_46__entries_2_3_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_46__entries_2_3_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_47__entries_2_3_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_47__entries_2_3_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_49__entries_2_4_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_49__entries_2_4_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_50__entries_2_4_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_50__entries_2_4_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_52__entries_2_5_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_52__entries_2_5_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_53__entries_2_5_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_53__entries_2_5_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_55__entries_3_0_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_55__entries_3_0_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_56__entries_3_0_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_56__entries_3_0_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_58__entries_3_1_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_58__entries_3_1_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_59__entries_3_1_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_59__entries_3_1_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_61__entries_3_2_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_61__entries_3_2_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_62__entries_3_2_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_62__entries_3_2_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_64__entries_3_3_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_64__entries_3_3_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_65__entries_3_3_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_65__entries_3_3_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_67__entries_3_4_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_67__entries_3_4_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_68__entries_3_4_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_68__entries_3_4_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_70__entries_3_5_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_70__entries_3_5_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_71__entries_3_5_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_71__entries_3_5_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_73__entries_4_0_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_73__entries_4_0_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_74__entries_4_0_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_74__entries_4_0_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_76__entries_4_1_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_76__entries_4_1_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_77__entries_4_1_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_77__entries_4_1_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_79__entries_4_2_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_79__entries_4_2_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_80__entries_4_2_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_80__entries_4_2_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_82__entries_4_3_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_82__entries_4_3_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_83__entries_4_3_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_83__entries_4_3_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_85__entries_4_4_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_85__entries_4_4_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_86__entries_4_4_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_86__entries_4_4_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_88__entries_4_5_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_88__entries_4_5_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_89__entries_4_5_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_89__entries_4_5_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_91__entries_5_0_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_91__entries_5_0_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_92__entries_5_0_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_92__entries_5_0_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_94__entries_5_1_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_94__entries_5_1_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_95__entries_5_1_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_95__entries_5_1_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_97__entries_5_2_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_97__entries_5_2_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_98__entries_5_2_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_98__entries_5_2_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_100__entries_5_3_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_100__entries_5_3_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_101__entries_5_3_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_101__entries_5_3_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_103__entries_5_4_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_103__entries_5_4_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_104__entries_5_4_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_104__entries_5_4_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_106__entries_5_5_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_106__entries_5_5_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_107__entries_5_5_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_107__entries_5_5_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_109__entries_6_0_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_109__entries_6_0_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_110__entries_6_0_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_110__entries_6_0_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_112__entries_6_1_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_112__entries_6_1_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_113__entries_6_1_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_113__entries_6_1_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_115__entries_6_2_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_115__entries_6_2_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_116__entries_6_2_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_116__entries_6_2_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_118__entries_6_3_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_118__entries_6_3_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_119__entries_6_3_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_119__entries_6_3_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_121__entries_6_4_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_121__entries_6_4_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_122__entries_6_4_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_122__entries_6_4_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_124__entries_6_5_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_124__entries_6_5_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_125__entries_6_5_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_125__entries_6_5_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_127__entries_7_0_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_127__entries_7_0_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_128__entries_7_0_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_128__entries_7_0_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_130__entries_7_1_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_130__entries_7_1_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_131__entries_7_1_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_131__entries_7_1_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_133__entries_7_2_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_133__entries_7_2_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_134__entries_7_2_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_134__entries_7_2_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_136__entries_7_3_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_136__entries_7_3_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_137__entries_7_3_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_137__entries_7_3_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_139__entries_7_4_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_139__entries_7_4_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_140__entries_7_4_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_140__entries_7_4_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_McArbBurstTime__SHIFT 0x18
-#define MCARB_DRAM_TIMING_TABLE_142__entries_7_5_McArbDramTiming_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_142__entries_7_5_McArbDramTiming__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_143__entries_7_5_McArbDramTiming2_MASK 0xffffffff
-#define MCARB_DRAM_TIMING_TABLE_143__entries_7_5_McArbDramTiming2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_2_MASK 0xff
-#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_2__SHIFT 0x0
-#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_1_MASK 0xff00
-#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_1__SHIFT 0x8
-#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_0_MASK 0xff0000
-#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_0__SHIFT 0x10
-#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_McArbBurstTime_MASK 0xff000000
-#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_McArbBurstTime__SHIFT 0x18
-#define MC_REGISTERS_TABLE_1__reserved_2_MASK 0xff
-#define MC_REGISTERS_TABLE_1__reserved_2__SHIFT 0x0
-#define MC_REGISTERS_TABLE_1__reserved_1_MASK 0xff00
-#define MC_REGISTERS_TABLE_1__reserved_1__SHIFT 0x8
-#define MC_REGISTERS_TABLE_1__reserved_0_MASK 0xff0000
-#define MC_REGISTERS_TABLE_1__reserved_0__SHIFT 0x10
-#define MC_REGISTERS_TABLE_1__last_MASK 0xff000000
-#define MC_REGISTERS_TABLE_1__last__SHIFT 0x18
-#define MC_REGISTERS_TABLE_2__address_0_s1_MASK 0xffff
-#define MC_REGISTERS_TABLE_2__address_0_s1__SHIFT 0x0
-#define MC_REGISTERS_TABLE_2__address_0_s0_MASK 0xffff0000
-#define MC_REGISTERS_TABLE_2__address_0_s0__SHIFT 0x10
-#define MC_REGISTERS_TABLE_3__address_1_s1_MASK 0xffff
-#define MC_REGISTERS_TABLE_3__address_1_s1__SHIFT 0x0
-#define MC_REGISTERS_TABLE_3__address_1_s0_MASK 0xffff0000
-#define MC_REGISTERS_TABLE_3__address_1_s0__SHIFT 0x10
-#define MC_REGISTERS_TABLE_4__address_2_s1_MASK 0xffff
-#define MC_REGISTERS_TABLE_4__address_2_s1__SHIFT 0x0
-#define MC_REGISTERS_TABLE_4__address_2_s0_MASK 0xffff0000
-#define MC_REGISTERS_TABLE_4__address_2_s0__SHIFT 0x10
-#define MC_REGISTERS_TABLE_5__address_3_s1_MASK 0xffff
-#define MC_REGISTERS_TABLE_5__address_3_s1__SHIFT 0x0
-#define MC_REGISTERS_TABLE_5__address_3_s0_MASK 0xffff0000
-#define MC_REGISTERS_TABLE_5__address_3_s0__SHIFT 0x10
-#define MC_REGISTERS_TABLE_6__address_4_s1_MASK 0xffff
-#define MC_REGISTERS_TABLE_6__address_4_s1__SHIFT 0x0
-#define MC_REGISTERS_TABLE_6__address_4_s0_MASK 0xffff0000
-#define MC_REGISTERS_TABLE_6__address_4_s0__SHIFT 0x10
-#define MC_REGISTERS_TABLE_7__address_5_s1_MASK 0xffff
-#define MC_REGISTERS_TABLE_7__address_5_s1__SHIFT 0x0
-#define MC_REGISTERS_TABLE_7__address_5_s0_MASK 0xffff0000
-#define MC_REGISTERS_TABLE_7__address_5_s0__SHIFT 0x10
-#define MC_REGISTERS_TABLE_8__address_6_s1_MASK 0xffff
-#define MC_REGISTERS_TABLE_8__address_6_s1__SHIFT 0x0
-#define MC_REGISTERS_TABLE_8__address_6_s0_MASK 0xffff0000
-#define MC_REGISTERS_TABLE_8__address_6_s0__SHIFT 0x10
-#define MC_REGISTERS_TABLE_9__address_7_s1_MASK 0xffff
-#define MC_REGISTERS_TABLE_9__address_7_s1__SHIFT 0x0
-#define MC_REGISTERS_TABLE_9__address_7_s0_MASK 0xffff0000
-#define MC_REGISTERS_TABLE_9__address_7_s0__SHIFT 0x10
-#define MC_REGISTERS_TABLE_10__address_8_s1_MASK 0xffff
-#define MC_REGISTERS_TABLE_10__address_8_s1__SHIFT 0x0
-#define MC_REGISTERS_TABLE_10__address_8_s0_MASK 0xffff0000
-#define MC_REGISTERS_TABLE_10__address_8_s0__SHIFT 0x10
-#define MC_REGISTERS_TABLE_11__address_9_s1_MASK 0xffff
-#define MC_REGISTERS_TABLE_11__address_9_s1__SHIFT 0x0
-#define MC_REGISTERS_TABLE_11__address_9_s0_MASK 0xffff0000
-#define MC_REGISTERS_TABLE_11__address_9_s0__SHIFT 0x10
-#define MC_REGISTERS_TABLE_12__address_10_s1_MASK 0xffff
-#define MC_REGISTERS_TABLE_12__address_10_s1__SHIFT 0x0
-#define MC_REGISTERS_TABLE_12__address_10_s0_MASK 0xffff0000
-#define MC_REGISTERS_TABLE_12__address_10_s0__SHIFT 0x10
-#define MC_REGISTERS_TABLE_13__address_11_s1_MASK 0xffff
-#define MC_REGISTERS_TABLE_13__address_11_s1__SHIFT 0x0
-#define MC_REGISTERS_TABLE_13__address_11_s0_MASK 0xffff0000
-#define MC_REGISTERS_TABLE_13__address_11_s0__SHIFT 0x10
-#define MC_REGISTERS_TABLE_14__address_12_s1_MASK 0xffff
-#define MC_REGISTERS_TABLE_14__address_12_s1__SHIFT 0x0
-#define MC_REGISTERS_TABLE_14__address_12_s0_MASK 0xffff0000
-#define MC_REGISTERS_TABLE_14__address_12_s0__SHIFT 0x10
-#define MC_REGISTERS_TABLE_15__address_13_s1_MASK 0xffff
-#define MC_REGISTERS_TABLE_15__address_13_s1__SHIFT 0x0
-#define MC_REGISTERS_TABLE_15__address_13_s0_MASK 0xffff0000
-#define MC_REGISTERS_TABLE_15__address_13_s0__SHIFT 0x10
-#define MC_REGISTERS_TABLE_16__address_14_s1_MASK 0xffff
-#define MC_REGISTERS_TABLE_16__address_14_s1__SHIFT 0x0
-#define MC_REGISTERS_TABLE_16__address_14_s0_MASK 0xffff0000
-#define MC_REGISTERS_TABLE_16__address_14_s0__SHIFT 0x10
-#define MC_REGISTERS_TABLE_17__address_15_s1_MASK 0xffff
-#define MC_REGISTERS_TABLE_17__address_15_s1__SHIFT 0x0
-#define MC_REGISTERS_TABLE_17__address_15_s0_MASK 0xffff0000
-#define MC_REGISTERS_TABLE_17__address_15_s0__SHIFT 0x10
-#define MC_REGISTERS_TABLE_18__data_0_value_0_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_18__data_0_value_0__SHIFT 0x0
-#define MC_REGISTERS_TABLE_19__data_0_value_1_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_19__data_0_value_1__SHIFT 0x0
-#define MC_REGISTERS_TABLE_20__data_0_value_2_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_20__data_0_value_2__SHIFT 0x0
-#define MC_REGISTERS_TABLE_21__data_0_value_3_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_21__data_0_value_3__SHIFT 0x0
-#define MC_REGISTERS_TABLE_22__data_0_value_4_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_22__data_0_value_4__SHIFT 0x0
-#define MC_REGISTERS_TABLE_23__data_0_value_5_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_23__data_0_value_5__SHIFT 0x0
-#define MC_REGISTERS_TABLE_24__data_0_value_6_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_24__data_0_value_6__SHIFT 0x0
-#define MC_REGISTERS_TABLE_25__data_0_value_7_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_25__data_0_value_7__SHIFT 0x0
-#define MC_REGISTERS_TABLE_26__data_0_value_8_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_26__data_0_value_8__SHIFT 0x0
-#define MC_REGISTERS_TABLE_27__data_0_value_9_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_27__data_0_value_9__SHIFT 0x0
-#define MC_REGISTERS_TABLE_28__data_0_value_10_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_28__data_0_value_10__SHIFT 0x0
-#define MC_REGISTERS_TABLE_29__data_0_value_11_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_29__data_0_value_11__SHIFT 0x0
-#define MC_REGISTERS_TABLE_30__data_0_value_12_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_30__data_0_value_12__SHIFT 0x0
-#define MC_REGISTERS_TABLE_31__data_0_value_13_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_31__data_0_value_13__SHIFT 0x0
-#define MC_REGISTERS_TABLE_32__data_0_value_14_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_32__data_0_value_14__SHIFT 0x0
-#define MC_REGISTERS_TABLE_33__data_0_value_15_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_33__data_0_value_15__SHIFT 0x0
-#define MC_REGISTERS_TABLE_34__data_1_value_0_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_34__data_1_value_0__SHIFT 0x0
-#define MC_REGISTERS_TABLE_35__data_1_value_1_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_35__data_1_value_1__SHIFT 0x0
-#define MC_REGISTERS_TABLE_36__data_1_value_2_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_36__data_1_value_2__SHIFT 0x0
-#define MC_REGISTERS_TABLE_37__data_1_value_3_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_37__data_1_value_3__SHIFT 0x0
-#define MC_REGISTERS_TABLE_38__data_1_value_4_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_38__data_1_value_4__SHIFT 0x0
-#define MC_REGISTERS_TABLE_39__data_1_value_5_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_39__data_1_value_5__SHIFT 0x0
-#define MC_REGISTERS_TABLE_40__data_1_value_6_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_40__data_1_value_6__SHIFT 0x0
-#define MC_REGISTERS_TABLE_41__data_1_value_7_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_41__data_1_value_7__SHIFT 0x0
-#define MC_REGISTERS_TABLE_42__data_1_value_8_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_42__data_1_value_8__SHIFT 0x0
-#define MC_REGISTERS_TABLE_43__data_1_value_9_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_43__data_1_value_9__SHIFT 0x0
-#define MC_REGISTERS_TABLE_44__data_1_value_10_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_44__data_1_value_10__SHIFT 0x0
-#define MC_REGISTERS_TABLE_45__data_1_value_11_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_45__data_1_value_11__SHIFT 0x0
-#define MC_REGISTERS_TABLE_46__data_1_value_12_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_46__data_1_value_12__SHIFT 0x0
-#define MC_REGISTERS_TABLE_47__data_1_value_13_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_47__data_1_value_13__SHIFT 0x0
-#define MC_REGISTERS_TABLE_48__data_1_value_14_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_48__data_1_value_14__SHIFT 0x0
-#define MC_REGISTERS_TABLE_49__data_1_value_15_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_49__data_1_value_15__SHIFT 0x0
-#define MC_REGISTERS_TABLE_50__data_2_value_0_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_50__data_2_value_0__SHIFT 0x0
-#define MC_REGISTERS_TABLE_51__data_2_value_1_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_51__data_2_value_1__SHIFT 0x0
-#define MC_REGISTERS_TABLE_52__data_2_value_2_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_52__data_2_value_2__SHIFT 0x0
-#define MC_REGISTERS_TABLE_53__data_2_value_3_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_53__data_2_value_3__SHIFT 0x0
-#define MC_REGISTERS_TABLE_54__data_2_value_4_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_54__data_2_value_4__SHIFT 0x0
-#define MC_REGISTERS_TABLE_55__data_2_value_5_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_55__data_2_value_5__SHIFT 0x0
-#define MC_REGISTERS_TABLE_56__data_2_value_6_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_56__data_2_value_6__SHIFT 0x0
-#define MC_REGISTERS_TABLE_57__data_2_value_7_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_57__data_2_value_7__SHIFT 0x0
-#define MC_REGISTERS_TABLE_58__data_2_value_8_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_58__data_2_value_8__SHIFT 0x0
-#define MC_REGISTERS_TABLE_59__data_2_value_9_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_59__data_2_value_9__SHIFT 0x0
-#define MC_REGISTERS_TABLE_60__data_2_value_10_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_60__data_2_value_10__SHIFT 0x0
-#define MC_REGISTERS_TABLE_61__data_2_value_11_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_61__data_2_value_11__SHIFT 0x0
-#define MC_REGISTERS_TABLE_62__data_2_value_12_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_62__data_2_value_12__SHIFT 0x0
-#define MC_REGISTERS_TABLE_63__data_2_value_13_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_63__data_2_value_13__SHIFT 0x0
-#define MC_REGISTERS_TABLE_64__data_2_value_14_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_64__data_2_value_14__SHIFT 0x0
-#define MC_REGISTERS_TABLE_65__data_2_value_15_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_65__data_2_value_15__SHIFT 0x0
-#define MC_REGISTERS_TABLE_66__data_3_value_0_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_66__data_3_value_0__SHIFT 0x0
-#define MC_REGISTERS_TABLE_67__data_3_value_1_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_67__data_3_value_1__SHIFT 0x0
-#define MC_REGISTERS_TABLE_68__data_3_value_2_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_68__data_3_value_2__SHIFT 0x0
-#define MC_REGISTERS_TABLE_69__data_3_value_3_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_69__data_3_value_3__SHIFT 0x0
-#define MC_REGISTERS_TABLE_70__data_3_value_4_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_70__data_3_value_4__SHIFT 0x0
-#define MC_REGISTERS_TABLE_71__data_3_value_5_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_71__data_3_value_5__SHIFT 0x0
-#define MC_REGISTERS_TABLE_72__data_3_value_6_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_72__data_3_value_6__SHIFT 0x0
-#define MC_REGISTERS_TABLE_73__data_3_value_7_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_73__data_3_value_7__SHIFT 0x0
-#define MC_REGISTERS_TABLE_74__data_3_value_8_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_74__data_3_value_8__SHIFT 0x0
-#define MC_REGISTERS_TABLE_75__data_3_value_9_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_75__data_3_value_9__SHIFT 0x0
-#define MC_REGISTERS_TABLE_76__data_3_value_10_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_76__data_3_value_10__SHIFT 0x0
-#define MC_REGISTERS_TABLE_77__data_3_value_11_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_77__data_3_value_11__SHIFT 0x0
-#define MC_REGISTERS_TABLE_78__data_3_value_12_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_78__data_3_value_12__SHIFT 0x0
-#define MC_REGISTERS_TABLE_79__data_3_value_13_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_79__data_3_value_13__SHIFT 0x0
-#define MC_REGISTERS_TABLE_80__data_3_value_14_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_80__data_3_value_14__SHIFT 0x0
-#define MC_REGISTERS_TABLE_81__data_3_value_15_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_81__data_3_value_15__SHIFT 0x0
-#define MC_REGISTERS_TABLE_82__data_4_value_0_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_82__data_4_value_0__SHIFT 0x0
-#define MC_REGISTERS_TABLE_83__data_4_value_1_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_83__data_4_value_1__SHIFT 0x0
-#define MC_REGISTERS_TABLE_84__data_4_value_2_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_84__data_4_value_2__SHIFT 0x0
-#define MC_REGISTERS_TABLE_85__data_4_value_3_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_85__data_4_value_3__SHIFT 0x0
-#define MC_REGISTERS_TABLE_86__data_4_value_4_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_86__data_4_value_4__SHIFT 0x0
-#define MC_REGISTERS_TABLE_87__data_4_value_5_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_87__data_4_value_5__SHIFT 0x0
-#define MC_REGISTERS_TABLE_88__data_4_value_6_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_88__data_4_value_6__SHIFT 0x0
-#define MC_REGISTERS_TABLE_89__data_4_value_7_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_89__data_4_value_7__SHIFT 0x0
-#define MC_REGISTERS_TABLE_90__data_4_value_8_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_90__data_4_value_8__SHIFT 0x0
-#define MC_REGISTERS_TABLE_91__data_4_value_9_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_91__data_4_value_9__SHIFT 0x0
-#define MC_REGISTERS_TABLE_92__data_4_value_10_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_92__data_4_value_10__SHIFT 0x0
-#define MC_REGISTERS_TABLE_93__data_4_value_11_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_93__data_4_value_11__SHIFT 0x0
-#define MC_REGISTERS_TABLE_94__data_4_value_12_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_94__data_4_value_12__SHIFT 0x0
-#define MC_REGISTERS_TABLE_95__data_4_value_13_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_95__data_4_value_13__SHIFT 0x0
-#define MC_REGISTERS_TABLE_96__data_4_value_14_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_96__data_4_value_14__SHIFT 0x0
-#define MC_REGISTERS_TABLE_97__data_4_value_15_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_97__data_4_value_15__SHIFT 0x0
-#define MC_REGISTERS_TABLE_98__data_5_value_0_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_98__data_5_value_0__SHIFT 0x0
-#define MC_REGISTERS_TABLE_99__data_5_value_1_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_99__data_5_value_1__SHIFT 0x0
-#define MC_REGISTERS_TABLE_100__data_5_value_2_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_100__data_5_value_2__SHIFT 0x0
-#define MC_REGISTERS_TABLE_101__data_5_value_3_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_101__data_5_value_3__SHIFT 0x0
-#define MC_REGISTERS_TABLE_102__data_5_value_4_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_102__data_5_value_4__SHIFT 0x0
-#define MC_REGISTERS_TABLE_103__data_5_value_5_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_103__data_5_value_5__SHIFT 0x0
-#define MC_REGISTERS_TABLE_104__data_5_value_6_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_104__data_5_value_6__SHIFT 0x0
-#define MC_REGISTERS_TABLE_105__data_5_value_7_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_105__data_5_value_7__SHIFT 0x0
-#define MC_REGISTERS_TABLE_106__data_5_value_8_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_106__data_5_value_8__SHIFT 0x0
-#define MC_REGISTERS_TABLE_107__data_5_value_9_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_107__data_5_value_9__SHIFT 0x0
-#define MC_REGISTERS_TABLE_108__data_5_value_10_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_108__data_5_value_10__SHIFT 0x0
-#define MC_REGISTERS_TABLE_109__data_5_value_11_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_109__data_5_value_11__SHIFT 0x0
-#define MC_REGISTERS_TABLE_110__data_5_value_12_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_110__data_5_value_12__SHIFT 0x0
-#define MC_REGISTERS_TABLE_111__data_5_value_13_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_111__data_5_value_13__SHIFT 0x0
-#define MC_REGISTERS_TABLE_112__data_5_value_14_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_112__data_5_value_14__SHIFT 0x0
-#define MC_REGISTERS_TABLE_113__data_5_value_15_MASK 0xffffffff
-#define MC_REGISTERS_TABLE_113__data_5_value_15__SHIFT 0x0
-#define FAN_TABLE_1__TempMin_MASK 0xffff
-#define FAN_TABLE_1__TempMin__SHIFT 0x0
-#define FAN_TABLE_1__FdoMode_MASK 0xffff0000
-#define FAN_TABLE_1__FdoMode__SHIFT 0x10
-#define FAN_TABLE_2__TempMax_MASK 0xffff
-#define FAN_TABLE_2__TempMax__SHIFT 0x0
-#define FAN_TABLE_2__TempMed_MASK 0xffff0000
-#define FAN_TABLE_2__TempMed__SHIFT 0x10
-#define FAN_TABLE_3__Slope2_MASK 0xffff
-#define FAN_TABLE_3__Slope2__SHIFT 0x0
-#define FAN_TABLE_3__Slope1_MASK 0xffff0000
-#define FAN_TABLE_3__Slope1__SHIFT 0x10
-#define FAN_TABLE_4__HystUp_MASK 0xffff
-#define FAN_TABLE_4__HystUp__SHIFT 0x0
-#define FAN_TABLE_4__FdoMin_MASK 0xffff0000
-#define FAN_TABLE_4__FdoMin__SHIFT 0x10
-#define FAN_TABLE_5__HystSlope_MASK 0xffff
-#define FAN_TABLE_5__HystSlope__SHIFT 0x0
-#define FAN_TABLE_5__HystDown_MASK 0xffff0000
-#define FAN_TABLE_5__HystDown__SHIFT 0x10
-#define FAN_TABLE_6__TempCurr_MASK 0xffff
-#define FAN_TABLE_6__TempCurr__SHIFT 0x0
-#define FAN_TABLE_6__TempRespLim_MASK 0xffff0000
-#define FAN_TABLE_6__TempRespLim__SHIFT 0x10
-#define FAN_TABLE_7__PwmCurr_MASK 0xffff
-#define FAN_TABLE_7__PwmCurr__SHIFT 0x0
-#define FAN_TABLE_7__SlopeCurr_MASK 0xffff0000
-#define FAN_TABLE_7__SlopeCurr__SHIFT 0x10
-#define FAN_TABLE_8__RefreshPeriod_MASK 0xffffffff
-#define FAN_TABLE_8__RefreshPeriod__SHIFT 0x0
-#define FAN_TABLE_9__Padding_MASK 0xff
-#define FAN_TABLE_9__Padding__SHIFT 0x0
-#define FAN_TABLE_9__TempSrc_MASK 0xff00
-#define FAN_TABLE_9__TempSrc__SHIFT 0x8
-#define FAN_TABLE_9__FdoMax_MASK 0xffff0000
-#define FAN_TABLE_9__FdoMax__SHIFT 0x10
-#define SOFT_REGISTERS_TABLE_1__RefClockFrequency_MASK 0xffffffff
-#define SOFT_REGISTERS_TABLE_1__RefClockFrequency__SHIFT 0x0
-#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod_MASK 0xffffffff
-#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod__SHIFT 0x0
-#define SOFT_REGISTERS_TABLE_3__FeatureEnables_MASK 0xffffffff
-#define SOFT_REGISTERS_TABLE_3__FeatureEnables__SHIFT 0x0
-#define SOFT_REGISTERS_TABLE_4__PreVBlankGap_MASK 0xffffffff
-#define SOFT_REGISTERS_TABLE_4__PreVBlankGap__SHIFT 0x0
-#define SOFT_REGISTERS_TABLE_5__VBlankTimeout_MASK 0xffffffff
-#define SOFT_REGISTERS_TABLE_5__VBlankTimeout__SHIFT 0x0
-#define SOFT_REGISTERS_TABLE_6__TrainTimeGap_MASK 0xffffffff
-#define SOFT_REGISTERS_TABLE_6__TrainTimeGap__SHIFT 0x0
-#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime_MASK 0xffffffff
-#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime__SHIFT 0x0
-#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime_MASK 0xffffffff
-#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime__SHIFT 0x0
-#define SOFT_REGISTERS_TABLE_9__AcpiDelay_MASK 0xffffffff
-#define SOFT_REGISTERS_TABLE_9__AcpiDelay__SHIFT 0x0
-#define SOFT_REGISTERS_TABLE_10__G5TrainTime_MASK 0xffffffff
-#define SOFT_REGISTERS_TABLE_10__G5TrainTime__SHIFT 0x0
-#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron_MASK 0xffffffff
-#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron__SHIFT 0x0
-#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout_MASK 0xffffffff
-#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout__SHIFT 0x0
-#define SOFT_REGISTERS_TABLE_13__HandshakeDisables_MASK 0xffffffff
-#define SOFT_REGISTERS_TABLE_13__HandshakeDisables__SHIFT 0x0
-#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config_MASK 0xff
-#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config__SHIFT 0x0
-#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config_MASK 0xff00
-#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config__SHIFT 0x8
-#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config_MASK 0xff0000
-#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config__SHIFT 0x10
-#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config_MASK 0xff000000
-#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config__SHIFT 0x18
-#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config_MASK 0xff
-#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config__SHIFT 0x0
-#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config_MASK 0xff00
-#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config__SHIFT 0x8
-#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config_MASK 0xff0000
-#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config__SHIFT 0x10
-#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config_MASK 0xff000000
-#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config__SHIFT 0x18
-#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity_MASK 0xffffffff
-#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity__SHIFT 0x0
-#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity_MASK 0xffffffff
-#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity__SHIFT 0x0
-#define SOFT_REGISTERS_TABLE_18__AverageGioActivity_MASK 0xffffffff
-#define SOFT_REGISTERS_TABLE_18__AverageGioActivity__SHIFT 0x0
-#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels_MASK 0xff
-#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels__SHIFT 0x0
-#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels_MASK 0xff00
-#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels__SHIFT 0x8
-#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels_MASK 0xff0000
-#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels__SHIFT 0x10
-#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels_MASK 0xff000000
-#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels__SHIFT 0x18
-#define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels_MASK 0xff
-#define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels__SHIFT 0x0
-#define SOFT_REGISTERS_TABLE_20__ACPDpmEnabledLevels_MASK 0xff00
-#define SOFT_REGISTERS_TABLE_20__ACPDpmEnabledLevels__SHIFT 0x8
-#define SOFT_REGISTERS_TABLE_20__SAMUDpmEnabledLevels_MASK 0xff0000
-#define SOFT_REGISTERS_TABLE_20__SAMUDpmEnabledLevels__SHIFT 0x10
-#define SOFT_REGISTERS_TABLE_20__UVDDpmEnabledLevels_MASK 0xff000000
-#define SOFT_REGISTERS_TABLE_20__UVDDpmEnabledLevels__SHIFT 0x18
-#define SOFT_REGISTERS_TABLE_21__DRAM_LOG_ADDR_H_MASK 0xffffffff
-#define SOFT_REGISTERS_TABLE_21__DRAM_LOG_ADDR_H__SHIFT 0x0
-#define SOFT_REGISTERS_TABLE_22__DRAM_LOG_ADDR_L_MASK 0xffffffff
-#define SOFT_REGISTERS_TABLE_22__DRAM_LOG_ADDR_L__SHIFT 0x0
-#define SOFT_REGISTERS_TABLE_23__DRAM_LOG_PHY_ADDR_H_MASK 0xffffffff
-#define SOFT_REGISTERS_TABLE_23__DRAM_LOG_PHY_ADDR_H__SHIFT 0x0
-#define SOFT_REGISTERS_TABLE_24__DRAM_LOG_PHY_ADDR_L_MASK 0xffffffff
-#define SOFT_REGISTERS_TABLE_24__DRAM_LOG_PHY_ADDR_L__SHIFT 0x0
-#define SOFT_REGISTERS_TABLE_25__DRAM_LOG_BUFF_SIZE_MASK 0xffffffff
-#define SOFT_REGISTERS_TABLE_25__DRAM_LOG_BUFF_SIZE__SHIFT 0x0
-#define SOFT_REGISTERS_TABLE_26__UlvEnterCount_MASK 0xffffffff
-#define SOFT_REGISTERS_TABLE_26__UlvEnterCount__SHIFT 0x0
-#define SOFT_REGISTERS_TABLE_27__UlvTime_MASK 0xffffffff
-#define SOFT_REGISTERS_TABLE_27__UlvTime__SHIFT 0x0
-#define SOFT_REGISTERS_TABLE_28__Reserved_0_MASK 0xffffffff
-#define SOFT_REGISTERS_TABLE_28__Reserved_0__SHIFT 0x0
-#define SOFT_REGISTERS_TABLE_29__Reserved_1_MASK 0xffffffff
-#define SOFT_REGISTERS_TABLE_29__Reserved_1__SHIFT 0x0
-#define SOFT_REGISTERS_TABLE_30__Reserved_2_MASK 0xffffffff
-#define SOFT_REGISTERS_TABLE_30__Reserved_2__SHIFT 0x0
-#define PM_FUSES_1__BapmVddCVidHiSidd_3_MASK 0xff
-#define PM_FUSES_1__BapmVddCVidHiSidd_3__SHIFT 0x0
-#define PM_FUSES_1__BapmVddCVidHiSidd_2_MASK 0xff00
-#define PM_FUSES_1__BapmVddCVidHiSidd_2__SHIFT 0x8
-#define PM_FUSES_1__BapmVddCVidHiSidd_1_MASK 0xff0000
-#define PM_FUSES_1__BapmVddCVidHiSidd_1__SHIFT 0x10
-#define PM_FUSES_1__BapmVddCVidHiSidd_0_MASK 0xff000000
-#define PM_FUSES_1__BapmVddCVidHiSidd_0__SHIFT 0x18
-#define PM_FUSES_2__BapmVddCVidHiSidd_7_MASK 0xff
-#define PM_FUSES_2__BapmVddCVidHiSidd_7__SHIFT 0x0
-#define PM_FUSES_2__BapmVddCVidHiSidd_6_MASK 0xff00
-#define PM_FUSES_2__BapmVddCVidHiSidd_6__SHIFT 0x8
-#define PM_FUSES_2__BapmVddCVidHiSidd_5_MASK 0xff0000
-#define PM_FUSES_2__BapmVddCVidHiSidd_5__SHIFT 0x10
-#define PM_FUSES_2__BapmVddCVidHiSidd_4_MASK 0xff000000
-#define PM_FUSES_2__BapmVddCVidHiSidd_4__SHIFT 0x18
-#define PM_FUSES_3__BapmVddCVidLoSidd_3_MASK 0xff
-#define PM_FUSES_3__BapmVddCVidLoSidd_3__SHIFT 0x0
-#define PM_FUSES_3__BapmVddCVidLoSidd_2_MASK 0xff00
-#define PM_FUSES_3__BapmVddCVidLoSidd_2__SHIFT 0x8
-#define PM_FUSES_3__BapmVddCVidLoSidd_1_MASK 0xff0000
-#define PM_FUSES_3__BapmVddCVidLoSidd_1__SHIFT 0x10
-#define PM_FUSES_3__BapmVddCVidLoSidd_0_MASK 0xff000000
-#define PM_FUSES_3__BapmVddCVidLoSidd_0__SHIFT 0x18
-#define PM_FUSES_4__BapmVddCVidLoSidd_7_MASK 0xff
-#define PM_FUSES_4__BapmVddCVidLoSidd_7__SHIFT 0x0
-#define PM_FUSES_4__BapmVddCVidLoSidd_6_MASK 0xff00
-#define PM_FUSES_4__BapmVddCVidLoSidd_6__SHIFT 0x8
-#define PM_FUSES_4__BapmVddCVidLoSidd_5_MASK 0xff0000
-#define PM_FUSES_4__BapmVddCVidLoSidd_5__SHIFT 0x10
-#define PM_FUSES_4__BapmVddCVidLoSidd_4_MASK 0xff000000
-#define PM_FUSES_4__BapmVddCVidLoSidd_4__SHIFT 0x18
-#define PM_FUSES_5__VddCVid_3_MASK 0xff
-#define PM_FUSES_5__VddCVid_3__SHIFT 0x0
-#define PM_FUSES_5__VddCVid_2_MASK 0xff00
-#define PM_FUSES_5__VddCVid_2__SHIFT 0x8
-#define PM_FUSES_5__VddCVid_1_MASK 0xff0000
-#define PM_FUSES_5__VddCVid_1__SHIFT 0x10
-#define PM_FUSES_5__VddCVid_0_MASK 0xff000000
-#define PM_FUSES_5__VddCVid_0__SHIFT 0x18
-#define PM_FUSES_6__VddCVid_7_MASK 0xff
-#define PM_FUSES_6__VddCVid_7__SHIFT 0x0
-#define PM_FUSES_6__VddCVid_6_MASK 0xff00
-#define PM_FUSES_6__VddCVid_6__SHIFT 0x8
-#define PM_FUSES_6__VddCVid_5_MASK 0xff0000
-#define PM_FUSES_6__VddCVid_5__SHIFT 0x10
-#define PM_FUSES_6__VddCVid_4_MASK 0xff000000
-#define PM_FUSES_6__VddCVid_4__SHIFT 0x18
-#define PM_FUSES_7__SviLoadLineOffsetVddC_MASK 0xff
-#define PM_FUSES_7__SviLoadLineOffsetVddC__SHIFT 0x0
-#define PM_FUSES_7__SviLoadLineTrimVddC_MASK 0xff00
-#define PM_FUSES_7__SviLoadLineTrimVddC__SHIFT 0x8
-#define PM_FUSES_7__SviLoadLineVddC_MASK 0xff0000
-#define PM_FUSES_7__SviLoadLineVddC__SHIFT 0x10
-#define PM_FUSES_7__SviLoadLineEn_MASK 0xff000000
-#define PM_FUSES_7__SviLoadLineEn__SHIFT 0x18
-#define PM_FUSES_8__TDC_MAWt_MASK 0xff
-#define PM_FUSES_8__TDC_MAWt__SHIFT 0x0
-#define PM_FUSES_8__TDC_VDDC_ThrottleReleaseLimitPerc_MASK 0xff00
-#define PM_FUSES_8__TDC_VDDC_ThrottleReleaseLimitPerc__SHIFT 0x8
-#define PM_FUSES_8__TDC_VDDC_PkgLimit_MASK 0xffff0000
-#define PM_FUSES_8__TDC_VDDC_PkgLimit__SHIFT 0x10
-#define PM_FUSES_9__Reserved_MASK 0xff
-#define PM_FUSES_9__Reserved__SHIFT 0x0
-#define PM_FUSES_9__LPMLTemperatureMax_MASK 0xff00
-#define PM_FUSES_9__LPMLTemperatureMax__SHIFT 0x8
-#define PM_FUSES_9__LPMLTemperatureMin_MASK 0xff0000
-#define PM_FUSES_9__LPMLTemperatureMin__SHIFT 0x10
-#define PM_FUSES_9__TdcWaterfallCtl_MASK 0xff000000
-#define PM_FUSES_9__TdcWaterfallCtl__SHIFT 0x18
-#define PM_FUSES_10__BapmVddCVidHiSidd2_3_MASK 0xff
-#define PM_FUSES_10__BapmVddCVidHiSidd2_3__SHIFT 0x0
-#define PM_FUSES_10__BapmVddCVidHiSidd2_2_MASK 0xff00
-#define PM_FUSES_10__BapmVddCVidHiSidd2_2__SHIFT 0x8
-#define PM_FUSES_10__BapmVddCVidHiSidd2_1_MASK 0xff0000
-#define PM_FUSES_10__BapmVddCVidHiSidd2_1__SHIFT 0x10
-#define PM_FUSES_10__BapmVddCVidHiSidd2_0_MASK 0xff000000
-#define PM_FUSES_10__BapmVddCVidHiSidd2_0__SHIFT 0x18
-#define PM_FUSES_11__BapmVddCVidHiSidd2_7_MASK 0xff
-#define PM_FUSES_11__BapmVddCVidHiSidd2_7__SHIFT 0x0
-#define PM_FUSES_11__BapmVddCVidHiSidd2_6_MASK 0xff00
-#define PM_FUSES_11__BapmVddCVidHiSidd2_6__SHIFT 0x8
-#define PM_FUSES_11__BapmVddCVidHiSidd2_5_MASK 0xff0000
-#define PM_FUSES_11__BapmVddCVidHiSidd2_5__SHIFT 0x10
-#define PM_FUSES_11__BapmVddCVidHiSidd2_4_MASK 0xff000000
-#define PM_FUSES_11__BapmVddCVidHiSidd2_4__SHIFT 0x18
-#define PM_FUSES_12__FuzzyFan_ErrorRateSetDelta_MASK 0xffff
-#define PM_FUSES_12__FuzzyFan_ErrorRateSetDelta__SHIFT 0x0
-#define PM_FUSES_12__FuzzyFan_ErrorSetDelta_MASK 0xffff0000
-#define PM_FUSES_12__FuzzyFan_ErrorSetDelta__SHIFT 0x10
-#define PM_FUSES_13__Reserved6_MASK 0xffff
-#define PM_FUSES_13__Reserved6__SHIFT 0x0
-#define PM_FUSES_13__FuzzyFan_PwmSetDelta_MASK 0xffff0000
-#define PM_FUSES_13__FuzzyFan_PwmSetDelta__SHIFT 0x10
-#define PM_FUSES_14__GnbLPML_3_MASK 0xff
-#define PM_FUSES_14__GnbLPML_3__SHIFT 0x0
-#define PM_FUSES_14__GnbLPML_2_MASK 0xff00
-#define PM_FUSES_14__GnbLPML_2__SHIFT 0x8
-#define PM_FUSES_14__GnbLPML_1_MASK 0xff0000
-#define PM_FUSES_14__GnbLPML_1__SHIFT 0x10
-#define PM_FUSES_14__GnbLPML_0_MASK 0xff000000
-#define PM_FUSES_14__GnbLPML_0__SHIFT 0x18
-#define PM_FUSES_15__GnbLPML_7_MASK 0xff
-#define PM_FUSES_15__GnbLPML_7__SHIFT 0x0
-#define PM_FUSES_15__GnbLPML_6_MASK 0xff00
-#define PM_FUSES_15__GnbLPML_6__SHIFT 0x8
-#define PM_FUSES_15__GnbLPML_5_MASK 0xff0000
-#define PM_FUSES_15__GnbLPML_5__SHIFT 0x10
-#define PM_FUSES_15__GnbLPML_4_MASK 0xff000000
-#define PM_FUSES_15__GnbLPML_4__SHIFT 0x18
-#define PM_FUSES_16__GnbLPML_11_MASK 0xff
-#define PM_FUSES_16__GnbLPML_11__SHIFT 0x0
-#define PM_FUSES_16__GnbLPML_10_MASK 0xff00
-#define PM_FUSES_16__GnbLPML_10__SHIFT 0x8
-#define PM_FUSES_16__GnbLPML_9_MASK 0xff0000
-#define PM_FUSES_16__GnbLPML_9__SHIFT 0x10
-#define PM_FUSES_16__GnbLPML_8_MASK 0xff000000
-#define PM_FUSES_16__GnbLPML_8__SHIFT 0x18
-#define PM_FUSES_17__GnbLPML_15_MASK 0xff
-#define PM_FUSES_17__GnbLPML_15__SHIFT 0x0
-#define PM_FUSES_17__GnbLPML_14_MASK 0xff00
-#define PM_FUSES_17__GnbLPML_14__SHIFT 0x8
-#define PM_FUSES_17__GnbLPML_13_MASK 0xff0000
-#define PM_FUSES_17__GnbLPML_13__SHIFT 0x10
-#define PM_FUSES_17__GnbLPML_12_MASK 0xff000000
-#define PM_FUSES_17__GnbLPML_12__SHIFT 0x18
-#define PM_FUSES_18__Reserved1_1_MASK 0xff
-#define PM_FUSES_18__Reserved1_1__SHIFT 0x0
-#define PM_FUSES_18__Reserved1_0_MASK 0xff00
-#define PM_FUSES_18__Reserved1_0__SHIFT 0x8
-#define PM_FUSES_18__GnbLPMLMinVid_MASK 0xff0000
-#define PM_FUSES_18__GnbLPMLMinVid__SHIFT 0x10
-#define PM_FUSES_18__GnbLPMLMaxVid_MASK 0xff000000
-#define PM_FUSES_18__GnbLPMLMaxVid__SHIFT 0x18
-#define PM_FUSES_19__BapmVddCBaseLeakageLoSidd_MASK 0xffff
-#define PM_FUSES_19__BapmVddCBaseLeakageLoSidd__SHIFT 0x0
-#define PM_FUSES_19__BapmVddCBaseLeakageHiSidd_MASK 0xffff0000
-#define PM_FUSES_19__BapmVddCBaseLeakageHiSidd__SHIFT 0x10
-#define SMU_PM_STATUS_0__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_0__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_1__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_1__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_2__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_2__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_3__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_3__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_4__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_4__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_5__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_5__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_6__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_6__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_7__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_7__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_8__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_8__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_9__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_9__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_10__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_10__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_11__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_11__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_12__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_12__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_13__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_13__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_14__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_14__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_15__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_15__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_16__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_16__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_17__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_17__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_18__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_18__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_19__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_19__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_20__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_20__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_21__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_21__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_22__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_22__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_23__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_23__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_24__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_24__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_25__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_25__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_26__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_26__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_27__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_27__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_28__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_28__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_29__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_29__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_30__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_30__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_31__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_31__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_32__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_32__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_33__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_33__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_34__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_34__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_35__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_35__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_36__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_36__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_37__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_37__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_38__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_38__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_39__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_39__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_40__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_40__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_41__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_41__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_42__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_42__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_43__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_43__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_44__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_44__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_45__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_45__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_46__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_46__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_47__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_47__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_48__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_48__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_49__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_49__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_50__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_50__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_51__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_51__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_52__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_52__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_53__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_53__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_54__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_54__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_55__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_55__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_56__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_56__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_57__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_57__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_58__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_58__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_59__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_59__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_60__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_60__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_61__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_61__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_62__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_62__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_63__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_63__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_64__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_64__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_65__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_65__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_66__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_66__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_67__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_67__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_68__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_68__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_69__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_69__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_70__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_70__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_71__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_71__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_72__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_72__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_73__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_73__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_74__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_74__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_75__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_75__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_76__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_76__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_77__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_77__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_78__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_78__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_79__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_79__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_80__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_80__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_81__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_81__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_82__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_82__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_83__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_83__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_84__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_84__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_85__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_85__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_86__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_86__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_87__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_87__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_88__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_88__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_89__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_89__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_90__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_90__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_91__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_91__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_92__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_92__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_93__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_93__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_94__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_94__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_95__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_95__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_96__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_96__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_97__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_97__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_98__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_98__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_99__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_99__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_100__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_100__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_101__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_101__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_102__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_102__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_103__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_103__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_104__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_104__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_105__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_105__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_106__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_106__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_107__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_107__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_108__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_108__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_109__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_109__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_110__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_110__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_111__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_111__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_112__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_112__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_113__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_113__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_114__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_114__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_115__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_115__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_116__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_116__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_117__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_117__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_118__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_118__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_119__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_119__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_120__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_120__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_121__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_121__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_122__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_122__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_123__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_123__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_124__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_124__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_125__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_125__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_126__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_126__DATA__SHIFT 0x0
-#define SMU_PM_STATUS_127__DATA_MASK 0xffffffff
-#define SMU_PM_STATUS_127__DATA__SHIFT 0x0
-#define CG_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x1
-#define CG_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0
-#define CG_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x2
-#define CG_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1
-#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x4
-#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2
-#define CG_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x8
-#define CG_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3
-#define CG_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x10
-#define CG_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4
-#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x20
-#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5
-#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0xff
-#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0
-#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0xff00
-#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8
-#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD_MASK 0xff0000
-#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD__SHIFT 0x10
-#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x1000000
-#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18
-#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x2000000
-#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19
-#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x4000000
-#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a
-#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK_MASK 0x8000000
-#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK__SHIFT 0x1b
-#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA_MASK 0x10000000
-#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA__SHIFT 0x1c
-#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x1
-#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0
-#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x2
-#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1
-#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x4
-#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2
-#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT_MASK 0x8
-#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT__SHIFT 0x3
-#define CG_THERMAL_CTRL__DPM_EVENT_SRC_MASK 0x7
-#define CG_THERMAL_CTRL__DPM_EVENT_SRC__SHIFT 0x0
-#define CG_THERMAL_CTRL__THERM_INC_CLK_MASK 0x8
-#define CG_THERMAL_CTRL__THERM_INC_CLK__SHIFT 0x3
-#define CG_THERMAL_CTRL__SPARE_MASK 0x3ff0
-#define CG_THERMAL_CTRL__SPARE__SHIFT 0x4
-#define CG_THERMAL_CTRL__DIG_THERM_DPM_MASK 0x3fc000
-#define CG_THERMAL_CTRL__DIG_THERM_DPM__SHIFT 0xe
-#define CG_THERMAL_CTRL__RESERVED_MASK 0x1c00000
-#define CG_THERMAL_CTRL__RESERVED__SHIFT 0x16
-#define CG_THERMAL_CTRL__CTF_PAD_POLARITY_MASK 0x2000000
-#define CG_THERMAL_CTRL__CTF_PAD_POLARITY__SHIFT 0x19
-#define CG_THERMAL_CTRL__CTF_PAD_EN_MASK 0x4000000
-#define CG_THERMAL_CTRL__CTF_PAD_EN__SHIFT 0x1a
-#define CG_THERMAL_STATUS__SPARE_MASK 0x1ff
-#define CG_THERMAL_STATUS__SPARE__SHIFT 0x0
-#define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK 0x1fe00
-#define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT 0x9
-#define CG_THERMAL_STATUS__THERM_ALERT_MASK 0x20000
-#define CG_THERMAL_STATUS__THERM_ALERT__SHIFT 0x11
-#define CG_THERMAL_STATUS__GEN_STATUS_MASK 0x3c0000
-#define CG_THERMAL_STATUS__GEN_STATUS__SHIFT 0x12
-#define CG_THERMAL_INT__DIG_THERM_CTF_MASK 0xff
-#define CG_THERMAL_INT__DIG_THERM_CTF__SHIFT 0x0
-#define CG_THERMAL_INT__DIG_THERM_INTH_MASK 0xff00
-#define CG_THERMAL_INT__DIG_THERM_INTH__SHIFT 0x8
-#define CG_THERMAL_INT__DIG_THERM_INTL_MASK 0xff0000
-#define CG_THERMAL_INT__DIG_THERM_INTL__SHIFT 0x10
-#define CG_THERMAL_INT__THERM_INT_MASK_MASK 0xf000000
-#define CG_THERMAL_INT__THERM_INT_MASK__SHIFT 0x18
-#define CG_MULT_THERMAL_CTRL__TS_FILTER_MASK 0xf
-#define CG_MULT_THERMAL_CTRL__TS_FILTER__SHIFT 0x0
-#define CG_MULT_THERMAL_CTRL__UNUSED_MASK 0xf0
-#define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT 0x4
-#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK 0x200
-#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT 0x9
-#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0xff00000
-#define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT 0x14
-#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x1ff
-#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0
-#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x3fe00
-#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9
-#define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK 0xff
-#define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT 0x0
-#define CG_FDO_CTRL0__FAN_SPINUP_DUTY_MASK 0xff00
-#define CG_FDO_CTRL0__FAN_SPINUP_DUTY__SHIFT 0x8
-#define CG_FDO_CTRL0__FDO_PWM_MANUAL_MASK 0x10000
-#define CG_FDO_CTRL0__FDO_PWM_MANUAL__SHIFT 0x10
-#define CG_FDO_CTRL0__FDO_PWM_HYSTER_MASK 0x7e0000
-#define CG_FDO_CTRL0__FDO_PWM_HYSTER__SHIFT 0x11
-#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN_MASK 0x800000
-#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN__SHIFT 0x17
-#define CG_FDO_CTRL0__FDO_PWM_RAMP_MASK 0xff000000
-#define CG_FDO_CTRL0__FDO_PWM_RAMP__SHIFT 0x18
-#define CG_FDO_CTRL1__FMAX_DUTY100_MASK 0xff
-#define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT 0x0
-#define CG_FDO_CTRL1__FMIN_DUTY_MASK 0xff00
-#define CG_FDO_CTRL1__FMIN_DUTY__SHIFT 0x8
-#define CG_FDO_CTRL1__M_MASK 0xff0000
-#define CG_FDO_CTRL1__M__SHIFT 0x10
-#define CG_FDO_CTRL1__RESERVED_MASK 0x3f000000
-#define CG_FDO_CTRL1__RESERVED__SHIFT 0x18
-#define CG_FDO_CTRL1__FDO_PWRDNB_MASK 0x40000000
-#define CG_FDO_CTRL1__FDO_PWRDNB__SHIFT 0x1e
-#define CG_FDO_CTRL2__TMIN_MASK 0xff
-#define CG_FDO_CTRL2__TMIN__SHIFT 0x0
-#define CG_FDO_CTRL2__FAN_SPINUP_TIME_MASK 0x700
-#define CG_FDO_CTRL2__FAN_SPINUP_TIME__SHIFT 0x8
-#define CG_FDO_CTRL2__FDO_PWM_MODE_MASK 0x3800
-#define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT 0xb
-#define CG_FDO_CTRL2__TMIN_HYSTER_MASK 0x1c000
-#define CG_FDO_CTRL2__TMIN_HYSTER__SHIFT 0xe
-#define CG_FDO_CTRL2__TMAX_MASK 0x1fe0000
-#define CG_FDO_CTRL2__TMAX__SHIFT 0x11
-#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK 0xfe000000
-#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19
-#define CG_TACH_CTRL__EDGE_PER_REV_MASK 0x7
-#define CG_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0
-#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xfffffff8
-#define CG_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3
-#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xffffffff
-#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0
-#define CC_THM_STRAPS0__TMON0_BGADJ_MASK 0x1fe
-#define CC_THM_STRAPS0__TMON0_BGADJ__SHIFT 0x1
-#define CC_THM_STRAPS0__TMON1_BGADJ_MASK 0x1fe00
-#define CC_THM_STRAPS0__TMON1_BGADJ__SHIFT 0x9
-#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL_MASK 0x20000
-#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL__SHIFT 0x11
-#define CC_THM_STRAPS0__NUM_ACQ_MASK 0x1c0000
-#define CC_THM_STRAPS0__NUM_ACQ__SHIFT 0x12
-#define CC_THM_STRAPS0__TMON_CLK_SEL_MASK 0xe00000
-#define CC_THM_STRAPS0__TMON_CLK_SEL__SHIFT 0x15
-#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE_MASK 0x1000000
-#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE__SHIFT 0x18
-#define CC_THM_STRAPS0__CTF_DISABLE_MASK 0x2000000
-#define CC_THM_STRAPS0__CTF_DISABLE__SHIFT 0x19
-#define CC_THM_STRAPS0__TMON0_DISABLE_MASK 0x4000000
-#define CC_THM_STRAPS0__TMON0_DISABLE__SHIFT 0x1a
-#define CC_THM_STRAPS0__TMON1_DISABLE_MASK 0x8000000
-#define CC_THM_STRAPS0__TMON1_DISABLE__SHIFT 0x1b
-#define CC_THM_STRAPS0__TMON2_DISABLE_MASK 0x10000000
-#define CC_THM_STRAPS0__TMON2_DISABLE__SHIFT 0x1c
-#define CC_THM_STRAPS0__TMON3_DISABLE_MASK 0x20000000
-#define CC_THM_STRAPS0__TMON3_DISABLE__SHIFT 0x1d
-#define CC_THM_STRAPS0__UNUSED_MASK 0x80000000
-#define CC_THM_STRAPS0__UNUSED__SHIFT 0x1f
-#define THM_TMON0_RDIL0_DATA__Z_MASK 0x7ff
-#define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x0
-#define THM_TMON0_RDIL0_DATA__VALID_MASK 0x800
-#define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0xb
-#define THM_TMON0_RDIL0_DATA__TEMP_MASK 0xfff000
-#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0xc
-#define THM_TMON0_RDIL1_DATA__Z_MASK 0x7ff
-#define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x0
-#define THM_TMON0_RDIL1_DATA__VALID_MASK 0x800
-#define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0xb
-#define THM_TMON0_RDIL1_DATA__TEMP_MASK 0xfff000
-#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0xc
-#define THM_TMON0_RDIL2_DATA__Z_MASK 0x7ff
-#define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x0
-#define THM_TMON0_RDIL2_DATA__VALID_MASK 0x800
-#define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0xb
-#define THM_TMON0_RDIL2_DATA__TEMP_MASK 0xfff000
-#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0xc
-#define THM_TMON0_RDIL3_DATA__Z_MASK 0x7ff
-#define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x0
-#define THM_TMON0_RDIL3_DATA__VALID_MASK 0x800
-#define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0xb
-#define THM_TMON0_RDIL3_DATA__TEMP_MASK 0xfff000
-#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0xc
-#define THM_TMON0_RDIL4_DATA__Z_MASK 0x7ff
-#define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x0
-#define THM_TMON0_RDIL4_DATA__VALID_MASK 0x800
-#define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0xb
-#define THM_TMON0_RDIL4_DATA__TEMP_MASK 0xfff000
-#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0xc
-#define THM_TMON0_RDIL5_DATA__Z_MASK 0x7ff
-#define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0
-#define THM_TMON0_RDIL5_DATA__VALID_MASK 0x800
-#define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0xb
-#define THM_TMON0_RDIL5_DATA__TEMP_MASK 0xfff000
-#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0xc
-#define THM_TMON0_RDIL6_DATA__Z_MASK 0x7ff
-#define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x0
-#define THM_TMON0_RDIL6_DATA__VALID_MASK 0x800
-#define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0xb
-#define THM_TMON0_RDIL6_DATA__TEMP_MASK 0xfff000
-#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0xc
-#define THM_TMON0_RDIL7_DATA__Z_MASK 0x7ff
-#define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x0
-#define THM_TMON0_RDIL7_DATA__VALID_MASK 0x800
-#define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0xb
-#define THM_TMON0_RDIL7_DATA__TEMP_MASK 0xfff000
-#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0xc
-#define THM_TMON0_RDIL8_DATA__Z_MASK 0x7ff
-#define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x0
-#define THM_TMON0_RDIL8_DATA__VALID_MASK 0x800
-#define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb
-#define THM_TMON0_RDIL8_DATA__TEMP_MASK 0xfff000
-#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0xc
-#define THM_TMON0_RDIL9_DATA__Z_MASK 0x7ff
-#define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x0
-#define THM_TMON0_RDIL9_DATA__VALID_MASK 0x800
-#define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0xb
-#define THM_TMON0_RDIL9_DATA__TEMP_MASK 0xfff000
-#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0xc
-#define THM_TMON0_RDIL10_DATA__Z_MASK 0x7ff
-#define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x0
-#define THM_TMON0_RDIL10_DATA__VALID_MASK 0x800
-#define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0xb
-#define THM_TMON0_RDIL10_DATA__TEMP_MASK 0xfff000
-#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0xc
-#define THM_TMON0_RDIL11_DATA__Z_MASK 0x7ff
-#define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x0
-#define THM_TMON0_RDIL11_DATA__VALID_MASK 0x800
-#define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0xb
-#define THM_TMON0_RDIL11_DATA__TEMP_MASK 0xfff000
-#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0xc
-#define THM_TMON0_RDIL12_DATA__Z_MASK 0x7ff
-#define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x0
-#define THM_TMON0_RDIL12_DATA__VALID_MASK 0x800
-#define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0xb
-#define THM_TMON0_RDIL12_DATA__TEMP_MASK 0xfff000
-#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0xc
-#define THM_TMON0_RDIL13_DATA__Z_MASK 0x7ff
-#define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x0
-#define THM_TMON0_RDIL13_DATA__VALID_MASK 0x800
-#define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0xb
-#define THM_TMON0_RDIL13_DATA__TEMP_MASK 0xfff000
-#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0xc
-#define THM_TMON0_RDIL14_DATA__Z_MASK 0x7ff
-#define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x0
-#define THM_TMON0_RDIL14_DATA__VALID_MASK 0x800
-#define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0xb
-#define THM_TMON0_RDIL14_DATA__TEMP_MASK 0xfff000
-#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0xc
-#define THM_TMON0_RDIL15_DATA__Z_MASK 0x7ff
-#define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x0
-#define THM_TMON0_RDIL15_DATA__VALID_MASK 0x800
-#define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0xb
-#define THM_TMON0_RDIL15_DATA__TEMP_MASK 0xfff000
-#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0xc
-#define THM_TMON0_RDIR0_DATA__Z_MASK 0x7ff
-#define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x0
-#define THM_TMON0_RDIR0_DATA__VALID_MASK 0x800
-#define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0xb
-#define THM_TMON0_RDIR0_DATA__TEMP_MASK 0xfff000
-#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0xc
-#define THM_TMON0_RDIR1_DATA__Z_MASK 0x7ff
-#define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x0
-#define THM_TMON0_RDIR1_DATA__VALID_MASK 0x800
-#define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0xb
-#define THM_TMON0_RDIR1_DATA__TEMP_MASK 0xfff000
-#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0xc
-#define THM_TMON0_RDIR2_DATA__Z_MASK 0x7ff
-#define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x0
-#define THM_TMON0_RDIR2_DATA__VALID_MASK 0x800
-#define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0xb
-#define THM_TMON0_RDIR2_DATA__TEMP_MASK 0xfff000
-#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0xc
-#define THM_TMON0_RDIR3_DATA__Z_MASK 0x7ff
-#define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x0
-#define THM_TMON0_RDIR3_DATA__VALID_MASK 0x800
-#define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0xb
-#define THM_TMON0_RDIR3_DATA__TEMP_MASK 0xfff000
-#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0xc
-#define THM_TMON0_RDIR4_DATA__Z_MASK 0x7ff
-#define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x0
-#define THM_TMON0_RDIR4_DATA__VALID_MASK 0x800
-#define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0xb
-#define THM_TMON0_RDIR4_DATA__TEMP_MASK 0xfff000
-#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0xc
-#define THM_TMON0_RDIR5_DATA__Z_MASK 0x7ff
-#define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x0
-#define THM_TMON0_RDIR5_DATA__VALID_MASK 0x800
-#define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb
-#define THM_TMON0_RDIR5_DATA__TEMP_MASK 0xfff000
-#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0xc
-#define THM_TMON0_RDIR6_DATA__Z_MASK 0x7ff
-#define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x0
-#define THM_TMON0_RDIR6_DATA__VALID_MASK 0x800
-#define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0xb
-#define THM_TMON0_RDIR6_DATA__TEMP_MASK 0xfff000
-#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0xc
-#define THM_TMON0_RDIR7_DATA__Z_MASK 0x7ff
-#define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x0
-#define THM_TMON0_RDIR7_DATA__VALID_MASK 0x800
-#define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0xb
-#define THM_TMON0_RDIR7_DATA__TEMP_MASK 0xfff000
-#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0xc
-#define THM_TMON0_RDIR8_DATA__Z_MASK 0x7ff
-#define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x0
-#define THM_TMON0_RDIR8_DATA__VALID_MASK 0x800
-#define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0xb
-#define THM_TMON0_RDIR8_DATA__TEMP_MASK 0xfff000
-#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0xc
-#define THM_TMON0_RDIR9_DATA__Z_MASK 0x7ff
-#define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x0
-#define THM_TMON0_RDIR9_DATA__VALID_MASK 0x800
-#define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0xb
-#define THM_TMON0_RDIR9_DATA__TEMP_MASK 0xfff000
-#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0xc
-#define THM_TMON0_RDIR10_DATA__Z_MASK 0x7ff
-#define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x0
-#define THM_TMON0_RDIR10_DATA__VALID_MASK 0x800
-#define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb
-#define THM_TMON0_RDIR10_DATA__TEMP_MASK 0xfff000
-#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0xc
-#define THM_TMON0_RDIR11_DATA__Z_MASK 0x7ff
-#define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x0
-#define THM_TMON0_RDIR11_DATA__VALID_MASK 0x800
-#define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0xb
-#define THM_TMON0_RDIR11_DATA__TEMP_MASK 0xfff000
-#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0xc
-#define THM_TMON0_RDIR12_DATA__Z_MASK 0x7ff
-#define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x0
-#define THM_TMON0_RDIR12_DATA__VALID_MASK 0x800
-#define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0xb
-#define THM_TMON0_RDIR12_DATA__TEMP_MASK 0xfff000
-#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0xc
-#define THM_TMON0_RDIR13_DATA__Z_MASK 0x7ff
-#define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x0
-#define THM_TMON0_RDIR13_DATA__VALID_MASK 0x800
-#define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0xb
-#define THM_TMON0_RDIR13_DATA__TEMP_MASK 0xfff000
-#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0xc
-#define THM_TMON0_RDIR14_DATA__Z_MASK 0x7ff
-#define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x0
-#define THM_TMON0_RDIR14_DATA__VALID_MASK 0x800
-#define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0xb
-#define THM_TMON0_RDIR14_DATA__TEMP_MASK 0xfff000
-#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0xc
-#define THM_TMON0_RDIR15_DATA__Z_MASK 0x7ff
-#define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x0
-#define THM_TMON0_RDIR15_DATA__VALID_MASK 0x800
-#define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0xb
-#define THM_TMON0_RDIR15_DATA__TEMP_MASK 0xfff000
-#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0xc
-#define THM_TMON1_RDIL0_DATA__Z_MASK 0x7ff
-#define THM_TMON1_RDIL0_DATA__Z__SHIFT 0x0
-#define THM_TMON1_RDIL0_DATA__VALID_MASK 0x800
-#define THM_TMON1_RDIL0_DATA__VALID__SHIFT 0xb
-#define THM_TMON1_RDIL0_DATA__TEMP_MASK 0xfff000
-#define THM_TMON1_RDIL0_DATA__TEMP__SHIFT 0xc
-#define THM_TMON1_RDIL1_DATA__Z_MASK 0x7ff
-#define THM_TMON1_RDIL1_DATA__Z__SHIFT 0x0
-#define THM_TMON1_RDIL1_DATA__VALID_MASK 0x800
-#define THM_TMON1_RDIL1_DATA__VALID__SHIFT 0xb
-#define THM_TMON1_RDIL1_DATA__TEMP_MASK 0xfff000
-#define THM_TMON1_RDIL1_DATA__TEMP__SHIFT 0xc
-#define THM_TMON1_RDIL2_DATA__Z_MASK 0x7ff
-#define THM_TMON1_RDIL2_DATA__Z__SHIFT 0x0
-#define THM_TMON1_RDIL2_DATA__VALID_MASK 0x800
-#define THM_TMON1_RDIL2_DATA__VALID__SHIFT 0xb
-#define THM_TMON1_RDIL2_DATA__TEMP_MASK 0xfff000
-#define THM_TMON1_RDIL2_DATA__TEMP__SHIFT 0xc
-#define THM_TMON1_RDIL3_DATA__Z_MASK 0x7ff
-#define THM_TMON1_RDIL3_DATA__Z__SHIFT 0x0
-#define THM_TMON1_RDIL3_DATA__VALID_MASK 0x800
-#define THM_TMON1_RDIL3_DATA__VALID__SHIFT 0xb
-#define THM_TMON1_RDIL3_DATA__TEMP_MASK 0xfff000
-#define THM_TMON1_RDIL3_DATA__TEMP__SHIFT 0xc
-#define THM_TMON1_RDIL4_DATA__Z_MASK 0x7ff
-#define THM_TMON1_RDIL4_DATA__Z__SHIFT 0x0
-#define THM_TMON1_RDIL4_DATA__VALID_MASK 0x800
-#define THM_TMON1_RDIL4_DATA__VALID__SHIFT 0xb
-#define THM_TMON1_RDIL4_DATA__TEMP_MASK 0xfff000
-#define THM_TMON1_RDIL4_DATA__TEMP__SHIFT 0xc
-#define THM_TMON1_RDIL5_DATA__Z_MASK 0x7ff
-#define THM_TMON1_RDIL5_DATA__Z__SHIFT 0x0
-#define THM_TMON1_RDIL5_DATA__VALID_MASK 0x800
-#define THM_TMON1_RDIL5_DATA__VALID__SHIFT 0xb
-#define THM_TMON1_RDIL5_DATA__TEMP_MASK 0xfff000
-#define THM_TMON1_RDIL5_DATA__TEMP__SHIFT 0xc
-#define THM_TMON1_RDIL6_DATA__Z_MASK 0x7ff
-#define THM_TMON1_RDIL6_DATA__Z__SHIFT 0x0
-#define THM_TMON1_RDIL6_DATA__VALID_MASK 0x800
-#define THM_TMON1_RDIL6_DATA__VALID__SHIFT 0xb
-#define THM_TMON1_RDIL6_DATA__TEMP_MASK 0xfff000
-#define THM_TMON1_RDIL6_DATA__TEMP__SHIFT 0xc
-#define THM_TMON1_RDIL7_DATA__Z_MASK 0x7ff
-#define THM_TMON1_RDIL7_DATA__Z__SHIFT 0x0
-#define THM_TMON1_RDIL7_DATA__VALID_MASK 0x800
-#define THM_TMON1_RDIL7_DATA__VALID__SHIFT 0xb
-#define THM_TMON1_RDIL7_DATA__TEMP_MASK 0xfff000
-#define THM_TMON1_RDIL7_DATA__TEMP__SHIFT 0xc
-#define THM_TMON1_RDIL8_DATA__Z_MASK 0x7ff
-#define THM_TMON1_RDIL8_DATA__Z__SHIFT 0x0
-#define THM_TMON1_RDIL8_DATA__VALID_MASK 0x800
-#define THM_TMON1_RDIL8_DATA__VALID__SHIFT 0xb
-#define THM_TMON1_RDIL8_DATA__TEMP_MASK 0xfff000
-#define THM_TMON1_RDIL8_DATA__TEMP__SHIFT 0xc
-#define THM_TMON1_RDIL9_DATA__Z_MASK 0x7ff
-#define THM_TMON1_RDIL9_DATA__Z__SHIFT 0x0
-#define THM_TMON1_RDIL9_DATA__VALID_MASK 0x800
-#define THM_TMON1_RDIL9_DATA__VALID__SHIFT 0xb
-#define THM_TMON1_RDIL9_DATA__TEMP_MASK 0xfff000
-#define THM_TMON1_RDIL9_DATA__TEMP__SHIFT 0xc
-#define THM_TMON1_RDIL10_DATA__Z_MASK 0x7ff
-#define THM_TMON1_RDIL10_DATA__Z__SHIFT 0x0
-#define THM_TMON1_RDIL10_DATA__VALID_MASK 0x800
-#define THM_TMON1_RDIL10_DATA__VALID__SHIFT 0xb
-#define THM_TMON1_RDIL10_DATA__TEMP_MASK 0xfff000
-#define THM_TMON1_RDIL10_DATA__TEMP__SHIFT 0xc
-#define THM_TMON1_RDIL11_DATA__Z_MASK 0x7ff
-#define THM_TMON1_RDIL11_DATA__Z__SHIFT 0x0
-#define THM_TMON1_RDIL11_DATA__VALID_MASK 0x800
-#define THM_TMON1_RDIL11_DATA__VALID__SHIFT 0xb
-#define THM_TMON1_RDIL11_DATA__TEMP_MASK 0xfff000
-#define THM_TMON1_RDIL11_DATA__TEMP__SHIFT 0xc
-#define THM_TMON1_RDIL12_DATA__Z_MASK 0x7ff
-#define THM_TMON1_RDIL12_DATA__Z__SHIFT 0x0
-#define THM_TMON1_RDIL12_DATA__VALID_MASK 0x800
-#define THM_TMON1_RDIL12_DATA__VALID__SHIFT 0xb
-#define THM_TMON1_RDIL12_DATA__TEMP_MASK 0xfff000
-#define THM_TMON1_RDIL12_DATA__TEMP__SHIFT 0xc
-#define THM_TMON1_RDIL13_DATA__Z_MASK 0x7ff
-#define THM_TMON1_RDIL13_DATA__Z__SHIFT 0x0
-#define THM_TMON1_RDIL13_DATA__VALID_MASK 0x800
-#define THM_TMON1_RDIL13_DATA__VALID__SHIFT 0xb
-#define THM_TMON1_RDIL13_DATA__TEMP_MASK 0xfff000
-#define THM_TMON1_RDIL13_DATA__TEMP__SHIFT 0xc
-#define THM_TMON1_RDIL14_DATA__Z_MASK 0x7ff
-#define THM_TMON1_RDIL14_DATA__Z__SHIFT 0x0
-#define THM_TMON1_RDIL14_DATA__VALID_MASK 0x800
-#define THM_TMON1_RDIL14_DATA__VALID__SHIFT 0xb
-#define THM_TMON1_RDIL14_DATA__TEMP_MASK 0xfff000
-#define THM_TMON1_RDIL14_DATA__TEMP__SHIFT 0xc
-#define THM_TMON1_RDIL15_DATA__Z_MASK 0x7ff
-#define THM_TMON1_RDIL15_DATA__Z__SHIFT 0x0
-#define THM_TMON1_RDIL15_DATA__VALID_MASK 0x800
-#define THM_TMON1_RDIL15_DATA__VALID__SHIFT 0xb
-#define THM_TMON1_RDIL15_DATA__TEMP_MASK 0xfff000
-#define THM_TMON1_RDIL15_DATA__TEMP__SHIFT 0xc
-#define THM_TMON1_RDIR0_DATA__Z_MASK 0x7ff
-#define THM_TMON1_RDIR0_DATA__Z__SHIFT 0x0
-#define THM_TMON1_RDIR0_DATA__VALID_MASK 0x800
-#define THM_TMON1_RDIR0_DATA__VALID__SHIFT 0xb
-#define THM_TMON1_RDIR0_DATA__TEMP_MASK 0xfff000
-#define THM_TMON1_RDIR0_DATA__TEMP__SHIFT 0xc
-#define THM_TMON1_RDIR1_DATA__Z_MASK 0x7ff
-#define THM_TMON1_RDIR1_DATA__Z__SHIFT 0x0
-#define THM_TMON1_RDIR1_DATA__VALID_MASK 0x800
-#define THM_TMON1_RDIR1_DATA__VALID__SHIFT 0xb
-#define THM_TMON1_RDIR1_DATA__TEMP_MASK 0xfff000
-#define THM_TMON1_RDIR1_DATA__TEMP__SHIFT 0xc
-#define THM_TMON1_RDIR2_DATA__Z_MASK 0x7ff
-#define THM_TMON1_RDIR2_DATA__Z__SHIFT 0x0
-#define THM_TMON1_RDIR2_DATA__VALID_MASK 0x800
-#define THM_TMON1_RDIR2_DATA__VALID__SHIFT 0xb
-#define THM_TMON1_RDIR2_DATA__TEMP_MASK 0xfff000
-#define THM_TMON1_RDIR2_DATA__TEMP__SHIFT 0xc
-#define THM_TMON1_RDIR3_DATA__Z_MASK 0x7ff
-#define THM_TMON1_RDIR3_DATA__Z__SHIFT 0x0
-#define THM_TMON1_RDIR3_DATA__VALID_MASK 0x800
-#define THM_TMON1_RDIR3_DATA__VALID__SHIFT 0xb
-#define THM_TMON1_RDIR3_DATA__TEMP_MASK 0xfff000
-#define THM_TMON1_RDIR3_DATA__TEMP__SHIFT 0xc
-#define THM_TMON1_RDIR4_DATA__Z_MASK 0x7ff
-#define THM_TMON1_RDIR4_DATA__Z__SHIFT 0x0
-#define THM_TMON1_RDIR4_DATA__VALID_MASK 0x800
-#define THM_TMON1_RDIR4_DATA__VALID__SHIFT 0xb
-#define THM_TMON1_RDIR4_DATA__TEMP_MASK 0xfff000
-#define THM_TMON1_RDIR4_DATA__TEMP__SHIFT 0xc
-#define THM_TMON1_RDIR5_DATA__Z_MASK 0x7ff
-#define THM_TMON1_RDIR5_DATA__Z__SHIFT 0x0
-#define THM_TMON1_RDIR5_DATA__VALID_MASK 0x800
-#define THM_TMON1_RDIR5_DATA__VALID__SHIFT 0xb
-#define THM_TMON1_RDIR5_DATA__TEMP_MASK 0xfff000
-#define THM_TMON1_RDIR5_DATA__TEMP__SHIFT 0xc
-#define THM_TMON1_RDIR6_DATA__Z_MASK 0x7ff
-#define THM_TMON1_RDIR6_DATA__Z__SHIFT 0x0
-#define THM_TMON1_RDIR6_DATA__VALID_MASK 0x800
-#define THM_TMON1_RDIR6_DATA__VALID__SHIFT 0xb
-#define THM_TMON1_RDIR6_DATA__TEMP_MASK 0xfff000
-#define THM_TMON1_RDIR6_DATA__TEMP__SHIFT 0xc
-#define THM_TMON1_RDIR7_DATA__Z_MASK 0x7ff
-#define THM_TMON1_RDIR7_DATA__Z__SHIFT 0x0
-#define THM_TMON1_RDIR7_DATA__VALID_MASK 0x800
-#define THM_TMON1_RDIR7_DATA__VALID__SHIFT 0xb
-#define THM_TMON1_RDIR7_DATA__TEMP_MASK 0xfff000
-#define THM_TMON1_RDIR7_DATA__TEMP__SHIFT 0xc
-#define THM_TMON1_RDIR8_DATA__Z_MASK 0x7ff
-#define THM_TMON1_RDIR8_DATA__Z__SHIFT 0x0
-#define THM_TMON1_RDIR8_DATA__VALID_MASK 0x800
-#define THM_TMON1_RDIR8_DATA__VALID__SHIFT 0xb
-#define THM_TMON1_RDIR8_DATA__TEMP_MASK 0xfff000
-#define THM_TMON1_RDIR8_DATA__TEMP__SHIFT 0xc
-#define THM_TMON1_RDIR9_DATA__Z_MASK 0x7ff
-#define THM_TMON1_RDIR9_DATA__Z__SHIFT 0x0
-#define THM_TMON1_RDIR9_DATA__VALID_MASK 0x800
-#define THM_TMON1_RDIR9_DATA__VALID__SHIFT 0xb
-#define THM_TMON1_RDIR9_DATA__TEMP_MASK 0xfff000
-#define THM_TMON1_RDIR9_DATA__TEMP__SHIFT 0xc
-#define THM_TMON1_RDIR10_DATA__Z_MASK 0x7ff
-#define THM_TMON1_RDIR10_DATA__Z__SHIFT 0x0
-#define THM_TMON1_RDIR10_DATA__VALID_MASK 0x800
-#define THM_TMON1_RDIR10_DATA__VALID__SHIFT 0xb
-#define THM_TMON1_RDIR10_DATA__TEMP_MASK 0xfff000
-#define THM_TMON1_RDIR10_DATA__TEMP__SHIFT 0xc
-#define THM_TMON1_RDIR11_DATA__Z_MASK 0x7ff
-#define THM_TMON1_RDIR11_DATA__Z__SHIFT 0x0
-#define THM_TMON1_RDIR11_DATA__VALID_MASK 0x800
-#define THM_TMON1_RDIR11_DATA__VALID__SHIFT 0xb
-#define THM_TMON1_RDIR11_DATA__TEMP_MASK 0xfff000
-#define THM_TMON1_RDIR11_DATA__TEMP__SHIFT 0xc
-#define THM_TMON1_RDIR12_DATA__Z_MASK 0x7ff
-#define THM_TMON1_RDIR12_DATA__Z__SHIFT 0x0
-#define THM_TMON1_RDIR12_DATA__VALID_MASK 0x800
-#define THM_TMON1_RDIR12_DATA__VALID__SHIFT 0xb
-#define THM_TMON1_RDIR12_DATA__TEMP_MASK 0xfff000
-#define THM_TMON1_RDIR12_DATA__TEMP__SHIFT 0xc
-#define THM_TMON1_RDIR13_DATA__Z_MASK 0x7ff
-#define THM_TMON1_RDIR13_DATA__Z__SHIFT 0x0
-#define THM_TMON1_RDIR13_DATA__VALID_MASK 0x800
-#define THM_TMON1_RDIR13_DATA__VALID__SHIFT 0xb
-#define THM_TMON1_RDIR13_DATA__TEMP_MASK 0xfff000
-#define THM_TMON1_RDIR13_DATA__TEMP__SHIFT 0xc
-#define THM_TMON1_RDIR14_DATA__Z_MASK 0x7ff
-#define THM_TMON1_RDIR14_DATA__Z__SHIFT 0x0
-#define THM_TMON1_RDIR14_DATA__VALID_MASK 0x800
-#define THM_TMON1_RDIR14_DATA__VALID__SHIFT 0xb
-#define THM_TMON1_RDIR14_DATA__TEMP_MASK 0xfff000
-#define THM_TMON1_RDIR14_DATA__TEMP__SHIFT 0xc
-#define THM_TMON1_RDIR15_DATA__Z_MASK 0x7ff
-#define THM_TMON1_RDIR15_DATA__Z__SHIFT 0x0
-#define THM_TMON1_RDIR15_DATA__VALID_MASK 0x800
-#define THM_TMON1_RDIR15_DATA__VALID__SHIFT 0xb
-#define THM_TMON1_RDIR15_DATA__TEMP_MASK 0xfff000
-#define THM_TMON1_RDIR15_DATA__TEMP__SHIFT 0xc
-#define THM_TMON0_INT_DATA__Z_MASK 0x7ff
-#define THM_TMON0_INT_DATA__Z__SHIFT 0x0
-#define THM_TMON0_INT_DATA__VALID_MASK 0x800
-#define THM_TMON0_INT_DATA__VALID__SHIFT 0xb
-#define THM_TMON0_INT_DATA__TEMP_MASK 0xfff000
-#define THM_TMON0_INT_DATA__TEMP__SHIFT 0xc
-#define THM_TMON1_INT_DATA__Z_MASK 0x7ff
-#define THM_TMON1_INT_DATA__Z__SHIFT 0x0
-#define THM_TMON1_INT_DATA__VALID_MASK 0x800
-#define THM_TMON1_INT_DATA__VALID__SHIFT 0xb
-#define THM_TMON1_INT_DATA__TEMP_MASK 0xfff000
-#define THM_TMON1_INT_DATA__TEMP__SHIFT 0xc
-#define THM_TMON0_DEBUG__DEBUG_RDI_MASK 0x1f
-#define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT 0x0
-#define THM_TMON0_DEBUG__DEBUG_Z_MASK 0xffe0
-#define THM_TMON0_DEBUG__DEBUG_Z__SHIFT 0x5
-#define THM_TMON1_DEBUG__DEBUG_RDI_MASK 0x1f
-#define THM_TMON1_DEBUG__DEBUG_RDI__SHIFT 0x0
-#define THM_TMON1_DEBUG__DEBUG_Z_MASK 0xffe0
-#define THM_TMON1_DEBUG__DEBUG_Z__SHIFT 0x5
-#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK 0x1
-#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN__SHIFT 0x0
-#define GENERAL_PWRMGT__STATIC_PM_EN_MASK 0x2
-#define GENERAL_PWRMGT__STATIC_PM_EN__SHIFT 0x1
-#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK 0x4
-#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT 0x2
-#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE_MASK 0x8
-#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE__SHIFT 0x3
-#define GENERAL_PWRMGT__SW_SMIO_INDEX_MASK 0x40
-#define GENERAL_PWRMGT__SW_SMIO_INDEX__SHIFT 0x6
-#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI_MASK 0x100
-#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI__SHIFT 0x8
-#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI_MASK 0x200
-#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI__SHIFT 0x9
-#define GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK 0x400
-#define GENERAL_PWRMGT__VOLT_PWRMGT_EN__SHIFT 0xa
-#define GENERAL_PWRMGT__SPARE11_MASK 0x800
-#define GENERAL_PWRMGT__SPARE11__SHIFT 0xb
-#define GENERAL_PWRMGT__GPU_COUNTER_ACPI_MASK 0x4000
-#define GENERAL_PWRMGT__GPU_COUNTER_ACPI__SHIFT 0xe
-#define GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK 0x8000
-#define GENERAL_PWRMGT__GPU_COUNTER_CLK__SHIFT 0xf
-#define GENERAL_PWRMGT__GPU_COUNTER_OFF_MASK 0x10000
-#define GENERAL_PWRMGT__GPU_COUNTER_OFF__SHIFT 0x10
-#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF_MASK 0x20000
-#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF__SHIFT 0x11
-#define GENERAL_PWRMGT__SPARE18_MASK 0x40000
-#define GENERAL_PWRMGT__SPARE18__SHIFT 0x12
-#define GENERAL_PWRMGT__ACPI_D3_VID_MASK 0x180000
-#define GENERAL_PWRMGT__ACPI_D3_VID__SHIFT 0x13
-#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK 0x800000
-#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN__SHIFT 0x17
-#define GENERAL_PWRMGT__SPARE27_MASK 0x8000000
-#define GENERAL_PWRMGT__SPARE27__SHIFT 0x1b
-#define GENERAL_PWRMGT__SPARE_MASK 0xf0000000
-#define GENERAL_PWRMGT__SPARE__SHIFT 0x1c
-#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK 0x3
-#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT 0x0
-#define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4
-#define CNB_PWRMGT_CNTL__GNB_SLOW__SHIFT 0x2
-#define CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK 0x8
-#define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3
-#define CNB_PWRMGT_CNTL__DPM_ENABLED_MASK 0x10
-#define CNB_PWRMGT_CNTL__DPM_ENABLED__SHIFT 0x4
-#define CNB_PWRMGT_CNTL__SPARE_MASK 0xffffffe0
-#define CNB_PWRMGT_CNTL__SPARE__SHIFT 0x5
-#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK 0x1
-#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF__SHIFT 0x0
-#define SCLK_PWRMGT_CNTL__SCLK_LOW_D1_MASK 0x2
-#define SCLK_PWRMGT_CNTL__SCLK_LOW_D1__SHIFT 0x1
-#define SCLK_PWRMGT_CNTL__DYN_PWR_DOWN_EN_MASK 0x4
-#define SCLK_PWRMGT_CNTL__DYN_PWR_DOWN_EN__SHIFT 0x2
-#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK 0x10
-#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT__SHIFT 0x4
-#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK 0x20
-#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT__SHIFT 0x5
-#define SCLK_PWRMGT_CNTL__RESERVED_0_MASK 0x40
-#define SCLK_PWRMGT_CNTL__RESERVED_0__SHIFT 0x6
-#define SCLK_PWRMGT_CNTL__DYN_GFX_CLK_OFF_EN_MASK 0x80
-#define SCLK_PWRMGT_CNTL__DYN_GFX_CLK_OFF_EN__SHIFT 0x7
-#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_ON_MASK 0x100
-#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_ON__SHIFT 0x8
-#define SCLK_PWRMGT_CNTL__GFX_CLK_REQUEST_OFF_MASK 0x200
-#define SCLK_PWRMGT_CNTL__GFX_CLK_REQUEST_OFF__SHIFT 0x9
-#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_OFF_MASK 0x400
-#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_OFF__SHIFT 0xa
-#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D1_MASK 0x800
-#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D1__SHIFT 0xb
-#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D2_MASK 0x1000
-#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D2__SHIFT 0xc
-#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D3_MASK 0x2000
-#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D3__SHIFT 0xd
-#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN_MASK 0x4000
-#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN__SHIFT 0xe
-#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP_MASK 0x8000
-#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP__SHIFT 0xf
-#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER_MASK 0x1f0000
-#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER__SHIFT 0x10
-#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK 0x200000
-#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN__SHIFT 0x15
-#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_CNTL_MASK 0x400000
-#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_CNTL__SHIFT 0x16
-#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_EN_MASK 0x800000
-#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_EN__SHIFT 0x17
-#define SCLK_PWRMGT_CNTL__RESERVED_3_MASK 0x1000000
-#define SCLK_PWRMGT_CNTL__RESERVED_3__SHIFT 0x18
-#define SCLK_PWRMGT_CNTL__VOLTAGE_UPDATE_EN_MASK 0x2000000
-#define SCLK_PWRMGT_CNTL__VOLTAGE_UPDATE_EN__SHIFT 0x19
-#define SCLK_PWRMGT_CNTL__FORCE_PM0_INTERRUPT_MASK 0x10000000
-#define SCLK_PWRMGT_CNTL__FORCE_PM0_INTERRUPT__SHIFT 0x1c
-#define SCLK_PWRMGT_CNTL__FORCE_PM1_INTERRUPT_MASK 0x20000000
-#define SCLK_PWRMGT_CNTL__FORCE_PM1_INTERRUPT__SHIFT 0x1d
-#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_EN_MASK 0x40000000
-#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_EN__SHIFT 0x1e
-#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_MODE_MASK 0x80000000
-#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_MODE__SHIFT 0x1f
-#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE_MASK 0xf
-#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE__SHIFT 0x0
-#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_MASK 0xf0
-#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 0x4
-#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK 0xf00
-#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT 0x8
-#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX_MASK 0xf000
-#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX__SHIFT 0xc
-#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK 0x1f0000
-#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT 0x10
-#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX_MASK 0x3e00000
-#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX__SHIFT 0x15
-#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX_MASK 0x1c000000
-#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX__SHIFT 0x1a
-#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX_MASK 0xe0000000
-#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX__SHIFT 0x1d
-#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
-#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
-#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
-#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
-#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
-#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
-#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
-#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
-#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
-#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
-#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
-#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
-#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
-#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
-#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
-#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
-#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
-#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
-#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
-#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
-#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
-#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
-#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
-#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
-#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
-#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
-#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
-#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
-#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
-#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
-#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
-#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
-#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
-#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
-#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
-#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
-#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
-#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
-#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
-#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
-#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
-#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
-#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
-#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
-#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
-#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
-#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
-#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
-#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
-#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
-#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
-#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
-#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
-#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
-#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
-#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
-#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
-#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
-#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
-#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
-#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
-#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
-#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
-#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
-#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
-#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
-#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
-#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
-#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
-#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
-#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
-#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
-#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
-#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
-#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
-#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
-#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
-#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
-#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
-#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
-#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
-#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
-#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
-#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
-#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
-#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
-#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
-#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
-#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
-#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
-#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
-#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
-#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
-#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
-#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
-#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
-#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
-#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
-#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
-#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
-#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
-#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
-#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
-#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
-#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
-#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
-#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
-#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
-#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
-#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
-#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
-#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
-#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
-#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
-#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
-#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
-#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
-#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
-#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
-#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
-#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
-#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
-#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
-#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
-#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
-#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
-#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
-#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
-#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
-#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
-#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
-#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
-#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
-#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
-#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
-#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
-#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
-#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
-#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
-#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
-#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
-#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
-#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
-#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
-#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
-#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
-#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
-#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
-#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
-#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
-#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
-#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
-#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
-#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
-#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
-#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
-#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
-#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
-#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
-#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
-#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
-#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
-#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
-#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
-#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
-#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
-#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
-#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
-#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
-#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
-#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
-#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
-#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
-#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
-#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
-#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
-#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
-#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
-#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
-#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
-#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
-#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
-#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
-#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
-#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
-#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
-#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
-#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
-#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
-#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
-#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
-#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
-#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
-#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
-#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
-#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
-#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
-#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
-#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
-#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
-#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
-#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
-#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
-#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
-#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
-#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
-#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
-#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
-#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
-#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
-#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
-#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
-#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
-#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
-#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
-#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
-#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
-#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
-#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
-#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
-#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
-#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
-#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
-#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
-#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
-#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
-#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
-#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
-#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
-#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
-#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
-#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
-#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
-#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
-#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
-#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
-#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
-#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
-#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
-#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
-#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
-#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
-#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
-#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
-#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
-#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
-#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
-#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
-#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
-#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
-#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
-#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
-#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
-#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
-#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
-#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
-#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
-#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
-#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
-#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
-#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
-#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
-#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
-#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
-#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
-#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
-#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
-#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
-#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
-#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
-#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
-#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
-#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
-#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
-#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
-#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
-#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
-#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
-#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
-#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
-#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
-#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
-#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
-#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
-#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
-#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
-#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
-#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
-#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
-#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
-#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
-#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
-#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
-#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
-#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
-#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
-#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
-#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
-#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
-#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
-#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
-#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
-#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
-#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
-#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
-#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
-#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
-#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
-#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
-#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
-#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
-#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
-#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
-#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
-#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
-#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
-#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
-#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
-#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
-#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
-#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
-#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
-#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
-#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
-#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
-#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
-#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
-#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
-#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
-#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
-#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
-#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
-#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
-#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
-#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
-#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
-#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
-#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
-#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
-#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
-#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
-#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
-#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
-#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
-#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
-#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
-#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
-#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
-#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
-#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
-#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
-#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
-#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
-#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
-#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
-#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
-#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
-#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
-#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
-#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
-#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
-#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
-#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
-#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
-#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
-#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
-#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
-#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
-#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
-#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
-#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
-#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
-#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
-#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
-#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
-#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
-#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
-#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
-#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
-#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
-#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
-#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
-#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
-#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
-#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
-#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
-#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
-#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
-#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
-#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
-#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
-#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
-#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
-#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
-#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
-#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
-#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
-#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
-#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
-#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
-#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
-#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
-#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
-#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
-#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
-#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
-#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
-#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
-#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
-#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
-#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
-#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
-#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
-#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
-#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
-#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
-#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
-#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
-#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
-#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
-#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
-#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
-#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
-#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
-#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
-#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
-#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
-#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
-#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
-#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
-#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
-#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
-#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
-#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
-#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
-#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
-#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
-#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
-#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
-#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
-#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
-#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
-#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
-#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
-#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
-#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
-#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
-#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
-#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
-#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
-#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
-#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
-#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
-#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
-#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
-#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
-#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
-#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
-#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
-#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
-#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
-#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
-#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
-#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
-#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
-#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
-#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
-#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
-#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
-#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
-#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
-#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
-#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
-#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
-#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
-#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
-#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
-#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
-#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
-#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
-#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
-#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
-#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
-#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
-#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
-#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
-#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
-#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
-#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
-#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
-#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
-#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
-#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
-#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
-#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
-#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
-#define PLL_TEST_CNTL__TST_SRC_SEL_MASK 0xf
-#define PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0
-#define PLL_TEST_CNTL__TST_REF_SEL_MASK 0xf0
-#define PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x4
-#define PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x7f00
-#define PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0x8
-#define PLL_TEST_CNTL__TST_RESET_MASK 0x8000
-#define PLL_TEST_CNTL__TST_RESET__SHIFT 0xf
-#define PLL_TEST_CNTL__TEST_COUNT_MASK 0xfffe0000
-#define PLL_TEST_CNTL__TEST_COUNT__SHIFT 0x11
-#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_MASK 0xffff
-#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT 0x0
-#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT_MASK 0xf0000
-#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT 0x10
-#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK 0x3
-#define CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT 0x0
-#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT_MASK 0x3fff0
-#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT__SHIFT 0x4
-#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT_MASK 0x700000
-#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT__SHIFT 0x14
-#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK 0x3000000
-#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT 0x18
-#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE_MASK 0x10000000
-#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE__SHIFT 0x1c
-#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION_MASK 0xffffffff
-#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION__SHIFT 0x0
-#define CG_ACPI_CNTL__SCLK_ACPI_DIV_MASK 0x7f
-#define CG_ACPI_CNTL__SCLK_ACPI_DIV__SHIFT 0x0
-#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP_MASK 0x80
-#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP__SHIFT 0x7
-#define SCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7
-#define SCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0
-#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8
-#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3
-#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0
-#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4
-#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK_MASK 0x10000
-#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK__SHIFT 0x10
-#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK_MASK 0x20000
-#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK__SHIFT 0x11
-#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK_MASK 0x40000
-#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK__SHIFT 0x12
-#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK_MASK 0x80000
-#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK__SHIFT 0x13
-#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK_MASK 0x100000
-#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK__SHIFT 0x14
-#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK_MASK 0x200000
-#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK__SHIFT 0x15
-#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK_MASK 0x400000
-#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK__SHIFT 0x16
-#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK_MASK 0x800000
-#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK__SHIFT 0x17
-#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK_MASK 0x1000000
-#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK__SHIFT 0x18
-#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK_MASK 0x2000000
-#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK__SHIFT 0x19
-#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE_MASK 0x4000000
-#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE__SHIFT 0x1a
-#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE_MASK 0x8000000
-#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE__SHIFT 0x1b
-#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK_MASK 0x10000000
-#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK__SHIFT 0x1c
-#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK_MASK 0x20000000
-#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK__SHIFT 0x1d
-#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK_MASK 0x40000000
-#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK__SHIFT 0x1e
-#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000
-#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f
-#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK_MASK 0x1
-#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK__SHIFT 0x0
-#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK_MASK 0x2
-#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK__SHIFT 0x1
-#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK_MASK 0x4
-#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK__SHIFT 0x2
-#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK_MASK 0x8
-#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK__SHIFT 0x3
-#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK_MASK 0x10
-#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK__SHIFT 0x4
-#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK_MASK 0x40
-#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK__SHIFT 0x6
-#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK_MASK 0x80
-#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK__SHIFT 0x7
-#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK_MASK 0x100
-#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK__SHIFT 0x8
-#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK_MASK 0x200
-#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK__SHIFT 0x9
-#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK_MASK 0x400
-#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK__SHIFT 0xa
-#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK_MASK 0x800
-#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK__SHIFT 0xb
-#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK_MASK 0x1000
-#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK__SHIFT 0xc
-#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK_MASK 0x2000
-#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK__SHIFT 0xd
-#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x4000
-#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0xe
-#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID_MASK 0xe00000
-#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID__SHIFT 0x15
-#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION_MASK 0xff000000
-#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION__SHIFT 0x18
-#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK_MASK 0x1
-#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK__SHIFT 0x0
-#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK_MASK 0x2
-#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK__SHIFT 0x1
-#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK_MASK 0x4
-#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK__SHIFT 0x2
-#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK_MASK 0x8
-#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK__SHIFT 0x3
-#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK_MASK 0x10
-#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK__SHIFT 0x4
-#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK_MASK 0x20
-#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK__SHIFT 0x5
-#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK_MASK 0x40
-#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK__SHIFT 0x6
-#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK_MASK 0x80
-#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK__SHIFT 0x7
-#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK_MASK 0x100
-#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK__SHIFT 0x8
-#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK_MASK 0x200
-#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK__SHIFT 0x9
-#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK_MASK 0x400
-#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK__SHIFT 0xa
-#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK_MASK 0x800
-#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK__SHIFT 0xb
-#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK_MASK 0x1000
-#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK__SHIFT 0xc
-#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK_MASK 0x2000
-#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK__SHIFT 0xd
-#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK_MASK 0x4000
-#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK__SHIFT 0xe
-#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK_MASK 0x8000
-#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK__SHIFT 0xf
-#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID_MASK 0x7
-#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID__SHIFT 0x0
-#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID_MASK 0x38
-#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID__SHIFT 0x3
-#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE_MASK 0x10000
-#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE__SHIFT 0x10
-#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID_MASK 0xe0000
-#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID__SHIFT 0x11
-#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID_MASK 0x700000
-#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID__SHIFT 0x14
-#define LCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7
-#define LCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0
-#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8
-#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3
-#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0
-#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4
-#define LCLK_DEEP_SLEEP_CNTL__RESERVED_MASK 0x7fff0000
-#define LCLK_DEEP_SLEEP_CNTL__RESERVED__SHIFT 0x10
-#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000
-#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f
-#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK_MASK 0x1
-#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK__SHIFT 0x0
-#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK_MASK 0x2
-#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK__SHIFT 0x1
-#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK_MASK 0x4
-#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK__SHIFT 0x2
-#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3_MASK 0x8
-#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3__SHIFT 0x3
-#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK_MASK 0x10
-#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK__SHIFT 0x4
-#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK_MASK 0x20
-#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK__SHIFT 0x5
-#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK_MASK 0x40
-#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK__SHIFT 0x6
-#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK_MASK 0x80
-#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK__SHIFT 0x7
-#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK_MASK 0x100
-#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK__SHIFT 0x8
-#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK_MASK 0x200
-#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK__SHIFT 0x9
-#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK_MASK 0x400
-#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK__SHIFT 0xa
-#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK_MASK 0x800
-#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK__SHIFT 0xb
-#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK_MASK 0x1000
-#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK__SHIFT 0xc
-#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK_MASK 0x2000
-#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK__SHIFT 0xd
-#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK_MASK 0x4000
-#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK__SHIFT 0xe
-#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK_MASK 0x8000
-#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK__SHIFT 0xf
-#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK_MASK 0x10000
-#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK__SHIFT 0x10
-#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK_MASK 0x20000
-#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK__SHIFT 0x11
-#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK_MASK 0x40000
-#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK__SHIFT 0x12
-#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK_MASK 0x80000
-#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK__SHIFT 0x13
-#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK_MASK 0x100000
-#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK__SHIFT 0x14
-#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x200000
-#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0x15
-#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_MASK 0xffc00000
-#define LCLK_DEEP_SLEEP_CNTL2__RESERVED__SHIFT 0x16
-#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX_MASK 0xf
-#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX__SHIFT 0x0
-#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX_MASK 0xf0
-#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX__SHIFT 0x4
-#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX_MASK 0xf00
-#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX__SHIFT 0x8
-#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX_MASK 0xf000
-#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX__SHIFT 0xc
-#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX_MASK 0xf0000
-#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX__SHIFT 0x10
-#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX_MASK 0xf00000
-#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX__SHIFT 0x14
-#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0xf000000
-#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18
-#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000
-#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x1c
-#define CG_ULV_PARAMETER__ULV_THRESHOLD_MASK 0xffff
-#define CG_ULV_PARAMETER__ULV_THRESHOLD__SHIFT 0x0
-#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT_MASK 0xf0000
-#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT__SHIFT 0x10
-#define SCLK_MIN_DIV__FRACV_MASK 0xfff
-#define SCLK_MIN_DIV__FRACV__SHIFT 0x0
-#define SCLK_MIN_DIV__INTV_MASK 0x7f000
-#define SCLK_MIN_DIV__INTV__SHIFT 0xc
-#define LCAC_SX0_CNTL__SX0_ENABLE_MASK 0x1
-#define LCAC_SX0_CNTL__SX0_ENABLE__SHIFT 0x0
-#define LCAC_SX0_CNTL__SX0_THRESHOLD_MASK 0x1fffe
-#define LCAC_SX0_CNTL__SX0_THRESHOLD__SHIFT 0x1
-#define LCAC_SX0_CNTL__SX0_BLOCK_ID_MASK 0x3e0000
-#define LCAC_SX0_CNTL__SX0_BLOCK_ID__SHIFT 0x11
-#define LCAC_SX0_CNTL__SX0_SIGNAL_ID_MASK 0x3fc00000
-#define LCAC_SX0_CNTL__SX0_SIGNAL_ID__SHIFT 0x16
-#define LCAC_SX0_OVR_SEL__SX0_OVR_SEL_MASK 0xffffffff
-#define LCAC_SX0_OVR_SEL__SX0_OVR_SEL__SHIFT 0x0
-#define LCAC_SX0_OVR_VAL__SX0_OVR_VAL_MASK 0xffffffff
-#define LCAC_SX0_OVR_VAL__SX0_OVR_VAL__SHIFT 0x0
-#define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x1
-#define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x0
-#define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x1fffe
-#define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x1
-#define LCAC_MC0_CNTL__MC0_BLOCK_ID_MASK 0x3e0000
-#define LCAC_MC0_CNTL__MC0_BLOCK_ID__SHIFT 0x11
-#define LCAC_MC0_CNTL__MC0_SIGNAL_ID_MASK 0x3fc00000
-#define LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT 0x16
-#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffff
-#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x0
-#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffff
-#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x0
-#define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x1
-#define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x0
-#define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x1fffe
-#define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x1
-#define LCAC_MC1_CNTL__MC1_BLOCK_ID_MASK 0x3e0000
-#define LCAC_MC1_CNTL__MC1_BLOCK_ID__SHIFT 0x11
-#define LCAC_MC1_CNTL__MC1_SIGNAL_ID_MASK 0x3fc00000
-#define LCAC_MC1_CNTL__MC1_SIGNAL_ID__SHIFT 0x16
-#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffff
-#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x0
-#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffff
-#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x0
-#define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x1
-#define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x0
-#define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x1fffe
-#define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x1
-#define LCAC_MC2_CNTL__MC2_BLOCK_ID_MASK 0x3e0000
-#define LCAC_MC2_CNTL__MC2_BLOCK_ID__SHIFT 0x11
-#define LCAC_MC2_CNTL__MC2_SIGNAL_ID_MASK 0x3fc00000
-#define LCAC_MC2_CNTL__MC2_SIGNAL_ID__SHIFT 0x16
-#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffff
-#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x0
-#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffff
-#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x0
-#define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x1
-#define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x0
-#define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x1fffe
-#define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x1
-#define LCAC_MC3_CNTL__MC3_BLOCK_ID_MASK 0x3e0000
-#define LCAC_MC3_CNTL__MC3_BLOCK_ID__SHIFT 0x11
-#define LCAC_MC3_CNTL__MC3_SIGNAL_ID_MASK 0x3fc00000
-#define LCAC_MC3_CNTL__MC3_SIGNAL_ID__SHIFT 0x16
-#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffff
-#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x0
-#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffff
-#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x0
-#define LCAC_CPL_CNTL__CPL_ENABLE_MASK 0x1
-#define LCAC_CPL_CNTL__CPL_ENABLE__SHIFT 0x0
-#define LCAC_CPL_CNTL__CPL_THRESHOLD_MASK 0x1fffe
-#define LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT 0x1
-#define LCAC_CPL_CNTL__CPL_BLOCK_ID_MASK 0x3e0000
-#define LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT 0x11
-#define LCAC_CPL_CNTL__CPL_SIGNAL_ID_MASK 0x3fc00000
-#define LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT 0x16
-#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL_MASK 0xffffffff
-#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL__SHIFT 0x0
-#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL_MASK 0xffffffff
-#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL__SHIFT 0x0
-#define ROM_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
-#define ROM_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
-#define ROM_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
-#define ROM_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
-#define ROM_CNTL__SCK_OVERWRITE_MASK 0x2
-#define ROM_CNTL__SCK_OVERWRITE__SHIFT 0x1
-#define ROM_CNTL__CLOCK_GATING_EN_MASK 0x4
-#define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x2
-#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME_MASK 0xff00
-#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME__SHIFT 0x8
-#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME_MASK 0xff0000
-#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME__SHIFT 0x10
-#define ROM_CNTL__SCK_PRESCALE_REFCLK_MASK 0xf000000
-#define ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT 0x18
-#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK_MASK 0xf0000000
-#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK__SHIFT 0x1c
-#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK 0xffffff
-#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT 0x0
-#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK 0x1000000
-#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT 0x18
-#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK 0x2000000
-#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT 0x19
-#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK 0xc000000
-#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT 0x1a
-#define ROM_STATUS__ROM_BUSY_MASK 0x1
-#define ROM_STATUS__ROM_BUSY__SHIFT 0x0
-#define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0xf
-#define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0
-#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0xff0
-#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
-#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000
-#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
-#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000
-#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
-#define ROM_INDEX__ROM_INDEX_MASK 0xffffff
-#define ROM_INDEX__ROM_INDEX__SHIFT 0x0
-#define ROM_DATA__ROM_DATA_MASK 0xffffffff
-#define ROM_DATA__ROM_DATA__SHIFT 0x0
-#define ROM_START__ROM_START_MASK 0xffffff
-#define ROM_START__ROM_START__SHIFT 0x0
-#define ROM_SW_CNTL__DATA_SIZE_MASK 0xffff
-#define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0
-#define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x30000
-#define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x10
-#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x40000
-#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x12
-#define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x1
-#define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0
-#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0xff
-#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0
-#define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xffffff00
-#define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x8
-#define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0
-#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xffffffff
-#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0
-
-#endif /* SMU_7_1_0_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_enum.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_enum.h
deleted file mode 100644
index c1a7aba19..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_enum.h
+++ /dev/null
@@ -1,1205 +0,0 @@
-/*
- * SMU_7_1_1 Register documentation
- *
- * Copyright (C) 2014 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef SMU_7_1_1_ENUM_H
-#define SMU_7_1_1_ENUM_H
-
-#define CG_SRBM_START_ADDR 0x600
-#define CG_SRBM_END_ADDR 0x8ff
-#define RCU_CCF_DWORDS0 0x80
-#define RCU_CCF_BITS0 0x1000
-#define RCU_CCF_DWORDS1 0x0
-#define RCU_CCF_BITS1 0x0
-#define RCU_SAM_BYTES 0x0
-#define RCU_SAM_RTL_BYTES 0x0
-#define RCU_SMU_BYTES 0x0
-#define RCU_SMU_RTL_BYTES 0x0
-#define SFP_CHAIN_ADDR 0x0
-#define SFP_BYTES 0x80
-#define SFP_SADR 0x180
-#define SFP_EADR 0x1ff
-#define SAMU_KEY_CHAIN_ADR 0x0
-#define SAMU_KEY_SADR 0x0
-#define SAMU_KEY_EADR 0x0
-#define SMU_KEY_CHAIN_ADR 0x0
-#define SMU_KEY_SADR 0x0
-#define SMU_KEY_EADR 0x0
-#define SMC_MSG_TEST 0x1
-#define SMC_MSG_PHY_LN_OFF 0x2
-#define SMC_MSG_PHY_LN_ON 0x3
-#define SMC_MSG_DDI_PHY_OFF 0x4
-#define SMC_MSG_DDI_PHY_ON 0x5
-#define SMC_MSG_CASCADE_PLL_OFF 0x6
-#define SMC_MSG_CASCADE_PLL_ON 0x7
-#define SMC_MSG_PWR_OFF_x16 0x8
-#define SMC_MSG_CONFIG_LCLK_DPM 0x9
-#define SMC_MSG_FLUSH_DATA_CACHE 0xa
-#define SMC_MSG_FLUSH_INSTRUCTION_CACHE 0xb
-#define SMC_MSG_CONFIG_VPC_ACCUMULATOR 0xc
-#define SMC_MSG_CONFIG_BAPM 0xd
-#define SMC_MSG_CONFIG_TDC_LIMIT 0xe
-#define SMC_MSG_CONFIG_LPMx 0xf
-#define SMC_MSG_CONFIG_HTC_LIMIT 0x10
-#define SMC_MSG_CONFIG_THERMAL_CNTL 0x11
-#define SMC_MSG_CONFIG_VOLTAGE_CNTL 0x12
-#define SMC_MSG_CONFIG_TDP_CNTL 0x13
-#define SMC_MSG_EN_PM_CNTL 0x14
-#define SMC_MSG_DIS_PM_CNTL 0x15
-#define SMC_MSG_CONFIG_NBDPM 0x16
-#define SMC_MSG_CONFIG_LOADLINE 0x17
-#define SMC_MSG_ADJUST_LOADLINE 0x18
-#define SMC_MSG_RESET 0x20
-#define SMC_MSG_VOLTAGE 0x25
-#define SMC_VERSION_MAJOR 0x7
-#define SMC_VERSION_MINOR 0x0
-#define SMC_HEADER_SIZE 0x40
-#define ROM_SIGNATURE 0xaa55
-typedef enum SurfaceEndian {
- ENDIAN_NONE = 0x0,
- ENDIAN_8IN16 = 0x1,
- ENDIAN_8IN32 = 0x2,
- ENDIAN_8IN64 = 0x3,
-} SurfaceEndian;
-typedef enum ArrayMode {
- ARRAY_LINEAR_GENERAL = 0x0,
- ARRAY_LINEAR_ALIGNED = 0x1,
- ARRAY_1D_TILED_THIN1 = 0x2,
- ARRAY_1D_TILED_THICK = 0x3,
- ARRAY_2D_TILED_THIN1 = 0x4,
- ARRAY_PRT_TILED_THIN1 = 0x5,
- ARRAY_PRT_2D_TILED_THIN1 = 0x6,
- ARRAY_2D_TILED_THICK = 0x7,
- ARRAY_2D_TILED_XTHICK = 0x8,
- ARRAY_PRT_TILED_THICK = 0x9,
- ARRAY_PRT_2D_TILED_THICK = 0xa,
- ARRAY_PRT_3D_TILED_THIN1 = 0xb,
- ARRAY_3D_TILED_THIN1 = 0xc,
- ARRAY_3D_TILED_THICK = 0xd,
- ARRAY_3D_TILED_XTHICK = 0xe,
- ARRAY_PRT_3D_TILED_THICK = 0xf,
-} ArrayMode;
-typedef enum PipeTiling {
- CONFIG_1_PIPE = 0x0,
- CONFIG_2_PIPE = 0x1,
- CONFIG_4_PIPE = 0x2,
- CONFIG_8_PIPE = 0x3,
-} PipeTiling;
-typedef enum BankTiling {
- CONFIG_4_BANK = 0x0,
- CONFIG_8_BANK = 0x1,
-} BankTiling;
-typedef enum GroupInterleave {
- CONFIG_256B_GROUP = 0x0,
- CONFIG_512B_GROUP = 0x1,
-} GroupInterleave;
-typedef enum RowTiling {
- CONFIG_1KB_ROW = 0x0,
- CONFIG_2KB_ROW = 0x1,
- CONFIG_4KB_ROW = 0x2,
- CONFIG_8KB_ROW = 0x3,
- CONFIG_1KB_ROW_OPT = 0x4,
- CONFIG_2KB_ROW_OPT = 0x5,
- CONFIG_4KB_ROW_OPT = 0x6,
- CONFIG_8KB_ROW_OPT = 0x7,
-} RowTiling;
-typedef enum BankSwapBytes {
- CONFIG_128B_SWAPS = 0x0,
- CONFIG_256B_SWAPS = 0x1,
- CONFIG_512B_SWAPS = 0x2,
- CONFIG_1KB_SWAPS = 0x3,
-} BankSwapBytes;
-typedef enum SampleSplitBytes {
- CONFIG_1KB_SPLIT = 0x0,
- CONFIG_2KB_SPLIT = 0x1,
- CONFIG_4KB_SPLIT = 0x2,
- CONFIG_8KB_SPLIT = 0x3,
-} SampleSplitBytes;
-typedef enum NumPipes {
- ADDR_CONFIG_1_PIPE = 0x0,
- ADDR_CONFIG_2_PIPE = 0x1,
- ADDR_CONFIG_4_PIPE = 0x2,
- ADDR_CONFIG_8_PIPE = 0x3,
-} NumPipes;
-typedef enum PipeInterleaveSize {
- ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
- ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
-} PipeInterleaveSize;
-typedef enum BankInterleaveSize {
- ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
- ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
- ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
- ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
-} BankInterleaveSize;
-typedef enum NumShaderEngines {
- ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
- ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
-} NumShaderEngines;
-typedef enum ShaderEngineTileSize {
- ADDR_CONFIG_SE_TILE_16 = 0x0,
- ADDR_CONFIG_SE_TILE_32 = 0x1,
-} ShaderEngineTileSize;
-typedef enum NumGPUs {
- ADDR_CONFIG_1_GPU = 0x0,
- ADDR_CONFIG_2_GPU = 0x1,
- ADDR_CONFIG_4_GPU = 0x2,
-} NumGPUs;
-typedef enum MultiGPUTileSize {
- ADDR_CONFIG_GPU_TILE_16 = 0x0,
- ADDR_CONFIG_GPU_TILE_32 = 0x1,
- ADDR_CONFIG_GPU_TILE_64 = 0x2,
- ADDR_CONFIG_GPU_TILE_128 = 0x3,
-} MultiGPUTileSize;
-typedef enum RowSize {
- ADDR_CONFIG_1KB_ROW = 0x0,
- ADDR_CONFIG_2KB_ROW = 0x1,
- ADDR_CONFIG_4KB_ROW = 0x2,
-} RowSize;
-typedef enum NumLowerPipes {
- ADDR_CONFIG_1_LOWER_PIPES = 0x0,
- ADDR_CONFIG_2_LOWER_PIPES = 0x1,
-} NumLowerPipes;
-typedef enum DebugBlockId {
- DBG_CLIENT_BLKID_RESERVED = 0x0,
- DBG_CLIENT_BLKID_dbg = 0x1,
- DBG_CLIENT_BLKID_uvdu_0 = 0x2,
- DBG_CLIENT_BLKID_uvdu_1 = 0x3,
- DBG_CLIENT_BLKID_uvdu_2 = 0x4,
- DBG_CLIENT_BLKID_uvdu_3 = 0x5,
- DBG_CLIENT_BLKID_uvdu_4 = 0x6,
- DBG_CLIENT_BLKID_uvdu_5 = 0x7,
- DBG_CLIENT_BLKID_uvdu_6 = 0x8,
- DBG_CLIENT_BLKID_uvdb_0 = 0x9,
- DBG_CLIENT_BLKID_uvdc_0 = 0xa,
- DBG_CLIENT_BLKID_uvdc_1 = 0xb,
- DBG_CLIENT_BLKID_uvdf_0 = 0xc,
- DBG_CLIENT_BLKID_uvdf_1 = 0xd,
- DBG_CLIENT_BLKID_uvdm_0 = 0xe,
- DBG_CLIENT_BLKID_uvdm_1 = 0xf,
- DBG_CLIENT_BLKID_uvdm_2 = 0x10,
- DBG_CLIENT_BLKID_uvdm_3 = 0x11,
- DBG_CLIENT_BLKID_vcea_0 = 0x12,
- DBG_CLIENT_BLKID_vcea_1 = 0x13,
- DBG_CLIENT_BLKID_vcea_2 = 0x14,
- DBG_CLIENT_BLKID_vcea_3 = 0x15,
- DBG_CLIENT_BLKID_vceb_0 = 0x16,
- DBG_CLIENT_BLKID_vcec_0 = 0x17,
- DBG_CLIENT_BLKID_dco = 0x18,
- DBG_CLIENT_BLKID_xdma = 0x19,
- DBG_CLIENT_BLKID_dci_pg = 0x1a,
- DBG_CLIENT_BLKID_smu_0 = 0x1b,
- DBG_CLIENT_BLKID_smu_1 = 0x1c,
- DBG_CLIENT_BLKID_smu_2 = 0x1d,
- DBG_CLIENT_BLKID_gck = 0x1e,
- DBG_CLIENT_BLKID_tmonw0 = 0x1f,
- DBG_CLIENT_BLKID_tmonw1 = 0x20,
- DBG_CLIENT_BLKID_grbm = 0x21,
- DBG_CLIENT_BLKID_rlc = 0x22,
- DBG_CLIENT_BLKID_ds0 = 0x23,
- DBG_CLIENT_BLKID_cpg_0 = 0x24,
- DBG_CLIENT_BLKID_cpg_1 = 0x25,
- DBG_CLIENT_BLKID_cpc_0 = 0x26,
- DBG_CLIENT_BLKID_cpc_1 = 0x27,
- DBG_CLIENT_BLKID_cpf_0 = 0x28,
- DBG_CLIENT_BLKID_cpf_1 = 0x29,
- DBG_CLIENT_BLKID_scf0 = 0x2a,
- DBG_CLIENT_BLKID_scf1 = 0x2b,
- DBG_CLIENT_BLKID_scf2 = 0x2c,
- DBG_CLIENT_BLKID_scf3 = 0x2d,
- DBG_CLIENT_BLKID_pc0 = 0x2e,
- DBG_CLIENT_BLKID_pc1 = 0x2f,
- DBG_CLIENT_BLKID_pc2 = 0x30,
- DBG_CLIENT_BLKID_pc3 = 0x31,
- DBG_CLIENT_BLKID_vgt0 = 0x32,
- DBG_CLIENT_BLKID_vgt1 = 0x33,
- DBG_CLIENT_BLKID_vgt2 = 0x34,
- DBG_CLIENT_BLKID_vgt3 = 0x35,
- DBG_CLIENT_BLKID_sx00 = 0x36,
- DBG_CLIENT_BLKID_sx10 = 0x37,
- DBG_CLIENT_BLKID_sx20 = 0x38,
- DBG_CLIENT_BLKID_sx30 = 0x39,
- DBG_CLIENT_BLKID_cb001 = 0x3a,
- DBG_CLIENT_BLKID_cb200 = 0x3b,
- DBG_CLIENT_BLKID_cb201 = 0x3c,
- DBG_CLIENT_BLKID_cbr0 = 0x3d,
- DBG_CLIENT_BLKID_cb000 = 0x3e,
- DBG_CLIENT_BLKID_cb101 = 0x3f,
- DBG_CLIENT_BLKID_cb300 = 0x40,
- DBG_CLIENT_BLKID_cb301 = 0x41,
- DBG_CLIENT_BLKID_cbr1 = 0x42,
- DBG_CLIENT_BLKID_cb100 = 0x43,
- DBG_CLIENT_BLKID_ia0 = 0x44,
- DBG_CLIENT_BLKID_ia1 = 0x45,
- DBG_CLIENT_BLKID_bci0 = 0x46,
- DBG_CLIENT_BLKID_bci1 = 0x47,
- DBG_CLIENT_BLKID_bci2 = 0x48,
- DBG_CLIENT_BLKID_bci3 = 0x49,
- DBG_CLIENT_BLKID_pa0 = 0x4a,
- DBG_CLIENT_BLKID_pa1 = 0x4b,
- DBG_CLIENT_BLKID_spim0 = 0x4c,
- DBG_CLIENT_BLKID_spim1 = 0x4d,
- DBG_CLIENT_BLKID_spim2 = 0x4e,
- DBG_CLIENT_BLKID_spim3 = 0x4f,
- DBG_CLIENT_BLKID_sdma = 0x50,
- DBG_CLIENT_BLKID_ih = 0x51,
- DBG_CLIENT_BLKID_sem = 0x52,
- DBG_CLIENT_BLKID_srbm = 0x53,
- DBG_CLIENT_BLKID_hdp = 0x54,
- DBG_CLIENT_BLKID_acp_0 = 0x55,
- DBG_CLIENT_BLKID_acp_1 = 0x56,
- DBG_CLIENT_BLKID_sam = 0x57,
- DBG_CLIENT_BLKID_mcc0 = 0x58,
- DBG_CLIENT_BLKID_mcc1 = 0x59,
- DBG_CLIENT_BLKID_mcc2 = 0x5a,
- DBG_CLIENT_BLKID_mcc3 = 0x5b,
- DBG_CLIENT_BLKID_mcd0 = 0x5c,
- DBG_CLIENT_BLKID_mcd1 = 0x5d,
- DBG_CLIENT_BLKID_mcd2 = 0x5e,
- DBG_CLIENT_BLKID_mcd3 = 0x5f,
- DBG_CLIENT_BLKID_mcb = 0x60,
- DBG_CLIENT_BLKID_vmc = 0x61,
- DBG_CLIENT_BLKID_gmcon = 0x62,
- DBG_CLIENT_BLKID_gdc_0 = 0x63,
- DBG_CLIENT_BLKID_gdc_1 = 0x64,
- DBG_CLIENT_BLKID_gdc_2 = 0x65,
- DBG_CLIENT_BLKID_gdc_3 = 0x66,
- DBG_CLIENT_BLKID_gdc_4 = 0x67,
- DBG_CLIENT_BLKID_gdc_5 = 0x68,
- DBG_CLIENT_BLKID_gdc_6 = 0x69,
- DBG_CLIENT_BLKID_gdc_7 = 0x6a,
- DBG_CLIENT_BLKID_gdc_8 = 0x6b,
- DBG_CLIENT_BLKID_gdc_9 = 0x6c,
- DBG_CLIENT_BLKID_gdc_10 = 0x6d,
- DBG_CLIENT_BLKID_gdc_11 = 0x6e,
- DBG_CLIENT_BLKID_gdc_12 = 0x6f,
- DBG_CLIENT_BLKID_gdc_13 = 0x70,
- DBG_CLIENT_BLKID_gdc_14 = 0x71,
- DBG_CLIENT_BLKID_gdc_15 = 0x72,
- DBG_CLIENT_BLKID_gdc_16 = 0x73,
- DBG_CLIENT_BLKID_gdc_17 = 0x74,
- DBG_CLIENT_BLKID_gdc_18 = 0x75,
- DBG_CLIENT_BLKID_gdc_19 = 0x76,
- DBG_CLIENT_BLKID_gdc_20 = 0x77,
- DBG_CLIENT_BLKID_gdc_21 = 0x78,
- DBG_CLIENT_BLKID_gdc_22 = 0x79,
- DBG_CLIENT_BLKID_gdc_23 = 0x7a,
- DBG_CLIENT_BLKID_gdc_24 = 0x7b,
- DBG_CLIENT_BLKID_gdc_25 = 0x7c,
- DBG_CLIENT_BLKID_gdc_26 = 0x7d,
- DBG_CLIENT_BLKID_gdc_27 = 0x7e,
- DBG_CLIENT_BLKID_gdc_28 = 0x7f,
- DBG_CLIENT_BLKID_wd = 0x80,
- DBG_CLIENT_BLKID_sdma_0 = 0x81,
- DBG_CLIENT_BLKID_sdma_1 = 0x82,
- DBG_CLIENT_BLKID_sammsp = 0x83,
- DBG_CLIENT_BLKID_dci_0 = 0x84,
- DBG_CLIENT_BLKID_dccg0_0 = 0x85,
- DBG_CLIENT_BLKID_dcfe01_0 = 0x86,
- DBG_CLIENT_BLKID_dcfe02_0 = 0x87,
- DBG_CLIENT_BLKID_dcfe03_0 = 0x88,
- DBG_CLIENT_BLKID_dccg0_1 = 0x89,
-} DebugBlockId;
-typedef enum DebugBlockId_OLD {
- DBG_BLOCK_ID_RESERVED = 0x0,
- DBG_BLOCK_ID_DBG = 0x1,
- DBG_BLOCK_ID_VMC = 0x2,
- DBG_BLOCK_ID_PDMA = 0x3,
- DBG_BLOCK_ID_CG = 0x4,
- DBG_BLOCK_ID_SRBM = 0x5,
- DBG_BLOCK_ID_GRBM = 0x6,
- DBG_BLOCK_ID_RLC = 0x7,
- DBG_BLOCK_ID_CSC = 0x8,
- DBG_BLOCK_ID_SEM = 0x9,
- DBG_BLOCK_ID_IH = 0xa,
- DBG_BLOCK_ID_SC = 0xb,
- DBG_BLOCK_ID_SQ = 0xc,
- DBG_BLOCK_ID_AVP = 0xd,
- DBG_BLOCK_ID_GMCON = 0xe,
- DBG_BLOCK_ID_SMU = 0xf,
- DBG_BLOCK_ID_DMA0 = 0x10,
- DBG_BLOCK_ID_DMA1 = 0x11,
- DBG_BLOCK_ID_SPIM = 0x12,
- DBG_BLOCK_ID_GDS = 0x13,
- DBG_BLOCK_ID_SPIS = 0x14,
- DBG_BLOCK_ID_UNUSED0 = 0x15,
- DBG_BLOCK_ID_PA0 = 0x16,
- DBG_BLOCK_ID_PA1 = 0x17,
- DBG_BLOCK_ID_CP0 = 0x18,
- DBG_BLOCK_ID_CP1 = 0x19,
- DBG_BLOCK_ID_CP2 = 0x1a,
- DBG_BLOCK_ID_UNUSED1 = 0x1b,
- DBG_BLOCK_ID_UVDU = 0x1c,
- DBG_BLOCK_ID_UVDM = 0x1d,
- DBG_BLOCK_ID_VCE = 0x1e,
- DBG_BLOCK_ID_UNUSED2 = 0x1f,
- DBG_BLOCK_ID_VGT0 = 0x20,
- DBG_BLOCK_ID_VGT1 = 0x21,
- DBG_BLOCK_ID_IA = 0x22,
- DBG_BLOCK_ID_UNUSED3 = 0x23,
- DBG_BLOCK_ID_SCT0 = 0x24,
- DBG_BLOCK_ID_SCT1 = 0x25,
- DBG_BLOCK_ID_SPM0 = 0x26,
- DBG_BLOCK_ID_SPM1 = 0x27,
- DBG_BLOCK_ID_TCAA = 0x28,
- DBG_BLOCK_ID_TCAB = 0x29,
- DBG_BLOCK_ID_TCCA = 0x2a,
- DBG_BLOCK_ID_TCCB = 0x2b,
- DBG_BLOCK_ID_MCC0 = 0x2c,
- DBG_BLOCK_ID_MCC1 = 0x2d,
- DBG_BLOCK_ID_MCC2 = 0x2e,
- DBG_BLOCK_ID_MCC3 = 0x2f,
- DBG_BLOCK_ID_SX0 = 0x30,
- DBG_BLOCK_ID_SX1 = 0x31,
- DBG_BLOCK_ID_SX2 = 0x32,
- DBG_BLOCK_ID_SX3 = 0x33,
- DBG_BLOCK_ID_UNUSED4 = 0x34,
- DBG_BLOCK_ID_UNUSED5 = 0x35,
- DBG_BLOCK_ID_UNUSED6 = 0x36,
- DBG_BLOCK_ID_UNUSED7 = 0x37,
- DBG_BLOCK_ID_PC0 = 0x38,
- DBG_BLOCK_ID_PC1 = 0x39,
- DBG_BLOCK_ID_UNUSED8 = 0x3a,
- DBG_BLOCK_ID_UNUSED9 = 0x3b,
- DBG_BLOCK_ID_UNUSED10 = 0x3c,
- DBG_BLOCK_ID_UNUSED11 = 0x3d,
- DBG_BLOCK_ID_MCB = 0x3e,
- DBG_BLOCK_ID_UNUSED12 = 0x3f,
- DBG_BLOCK_ID_SCB0 = 0x40,
- DBG_BLOCK_ID_SCB1 = 0x41,
- DBG_BLOCK_ID_UNUSED13 = 0x42,
- DBG_BLOCK_ID_UNUSED14 = 0x43,
- DBG_BLOCK_ID_SCF0 = 0x44,
- DBG_BLOCK_ID_SCF1 = 0x45,
- DBG_BLOCK_ID_UNUSED15 = 0x46,
- DBG_BLOCK_ID_UNUSED16 = 0x47,
- DBG_BLOCK_ID_BCI0 = 0x48,
- DBG_BLOCK_ID_BCI1 = 0x49,
- DBG_BLOCK_ID_BCI2 = 0x4a,
- DBG_BLOCK_ID_BCI3 = 0x4b,
- DBG_BLOCK_ID_UNUSED17 = 0x4c,
- DBG_BLOCK_ID_UNUSED18 = 0x4d,
- DBG_BLOCK_ID_UNUSED19 = 0x4e,
- DBG_BLOCK_ID_UNUSED20 = 0x4f,
- DBG_BLOCK_ID_CB00 = 0x50,
- DBG_BLOCK_ID_CB01 = 0x51,
- DBG_BLOCK_ID_CB02 = 0x52,
- DBG_BLOCK_ID_CB03 = 0x53,
- DBG_BLOCK_ID_CB04 = 0x54,
- DBG_BLOCK_ID_UNUSED21 = 0x55,
- DBG_BLOCK_ID_UNUSED22 = 0x56,
- DBG_BLOCK_ID_UNUSED23 = 0x57,
- DBG_BLOCK_ID_CB10 = 0x58,
- DBG_BLOCK_ID_CB11 = 0x59,
- DBG_BLOCK_ID_CB12 = 0x5a,
- DBG_BLOCK_ID_CB13 = 0x5b,
- DBG_BLOCK_ID_CB14 = 0x5c,
- DBG_BLOCK_ID_UNUSED24 = 0x5d,
- DBG_BLOCK_ID_UNUSED25 = 0x5e,
- DBG_BLOCK_ID_UNUSED26 = 0x5f,
- DBG_BLOCK_ID_TCP0 = 0x60,
- DBG_BLOCK_ID_TCP1 = 0x61,
- DBG_BLOCK_ID_TCP2 = 0x62,
- DBG_BLOCK_ID_TCP3 = 0x63,
- DBG_BLOCK_ID_TCP4 = 0x64,
- DBG_BLOCK_ID_TCP5 = 0x65,
- DBG_BLOCK_ID_TCP6 = 0x66,
- DBG_BLOCK_ID_TCP7 = 0x67,
- DBG_BLOCK_ID_TCP8 = 0x68,
- DBG_BLOCK_ID_TCP9 = 0x69,
- DBG_BLOCK_ID_TCP10 = 0x6a,
- DBG_BLOCK_ID_TCP11 = 0x6b,
- DBG_BLOCK_ID_TCP12 = 0x6c,
- DBG_BLOCK_ID_TCP13 = 0x6d,
- DBG_BLOCK_ID_TCP14 = 0x6e,
- DBG_BLOCK_ID_TCP15 = 0x6f,
- DBG_BLOCK_ID_TCP16 = 0x70,
- DBG_BLOCK_ID_TCP17 = 0x71,
- DBG_BLOCK_ID_TCP18 = 0x72,
- DBG_BLOCK_ID_TCP19 = 0x73,
- DBG_BLOCK_ID_TCP20 = 0x74,
- DBG_BLOCK_ID_TCP21 = 0x75,
- DBG_BLOCK_ID_TCP22 = 0x76,
- DBG_BLOCK_ID_TCP23 = 0x77,
- DBG_BLOCK_ID_TCP_RESERVED0 = 0x78,
- DBG_BLOCK_ID_TCP_RESERVED1 = 0x79,
- DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a,
- DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b,
- DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c,
- DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d,
- DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e,
- DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f,
- DBG_BLOCK_ID_DB00 = 0x80,
- DBG_BLOCK_ID_DB01 = 0x81,
- DBG_BLOCK_ID_DB02 = 0x82,
- DBG_BLOCK_ID_DB03 = 0x83,
- DBG_BLOCK_ID_DB04 = 0x84,
- DBG_BLOCK_ID_UNUSED27 = 0x85,
- DBG_BLOCK_ID_UNUSED28 = 0x86,
- DBG_BLOCK_ID_UNUSED29 = 0x87,
- DBG_BLOCK_ID_DB10 = 0x88,
- DBG_BLOCK_ID_DB11 = 0x89,
- DBG_BLOCK_ID_DB12 = 0x8a,
- DBG_BLOCK_ID_DB13 = 0x8b,
- DBG_BLOCK_ID_DB14 = 0x8c,
- DBG_BLOCK_ID_UNUSED30 = 0x8d,
- DBG_BLOCK_ID_UNUSED31 = 0x8e,
- DBG_BLOCK_ID_UNUSED32 = 0x8f,
- DBG_BLOCK_ID_TCC0 = 0x90,
- DBG_BLOCK_ID_TCC1 = 0x91,
- DBG_BLOCK_ID_TCC2 = 0x92,
- DBG_BLOCK_ID_TCC3 = 0x93,
- DBG_BLOCK_ID_TCC4 = 0x94,
- DBG_BLOCK_ID_TCC5 = 0x95,
- DBG_BLOCK_ID_TCC6 = 0x96,
- DBG_BLOCK_ID_TCC7 = 0x97,
- DBG_BLOCK_ID_SPS00 = 0x98,
- DBG_BLOCK_ID_SPS01 = 0x99,
- DBG_BLOCK_ID_SPS02 = 0x9a,
- DBG_BLOCK_ID_SPS10 = 0x9b,
- DBG_BLOCK_ID_SPS11 = 0x9c,
- DBG_BLOCK_ID_SPS12 = 0x9d,
- DBG_BLOCK_ID_UNUSED33 = 0x9e,
- DBG_BLOCK_ID_UNUSED34 = 0x9f,
- DBG_BLOCK_ID_TA00 = 0xa0,
- DBG_BLOCK_ID_TA01 = 0xa1,
- DBG_BLOCK_ID_TA02 = 0xa2,
- DBG_BLOCK_ID_TA03 = 0xa3,
- DBG_BLOCK_ID_TA04 = 0xa4,
- DBG_BLOCK_ID_TA05 = 0xa5,
- DBG_BLOCK_ID_TA06 = 0xa6,
- DBG_BLOCK_ID_TA07 = 0xa7,
- DBG_BLOCK_ID_TA08 = 0xa8,
- DBG_BLOCK_ID_TA09 = 0xa9,
- DBG_BLOCK_ID_TA0A = 0xaa,
- DBG_BLOCK_ID_TA0B = 0xab,
- DBG_BLOCK_ID_UNUSED35 = 0xac,
- DBG_BLOCK_ID_UNUSED36 = 0xad,
- DBG_BLOCK_ID_UNUSED37 = 0xae,
- DBG_BLOCK_ID_UNUSED38 = 0xaf,
- DBG_BLOCK_ID_TA10 = 0xb0,
- DBG_BLOCK_ID_TA11 = 0xb1,
- DBG_BLOCK_ID_TA12 = 0xb2,
- DBG_BLOCK_ID_TA13 = 0xb3,
- DBG_BLOCK_ID_TA14 = 0xb4,
- DBG_BLOCK_ID_TA15 = 0xb5,
- DBG_BLOCK_ID_TA16 = 0xb6,
- DBG_BLOCK_ID_TA17 = 0xb7,
- DBG_BLOCK_ID_TA18 = 0xb8,
- DBG_BLOCK_ID_TA19 = 0xb9,
- DBG_BLOCK_ID_TA1A = 0xba,
- DBG_BLOCK_ID_TA1B = 0xbb,
- DBG_BLOCK_ID_UNUSED39 = 0xbc,
- DBG_BLOCK_ID_UNUSED40 = 0xbd,
- DBG_BLOCK_ID_UNUSED41 = 0xbe,
- DBG_BLOCK_ID_UNUSED42 = 0xbf,
- DBG_BLOCK_ID_TD00 = 0xc0,
- DBG_BLOCK_ID_TD01 = 0xc1,
- DBG_BLOCK_ID_TD02 = 0xc2,
- DBG_BLOCK_ID_TD03 = 0xc3,
- DBG_BLOCK_ID_TD04 = 0xc4,
- DBG_BLOCK_ID_TD05 = 0xc5,
- DBG_BLOCK_ID_TD06 = 0xc6,
- DBG_BLOCK_ID_TD07 = 0xc7,
- DBG_BLOCK_ID_TD08 = 0xc8,
- DBG_BLOCK_ID_TD09 = 0xc9,
- DBG_BLOCK_ID_TD0A = 0xca,
- DBG_BLOCK_ID_TD0B = 0xcb,
- DBG_BLOCK_ID_UNUSED43 = 0xcc,
- DBG_BLOCK_ID_UNUSED44 = 0xcd,
- DBG_BLOCK_ID_UNUSED45 = 0xce,
- DBG_BLOCK_ID_UNUSED46 = 0xcf,
- DBG_BLOCK_ID_TD10 = 0xd0,
- DBG_BLOCK_ID_TD11 = 0xd1,
- DBG_BLOCK_ID_TD12 = 0xd2,
- DBG_BLOCK_ID_TD13 = 0xd3,
- DBG_BLOCK_ID_TD14 = 0xd4,
- DBG_BLOCK_ID_TD15 = 0xd5,
- DBG_BLOCK_ID_TD16 = 0xd6,
- DBG_BLOCK_ID_TD17 = 0xd7,
- DBG_BLOCK_ID_TD18 = 0xd8,
- DBG_BLOCK_ID_TD19 = 0xd9,
- DBG_BLOCK_ID_TD1A = 0xda,
- DBG_BLOCK_ID_TD1B = 0xdb,
- DBG_BLOCK_ID_UNUSED47 = 0xdc,
- DBG_BLOCK_ID_UNUSED48 = 0xdd,
- DBG_BLOCK_ID_UNUSED49 = 0xde,
- DBG_BLOCK_ID_UNUSED50 = 0xdf,
- DBG_BLOCK_ID_MCD0 = 0xe0,
- DBG_BLOCK_ID_MCD1 = 0xe1,
- DBG_BLOCK_ID_MCD2 = 0xe2,
- DBG_BLOCK_ID_MCD3 = 0xe3,
- DBG_BLOCK_ID_MCD4 = 0xe4,
- DBG_BLOCK_ID_MCD5 = 0xe5,
- DBG_BLOCK_ID_UNUSED51 = 0xe6,
- DBG_BLOCK_ID_UNUSED52 = 0xe7,
-} DebugBlockId_OLD;
-typedef enum DebugBlockId_BY2 {
- DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
- DBG_BLOCK_ID_VMC_BY2 = 0x1,
- DBG_BLOCK_ID_CG_BY2 = 0x2,
- DBG_BLOCK_ID_GRBM_BY2 = 0x3,
- DBG_BLOCK_ID_CSC_BY2 = 0x4,
- DBG_BLOCK_ID_IH_BY2 = 0x5,
- DBG_BLOCK_ID_SQ_BY2 = 0x6,
- DBG_BLOCK_ID_GMCON_BY2 = 0x7,
- DBG_BLOCK_ID_DMA0_BY2 = 0x8,
- DBG_BLOCK_ID_SPIM_BY2 = 0x9,
- DBG_BLOCK_ID_SPIS_BY2 = 0xa,
- DBG_BLOCK_ID_PA0_BY2 = 0xb,
- DBG_BLOCK_ID_CP0_BY2 = 0xc,
- DBG_BLOCK_ID_CP2_BY2 = 0xd,
- DBG_BLOCK_ID_UVDU_BY2 = 0xe,
- DBG_BLOCK_ID_VCE_BY2 = 0xf,
- DBG_BLOCK_ID_VGT0_BY2 = 0x10,
- DBG_BLOCK_ID_IA_BY2 = 0x11,
- DBG_BLOCK_ID_SCT0_BY2 = 0x12,
- DBG_BLOCK_ID_SPM0_BY2 = 0x13,
- DBG_BLOCK_ID_TCAA_BY2 = 0x14,
- DBG_BLOCK_ID_TCCA_BY2 = 0x15,
- DBG_BLOCK_ID_MCC0_BY2 = 0x16,
- DBG_BLOCK_ID_MCC2_BY2 = 0x17,
- DBG_BLOCK_ID_SX0_BY2 = 0x18,
- DBG_BLOCK_ID_SX2_BY2 = 0x19,
- DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a,
- DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b,
- DBG_BLOCK_ID_PC0_BY2 = 0x1c,
- DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d,
- DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e,
- DBG_BLOCK_ID_MCB_BY2 = 0x1f,
- DBG_BLOCK_ID_SCB0_BY2 = 0x20,
- DBG_BLOCK_ID_UNUSED13_BY2 = 0x21,
- DBG_BLOCK_ID_SCF0_BY2 = 0x22,
- DBG_BLOCK_ID_UNUSED15_BY2 = 0x23,
- DBG_BLOCK_ID_BCI0_BY2 = 0x24,
- DBG_BLOCK_ID_BCI2_BY2 = 0x25,
- DBG_BLOCK_ID_UNUSED17_BY2 = 0x26,
- DBG_BLOCK_ID_UNUSED19_BY2 = 0x27,
- DBG_BLOCK_ID_CB00_BY2 = 0x28,
- DBG_BLOCK_ID_CB02_BY2 = 0x29,
- DBG_BLOCK_ID_CB04_BY2 = 0x2a,
- DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b,
- DBG_BLOCK_ID_CB10_BY2 = 0x2c,
- DBG_BLOCK_ID_CB12_BY2 = 0x2d,
- DBG_BLOCK_ID_CB14_BY2 = 0x2e,
- DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f,
- DBG_BLOCK_ID_TCP0_BY2 = 0x30,
- DBG_BLOCK_ID_TCP2_BY2 = 0x31,
- DBG_BLOCK_ID_TCP4_BY2 = 0x32,
- DBG_BLOCK_ID_TCP6_BY2 = 0x33,
- DBG_BLOCK_ID_TCP8_BY2 = 0x34,
- DBG_BLOCK_ID_TCP10_BY2 = 0x35,
- DBG_BLOCK_ID_TCP12_BY2 = 0x36,
- DBG_BLOCK_ID_TCP14_BY2 = 0x37,
- DBG_BLOCK_ID_TCP16_BY2 = 0x38,
- DBG_BLOCK_ID_TCP18_BY2 = 0x39,
- DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
- DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
- DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
- DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
- DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
- DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
- DBG_BLOCK_ID_DB00_BY2 = 0x40,
- DBG_BLOCK_ID_DB02_BY2 = 0x41,
- DBG_BLOCK_ID_DB04_BY2 = 0x42,
- DBG_BLOCK_ID_UNUSED28_BY2 = 0x43,
- DBG_BLOCK_ID_DB10_BY2 = 0x44,
- DBG_BLOCK_ID_DB12_BY2 = 0x45,
- DBG_BLOCK_ID_DB14_BY2 = 0x46,
- DBG_BLOCK_ID_UNUSED31_BY2 = 0x47,
- DBG_BLOCK_ID_TCC0_BY2 = 0x48,
- DBG_BLOCK_ID_TCC2_BY2 = 0x49,
- DBG_BLOCK_ID_TCC4_BY2 = 0x4a,
- DBG_BLOCK_ID_TCC6_BY2 = 0x4b,
- DBG_BLOCK_ID_SPS00_BY2 = 0x4c,
- DBG_BLOCK_ID_SPS02_BY2 = 0x4d,
- DBG_BLOCK_ID_SPS11_BY2 = 0x4e,
- DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f,
- DBG_BLOCK_ID_TA00_BY2 = 0x50,
- DBG_BLOCK_ID_TA02_BY2 = 0x51,
- DBG_BLOCK_ID_TA04_BY2 = 0x52,
- DBG_BLOCK_ID_TA06_BY2 = 0x53,
- DBG_BLOCK_ID_TA08_BY2 = 0x54,
- DBG_BLOCK_ID_TA0A_BY2 = 0x55,
- DBG_BLOCK_ID_UNUSED35_BY2 = 0x56,
- DBG_BLOCK_ID_UNUSED37_BY2 = 0x57,
- DBG_BLOCK_ID_TA10_BY2 = 0x58,
- DBG_BLOCK_ID_TA12_BY2 = 0x59,
- DBG_BLOCK_ID_TA14_BY2 = 0x5a,
- DBG_BLOCK_ID_TA16_BY2 = 0x5b,
- DBG_BLOCK_ID_TA18_BY2 = 0x5c,
- DBG_BLOCK_ID_TA1A_BY2 = 0x5d,
- DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e,
- DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f,
- DBG_BLOCK_ID_TD00_BY2 = 0x60,
- DBG_BLOCK_ID_TD02_BY2 = 0x61,
- DBG_BLOCK_ID_TD04_BY2 = 0x62,
- DBG_BLOCK_ID_TD06_BY2 = 0x63,
- DBG_BLOCK_ID_TD08_BY2 = 0x64,
- DBG_BLOCK_ID_TD0A_BY2 = 0x65,
- DBG_BLOCK_ID_UNUSED43_BY2 = 0x66,
- DBG_BLOCK_ID_UNUSED45_BY2 = 0x67,
- DBG_BLOCK_ID_TD10_BY2 = 0x68,
- DBG_BLOCK_ID_TD12_BY2 = 0x69,
- DBG_BLOCK_ID_TD14_BY2 = 0x6a,
- DBG_BLOCK_ID_TD16_BY2 = 0x6b,
- DBG_BLOCK_ID_TD18_BY2 = 0x6c,
- DBG_BLOCK_ID_TD1A_BY2 = 0x6d,
- DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e,
- DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f,
- DBG_BLOCK_ID_MCD0_BY2 = 0x70,
- DBG_BLOCK_ID_MCD2_BY2 = 0x71,
- DBG_BLOCK_ID_MCD4_BY2 = 0x72,
- DBG_BLOCK_ID_UNUSED51_BY2 = 0x73,
-} DebugBlockId_BY2;
-typedef enum DebugBlockId_BY4 {
- DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
- DBG_BLOCK_ID_CG_BY4 = 0x1,
- DBG_BLOCK_ID_CSC_BY4 = 0x2,
- DBG_BLOCK_ID_SQ_BY4 = 0x3,
- DBG_BLOCK_ID_DMA0_BY4 = 0x4,
- DBG_BLOCK_ID_SPIS_BY4 = 0x5,
- DBG_BLOCK_ID_CP0_BY4 = 0x6,
- DBG_BLOCK_ID_UVDU_BY4 = 0x7,
- DBG_BLOCK_ID_VGT0_BY4 = 0x8,
- DBG_BLOCK_ID_SCT0_BY4 = 0x9,
- DBG_BLOCK_ID_TCAA_BY4 = 0xa,
- DBG_BLOCK_ID_MCC0_BY4 = 0xb,
- DBG_BLOCK_ID_SX0_BY4 = 0xc,
- DBG_BLOCK_ID_UNUSED4_BY4 = 0xd,
- DBG_BLOCK_ID_PC0_BY4 = 0xe,
- DBG_BLOCK_ID_UNUSED10_BY4 = 0xf,
- DBG_BLOCK_ID_SCB0_BY4 = 0x10,
- DBG_BLOCK_ID_SCF0_BY4 = 0x11,
- DBG_BLOCK_ID_BCI0_BY4 = 0x12,
- DBG_BLOCK_ID_UNUSED17_BY4 = 0x13,
- DBG_BLOCK_ID_CB00_BY4 = 0x14,
- DBG_BLOCK_ID_CB04_BY4 = 0x15,
- DBG_BLOCK_ID_CB10_BY4 = 0x16,
- DBG_BLOCK_ID_CB14_BY4 = 0x17,
- DBG_BLOCK_ID_TCP0_BY4 = 0x18,
- DBG_BLOCK_ID_TCP4_BY4 = 0x19,
- DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
- DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
- DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
- DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
- DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
- DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
- DBG_BLOCK_ID_DB_BY4 = 0x20,
- DBG_BLOCK_ID_DB04_BY4 = 0x21,
- DBG_BLOCK_ID_DB10_BY4 = 0x22,
- DBG_BLOCK_ID_DB14_BY4 = 0x23,
- DBG_BLOCK_ID_TCC0_BY4 = 0x24,
- DBG_BLOCK_ID_TCC4_BY4 = 0x25,
- DBG_BLOCK_ID_SPS00_BY4 = 0x26,
- DBG_BLOCK_ID_SPS11_BY4 = 0x27,
- DBG_BLOCK_ID_TA00_BY4 = 0x28,
- DBG_BLOCK_ID_TA04_BY4 = 0x29,
- DBG_BLOCK_ID_TA08_BY4 = 0x2a,
- DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b,
- DBG_BLOCK_ID_TA10_BY4 = 0x2c,
- DBG_BLOCK_ID_TA14_BY4 = 0x2d,
- DBG_BLOCK_ID_TA18_BY4 = 0x2e,
- DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f,
- DBG_BLOCK_ID_TD00_BY4 = 0x30,
- DBG_BLOCK_ID_TD04_BY4 = 0x31,
- DBG_BLOCK_ID_TD08_BY4 = 0x32,
- DBG_BLOCK_ID_UNUSED43_BY4 = 0x33,
- DBG_BLOCK_ID_TD10_BY4 = 0x34,
- DBG_BLOCK_ID_TD14_BY4 = 0x35,
- DBG_BLOCK_ID_TD18_BY4 = 0x36,
- DBG_BLOCK_ID_UNUSED47_BY4 = 0x37,
- DBG_BLOCK_ID_MCD0_BY4 = 0x38,
- DBG_BLOCK_ID_MCD4_BY4 = 0x39,
-} DebugBlockId_BY4;
-typedef enum DebugBlockId_BY8 {
- DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
- DBG_BLOCK_ID_CSC_BY8 = 0x1,
- DBG_BLOCK_ID_DMA0_BY8 = 0x2,
- DBG_BLOCK_ID_CP0_BY8 = 0x3,
- DBG_BLOCK_ID_VGT0_BY8 = 0x4,
- DBG_BLOCK_ID_TCAA_BY8 = 0x5,
- DBG_BLOCK_ID_SX0_BY8 = 0x6,
- DBG_BLOCK_ID_PC0_BY8 = 0x7,
- DBG_BLOCK_ID_SCB0_BY8 = 0x8,
- DBG_BLOCK_ID_BCI0_BY8 = 0x9,
- DBG_BLOCK_ID_CB00_BY8 = 0xa,
- DBG_BLOCK_ID_CB10_BY8 = 0xb,
- DBG_BLOCK_ID_TCP0_BY8 = 0xc,
- DBG_BLOCK_ID_TCP8_BY8 = 0xd,
- DBG_BLOCK_ID_TCP16_BY8 = 0xe,
- DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
- DBG_BLOCK_ID_DB00_BY8 = 0x10,
- DBG_BLOCK_ID_DB10_BY8 = 0x11,
- DBG_BLOCK_ID_TCC0_BY8 = 0x12,
- DBG_BLOCK_ID_SPS00_BY8 = 0x13,
- DBG_BLOCK_ID_TA00_BY8 = 0x14,
- DBG_BLOCK_ID_TA08_BY8 = 0x15,
- DBG_BLOCK_ID_TA10_BY8 = 0x16,
- DBG_BLOCK_ID_TA18_BY8 = 0x17,
- DBG_BLOCK_ID_TD00_BY8 = 0x18,
- DBG_BLOCK_ID_TD08_BY8 = 0x19,
- DBG_BLOCK_ID_TD10_BY8 = 0x1a,
- DBG_BLOCK_ID_TD18_BY8 = 0x1b,
- DBG_BLOCK_ID_MCD0_BY8 = 0x1c,
-} DebugBlockId_BY8;
-typedef enum DebugBlockId_BY16 {
- DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
- DBG_BLOCK_ID_DMA0_BY16 = 0x1,
- DBG_BLOCK_ID_VGT0_BY16 = 0x2,
- DBG_BLOCK_ID_SX0_BY16 = 0x3,
- DBG_BLOCK_ID_SCB0_BY16 = 0x4,
- DBG_BLOCK_ID_CB00_BY16 = 0x5,
- DBG_BLOCK_ID_TCP0_BY16 = 0x6,
- DBG_BLOCK_ID_TCP16_BY16 = 0x7,
- DBG_BLOCK_ID_DB00_BY16 = 0x8,
- DBG_BLOCK_ID_TCC0_BY16 = 0x9,
- DBG_BLOCK_ID_TA00_BY16 = 0xa,
- DBG_BLOCK_ID_TA10_BY16 = 0xb,
- DBG_BLOCK_ID_TD00_BY16 = 0xc,
- DBG_BLOCK_ID_TD10_BY16 = 0xd,
- DBG_BLOCK_ID_MCD0_BY16 = 0xe,
-} DebugBlockId_BY16;
-typedef enum ColorTransform {
- DCC_CT_AUTO = 0x0,
- DCC_CT_NONE = 0x1,
- ABGR_TO_A_BG_G_RB = 0x2,
- BGRA_TO_BG_G_RB_A = 0x3,
-} ColorTransform;
-typedef enum CompareRef {
- REF_NEVER = 0x0,
- REF_LESS = 0x1,
- REF_EQUAL = 0x2,
- REF_LEQUAL = 0x3,
- REF_GREATER = 0x4,
- REF_NOTEQUAL = 0x5,
- REF_GEQUAL = 0x6,
- REF_ALWAYS = 0x7,
-} CompareRef;
-typedef enum ReadSize {
- READ_256_BITS = 0x0,
- READ_512_BITS = 0x1,
-} ReadSize;
-typedef enum DepthFormat {
- DEPTH_INVALID = 0x0,
- DEPTH_16 = 0x1,
- DEPTH_X8_24 = 0x2,
- DEPTH_8_24 = 0x3,
- DEPTH_X8_24_FLOAT = 0x4,
- DEPTH_8_24_FLOAT = 0x5,
- DEPTH_32_FLOAT = 0x6,
- DEPTH_X24_8_32_FLOAT = 0x7,
-} DepthFormat;
-typedef enum ZFormat {
- Z_INVALID = 0x0,
- Z_16 = 0x1,
- Z_24 = 0x2,
- Z_32_FLOAT = 0x3,
-} ZFormat;
-typedef enum StencilFormat {
- STENCIL_INVALID = 0x0,
- STENCIL_8 = 0x1,
-} StencilFormat;
-typedef enum CmaskMode {
- CMASK_CLEAR_NONE = 0x0,
- CMASK_CLEAR_ONE = 0x1,
- CMASK_CLEAR_ALL = 0x2,
- CMASK_ANY_EXPANDED = 0x3,
- CMASK_ALPHA0_FRAG1 = 0x4,
- CMASK_ALPHA0_FRAG2 = 0x5,
- CMASK_ALPHA0_FRAG4 = 0x6,
- CMASK_ALPHA0_FRAGS = 0x7,
- CMASK_ALPHA1_FRAG1 = 0x8,
- CMASK_ALPHA1_FRAG2 = 0x9,
- CMASK_ALPHA1_FRAG4 = 0xa,
- CMASK_ALPHA1_FRAGS = 0xb,
- CMASK_ALPHAX_FRAG1 = 0xc,
- CMASK_ALPHAX_FRAG2 = 0xd,
- CMASK_ALPHAX_FRAG4 = 0xe,
- CMASK_ALPHAX_FRAGS = 0xf,
-} CmaskMode;
-typedef enum QuadExportFormat {
- EXPORT_UNUSED = 0x0,
- EXPORT_32_R = 0x1,
- EXPORT_32_GR = 0x2,
- EXPORT_32_AR = 0x3,
- EXPORT_FP16_ABGR = 0x4,
- EXPORT_UNSIGNED16_ABGR = 0x5,
- EXPORT_SIGNED16_ABGR = 0x6,
- EXPORT_32_ABGR = 0x7,
-} QuadExportFormat;
-typedef enum QuadExportFormatOld {
- EXPORT_4P_32BPC_ABGR = 0x0,
- EXPORT_4P_16BPC_ABGR = 0x1,
- EXPORT_4P_32BPC_GR = 0x2,
- EXPORT_4P_32BPC_AR = 0x3,
- EXPORT_2P_32BPC_ABGR = 0x4,
- EXPORT_8P_32BPC_R = 0x5,
-} QuadExportFormatOld;
-typedef enum ColorFormat {
- COLOR_INVALID = 0x0,
- COLOR_8 = 0x1,
- COLOR_16 = 0x2,
- COLOR_8_8 = 0x3,
- COLOR_32 = 0x4,
- COLOR_16_16 = 0x5,
- COLOR_10_11_11 = 0x6,
- COLOR_11_11_10 = 0x7,
- COLOR_10_10_10_2 = 0x8,
- COLOR_2_10_10_10 = 0x9,
- COLOR_8_8_8_8 = 0xa,
- COLOR_32_32 = 0xb,
- COLOR_16_16_16_16 = 0xc,
- COLOR_RESERVED_13 = 0xd,
- COLOR_32_32_32_32 = 0xe,
- COLOR_RESERVED_15 = 0xf,
- COLOR_5_6_5 = 0x10,
- COLOR_1_5_5_5 = 0x11,
- COLOR_5_5_5_1 = 0x12,
- COLOR_4_4_4_4 = 0x13,
- COLOR_8_24 = 0x14,
- COLOR_24_8 = 0x15,
- COLOR_X24_8_32_FLOAT = 0x16,
- COLOR_RESERVED_23 = 0x17,
-} ColorFormat;
-typedef enum SurfaceFormat {
- FMT_INVALID = 0x0,
- FMT_8 = 0x1,
- FMT_16 = 0x2,
- FMT_8_8 = 0x3,
- FMT_32 = 0x4,
- FMT_16_16 = 0x5,
- FMT_10_11_11 = 0x6,
- FMT_11_11_10 = 0x7,
- FMT_10_10_10_2 = 0x8,
- FMT_2_10_10_10 = 0x9,
- FMT_8_8_8_8 = 0xa,
- FMT_32_32 = 0xb,
- FMT_16_16_16_16 = 0xc,
- FMT_32_32_32 = 0xd,
- FMT_32_32_32_32 = 0xe,
- FMT_RESERVED_4 = 0xf,
- FMT_5_6_5 = 0x10,
- FMT_1_5_5_5 = 0x11,
- FMT_5_5_5_1 = 0x12,
- FMT_4_4_4_4 = 0x13,
- FMT_8_24 = 0x14,
- FMT_24_8 = 0x15,
- FMT_X24_8_32_FLOAT = 0x16,
- FMT_RESERVED_33 = 0x17,
- FMT_11_11_10_FLOAT = 0x18,
- FMT_16_FLOAT = 0x19,
- FMT_32_FLOAT = 0x1a,
- FMT_16_16_FLOAT = 0x1b,
- FMT_8_24_FLOAT = 0x1c,
- FMT_24_8_FLOAT = 0x1d,
- FMT_32_32_FLOAT = 0x1e,
- FMT_10_11_11_FLOAT = 0x1f,
- FMT_16_16_16_16_FLOAT = 0x20,
- FMT_3_3_2 = 0x21,
- FMT_6_5_5 = 0x22,
- FMT_32_32_32_32_FLOAT = 0x23,
- FMT_RESERVED_36 = 0x24,
- FMT_1 = 0x25,
- FMT_1_REVERSED = 0x26,
- FMT_GB_GR = 0x27,
- FMT_BG_RG = 0x28,
- FMT_32_AS_8 = 0x29,
- FMT_32_AS_8_8 = 0x2a,
- FMT_5_9_9_9_SHAREDEXP = 0x2b,
- FMT_8_8_8 = 0x2c,
- FMT_16_16_16 = 0x2d,
- FMT_16_16_16_FLOAT = 0x2e,
- FMT_4_4 = 0x2f,
- FMT_32_32_32_FLOAT = 0x30,
- FMT_BC1 = 0x31,
- FMT_BC2 = 0x32,
- FMT_BC3 = 0x33,
- FMT_BC4 = 0x34,
- FMT_BC5 = 0x35,
- FMT_BC6 = 0x36,
- FMT_BC7 = 0x37,
- FMT_32_AS_32_32_32_32 = 0x38,
- FMT_APC3 = 0x39,
- FMT_APC4 = 0x3a,
- FMT_APC5 = 0x3b,
- FMT_APC6 = 0x3c,
- FMT_APC7 = 0x3d,
- FMT_CTX1 = 0x3e,
- FMT_RESERVED_63 = 0x3f,
-} SurfaceFormat;
-typedef enum BUF_DATA_FORMAT {
- BUF_DATA_FORMAT_INVALID = 0x0,
- BUF_DATA_FORMAT_8 = 0x1,
- BUF_DATA_FORMAT_16 = 0x2,
- BUF_DATA_FORMAT_8_8 = 0x3,
- BUF_DATA_FORMAT_32 = 0x4,
- BUF_DATA_FORMAT_16_16 = 0x5,
- BUF_DATA_FORMAT_10_11_11 = 0x6,
- BUF_DATA_FORMAT_11_11_10 = 0x7,
- BUF_DATA_FORMAT_10_10_10_2 = 0x8,
- BUF_DATA_FORMAT_2_10_10_10 = 0x9,
- BUF_DATA_FORMAT_8_8_8_8 = 0xa,
- BUF_DATA_FORMAT_32_32 = 0xb,
- BUF_DATA_FORMAT_16_16_16_16 = 0xc,
- BUF_DATA_FORMAT_32_32_32 = 0xd,
- BUF_DATA_FORMAT_32_32_32_32 = 0xe,
- BUF_DATA_FORMAT_RESERVED_15 = 0xf,
-} BUF_DATA_FORMAT;
-typedef enum IMG_DATA_FORMAT {
- IMG_DATA_FORMAT_INVALID = 0x0,
- IMG_DATA_FORMAT_8 = 0x1,
- IMG_DATA_FORMAT_16 = 0x2,
- IMG_DATA_FORMAT_8_8 = 0x3,
- IMG_DATA_FORMAT_32 = 0x4,
- IMG_DATA_FORMAT_16_16 = 0x5,
- IMG_DATA_FORMAT_10_11_11 = 0x6,
- IMG_DATA_FORMAT_11_11_10 = 0x7,
- IMG_DATA_FORMAT_10_10_10_2 = 0x8,
- IMG_DATA_FORMAT_2_10_10_10 = 0x9,
- IMG_DATA_FORMAT_8_8_8_8 = 0xa,
- IMG_DATA_FORMAT_32_32 = 0xb,
- IMG_DATA_FORMAT_16_16_16_16 = 0xc,
- IMG_DATA_FORMAT_32_32_32 = 0xd,
- IMG_DATA_FORMAT_32_32_32_32 = 0xe,
- IMG_DATA_FORMAT_RESERVED_15 = 0xf,
- IMG_DATA_FORMAT_5_6_5 = 0x10,
- IMG_DATA_FORMAT_1_5_5_5 = 0x11,
- IMG_DATA_FORMAT_5_5_5_1 = 0x12,
- IMG_DATA_FORMAT_4_4_4_4 = 0x13,
- IMG_DATA_FORMAT_8_24 = 0x14,
- IMG_DATA_FORMAT_24_8 = 0x15,
- IMG_DATA_FORMAT_X24_8_32 = 0x16,
- IMG_DATA_FORMAT_RESERVED_23 = 0x17,
- IMG_DATA_FORMAT_RESERVED_24 = 0x18,
- IMG_DATA_FORMAT_RESERVED_25 = 0x19,
- IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
- IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
- IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
- IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
- IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
- IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
- IMG_DATA_FORMAT_GB_GR = 0x20,
- IMG_DATA_FORMAT_BG_RG = 0x21,
- IMG_DATA_FORMAT_5_9_9_9 = 0x22,
- IMG_DATA_FORMAT_BC1 = 0x23,
- IMG_DATA_FORMAT_BC2 = 0x24,
- IMG_DATA_FORMAT_BC3 = 0x25,
- IMG_DATA_FORMAT_BC4 = 0x26,
- IMG_DATA_FORMAT_BC5 = 0x27,
- IMG_DATA_FORMAT_BC6 = 0x28,
- IMG_DATA_FORMAT_BC7 = 0x29,
- IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
- IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
- IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
- IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
- IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
- IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
- IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
- IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
- IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
- IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
- IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
- IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
- IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
- IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
- IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
- IMG_DATA_FORMAT_4_4 = 0x39,
- IMG_DATA_FORMAT_6_5_5 = 0x3a,
- IMG_DATA_FORMAT_1 = 0x3b,
- IMG_DATA_FORMAT_1_REVERSED = 0x3c,
- IMG_DATA_FORMAT_32_AS_8 = 0x3d,
- IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
- IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
-} IMG_DATA_FORMAT;
-typedef enum BUF_NUM_FORMAT {
- BUF_NUM_FORMAT_UNORM = 0x0,
- BUF_NUM_FORMAT_SNORM = 0x1,
- BUF_NUM_FORMAT_USCALED = 0x2,
- BUF_NUM_FORMAT_SSCALED = 0x3,
- BUF_NUM_FORMAT_UINT = 0x4,
- BUF_NUM_FORMAT_SINT = 0x5,
- BUF_NUM_FORMAT_RESERVED_6 = 0x6,
- BUF_NUM_FORMAT_FLOAT = 0x7,
-} BUF_NUM_FORMAT;
-typedef enum IMG_NUM_FORMAT {
- IMG_NUM_FORMAT_UNORM = 0x0,
- IMG_NUM_FORMAT_SNORM = 0x1,
- IMG_NUM_FORMAT_USCALED = 0x2,
- IMG_NUM_FORMAT_SSCALED = 0x3,
- IMG_NUM_FORMAT_UINT = 0x4,
- IMG_NUM_FORMAT_SINT = 0x5,
- IMG_NUM_FORMAT_RESERVED_6 = 0x6,
- IMG_NUM_FORMAT_FLOAT = 0x7,
- IMG_NUM_FORMAT_RESERVED_8 = 0x8,
- IMG_NUM_FORMAT_SRGB = 0x9,
- IMG_NUM_FORMAT_RESERVED_10 = 0xa,
- IMG_NUM_FORMAT_RESERVED_11 = 0xb,
- IMG_NUM_FORMAT_RESERVED_12 = 0xc,
- IMG_NUM_FORMAT_RESERVED_13 = 0xd,
- IMG_NUM_FORMAT_RESERVED_14 = 0xe,
- IMG_NUM_FORMAT_RESERVED_15 = 0xf,
-} IMG_NUM_FORMAT;
-typedef enum TileType {
- ARRAY_COLOR_TILE = 0x0,
- ARRAY_DEPTH_TILE = 0x1,
-} TileType;
-typedef enum NonDispTilingOrder {
- ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
- ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
-} NonDispTilingOrder;
-typedef enum MicroTileMode {
- ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
- ADDR_SURF_THIN_MICRO_TILING = 0x1,
- ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
- ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
- ADDR_SURF_THICK_MICRO_TILING = 0x4,
-} MicroTileMode;
-typedef enum TileSplit {
- ADDR_SURF_TILE_SPLIT_64B = 0x0,
- ADDR_SURF_TILE_SPLIT_128B = 0x1,
- ADDR_SURF_TILE_SPLIT_256B = 0x2,
- ADDR_SURF_TILE_SPLIT_512B = 0x3,
- ADDR_SURF_TILE_SPLIT_1KB = 0x4,
- ADDR_SURF_TILE_SPLIT_2KB = 0x5,
- ADDR_SURF_TILE_SPLIT_4KB = 0x6,
-} TileSplit;
-typedef enum SampleSplit {
- ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
- ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
- ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
- ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
-} SampleSplit;
-typedef enum PipeConfig {
- ADDR_SURF_P2 = 0x0,
- ADDR_SURF_P2_RESERVED0 = 0x1,
- ADDR_SURF_P2_RESERVED1 = 0x2,
- ADDR_SURF_P2_RESERVED2 = 0x3,
- ADDR_SURF_P4_8x16 = 0x4,
- ADDR_SURF_P4_16x16 = 0x5,
- ADDR_SURF_P4_16x32 = 0x6,
- ADDR_SURF_P4_32x32 = 0x7,
- ADDR_SURF_P8_16x16_8x16 = 0x8,
- ADDR_SURF_P8_16x32_8x16 = 0x9,
- ADDR_SURF_P8_32x32_8x16 = 0xa,
- ADDR_SURF_P8_16x32_16x16 = 0xb,
- ADDR_SURF_P8_32x32_16x16 = 0xc,
- ADDR_SURF_P8_32x32_16x32 = 0xd,
- ADDR_SURF_P8_32x64_32x32 = 0xe,
- ADDR_SURF_P8_RESERVED0 = 0xf,
- ADDR_SURF_P16_32x32_8x16 = 0x10,
- ADDR_SURF_P16_32x32_16x16 = 0x11,
-} PipeConfig;
-typedef enum NumBanks {
- ADDR_SURF_2_BANK = 0x0,
- ADDR_SURF_4_BANK = 0x1,
- ADDR_SURF_8_BANK = 0x2,
- ADDR_SURF_16_BANK = 0x3,
-} NumBanks;
-typedef enum BankWidth {
- ADDR_SURF_BANK_WIDTH_1 = 0x0,
- ADDR_SURF_BANK_WIDTH_2 = 0x1,
- ADDR_SURF_BANK_WIDTH_4 = 0x2,
- ADDR_SURF_BANK_WIDTH_8 = 0x3,
-} BankWidth;
-typedef enum BankHeight {
- ADDR_SURF_BANK_HEIGHT_1 = 0x0,
- ADDR_SURF_BANK_HEIGHT_2 = 0x1,
- ADDR_SURF_BANK_HEIGHT_4 = 0x2,
- ADDR_SURF_BANK_HEIGHT_8 = 0x3,
-} BankHeight;
-typedef enum BankWidthHeight {
- ADDR_SURF_BANK_WH_1 = 0x0,
- ADDR_SURF_BANK_WH_2 = 0x1,
- ADDR_SURF_BANK_WH_4 = 0x2,
- ADDR_SURF_BANK_WH_8 = 0x3,
-} BankWidthHeight;
-typedef enum MacroTileAspect {
- ADDR_SURF_MACRO_ASPECT_1 = 0x0,
- ADDR_SURF_MACRO_ASPECT_2 = 0x1,
- ADDR_SURF_MACRO_ASPECT_4 = 0x2,
- ADDR_SURF_MACRO_ASPECT_8 = 0x3,
-} MacroTileAspect;
-typedef enum GATCL1RequestType {
- GATCL1_TYPE_NORMAL = 0x0,
- GATCL1_TYPE_SHOOTDOWN = 0x1,
- GATCL1_TYPE_BYPASS = 0x2,
-} GATCL1RequestType;
-typedef enum TCC_CACHE_POLICIES {
- TCC_CACHE_POLICY_LRU = 0x0,
- TCC_CACHE_POLICY_STREAM = 0x1,
-} TCC_CACHE_POLICIES;
-typedef enum MTYPE {
- MTYPE_NC_NV = 0x0,
- MTYPE_NC = 0x1,
- MTYPE_CC = 0x2,
- MTYPE_UC = 0x3,
-} MTYPE;
-typedef enum PERFMON_COUNTER_MODE {
- PERFMON_COUNTER_MODE_ACCUM = 0x0,
- PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
- PERFMON_COUNTER_MODE_MAX = 0x2,
- PERFMON_COUNTER_MODE_DIRTY = 0x3,
- PERFMON_COUNTER_MODE_SAMPLE = 0x4,
- PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
- PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
- PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
- PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
- PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
- PERFMON_COUNTER_MODE_RESERVED = 0xf,
-} PERFMON_COUNTER_MODE;
-typedef enum PERFMON_SPM_MODE {
- PERFMON_SPM_MODE_OFF = 0x0,
- PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
- PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
- PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
- PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
- PERFMON_SPM_MODE_RESERVED_5 = 0x5,
- PERFMON_SPM_MODE_RESERVED_6 = 0x6,
- PERFMON_SPM_MODE_RESERVED_7 = 0x7,
- PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
- PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
- PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
-} PERFMON_SPM_MODE;
-typedef enum SurfaceTiling {
- ARRAY_LINEAR = 0x0,
- ARRAY_TILED = 0x1,
-} SurfaceTiling;
-typedef enum SurfaceArray {
- ARRAY_1D = 0x0,
- ARRAY_2D = 0x1,
- ARRAY_3D = 0x2,
- ARRAY_3D_SLICE = 0x3,
-} SurfaceArray;
-typedef enum ColorArray {
- ARRAY_2D_ALT_COLOR = 0x0,
- ARRAY_2D_COLOR = 0x1,
- ARRAY_3D_SLICE_COLOR = 0x3,
-} ColorArray;
-typedef enum DepthArray {
- ARRAY_2D_ALT_DEPTH = 0x0,
- ARRAY_2D_DEPTH = 0x1,
-} DepthArray;
-typedef enum ENUM_NUM_SIMD_PER_CU {
- NUM_SIMD_PER_CU = 0x4,
-} ENUM_NUM_SIMD_PER_CU;
-
-#endif /* SMU_7_1_1_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_enum.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_enum.h
deleted file mode 100644
index 73bbf506b..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_enum.h
+++ /dev/null
@@ -1,1246 +0,0 @@
-/*
- * SMU_7_1_2 Register documentation
- *
- * Copyright (C) 2014 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef SMU_7_1_2_ENUM_H
-#define SMU_7_1_2_ENUM_H
-
-#define CG_SRBM_START_ADDR 0x600
-#define CG_SRBM_END_ADDR 0x8ff
-#define RCU_CCF_DWORDS0 0xa0
-#define RCU_CCF_BITS0 0x1400
-#define RCU_CCF_DWORDS1 0x0
-#define RCU_CCF_BITS1 0x0
-#define RCU_SAM_BYTES 0x2c
-#define RCU_SAM_RTL_BYTES 0x2c
-#define RCU_SMU_BYTES 0x14
-#define RCU_SMU_RTL_BYTES 0x14
-#define SFP_CHAIN_ADDR 0x0
-#define SFP_BYTES 0x140
-#define SFP_SADR 0xc0
-#define SFP_EADR 0x1ff
-#define SAMU_KEY_CHAIN_ADR 0x0
-#define SAMU_KEY_SADR 0x2a0
-#define SAMU_KEY_EADR 0x2cb
-#define SMU_KEY_CHAIN_ADR 0x0
-#define SMU_KEY_SADR 0x2cc
-#define SMU_KEY_EADR 0x2df
-#define SMC_MSG_TEST 0x1
-#define SMC_MSG_PHY_LN_OFF 0x2
-#define SMC_MSG_PHY_LN_ON 0x3
-#define SMC_MSG_DDI_PHY_OFF 0x4
-#define SMC_MSG_DDI_PHY_ON 0x5
-#define SMC_MSG_CASCADE_PLL_OFF 0x6
-#define SMC_MSG_CASCADE_PLL_ON 0x7
-#define SMC_MSG_PWR_OFF_x16 0x8
-#define SMC_MSG_CONFIG_LCLK_DPM 0x9
-#define SMC_MSG_FLUSH_DATA_CACHE 0xa
-#define SMC_MSG_FLUSH_INSTRUCTION_CACHE 0xb
-#define SMC_MSG_CONFIG_VPC_ACCUMULATOR 0xc
-#define SMC_MSG_CONFIG_BAPM 0xd
-#define SMC_MSG_CONFIG_TDC_LIMIT 0xe
-#define SMC_MSG_CONFIG_LPMx 0xf
-#define SMC_MSG_CONFIG_HTC_LIMIT 0x10
-#define SMC_MSG_CONFIG_THERMAL_CNTL 0x11
-#define SMC_MSG_CONFIG_VOLTAGE_CNTL 0x12
-#define SMC_MSG_CONFIG_TDP_CNTL 0x13
-#define SMC_MSG_EN_PM_CNTL 0x14
-#define SMC_MSG_DIS_PM_CNTL 0x15
-#define SMC_MSG_CONFIG_NBDPM 0x16
-#define SMC_MSG_CONFIG_LOADLINE 0x17
-#define SMC_MSG_ADJUST_LOADLINE 0x18
-#define SMC_MSG_RESET 0x20
-#define SMC_MSG_VOLTAGE 0x25
-#define SMC_VERSION_MAJOR 0x7
-#define SMC_VERSION_MINOR 0x0
-#define SMC_HEADER_SIZE 0x40
-#define ROM_SIGNATURE 0xaa55
-typedef enum SurfaceEndian {
- ENDIAN_NONE = 0x0,
- ENDIAN_8IN16 = 0x1,
- ENDIAN_8IN32 = 0x2,
- ENDIAN_8IN64 = 0x3,
-} SurfaceEndian;
-typedef enum ArrayMode {
- ARRAY_LINEAR_GENERAL = 0x0,
- ARRAY_LINEAR_ALIGNED = 0x1,
- ARRAY_1D_TILED_THIN1 = 0x2,
- ARRAY_1D_TILED_THICK = 0x3,
- ARRAY_2D_TILED_THIN1 = 0x4,
- ARRAY_PRT_TILED_THIN1 = 0x5,
- ARRAY_PRT_2D_TILED_THIN1 = 0x6,
- ARRAY_2D_TILED_THICK = 0x7,
- ARRAY_2D_TILED_XTHICK = 0x8,
- ARRAY_PRT_TILED_THICK = 0x9,
- ARRAY_PRT_2D_TILED_THICK = 0xa,
- ARRAY_PRT_3D_TILED_THIN1 = 0xb,
- ARRAY_3D_TILED_THIN1 = 0xc,
- ARRAY_3D_TILED_THICK = 0xd,
- ARRAY_3D_TILED_XTHICK = 0xe,
- ARRAY_PRT_3D_TILED_THICK = 0xf,
-} ArrayMode;
-typedef enum PipeTiling {
- CONFIG_1_PIPE = 0x0,
- CONFIG_2_PIPE = 0x1,
- CONFIG_4_PIPE = 0x2,
- CONFIG_8_PIPE = 0x3,
-} PipeTiling;
-typedef enum BankTiling {
- CONFIG_4_BANK = 0x0,
- CONFIG_8_BANK = 0x1,
-} BankTiling;
-typedef enum GroupInterleave {
- CONFIG_256B_GROUP = 0x0,
- CONFIG_512B_GROUP = 0x1,
-} GroupInterleave;
-typedef enum RowTiling {
- CONFIG_1KB_ROW = 0x0,
- CONFIG_2KB_ROW = 0x1,
- CONFIG_4KB_ROW = 0x2,
- CONFIG_8KB_ROW = 0x3,
- CONFIG_1KB_ROW_OPT = 0x4,
- CONFIG_2KB_ROW_OPT = 0x5,
- CONFIG_4KB_ROW_OPT = 0x6,
- CONFIG_8KB_ROW_OPT = 0x7,
-} RowTiling;
-typedef enum BankSwapBytes {
- CONFIG_128B_SWAPS = 0x0,
- CONFIG_256B_SWAPS = 0x1,
- CONFIG_512B_SWAPS = 0x2,
- CONFIG_1KB_SWAPS = 0x3,
-} BankSwapBytes;
-typedef enum SampleSplitBytes {
- CONFIG_1KB_SPLIT = 0x0,
- CONFIG_2KB_SPLIT = 0x1,
- CONFIG_4KB_SPLIT = 0x2,
- CONFIG_8KB_SPLIT = 0x3,
-} SampleSplitBytes;
-typedef enum NumPipes {
- ADDR_CONFIG_1_PIPE = 0x0,
- ADDR_CONFIG_2_PIPE = 0x1,
- ADDR_CONFIG_4_PIPE = 0x2,
- ADDR_CONFIG_8_PIPE = 0x3,
-} NumPipes;
-typedef enum PipeInterleaveSize {
- ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
- ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
-} PipeInterleaveSize;
-typedef enum BankInterleaveSize {
- ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
- ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
- ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
- ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
-} BankInterleaveSize;
-typedef enum NumShaderEngines {
- ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
- ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
-} NumShaderEngines;
-typedef enum ShaderEngineTileSize {
- ADDR_CONFIG_SE_TILE_16 = 0x0,
- ADDR_CONFIG_SE_TILE_32 = 0x1,
-} ShaderEngineTileSize;
-typedef enum NumGPUs {
- ADDR_CONFIG_1_GPU = 0x0,
- ADDR_CONFIG_2_GPU = 0x1,
- ADDR_CONFIG_4_GPU = 0x2,
-} NumGPUs;
-typedef enum MultiGPUTileSize {
- ADDR_CONFIG_GPU_TILE_16 = 0x0,
- ADDR_CONFIG_GPU_TILE_32 = 0x1,
- ADDR_CONFIG_GPU_TILE_64 = 0x2,
- ADDR_CONFIG_GPU_TILE_128 = 0x3,
-} MultiGPUTileSize;
-typedef enum RowSize {
- ADDR_CONFIG_1KB_ROW = 0x0,
- ADDR_CONFIG_2KB_ROW = 0x1,
- ADDR_CONFIG_4KB_ROW = 0x2,
-} RowSize;
-typedef enum NumLowerPipes {
- ADDR_CONFIG_1_LOWER_PIPES = 0x0,
- ADDR_CONFIG_2_LOWER_PIPES = 0x1,
-} NumLowerPipes;
-typedef enum DebugBlockId {
- DBG_CLIENT_BLKID_RESERVED = 0x0,
- DBG_CLIENT_BLKID_dbg = 0x1,
- DBG_CLIENT_BLKID_scf2 = 0x2,
- DBG_CLIENT_BLKID_mcd5 = 0x3,
- DBG_CLIENT_BLKID_vmc = 0x4,
- DBG_CLIENT_BLKID_sx30 = 0x5,
- DBG_CLIENT_BLKID_mcd2 = 0x6,
- DBG_CLIENT_BLKID_bci1 = 0x7,
- DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0x8,
- DBG_CLIENT_BLKID_mcc0 = 0x9,
- DBG_CLIENT_BLKID_uvdf_0 = 0xa,
- DBG_CLIENT_BLKID_uvdf_1 = 0xb,
- DBG_CLIENT_BLKID_bci0 = 0xc,
- DBG_CLIENT_BLKID_vcec0_0 = 0xd,
- DBG_CLIENT_BLKID_cb100 = 0xe,
- DBG_CLIENT_BLKID_cb001 = 0xf,
- DBG_CLIENT_BLKID_mcd4 = 0x10,
- DBG_CLIENT_BLKID_tmonw00 = 0x11,
- DBG_CLIENT_BLKID_cb101 = 0x12,
- DBG_CLIENT_BLKID_sx10 = 0x13,
- DBG_CLIENT_BLKID_cb301 = 0x14,
- DBG_CLIENT_BLKID_tmonw01 = 0x15,
- DBG_CLIENT_BLKID_vcea0_0 = 0x16,
- DBG_CLIENT_BLKID_vcea0_1 = 0x17,
- DBG_CLIENT_BLKID_vcea0_2 = 0x18,
- DBG_CLIENT_BLKID_vcea0_3 = 0x19,
- DBG_CLIENT_BLKID_scf1 = 0x1a,
- DBG_CLIENT_BLKID_sx20 = 0x1b,
- DBG_CLIENT_BLKID_spim1 = 0x1c,
- DBG_CLIENT_BLKID_pa10 = 0x1d,
- DBG_CLIENT_BLKID_pa00 = 0x1e,
- DBG_CLIENT_BLKID_gmcon = 0x1f,
- DBG_CLIENT_BLKID_mcb = 0x20,
- DBG_CLIENT_BLKID_vgt0 = 0x21,
- DBG_CLIENT_BLKID_pc0 = 0x22,
- DBG_CLIENT_BLKID_bci2 = 0x23,
- DBG_CLIENT_BLKID_uvdb_0 = 0x24,
- DBG_CLIENT_BLKID_spim3 = 0x25,
- DBG_CLIENT_BLKID_cpc_0 = 0x26,
- DBG_CLIENT_BLKID_cpc_1 = 0x27,
- DBG_CLIENT_BLKID_uvdm_0 = 0x28,
- DBG_CLIENT_BLKID_uvdm_1 = 0x29,
- DBG_CLIENT_BLKID_uvdm_2 = 0x2a,
- DBG_CLIENT_BLKID_uvdm_3 = 0x2b,
- DBG_CLIENT_BLKID_cb000 = 0x2c,
- DBG_CLIENT_BLKID_spim0 = 0x2d,
- DBG_CLIENT_BLKID_mcc2 = 0x2e,
- DBG_CLIENT_BLKID_ds0 = 0x2f,
- DBG_CLIENT_BLKID_srbm = 0x30,
- DBG_CLIENT_BLKID_ih = 0x31,
- DBG_CLIENT_BLKID_sem = 0x32,
- DBG_CLIENT_BLKID_sdma_0 = 0x33,
- DBG_CLIENT_BLKID_sdma_1 = 0x34,
- DBG_CLIENT_BLKID_hdp = 0x35,
- DBG_CLIENT_BLKID_acp_0 = 0x36,
- DBG_CLIENT_BLKID_acp_1 = 0x37,
- DBG_CLIENT_BLKID_cb200 = 0x38,
- DBG_CLIENT_BLKID_scf3 = 0x39,
- DBG_CLIENT_BLKID_vceb1_0 = 0x3a,
- DBG_CLIENT_BLKID_vcea1_0 = 0x3b,
- DBG_CLIENT_BLKID_vcea1_1 = 0x3c,
- DBG_CLIENT_BLKID_vcea1_2 = 0x3d,
- DBG_CLIENT_BLKID_vcea1_3 = 0x3e,
- DBG_CLIENT_BLKID_bci3 = 0x3f,
- DBG_CLIENT_BLKID_mcd0 = 0x40,
- DBG_CLIENT_BLKID_pa11 = 0x41,
- DBG_CLIENT_BLKID_pa01 = 0x42,
- DBG_CLIENT_BLKID_cb201 = 0x43,
- DBG_CLIENT_BLKID_spim2 = 0x44,
- DBG_CLIENT_BLKID_vgt2 = 0x45,
- DBG_CLIENT_BLKID_pc2 = 0x46,
- DBG_CLIENT_BLKID_smu_0 = 0x47,
- DBG_CLIENT_BLKID_smu_1 = 0x48,
- DBG_CLIENT_BLKID_smu_2 = 0x49,
- DBG_CLIENT_BLKID_cb1 = 0x4a,
- DBG_CLIENT_BLKID_ia0 = 0x4b,
- DBG_CLIENT_BLKID_wd = 0x4c,
- DBG_CLIENT_BLKID_ia1 = 0x4d,
- DBG_CLIENT_BLKID_vcec1_0 = 0x4e,
- DBG_CLIENT_BLKID_scf0 = 0x4f,
- DBG_CLIENT_BLKID_vgt1 = 0x50,
- DBG_CLIENT_BLKID_pc1 = 0x51,
- DBG_CLIENT_BLKID_cb0 = 0x52,
- DBG_CLIENT_BLKID_gdc_one_0 = 0x53,
- DBG_CLIENT_BLKID_gdc_one_1 = 0x54,
- DBG_CLIENT_BLKID_gdc_one_2 = 0x55,
- DBG_CLIENT_BLKID_gdc_one_3 = 0x56,
- DBG_CLIENT_BLKID_gdc_one_4 = 0x57,
- DBG_CLIENT_BLKID_gdc_one_5 = 0x58,
- DBG_CLIENT_BLKID_gdc_one_6 = 0x59,
- DBG_CLIENT_BLKID_gdc_one_7 = 0x5a,
- DBG_CLIENT_BLKID_gdc_one_8 = 0x5b,
- DBG_CLIENT_BLKID_gdc_one_9 = 0x5c,
- DBG_CLIENT_BLKID_gdc_one_10 = 0x5d,
- DBG_CLIENT_BLKID_gdc_one_11 = 0x5e,
- DBG_CLIENT_BLKID_gdc_one_12 = 0x5f,
- DBG_CLIENT_BLKID_gdc_one_13 = 0x60,
- DBG_CLIENT_BLKID_gdc_one_14 = 0x61,
- DBG_CLIENT_BLKID_gdc_one_15 = 0x62,
- DBG_CLIENT_BLKID_gdc_one_16 = 0x63,
- DBG_CLIENT_BLKID_gdc_one_17 = 0x64,
- DBG_CLIENT_BLKID_gdc_one_18 = 0x65,
- DBG_CLIENT_BLKID_gdc_one_19 = 0x66,
- DBG_CLIENT_BLKID_gdc_one_20 = 0x67,
- DBG_CLIENT_BLKID_gdc_one_21 = 0x68,
- DBG_CLIENT_BLKID_gdc_one_22 = 0x69,
- DBG_CLIENT_BLKID_gdc_one_23 = 0x6a,
- DBG_CLIENT_BLKID_gdc_one_24 = 0x6b,
- DBG_CLIENT_BLKID_gdc_one_25 = 0x6c,
- DBG_CLIENT_BLKID_gdc_one_26 = 0x6d,
- DBG_CLIENT_BLKID_gdc_one_27 = 0x6e,
- DBG_CLIENT_BLKID_gdc_one_28 = 0x6f,
- DBG_CLIENT_BLKID_gdc_one_29 = 0x70,
- DBG_CLIENT_BLKID_gdc_one_30 = 0x71,
- DBG_CLIENT_BLKID_gdc_one_31 = 0x72,
- DBG_CLIENT_BLKID_gdc_one_32 = 0x73,
- DBG_CLIENT_BLKID_gdc_one_33 = 0x74,
- DBG_CLIENT_BLKID_gdc_one_34 = 0x75,
- DBG_CLIENT_BLKID_gdc_one_35 = 0x76,
- DBG_CLIENT_BLKID_vceb0_0 = 0x77,
- DBG_CLIENT_BLKID_vgt3 = 0x78,
- DBG_CLIENT_BLKID_pc3 = 0x79,
- DBG_CLIENT_BLKID_mcd3 = 0x7a,
- DBG_CLIENT_BLKID_uvdu_0 = 0x7b,
- DBG_CLIENT_BLKID_uvdu_1 = 0x7c,
- DBG_CLIENT_BLKID_uvdu_2 = 0x7d,
- DBG_CLIENT_BLKID_uvdu_3 = 0x7e,
- DBG_CLIENT_BLKID_uvdu_4 = 0x7f,
- DBG_CLIENT_BLKID_uvdu_5 = 0x80,
- DBG_CLIENT_BLKID_uvdu_6 = 0x81,
- DBG_CLIENT_BLKID_cb300 = 0x82,
- DBG_CLIENT_BLKID_mcd1 = 0x83,
- DBG_CLIENT_BLKID_sx00 = 0x84,
- DBG_CLIENT_BLKID_uvdc_0 = 0x85,
- DBG_CLIENT_BLKID_uvdc_1 = 0x86,
- DBG_CLIENT_BLKID_mcc3 = 0x87,
- DBG_CLIENT_BLKID_cpg_0 = 0x88,
- DBG_CLIENT_BLKID_cpg_1 = 0x89,
- DBG_CLIENT_BLKID_gck = 0x8a,
- DBG_CLIENT_BLKID_mcc1 = 0x8b,
- DBG_CLIENT_BLKID_cpf_0 = 0x8c,
- DBG_CLIENT_BLKID_cpf_1 = 0x8d,
- DBG_CLIENT_BLKID_rlc = 0x8e,
- DBG_CLIENT_BLKID_grbm = 0x8f,
- DBG_CLIENT_BLKID_sammsp = 0x90,
- DBG_CLIENT_BLKID_dci_pg = 0x91,
- DBG_CLIENT_BLKID_dci_0 = 0x92,
- DBG_CLIENT_BLKID_dccg0_0 = 0x93,
- DBG_CLIENT_BLKID_dccg0_1 = 0x94,
- DBG_CLIENT_BLKID_dcfe01_0 = 0x95,
- DBG_CLIENT_BLKID_dcfe02_0 = 0x96,
- DBG_CLIENT_BLKID_dcfe03_0 = 0x97,
- DBG_CLIENT_BLKID_dcfe04_0 = 0x98,
- DBG_CLIENT_BLKID_dcfe05_0 = 0x99,
- DBG_CLIENT_BLKID_dcfe06_0 = 0x9a,
- DBG_CLIENT_BLKID_RESERVED_LAST = 0x9b,
-} DebugBlockId;
-typedef enum DebugBlockId_OLD {
- DBG_BLOCK_ID_RESERVED = 0x0,
- DBG_BLOCK_ID_DBG = 0x1,
- DBG_BLOCK_ID_VMC = 0x2,
- DBG_BLOCK_ID_PDMA = 0x3,
- DBG_BLOCK_ID_CG = 0x4,
- DBG_BLOCK_ID_SRBM = 0x5,
- DBG_BLOCK_ID_GRBM = 0x6,
- DBG_BLOCK_ID_RLC = 0x7,
- DBG_BLOCK_ID_CSC = 0x8,
- DBG_BLOCK_ID_SEM = 0x9,
- DBG_BLOCK_ID_IH = 0xa,
- DBG_BLOCK_ID_SC = 0xb,
- DBG_BLOCK_ID_SQ = 0xc,
- DBG_BLOCK_ID_AVP = 0xd,
- DBG_BLOCK_ID_GMCON = 0xe,
- DBG_BLOCK_ID_SMU = 0xf,
- DBG_BLOCK_ID_DMA0 = 0x10,
- DBG_BLOCK_ID_DMA1 = 0x11,
- DBG_BLOCK_ID_SPIM = 0x12,
- DBG_BLOCK_ID_GDS = 0x13,
- DBG_BLOCK_ID_SPIS = 0x14,
- DBG_BLOCK_ID_UNUSED0 = 0x15,
- DBG_BLOCK_ID_PA0 = 0x16,
- DBG_BLOCK_ID_PA1 = 0x17,
- DBG_BLOCK_ID_CP0 = 0x18,
- DBG_BLOCK_ID_CP1 = 0x19,
- DBG_BLOCK_ID_CP2 = 0x1a,
- DBG_BLOCK_ID_UNUSED1 = 0x1b,
- DBG_BLOCK_ID_UVDU = 0x1c,
- DBG_BLOCK_ID_UVDM = 0x1d,
- DBG_BLOCK_ID_VCE = 0x1e,
- DBG_BLOCK_ID_UNUSED2 = 0x1f,
- DBG_BLOCK_ID_VGT0 = 0x20,
- DBG_BLOCK_ID_VGT1 = 0x21,
- DBG_BLOCK_ID_IA = 0x22,
- DBG_BLOCK_ID_UNUSED3 = 0x23,
- DBG_BLOCK_ID_SCT0 = 0x24,
- DBG_BLOCK_ID_SCT1 = 0x25,
- DBG_BLOCK_ID_SPM0 = 0x26,
- DBG_BLOCK_ID_SPM1 = 0x27,
- DBG_BLOCK_ID_TCAA = 0x28,
- DBG_BLOCK_ID_TCAB = 0x29,
- DBG_BLOCK_ID_TCCA = 0x2a,
- DBG_BLOCK_ID_TCCB = 0x2b,
- DBG_BLOCK_ID_MCC0 = 0x2c,
- DBG_BLOCK_ID_MCC1 = 0x2d,
- DBG_BLOCK_ID_MCC2 = 0x2e,
- DBG_BLOCK_ID_MCC3 = 0x2f,
- DBG_BLOCK_ID_SX0 = 0x30,
- DBG_BLOCK_ID_SX1 = 0x31,
- DBG_BLOCK_ID_SX2 = 0x32,
- DBG_BLOCK_ID_SX3 = 0x33,
- DBG_BLOCK_ID_UNUSED4 = 0x34,
- DBG_BLOCK_ID_UNUSED5 = 0x35,
- DBG_BLOCK_ID_UNUSED6 = 0x36,
- DBG_BLOCK_ID_UNUSED7 = 0x37,
- DBG_BLOCK_ID_PC0 = 0x38,
- DBG_BLOCK_ID_PC1 = 0x39,
- DBG_BLOCK_ID_UNUSED8 = 0x3a,
- DBG_BLOCK_ID_UNUSED9 = 0x3b,
- DBG_BLOCK_ID_UNUSED10 = 0x3c,
- DBG_BLOCK_ID_UNUSED11 = 0x3d,
- DBG_BLOCK_ID_MCB = 0x3e,
- DBG_BLOCK_ID_UNUSED12 = 0x3f,
- DBG_BLOCK_ID_SCB0 = 0x40,
- DBG_BLOCK_ID_SCB1 = 0x41,
- DBG_BLOCK_ID_UNUSED13 = 0x42,
- DBG_BLOCK_ID_UNUSED14 = 0x43,
- DBG_BLOCK_ID_SCF0 = 0x44,
- DBG_BLOCK_ID_SCF1 = 0x45,
- DBG_BLOCK_ID_UNUSED15 = 0x46,
- DBG_BLOCK_ID_UNUSED16 = 0x47,
- DBG_BLOCK_ID_BCI0 = 0x48,
- DBG_BLOCK_ID_BCI1 = 0x49,
- DBG_BLOCK_ID_BCI2 = 0x4a,
- DBG_BLOCK_ID_BCI3 = 0x4b,
- DBG_BLOCK_ID_UNUSED17 = 0x4c,
- DBG_BLOCK_ID_UNUSED18 = 0x4d,
- DBG_BLOCK_ID_UNUSED19 = 0x4e,
- DBG_BLOCK_ID_UNUSED20 = 0x4f,
- DBG_BLOCK_ID_CB00 = 0x50,
- DBG_BLOCK_ID_CB01 = 0x51,
- DBG_BLOCK_ID_CB02 = 0x52,
- DBG_BLOCK_ID_CB03 = 0x53,
- DBG_BLOCK_ID_CB04 = 0x54,
- DBG_BLOCK_ID_UNUSED21 = 0x55,
- DBG_BLOCK_ID_UNUSED22 = 0x56,
- DBG_BLOCK_ID_UNUSED23 = 0x57,
- DBG_BLOCK_ID_CB10 = 0x58,
- DBG_BLOCK_ID_CB11 = 0x59,
- DBG_BLOCK_ID_CB12 = 0x5a,
- DBG_BLOCK_ID_CB13 = 0x5b,
- DBG_BLOCK_ID_CB14 = 0x5c,
- DBG_BLOCK_ID_UNUSED24 = 0x5d,
- DBG_BLOCK_ID_UNUSED25 = 0x5e,
- DBG_BLOCK_ID_UNUSED26 = 0x5f,
- DBG_BLOCK_ID_TCP0 = 0x60,
- DBG_BLOCK_ID_TCP1 = 0x61,
- DBG_BLOCK_ID_TCP2 = 0x62,
- DBG_BLOCK_ID_TCP3 = 0x63,
- DBG_BLOCK_ID_TCP4 = 0x64,
- DBG_BLOCK_ID_TCP5 = 0x65,
- DBG_BLOCK_ID_TCP6 = 0x66,
- DBG_BLOCK_ID_TCP7 = 0x67,
- DBG_BLOCK_ID_TCP8 = 0x68,
- DBG_BLOCK_ID_TCP9 = 0x69,
- DBG_BLOCK_ID_TCP10 = 0x6a,
- DBG_BLOCK_ID_TCP11 = 0x6b,
- DBG_BLOCK_ID_TCP12 = 0x6c,
- DBG_BLOCK_ID_TCP13 = 0x6d,
- DBG_BLOCK_ID_TCP14 = 0x6e,
- DBG_BLOCK_ID_TCP15 = 0x6f,
- DBG_BLOCK_ID_TCP16 = 0x70,
- DBG_BLOCK_ID_TCP17 = 0x71,
- DBG_BLOCK_ID_TCP18 = 0x72,
- DBG_BLOCK_ID_TCP19 = 0x73,
- DBG_BLOCK_ID_TCP20 = 0x74,
- DBG_BLOCK_ID_TCP21 = 0x75,
- DBG_BLOCK_ID_TCP22 = 0x76,
- DBG_BLOCK_ID_TCP23 = 0x77,
- DBG_BLOCK_ID_TCP_RESERVED0 = 0x78,
- DBG_BLOCK_ID_TCP_RESERVED1 = 0x79,
- DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a,
- DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b,
- DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c,
- DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d,
- DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e,
- DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f,
- DBG_BLOCK_ID_DB00 = 0x80,
- DBG_BLOCK_ID_DB01 = 0x81,
- DBG_BLOCK_ID_DB02 = 0x82,
- DBG_BLOCK_ID_DB03 = 0x83,
- DBG_BLOCK_ID_DB04 = 0x84,
- DBG_BLOCK_ID_UNUSED27 = 0x85,
- DBG_BLOCK_ID_UNUSED28 = 0x86,
- DBG_BLOCK_ID_UNUSED29 = 0x87,
- DBG_BLOCK_ID_DB10 = 0x88,
- DBG_BLOCK_ID_DB11 = 0x89,
- DBG_BLOCK_ID_DB12 = 0x8a,
- DBG_BLOCK_ID_DB13 = 0x8b,
- DBG_BLOCK_ID_DB14 = 0x8c,
- DBG_BLOCK_ID_UNUSED30 = 0x8d,
- DBG_BLOCK_ID_UNUSED31 = 0x8e,
- DBG_BLOCK_ID_UNUSED32 = 0x8f,
- DBG_BLOCK_ID_TCC0 = 0x90,
- DBG_BLOCK_ID_TCC1 = 0x91,
- DBG_BLOCK_ID_TCC2 = 0x92,
- DBG_BLOCK_ID_TCC3 = 0x93,
- DBG_BLOCK_ID_TCC4 = 0x94,
- DBG_BLOCK_ID_TCC5 = 0x95,
- DBG_BLOCK_ID_TCC6 = 0x96,
- DBG_BLOCK_ID_TCC7 = 0x97,
- DBG_BLOCK_ID_SPS00 = 0x98,
- DBG_BLOCK_ID_SPS01 = 0x99,
- DBG_BLOCK_ID_SPS02 = 0x9a,
- DBG_BLOCK_ID_SPS10 = 0x9b,
- DBG_BLOCK_ID_SPS11 = 0x9c,
- DBG_BLOCK_ID_SPS12 = 0x9d,
- DBG_BLOCK_ID_UNUSED33 = 0x9e,
- DBG_BLOCK_ID_UNUSED34 = 0x9f,
- DBG_BLOCK_ID_TA00 = 0xa0,
- DBG_BLOCK_ID_TA01 = 0xa1,
- DBG_BLOCK_ID_TA02 = 0xa2,
- DBG_BLOCK_ID_TA03 = 0xa3,
- DBG_BLOCK_ID_TA04 = 0xa4,
- DBG_BLOCK_ID_TA05 = 0xa5,
- DBG_BLOCK_ID_TA06 = 0xa6,
- DBG_BLOCK_ID_TA07 = 0xa7,
- DBG_BLOCK_ID_TA08 = 0xa8,
- DBG_BLOCK_ID_TA09 = 0xa9,
- DBG_BLOCK_ID_TA0A = 0xaa,
- DBG_BLOCK_ID_TA0B = 0xab,
- DBG_BLOCK_ID_UNUSED35 = 0xac,
- DBG_BLOCK_ID_UNUSED36 = 0xad,
- DBG_BLOCK_ID_UNUSED37 = 0xae,
- DBG_BLOCK_ID_UNUSED38 = 0xaf,
- DBG_BLOCK_ID_TA10 = 0xb0,
- DBG_BLOCK_ID_TA11 = 0xb1,
- DBG_BLOCK_ID_TA12 = 0xb2,
- DBG_BLOCK_ID_TA13 = 0xb3,
- DBG_BLOCK_ID_TA14 = 0xb4,
- DBG_BLOCK_ID_TA15 = 0xb5,
- DBG_BLOCK_ID_TA16 = 0xb6,
- DBG_BLOCK_ID_TA17 = 0xb7,
- DBG_BLOCK_ID_TA18 = 0xb8,
- DBG_BLOCK_ID_TA19 = 0xb9,
- DBG_BLOCK_ID_TA1A = 0xba,
- DBG_BLOCK_ID_TA1B = 0xbb,
- DBG_BLOCK_ID_UNUSED39 = 0xbc,
- DBG_BLOCK_ID_UNUSED40 = 0xbd,
- DBG_BLOCK_ID_UNUSED41 = 0xbe,
- DBG_BLOCK_ID_UNUSED42 = 0xbf,
- DBG_BLOCK_ID_TD00 = 0xc0,
- DBG_BLOCK_ID_TD01 = 0xc1,
- DBG_BLOCK_ID_TD02 = 0xc2,
- DBG_BLOCK_ID_TD03 = 0xc3,
- DBG_BLOCK_ID_TD04 = 0xc4,
- DBG_BLOCK_ID_TD05 = 0xc5,
- DBG_BLOCK_ID_TD06 = 0xc6,
- DBG_BLOCK_ID_TD07 = 0xc7,
- DBG_BLOCK_ID_TD08 = 0xc8,
- DBG_BLOCK_ID_TD09 = 0xc9,
- DBG_BLOCK_ID_TD0A = 0xca,
- DBG_BLOCK_ID_TD0B = 0xcb,
- DBG_BLOCK_ID_UNUSED43 = 0xcc,
- DBG_BLOCK_ID_UNUSED44 = 0xcd,
- DBG_BLOCK_ID_UNUSED45 = 0xce,
- DBG_BLOCK_ID_UNUSED46 = 0xcf,
- DBG_BLOCK_ID_TD10 = 0xd0,
- DBG_BLOCK_ID_TD11 = 0xd1,
- DBG_BLOCK_ID_TD12 = 0xd2,
- DBG_BLOCK_ID_TD13 = 0xd3,
- DBG_BLOCK_ID_TD14 = 0xd4,
- DBG_BLOCK_ID_TD15 = 0xd5,
- DBG_BLOCK_ID_TD16 = 0xd6,
- DBG_BLOCK_ID_TD17 = 0xd7,
- DBG_BLOCK_ID_TD18 = 0xd8,
- DBG_BLOCK_ID_TD19 = 0xd9,
- DBG_BLOCK_ID_TD1A = 0xda,
- DBG_BLOCK_ID_TD1B = 0xdb,
- DBG_BLOCK_ID_UNUSED47 = 0xdc,
- DBG_BLOCK_ID_UNUSED48 = 0xdd,
- DBG_BLOCK_ID_UNUSED49 = 0xde,
- DBG_BLOCK_ID_UNUSED50 = 0xdf,
- DBG_BLOCK_ID_MCD0 = 0xe0,
- DBG_BLOCK_ID_MCD1 = 0xe1,
- DBG_BLOCK_ID_MCD2 = 0xe2,
- DBG_BLOCK_ID_MCD3 = 0xe3,
- DBG_BLOCK_ID_MCD4 = 0xe4,
- DBG_BLOCK_ID_MCD5 = 0xe5,
- DBG_BLOCK_ID_UNUSED51 = 0xe6,
- DBG_BLOCK_ID_UNUSED52 = 0xe7,
-} DebugBlockId_OLD;
-typedef enum DebugBlockId_BY2 {
- DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
- DBG_BLOCK_ID_VMC_BY2 = 0x1,
- DBG_BLOCK_ID_CG_BY2 = 0x2,
- DBG_BLOCK_ID_GRBM_BY2 = 0x3,
- DBG_BLOCK_ID_CSC_BY2 = 0x4,
- DBG_BLOCK_ID_IH_BY2 = 0x5,
- DBG_BLOCK_ID_SQ_BY2 = 0x6,
- DBG_BLOCK_ID_GMCON_BY2 = 0x7,
- DBG_BLOCK_ID_DMA0_BY2 = 0x8,
- DBG_BLOCK_ID_SPIM_BY2 = 0x9,
- DBG_BLOCK_ID_SPIS_BY2 = 0xa,
- DBG_BLOCK_ID_PA0_BY2 = 0xb,
- DBG_BLOCK_ID_CP0_BY2 = 0xc,
- DBG_BLOCK_ID_CP2_BY2 = 0xd,
- DBG_BLOCK_ID_UVDU_BY2 = 0xe,
- DBG_BLOCK_ID_VCE_BY2 = 0xf,
- DBG_BLOCK_ID_VGT0_BY2 = 0x10,
- DBG_BLOCK_ID_IA_BY2 = 0x11,
- DBG_BLOCK_ID_SCT0_BY2 = 0x12,
- DBG_BLOCK_ID_SPM0_BY2 = 0x13,
- DBG_BLOCK_ID_TCAA_BY2 = 0x14,
- DBG_BLOCK_ID_TCCA_BY2 = 0x15,
- DBG_BLOCK_ID_MCC0_BY2 = 0x16,
- DBG_BLOCK_ID_MCC2_BY2 = 0x17,
- DBG_BLOCK_ID_SX0_BY2 = 0x18,
- DBG_BLOCK_ID_SX2_BY2 = 0x19,
- DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a,
- DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b,
- DBG_BLOCK_ID_PC0_BY2 = 0x1c,
- DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d,
- DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e,
- DBG_BLOCK_ID_MCB_BY2 = 0x1f,
- DBG_BLOCK_ID_SCB0_BY2 = 0x20,
- DBG_BLOCK_ID_UNUSED13_BY2 = 0x21,
- DBG_BLOCK_ID_SCF0_BY2 = 0x22,
- DBG_BLOCK_ID_UNUSED15_BY2 = 0x23,
- DBG_BLOCK_ID_BCI0_BY2 = 0x24,
- DBG_BLOCK_ID_BCI2_BY2 = 0x25,
- DBG_BLOCK_ID_UNUSED17_BY2 = 0x26,
- DBG_BLOCK_ID_UNUSED19_BY2 = 0x27,
- DBG_BLOCK_ID_CB00_BY2 = 0x28,
- DBG_BLOCK_ID_CB02_BY2 = 0x29,
- DBG_BLOCK_ID_CB04_BY2 = 0x2a,
- DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b,
- DBG_BLOCK_ID_CB10_BY2 = 0x2c,
- DBG_BLOCK_ID_CB12_BY2 = 0x2d,
- DBG_BLOCK_ID_CB14_BY2 = 0x2e,
- DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f,
- DBG_BLOCK_ID_TCP0_BY2 = 0x30,
- DBG_BLOCK_ID_TCP2_BY2 = 0x31,
- DBG_BLOCK_ID_TCP4_BY2 = 0x32,
- DBG_BLOCK_ID_TCP6_BY2 = 0x33,
- DBG_BLOCK_ID_TCP8_BY2 = 0x34,
- DBG_BLOCK_ID_TCP10_BY2 = 0x35,
- DBG_BLOCK_ID_TCP12_BY2 = 0x36,
- DBG_BLOCK_ID_TCP14_BY2 = 0x37,
- DBG_BLOCK_ID_TCP16_BY2 = 0x38,
- DBG_BLOCK_ID_TCP18_BY2 = 0x39,
- DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
- DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
- DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
- DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
- DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
- DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
- DBG_BLOCK_ID_DB00_BY2 = 0x40,
- DBG_BLOCK_ID_DB02_BY2 = 0x41,
- DBG_BLOCK_ID_DB04_BY2 = 0x42,
- DBG_BLOCK_ID_UNUSED28_BY2 = 0x43,
- DBG_BLOCK_ID_DB10_BY2 = 0x44,
- DBG_BLOCK_ID_DB12_BY2 = 0x45,
- DBG_BLOCK_ID_DB14_BY2 = 0x46,
- DBG_BLOCK_ID_UNUSED31_BY2 = 0x47,
- DBG_BLOCK_ID_TCC0_BY2 = 0x48,
- DBG_BLOCK_ID_TCC2_BY2 = 0x49,
- DBG_BLOCK_ID_TCC4_BY2 = 0x4a,
- DBG_BLOCK_ID_TCC6_BY2 = 0x4b,
- DBG_BLOCK_ID_SPS00_BY2 = 0x4c,
- DBG_BLOCK_ID_SPS02_BY2 = 0x4d,
- DBG_BLOCK_ID_SPS11_BY2 = 0x4e,
- DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f,
- DBG_BLOCK_ID_TA00_BY2 = 0x50,
- DBG_BLOCK_ID_TA02_BY2 = 0x51,
- DBG_BLOCK_ID_TA04_BY2 = 0x52,
- DBG_BLOCK_ID_TA06_BY2 = 0x53,
- DBG_BLOCK_ID_TA08_BY2 = 0x54,
- DBG_BLOCK_ID_TA0A_BY2 = 0x55,
- DBG_BLOCK_ID_UNUSED35_BY2 = 0x56,
- DBG_BLOCK_ID_UNUSED37_BY2 = 0x57,
- DBG_BLOCK_ID_TA10_BY2 = 0x58,
- DBG_BLOCK_ID_TA12_BY2 = 0x59,
- DBG_BLOCK_ID_TA14_BY2 = 0x5a,
- DBG_BLOCK_ID_TA16_BY2 = 0x5b,
- DBG_BLOCK_ID_TA18_BY2 = 0x5c,
- DBG_BLOCK_ID_TA1A_BY2 = 0x5d,
- DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e,
- DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f,
- DBG_BLOCK_ID_TD00_BY2 = 0x60,
- DBG_BLOCK_ID_TD02_BY2 = 0x61,
- DBG_BLOCK_ID_TD04_BY2 = 0x62,
- DBG_BLOCK_ID_TD06_BY2 = 0x63,
- DBG_BLOCK_ID_TD08_BY2 = 0x64,
- DBG_BLOCK_ID_TD0A_BY2 = 0x65,
- DBG_BLOCK_ID_UNUSED43_BY2 = 0x66,
- DBG_BLOCK_ID_UNUSED45_BY2 = 0x67,
- DBG_BLOCK_ID_TD10_BY2 = 0x68,
- DBG_BLOCK_ID_TD12_BY2 = 0x69,
- DBG_BLOCK_ID_TD14_BY2 = 0x6a,
- DBG_BLOCK_ID_TD16_BY2 = 0x6b,
- DBG_BLOCK_ID_TD18_BY2 = 0x6c,
- DBG_BLOCK_ID_TD1A_BY2 = 0x6d,
- DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e,
- DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f,
- DBG_BLOCK_ID_MCD0_BY2 = 0x70,
- DBG_BLOCK_ID_MCD2_BY2 = 0x71,
- DBG_BLOCK_ID_MCD4_BY2 = 0x72,
- DBG_BLOCK_ID_UNUSED51_BY2 = 0x73,
-} DebugBlockId_BY2;
-typedef enum DebugBlockId_BY4 {
- DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
- DBG_BLOCK_ID_CG_BY4 = 0x1,
- DBG_BLOCK_ID_CSC_BY4 = 0x2,
- DBG_BLOCK_ID_SQ_BY4 = 0x3,
- DBG_BLOCK_ID_DMA0_BY4 = 0x4,
- DBG_BLOCK_ID_SPIS_BY4 = 0x5,
- DBG_BLOCK_ID_CP0_BY4 = 0x6,
- DBG_BLOCK_ID_UVDU_BY4 = 0x7,
- DBG_BLOCK_ID_VGT0_BY4 = 0x8,
- DBG_BLOCK_ID_SCT0_BY4 = 0x9,
- DBG_BLOCK_ID_TCAA_BY4 = 0xa,
- DBG_BLOCK_ID_MCC0_BY4 = 0xb,
- DBG_BLOCK_ID_SX0_BY4 = 0xc,
- DBG_BLOCK_ID_UNUSED4_BY4 = 0xd,
- DBG_BLOCK_ID_PC0_BY4 = 0xe,
- DBG_BLOCK_ID_UNUSED10_BY4 = 0xf,
- DBG_BLOCK_ID_SCB0_BY4 = 0x10,
- DBG_BLOCK_ID_SCF0_BY4 = 0x11,
- DBG_BLOCK_ID_BCI0_BY4 = 0x12,
- DBG_BLOCK_ID_UNUSED17_BY4 = 0x13,
- DBG_BLOCK_ID_CB00_BY4 = 0x14,
- DBG_BLOCK_ID_CB04_BY4 = 0x15,
- DBG_BLOCK_ID_CB10_BY4 = 0x16,
- DBG_BLOCK_ID_CB14_BY4 = 0x17,
- DBG_BLOCK_ID_TCP0_BY4 = 0x18,
- DBG_BLOCK_ID_TCP4_BY4 = 0x19,
- DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
- DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
- DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
- DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
- DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
- DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
- DBG_BLOCK_ID_DB_BY4 = 0x20,
- DBG_BLOCK_ID_DB04_BY4 = 0x21,
- DBG_BLOCK_ID_DB10_BY4 = 0x22,
- DBG_BLOCK_ID_DB14_BY4 = 0x23,
- DBG_BLOCK_ID_TCC0_BY4 = 0x24,
- DBG_BLOCK_ID_TCC4_BY4 = 0x25,
- DBG_BLOCK_ID_SPS00_BY4 = 0x26,
- DBG_BLOCK_ID_SPS11_BY4 = 0x27,
- DBG_BLOCK_ID_TA00_BY4 = 0x28,
- DBG_BLOCK_ID_TA04_BY4 = 0x29,
- DBG_BLOCK_ID_TA08_BY4 = 0x2a,
- DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b,
- DBG_BLOCK_ID_TA10_BY4 = 0x2c,
- DBG_BLOCK_ID_TA14_BY4 = 0x2d,
- DBG_BLOCK_ID_TA18_BY4 = 0x2e,
- DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f,
- DBG_BLOCK_ID_TD00_BY4 = 0x30,
- DBG_BLOCK_ID_TD04_BY4 = 0x31,
- DBG_BLOCK_ID_TD08_BY4 = 0x32,
- DBG_BLOCK_ID_UNUSED43_BY4 = 0x33,
- DBG_BLOCK_ID_TD10_BY4 = 0x34,
- DBG_BLOCK_ID_TD14_BY4 = 0x35,
- DBG_BLOCK_ID_TD18_BY4 = 0x36,
- DBG_BLOCK_ID_UNUSED47_BY4 = 0x37,
- DBG_BLOCK_ID_MCD0_BY4 = 0x38,
- DBG_BLOCK_ID_MCD4_BY4 = 0x39,
-} DebugBlockId_BY4;
-typedef enum DebugBlockId_BY8 {
- DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
- DBG_BLOCK_ID_CSC_BY8 = 0x1,
- DBG_BLOCK_ID_DMA0_BY8 = 0x2,
- DBG_BLOCK_ID_CP0_BY8 = 0x3,
- DBG_BLOCK_ID_VGT0_BY8 = 0x4,
- DBG_BLOCK_ID_TCAA_BY8 = 0x5,
- DBG_BLOCK_ID_SX0_BY8 = 0x6,
- DBG_BLOCK_ID_PC0_BY8 = 0x7,
- DBG_BLOCK_ID_SCB0_BY8 = 0x8,
- DBG_BLOCK_ID_BCI0_BY8 = 0x9,
- DBG_BLOCK_ID_CB00_BY8 = 0xa,
- DBG_BLOCK_ID_CB10_BY8 = 0xb,
- DBG_BLOCK_ID_TCP0_BY8 = 0xc,
- DBG_BLOCK_ID_TCP8_BY8 = 0xd,
- DBG_BLOCK_ID_TCP16_BY8 = 0xe,
- DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
- DBG_BLOCK_ID_DB00_BY8 = 0x10,
- DBG_BLOCK_ID_DB10_BY8 = 0x11,
- DBG_BLOCK_ID_TCC0_BY8 = 0x12,
- DBG_BLOCK_ID_SPS00_BY8 = 0x13,
- DBG_BLOCK_ID_TA00_BY8 = 0x14,
- DBG_BLOCK_ID_TA08_BY8 = 0x15,
- DBG_BLOCK_ID_TA10_BY8 = 0x16,
- DBG_BLOCK_ID_TA18_BY8 = 0x17,
- DBG_BLOCK_ID_TD00_BY8 = 0x18,
- DBG_BLOCK_ID_TD08_BY8 = 0x19,
- DBG_BLOCK_ID_TD10_BY8 = 0x1a,
- DBG_BLOCK_ID_TD18_BY8 = 0x1b,
- DBG_BLOCK_ID_MCD0_BY8 = 0x1c,
-} DebugBlockId_BY8;
-typedef enum DebugBlockId_BY16 {
- DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
- DBG_BLOCK_ID_DMA0_BY16 = 0x1,
- DBG_BLOCK_ID_VGT0_BY16 = 0x2,
- DBG_BLOCK_ID_SX0_BY16 = 0x3,
- DBG_BLOCK_ID_SCB0_BY16 = 0x4,
- DBG_BLOCK_ID_CB00_BY16 = 0x5,
- DBG_BLOCK_ID_TCP0_BY16 = 0x6,
- DBG_BLOCK_ID_TCP16_BY16 = 0x7,
- DBG_BLOCK_ID_DB00_BY16 = 0x8,
- DBG_BLOCK_ID_TCC0_BY16 = 0x9,
- DBG_BLOCK_ID_TA00_BY16 = 0xa,
- DBG_BLOCK_ID_TA10_BY16 = 0xb,
- DBG_BLOCK_ID_TD00_BY16 = 0xc,
- DBG_BLOCK_ID_TD10_BY16 = 0xd,
- DBG_BLOCK_ID_MCD0_BY16 = 0xe,
-} DebugBlockId_BY16;
-typedef enum ColorTransform {
- DCC_CT_AUTO = 0x0,
- DCC_CT_NONE = 0x1,
- ABGR_TO_A_BG_G_RB = 0x2,
- BGRA_TO_BG_G_RB_A = 0x3,
-} ColorTransform;
-typedef enum CompareRef {
- REF_NEVER = 0x0,
- REF_LESS = 0x1,
- REF_EQUAL = 0x2,
- REF_LEQUAL = 0x3,
- REF_GREATER = 0x4,
- REF_NOTEQUAL = 0x5,
- REF_GEQUAL = 0x6,
- REF_ALWAYS = 0x7,
-} CompareRef;
-typedef enum ReadSize {
- READ_256_BITS = 0x0,
- READ_512_BITS = 0x1,
-} ReadSize;
-typedef enum DepthFormat {
- DEPTH_INVALID = 0x0,
- DEPTH_16 = 0x1,
- DEPTH_X8_24 = 0x2,
- DEPTH_8_24 = 0x3,
- DEPTH_X8_24_FLOAT = 0x4,
- DEPTH_8_24_FLOAT = 0x5,
- DEPTH_32_FLOAT = 0x6,
- DEPTH_X24_8_32_FLOAT = 0x7,
-} DepthFormat;
-typedef enum ZFormat {
- Z_INVALID = 0x0,
- Z_16 = 0x1,
- Z_24 = 0x2,
- Z_32_FLOAT = 0x3,
-} ZFormat;
-typedef enum StencilFormat {
- STENCIL_INVALID = 0x0,
- STENCIL_8 = 0x1,
-} StencilFormat;
-typedef enum CmaskMode {
- CMASK_CLEAR_NONE = 0x0,
- CMASK_CLEAR_ONE = 0x1,
- CMASK_CLEAR_ALL = 0x2,
- CMASK_ANY_EXPANDED = 0x3,
- CMASK_ALPHA0_FRAG1 = 0x4,
- CMASK_ALPHA0_FRAG2 = 0x5,
- CMASK_ALPHA0_FRAG4 = 0x6,
- CMASK_ALPHA0_FRAGS = 0x7,
- CMASK_ALPHA1_FRAG1 = 0x8,
- CMASK_ALPHA1_FRAG2 = 0x9,
- CMASK_ALPHA1_FRAG4 = 0xa,
- CMASK_ALPHA1_FRAGS = 0xb,
- CMASK_ALPHAX_FRAG1 = 0xc,
- CMASK_ALPHAX_FRAG2 = 0xd,
- CMASK_ALPHAX_FRAG4 = 0xe,
- CMASK_ALPHAX_FRAGS = 0xf,
-} CmaskMode;
-typedef enum QuadExportFormat {
- EXPORT_UNUSED = 0x0,
- EXPORT_32_R = 0x1,
- EXPORT_32_GR = 0x2,
- EXPORT_32_AR = 0x3,
- EXPORT_FP16_ABGR = 0x4,
- EXPORT_UNSIGNED16_ABGR = 0x5,
- EXPORT_SIGNED16_ABGR = 0x6,
- EXPORT_32_ABGR = 0x7,
-} QuadExportFormat;
-typedef enum QuadExportFormatOld {
- EXPORT_4P_32BPC_ABGR = 0x0,
- EXPORT_4P_16BPC_ABGR = 0x1,
- EXPORT_4P_32BPC_GR = 0x2,
- EXPORT_4P_32BPC_AR = 0x3,
- EXPORT_2P_32BPC_ABGR = 0x4,
- EXPORT_8P_32BPC_R = 0x5,
-} QuadExportFormatOld;
-typedef enum ColorFormat {
- COLOR_INVALID = 0x0,
- COLOR_8 = 0x1,
- COLOR_16 = 0x2,
- COLOR_8_8 = 0x3,
- COLOR_32 = 0x4,
- COLOR_16_16 = 0x5,
- COLOR_10_11_11 = 0x6,
- COLOR_11_11_10 = 0x7,
- COLOR_10_10_10_2 = 0x8,
- COLOR_2_10_10_10 = 0x9,
- COLOR_8_8_8_8 = 0xa,
- COLOR_32_32 = 0xb,
- COLOR_16_16_16_16 = 0xc,
- COLOR_RESERVED_13 = 0xd,
- COLOR_32_32_32_32 = 0xe,
- COLOR_RESERVED_15 = 0xf,
- COLOR_5_6_5 = 0x10,
- COLOR_1_5_5_5 = 0x11,
- COLOR_5_5_5_1 = 0x12,
- COLOR_4_4_4_4 = 0x13,
- COLOR_8_24 = 0x14,
- COLOR_24_8 = 0x15,
- COLOR_X24_8_32_FLOAT = 0x16,
- COLOR_RESERVED_23 = 0x17,
-} ColorFormat;
-typedef enum SurfaceFormat {
- FMT_INVALID = 0x0,
- FMT_8 = 0x1,
- FMT_16 = 0x2,
- FMT_8_8 = 0x3,
- FMT_32 = 0x4,
- FMT_16_16 = 0x5,
- FMT_10_11_11 = 0x6,
- FMT_11_11_10 = 0x7,
- FMT_10_10_10_2 = 0x8,
- FMT_2_10_10_10 = 0x9,
- FMT_8_8_8_8 = 0xa,
- FMT_32_32 = 0xb,
- FMT_16_16_16_16 = 0xc,
- FMT_32_32_32 = 0xd,
- FMT_32_32_32_32 = 0xe,
- FMT_RESERVED_4 = 0xf,
- FMT_5_6_5 = 0x10,
- FMT_1_5_5_5 = 0x11,
- FMT_5_5_5_1 = 0x12,
- FMT_4_4_4_4 = 0x13,
- FMT_8_24 = 0x14,
- FMT_24_8 = 0x15,
- FMT_X24_8_32_FLOAT = 0x16,
- FMT_RESERVED_33 = 0x17,
- FMT_11_11_10_FLOAT = 0x18,
- FMT_16_FLOAT = 0x19,
- FMT_32_FLOAT = 0x1a,
- FMT_16_16_FLOAT = 0x1b,
- FMT_8_24_FLOAT = 0x1c,
- FMT_24_8_FLOAT = 0x1d,
- FMT_32_32_FLOAT = 0x1e,
- FMT_10_11_11_FLOAT = 0x1f,
- FMT_16_16_16_16_FLOAT = 0x20,
- FMT_3_3_2 = 0x21,
- FMT_6_5_5 = 0x22,
- FMT_32_32_32_32_FLOAT = 0x23,
- FMT_RESERVED_36 = 0x24,
- FMT_1 = 0x25,
- FMT_1_REVERSED = 0x26,
- FMT_GB_GR = 0x27,
- FMT_BG_RG = 0x28,
- FMT_32_AS_8 = 0x29,
- FMT_32_AS_8_8 = 0x2a,
- FMT_5_9_9_9_SHAREDEXP = 0x2b,
- FMT_8_8_8 = 0x2c,
- FMT_16_16_16 = 0x2d,
- FMT_16_16_16_FLOAT = 0x2e,
- FMT_4_4 = 0x2f,
- FMT_32_32_32_FLOAT = 0x30,
- FMT_BC1 = 0x31,
- FMT_BC2 = 0x32,
- FMT_BC3 = 0x33,
- FMT_BC4 = 0x34,
- FMT_BC5 = 0x35,
- FMT_BC6 = 0x36,
- FMT_BC7 = 0x37,
- FMT_32_AS_32_32_32_32 = 0x38,
- FMT_APC3 = 0x39,
- FMT_APC4 = 0x3a,
- FMT_APC5 = 0x3b,
- FMT_APC6 = 0x3c,
- FMT_APC7 = 0x3d,
- FMT_CTX1 = 0x3e,
- FMT_RESERVED_63 = 0x3f,
-} SurfaceFormat;
-typedef enum BUF_DATA_FORMAT {
- BUF_DATA_FORMAT_INVALID = 0x0,
- BUF_DATA_FORMAT_8 = 0x1,
- BUF_DATA_FORMAT_16 = 0x2,
- BUF_DATA_FORMAT_8_8 = 0x3,
- BUF_DATA_FORMAT_32 = 0x4,
- BUF_DATA_FORMAT_16_16 = 0x5,
- BUF_DATA_FORMAT_10_11_11 = 0x6,
- BUF_DATA_FORMAT_11_11_10 = 0x7,
- BUF_DATA_FORMAT_10_10_10_2 = 0x8,
- BUF_DATA_FORMAT_2_10_10_10 = 0x9,
- BUF_DATA_FORMAT_8_8_8_8 = 0xa,
- BUF_DATA_FORMAT_32_32 = 0xb,
- BUF_DATA_FORMAT_16_16_16_16 = 0xc,
- BUF_DATA_FORMAT_32_32_32 = 0xd,
- BUF_DATA_FORMAT_32_32_32_32 = 0xe,
- BUF_DATA_FORMAT_RESERVED_15 = 0xf,
-} BUF_DATA_FORMAT;
-typedef enum IMG_DATA_FORMAT {
- IMG_DATA_FORMAT_INVALID = 0x0,
- IMG_DATA_FORMAT_8 = 0x1,
- IMG_DATA_FORMAT_16 = 0x2,
- IMG_DATA_FORMAT_8_8 = 0x3,
- IMG_DATA_FORMAT_32 = 0x4,
- IMG_DATA_FORMAT_16_16 = 0x5,
- IMG_DATA_FORMAT_10_11_11 = 0x6,
- IMG_DATA_FORMAT_11_11_10 = 0x7,
- IMG_DATA_FORMAT_10_10_10_2 = 0x8,
- IMG_DATA_FORMAT_2_10_10_10 = 0x9,
- IMG_DATA_FORMAT_8_8_8_8 = 0xa,
- IMG_DATA_FORMAT_32_32 = 0xb,
- IMG_DATA_FORMAT_16_16_16_16 = 0xc,
- IMG_DATA_FORMAT_32_32_32 = 0xd,
- IMG_DATA_FORMAT_32_32_32_32 = 0xe,
- IMG_DATA_FORMAT_RESERVED_15 = 0xf,
- IMG_DATA_FORMAT_5_6_5 = 0x10,
- IMG_DATA_FORMAT_1_5_5_5 = 0x11,
- IMG_DATA_FORMAT_5_5_5_1 = 0x12,
- IMG_DATA_FORMAT_4_4_4_4 = 0x13,
- IMG_DATA_FORMAT_8_24 = 0x14,
- IMG_DATA_FORMAT_24_8 = 0x15,
- IMG_DATA_FORMAT_X24_8_32 = 0x16,
- IMG_DATA_FORMAT_RESERVED_23 = 0x17,
- IMG_DATA_FORMAT_RESERVED_24 = 0x18,
- IMG_DATA_FORMAT_RESERVED_25 = 0x19,
- IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
- IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
- IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
- IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
- IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
- IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
- IMG_DATA_FORMAT_GB_GR = 0x20,
- IMG_DATA_FORMAT_BG_RG = 0x21,
- IMG_DATA_FORMAT_5_9_9_9 = 0x22,
- IMG_DATA_FORMAT_BC1 = 0x23,
- IMG_DATA_FORMAT_BC2 = 0x24,
- IMG_DATA_FORMAT_BC3 = 0x25,
- IMG_DATA_FORMAT_BC4 = 0x26,
- IMG_DATA_FORMAT_BC5 = 0x27,
- IMG_DATA_FORMAT_BC6 = 0x28,
- IMG_DATA_FORMAT_BC7 = 0x29,
- IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
- IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
- IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
- IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
- IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
- IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
- IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
- IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
- IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
- IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
- IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
- IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
- IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
- IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
- IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
- IMG_DATA_FORMAT_4_4 = 0x39,
- IMG_DATA_FORMAT_6_5_5 = 0x3a,
- IMG_DATA_FORMAT_1 = 0x3b,
- IMG_DATA_FORMAT_1_REVERSED = 0x3c,
- IMG_DATA_FORMAT_32_AS_8 = 0x3d,
- IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
- IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
-} IMG_DATA_FORMAT;
-typedef enum BUF_NUM_FORMAT {
- BUF_NUM_FORMAT_UNORM = 0x0,
- BUF_NUM_FORMAT_SNORM = 0x1,
- BUF_NUM_FORMAT_USCALED = 0x2,
- BUF_NUM_FORMAT_SSCALED = 0x3,
- BUF_NUM_FORMAT_UINT = 0x4,
- BUF_NUM_FORMAT_SINT = 0x5,
- BUF_NUM_FORMAT_RESERVED_6 = 0x6,
- BUF_NUM_FORMAT_FLOAT = 0x7,
-} BUF_NUM_FORMAT;
-typedef enum IMG_NUM_FORMAT {
- IMG_NUM_FORMAT_UNORM = 0x0,
- IMG_NUM_FORMAT_SNORM = 0x1,
- IMG_NUM_FORMAT_USCALED = 0x2,
- IMG_NUM_FORMAT_SSCALED = 0x3,
- IMG_NUM_FORMAT_UINT = 0x4,
- IMG_NUM_FORMAT_SINT = 0x5,
- IMG_NUM_FORMAT_RESERVED_6 = 0x6,
- IMG_NUM_FORMAT_FLOAT = 0x7,
- IMG_NUM_FORMAT_RESERVED_8 = 0x8,
- IMG_NUM_FORMAT_SRGB = 0x9,
- IMG_NUM_FORMAT_RESERVED_10 = 0xa,
- IMG_NUM_FORMAT_RESERVED_11 = 0xb,
- IMG_NUM_FORMAT_RESERVED_12 = 0xc,
- IMG_NUM_FORMAT_RESERVED_13 = 0xd,
- IMG_NUM_FORMAT_RESERVED_14 = 0xe,
- IMG_NUM_FORMAT_RESERVED_15 = 0xf,
-} IMG_NUM_FORMAT;
-typedef enum TileType {
- ARRAY_COLOR_TILE = 0x0,
- ARRAY_DEPTH_TILE = 0x1,
-} TileType;
-typedef enum NonDispTilingOrder {
- ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
- ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
-} NonDispTilingOrder;
-typedef enum MicroTileMode {
- ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
- ADDR_SURF_THIN_MICRO_TILING = 0x1,
- ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
- ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
- ADDR_SURF_THICK_MICRO_TILING = 0x4,
-} MicroTileMode;
-typedef enum TileSplit {
- ADDR_SURF_TILE_SPLIT_64B = 0x0,
- ADDR_SURF_TILE_SPLIT_128B = 0x1,
- ADDR_SURF_TILE_SPLIT_256B = 0x2,
- ADDR_SURF_TILE_SPLIT_512B = 0x3,
- ADDR_SURF_TILE_SPLIT_1KB = 0x4,
- ADDR_SURF_TILE_SPLIT_2KB = 0x5,
- ADDR_SURF_TILE_SPLIT_4KB = 0x6,
-} TileSplit;
-typedef enum SampleSplit {
- ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
- ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
- ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
- ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
-} SampleSplit;
-typedef enum PipeConfig {
- ADDR_SURF_P2 = 0x0,
- ADDR_SURF_P2_RESERVED0 = 0x1,
- ADDR_SURF_P2_RESERVED1 = 0x2,
- ADDR_SURF_P2_RESERVED2 = 0x3,
- ADDR_SURF_P4_8x16 = 0x4,
- ADDR_SURF_P4_16x16 = 0x5,
- ADDR_SURF_P4_16x32 = 0x6,
- ADDR_SURF_P4_32x32 = 0x7,
- ADDR_SURF_P8_16x16_8x16 = 0x8,
- ADDR_SURF_P8_16x32_8x16 = 0x9,
- ADDR_SURF_P8_32x32_8x16 = 0xa,
- ADDR_SURF_P8_16x32_16x16 = 0xb,
- ADDR_SURF_P8_32x32_16x16 = 0xc,
- ADDR_SURF_P8_32x32_16x32 = 0xd,
- ADDR_SURF_P8_32x64_32x32 = 0xe,
- ADDR_SURF_P8_RESERVED0 = 0xf,
- ADDR_SURF_P16_32x32_8x16 = 0x10,
- ADDR_SURF_P16_32x32_16x16 = 0x11,
-} PipeConfig;
-typedef enum NumBanks {
- ADDR_SURF_2_BANK = 0x0,
- ADDR_SURF_4_BANK = 0x1,
- ADDR_SURF_8_BANK = 0x2,
- ADDR_SURF_16_BANK = 0x3,
-} NumBanks;
-typedef enum BankWidth {
- ADDR_SURF_BANK_WIDTH_1 = 0x0,
- ADDR_SURF_BANK_WIDTH_2 = 0x1,
- ADDR_SURF_BANK_WIDTH_4 = 0x2,
- ADDR_SURF_BANK_WIDTH_8 = 0x3,
-} BankWidth;
-typedef enum BankHeight {
- ADDR_SURF_BANK_HEIGHT_1 = 0x0,
- ADDR_SURF_BANK_HEIGHT_2 = 0x1,
- ADDR_SURF_BANK_HEIGHT_4 = 0x2,
- ADDR_SURF_BANK_HEIGHT_8 = 0x3,
-} BankHeight;
-typedef enum BankWidthHeight {
- ADDR_SURF_BANK_WH_1 = 0x0,
- ADDR_SURF_BANK_WH_2 = 0x1,
- ADDR_SURF_BANK_WH_4 = 0x2,
- ADDR_SURF_BANK_WH_8 = 0x3,
-} BankWidthHeight;
-typedef enum MacroTileAspect {
- ADDR_SURF_MACRO_ASPECT_1 = 0x0,
- ADDR_SURF_MACRO_ASPECT_2 = 0x1,
- ADDR_SURF_MACRO_ASPECT_4 = 0x2,
- ADDR_SURF_MACRO_ASPECT_8 = 0x3,
-} MacroTileAspect;
-typedef enum GATCL1RequestType {
- GATCL1_TYPE_NORMAL = 0x0,
- GATCL1_TYPE_SHOOTDOWN = 0x1,
- GATCL1_TYPE_BYPASS = 0x2,
-} GATCL1RequestType;
-typedef enum TCC_CACHE_POLICIES {
- TCC_CACHE_POLICY_LRU = 0x0,
- TCC_CACHE_POLICY_STREAM = 0x1,
-} TCC_CACHE_POLICIES;
-typedef enum MTYPE {
- MTYPE_NC_NV = 0x0,
- MTYPE_NC = 0x1,
- MTYPE_CC = 0x2,
- MTYPE_UC = 0x3,
-} MTYPE;
-typedef enum PERFMON_COUNTER_MODE {
- PERFMON_COUNTER_MODE_ACCUM = 0x0,
- PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
- PERFMON_COUNTER_MODE_MAX = 0x2,
- PERFMON_COUNTER_MODE_DIRTY = 0x3,
- PERFMON_COUNTER_MODE_SAMPLE = 0x4,
- PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
- PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
- PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
- PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
- PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
- PERFMON_COUNTER_MODE_RESERVED = 0xf,
-} PERFMON_COUNTER_MODE;
-typedef enum PERFMON_SPM_MODE {
- PERFMON_SPM_MODE_OFF = 0x0,
- PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
- PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
- PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
- PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
- PERFMON_SPM_MODE_RESERVED_5 = 0x5,
- PERFMON_SPM_MODE_RESERVED_6 = 0x6,
- PERFMON_SPM_MODE_RESERVED_7 = 0x7,
- PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
- PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
- PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
-} PERFMON_SPM_MODE;
-typedef enum SurfaceTiling {
- ARRAY_LINEAR = 0x0,
- ARRAY_TILED = 0x1,
-} SurfaceTiling;
-typedef enum SurfaceArray {
- ARRAY_1D = 0x0,
- ARRAY_2D = 0x1,
- ARRAY_3D = 0x2,
- ARRAY_3D_SLICE = 0x3,
-} SurfaceArray;
-typedef enum ColorArray {
- ARRAY_2D_ALT_COLOR = 0x0,
- ARRAY_2D_COLOR = 0x1,
- ARRAY_3D_SLICE_COLOR = 0x3,
-} ColorArray;
-typedef enum DepthArray {
- ARRAY_2D_ALT_DEPTH = 0x0,
- ARRAY_2D_DEPTH = 0x1,
-} DepthArray;
-typedef enum ENUM_NUM_SIMD_PER_CU {
- NUM_SIMD_PER_CU = 0x4,
-} ENUM_NUM_SIMD_PER_CU;
-typedef enum MEM_PWR_FORCE_CTRL {
- NO_FORCE_REQUEST = 0x0,
- FORCE_LIGHT_SLEEP_REQUEST = 0x1,
- FORCE_DEEP_SLEEP_REQUEST = 0x2,
- FORCE_SHUT_DOWN_REQUEST = 0x3,
-} MEM_PWR_FORCE_CTRL;
-typedef enum MEM_PWR_FORCE_CTRL2 {
- NO_FORCE_REQ = 0x0,
- FORCE_LIGHT_SLEEP_REQ = 0x1,
-} MEM_PWR_FORCE_CTRL2;
-typedef enum MEM_PWR_DIS_CTRL {
- ENABLE_MEM_PWR_CTRL = 0x0,
- DISABLE_MEM_PWR_CTRL = 0x1,
-} MEM_PWR_DIS_CTRL;
-typedef enum MEM_PWR_SEL_CTRL {
- DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
- DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
- DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
-} MEM_PWR_SEL_CTRL;
-typedef enum MEM_PWR_SEL_CTRL2 {
- DYNAMIC_DEEP_SLEEP_EN = 0x0,
- DYNAMIC_LIGHT_SLEEP_EN = 0x1,
-} MEM_PWR_SEL_CTRL2;
-
-#endif /* SMU_7_1_2_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_enum.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_enum.h
deleted file mode 100644
index f19c4208d..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_enum.h
+++ /dev/null
@@ -1,1282 +0,0 @@
-/*
- * SMU_7_1_3 Register documentation
- *
- * Copyright (C) 2014 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef SMU_7_1_3_ENUM_H
-#define SMU_7_1_3_ENUM_H
-
-#define CG_SRBM_START_ADDR 0x600
-#define CG_SRBM_END_ADDR 0x8ff
-#define RCU_CCF_DWORDS0 0xa0
-#define RCU_CCF_BITS0 0x1400
-#define RCU_SAM_BYTES 0x2c
-#define RCU_SAM_RTL_BYTES 0x2c
-#define RCU_SMU_BYTES 0x14
-#define RCU_SMU_RTL_BYTES 0x14
-#define SFP_CHAIN_ADDR 0x1
-#define SFP_SADR 0x0
-#define SFP_EADR 0x37f
-#define SAMU_KEY_CHAIN_ADR 0x0
-#define SAMU_KEY_SADR 0x280
-#define SAMU_KEY_EADR 0x2ab
-#define SMU_KEY_CHAIN_ADR 0x0
-#define SMU_KEY_SADR 0x2ac
-#define SMU_KEY_EADR 0x2bf
-#define SMC_MSG_TEST 0x1
-#define SMC_MSG_PHY_LN_OFF 0x2
-#define SMC_MSG_PHY_LN_ON 0x3
-#define SMC_MSG_DDI_PHY_OFF 0x4
-#define SMC_MSG_DDI_PHY_ON 0x5
-#define SMC_MSG_CASCADE_PLL_OFF 0x6
-#define SMC_MSG_CASCADE_PLL_ON 0x7
-#define SMC_MSG_PWR_OFF_x16 0x8
-#define SMC_MSG_CONFIG_LCLK_DPM 0x9
-#define SMC_MSG_FLUSH_DATA_CACHE 0xa
-#define SMC_MSG_FLUSH_INSTRUCTION_CACHE 0xb
-#define SMC_MSG_CONFIG_VPC_ACCUMULATOR 0xc
-#define SMC_MSG_CONFIG_BAPM 0xd
-#define SMC_MSG_CONFIG_TDC_LIMIT 0xe
-#define SMC_MSG_CONFIG_LPMx 0xf
-#define SMC_MSG_CONFIG_HTC_LIMIT 0x10
-#define SMC_MSG_CONFIG_THERMAL_CNTL 0x11
-#define SMC_MSG_CONFIG_VOLTAGE_CNTL 0x12
-#define SMC_MSG_CONFIG_TDP_CNTL 0x13
-#define SMC_MSG_EN_PM_CNTL 0x14
-#define SMC_MSG_DIS_PM_CNTL 0x15
-#define SMC_MSG_CONFIG_NBDPM 0x16
-#define SMC_MSG_CONFIG_LOADLINE 0x17
-#define SMC_MSG_ADJUST_LOADLINE 0x18
-#define SMC_MSG_RESET 0x20
-#define SMC_MSG_VOLTAGE 0x25
-#define SMC_VERSION_MAJOR 0x7
-#define SMC_VERSION_MINOR 0x0
-#define SMC_HEADER_SIZE 0x40
-#define ROM_SIGNATURE 0xaa55
-typedef enum SurfaceEndian {
- ENDIAN_NONE = 0x0,
- ENDIAN_8IN16 = 0x1,
- ENDIAN_8IN32 = 0x2,
- ENDIAN_8IN64 = 0x3,
-} SurfaceEndian;
-typedef enum ArrayMode {
- ARRAY_LINEAR_GENERAL = 0x0,
- ARRAY_LINEAR_ALIGNED = 0x1,
- ARRAY_1D_TILED_THIN1 = 0x2,
- ARRAY_1D_TILED_THICK = 0x3,
- ARRAY_2D_TILED_THIN1 = 0x4,
- ARRAY_PRT_TILED_THIN1 = 0x5,
- ARRAY_PRT_2D_TILED_THIN1 = 0x6,
- ARRAY_2D_TILED_THICK = 0x7,
- ARRAY_2D_TILED_XTHICK = 0x8,
- ARRAY_PRT_TILED_THICK = 0x9,
- ARRAY_PRT_2D_TILED_THICK = 0xa,
- ARRAY_PRT_3D_TILED_THIN1 = 0xb,
- ARRAY_3D_TILED_THIN1 = 0xc,
- ARRAY_3D_TILED_THICK = 0xd,
- ARRAY_3D_TILED_XTHICK = 0xe,
- ARRAY_PRT_3D_TILED_THICK = 0xf,
-} ArrayMode;
-typedef enum PipeTiling {
- CONFIG_1_PIPE = 0x0,
- CONFIG_2_PIPE = 0x1,
- CONFIG_4_PIPE = 0x2,
- CONFIG_8_PIPE = 0x3,
-} PipeTiling;
-typedef enum BankTiling {
- CONFIG_4_BANK = 0x0,
- CONFIG_8_BANK = 0x1,
-} BankTiling;
-typedef enum GroupInterleave {
- CONFIG_256B_GROUP = 0x0,
- CONFIG_512B_GROUP = 0x1,
-} GroupInterleave;
-typedef enum RowTiling {
- CONFIG_1KB_ROW = 0x0,
- CONFIG_2KB_ROW = 0x1,
- CONFIG_4KB_ROW = 0x2,
- CONFIG_8KB_ROW = 0x3,
- CONFIG_1KB_ROW_OPT = 0x4,
- CONFIG_2KB_ROW_OPT = 0x5,
- CONFIG_4KB_ROW_OPT = 0x6,
- CONFIG_8KB_ROW_OPT = 0x7,
-} RowTiling;
-typedef enum BankSwapBytes {
- CONFIG_128B_SWAPS = 0x0,
- CONFIG_256B_SWAPS = 0x1,
- CONFIG_512B_SWAPS = 0x2,
- CONFIG_1KB_SWAPS = 0x3,
-} BankSwapBytes;
-typedef enum SampleSplitBytes {
- CONFIG_1KB_SPLIT = 0x0,
- CONFIG_2KB_SPLIT = 0x1,
- CONFIG_4KB_SPLIT = 0x2,
- CONFIG_8KB_SPLIT = 0x3,
-} SampleSplitBytes;
-typedef enum NumPipes {
- ADDR_CONFIG_1_PIPE = 0x0,
- ADDR_CONFIG_2_PIPE = 0x1,
- ADDR_CONFIG_4_PIPE = 0x2,
- ADDR_CONFIG_8_PIPE = 0x3,
-} NumPipes;
-typedef enum PipeInterleaveSize {
- ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
- ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
-} PipeInterleaveSize;
-typedef enum BankInterleaveSize {
- ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
- ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
- ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
- ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
-} BankInterleaveSize;
-typedef enum NumShaderEngines {
- ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
- ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
-} NumShaderEngines;
-typedef enum ShaderEngineTileSize {
- ADDR_CONFIG_SE_TILE_16 = 0x0,
- ADDR_CONFIG_SE_TILE_32 = 0x1,
-} ShaderEngineTileSize;
-typedef enum NumGPUs {
- ADDR_CONFIG_1_GPU = 0x0,
- ADDR_CONFIG_2_GPU = 0x1,
- ADDR_CONFIG_4_GPU = 0x2,
-} NumGPUs;
-typedef enum MultiGPUTileSize {
- ADDR_CONFIG_GPU_TILE_16 = 0x0,
- ADDR_CONFIG_GPU_TILE_32 = 0x1,
- ADDR_CONFIG_GPU_TILE_64 = 0x2,
- ADDR_CONFIG_GPU_TILE_128 = 0x3,
-} MultiGPUTileSize;
-typedef enum RowSize {
- ADDR_CONFIG_1KB_ROW = 0x0,
- ADDR_CONFIG_2KB_ROW = 0x1,
- ADDR_CONFIG_4KB_ROW = 0x2,
-} RowSize;
-typedef enum NumLowerPipes {
- ADDR_CONFIG_1_LOWER_PIPES = 0x0,
- ADDR_CONFIG_2_LOWER_PIPES = 0x1,
-} NumLowerPipes;
-typedef enum DebugBlockId {
- DBG_CLIENT_BLKID_RESERVED = 0x0,
- DBG_CLIENT_BLKID_dbg = 0x1,
- DBG_CLIENT_BLKID_scf2 = 0x2,
- DBG_CLIENT_BLKID_mcd5_0 = 0x3,
- DBG_CLIENT_BLKID_mcd5_1 = 0x4,
- DBG_CLIENT_BLKID_mcd6_0 = 0x5,
- DBG_CLIENT_BLKID_mcd6_1 = 0x6,
- DBG_CLIENT_BLKID_mcd7_0 = 0x7,
- DBG_CLIENT_BLKID_mcd7_1 = 0x8,
- DBG_CLIENT_BLKID_vmc = 0x9,
- DBG_CLIENT_BLKID_sx30 = 0xa,
- DBG_CLIENT_BLKID_mcd2_0 = 0xb,
- DBG_CLIENT_BLKID_mcd2_1 = 0xc,
- DBG_CLIENT_BLKID_bci1 = 0xd,
- DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0xe,
- DBG_CLIENT_BLKID_mcc0 = 0xf,
- DBG_CLIENT_BLKID_uvdf_0 = 0x10,
- DBG_CLIENT_BLKID_uvdf_1 = 0x11,
- DBG_CLIENT_BLKID_uvdf_2 = 0x12,
- DBG_CLIENT_BLKID_bci0 = 0x13,
- DBG_CLIENT_BLKID_vcec0_0 = 0x14,
- DBG_CLIENT_BLKID_cb100 = 0x15,
- DBG_CLIENT_BLKID_cb001 = 0x16,
- DBG_CLIENT_BLKID_cb002 = 0x17,
- DBG_CLIENT_BLKID_cb003 = 0x18,
- DBG_CLIENT_BLKID_mcd4_0 = 0x19,
- DBG_CLIENT_BLKID_mcd4_1 = 0x1a,
- DBG_CLIENT_BLKID_tmonw00 = 0x1b,
- DBG_CLIENT_BLKID_cb101 = 0x1c,
- DBG_CLIENT_BLKID_cb102 = 0x1d,
- DBG_CLIENT_BLKID_cb103 = 0x1e,
- DBG_CLIENT_BLKID_sx10 = 0x1f,
- DBG_CLIENT_BLKID_cb301 = 0x20,
- DBG_CLIENT_BLKID_cb302 = 0x21,
- DBG_CLIENT_BLKID_cb303 = 0x22,
- DBG_CLIENT_BLKID_tmonw01 = 0x23,
- DBG_CLIENT_BLKID_tmonw02 = 0x24,
- DBG_CLIENT_BLKID_vcea0_0 = 0x25,
- DBG_CLIENT_BLKID_vcea0_1 = 0x26,
- DBG_CLIENT_BLKID_vcea0_2 = 0x27,
- DBG_CLIENT_BLKID_vcea0_3 = 0x28,
- DBG_CLIENT_BLKID_scf1 = 0x29,
- DBG_CLIENT_BLKID_sx20 = 0x2a,
- DBG_CLIENT_BLKID_spim1 = 0x2b,
- DBG_CLIENT_BLKID_scb1 = 0x2c,
- DBG_CLIENT_BLKID_pa10 = 0x2d,
- DBG_CLIENT_BLKID_pa00 = 0x2e,
- DBG_CLIENT_BLKID_gmcon = 0x2f,
- DBG_CLIENT_BLKID_mcb = 0x30,
- DBG_CLIENT_BLKID_vgt0 = 0x31,
- DBG_CLIENT_BLKID_pc0 = 0x32,
- DBG_CLIENT_BLKID_bci2 = 0x33,
- DBG_CLIENT_BLKID_uvdb_0 = 0x34,
- DBG_CLIENT_BLKID_spim3 = 0x35,
- DBG_CLIENT_BLKID_scb3 = 0x36,
- DBG_CLIENT_BLKID_cpc_0 = 0x37,
- DBG_CLIENT_BLKID_cpc_1 = 0x38,
- DBG_CLIENT_BLKID_uvdm_0 = 0x39,
- DBG_CLIENT_BLKID_uvdm_1 = 0x3a,
- DBG_CLIENT_BLKID_uvdm_2 = 0x3b,
- DBG_CLIENT_BLKID_uvdm_3 = 0x3c,
- DBG_CLIENT_BLKID_cb000 = 0x3d,
- DBG_CLIENT_BLKID_spim0 = 0x3e,
- DBG_CLIENT_BLKID_scb0 = 0x3f,
- DBG_CLIENT_BLKID_mcc2 = 0x40,
- DBG_CLIENT_BLKID_ds0 = 0x41,
- DBG_CLIENT_BLKID_srbm = 0x42,
- DBG_CLIENT_BLKID_ih = 0x43,
- DBG_CLIENT_BLKID_sem = 0x44,
- DBG_CLIENT_BLKID_sdma_0 = 0x45,
- DBG_CLIENT_BLKID_sdma_1 = 0x46,
- DBG_CLIENT_BLKID_hdp = 0x47,
- DBG_CLIENT_BLKID_acp_0 = 0x48,
- DBG_CLIENT_BLKID_acp_1 = 0x49,
- DBG_CLIENT_BLKID_cb200 = 0x4a,
- DBG_CLIENT_BLKID_scf3 = 0x4b,
- DBG_CLIENT_BLKID_bci3 = 0x4c,
- DBG_CLIENT_BLKID_mcd0_0 = 0x4d,
- DBG_CLIENT_BLKID_mcd0_1 = 0x4e,
- DBG_CLIENT_BLKID_pa11 = 0x4f,
- DBG_CLIENT_BLKID_pa01 = 0x50,
- DBG_CLIENT_BLKID_cb201 = 0x51,
- DBG_CLIENT_BLKID_cb202 = 0x52,
- DBG_CLIENT_BLKID_cb203 = 0x53,
- DBG_CLIENT_BLKID_spim2 = 0x54,
- DBG_CLIENT_BLKID_scb2 = 0x55,
- DBG_CLIENT_BLKID_vgt2 = 0x56,
- DBG_CLIENT_BLKID_pc2 = 0x57,
- DBG_CLIENT_BLKID_smu_0 = 0x58,
- DBG_CLIENT_BLKID_smu_1 = 0x59,
- DBG_CLIENT_BLKID_smu_2 = 0x5a,
- DBG_CLIENT_BLKID_cb1 = 0x5b,
- DBG_CLIENT_BLKID_ia0 = 0x5c,
- DBG_CLIENT_BLKID_wd = 0x5d,
- DBG_CLIENT_BLKID_ia1 = 0x5e,
- DBG_CLIENT_BLKID_scf0 = 0x5f,
- DBG_CLIENT_BLKID_vgt1 = 0x60,
- DBG_CLIENT_BLKID_pc1 = 0x61,
- DBG_CLIENT_BLKID_cb0 = 0x62,
- DBG_CLIENT_BLKID_gdc_one_0 = 0x63,
- DBG_CLIENT_BLKID_gdc_one_1 = 0x64,
- DBG_CLIENT_BLKID_gdc_one_2 = 0x65,
- DBG_CLIENT_BLKID_gdc_one_3 = 0x66,
- DBG_CLIENT_BLKID_gdc_one_4 = 0x67,
- DBG_CLIENT_BLKID_gdc_one_5 = 0x68,
- DBG_CLIENT_BLKID_gdc_one_6 = 0x69,
- DBG_CLIENT_BLKID_gdc_one_7 = 0x6a,
- DBG_CLIENT_BLKID_gdc_one_8 = 0x6b,
- DBG_CLIENT_BLKID_gdc_one_9 = 0x6c,
- DBG_CLIENT_BLKID_gdc_one_10 = 0x6d,
- DBG_CLIENT_BLKID_gdc_one_11 = 0x6e,
- DBG_CLIENT_BLKID_gdc_one_12 = 0x6f,
- DBG_CLIENT_BLKID_gdc_one_13 = 0x70,
- DBG_CLIENT_BLKID_gdc_one_14 = 0x71,
- DBG_CLIENT_BLKID_gdc_one_15 = 0x72,
- DBG_CLIENT_BLKID_gdc_one_16 = 0x73,
- DBG_CLIENT_BLKID_gdc_one_17 = 0x74,
- DBG_CLIENT_BLKID_gdc_one_18 = 0x75,
- DBG_CLIENT_BLKID_gdc_one_19 = 0x76,
- DBG_CLIENT_BLKID_gdc_one_20 = 0x77,
- DBG_CLIENT_BLKID_gdc_one_21 = 0x78,
- DBG_CLIENT_BLKID_gdc_one_22 = 0x79,
- DBG_CLIENT_BLKID_gdc_one_23 = 0x7a,
- DBG_CLIENT_BLKID_gdc_one_24 = 0x7b,
- DBG_CLIENT_BLKID_gdc_one_25 = 0x7c,
- DBG_CLIENT_BLKID_gdc_one_26 = 0x7d,
- DBG_CLIENT_BLKID_gdc_one_27 = 0x7e,
- DBG_CLIENT_BLKID_gdc_one_28 = 0x7f,
- DBG_CLIENT_BLKID_gdc_one_29 = 0x80,
- DBG_CLIENT_BLKID_gdc_one_30 = 0x81,
- DBG_CLIENT_BLKID_gdc_one_31 = 0x82,
- DBG_CLIENT_BLKID_gdc_one_32 = 0x83,
- DBG_CLIENT_BLKID_gdc_one_33 = 0x84,
- DBG_CLIENT_BLKID_gdc_one_34 = 0x85,
- DBG_CLIENT_BLKID_gdc_one_35 = 0x86,
- DBG_CLIENT_BLKID_vceb0_0 = 0x87,
- DBG_CLIENT_BLKID_vgt3 = 0x88,
- DBG_CLIENT_BLKID_pc3 = 0x89,
- DBG_CLIENT_BLKID_mcd3_0 = 0x8a,
- DBG_CLIENT_BLKID_mcd3_1 = 0x8b,
- DBG_CLIENT_BLKID_uvdu_0 = 0x8c,
- DBG_CLIENT_BLKID_uvdu_1 = 0x8d,
- DBG_CLIENT_BLKID_uvdu_2 = 0x8e,
- DBG_CLIENT_BLKID_uvdu_3 = 0x8f,
- DBG_CLIENT_BLKID_uvdu_4 = 0x90,
- DBG_CLIENT_BLKID_uvdu_5 = 0x91,
- DBG_CLIENT_BLKID_uvdu_6 = 0x92,
- DBG_CLIENT_BLKID_cb300 = 0x93,
- DBG_CLIENT_BLKID_mcd1_0 = 0x94,
- DBG_CLIENT_BLKID_mcd1_1 = 0x95,
- DBG_CLIENT_BLKID_sx00 = 0x96,
- DBG_CLIENT_BLKID_uvdc_0 = 0x97,
- DBG_CLIENT_BLKID_uvdc_1 = 0x98,
- DBG_CLIENT_BLKID_mcc3 = 0x99,
- DBG_CLIENT_BLKID_mcc4 = 0x9a,
- DBG_CLIENT_BLKID_mcc5 = 0x9b,
- DBG_CLIENT_BLKID_mcc6 = 0x9c,
- DBG_CLIENT_BLKID_mcc7 = 0x9d,
- DBG_CLIENT_BLKID_cpg_0 = 0x9e,
- DBG_CLIENT_BLKID_cpg_1 = 0x9f,
- DBG_CLIENT_BLKID_gck = 0xa0,
- DBG_CLIENT_BLKID_mcc1 = 0xa1,
- DBG_CLIENT_BLKID_cpf_0 = 0xa2,
- DBG_CLIENT_BLKID_cpf_1 = 0xa3,
- DBG_CLIENT_BLKID_rlc = 0xa4,
- DBG_CLIENT_BLKID_grbm = 0xa5,
- DBG_CLIENT_BLKID_sammsp = 0xa6,
- DBG_CLIENT_BLKID_dci_pg = 0xa7,
- DBG_CLIENT_BLKID_dci_0 = 0xa8,
- DBG_CLIENT_BLKID_dccg0_0 = 0xa9,
- DBG_CLIENT_BLKID_dccg0_1 = 0xaa,
- DBG_CLIENT_BLKID_dcfe01_0 = 0xab,
- DBG_CLIENT_BLKID_dcfe02_0 = 0xac,
- DBG_CLIENT_BLKID_dcfe03_0 = 0xad,
- DBG_CLIENT_BLKID_dcfe04_0 = 0xae,
- DBG_CLIENT_BLKID_dcfe05_0 = 0xaf,
- DBG_CLIENT_BLKID_dcfe06_0 = 0xb0,
- DBG_CLIENT_BLKID_mcq0_0 = 0xb1,
- DBG_CLIENT_BLKID_mcq0_1 = 0xb2,
- DBG_CLIENT_BLKID_mcq1_0 = 0xb3,
- DBG_CLIENT_BLKID_mcq1_1 = 0xb4,
- DBG_CLIENT_BLKID_mcq2_0 = 0xb5,
- DBG_CLIENT_BLKID_mcq2_1 = 0xb6,
- DBG_CLIENT_BLKID_mcq3_0 = 0xb7,
- DBG_CLIENT_BLKID_mcq3_1 = 0xb8,
- DBG_CLIENT_BLKID_mcq4_0 = 0xb9,
- DBG_CLIENT_BLKID_mcq4_1 = 0xba,
- DBG_CLIENT_BLKID_mcq5_0 = 0xbb,
- DBG_CLIENT_BLKID_mcq5_1 = 0xbc,
- DBG_CLIENT_BLKID_mcq6_0 = 0xbd,
- DBG_CLIENT_BLKID_mcq6_1 = 0xbe,
- DBG_CLIENT_BLKID_mcq7_0 = 0xbf,
- DBG_CLIENT_BLKID_mcq7_1 = 0xc0,
- DBG_CLIENT_BLKID_uvdi_0 = 0xc1,
- DBG_CLIENT_BLKID_RESERVED_LAST = 0xc2,
-} DebugBlockId;
-typedef enum DebugBlockId_OLD {
- DBG_BLOCK_ID_RESERVED = 0x0,
- DBG_BLOCK_ID_DBG = 0x1,
- DBG_BLOCK_ID_VMC = 0x2,
- DBG_BLOCK_ID_PDMA = 0x3,
- DBG_BLOCK_ID_CG = 0x4,
- DBG_BLOCK_ID_SRBM = 0x5,
- DBG_BLOCK_ID_GRBM = 0x6,
- DBG_BLOCK_ID_RLC = 0x7,
- DBG_BLOCK_ID_CSC = 0x8,
- DBG_BLOCK_ID_SEM = 0x9,
- DBG_BLOCK_ID_IH = 0xa,
- DBG_BLOCK_ID_SC = 0xb,
- DBG_BLOCK_ID_SQ = 0xc,
- DBG_BLOCK_ID_AVP = 0xd,
- DBG_BLOCK_ID_GMCON = 0xe,
- DBG_BLOCK_ID_SMU = 0xf,
- DBG_BLOCK_ID_DMA0 = 0x10,
- DBG_BLOCK_ID_DMA1 = 0x11,
- DBG_BLOCK_ID_SPIM = 0x12,
- DBG_BLOCK_ID_GDS = 0x13,
- DBG_BLOCK_ID_SPIS = 0x14,
- DBG_BLOCK_ID_UNUSED0 = 0x15,
- DBG_BLOCK_ID_PA0 = 0x16,
- DBG_BLOCK_ID_PA1 = 0x17,
- DBG_BLOCK_ID_CP0 = 0x18,
- DBG_BLOCK_ID_CP1 = 0x19,
- DBG_BLOCK_ID_CP2 = 0x1a,
- DBG_BLOCK_ID_UNUSED1 = 0x1b,
- DBG_BLOCK_ID_UVDU = 0x1c,
- DBG_BLOCK_ID_UVDM = 0x1d,
- DBG_BLOCK_ID_VCE = 0x1e,
- DBG_BLOCK_ID_UNUSED2 = 0x1f,
- DBG_BLOCK_ID_VGT0 = 0x20,
- DBG_BLOCK_ID_VGT1 = 0x21,
- DBG_BLOCK_ID_IA = 0x22,
- DBG_BLOCK_ID_UNUSED3 = 0x23,
- DBG_BLOCK_ID_SCT0 = 0x24,
- DBG_BLOCK_ID_SCT1 = 0x25,
- DBG_BLOCK_ID_SPM0 = 0x26,
- DBG_BLOCK_ID_SPM1 = 0x27,
- DBG_BLOCK_ID_TCAA = 0x28,
- DBG_BLOCK_ID_TCAB = 0x29,
- DBG_BLOCK_ID_TCCA = 0x2a,
- DBG_BLOCK_ID_TCCB = 0x2b,
- DBG_BLOCK_ID_MCC0 = 0x2c,
- DBG_BLOCK_ID_MCC1 = 0x2d,
- DBG_BLOCK_ID_MCC2 = 0x2e,
- DBG_BLOCK_ID_MCC3 = 0x2f,
- DBG_BLOCK_ID_SX0 = 0x30,
- DBG_BLOCK_ID_SX1 = 0x31,
- DBG_BLOCK_ID_SX2 = 0x32,
- DBG_BLOCK_ID_SX3 = 0x33,
- DBG_BLOCK_ID_UNUSED4 = 0x34,
- DBG_BLOCK_ID_UNUSED5 = 0x35,
- DBG_BLOCK_ID_UNUSED6 = 0x36,
- DBG_BLOCK_ID_UNUSED7 = 0x37,
- DBG_BLOCK_ID_PC0 = 0x38,
- DBG_BLOCK_ID_PC1 = 0x39,
- DBG_BLOCK_ID_UNUSED8 = 0x3a,
- DBG_BLOCK_ID_UNUSED9 = 0x3b,
- DBG_BLOCK_ID_UNUSED10 = 0x3c,
- DBG_BLOCK_ID_UNUSED11 = 0x3d,
- DBG_BLOCK_ID_MCB = 0x3e,
- DBG_BLOCK_ID_UNUSED12 = 0x3f,
- DBG_BLOCK_ID_SCB0 = 0x40,
- DBG_BLOCK_ID_SCB1 = 0x41,
- DBG_BLOCK_ID_UNUSED13 = 0x42,
- DBG_BLOCK_ID_UNUSED14 = 0x43,
- DBG_BLOCK_ID_SCF0 = 0x44,
- DBG_BLOCK_ID_SCF1 = 0x45,
- DBG_BLOCK_ID_UNUSED15 = 0x46,
- DBG_BLOCK_ID_UNUSED16 = 0x47,
- DBG_BLOCK_ID_BCI0 = 0x48,
- DBG_BLOCK_ID_BCI1 = 0x49,
- DBG_BLOCK_ID_BCI2 = 0x4a,
- DBG_BLOCK_ID_BCI3 = 0x4b,
- DBG_BLOCK_ID_UNUSED17 = 0x4c,
- DBG_BLOCK_ID_UNUSED18 = 0x4d,
- DBG_BLOCK_ID_UNUSED19 = 0x4e,
- DBG_BLOCK_ID_UNUSED20 = 0x4f,
- DBG_BLOCK_ID_CB00 = 0x50,
- DBG_BLOCK_ID_CB01 = 0x51,
- DBG_BLOCK_ID_CB02 = 0x52,
- DBG_BLOCK_ID_CB03 = 0x53,
- DBG_BLOCK_ID_CB04 = 0x54,
- DBG_BLOCK_ID_UNUSED21 = 0x55,
- DBG_BLOCK_ID_UNUSED22 = 0x56,
- DBG_BLOCK_ID_UNUSED23 = 0x57,
- DBG_BLOCK_ID_CB10 = 0x58,
- DBG_BLOCK_ID_CB11 = 0x59,
- DBG_BLOCK_ID_CB12 = 0x5a,
- DBG_BLOCK_ID_CB13 = 0x5b,
- DBG_BLOCK_ID_CB14 = 0x5c,
- DBG_BLOCK_ID_UNUSED24 = 0x5d,
- DBG_BLOCK_ID_UNUSED25 = 0x5e,
- DBG_BLOCK_ID_UNUSED26 = 0x5f,
- DBG_BLOCK_ID_TCP0 = 0x60,
- DBG_BLOCK_ID_TCP1 = 0x61,
- DBG_BLOCK_ID_TCP2 = 0x62,
- DBG_BLOCK_ID_TCP3 = 0x63,
- DBG_BLOCK_ID_TCP4 = 0x64,
- DBG_BLOCK_ID_TCP5 = 0x65,
- DBG_BLOCK_ID_TCP6 = 0x66,
- DBG_BLOCK_ID_TCP7 = 0x67,
- DBG_BLOCK_ID_TCP8 = 0x68,
- DBG_BLOCK_ID_TCP9 = 0x69,
- DBG_BLOCK_ID_TCP10 = 0x6a,
- DBG_BLOCK_ID_TCP11 = 0x6b,
- DBG_BLOCK_ID_TCP12 = 0x6c,
- DBG_BLOCK_ID_TCP13 = 0x6d,
- DBG_BLOCK_ID_TCP14 = 0x6e,
- DBG_BLOCK_ID_TCP15 = 0x6f,
- DBG_BLOCK_ID_TCP16 = 0x70,
- DBG_BLOCK_ID_TCP17 = 0x71,
- DBG_BLOCK_ID_TCP18 = 0x72,
- DBG_BLOCK_ID_TCP19 = 0x73,
- DBG_BLOCK_ID_TCP20 = 0x74,
- DBG_BLOCK_ID_TCP21 = 0x75,
- DBG_BLOCK_ID_TCP22 = 0x76,
- DBG_BLOCK_ID_TCP23 = 0x77,
- DBG_BLOCK_ID_TCP_RESERVED0 = 0x78,
- DBG_BLOCK_ID_TCP_RESERVED1 = 0x79,
- DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a,
- DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b,
- DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c,
- DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d,
- DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e,
- DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f,
- DBG_BLOCK_ID_DB00 = 0x80,
- DBG_BLOCK_ID_DB01 = 0x81,
- DBG_BLOCK_ID_DB02 = 0x82,
- DBG_BLOCK_ID_DB03 = 0x83,
- DBG_BLOCK_ID_DB04 = 0x84,
- DBG_BLOCK_ID_UNUSED27 = 0x85,
- DBG_BLOCK_ID_UNUSED28 = 0x86,
- DBG_BLOCK_ID_UNUSED29 = 0x87,
- DBG_BLOCK_ID_DB10 = 0x88,
- DBG_BLOCK_ID_DB11 = 0x89,
- DBG_BLOCK_ID_DB12 = 0x8a,
- DBG_BLOCK_ID_DB13 = 0x8b,
- DBG_BLOCK_ID_DB14 = 0x8c,
- DBG_BLOCK_ID_UNUSED30 = 0x8d,
- DBG_BLOCK_ID_UNUSED31 = 0x8e,
- DBG_BLOCK_ID_UNUSED32 = 0x8f,
- DBG_BLOCK_ID_TCC0 = 0x90,
- DBG_BLOCK_ID_TCC1 = 0x91,
- DBG_BLOCK_ID_TCC2 = 0x92,
- DBG_BLOCK_ID_TCC3 = 0x93,
- DBG_BLOCK_ID_TCC4 = 0x94,
- DBG_BLOCK_ID_TCC5 = 0x95,
- DBG_BLOCK_ID_TCC6 = 0x96,
- DBG_BLOCK_ID_TCC7 = 0x97,
- DBG_BLOCK_ID_SPS00 = 0x98,
- DBG_BLOCK_ID_SPS01 = 0x99,
- DBG_BLOCK_ID_SPS02 = 0x9a,
- DBG_BLOCK_ID_SPS10 = 0x9b,
- DBG_BLOCK_ID_SPS11 = 0x9c,
- DBG_BLOCK_ID_SPS12 = 0x9d,
- DBG_BLOCK_ID_UNUSED33 = 0x9e,
- DBG_BLOCK_ID_UNUSED34 = 0x9f,
- DBG_BLOCK_ID_TA00 = 0xa0,
- DBG_BLOCK_ID_TA01 = 0xa1,
- DBG_BLOCK_ID_TA02 = 0xa2,
- DBG_BLOCK_ID_TA03 = 0xa3,
- DBG_BLOCK_ID_TA04 = 0xa4,
- DBG_BLOCK_ID_TA05 = 0xa5,
- DBG_BLOCK_ID_TA06 = 0xa6,
- DBG_BLOCK_ID_TA07 = 0xa7,
- DBG_BLOCK_ID_TA08 = 0xa8,
- DBG_BLOCK_ID_TA09 = 0xa9,
- DBG_BLOCK_ID_TA0A = 0xaa,
- DBG_BLOCK_ID_TA0B = 0xab,
- DBG_BLOCK_ID_UNUSED35 = 0xac,
- DBG_BLOCK_ID_UNUSED36 = 0xad,
- DBG_BLOCK_ID_UNUSED37 = 0xae,
- DBG_BLOCK_ID_UNUSED38 = 0xaf,
- DBG_BLOCK_ID_TA10 = 0xb0,
- DBG_BLOCK_ID_TA11 = 0xb1,
- DBG_BLOCK_ID_TA12 = 0xb2,
- DBG_BLOCK_ID_TA13 = 0xb3,
- DBG_BLOCK_ID_TA14 = 0xb4,
- DBG_BLOCK_ID_TA15 = 0xb5,
- DBG_BLOCK_ID_TA16 = 0xb6,
- DBG_BLOCK_ID_TA17 = 0xb7,
- DBG_BLOCK_ID_TA18 = 0xb8,
- DBG_BLOCK_ID_TA19 = 0xb9,
- DBG_BLOCK_ID_TA1A = 0xba,
- DBG_BLOCK_ID_TA1B = 0xbb,
- DBG_BLOCK_ID_UNUSED39 = 0xbc,
- DBG_BLOCK_ID_UNUSED40 = 0xbd,
- DBG_BLOCK_ID_UNUSED41 = 0xbe,
- DBG_BLOCK_ID_UNUSED42 = 0xbf,
- DBG_BLOCK_ID_TD00 = 0xc0,
- DBG_BLOCK_ID_TD01 = 0xc1,
- DBG_BLOCK_ID_TD02 = 0xc2,
- DBG_BLOCK_ID_TD03 = 0xc3,
- DBG_BLOCK_ID_TD04 = 0xc4,
- DBG_BLOCK_ID_TD05 = 0xc5,
- DBG_BLOCK_ID_TD06 = 0xc6,
- DBG_BLOCK_ID_TD07 = 0xc7,
- DBG_BLOCK_ID_TD08 = 0xc8,
- DBG_BLOCK_ID_TD09 = 0xc9,
- DBG_BLOCK_ID_TD0A = 0xca,
- DBG_BLOCK_ID_TD0B = 0xcb,
- DBG_BLOCK_ID_UNUSED43 = 0xcc,
- DBG_BLOCK_ID_UNUSED44 = 0xcd,
- DBG_BLOCK_ID_UNUSED45 = 0xce,
- DBG_BLOCK_ID_UNUSED46 = 0xcf,
- DBG_BLOCK_ID_TD10 = 0xd0,
- DBG_BLOCK_ID_TD11 = 0xd1,
- DBG_BLOCK_ID_TD12 = 0xd2,
- DBG_BLOCK_ID_TD13 = 0xd3,
- DBG_BLOCK_ID_TD14 = 0xd4,
- DBG_BLOCK_ID_TD15 = 0xd5,
- DBG_BLOCK_ID_TD16 = 0xd6,
- DBG_BLOCK_ID_TD17 = 0xd7,
- DBG_BLOCK_ID_TD18 = 0xd8,
- DBG_BLOCK_ID_TD19 = 0xd9,
- DBG_BLOCK_ID_TD1A = 0xda,
- DBG_BLOCK_ID_TD1B = 0xdb,
- DBG_BLOCK_ID_UNUSED47 = 0xdc,
- DBG_BLOCK_ID_UNUSED48 = 0xdd,
- DBG_BLOCK_ID_UNUSED49 = 0xde,
- DBG_BLOCK_ID_UNUSED50 = 0xdf,
- DBG_BLOCK_ID_MCD0 = 0xe0,
- DBG_BLOCK_ID_MCD1 = 0xe1,
- DBG_BLOCK_ID_MCD2 = 0xe2,
- DBG_BLOCK_ID_MCD3 = 0xe3,
- DBG_BLOCK_ID_MCD4 = 0xe4,
- DBG_BLOCK_ID_MCD5 = 0xe5,
- DBG_BLOCK_ID_UNUSED51 = 0xe6,
- DBG_BLOCK_ID_UNUSED52 = 0xe7,
-} DebugBlockId_OLD;
-typedef enum DebugBlockId_BY2 {
- DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
- DBG_BLOCK_ID_VMC_BY2 = 0x1,
- DBG_BLOCK_ID_CG_BY2 = 0x2,
- DBG_BLOCK_ID_GRBM_BY2 = 0x3,
- DBG_BLOCK_ID_CSC_BY2 = 0x4,
- DBG_BLOCK_ID_IH_BY2 = 0x5,
- DBG_BLOCK_ID_SQ_BY2 = 0x6,
- DBG_BLOCK_ID_GMCON_BY2 = 0x7,
- DBG_BLOCK_ID_DMA0_BY2 = 0x8,
- DBG_BLOCK_ID_SPIM_BY2 = 0x9,
- DBG_BLOCK_ID_SPIS_BY2 = 0xa,
- DBG_BLOCK_ID_PA0_BY2 = 0xb,
- DBG_BLOCK_ID_CP0_BY2 = 0xc,
- DBG_BLOCK_ID_CP2_BY2 = 0xd,
- DBG_BLOCK_ID_UVDU_BY2 = 0xe,
- DBG_BLOCK_ID_VCE_BY2 = 0xf,
- DBG_BLOCK_ID_VGT0_BY2 = 0x10,
- DBG_BLOCK_ID_IA_BY2 = 0x11,
- DBG_BLOCK_ID_SCT0_BY2 = 0x12,
- DBG_BLOCK_ID_SPM0_BY2 = 0x13,
- DBG_BLOCK_ID_TCAA_BY2 = 0x14,
- DBG_BLOCK_ID_TCCA_BY2 = 0x15,
- DBG_BLOCK_ID_MCC0_BY2 = 0x16,
- DBG_BLOCK_ID_MCC2_BY2 = 0x17,
- DBG_BLOCK_ID_SX0_BY2 = 0x18,
- DBG_BLOCK_ID_SX2_BY2 = 0x19,
- DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a,
- DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b,
- DBG_BLOCK_ID_PC0_BY2 = 0x1c,
- DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d,
- DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e,
- DBG_BLOCK_ID_MCB_BY2 = 0x1f,
- DBG_BLOCK_ID_SCB0_BY2 = 0x20,
- DBG_BLOCK_ID_UNUSED13_BY2 = 0x21,
- DBG_BLOCK_ID_SCF0_BY2 = 0x22,
- DBG_BLOCK_ID_UNUSED15_BY2 = 0x23,
- DBG_BLOCK_ID_BCI0_BY2 = 0x24,
- DBG_BLOCK_ID_BCI2_BY2 = 0x25,
- DBG_BLOCK_ID_UNUSED17_BY2 = 0x26,
- DBG_BLOCK_ID_UNUSED19_BY2 = 0x27,
- DBG_BLOCK_ID_CB00_BY2 = 0x28,
- DBG_BLOCK_ID_CB02_BY2 = 0x29,
- DBG_BLOCK_ID_CB04_BY2 = 0x2a,
- DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b,
- DBG_BLOCK_ID_CB10_BY2 = 0x2c,
- DBG_BLOCK_ID_CB12_BY2 = 0x2d,
- DBG_BLOCK_ID_CB14_BY2 = 0x2e,
- DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f,
- DBG_BLOCK_ID_TCP0_BY2 = 0x30,
- DBG_BLOCK_ID_TCP2_BY2 = 0x31,
- DBG_BLOCK_ID_TCP4_BY2 = 0x32,
- DBG_BLOCK_ID_TCP6_BY2 = 0x33,
- DBG_BLOCK_ID_TCP8_BY2 = 0x34,
- DBG_BLOCK_ID_TCP10_BY2 = 0x35,
- DBG_BLOCK_ID_TCP12_BY2 = 0x36,
- DBG_BLOCK_ID_TCP14_BY2 = 0x37,
- DBG_BLOCK_ID_TCP16_BY2 = 0x38,
- DBG_BLOCK_ID_TCP18_BY2 = 0x39,
- DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
- DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
- DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
- DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
- DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
- DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
- DBG_BLOCK_ID_DB00_BY2 = 0x40,
- DBG_BLOCK_ID_DB02_BY2 = 0x41,
- DBG_BLOCK_ID_DB04_BY2 = 0x42,
- DBG_BLOCK_ID_UNUSED28_BY2 = 0x43,
- DBG_BLOCK_ID_DB10_BY2 = 0x44,
- DBG_BLOCK_ID_DB12_BY2 = 0x45,
- DBG_BLOCK_ID_DB14_BY2 = 0x46,
- DBG_BLOCK_ID_UNUSED31_BY2 = 0x47,
- DBG_BLOCK_ID_TCC0_BY2 = 0x48,
- DBG_BLOCK_ID_TCC2_BY2 = 0x49,
- DBG_BLOCK_ID_TCC4_BY2 = 0x4a,
- DBG_BLOCK_ID_TCC6_BY2 = 0x4b,
- DBG_BLOCK_ID_SPS00_BY2 = 0x4c,
- DBG_BLOCK_ID_SPS02_BY2 = 0x4d,
- DBG_BLOCK_ID_SPS11_BY2 = 0x4e,
- DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f,
- DBG_BLOCK_ID_TA00_BY2 = 0x50,
- DBG_BLOCK_ID_TA02_BY2 = 0x51,
- DBG_BLOCK_ID_TA04_BY2 = 0x52,
- DBG_BLOCK_ID_TA06_BY2 = 0x53,
- DBG_BLOCK_ID_TA08_BY2 = 0x54,
- DBG_BLOCK_ID_TA0A_BY2 = 0x55,
- DBG_BLOCK_ID_UNUSED35_BY2 = 0x56,
- DBG_BLOCK_ID_UNUSED37_BY2 = 0x57,
- DBG_BLOCK_ID_TA10_BY2 = 0x58,
- DBG_BLOCK_ID_TA12_BY2 = 0x59,
- DBG_BLOCK_ID_TA14_BY2 = 0x5a,
- DBG_BLOCK_ID_TA16_BY2 = 0x5b,
- DBG_BLOCK_ID_TA18_BY2 = 0x5c,
- DBG_BLOCK_ID_TA1A_BY2 = 0x5d,
- DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e,
- DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f,
- DBG_BLOCK_ID_TD00_BY2 = 0x60,
- DBG_BLOCK_ID_TD02_BY2 = 0x61,
- DBG_BLOCK_ID_TD04_BY2 = 0x62,
- DBG_BLOCK_ID_TD06_BY2 = 0x63,
- DBG_BLOCK_ID_TD08_BY2 = 0x64,
- DBG_BLOCK_ID_TD0A_BY2 = 0x65,
- DBG_BLOCK_ID_UNUSED43_BY2 = 0x66,
- DBG_BLOCK_ID_UNUSED45_BY2 = 0x67,
- DBG_BLOCK_ID_TD10_BY2 = 0x68,
- DBG_BLOCK_ID_TD12_BY2 = 0x69,
- DBG_BLOCK_ID_TD14_BY2 = 0x6a,
- DBG_BLOCK_ID_TD16_BY2 = 0x6b,
- DBG_BLOCK_ID_TD18_BY2 = 0x6c,
- DBG_BLOCK_ID_TD1A_BY2 = 0x6d,
- DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e,
- DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f,
- DBG_BLOCK_ID_MCD0_BY2 = 0x70,
- DBG_BLOCK_ID_MCD2_BY2 = 0x71,
- DBG_BLOCK_ID_MCD4_BY2 = 0x72,
- DBG_BLOCK_ID_UNUSED51_BY2 = 0x73,
-} DebugBlockId_BY2;
-typedef enum DebugBlockId_BY4 {
- DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
- DBG_BLOCK_ID_CG_BY4 = 0x1,
- DBG_BLOCK_ID_CSC_BY4 = 0x2,
- DBG_BLOCK_ID_SQ_BY4 = 0x3,
- DBG_BLOCK_ID_DMA0_BY4 = 0x4,
- DBG_BLOCK_ID_SPIS_BY4 = 0x5,
- DBG_BLOCK_ID_CP0_BY4 = 0x6,
- DBG_BLOCK_ID_UVDU_BY4 = 0x7,
- DBG_BLOCK_ID_VGT0_BY4 = 0x8,
- DBG_BLOCK_ID_SCT0_BY4 = 0x9,
- DBG_BLOCK_ID_TCAA_BY4 = 0xa,
- DBG_BLOCK_ID_MCC0_BY4 = 0xb,
- DBG_BLOCK_ID_SX0_BY4 = 0xc,
- DBG_BLOCK_ID_UNUSED4_BY4 = 0xd,
- DBG_BLOCK_ID_PC0_BY4 = 0xe,
- DBG_BLOCK_ID_UNUSED10_BY4 = 0xf,
- DBG_BLOCK_ID_SCB0_BY4 = 0x10,
- DBG_BLOCK_ID_SCF0_BY4 = 0x11,
- DBG_BLOCK_ID_BCI0_BY4 = 0x12,
- DBG_BLOCK_ID_UNUSED17_BY4 = 0x13,
- DBG_BLOCK_ID_CB00_BY4 = 0x14,
- DBG_BLOCK_ID_CB04_BY4 = 0x15,
- DBG_BLOCK_ID_CB10_BY4 = 0x16,
- DBG_BLOCK_ID_CB14_BY4 = 0x17,
- DBG_BLOCK_ID_TCP0_BY4 = 0x18,
- DBG_BLOCK_ID_TCP4_BY4 = 0x19,
- DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
- DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
- DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
- DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
- DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
- DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
- DBG_BLOCK_ID_DB_BY4 = 0x20,
- DBG_BLOCK_ID_DB04_BY4 = 0x21,
- DBG_BLOCK_ID_DB10_BY4 = 0x22,
- DBG_BLOCK_ID_DB14_BY4 = 0x23,
- DBG_BLOCK_ID_TCC0_BY4 = 0x24,
- DBG_BLOCK_ID_TCC4_BY4 = 0x25,
- DBG_BLOCK_ID_SPS00_BY4 = 0x26,
- DBG_BLOCK_ID_SPS11_BY4 = 0x27,
- DBG_BLOCK_ID_TA00_BY4 = 0x28,
- DBG_BLOCK_ID_TA04_BY4 = 0x29,
- DBG_BLOCK_ID_TA08_BY4 = 0x2a,
- DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b,
- DBG_BLOCK_ID_TA10_BY4 = 0x2c,
- DBG_BLOCK_ID_TA14_BY4 = 0x2d,
- DBG_BLOCK_ID_TA18_BY4 = 0x2e,
- DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f,
- DBG_BLOCK_ID_TD00_BY4 = 0x30,
- DBG_BLOCK_ID_TD04_BY4 = 0x31,
- DBG_BLOCK_ID_TD08_BY4 = 0x32,
- DBG_BLOCK_ID_UNUSED43_BY4 = 0x33,
- DBG_BLOCK_ID_TD10_BY4 = 0x34,
- DBG_BLOCK_ID_TD14_BY4 = 0x35,
- DBG_BLOCK_ID_TD18_BY4 = 0x36,
- DBG_BLOCK_ID_UNUSED47_BY4 = 0x37,
- DBG_BLOCK_ID_MCD0_BY4 = 0x38,
- DBG_BLOCK_ID_MCD4_BY4 = 0x39,
-} DebugBlockId_BY4;
-typedef enum DebugBlockId_BY8 {
- DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
- DBG_BLOCK_ID_CSC_BY8 = 0x1,
- DBG_BLOCK_ID_DMA0_BY8 = 0x2,
- DBG_BLOCK_ID_CP0_BY8 = 0x3,
- DBG_BLOCK_ID_VGT0_BY8 = 0x4,
- DBG_BLOCK_ID_TCAA_BY8 = 0x5,
- DBG_BLOCK_ID_SX0_BY8 = 0x6,
- DBG_BLOCK_ID_PC0_BY8 = 0x7,
- DBG_BLOCK_ID_SCB0_BY8 = 0x8,
- DBG_BLOCK_ID_BCI0_BY8 = 0x9,
- DBG_BLOCK_ID_CB00_BY8 = 0xa,
- DBG_BLOCK_ID_CB10_BY8 = 0xb,
- DBG_BLOCK_ID_TCP0_BY8 = 0xc,
- DBG_BLOCK_ID_TCP8_BY8 = 0xd,
- DBG_BLOCK_ID_TCP16_BY8 = 0xe,
- DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
- DBG_BLOCK_ID_DB00_BY8 = 0x10,
- DBG_BLOCK_ID_DB10_BY8 = 0x11,
- DBG_BLOCK_ID_TCC0_BY8 = 0x12,
- DBG_BLOCK_ID_SPS00_BY8 = 0x13,
- DBG_BLOCK_ID_TA00_BY8 = 0x14,
- DBG_BLOCK_ID_TA08_BY8 = 0x15,
- DBG_BLOCK_ID_TA10_BY8 = 0x16,
- DBG_BLOCK_ID_TA18_BY8 = 0x17,
- DBG_BLOCK_ID_TD00_BY8 = 0x18,
- DBG_BLOCK_ID_TD08_BY8 = 0x19,
- DBG_BLOCK_ID_TD10_BY8 = 0x1a,
- DBG_BLOCK_ID_TD18_BY8 = 0x1b,
- DBG_BLOCK_ID_MCD0_BY8 = 0x1c,
-} DebugBlockId_BY8;
-typedef enum DebugBlockId_BY16 {
- DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
- DBG_BLOCK_ID_DMA0_BY16 = 0x1,
- DBG_BLOCK_ID_VGT0_BY16 = 0x2,
- DBG_BLOCK_ID_SX0_BY16 = 0x3,
- DBG_BLOCK_ID_SCB0_BY16 = 0x4,
- DBG_BLOCK_ID_CB00_BY16 = 0x5,
- DBG_BLOCK_ID_TCP0_BY16 = 0x6,
- DBG_BLOCK_ID_TCP16_BY16 = 0x7,
- DBG_BLOCK_ID_DB00_BY16 = 0x8,
- DBG_BLOCK_ID_TCC0_BY16 = 0x9,
- DBG_BLOCK_ID_TA00_BY16 = 0xa,
- DBG_BLOCK_ID_TA10_BY16 = 0xb,
- DBG_BLOCK_ID_TD00_BY16 = 0xc,
- DBG_BLOCK_ID_TD10_BY16 = 0xd,
- DBG_BLOCK_ID_MCD0_BY16 = 0xe,
-} DebugBlockId_BY16;
-typedef enum ColorTransform {
- DCC_CT_AUTO = 0x0,
- DCC_CT_NONE = 0x1,
- ABGR_TO_A_BG_G_RB = 0x2,
- BGRA_TO_BG_G_RB_A = 0x3,
-} ColorTransform;
-typedef enum CompareRef {
- REF_NEVER = 0x0,
- REF_LESS = 0x1,
- REF_EQUAL = 0x2,
- REF_LEQUAL = 0x3,
- REF_GREATER = 0x4,
- REF_NOTEQUAL = 0x5,
- REF_GEQUAL = 0x6,
- REF_ALWAYS = 0x7,
-} CompareRef;
-typedef enum ReadSize {
- READ_256_BITS = 0x0,
- READ_512_BITS = 0x1,
-} ReadSize;
-typedef enum DepthFormat {
- DEPTH_INVALID = 0x0,
- DEPTH_16 = 0x1,
- DEPTH_X8_24 = 0x2,
- DEPTH_8_24 = 0x3,
- DEPTH_X8_24_FLOAT = 0x4,
- DEPTH_8_24_FLOAT = 0x5,
- DEPTH_32_FLOAT = 0x6,
- DEPTH_X24_8_32_FLOAT = 0x7,
-} DepthFormat;
-typedef enum ZFormat {
- Z_INVALID = 0x0,
- Z_16 = 0x1,
- Z_24 = 0x2,
- Z_32_FLOAT = 0x3,
-} ZFormat;
-typedef enum StencilFormat {
- STENCIL_INVALID = 0x0,
- STENCIL_8 = 0x1,
-} StencilFormat;
-typedef enum CmaskMode {
- CMASK_CLEAR_NONE = 0x0,
- CMASK_CLEAR_ONE = 0x1,
- CMASK_CLEAR_ALL = 0x2,
- CMASK_ANY_EXPANDED = 0x3,
- CMASK_ALPHA0_FRAG1 = 0x4,
- CMASK_ALPHA0_FRAG2 = 0x5,
- CMASK_ALPHA0_FRAG4 = 0x6,
- CMASK_ALPHA0_FRAGS = 0x7,
- CMASK_ALPHA1_FRAG1 = 0x8,
- CMASK_ALPHA1_FRAG2 = 0x9,
- CMASK_ALPHA1_FRAG4 = 0xa,
- CMASK_ALPHA1_FRAGS = 0xb,
- CMASK_ALPHAX_FRAG1 = 0xc,
- CMASK_ALPHAX_FRAG2 = 0xd,
- CMASK_ALPHAX_FRAG4 = 0xe,
- CMASK_ALPHAX_FRAGS = 0xf,
-} CmaskMode;
-typedef enum QuadExportFormat {
- EXPORT_UNUSED = 0x0,
- EXPORT_32_R = 0x1,
- EXPORT_32_GR = 0x2,
- EXPORT_32_AR = 0x3,
- EXPORT_FP16_ABGR = 0x4,
- EXPORT_UNSIGNED16_ABGR = 0x5,
- EXPORT_SIGNED16_ABGR = 0x6,
- EXPORT_32_ABGR = 0x7,
-} QuadExportFormat;
-typedef enum QuadExportFormatOld {
- EXPORT_4P_32BPC_ABGR = 0x0,
- EXPORT_4P_16BPC_ABGR = 0x1,
- EXPORT_4P_32BPC_GR = 0x2,
- EXPORT_4P_32BPC_AR = 0x3,
- EXPORT_2P_32BPC_ABGR = 0x4,
- EXPORT_8P_32BPC_R = 0x5,
-} QuadExportFormatOld;
-typedef enum ColorFormat {
- COLOR_INVALID = 0x0,
- COLOR_8 = 0x1,
- COLOR_16 = 0x2,
- COLOR_8_8 = 0x3,
- COLOR_32 = 0x4,
- COLOR_16_16 = 0x5,
- COLOR_10_11_11 = 0x6,
- COLOR_11_11_10 = 0x7,
- COLOR_10_10_10_2 = 0x8,
- COLOR_2_10_10_10 = 0x9,
- COLOR_8_8_8_8 = 0xa,
- COLOR_32_32 = 0xb,
- COLOR_16_16_16_16 = 0xc,
- COLOR_RESERVED_13 = 0xd,
- COLOR_32_32_32_32 = 0xe,
- COLOR_RESERVED_15 = 0xf,
- COLOR_5_6_5 = 0x10,
- COLOR_1_5_5_5 = 0x11,
- COLOR_5_5_5_1 = 0x12,
- COLOR_4_4_4_4 = 0x13,
- COLOR_8_24 = 0x14,
- COLOR_24_8 = 0x15,
- COLOR_X24_8_32_FLOAT = 0x16,
- COLOR_RESERVED_23 = 0x17,
-} ColorFormat;
-typedef enum SurfaceFormat {
- FMT_INVALID = 0x0,
- FMT_8 = 0x1,
- FMT_16 = 0x2,
- FMT_8_8 = 0x3,
- FMT_32 = 0x4,
- FMT_16_16 = 0x5,
- FMT_10_11_11 = 0x6,
- FMT_11_11_10 = 0x7,
- FMT_10_10_10_2 = 0x8,
- FMT_2_10_10_10 = 0x9,
- FMT_8_8_8_8 = 0xa,
- FMT_32_32 = 0xb,
- FMT_16_16_16_16 = 0xc,
- FMT_32_32_32 = 0xd,
- FMT_32_32_32_32 = 0xe,
- FMT_RESERVED_4 = 0xf,
- FMT_5_6_5 = 0x10,
- FMT_1_5_5_5 = 0x11,
- FMT_5_5_5_1 = 0x12,
- FMT_4_4_4_4 = 0x13,
- FMT_8_24 = 0x14,
- FMT_24_8 = 0x15,
- FMT_X24_8_32_FLOAT = 0x16,
- FMT_RESERVED_33 = 0x17,
- FMT_11_11_10_FLOAT = 0x18,
- FMT_16_FLOAT = 0x19,
- FMT_32_FLOAT = 0x1a,
- FMT_16_16_FLOAT = 0x1b,
- FMT_8_24_FLOAT = 0x1c,
- FMT_24_8_FLOAT = 0x1d,
- FMT_32_32_FLOAT = 0x1e,
- FMT_10_11_11_FLOAT = 0x1f,
- FMT_16_16_16_16_FLOAT = 0x20,
- FMT_3_3_2 = 0x21,
- FMT_6_5_5 = 0x22,
- FMT_32_32_32_32_FLOAT = 0x23,
- FMT_RESERVED_36 = 0x24,
- FMT_1 = 0x25,
- FMT_1_REVERSED = 0x26,
- FMT_GB_GR = 0x27,
- FMT_BG_RG = 0x28,
- FMT_32_AS_8 = 0x29,
- FMT_32_AS_8_8 = 0x2a,
- FMT_5_9_9_9_SHAREDEXP = 0x2b,
- FMT_8_8_8 = 0x2c,
- FMT_16_16_16 = 0x2d,
- FMT_16_16_16_FLOAT = 0x2e,
- FMT_4_4 = 0x2f,
- FMT_32_32_32_FLOAT = 0x30,
- FMT_BC1 = 0x31,
- FMT_BC2 = 0x32,
- FMT_BC3 = 0x33,
- FMT_BC4 = 0x34,
- FMT_BC5 = 0x35,
- FMT_BC6 = 0x36,
- FMT_BC7 = 0x37,
- FMT_32_AS_32_32_32_32 = 0x38,
- FMT_APC3 = 0x39,
- FMT_APC4 = 0x3a,
- FMT_APC5 = 0x3b,
- FMT_APC6 = 0x3c,
- FMT_APC7 = 0x3d,
- FMT_CTX1 = 0x3e,
- FMT_RESERVED_63 = 0x3f,
-} SurfaceFormat;
-typedef enum BUF_DATA_FORMAT {
- BUF_DATA_FORMAT_INVALID = 0x0,
- BUF_DATA_FORMAT_8 = 0x1,
- BUF_DATA_FORMAT_16 = 0x2,
- BUF_DATA_FORMAT_8_8 = 0x3,
- BUF_DATA_FORMAT_32 = 0x4,
- BUF_DATA_FORMAT_16_16 = 0x5,
- BUF_DATA_FORMAT_10_11_11 = 0x6,
- BUF_DATA_FORMAT_11_11_10 = 0x7,
- BUF_DATA_FORMAT_10_10_10_2 = 0x8,
- BUF_DATA_FORMAT_2_10_10_10 = 0x9,
- BUF_DATA_FORMAT_8_8_8_8 = 0xa,
- BUF_DATA_FORMAT_32_32 = 0xb,
- BUF_DATA_FORMAT_16_16_16_16 = 0xc,
- BUF_DATA_FORMAT_32_32_32 = 0xd,
- BUF_DATA_FORMAT_32_32_32_32 = 0xe,
- BUF_DATA_FORMAT_RESERVED_15 = 0xf,
-} BUF_DATA_FORMAT;
-typedef enum IMG_DATA_FORMAT {
- IMG_DATA_FORMAT_INVALID = 0x0,
- IMG_DATA_FORMAT_8 = 0x1,
- IMG_DATA_FORMAT_16 = 0x2,
- IMG_DATA_FORMAT_8_8 = 0x3,
- IMG_DATA_FORMAT_32 = 0x4,
- IMG_DATA_FORMAT_16_16 = 0x5,
- IMG_DATA_FORMAT_10_11_11 = 0x6,
- IMG_DATA_FORMAT_11_11_10 = 0x7,
- IMG_DATA_FORMAT_10_10_10_2 = 0x8,
- IMG_DATA_FORMAT_2_10_10_10 = 0x9,
- IMG_DATA_FORMAT_8_8_8_8 = 0xa,
- IMG_DATA_FORMAT_32_32 = 0xb,
- IMG_DATA_FORMAT_16_16_16_16 = 0xc,
- IMG_DATA_FORMAT_32_32_32 = 0xd,
- IMG_DATA_FORMAT_32_32_32_32 = 0xe,
- IMG_DATA_FORMAT_RESERVED_15 = 0xf,
- IMG_DATA_FORMAT_5_6_5 = 0x10,
- IMG_DATA_FORMAT_1_5_5_5 = 0x11,
- IMG_DATA_FORMAT_5_5_5_1 = 0x12,
- IMG_DATA_FORMAT_4_4_4_4 = 0x13,
- IMG_DATA_FORMAT_8_24 = 0x14,
- IMG_DATA_FORMAT_24_8 = 0x15,
- IMG_DATA_FORMAT_X24_8_32 = 0x16,
- IMG_DATA_FORMAT_RESERVED_23 = 0x17,
- IMG_DATA_FORMAT_RESERVED_24 = 0x18,
- IMG_DATA_FORMAT_RESERVED_25 = 0x19,
- IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
- IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
- IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
- IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
- IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
- IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
- IMG_DATA_FORMAT_GB_GR = 0x20,
- IMG_DATA_FORMAT_BG_RG = 0x21,
- IMG_DATA_FORMAT_5_9_9_9 = 0x22,
- IMG_DATA_FORMAT_BC1 = 0x23,
- IMG_DATA_FORMAT_BC2 = 0x24,
- IMG_DATA_FORMAT_BC3 = 0x25,
- IMG_DATA_FORMAT_BC4 = 0x26,
- IMG_DATA_FORMAT_BC5 = 0x27,
- IMG_DATA_FORMAT_BC6 = 0x28,
- IMG_DATA_FORMAT_BC7 = 0x29,
- IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
- IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
- IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
- IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
- IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
- IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
- IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
- IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
- IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
- IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
- IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
- IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
- IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
- IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
- IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
- IMG_DATA_FORMAT_4_4 = 0x39,
- IMG_DATA_FORMAT_6_5_5 = 0x3a,
- IMG_DATA_FORMAT_1 = 0x3b,
- IMG_DATA_FORMAT_1_REVERSED = 0x3c,
- IMG_DATA_FORMAT_32_AS_8 = 0x3d,
- IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
- IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
-} IMG_DATA_FORMAT;
-typedef enum BUF_NUM_FORMAT {
- BUF_NUM_FORMAT_UNORM = 0x0,
- BUF_NUM_FORMAT_SNORM = 0x1,
- BUF_NUM_FORMAT_USCALED = 0x2,
- BUF_NUM_FORMAT_SSCALED = 0x3,
- BUF_NUM_FORMAT_UINT = 0x4,
- BUF_NUM_FORMAT_SINT = 0x5,
- BUF_NUM_FORMAT_RESERVED_6 = 0x6,
- BUF_NUM_FORMAT_FLOAT = 0x7,
-} BUF_NUM_FORMAT;
-typedef enum IMG_NUM_FORMAT {
- IMG_NUM_FORMAT_UNORM = 0x0,
- IMG_NUM_FORMAT_SNORM = 0x1,
- IMG_NUM_FORMAT_USCALED = 0x2,
- IMG_NUM_FORMAT_SSCALED = 0x3,
- IMG_NUM_FORMAT_UINT = 0x4,
- IMG_NUM_FORMAT_SINT = 0x5,
- IMG_NUM_FORMAT_RESERVED_6 = 0x6,
- IMG_NUM_FORMAT_FLOAT = 0x7,
- IMG_NUM_FORMAT_RESERVED_8 = 0x8,
- IMG_NUM_FORMAT_SRGB = 0x9,
- IMG_NUM_FORMAT_RESERVED_10 = 0xa,
- IMG_NUM_FORMAT_RESERVED_11 = 0xb,
- IMG_NUM_FORMAT_RESERVED_12 = 0xc,
- IMG_NUM_FORMAT_RESERVED_13 = 0xd,
- IMG_NUM_FORMAT_RESERVED_14 = 0xe,
- IMG_NUM_FORMAT_RESERVED_15 = 0xf,
-} IMG_NUM_FORMAT;
-typedef enum TileType {
- ARRAY_COLOR_TILE = 0x0,
- ARRAY_DEPTH_TILE = 0x1,
-} TileType;
-typedef enum NonDispTilingOrder {
- ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
- ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
-} NonDispTilingOrder;
-typedef enum MicroTileMode {
- ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
- ADDR_SURF_THIN_MICRO_TILING = 0x1,
- ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
- ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
- ADDR_SURF_THICK_MICRO_TILING = 0x4,
-} MicroTileMode;
-typedef enum TileSplit {
- ADDR_SURF_TILE_SPLIT_64B = 0x0,
- ADDR_SURF_TILE_SPLIT_128B = 0x1,
- ADDR_SURF_TILE_SPLIT_256B = 0x2,
- ADDR_SURF_TILE_SPLIT_512B = 0x3,
- ADDR_SURF_TILE_SPLIT_1KB = 0x4,
- ADDR_SURF_TILE_SPLIT_2KB = 0x5,
- ADDR_SURF_TILE_SPLIT_4KB = 0x6,
-} TileSplit;
-typedef enum SampleSplit {
- ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
- ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
- ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
- ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
-} SampleSplit;
-typedef enum PipeConfig {
- ADDR_SURF_P2 = 0x0,
- ADDR_SURF_P2_RESERVED0 = 0x1,
- ADDR_SURF_P2_RESERVED1 = 0x2,
- ADDR_SURF_P2_RESERVED2 = 0x3,
- ADDR_SURF_P4_8x16 = 0x4,
- ADDR_SURF_P4_16x16 = 0x5,
- ADDR_SURF_P4_16x32 = 0x6,
- ADDR_SURF_P4_32x32 = 0x7,
- ADDR_SURF_P8_16x16_8x16 = 0x8,
- ADDR_SURF_P8_16x32_8x16 = 0x9,
- ADDR_SURF_P8_32x32_8x16 = 0xa,
- ADDR_SURF_P8_16x32_16x16 = 0xb,
- ADDR_SURF_P8_32x32_16x16 = 0xc,
- ADDR_SURF_P8_32x32_16x32 = 0xd,
- ADDR_SURF_P8_32x64_32x32 = 0xe,
- ADDR_SURF_P8_RESERVED0 = 0xf,
- ADDR_SURF_P16_32x32_8x16 = 0x10,
- ADDR_SURF_P16_32x32_16x16 = 0x11,
-} PipeConfig;
-typedef enum NumBanks {
- ADDR_SURF_2_BANK = 0x0,
- ADDR_SURF_4_BANK = 0x1,
- ADDR_SURF_8_BANK = 0x2,
- ADDR_SURF_16_BANK = 0x3,
-} NumBanks;
-typedef enum BankWidth {
- ADDR_SURF_BANK_WIDTH_1 = 0x0,
- ADDR_SURF_BANK_WIDTH_2 = 0x1,
- ADDR_SURF_BANK_WIDTH_4 = 0x2,
- ADDR_SURF_BANK_WIDTH_8 = 0x3,
-} BankWidth;
-typedef enum BankHeight {
- ADDR_SURF_BANK_HEIGHT_1 = 0x0,
- ADDR_SURF_BANK_HEIGHT_2 = 0x1,
- ADDR_SURF_BANK_HEIGHT_4 = 0x2,
- ADDR_SURF_BANK_HEIGHT_8 = 0x3,
-} BankHeight;
-typedef enum BankWidthHeight {
- ADDR_SURF_BANK_WH_1 = 0x0,
- ADDR_SURF_BANK_WH_2 = 0x1,
- ADDR_SURF_BANK_WH_4 = 0x2,
- ADDR_SURF_BANK_WH_8 = 0x3,
-} BankWidthHeight;
-typedef enum MacroTileAspect {
- ADDR_SURF_MACRO_ASPECT_1 = 0x0,
- ADDR_SURF_MACRO_ASPECT_2 = 0x1,
- ADDR_SURF_MACRO_ASPECT_4 = 0x2,
- ADDR_SURF_MACRO_ASPECT_8 = 0x3,
-} MacroTileAspect;
-typedef enum GATCL1RequestType {
- GATCL1_TYPE_NORMAL = 0x0,
- GATCL1_TYPE_SHOOTDOWN = 0x1,
- GATCL1_TYPE_BYPASS = 0x2,
-} GATCL1RequestType;
-typedef enum TCC_CACHE_POLICIES {
- TCC_CACHE_POLICY_LRU = 0x0,
- TCC_CACHE_POLICY_STREAM = 0x1,
-} TCC_CACHE_POLICIES;
-typedef enum MTYPE {
- MTYPE_NC_NV = 0x0,
- MTYPE_NC = 0x1,
- MTYPE_CC = 0x2,
- MTYPE_UC = 0x3,
-} MTYPE;
-typedef enum PERFMON_COUNTER_MODE {
- PERFMON_COUNTER_MODE_ACCUM = 0x0,
- PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
- PERFMON_COUNTER_MODE_MAX = 0x2,
- PERFMON_COUNTER_MODE_DIRTY = 0x3,
- PERFMON_COUNTER_MODE_SAMPLE = 0x4,
- PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
- PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
- PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
- PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
- PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
- PERFMON_COUNTER_MODE_RESERVED = 0xf,
-} PERFMON_COUNTER_MODE;
-typedef enum PERFMON_SPM_MODE {
- PERFMON_SPM_MODE_OFF = 0x0,
- PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
- PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
- PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
- PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
- PERFMON_SPM_MODE_RESERVED_5 = 0x5,
- PERFMON_SPM_MODE_RESERVED_6 = 0x6,
- PERFMON_SPM_MODE_RESERVED_7 = 0x7,
- PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
- PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
- PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
-} PERFMON_SPM_MODE;
-typedef enum SurfaceTiling {
- ARRAY_LINEAR = 0x0,
- ARRAY_TILED = 0x1,
-} SurfaceTiling;
-typedef enum SurfaceArray {
- ARRAY_1D = 0x0,
- ARRAY_2D = 0x1,
- ARRAY_3D = 0x2,
- ARRAY_3D_SLICE = 0x3,
-} SurfaceArray;
-typedef enum ColorArray {
- ARRAY_2D_ALT_COLOR = 0x0,
- ARRAY_2D_COLOR = 0x1,
- ARRAY_3D_SLICE_COLOR = 0x3,
-} ColorArray;
-typedef enum DepthArray {
- ARRAY_2D_ALT_DEPTH = 0x0,
- ARRAY_2D_DEPTH = 0x1,
-} DepthArray;
-typedef enum ENUM_NUM_SIMD_PER_CU {
- NUM_SIMD_PER_CU = 0x4,
-} ENUM_NUM_SIMD_PER_CU;
-typedef enum MEM_PWR_FORCE_CTRL {
- NO_FORCE_REQUEST = 0x0,
- FORCE_LIGHT_SLEEP_REQUEST = 0x1,
- FORCE_DEEP_SLEEP_REQUEST = 0x2,
- FORCE_SHUT_DOWN_REQUEST = 0x3,
-} MEM_PWR_FORCE_CTRL;
-typedef enum MEM_PWR_FORCE_CTRL2 {
- NO_FORCE_REQ = 0x0,
- FORCE_LIGHT_SLEEP_REQ = 0x1,
-} MEM_PWR_FORCE_CTRL2;
-typedef enum MEM_PWR_DIS_CTRL {
- ENABLE_MEM_PWR_CTRL = 0x0,
- DISABLE_MEM_PWR_CTRL = 0x1,
-} MEM_PWR_DIS_CTRL;
-typedef enum MEM_PWR_SEL_CTRL {
- DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
- DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
- DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
-} MEM_PWR_SEL_CTRL;
-typedef enum MEM_PWR_SEL_CTRL2 {
- DYNAMIC_DEEP_SLEEP_EN = 0x0,
- DYNAMIC_LIGHT_SLEEP_EN = 0x1,
-} MEM_PWR_SEL_CTRL2;
-
-#endif /* SMU_7_1_3_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_enum.h
deleted file mode 100644
index e1540c181..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_enum.h
+++ /dev/null
@@ -1,1072 +0,0 @@
-/*
- * SMU_8_0 Register documentation
- *
- * Copyright (C) 2014 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef SMU_8_0_ENUM_H
-#define SMU_8_0_ENUM_H
-
-typedef enum DebugBlockId {
- DBG_BLOCK_ID_RESERVED = 0x0,
- DBG_BLOCK_ID_DBG = 0x1,
- DBG_BLOCK_ID_VMC = 0x2,
- DBG_BLOCK_ID_PDMA = 0x3,
- DBG_BLOCK_ID_CG = 0x4,
- DBG_BLOCK_ID_SRBM = 0x5,
- DBG_BLOCK_ID_GRBM = 0x6,
- DBG_BLOCK_ID_RLC = 0x7,
- DBG_BLOCK_ID_CSC = 0x8,
- DBG_BLOCK_ID_SEM = 0x9,
- DBG_BLOCK_ID_IH = 0xa,
- DBG_BLOCK_ID_SC = 0xb,
- DBG_BLOCK_ID_SQ = 0xc,
- DBG_BLOCK_ID_UVDU = 0xd,
- DBG_BLOCK_ID_SQA = 0xe,
- DBG_BLOCK_ID_SDMA0 = 0xf,
- DBG_BLOCK_ID_SDMA1 = 0x10,
- DBG_BLOCK_ID_SPIM = 0x11,
- DBG_BLOCK_ID_GDS = 0x12,
- DBG_BLOCK_ID_VC0 = 0x13,
- DBG_BLOCK_ID_VC1 = 0x14,
- DBG_BLOCK_ID_PA0 = 0x15,
- DBG_BLOCK_ID_PA1 = 0x16,
- DBG_BLOCK_ID_CP0 = 0x17,
- DBG_BLOCK_ID_CP1 = 0x18,
- DBG_BLOCK_ID_CP2 = 0x19,
- DBG_BLOCK_ID_XBR = 0x1a,
- DBG_BLOCK_ID_UVDM = 0x1b,
- DBG_BLOCK_ID_VGT0 = 0x1c,
- DBG_BLOCK_ID_VGT1 = 0x1d,
- DBG_BLOCK_ID_IA = 0x1e,
- DBG_BLOCK_ID_SXM0 = 0x1f,
- DBG_BLOCK_ID_SXM1 = 0x20,
- DBG_BLOCK_ID_SCT0 = 0x21,
- DBG_BLOCK_ID_SCT1 = 0x22,
- DBG_BLOCK_ID_SPM0 = 0x23,
- DBG_BLOCK_ID_SPM1 = 0x24,
- DBG_BLOCK_ID_UNUSED0 = 0x25,
- DBG_BLOCK_ID_UNUSED1 = 0x26,
- DBG_BLOCK_ID_TCAA = 0x27,
- DBG_BLOCK_ID_TCAB = 0x28,
- DBG_BLOCK_ID_TCCA = 0x29,
- DBG_BLOCK_ID_TCCB = 0x2a,
- DBG_BLOCK_ID_MCC0 = 0x2b,
- DBG_BLOCK_ID_MCC1 = 0x2c,
- DBG_BLOCK_ID_MCC2 = 0x2d,
- DBG_BLOCK_ID_MCC3 = 0x2e,
- DBG_BLOCK_ID_SXS0 = 0x2f,
- DBG_BLOCK_ID_SXS1 = 0x30,
- DBG_BLOCK_ID_SXS2 = 0x31,
- DBG_BLOCK_ID_SXS3 = 0x32,
- DBG_BLOCK_ID_SXS4 = 0x33,
- DBG_BLOCK_ID_SXS5 = 0x34,
- DBG_BLOCK_ID_SXS6 = 0x35,
- DBG_BLOCK_ID_SXS7 = 0x36,
- DBG_BLOCK_ID_SXS8 = 0x37,
- DBG_BLOCK_ID_SXS9 = 0x38,
- DBG_BLOCK_ID_BCI0 = 0x39,
- DBG_BLOCK_ID_BCI1 = 0x3a,
- DBG_BLOCK_ID_BCI2 = 0x3b,
- DBG_BLOCK_ID_BCI3 = 0x3c,
- DBG_BLOCK_ID_MCB = 0x3d,
- DBG_BLOCK_ID_UNUSED6 = 0x3e,
- DBG_BLOCK_ID_SQA00 = 0x3f,
- DBG_BLOCK_ID_SQA01 = 0x40,
- DBG_BLOCK_ID_SQA02 = 0x41,
- DBG_BLOCK_ID_SQA10 = 0x42,
- DBG_BLOCK_ID_SQA11 = 0x43,
- DBG_BLOCK_ID_SQA12 = 0x44,
- DBG_BLOCK_ID_UNUSED7 = 0x45,
- DBG_BLOCK_ID_UNUSED8 = 0x46,
- DBG_BLOCK_ID_SQB00 = 0x47,
- DBG_BLOCK_ID_SQB01 = 0x48,
- DBG_BLOCK_ID_SQB10 = 0x49,
- DBG_BLOCK_ID_SQB11 = 0x4a,
- DBG_BLOCK_ID_SQ00 = 0x4b,
- DBG_BLOCK_ID_SQ01 = 0x4c,
- DBG_BLOCK_ID_SQ10 = 0x4d,
- DBG_BLOCK_ID_SQ11 = 0x4e,
- DBG_BLOCK_ID_CB00 = 0x4f,
- DBG_BLOCK_ID_CB01 = 0x50,
- DBG_BLOCK_ID_CB02 = 0x51,
- DBG_BLOCK_ID_CB03 = 0x52,
- DBG_BLOCK_ID_CB04 = 0x53,
- DBG_BLOCK_ID_UNUSED9 = 0x54,
- DBG_BLOCK_ID_UNUSED10 = 0x55,
- DBG_BLOCK_ID_UNUSED11 = 0x56,
- DBG_BLOCK_ID_CB10 = 0x57,
- DBG_BLOCK_ID_CB11 = 0x58,
- DBG_BLOCK_ID_CB12 = 0x59,
- DBG_BLOCK_ID_CB13 = 0x5a,
- DBG_BLOCK_ID_CB14 = 0x5b,
- DBG_BLOCK_ID_UNUSED12 = 0x5c,
- DBG_BLOCK_ID_UNUSED13 = 0x5d,
- DBG_BLOCK_ID_UNUSED14 = 0x5e,
- DBG_BLOCK_ID_TCP0 = 0x5f,
- DBG_BLOCK_ID_TCP1 = 0x60,
- DBG_BLOCK_ID_TCP2 = 0x61,
- DBG_BLOCK_ID_TCP3 = 0x62,
- DBG_BLOCK_ID_TCP4 = 0x63,
- DBG_BLOCK_ID_TCP5 = 0x64,
- DBG_BLOCK_ID_TCP6 = 0x65,
- DBG_BLOCK_ID_TCP7 = 0x66,
- DBG_BLOCK_ID_TCP8 = 0x67,
- DBG_BLOCK_ID_TCP9 = 0x68,
- DBG_BLOCK_ID_TCP10 = 0x69,
- DBG_BLOCK_ID_TCP11 = 0x6a,
- DBG_BLOCK_ID_TCP12 = 0x6b,
- DBG_BLOCK_ID_TCP13 = 0x6c,
- DBG_BLOCK_ID_TCP14 = 0x6d,
- DBG_BLOCK_ID_TCP15 = 0x6e,
- DBG_BLOCK_ID_TCP16 = 0x6f,
- DBG_BLOCK_ID_TCP17 = 0x70,
- DBG_BLOCK_ID_TCP18 = 0x71,
- DBG_BLOCK_ID_TCP19 = 0x72,
- DBG_BLOCK_ID_TCP20 = 0x73,
- DBG_BLOCK_ID_TCP21 = 0x74,
- DBG_BLOCK_ID_TCP22 = 0x75,
- DBG_BLOCK_ID_TCP23 = 0x76,
- DBG_BLOCK_ID_TCP_RESERVED0 = 0x77,
- DBG_BLOCK_ID_TCP_RESERVED1 = 0x78,
- DBG_BLOCK_ID_TCP_RESERVED2 = 0x79,
- DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a,
- DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b,
- DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c,
- DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d,
- DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e,
- DBG_BLOCK_ID_DB00 = 0x7f,
- DBG_BLOCK_ID_DB01 = 0x80,
- DBG_BLOCK_ID_DB02 = 0x81,
- DBG_BLOCK_ID_DB03 = 0x82,
- DBG_BLOCK_ID_DB04 = 0x83,
- DBG_BLOCK_ID_UNUSED15 = 0x84,
- DBG_BLOCK_ID_UNUSED16 = 0x85,
- DBG_BLOCK_ID_UNUSED17 = 0x86,
- DBG_BLOCK_ID_DB10 = 0x87,
- DBG_BLOCK_ID_DB11 = 0x88,
- DBG_BLOCK_ID_DB12 = 0x89,
- DBG_BLOCK_ID_DB13 = 0x8a,
- DBG_BLOCK_ID_DB14 = 0x8b,
- DBG_BLOCK_ID_UNUSED18 = 0x8c,
- DBG_BLOCK_ID_UNUSED19 = 0x8d,
- DBG_BLOCK_ID_UNUSED20 = 0x8e,
- DBG_BLOCK_ID_TCC0 = 0x8f,
- DBG_BLOCK_ID_TCC1 = 0x90,
- DBG_BLOCK_ID_TCC2 = 0x91,
- DBG_BLOCK_ID_TCC3 = 0x92,
- DBG_BLOCK_ID_TCC4 = 0x93,
- DBG_BLOCK_ID_TCC5 = 0x94,
- DBG_BLOCK_ID_TCC6 = 0x95,
- DBG_BLOCK_ID_TCC7 = 0x96,
- DBG_BLOCK_ID_SPS00 = 0x97,
- DBG_BLOCK_ID_SPS01 = 0x98,
- DBG_BLOCK_ID_SPS02 = 0x99,
- DBG_BLOCK_ID_SPS10 = 0x9a,
- DBG_BLOCK_ID_SPS11 = 0x9b,
- DBG_BLOCK_ID_SPS12 = 0x9c,
- DBG_BLOCK_ID_UNUSED21 = 0x9d,
- DBG_BLOCK_ID_UNUSED22 = 0x9e,
- DBG_BLOCK_ID_TA00 = 0x9f,
- DBG_BLOCK_ID_TA01 = 0xa0,
- DBG_BLOCK_ID_TA02 = 0xa1,
- DBG_BLOCK_ID_TA03 = 0xa2,
- DBG_BLOCK_ID_TA04 = 0xa3,
- DBG_BLOCK_ID_TA05 = 0xa4,
- DBG_BLOCK_ID_TA06 = 0xa5,
- DBG_BLOCK_ID_TA07 = 0xa6,
- DBG_BLOCK_ID_TA08 = 0xa7,
- DBG_BLOCK_ID_TA09 = 0xa8,
- DBG_BLOCK_ID_TA0A = 0xa9,
- DBG_BLOCK_ID_TA0B = 0xaa,
- DBG_BLOCK_ID_UNUSED23 = 0xab,
- DBG_BLOCK_ID_UNUSED24 = 0xac,
- DBG_BLOCK_ID_UNUSED25 = 0xad,
- DBG_BLOCK_ID_UNUSED26 = 0xae,
- DBG_BLOCK_ID_TA10 = 0xaf,
- DBG_BLOCK_ID_TA11 = 0xb0,
- DBG_BLOCK_ID_TA12 = 0xb1,
- DBG_BLOCK_ID_TA13 = 0xb2,
- DBG_BLOCK_ID_TA14 = 0xb3,
- DBG_BLOCK_ID_TA15 = 0xb4,
- DBG_BLOCK_ID_TA16 = 0xb5,
- DBG_BLOCK_ID_TA17 = 0xb6,
- DBG_BLOCK_ID_TA18 = 0xb7,
- DBG_BLOCK_ID_TA19 = 0xb8,
- DBG_BLOCK_ID_TA1A = 0xb9,
- DBG_BLOCK_ID_TA1B = 0xba,
- DBG_BLOCK_ID_UNUSED27 = 0xbb,
- DBG_BLOCK_ID_UNUSED28 = 0xbc,
- DBG_BLOCK_ID_UNUSED29 = 0xbd,
- DBG_BLOCK_ID_UNUSED30 = 0xbe,
- DBG_BLOCK_ID_TD00 = 0xbf,
- DBG_BLOCK_ID_TD01 = 0xc0,
- DBG_BLOCK_ID_TD02 = 0xc1,
- DBG_BLOCK_ID_TD03 = 0xc2,
- DBG_BLOCK_ID_TD04 = 0xc3,
- DBG_BLOCK_ID_TD05 = 0xc4,
- DBG_BLOCK_ID_TD06 = 0xc5,
- DBG_BLOCK_ID_TD07 = 0xc6,
- DBG_BLOCK_ID_TD08 = 0xc7,
- DBG_BLOCK_ID_TD09 = 0xc8,
- DBG_BLOCK_ID_TD0A = 0xc9,
- DBG_BLOCK_ID_TD0B = 0xca,
- DBG_BLOCK_ID_UNUSED31 = 0xcb,
- DBG_BLOCK_ID_UNUSED32 = 0xcc,
- DBG_BLOCK_ID_UNUSED33 = 0xcd,
- DBG_BLOCK_ID_UNUSED34 = 0xce,
- DBG_BLOCK_ID_TD10 = 0xcf,
- DBG_BLOCK_ID_TD11 = 0xd0,
- DBG_BLOCK_ID_TD12 = 0xd1,
- DBG_BLOCK_ID_TD13 = 0xd2,
- DBG_BLOCK_ID_TD14 = 0xd3,
- DBG_BLOCK_ID_TD15 = 0xd4,
- DBG_BLOCK_ID_TD16 = 0xd5,
- DBG_BLOCK_ID_TD17 = 0xd6,
- DBG_BLOCK_ID_TD18 = 0xd7,
- DBG_BLOCK_ID_TD19 = 0xd8,
- DBG_BLOCK_ID_TD1A = 0xd9,
- DBG_BLOCK_ID_TD1B = 0xda,
- DBG_BLOCK_ID_UNUSED35 = 0xdb,
- DBG_BLOCK_ID_UNUSED36 = 0xdc,
- DBG_BLOCK_ID_UNUSED37 = 0xdd,
- DBG_BLOCK_ID_UNUSED38 = 0xde,
- DBG_BLOCK_ID_LDS00 = 0xdf,
- DBG_BLOCK_ID_LDS01 = 0xe0,
- DBG_BLOCK_ID_LDS02 = 0xe1,
- DBG_BLOCK_ID_LDS03 = 0xe2,
- DBG_BLOCK_ID_LDS04 = 0xe3,
- DBG_BLOCK_ID_LDS05 = 0xe4,
- DBG_BLOCK_ID_LDS06 = 0xe5,
- DBG_BLOCK_ID_LDS07 = 0xe6,
- DBG_BLOCK_ID_LDS08 = 0xe7,
- DBG_BLOCK_ID_LDS09 = 0xe8,
- DBG_BLOCK_ID_LDS0A = 0xe9,
- DBG_BLOCK_ID_LDS0B = 0xea,
- DBG_BLOCK_ID_UNUSED39 = 0xeb,
- DBG_BLOCK_ID_UNUSED40 = 0xec,
- DBG_BLOCK_ID_UNUSED41 = 0xed,
- DBG_BLOCK_ID_UNUSED42 = 0xee,
- DBG_BLOCK_ID_LDS10 = 0xef,
- DBG_BLOCK_ID_LDS11 = 0xf0,
- DBG_BLOCK_ID_LDS12 = 0xf1,
- DBG_BLOCK_ID_LDS13 = 0xf2,
- DBG_BLOCK_ID_LDS14 = 0xf3,
- DBG_BLOCK_ID_LDS15 = 0xf4,
- DBG_BLOCK_ID_LDS16 = 0xf5,
- DBG_BLOCK_ID_LDS17 = 0xf6,
- DBG_BLOCK_ID_LDS18 = 0xf7,
- DBG_BLOCK_ID_LDS19 = 0xf8,
- DBG_BLOCK_ID_LDS1A = 0xf9,
- DBG_BLOCK_ID_LDS1B = 0xfa,
- DBG_BLOCK_ID_UNUSED43 = 0xfb,
- DBG_BLOCK_ID_UNUSED44 = 0xfc,
- DBG_BLOCK_ID_UNUSED45 = 0xfd,
- DBG_BLOCK_ID_UNUSED46 = 0xfe,
-} DebugBlockId;
-typedef enum DebugBlockId_BY2 {
- DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
- DBG_BLOCK_ID_VMC_BY2 = 0x1,
- DBG_BLOCK_ID_UNUSED0_BY2 = 0x2,
- DBG_BLOCK_ID_GRBM_BY2 = 0x3,
- DBG_BLOCK_ID_CSC_BY2 = 0x4,
- DBG_BLOCK_ID_IH_BY2 = 0x5,
- DBG_BLOCK_ID_SQ_BY2 = 0x6,
- DBG_BLOCK_ID_UVD_BY2 = 0x7,
- DBG_BLOCK_ID_SDMA0_BY2 = 0x8,
- DBG_BLOCK_ID_SPIM_BY2 = 0x9,
- DBG_BLOCK_ID_VC0_BY2 = 0xa,
- DBG_BLOCK_ID_PA_BY2 = 0xb,
- DBG_BLOCK_ID_CP0_BY2 = 0xc,
- DBG_BLOCK_ID_CP2_BY2 = 0xd,
- DBG_BLOCK_ID_PC0_BY2 = 0xe,
- DBG_BLOCK_ID_BCI0_BY2 = 0xf,
- DBG_BLOCK_ID_SXM0_BY2 = 0x10,
- DBG_BLOCK_ID_SCT0_BY2 = 0x11,
- DBG_BLOCK_ID_SPM0_BY2 = 0x12,
- DBG_BLOCK_ID_BCI2_BY2 = 0x13,
- DBG_BLOCK_ID_TCA_BY2 = 0x14,
- DBG_BLOCK_ID_TCCA_BY2 = 0x15,
- DBG_BLOCK_ID_MCC_BY2 = 0x16,
- DBG_BLOCK_ID_MCC2_BY2 = 0x17,
- DBG_BLOCK_ID_MCD_BY2 = 0x18,
- DBG_BLOCK_ID_MCD2_BY2 = 0x19,
- DBG_BLOCK_ID_MCD4_BY2 = 0x1a,
- DBG_BLOCK_ID_MCB_BY2 = 0x1b,
- DBG_BLOCK_ID_SQA_BY2 = 0x1c,
- DBG_BLOCK_ID_SQA02_BY2 = 0x1d,
- DBG_BLOCK_ID_SQA11_BY2 = 0x1e,
- DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f,
- DBG_BLOCK_ID_SQB_BY2 = 0x20,
- DBG_BLOCK_ID_SQB10_BY2 = 0x21,
- DBG_BLOCK_ID_UNUSED10_BY2 = 0x22,
- DBG_BLOCK_ID_UNUSED12_BY2 = 0x23,
- DBG_BLOCK_ID_CB_BY2 = 0x24,
- DBG_BLOCK_ID_CB02_BY2 = 0x25,
- DBG_BLOCK_ID_CB10_BY2 = 0x26,
- DBG_BLOCK_ID_CB12_BY2 = 0x27,
- DBG_BLOCK_ID_SXS_BY2 = 0x28,
- DBG_BLOCK_ID_SXS2_BY2 = 0x29,
- DBG_BLOCK_ID_SXS4_BY2 = 0x2a,
- DBG_BLOCK_ID_SXS6_BY2 = 0x2b,
- DBG_BLOCK_ID_DB_BY2 = 0x2c,
- DBG_BLOCK_ID_DB02_BY2 = 0x2d,
- DBG_BLOCK_ID_DB10_BY2 = 0x2e,
- DBG_BLOCK_ID_DB12_BY2 = 0x2f,
- DBG_BLOCK_ID_TCP_BY2 = 0x30,
- DBG_BLOCK_ID_TCP2_BY2 = 0x31,
- DBG_BLOCK_ID_TCP4_BY2 = 0x32,
- DBG_BLOCK_ID_TCP6_BY2 = 0x33,
- DBG_BLOCK_ID_TCP8_BY2 = 0x34,
- DBG_BLOCK_ID_TCP10_BY2 = 0x35,
- DBG_BLOCK_ID_TCP12_BY2 = 0x36,
- DBG_BLOCK_ID_TCP14_BY2 = 0x37,
- DBG_BLOCK_ID_TCP16_BY2 = 0x38,
- DBG_BLOCK_ID_TCP18_BY2 = 0x39,
- DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
- DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
- DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
- DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
- DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
- DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
- DBG_BLOCK_ID_TCC_BY2 = 0x40,
- DBG_BLOCK_ID_TCC2_BY2 = 0x41,
- DBG_BLOCK_ID_TCC4_BY2 = 0x42,
- DBG_BLOCK_ID_TCC6_BY2 = 0x43,
- DBG_BLOCK_ID_SPS_BY2 = 0x44,
- DBG_BLOCK_ID_SPS02_BY2 = 0x45,
- DBG_BLOCK_ID_SPS11_BY2 = 0x46,
- DBG_BLOCK_ID_UNUSED14_BY2 = 0x47,
- DBG_BLOCK_ID_TA_BY2 = 0x48,
- DBG_BLOCK_ID_TA02_BY2 = 0x49,
- DBG_BLOCK_ID_TA04_BY2 = 0x4a,
- DBG_BLOCK_ID_TA06_BY2 = 0x4b,
- DBG_BLOCK_ID_TA08_BY2 = 0x4c,
- DBG_BLOCK_ID_TA0A_BY2 = 0x4d,
- DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e,
- DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f,
- DBG_BLOCK_ID_TA10_BY2 = 0x50,
- DBG_BLOCK_ID_TA12_BY2 = 0x51,
- DBG_BLOCK_ID_TA14_BY2 = 0x52,
- DBG_BLOCK_ID_TA16_BY2 = 0x53,
- DBG_BLOCK_ID_TA18_BY2 = 0x54,
- DBG_BLOCK_ID_TA1A_BY2 = 0x55,
- DBG_BLOCK_ID_UNUSED24_BY2 = 0x56,
- DBG_BLOCK_ID_UNUSED26_BY2 = 0x57,
- DBG_BLOCK_ID_TD_BY2 = 0x58,
- DBG_BLOCK_ID_TD02_BY2 = 0x59,
- DBG_BLOCK_ID_TD04_BY2 = 0x5a,
- DBG_BLOCK_ID_TD06_BY2 = 0x5b,
- DBG_BLOCK_ID_TD08_BY2 = 0x5c,
- DBG_BLOCK_ID_TD0A_BY2 = 0x5d,
- DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e,
- DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f,
- DBG_BLOCK_ID_TD10_BY2 = 0x60,
- DBG_BLOCK_ID_TD12_BY2 = 0x61,
- DBG_BLOCK_ID_TD14_BY2 = 0x62,
- DBG_BLOCK_ID_TD16_BY2 = 0x63,
- DBG_BLOCK_ID_TD18_BY2 = 0x64,
- DBG_BLOCK_ID_TD1A_BY2 = 0x65,
- DBG_BLOCK_ID_UNUSED32_BY2 = 0x66,
- DBG_BLOCK_ID_UNUSED34_BY2 = 0x67,
- DBG_BLOCK_ID_LDS_BY2 = 0x68,
- DBG_BLOCK_ID_LDS02_BY2 = 0x69,
- DBG_BLOCK_ID_LDS04_BY2 = 0x6a,
- DBG_BLOCK_ID_LDS06_BY2 = 0x6b,
- DBG_BLOCK_ID_LDS08_BY2 = 0x6c,
- DBG_BLOCK_ID_LDS0A_BY2 = 0x6d,
- DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e,
- DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f,
- DBG_BLOCK_ID_LDS10_BY2 = 0x70,
- DBG_BLOCK_ID_LDS12_BY2 = 0x71,
- DBG_BLOCK_ID_LDS14_BY2 = 0x72,
- DBG_BLOCK_ID_LDS16_BY2 = 0x73,
- DBG_BLOCK_ID_LDS18_BY2 = 0x74,
- DBG_BLOCK_ID_LDS1A_BY2 = 0x75,
- DBG_BLOCK_ID_UNUSED40_BY2 = 0x76,
- DBG_BLOCK_ID_UNUSED42_BY2 = 0x77,
-} DebugBlockId_BY2;
-typedef enum DebugBlockId_BY4 {
- DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
- DBG_BLOCK_ID_UNUSED0_BY4 = 0x1,
- DBG_BLOCK_ID_CSC_BY4 = 0x2,
- DBG_BLOCK_ID_SQ_BY4 = 0x3,
- DBG_BLOCK_ID_SDMA0_BY4 = 0x4,
- DBG_BLOCK_ID_VC0_BY4 = 0x5,
- DBG_BLOCK_ID_CP0_BY4 = 0x6,
- DBG_BLOCK_ID_UNUSED1_BY4 = 0x7,
- DBG_BLOCK_ID_SXM0_BY4 = 0x8,
- DBG_BLOCK_ID_SPM0_BY4 = 0x9,
- DBG_BLOCK_ID_TCAA_BY4 = 0xa,
- DBG_BLOCK_ID_MCC_BY4 = 0xb,
- DBG_BLOCK_ID_MCD_BY4 = 0xc,
- DBG_BLOCK_ID_MCD4_BY4 = 0xd,
- DBG_BLOCK_ID_SQA_BY4 = 0xe,
- DBG_BLOCK_ID_SQA11_BY4 = 0xf,
- DBG_BLOCK_ID_SQB_BY4 = 0x10,
- DBG_BLOCK_ID_UNUSED10_BY4 = 0x11,
- DBG_BLOCK_ID_CB_BY4 = 0x12,
- DBG_BLOCK_ID_CB10_BY4 = 0x13,
- DBG_BLOCK_ID_SXS_BY4 = 0x14,
- DBG_BLOCK_ID_SXS4_BY4 = 0x15,
- DBG_BLOCK_ID_DB_BY4 = 0x16,
- DBG_BLOCK_ID_DB10_BY4 = 0x17,
- DBG_BLOCK_ID_TCP_BY4 = 0x18,
- DBG_BLOCK_ID_TCP4_BY4 = 0x19,
- DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
- DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
- DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
- DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
- DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
- DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
- DBG_BLOCK_ID_TCC_BY4 = 0x20,
- DBG_BLOCK_ID_TCC4_BY4 = 0x21,
- DBG_BLOCK_ID_SPS_BY4 = 0x22,
- DBG_BLOCK_ID_SPS11_BY4 = 0x23,
- DBG_BLOCK_ID_TA_BY4 = 0x24,
- DBG_BLOCK_ID_TA04_BY4 = 0x25,
- DBG_BLOCK_ID_TA08_BY4 = 0x26,
- DBG_BLOCK_ID_UNUSED20_BY4 = 0x27,
- DBG_BLOCK_ID_TA10_BY4 = 0x28,
- DBG_BLOCK_ID_TA14_BY4 = 0x29,
- DBG_BLOCK_ID_TA18_BY4 = 0x2a,
- DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b,
- DBG_BLOCK_ID_TD_BY4 = 0x2c,
- DBG_BLOCK_ID_TD04_BY4 = 0x2d,
- DBG_BLOCK_ID_TD08_BY4 = 0x2e,
- DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f,
- DBG_BLOCK_ID_TD10_BY4 = 0x30,
- DBG_BLOCK_ID_TD14_BY4 = 0x31,
- DBG_BLOCK_ID_TD18_BY4 = 0x32,
- DBG_BLOCK_ID_UNUSED32_BY4 = 0x33,
- DBG_BLOCK_ID_LDS_BY4 = 0x34,
- DBG_BLOCK_ID_LDS04_BY4 = 0x35,
- DBG_BLOCK_ID_LDS08_BY4 = 0x36,
- DBG_BLOCK_ID_UNUSED36_BY4 = 0x37,
- DBG_BLOCK_ID_LDS10_BY4 = 0x38,
- DBG_BLOCK_ID_LDS14_BY4 = 0x39,
- DBG_BLOCK_ID_LDS18_BY4 = 0x3a,
- DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b,
-} DebugBlockId_BY4;
-typedef enum DebugBlockId_BY8 {
- DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
- DBG_BLOCK_ID_CSC_BY8 = 0x1,
- DBG_BLOCK_ID_SDMA0_BY8 = 0x2,
- DBG_BLOCK_ID_CP0_BY8 = 0x3,
- DBG_BLOCK_ID_SXM0_BY8 = 0x4,
- DBG_BLOCK_ID_TCA_BY8 = 0x5,
- DBG_BLOCK_ID_MCD_BY8 = 0x6,
- DBG_BLOCK_ID_SQA_BY8 = 0x7,
- DBG_BLOCK_ID_SQB_BY8 = 0x8,
- DBG_BLOCK_ID_CB_BY8 = 0x9,
- DBG_BLOCK_ID_SXS_BY8 = 0xa,
- DBG_BLOCK_ID_DB_BY8 = 0xb,
- DBG_BLOCK_ID_TCP_BY8 = 0xc,
- DBG_BLOCK_ID_TCP8_BY8 = 0xd,
- DBG_BLOCK_ID_TCP16_BY8 = 0xe,
- DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
- DBG_BLOCK_ID_TCC_BY8 = 0x10,
- DBG_BLOCK_ID_SPS_BY8 = 0x11,
- DBG_BLOCK_ID_TA_BY8 = 0x12,
- DBG_BLOCK_ID_TA08_BY8 = 0x13,
- DBG_BLOCK_ID_TA10_BY8 = 0x14,
- DBG_BLOCK_ID_TA18_BY8 = 0x15,
- DBG_BLOCK_ID_TD_BY8 = 0x16,
- DBG_BLOCK_ID_TD08_BY8 = 0x17,
- DBG_BLOCK_ID_TD10_BY8 = 0x18,
- DBG_BLOCK_ID_TD18_BY8 = 0x19,
- DBG_BLOCK_ID_LDS_BY8 = 0x1a,
- DBG_BLOCK_ID_LDS08_BY8 = 0x1b,
- DBG_BLOCK_ID_LDS10_BY8 = 0x1c,
- DBG_BLOCK_ID_LDS18_BY8 = 0x1d,
-} DebugBlockId_BY8;
-typedef enum DebugBlockId_BY16 {
- DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
- DBG_BLOCK_ID_SDMA0_BY16 = 0x1,
- DBG_BLOCK_ID_SXM_BY16 = 0x2,
- DBG_BLOCK_ID_MCD_BY16 = 0x3,
- DBG_BLOCK_ID_SQB_BY16 = 0x4,
- DBG_BLOCK_ID_SXS_BY16 = 0x5,
- DBG_BLOCK_ID_TCP_BY16 = 0x6,
- DBG_BLOCK_ID_TCP16_BY16 = 0x7,
- DBG_BLOCK_ID_TCC_BY16 = 0x8,
- DBG_BLOCK_ID_TA_BY16 = 0x9,
- DBG_BLOCK_ID_TA10_BY16 = 0xa,
- DBG_BLOCK_ID_TD_BY16 = 0xb,
- DBG_BLOCK_ID_TD10_BY16 = 0xc,
- DBG_BLOCK_ID_LDS_BY16 = 0xd,
- DBG_BLOCK_ID_LDS10_BY16 = 0xe,
-} DebugBlockId_BY16;
-typedef enum SurfaceEndian {
- ENDIAN_NONE = 0x0,
- ENDIAN_8IN16 = 0x1,
- ENDIAN_8IN32 = 0x2,
- ENDIAN_8IN64 = 0x3,
-} SurfaceEndian;
-typedef enum ArrayMode {
- ARRAY_LINEAR_GENERAL = 0x0,
- ARRAY_LINEAR_ALIGNED = 0x1,
- ARRAY_1D_TILED_THIN1 = 0x2,
- ARRAY_1D_TILED_THICK = 0x3,
- ARRAY_2D_TILED_THIN1 = 0x4,
- ARRAY_PRT_TILED_THIN1 = 0x5,
- ARRAY_PRT_2D_TILED_THIN1 = 0x6,
- ARRAY_2D_TILED_THICK = 0x7,
- ARRAY_2D_TILED_XTHICK = 0x8,
- ARRAY_PRT_TILED_THICK = 0x9,
- ARRAY_PRT_2D_TILED_THICK = 0xa,
- ARRAY_PRT_3D_TILED_THIN1 = 0xb,
- ARRAY_3D_TILED_THIN1 = 0xc,
- ARRAY_3D_TILED_THICK = 0xd,
- ARRAY_3D_TILED_XTHICK = 0xe,
- ARRAY_PRT_3D_TILED_THICK = 0xf,
-} ArrayMode;
-typedef enum PipeTiling {
- CONFIG_1_PIPE = 0x0,
- CONFIG_2_PIPE = 0x1,
- CONFIG_4_PIPE = 0x2,
- CONFIG_8_PIPE = 0x3,
-} PipeTiling;
-typedef enum BankTiling {
- CONFIG_4_BANK = 0x0,
- CONFIG_8_BANK = 0x1,
-} BankTiling;
-typedef enum GroupInterleave {
- CONFIG_256B_GROUP = 0x0,
- CONFIG_512B_GROUP = 0x1,
-} GroupInterleave;
-typedef enum RowTiling {
- CONFIG_1KB_ROW = 0x0,
- CONFIG_2KB_ROW = 0x1,
- CONFIG_4KB_ROW = 0x2,
- CONFIG_8KB_ROW = 0x3,
- CONFIG_1KB_ROW_OPT = 0x4,
- CONFIG_2KB_ROW_OPT = 0x5,
- CONFIG_4KB_ROW_OPT = 0x6,
- CONFIG_8KB_ROW_OPT = 0x7,
-} RowTiling;
-typedef enum BankSwapBytes {
- CONFIG_128B_SWAPS = 0x0,
- CONFIG_256B_SWAPS = 0x1,
- CONFIG_512B_SWAPS = 0x2,
- CONFIG_1KB_SWAPS = 0x3,
-} BankSwapBytes;
-typedef enum SampleSplitBytes {
- CONFIG_1KB_SPLIT = 0x0,
- CONFIG_2KB_SPLIT = 0x1,
- CONFIG_4KB_SPLIT = 0x2,
- CONFIG_8KB_SPLIT = 0x3,
-} SampleSplitBytes;
-typedef enum NumPipes {
- ADDR_CONFIG_1_PIPE = 0x0,
- ADDR_CONFIG_2_PIPE = 0x1,
- ADDR_CONFIG_4_PIPE = 0x2,
- ADDR_CONFIG_8_PIPE = 0x3,
-} NumPipes;
-typedef enum PipeInterleaveSize {
- ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
- ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
-} PipeInterleaveSize;
-typedef enum BankInterleaveSize {
- ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
- ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
- ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
- ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
-} BankInterleaveSize;
-typedef enum NumShaderEngines {
- ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
- ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
-} NumShaderEngines;
-typedef enum ShaderEngineTileSize {
- ADDR_CONFIG_SE_TILE_16 = 0x0,
- ADDR_CONFIG_SE_TILE_32 = 0x1,
-} ShaderEngineTileSize;
-typedef enum NumGPUs {
- ADDR_CONFIG_1_GPU = 0x0,
- ADDR_CONFIG_2_GPU = 0x1,
- ADDR_CONFIG_4_GPU = 0x2,
-} NumGPUs;
-typedef enum MultiGPUTileSize {
- ADDR_CONFIG_GPU_TILE_16 = 0x0,
- ADDR_CONFIG_GPU_TILE_32 = 0x1,
- ADDR_CONFIG_GPU_TILE_64 = 0x2,
- ADDR_CONFIG_GPU_TILE_128 = 0x3,
-} MultiGPUTileSize;
-typedef enum RowSize {
- ADDR_CONFIG_1KB_ROW = 0x0,
- ADDR_CONFIG_2KB_ROW = 0x1,
- ADDR_CONFIG_4KB_ROW = 0x2,
-} RowSize;
-typedef enum NumLowerPipes {
- ADDR_CONFIG_1_LOWER_PIPES = 0x0,
- ADDR_CONFIG_2_LOWER_PIPES = 0x1,
-} NumLowerPipes;
-typedef enum ColorTransform {
- DCC_CT_AUTO = 0x0,
- DCC_CT_NONE = 0x1,
- ABGR_TO_A_BG_G_RB = 0x2,
- BGRA_TO_BG_G_RB_A = 0x3,
-} ColorTransform;
-typedef enum CompareRef {
- REF_NEVER = 0x0,
- REF_LESS = 0x1,
- REF_EQUAL = 0x2,
- REF_LEQUAL = 0x3,
- REF_GREATER = 0x4,
- REF_NOTEQUAL = 0x5,
- REF_GEQUAL = 0x6,
- REF_ALWAYS = 0x7,
-} CompareRef;
-typedef enum ReadSize {
- READ_256_BITS = 0x0,
- READ_512_BITS = 0x1,
-} ReadSize;
-typedef enum DepthFormat {
- DEPTH_INVALID = 0x0,
- DEPTH_16 = 0x1,
- DEPTH_X8_24 = 0x2,
- DEPTH_8_24 = 0x3,
- DEPTH_X8_24_FLOAT = 0x4,
- DEPTH_8_24_FLOAT = 0x5,
- DEPTH_32_FLOAT = 0x6,
- DEPTH_X24_8_32_FLOAT = 0x7,
-} DepthFormat;
-typedef enum ZFormat {
- Z_INVALID = 0x0,
- Z_16 = 0x1,
- Z_24 = 0x2,
- Z_32_FLOAT = 0x3,
-} ZFormat;
-typedef enum StencilFormat {
- STENCIL_INVALID = 0x0,
- STENCIL_8 = 0x1,
-} StencilFormat;
-typedef enum CmaskMode {
- CMASK_CLEAR_NONE = 0x0,
- CMASK_CLEAR_ONE = 0x1,
- CMASK_CLEAR_ALL = 0x2,
- CMASK_ANY_EXPANDED = 0x3,
- CMASK_ALPHA0_FRAG1 = 0x4,
- CMASK_ALPHA0_FRAG2 = 0x5,
- CMASK_ALPHA0_FRAG4 = 0x6,
- CMASK_ALPHA0_FRAGS = 0x7,
- CMASK_ALPHA1_FRAG1 = 0x8,
- CMASK_ALPHA1_FRAG2 = 0x9,
- CMASK_ALPHA1_FRAG4 = 0xa,
- CMASK_ALPHA1_FRAGS = 0xb,
- CMASK_ALPHAX_FRAG1 = 0xc,
- CMASK_ALPHAX_FRAG2 = 0xd,
- CMASK_ALPHAX_FRAG4 = 0xe,
- CMASK_ALPHAX_FRAGS = 0xf,
-} CmaskMode;
-typedef enum QuadExportFormat {
- EXPORT_UNUSED = 0x0,
- EXPORT_32_R = 0x1,
- EXPORT_32_GR = 0x2,
- EXPORT_32_AR = 0x3,
- EXPORT_FP16_ABGR = 0x4,
- EXPORT_UNSIGNED16_ABGR = 0x5,
- EXPORT_SIGNED16_ABGR = 0x6,
- EXPORT_32_ABGR = 0x7,
-} QuadExportFormat;
-typedef enum QuadExportFormatOld {
- EXPORT_4P_32BPC_ABGR = 0x0,
- EXPORT_4P_16BPC_ABGR = 0x1,
- EXPORT_4P_32BPC_GR = 0x2,
- EXPORT_4P_32BPC_AR = 0x3,
- EXPORT_2P_32BPC_ABGR = 0x4,
- EXPORT_8P_32BPC_R = 0x5,
-} QuadExportFormatOld;
-typedef enum ColorFormat {
- COLOR_INVALID = 0x0,
- COLOR_8 = 0x1,
- COLOR_16 = 0x2,
- COLOR_8_8 = 0x3,
- COLOR_32 = 0x4,
- COLOR_16_16 = 0x5,
- COLOR_10_11_11 = 0x6,
- COLOR_11_11_10 = 0x7,
- COLOR_10_10_10_2 = 0x8,
- COLOR_2_10_10_10 = 0x9,
- COLOR_8_8_8_8 = 0xa,
- COLOR_32_32 = 0xb,
- COLOR_16_16_16_16 = 0xc,
- COLOR_RESERVED_13 = 0xd,
- COLOR_32_32_32_32 = 0xe,
- COLOR_RESERVED_15 = 0xf,
- COLOR_5_6_5 = 0x10,
- COLOR_1_5_5_5 = 0x11,
- COLOR_5_5_5_1 = 0x12,
- COLOR_4_4_4_4 = 0x13,
- COLOR_8_24 = 0x14,
- COLOR_24_8 = 0x15,
- COLOR_X24_8_32_FLOAT = 0x16,
- COLOR_RESERVED_23 = 0x17,
-} ColorFormat;
-typedef enum SurfaceFormat {
- FMT_INVALID = 0x0,
- FMT_8 = 0x1,
- FMT_16 = 0x2,
- FMT_8_8 = 0x3,
- FMT_32 = 0x4,
- FMT_16_16 = 0x5,
- FMT_10_11_11 = 0x6,
- FMT_11_11_10 = 0x7,
- FMT_10_10_10_2 = 0x8,
- FMT_2_10_10_10 = 0x9,
- FMT_8_8_8_8 = 0xa,
- FMT_32_32 = 0xb,
- FMT_16_16_16_16 = 0xc,
- FMT_32_32_32 = 0xd,
- FMT_32_32_32_32 = 0xe,
- FMT_RESERVED_4 = 0xf,
- FMT_5_6_5 = 0x10,
- FMT_1_5_5_5 = 0x11,
- FMT_5_5_5_1 = 0x12,
- FMT_4_4_4_4 = 0x13,
- FMT_8_24 = 0x14,
- FMT_24_8 = 0x15,
- FMT_X24_8_32_FLOAT = 0x16,
- FMT_RESERVED_33 = 0x17,
- FMT_11_11_10_FLOAT = 0x18,
- FMT_16_FLOAT = 0x19,
- FMT_32_FLOAT = 0x1a,
- FMT_16_16_FLOAT = 0x1b,
- FMT_8_24_FLOAT = 0x1c,
- FMT_24_8_FLOAT = 0x1d,
- FMT_32_32_FLOAT = 0x1e,
- FMT_10_11_11_FLOAT = 0x1f,
- FMT_16_16_16_16_FLOAT = 0x20,
- FMT_3_3_2 = 0x21,
- FMT_6_5_5 = 0x22,
- FMT_32_32_32_32_FLOAT = 0x23,
- FMT_RESERVED_36 = 0x24,
- FMT_1 = 0x25,
- FMT_1_REVERSED = 0x26,
- FMT_GB_GR = 0x27,
- FMT_BG_RG = 0x28,
- FMT_32_AS_8 = 0x29,
- FMT_32_AS_8_8 = 0x2a,
- FMT_5_9_9_9_SHAREDEXP = 0x2b,
- FMT_8_8_8 = 0x2c,
- FMT_16_16_16 = 0x2d,
- FMT_16_16_16_FLOAT = 0x2e,
- FMT_4_4 = 0x2f,
- FMT_32_32_32_FLOAT = 0x30,
- FMT_BC1 = 0x31,
- FMT_BC2 = 0x32,
- FMT_BC3 = 0x33,
- FMT_BC4 = 0x34,
- FMT_BC5 = 0x35,
- FMT_BC6 = 0x36,
- FMT_BC7 = 0x37,
- FMT_32_AS_32_32_32_32 = 0x38,
- FMT_APC3 = 0x39,
- FMT_APC4 = 0x3a,
- FMT_APC5 = 0x3b,
- FMT_APC6 = 0x3c,
- FMT_APC7 = 0x3d,
- FMT_CTX1 = 0x3e,
- FMT_RESERVED_63 = 0x3f,
-} SurfaceFormat;
-typedef enum BUF_DATA_FORMAT {
- BUF_DATA_FORMAT_INVALID = 0x0,
- BUF_DATA_FORMAT_8 = 0x1,
- BUF_DATA_FORMAT_16 = 0x2,
- BUF_DATA_FORMAT_8_8 = 0x3,
- BUF_DATA_FORMAT_32 = 0x4,
- BUF_DATA_FORMAT_16_16 = 0x5,
- BUF_DATA_FORMAT_10_11_11 = 0x6,
- BUF_DATA_FORMAT_11_11_10 = 0x7,
- BUF_DATA_FORMAT_10_10_10_2 = 0x8,
- BUF_DATA_FORMAT_2_10_10_10 = 0x9,
- BUF_DATA_FORMAT_8_8_8_8 = 0xa,
- BUF_DATA_FORMAT_32_32 = 0xb,
- BUF_DATA_FORMAT_16_16_16_16 = 0xc,
- BUF_DATA_FORMAT_32_32_32 = 0xd,
- BUF_DATA_FORMAT_32_32_32_32 = 0xe,
- BUF_DATA_FORMAT_RESERVED_15 = 0xf,
-} BUF_DATA_FORMAT;
-typedef enum IMG_DATA_FORMAT {
- IMG_DATA_FORMAT_INVALID = 0x0,
- IMG_DATA_FORMAT_8 = 0x1,
- IMG_DATA_FORMAT_16 = 0x2,
- IMG_DATA_FORMAT_8_8 = 0x3,
- IMG_DATA_FORMAT_32 = 0x4,
- IMG_DATA_FORMAT_16_16 = 0x5,
- IMG_DATA_FORMAT_10_11_11 = 0x6,
- IMG_DATA_FORMAT_11_11_10 = 0x7,
- IMG_DATA_FORMAT_10_10_10_2 = 0x8,
- IMG_DATA_FORMAT_2_10_10_10 = 0x9,
- IMG_DATA_FORMAT_8_8_8_8 = 0xa,
- IMG_DATA_FORMAT_32_32 = 0xb,
- IMG_DATA_FORMAT_16_16_16_16 = 0xc,
- IMG_DATA_FORMAT_32_32_32 = 0xd,
- IMG_DATA_FORMAT_32_32_32_32 = 0xe,
- IMG_DATA_FORMAT_RESERVED_15 = 0xf,
- IMG_DATA_FORMAT_5_6_5 = 0x10,
- IMG_DATA_FORMAT_1_5_5_5 = 0x11,
- IMG_DATA_FORMAT_5_5_5_1 = 0x12,
- IMG_DATA_FORMAT_4_4_4_4 = 0x13,
- IMG_DATA_FORMAT_8_24 = 0x14,
- IMG_DATA_FORMAT_24_8 = 0x15,
- IMG_DATA_FORMAT_X24_8_32 = 0x16,
- IMG_DATA_FORMAT_RESERVED_23 = 0x17,
- IMG_DATA_FORMAT_RESERVED_24 = 0x18,
- IMG_DATA_FORMAT_RESERVED_25 = 0x19,
- IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
- IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
- IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
- IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
- IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
- IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
- IMG_DATA_FORMAT_GB_GR = 0x20,
- IMG_DATA_FORMAT_BG_RG = 0x21,
- IMG_DATA_FORMAT_5_9_9_9 = 0x22,
- IMG_DATA_FORMAT_BC1 = 0x23,
- IMG_DATA_FORMAT_BC2 = 0x24,
- IMG_DATA_FORMAT_BC3 = 0x25,
- IMG_DATA_FORMAT_BC4 = 0x26,
- IMG_DATA_FORMAT_BC5 = 0x27,
- IMG_DATA_FORMAT_BC6 = 0x28,
- IMG_DATA_FORMAT_BC7 = 0x29,
- IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
- IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
- IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
- IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
- IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
- IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
- IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
- IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
- IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
- IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
- IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
- IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
- IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
- IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
- IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
- IMG_DATA_FORMAT_4_4 = 0x39,
- IMG_DATA_FORMAT_6_5_5 = 0x3a,
- IMG_DATA_FORMAT_1 = 0x3b,
- IMG_DATA_FORMAT_1_REVERSED = 0x3c,
- IMG_DATA_FORMAT_32_AS_8 = 0x3d,
- IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
- IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
-} IMG_DATA_FORMAT;
-typedef enum BUF_NUM_FORMAT {
- BUF_NUM_FORMAT_UNORM = 0x0,
- BUF_NUM_FORMAT_SNORM = 0x1,
- BUF_NUM_FORMAT_USCALED = 0x2,
- BUF_NUM_FORMAT_SSCALED = 0x3,
- BUF_NUM_FORMAT_UINT = 0x4,
- BUF_NUM_FORMAT_SINT = 0x5,
- BUF_NUM_FORMAT_RESERVED_6 = 0x6,
- BUF_NUM_FORMAT_FLOAT = 0x7,
-} BUF_NUM_FORMAT;
-typedef enum IMG_NUM_FORMAT {
- IMG_NUM_FORMAT_UNORM = 0x0,
- IMG_NUM_FORMAT_SNORM = 0x1,
- IMG_NUM_FORMAT_USCALED = 0x2,
- IMG_NUM_FORMAT_SSCALED = 0x3,
- IMG_NUM_FORMAT_UINT = 0x4,
- IMG_NUM_FORMAT_SINT = 0x5,
- IMG_NUM_FORMAT_RESERVED_6 = 0x6,
- IMG_NUM_FORMAT_FLOAT = 0x7,
- IMG_NUM_FORMAT_RESERVED_8 = 0x8,
- IMG_NUM_FORMAT_SRGB = 0x9,
- IMG_NUM_FORMAT_RESERVED_10 = 0xa,
- IMG_NUM_FORMAT_RESERVED_11 = 0xb,
- IMG_NUM_FORMAT_RESERVED_12 = 0xc,
- IMG_NUM_FORMAT_RESERVED_13 = 0xd,
- IMG_NUM_FORMAT_RESERVED_14 = 0xe,
- IMG_NUM_FORMAT_RESERVED_15 = 0xf,
-} IMG_NUM_FORMAT;
-typedef enum TileType {
- ARRAY_COLOR_TILE = 0x0,
- ARRAY_DEPTH_TILE = 0x1,
-} TileType;
-typedef enum NonDispTilingOrder {
- ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
- ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
-} NonDispTilingOrder;
-typedef enum MicroTileMode {
- ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
- ADDR_SURF_THIN_MICRO_TILING = 0x1,
- ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
- ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
- ADDR_SURF_THICK_MICRO_TILING = 0x4,
-} MicroTileMode;
-typedef enum TileSplit {
- ADDR_SURF_TILE_SPLIT_64B = 0x0,
- ADDR_SURF_TILE_SPLIT_128B = 0x1,
- ADDR_SURF_TILE_SPLIT_256B = 0x2,
- ADDR_SURF_TILE_SPLIT_512B = 0x3,
- ADDR_SURF_TILE_SPLIT_1KB = 0x4,
- ADDR_SURF_TILE_SPLIT_2KB = 0x5,
- ADDR_SURF_TILE_SPLIT_4KB = 0x6,
-} TileSplit;
-typedef enum SampleSplit {
- ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
- ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
- ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
- ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
-} SampleSplit;
-typedef enum PipeConfig {
- ADDR_SURF_P2 = 0x0,
- ADDR_SURF_P2_RESERVED0 = 0x1,
- ADDR_SURF_P2_RESERVED1 = 0x2,
- ADDR_SURF_P2_RESERVED2 = 0x3,
- ADDR_SURF_P4_8x16 = 0x4,
- ADDR_SURF_P4_16x16 = 0x5,
- ADDR_SURF_P4_16x32 = 0x6,
- ADDR_SURF_P4_32x32 = 0x7,
- ADDR_SURF_P8_16x16_8x16 = 0x8,
- ADDR_SURF_P8_16x32_8x16 = 0x9,
- ADDR_SURF_P8_32x32_8x16 = 0xa,
- ADDR_SURF_P8_16x32_16x16 = 0xb,
- ADDR_SURF_P8_32x32_16x16 = 0xc,
- ADDR_SURF_P8_32x32_16x32 = 0xd,
- ADDR_SURF_P8_32x64_32x32 = 0xe,
- ADDR_SURF_P8_RESERVED0 = 0xf,
- ADDR_SURF_P16_32x32_8x16 = 0x10,
- ADDR_SURF_P16_32x32_16x16 = 0x11,
-} PipeConfig;
-typedef enum NumBanks {
- ADDR_SURF_2_BANK = 0x0,
- ADDR_SURF_4_BANK = 0x1,
- ADDR_SURF_8_BANK = 0x2,
- ADDR_SURF_16_BANK = 0x3,
-} NumBanks;
-typedef enum BankWidth {
- ADDR_SURF_BANK_WIDTH_1 = 0x0,
- ADDR_SURF_BANK_WIDTH_2 = 0x1,
- ADDR_SURF_BANK_WIDTH_4 = 0x2,
- ADDR_SURF_BANK_WIDTH_8 = 0x3,
-} BankWidth;
-typedef enum BankHeight {
- ADDR_SURF_BANK_HEIGHT_1 = 0x0,
- ADDR_SURF_BANK_HEIGHT_2 = 0x1,
- ADDR_SURF_BANK_HEIGHT_4 = 0x2,
- ADDR_SURF_BANK_HEIGHT_8 = 0x3,
-} BankHeight;
-typedef enum BankWidthHeight {
- ADDR_SURF_BANK_WH_1 = 0x0,
- ADDR_SURF_BANK_WH_2 = 0x1,
- ADDR_SURF_BANK_WH_4 = 0x2,
- ADDR_SURF_BANK_WH_8 = 0x3,
-} BankWidthHeight;
-typedef enum MacroTileAspect {
- ADDR_SURF_MACRO_ASPECT_1 = 0x0,
- ADDR_SURF_MACRO_ASPECT_2 = 0x1,
- ADDR_SURF_MACRO_ASPECT_4 = 0x2,
- ADDR_SURF_MACRO_ASPECT_8 = 0x3,
-} MacroTileAspect;
-typedef enum GATCL1RequestType {
- GATCL1_TYPE_NORMAL = 0x0,
- GATCL1_TYPE_SHOOTDOWN = 0x1,
- GATCL1_TYPE_BYPASS = 0x2,
-} GATCL1RequestType;
-typedef enum TCC_CACHE_POLICIES {
- TCC_CACHE_POLICY_LRU = 0x0,
- TCC_CACHE_POLICY_STREAM = 0x1,
-} TCC_CACHE_POLICIES;
-typedef enum MTYPE {
- MTYPE_NC_NV = 0x0,
- MTYPE_NC = 0x1,
- MTYPE_CC = 0x2,
- MTYPE_UC = 0x3,
-} MTYPE;
-typedef enum PERFMON_COUNTER_MODE {
- PERFMON_COUNTER_MODE_ACCUM = 0x0,
- PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
- PERFMON_COUNTER_MODE_MAX = 0x2,
- PERFMON_COUNTER_MODE_DIRTY = 0x3,
- PERFMON_COUNTER_MODE_SAMPLE = 0x4,
- PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
- PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
- PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
- PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
- PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
- PERFMON_COUNTER_MODE_RESERVED = 0xf,
-} PERFMON_COUNTER_MODE;
-typedef enum PERFMON_SPM_MODE {
- PERFMON_SPM_MODE_OFF = 0x0,
- PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
- PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
- PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
- PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
- PERFMON_SPM_MODE_RESERVED_5 = 0x5,
- PERFMON_SPM_MODE_RESERVED_6 = 0x6,
- PERFMON_SPM_MODE_RESERVED_7 = 0x7,
- PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
- PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
- PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
-} PERFMON_SPM_MODE;
-typedef enum SurfaceTiling {
- ARRAY_LINEAR = 0x0,
- ARRAY_TILED = 0x1,
-} SurfaceTiling;
-typedef enum SurfaceArray {
- ARRAY_1D = 0x0,
- ARRAY_2D = 0x1,
- ARRAY_3D = 0x2,
- ARRAY_3D_SLICE = 0x3,
-} SurfaceArray;
-typedef enum ColorArray {
- ARRAY_2D_ALT_COLOR = 0x0,
- ARRAY_2D_COLOR = 0x1,
- ARRAY_3D_SLICE_COLOR = 0x3,
-} ColorArray;
-typedef enum DepthArray {
- ARRAY_2D_ALT_DEPTH = 0x0,
- ARRAY_2D_DEPTH = 0x1,
-} DepthArray;
-typedef enum ENUM_NUM_SIMD_PER_CU {
- NUM_SIMD_PER_CU = 0x4,
-} ENUM_NUM_SIMD_PER_CU;
-typedef enum MEM_PWR_FORCE_CTRL {
- NO_FORCE_REQUEST = 0x0,
- FORCE_LIGHT_SLEEP_REQUEST = 0x1,
- FORCE_DEEP_SLEEP_REQUEST = 0x2,
- FORCE_SHUT_DOWN_REQUEST = 0x3,
-} MEM_PWR_FORCE_CTRL;
-typedef enum MEM_PWR_FORCE_CTRL2 {
- NO_FORCE_REQ = 0x0,
- FORCE_LIGHT_SLEEP_REQ = 0x1,
-} MEM_PWR_FORCE_CTRL2;
-typedef enum MEM_PWR_DIS_CTRL {
- ENABLE_MEM_PWR_CTRL = 0x0,
- DISABLE_MEM_PWR_CTRL = 0x1,
-} MEM_PWR_DIS_CTRL;
-typedef enum MEM_PWR_SEL_CTRL {
- DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
- DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
- DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
-} MEM_PWR_SEL_CTRL;
-typedef enum MEM_PWR_SEL_CTRL2 {
- DYNAMIC_DEEP_SLEEP_EN = 0x0,
- DYNAMIC_LIGHT_SLEEP_EN = 0x1,
-} MEM_PWR_SEL_CTRL2;
-#define CG_SRBM_START_ADDR 0x600
-#define CG_SRBM_END_ADDR 0x8ff
-#define CG_SRBM_DEC0_START_ADDR 0x200
-#define CG_SRBM_DEC0_END_ADDR 0x2ff
-
-#endif /* SMU_8_0_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_2_offset.h
deleted file mode 100644
index a4dd372c0..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_2_offset.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * Copyright (C) 2023 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _smuio_10_0_2_OFFSET_HEADER
-
-// addressBlock: smuio_smuio_misc_SmuSmuioDec
-// base address: 0x5a000
-#define mmSMUIO_MCM_CONFIG 0x0023
-#define mmSMUIO_MCM_CONFIG_BASE_IDX 0
-#define mmIP_DISCOVERY_VERSION 0x0000
-#define mmIP_DISCOVERY_VERSION_BASE_IDX 1
-#define mmIO_SMUIO_PINSTRAP 0x01b1
-#define mmIO_SMUIO_PINSTRAP_BASE_IDX 1
-#define mmSCRATCH_REGISTER0 0x01b2
-#define mmSCRATCH_REGISTER0_BASE_IDX 1
-#define mmSCRATCH_REGISTER1 0x01b3
-#define mmSCRATCH_REGISTER1_BASE_IDX 1
-#define mmSCRATCH_REGISTER2 0x01b4
-#define mmSCRATCH_REGISTER2_BASE_IDX 1
-#define mmSCRATCH_REGISTER3 0x01b5
-#define mmSCRATCH_REGISTER3_BASE_IDX 1
-#define mmSCRATCH_REGISTER4 0x01b6
-#define mmSCRATCH_REGISTER4_BASE_IDX 1
-#define mmSCRATCH_REGISTER5 0x01b7
-#define mmSCRATCH_REGISTER5_BASE_IDX 1
-#define mmSCRATCH_REGISTER6 0x01b8
-#define mmSCRATCH_REGISTER6_BASE_IDX 1
-#define mmSCRATCH_REGISTER7 0x01b9
-#define mmSCRATCH_REGISTER7_BASE_IDX 1
-
-
-// addressBlock: smuio_smuio_reset_SmuSmuioDec
-// base address: 0x5a300
-#define mmSMUIO_MP_RESET_INTR 0x00c1
-#define mmSMUIO_MP_RESET_INTR_BASE_IDX 0
-#define mmSMUIO_SOC_HALT 0x00c2
-#define mmSMUIO_SOC_HALT_BASE_IDX 0
-#define mmSMUIO_GFX_MISC_CNTL 0x00c8
-#define mmSMUIO_GFX_MISC_CNTL_BASE_IDX 0
-
-
-// addressBlock: smuio_smuio_ccxctrl_SmuSmuioDec
-// base address: 0x5a000
-#define mmPWROK_REFCLK_GAP_CYCLES 0x0001
-#define mmPWROK_REFCLK_GAP_CYCLES_BASE_IDX 1
-#define mmGOLDEN_TSC_INCREMENT_UPPER 0x0004
-#define mmGOLDEN_TSC_INCREMENT_UPPER_BASE_IDX 1
-#define mmGOLDEN_TSC_INCREMENT_LOWER 0x0005
-#define mmGOLDEN_TSC_INCREMENT_LOWER_BASE_IDX 1
-#define mmGOLDEN_TSC_COUNT_UPPER 0x0025
-#define mmGOLDEN_TSC_COUNT_UPPER_BASE_IDX 1
-#define mmGOLDEN_TSC_COUNT_LOWER 0x0026
-#define mmGOLDEN_TSC_COUNT_LOWER_BASE_IDX 1
-#define mmGFX_GOLDEN_TSC_SHADOW_UPPER 0x0029
-#define mmGFX_GOLDEN_TSC_SHADOW_UPPER_BASE_IDX 1
-#define mmGFX_GOLDEN_TSC_SHADOW_LOWER 0x002a
-#define mmGFX_GOLDEN_TSC_SHADOW_LOWER_BASE_IDX 1
-#define mmSOC_GOLDEN_TSC_SHADOW_UPPER 0x002b
-#define mmSOC_GOLDEN_TSC_SHADOW_UPPER_BASE_IDX 1
-#define mmSOC_GOLDEN_TSC_SHADOW_LOWER 0x002c
-#define mmSOC_GOLDEN_TSC_SHADOW_LOWER_BASE_IDX 1
-#define mmSOC_GAP_PWROK 0x002d
-#define mmSOC_GAP_PWROK_BASE_IDX 1
-
-// addressBlock: smuio_smuio_swtimer_SmuSmuioDec
-// base address: 0x5ac40
-#define mmPWR_VIRT_RESET_REQ 0x0110
-#define mmPWR_VIRT_RESET_REQ_BASE_IDX 1
-#define mmPWR_DISP_TIMER_CONTROL 0x0111
-#define mmPWR_DISP_TIMER_CONTROL_BASE_IDX 1
-#define mmPWR_DISP_TIMER2_CONTROL 0x0113
-#define mmPWR_DISP_TIMER2_CONTROL_BASE_IDX 1
-#define mmPWR_DISP_TIMER_GLOBAL_CONTROL 0x0115
-#define mmPWR_DISP_TIMER_GLOBAL_CONTROL_BASE_IDX 1
-#define mmPWR_IH_CONTROL 0x0116
-#define mmPWR_IH_CONTROL_BASE_IDX 1
-
-// addressBlock: smuio_smuio_svi0_SmuSmuioDec
-// base address: 0x6f000
-#define mmSMUSVI0_TEL_PLANE0 0x520e
-#define mmSMUSVI0_TEL_PLANE0_BASE_IDX 1
-#define mmSMUSVI0_PLANE0_CURRENTVID 0x5217
-#define mmSMUSVI0_PLANE0_CURRENTVID_BASE_IDX 1
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_2_sh_mask.h
deleted file mode 100644
index d10ae61c3..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_2_sh_mask.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * Copyright (C) 2023 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _smuio_10_0_2_SH_MASK_HEADER
-
-// addressBlock: smuio_smuio_misc_SmuSmuioDec
-//SMUIO_MCM_CONFIG
-#define SMUIO_MCM_CONFIG__DIE_ID__SHIFT 0x0
-#define SMUIO_MCM_CONFIG__PKG_TYPE__SHIFT 0x2
-#define SMUIO_MCM_CONFIG__SOCKET_ID__SHIFT 0x5
-#define SMUIO_MCM_CONFIG__PKG_SUBTYPE__SHIFT 0x6
-#define SMUIO_MCM_CONFIG__CONSOLE_K__SHIFT 0x10
-#define SMUIO_MCM_CONFIG__CONSOLE_A__SHIFT 0x11
-#define SMUIO_MCM_CONFIG__DIE_ID_MASK 0x00000003L
-#define SMUIO_MCM_CONFIG__PKG_TYPE_MASK 0x0000001CL
-#define SMUIO_MCM_CONFIG__SOCKET_ID_MASK 0x00000020L
-#define SMUIO_MCM_CONFIG__PKG_SUBTYPE_MASK 0x000000C0L
-#define SMUIO_MCM_CONFIG__CONSOLE_K_MASK 0x00010000L
-#define SMUIO_MCM_CONFIG__CONSOLE_A_MASK 0x00020000L
-//IP_DISCOVERY_VERSION
-#define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION__SHIFT 0x0
-#define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION_MASK 0xFFFFFFFFL
-//IO_SMUIO_PINSTRAP
-#define IO_SMUIO_PINSTRAP__AUD_PORT_CONN__SHIFT 0x0
-#define IO_SMUIO_PINSTRAP__AUD__SHIFT 0x3
-#define IO_SMUIO_PINSTRAP__AUD_PORT_CONN_MASK 0x00000007L
-#define IO_SMUIO_PINSTRAP__AUD_MASK 0x00000018L
-//SCRATCH_REGISTER0
-#define SCRATCH_REGISTER0__ScratchPad0__SHIFT 0x0
-#define SCRATCH_REGISTER0__ScratchPad0_MASK 0xFFFFFFFFL
-//SCRATCH_REGISTER1
-#define SCRATCH_REGISTER1__ScratchPad1__SHIFT 0x0
-#define SCRATCH_REGISTER1__ScratchPad1_MASK 0xFFFFFFFFL
-//SCRATCH_REGISTER2
-#define SCRATCH_REGISTER2__ScratchPad2__SHIFT 0x0
-#define SCRATCH_REGISTER2__ScratchPad2_MASK 0xFFFFFFFFL
-//SCRATCH_REGISTER3
-#define SCRATCH_REGISTER3__ScratchPad3__SHIFT 0x0
-#define SCRATCH_REGISTER3__ScratchPad3_MASK 0xFFFFFFFFL
-//SCRATCH_REGISTER4
-#define SCRATCH_REGISTER4__ScratchPad4__SHIFT 0x0
-#define SCRATCH_REGISTER4__ScratchPad4_MASK 0xFFFFFFFFL
-//SCRATCH_REGISTER5
-#define SCRATCH_REGISTER5__ScratchPad5__SHIFT 0x0
-#define SCRATCH_REGISTER5__ScratchPad5_MASK 0xFFFFFFFFL
-//SCRATCH_REGISTER6
-#define SCRATCH_REGISTER6__ScratchPad6__SHIFT 0x0
-#define SCRATCH_REGISTER6__ScratchPad6_MASK 0xFFFFFFFFL
-//SCRATCH_REGISTER7
-#define SCRATCH_REGISTER7__ScratchPad7__SHIFT 0x0
-#define SCRATCH_REGISTER7__ScratchPad7_MASK 0xFFFFFFFFL
-
-// addressBlock: smuio_smuio_reset_SmuSmuioDec
-//SMUIO_MP_RESET_INTR
-#define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR__SHIFT 0x0
-#define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR_MASK 0x00000001L
-//SMUIO_SOC_HALT
-#define SMUIO_SOC_HALT__WDT_FORCE_PWROK_EN__SHIFT 0x2
-#define SMUIO_SOC_HALT__WDT_FORCE_RESETn_EN__SHIFT 0x3
-#define SMUIO_SOC_HALT__WDT_FORCE_PWROK_EN_MASK 0x00000004L
-#define SMUIO_SOC_HALT__WDT_FORCE_RESETn_EN_MASK 0x00000008L
-//SMUIO_GFX_MISC_CNTL
-#define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff__SHIFT 0x0
-#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT 0x1
-#define SMUIO_GFX_MISC_CNTL__PWR_GFX_DLDO_CLK_SWITCH__SHIFT 0x3
-#define SMUIO_GFX_MISC_CNTL__PWR_GFX_RLC_CGPG_EN__SHIFT 0x4
-#define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff_MASK 0x00000001L
-#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK 0x00000006L
-#define SMUIO_GFX_MISC_CNTL__PWR_GFX_DLDO_CLK_SWITCH_MASK 0x00000008L
-#define SMUIO_GFX_MISC_CNTL__PWR_GFX_RLC_CGPG_EN_MASK 0x00000010L
-
-// addressBlock: smuio_smuio_ccxctrl_SmuSmuioDec
-//PWROK_REFCLK_GAP_CYCLES
-#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles__SHIFT 0x0
-#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles__SHIFT 0x8
-#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles_MASK 0x000000FFL
-#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles_MASK 0x0000FF00L
-//GOLDEN_TSC_INCREMENT_UPPER
-#define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper__SHIFT 0x0
-#define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper_MASK 0x00FFFFFFL
-//GOLDEN_TSC_INCREMENT_LOWER
-#define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower__SHIFT 0x0
-#define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower_MASK 0xFFFFFFFFL
-//GOLDEN_TSC_COUNT_UPPER
-#define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper__SHIFT 0x0
-#define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper_MASK 0x00FFFFFFL
-//GOLDEN_TSC_COUNT_LOWER
-#define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower__SHIFT 0x0
-#define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower_MASK 0xFFFFFFFFL
-//GFX_GOLDEN_TSC_SHADOW_UPPER
-#define GFX_GOLDEN_TSC_SHADOW_UPPER__GfxGoldenTscShadowUpper__SHIFT 0x0
-#define GFX_GOLDEN_TSC_SHADOW_UPPER__GfxGoldenTscShadowUpper_MASK 0x00FFFFFFL
-//GFX_GOLDEN_TSC_SHADOW_LOWER
-#define GFX_GOLDEN_TSC_SHADOW_LOWER__GfxGoldenTscShadowLower__SHIFT 0x0
-#define GFX_GOLDEN_TSC_SHADOW_LOWER__GfxGoldenTscShadowLower_MASK 0xFFFFFFFFL
-//SOC_GOLDEN_TSC_SHADOW_UPPER
-#define SOC_GOLDEN_TSC_SHADOW_UPPER__SocGoldenTscShadowUpper__SHIFT 0x0
-#define SOC_GOLDEN_TSC_SHADOW_UPPER__SocGoldenTscShadowUpper_MASK 0x00FFFFFFL
-//SOC_GOLDEN_TSC_SHADOW_LOWER
-#define SOC_GOLDEN_TSC_SHADOW_LOWER__SocGoldenTscShadowLower__SHIFT 0x0
-#define SOC_GOLDEN_TSC_SHADOW_LOWER__SocGoldenTscShadowLower_MASK 0xFFFFFFFFL
-//SOC_GAP_PWROK
-#define SOC_GAP_PWROK__soc_gap_pwrok__SHIFT 0x0
-#define SOC_GAP_PWROK__soc_gap_pwrok_MASK 0x00000001L
-
-// addressBlock: smuio_smuio_swtimer_SmuSmuioDec
-//PWR_VIRT_RESET_REQ
-#define PWR_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0
-#define PWR_VIRT_RESET_REQ__PF_FLR__SHIFT 0x1f
-#define PWR_VIRT_RESET_REQ__VF_FLR_MASK 0x7FFFFFFFL
-#define PWR_VIRT_RESET_REQ__PF_FLR_MASK 0x80000000L
-//PWR_DISP_TIMER_CONTROL
-#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
-#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
-#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a
-#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
-#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c
-#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d
-#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e
-#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01FFFFFFL
-#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L
-#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x04000000L
-#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK_MASK 0x08000000L
-#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000L
-#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000L
-#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L
-//PWR_DISP_TIMER2_CONTROL
-#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
-#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
-#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a
-#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
-#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c
-#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d
-#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e
-#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01FFFFFFL
-#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L
-#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x04000000L
-#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK_MASK 0x08000000L
-#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000L
-#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000L
-#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L
-//PWR_DISP_TIMER_GLOBAL_CONTROL
-#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH__SHIFT 0x0
-#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN__SHIFT 0xa
-#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH_MASK 0x000003FFL
-#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN_MASK 0x00000400L
-//PWR_IH_CONTROL
-#define PWR_IH_CONTROL__MAX_CREDIT__SHIFT 0x0
-#define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK__SHIFT 0x5
-#define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK__SHIFT 0x6
-#define PWR_IH_CONTROL__PWR_IH_CLK_GATE_EN__SHIFT 0x1f
-#define PWR_IH_CONTROL__MAX_CREDIT_MASK 0x0000001FL
-#define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK_MASK 0x00000020L
-#define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK_MASK 0x00000040L
-#define PWR_IH_CONTROL__PWR_IH_CLK_GATE_EN_MASK 0x80000000L
-
-// addressBlock: smuio_smuio_svi0_SmuSmuioDec
-//SMUSVI0_TEL_PLANE0
-#define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_IDDCOR__SHIFT 0x0
-#define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT 0x10
-#define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_IDDCOR_MASK 0x000000FFL
-#define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK 0x01FF0000L
-//SMUSVI0_PLANE0_CURRENTVID
-#define SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID__SHIFT 0x18
-#define SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID_MASK 0xFF000000L
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_default.h
deleted file mode 100644
index 128a18f1e..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_default.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _umc_6_0_DEFAULT_HEADER
-#define _umc_6_0_DEFAULT_HEADER
-
-#define mmUMCCH0_0_EccCtrl_DEFAULT 0x00000000
-
-#define mmUMCCH0_0_UMC_CONFIG_DEFAULT 0x00000203
-
-#define mmUMCCH0_0_UmcLocalCap_DEFAULT 0x00000000
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_offset.h
deleted file mode 100644
index 6985dbba3..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_offset.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _umc_6_0_OFFSET_H_
-#define _umc_6_0_OFFSET_H_
-
-#define mmUMCCH0_0_EccCtrl 0x0053
-#define mmUMCCH0_0_EccCtrl_BASE_IDX 0
-#define mmUMCCH1_0_EccCtrl 0x0853
-#define mmUMCCH1_0_EccCtrl_BASE_IDX 0
-#define mmUMCCH2_0_EccCtrl 0x1053
-#define mmUMCCH2_0_EccCtrl_BASE_IDX 0
-#define mmUMCCH3_0_EccCtrl 0x1853
-#define mmUMCCH3_0_EccCtrl_BASE_IDX 0
-
-#define mmUMCCH0_0_UMC_CONFIG 0x0040
-#define mmUMCCH0_0_UMC_CONFIG_BASE_IDX 0
-#define mmUMCCH1_0_UMC_CONFIG 0x0840
-#define mmUMCCH1_0_UMC_CONFIG_BASE_IDX 0
-#define mmUMCCH2_0_UMC_CONFIG 0x1040
-#define mmUMCCH2_0_UMC_CONFIG_BASE_IDX 0
-#define mmUMCCH3_0_UMC_CONFIG 0x1840
-#define mmUMCCH3_0_UMC_CONFIG_BASE_IDX 0
-
-#define mmUMCCH0_0_UmcLocalCap 0x0306
-#define mmUMCCH0_0_UmcLocalCap_BASE_IDX 0
-#define mmUMCCH1_0_UmcLocalCap 0x0b06
-#define mmUMCCH1_0_UmcLocalCap_BASE_IDX 0
-#define mmUMCCH2_0_UmcLocalCap 0x1306
-#define mmUMCCH2_0_UmcLocalCap_BASE_IDX 0
-#define mmUMCCH3_0_UmcLocalCap 0x1b06
-#define mmUMCCH3_0_UmcLocalCap_BASE_IDX 0
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_2_sh_mask.h
deleted file mode 100644
index a5a8c993e..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_2_sh_mask.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * Copyright (C) 2020 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _umc_6_1_2_SH_MASK_HEADER
-#define _umc_6_1_2_SH_MASK_HEADER
-
-//UMCCH0_0_EccErrCntSel_ARCT
-#define UMCCH0_0_EccErrCntSel_ARCT__EccErrCntCsSel__SHIFT 0x0
-#define UMCCH0_0_EccErrCntSel_ARCT__EccErrInt__SHIFT 0xc
-#define UMCCH0_0_EccErrCntSel_ARCT__EccErrCntEn__SHIFT 0xf
-#define UMCCH0_0_EccErrCntSel_ARCT__EccErrCntCsSel_MASK 0x0000000FL
-#define UMCCH0_0_EccErrCntSel_ARCT__EccErrInt_MASK 0x00003000L
-#define UMCCH0_0_EccErrCntSel_ARCT__EccErrCntEn_MASK 0x00008000L
-//UMCCH0_0_EccErrCnt_ARCT
-#define UMCCH0_0_EccErrCnt_ARCT__EccErrCnt__SHIFT 0x0
-#define UMCCH0_0_EccErrCnt_ARCT__EccErrCnt_MASK 0x0000FFFFL
-//MCA_UMC_UMC0_MCUMC_STATUST0_ARCT
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__ErrorCode__SHIFT 0x0
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__ErrorCodeExt__SHIFT 0x10
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__RESERV0__SHIFT 0x16
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__ErrCoreId__SHIFT 0x20
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__RESERV1__SHIFT 0x26
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__Scrub__SHIFT 0x28
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__RESERV2__SHIFT 0x29
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__Poison__SHIFT 0x2b
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__Deferred__SHIFT 0x2c
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__UECC__SHIFT 0x2d
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__CECC__SHIFT 0x2e
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__RESERV3__SHIFT 0x2f
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__Transparent__SHIFT 0x34
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__SyndV__SHIFT 0x35
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__RESERV4__SHIFT 0x36
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__TCC__SHIFT 0x37
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__ErrCoreIdVal__SHIFT 0x38
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__PCC__SHIFT 0x39
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__AddrV__SHIFT 0x3a
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__MiscV__SHIFT 0x3b
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__En__SHIFT 0x3c
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__UC__SHIFT 0x3d
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__Overflow__SHIFT 0x3e
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__Val__SHIFT 0x3f
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__ErrorCode_MASK 0x000000000000FFFFL
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__ErrorCodeExt_MASK 0x00000000003F0000L
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__RESERV0_MASK 0x00000000FFC00000L
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__ErrCoreId_MASK 0x0000003F00000000L
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__RESERV1_MASK 0x000000C000000000L
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__Scrub_MASK 0x0000010000000000L
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__RESERV2_MASK 0x0000060000000000L
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__Poison_MASK 0x0000080000000000L
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__Deferred_MASK 0x0000100000000000L
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__UECC_MASK 0x0000200000000000L
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__CECC_MASK 0x0000400000000000L
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__RESERV3_MASK 0x000F800000000000L
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__Transparent_MASK 0x0010000000000000L
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__SyndV_MASK 0x0020000000000000L
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__RESERV4_MASK 0x0040000000000000L
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__TCC_MASK 0x0080000000000000L
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__ErrCoreIdVal_MASK 0x0100000000000000L
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__PCC_MASK 0x0200000000000000L
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__AddrV_MASK 0x0400000000000000L
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__MiscV_MASK 0x0800000000000000L
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__En_MASK 0x1000000000000000L
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__UC_MASK 0x2000000000000000L
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__Overflow_MASK 0x4000000000000000L
-#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__Val_MASK 0x8000000000000000L
-//MCA_UMC_UMC0_MCUMC_ADDRT0_ARCT
-#define MCA_UMC_UMC0_MCUMC_ADDRT0_ARCT__ErrorAddr__SHIFT 0x0
-#define MCA_UMC_UMC0_MCUMC_ADDRT0_ARCT__LSB__SHIFT 0x38
-#define MCA_UMC_UMC0_MCUMC_ADDRT0_ARCT__Reserved__SHIFT 0x3e
-#define MCA_UMC_UMC0_MCUMC_ADDRT0_ARCT__ErrorAddr_MASK 0x00FFFFFFFFFFFFFFL
-#define MCA_UMC_UMC0_MCUMC_ADDRT0_ARCT__LSB_MASK 0x3F00000000000000L
-#define MCA_UMC_UMC0_MCUMC_ADDRT0_ARCT__Reserved_MASK 0xC000000000000000L
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h
deleted file mode 100644
index 2ef1273e6..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h
+++ /dev/null
@@ -1,793 +0,0 @@
-/*
- *
- * Copyright (C) 2016 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef UVD_4_0_SH_MASK_H
-#define UVD_4_0_SH_MASK_H
-
-#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L
-#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x00000000
-#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L
-#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x00000001
-#define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x0000001cL
-#define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x00000002
-#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003cL
-#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x00000002
-#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007c0L
-#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x00000006
-#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L
-#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x00000000
-#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L
-#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x00000017
-#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L
-#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x0000001a
-#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L
-#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x00000015
-#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L
-#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x00000016
-#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L
-#define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x0000001b
-#define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L
-#define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x00000019
-#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L
-#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x00000012
-#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L
-#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x00000018
-#define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L
-#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x00000014
-#define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L
-#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x00000013
-#define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000L
-#define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x0000001e
-#define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L
-#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x00000010
-#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L
-#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0x0000000c
-#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L
-#define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0x0000000e
-#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L
-#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0x0000000d
-#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L
-#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x00000011
-#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L
-#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0x0000000f
-#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L
-#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0x0000000b
-#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L
-#define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x0000001d
-#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L
-#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x0000001c
-#define UVD_CGC_GATE__IDCT_MASK 0x00000080L
-#define UVD_CGC_GATE__IDCT__SHIFT 0x00000007
-#define UVD_CGC_GATE__LBSI_MASK 0x00000400L
-#define UVD_CGC_GATE__LBSI__SHIFT 0x0000000a
-#define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L
-#define UVD_CGC_GATE__LMI_MC__SHIFT 0x00000005
-#define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L
-#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x00000006
-#define UVD_CGC_GATE__LRBBM_MASK 0x00000800L
-#define UVD_CGC_GATE__LRBBM__SHIFT 0x0000000b
-#define UVD_CGC_GATE__MPC_MASK 0x00000200L
-#define UVD_CGC_GATE__MPC__SHIFT 0x00000009
-#define UVD_CGC_GATE__MPEG2_MASK 0x00000004L
-#define UVD_CGC_GATE__MPEG2__SHIFT 0x00000002
-#define UVD_CGC_GATE__MPRD_MASK 0x00000100L
-#define UVD_CGC_GATE__MPRD__SHIFT 0x00000008
-#define UVD_CGC_GATE__RBC_MASK 0x00000010L
-#define UVD_CGC_GATE__RBC__SHIFT 0x00000004
-#define UVD_CGC_GATE__REGS_MASK 0x00000008L
-#define UVD_CGC_GATE__REGS__SHIFT 0x00000003
-#define UVD_CGC_GATE__SCPU_MASK 0x00080000L
-#define UVD_CGC_GATE__SCPU__SHIFT 0x00000013
-#define UVD_CGC_GATE__SYS_MASK 0x00000001L
-#define UVD_CGC_GATE__SYS__SHIFT 0x00000000
-#define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L
-#define UVD_CGC_GATE__UDEC_CM__SHIFT 0x0000000d
-#define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L
-#define UVD_CGC_GATE__UDEC_DB__SHIFT 0x0000000f
-#define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L
-#define UVD_CGC_GATE__UDEC_IT__SHIFT 0x0000000e
-#define UVD_CGC_GATE__UDEC_MASK 0x00000002L
-#define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L
-#define UVD_CGC_GATE__UDEC_MP__SHIFT 0x00000010
-#define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L
-#define UVD_CGC_GATE__UDEC_RE__SHIFT 0x0000000c
-#define UVD_CGC_GATE__UDEC__SHIFT 0x00000001
-#define UVD_CGC_GATE__VCPU_MASK 0x00040000L
-#define UVD_CGC_GATE__VCPU__SHIFT 0x00000012
-#define UVD_CGC_GATE__WCB_MASK 0x00020000L
-#define UVD_CGC_GATE__WCB__SHIFT 0x00000011
-#define UVD_CGC_MEM_CTRL__LCM_LS_EN_MASK 0x00002000L
-#define UVD_CGC_MEM_CTRL__LCM_LS_EN__SHIFT 0x0000000d
-#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN_MASK 0x00000001L
-#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN__SHIFT 0x00000000
-#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0x00f00000L
-#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x00000014
-#define UVD_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0x000f0000L
-#define UVD_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x00000010
-#define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x00001000L
-#define UVD_CGC_MEM_CTRL__MIF_LS_EN__SHIFT 0x0000000c
-#define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x00000002L
-#define UVD_CGC_MEM_CTRL__MPC_LS_EN__SHIFT 0x00000001
-#define UVD_CGC_MEM_CTRL__MPRD_LS_EN_MASK 0x00000004L
-#define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x00000002
-#define UVD_CGC_MEM_CTRL__SCPU_LS_EN_MASK 0x00000800L
-#define UVD_CGC_MEM_CTRL__SCPU_LS_EN__SHIFT 0x0000000b
-#define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x00000200L
-#define UVD_CGC_MEM_CTRL__SYS_LS_EN__SHIFT 0x00000009
-#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x00000020L
-#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x00000005
-#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x00000080L
-#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN__SHIFT 0x00000007
-#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN_MASK 0x00000040L
-#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN__SHIFT 0x00000006
-#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x00000100L
-#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN__SHIFT 0x00000008
-#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN_MASK 0x00000010L
-#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN__SHIFT 0x00000004
-#define UVD_CGC_MEM_CTRL__VCPU_LS_EN_MASK 0x00000400L
-#define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0x0000000a
-#define UVD_CGC_MEM_CTRL__WCB_LS_EN_MASK 0x00000008L
-#define UVD_CGC_MEM_CTRL__WCB_LS_EN__SHIFT 0x00000003
-#define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x00004000L
-#define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0x0000000e
-#define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x00008000L
-#define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0x0000000f
-#define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x00200000L
-#define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x00000015
-#define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x00400000L
-#define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x00000016
-#define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x00001000L
-#define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0x0000000c
-#define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x00002000L
-#define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0x0000000d
-#define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x00800000L
-#define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x00000017
-#define UVD_CGC_STATUS__MPC_DCLK_MASK 0x00100000L
-#define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x00000014
-#define UVD_CGC_STATUS__MPC_SCLK_MASK 0x00080000L
-#define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x00000013
-#define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x00000080L
-#define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x00000007
-#define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x00000040L
-#define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x00000006
-#define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x00000100L
-#define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x00000008
-#define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x00020000L
-#define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x00000011
-#define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x00010000L
-#define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x00000010
-#define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x00040000L
-#define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x00000012
-#define UVD_CGC_STATUS__RBC_SCLK_MASK 0x00000800L
-#define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0x0000000b
-#define UVD_CGC_STATUS__REGS_SCLK_MASK 0x00000200L
-#define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x00000009
-#define UVD_CGC_STATUS__REGS_VCLK_MASK 0x00000400L
-#define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0x0000000a
-#define UVD_CGC_STATUS__SCPU_SCLK_MASK 0x08000000L
-#define UVD_CGC_STATUS__SCPU_SCLK__SHIFT 0x0000001b
-#define UVD_CGC_STATUS__SCPU_VCLK_MASK 0x10000000L
-#define UVD_CGC_STATUS__SCPU_VCLK__SHIFT 0x0000001c
-#define UVD_CGC_STATUS__SYS_DCLK_MASK 0x00000002L
-#define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x00000001
-#define UVD_CGC_STATUS__SYS_SCLK_MASK 0x00000001L
-#define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x00000000
-#define UVD_CGC_STATUS__SYS_VCLK_MASK 0x00000004L
-#define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x00000002
-#define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x00000010L
-#define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x00000004
-#define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x00000008L
-#define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x00000003
-#define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x00000020L
-#define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x00000005
-#define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x02000000L
-#define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x00000019
-#define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x04000000L
-#define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x0000001a
-#define UVD_CGC_STATUS__WCB_SCLK_MASK 0x01000000L
-#define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x00000018
-#define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x00000010L
-#define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x00000004
-#define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x00000008L
-#define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x00000003
-#define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x00000020L
-#define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x00000005
-#define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x00000400L
-#define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0x0000000a
-#define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x00000200L
-#define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x00000009
-#define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x00000800L
-#define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0x0000000b
-#define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x00000080L
-#define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x00000007
-#define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x00000040L
-#define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x00000006
-#define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x00000100L
-#define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x00000008
-#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x00002000L
-#define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0x0000000d
-#define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x00001000L
-#define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0x0000000c
-#define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x00004000L
-#define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0x0000000e
-#define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x00000002L
-#define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x00000001
-#define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x00000001L
-#define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x00000000
-#define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x00000004L
-#define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x00000002
-#define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xffffffffL
-#define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x00000000
-#define UVD_CTX_DATA__DATA_MASK 0xffffffffL
-#define UVD_CTX_DATA__DATA__SHIFT 0x00000000
-#define UVD_CTX_INDEX__INDEX_MASK 0x000001ffL
-#define UVD_CTX_INDEX__INDEX__SHIFT 0x00000000
-#define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x00000001L
-#define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x00000002L
-#define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x00000001
-#define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x00000000
-#define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7ffffffeL
-#define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x00000001L
-#define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x00000000
-#define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x00000001
-#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000L
-#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x0000001f
-#define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xffffffffL
-#define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x00000000
-#define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xffffffffL
-#define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x00000000
-#define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT_MASK 0x0000000fL
-#define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT__SHIFT 0x00000000
-#define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT_MASK 0x00000f00L
-#define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT__SHIFT 0x00000008
-#define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT_MASK 0x0000f000L
-#define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT__SHIFT 0x0000000c
-#define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT_MASK 0x000000f0L
-#define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT__SHIFT 0x00000004
-#define UVD_LMI_ADDR_EXT__CM_ADDR_EXT_MASK 0x000000f0L
-#define UVD_LMI_ADDR_EXT__CM_ADDR_EXT__SHIFT 0x00000004
-#define UVD_LMI_ADDR_EXT__IT_ADDR_EXT_MASK 0x00000f00L
-#define UVD_LMI_ADDR_EXT__IT_ADDR_EXT__SHIFT 0x00000008
-#define UVD_LMI_ADDR_EXT__MP_ADDR_EXT_MASK 0x00f00000L
-#define UVD_LMI_ADDR_EXT__MP_ADDR_EXT__SHIFT 0x00000014
-#define UVD_LMI_ADDR_EXT__RE_ADDR_EXT_MASK 0x000f0000L
-#define UVD_LMI_ADDR_EXT__RE_ADDR_EXT__SHIFT 0x00000010
-#define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT_MASK 0x0000000fL
-#define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT__SHIFT 0x00000000
-#define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT_MASK 0x0f000000L
-#define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT__SHIFT 0x00000018
-#define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT_MASK 0xf0000000L
-#define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT__SHIFT 0x0000001c
-#define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT_MASK 0x0000f000L
-#define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT__SHIFT 0x0000000c
-#define UVD_LMI_CACHE_CTRL__CM_EN_MASK 0x00000004L
-#define UVD_LMI_CACHE_CTRL__CM_EN__SHIFT 0x00000002
-#define UVD_LMI_CACHE_CTRL__CM_FLUSH_MASK 0x00000008L
-#define UVD_LMI_CACHE_CTRL__CM_FLUSH__SHIFT 0x00000003
-#define UVD_LMI_CACHE_CTRL__IT_EN_MASK 0x00000001L
-#define UVD_LMI_CACHE_CTRL__IT_EN__SHIFT 0x00000000
-#define UVD_LMI_CACHE_CTRL__IT_FLUSH_MASK 0x00000002L
-#define UVD_LMI_CACHE_CTRL__IT_FLUSH__SHIFT 0x00000001
-#define UVD_LMI_CACHE_CTRL__VCPU_EN_MASK 0x00000010L
-#define UVD_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x00000004
-#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH_MASK 0x00000020L
-#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT 0x00000005
-#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L
-#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x00000002
-#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x00000080L
-#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x00000007
-#define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x00000008L
-#define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x00000003
-#define UVD_LMI_CTRL2__MCIF_WR_WATERMARK_MASK 0x00000070L
-#define UVD_LMI_CTRL2__MCIF_WR_WATERMARK__SHIFT 0x00000004
-#define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L
-#define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x00000009
-#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L
-#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0x0000000b
-#define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L
-#define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x00000000
-#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x00008000L
-#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0x0000000f
-#define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L
-#define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x00000001
-#define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L
-#define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x00000008
-#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x00002000L
-#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0x0000000d
-#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x00004000L
-#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0x0000000e
-#define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000800L
-#define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0x0000000b
-#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x00400000L
-#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x00000016
-#define UVD_LMI_CTRL__CRC_RESET_MASK 0x00004000L
-#define UVD_LMI_CTRL__CRC_RESET__SHIFT 0x0000000e
-#define UVD_LMI_CTRL__CRC_SEL_MASK 0x000f8000L
-#define UVD_LMI_CTRL__CRC_SEL__SHIFT 0x0000000f
-#define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x00002000L
-#define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0x0000000d
-#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x00800000L
-#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x00000017
-#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L
-#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x00000018
-#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x00100000L
-#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x00000014
-#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L
-#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x00000019
-#define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x00001000L
-#define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0x0000000c
-#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x04000000L
-#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x0000001a
-#define UVD_LMI_CTRL__REQ_MODE_MASK 0x00000200L
-#define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x00000009
-#define UVD_LMI_CTRL__RFU_MASK 0xf8000000L
-#define UVD_LMI_CTRL__RFU__SHIFT 0x0000001b
-#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L
-#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x00000015
-#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L
-#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x00000008
-#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0x000000ffL
-#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x00000000
-#define UVD_LMI_EXT40_ADDR__ADDR_MASK 0x000000ffL
-#define UVD_LMI_EXT40_ADDR__ADDR__SHIFT 0x00000000
-#define UVD_LMI_EXT40_ADDR__INDEX_MASK 0x001f0000L
-#define UVD_LMI_EXT40_ADDR__INDEX__SHIFT 0x00000010
-#define UVD_LMI_EXT40_ADDR__WRITE_ADDR_MASK 0x80000000L
-#define UVD_LMI_EXT40_ADDR__WRITE_ADDR__SHIFT 0x0000001f
-#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x00001000L
-#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0x0000000c
-#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x00002000L
-#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0x0000000d
-#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x00000080L
-#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x00000007
-#define UVD_LMI_STATUS__READ_CLEAN_MASK 0x00000001L
-#define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x00000100L
-#define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x00000008
-#define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x00000000
-#define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x00000800L
-#define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0x0000000b
-#define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x00000010L
-#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x00000200L
-#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x00000009
-#define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x00000004
-#define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x00000400L
-#define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0x0000000a
-#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x00000020L
-#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x00000040L
-#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x00000006
-#define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x00000005
-#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x00000008L
-#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x00000003
-#define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x00000002L
-#define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x00000004L
-#define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x00000002
-#define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x00000001
-#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP_MASK 0x00000003L
-#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP__SHIFT 0x00000000
-#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP_MASK 0x0000000cL
-#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP__SHIFT 0x00000002
-#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK 0x00000c00L
-#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0x0000000a
-#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK 0x000c0000L
-#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x00000012
-#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK 0x0000c000L
-#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0x0000000e
-#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x00030000L
-#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK 0x03000000L
-#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x00000010
-#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x00000018
-#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000cL
-#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x00000002
-#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK 0x00003000L
-#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT 0x0000000c
-#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xc0000000L
-#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x0000001e
-#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK 0x00c00000L
-#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT 0x00000016
-#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L
-#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x00000000
-#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x00000030L
-#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x00000004
-#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0x0c000000L
-#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x0000001a
-#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000L
-#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x0000001c
-#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0x000000c0L
-#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x00000006
-#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x00000300L
-#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x00000008
-#define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x007ffff0L
-#define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x00000004
-#define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L
-#define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x00000000
-#define UVD_MASTINT_EN__SYS_EN_MASK 0x00000004L
-#define UVD_MASTINT_EN__SYS_EN__SHIFT 0x00000002
-#define UVD_MASTINT_EN__VCPU_EN_MASK 0x00000002L
-#define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x00000001
-#define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
-#define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008
-#define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
-#define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018
-#define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L
-#define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014
-#define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
-#define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e
-#define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
-#define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000
-#define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L
-#define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c
-#define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L
-#define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004
-#define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
-#define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c
-#define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
-#define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010
-#define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
-#define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008
-#define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
-#define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018
-#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L
-#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014
-#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
-#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e
-#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
-#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000
-#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L
-#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c
-#define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L
-#define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004
-#define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
-#define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c
-#define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
-#define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010
-#define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
-#define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008
-#define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
-#define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018
-#define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L
-#define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014
-#define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
-#define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e
-#define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
-#define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000
-#define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L
-#define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c
-#define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L
-#define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004
-#define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
-#define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c
-#define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
-#define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010
-#define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x00030000L
-#define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x00000010
-#define UVD_MPC_CNTL__DBG_MUX_MASK 0x00000700L
-#define UVD_MPC_CNTL__DBG_MUX__SHIFT 0x00000008
-#define UVD_MPC_CNTL__PERF_RST_MASK 0x00000040L
-#define UVD_MPC_CNTL__PERF_RST__SHIFT 0x00000006
-#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L
-#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x00000003
-#define UVD_MPC_CNTL__URGENT_EN_MASK 0x00040000L
-#define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x00000012
-#define UVD_MPC_SET_ALU__FUNCT_MASK 0x00000007L
-#define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x00000000
-#define UVD_MPC_SET_ALU__OPERAND_MASK 0x00000ff0L
-#define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x00000004
-#define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x0000003fL
-#define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x00000000
-#define UVD_MPC_SET_MUXA0__VARA_1_MASK 0x00000fc0L
-#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x00000006
-#define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x0003f000L
-#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0x0000000c
-#define UVD_MPC_SET_MUXA0__VARA_3_MASK 0x00fc0000L
-#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x00000012
-#define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3f000000L
-#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x00000018
-#define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x0000003fL
-#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x00000000
-#define UVD_MPC_SET_MUXA1__VARA_6_MASK 0x00000fc0L
-#define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x00000006
-#define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x0003f000L
-#define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0x0000000c
-#define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x0000003fL
-#define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x00000000
-#define UVD_MPC_SET_MUXB0__VARB_1_MASK 0x00000fc0L
-#define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x00000006
-#define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x0003f000L
-#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0x0000000c
-#define UVD_MPC_SET_MUXB0__VARB_3_MASK 0x00fc0000L
-#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x00000012
-#define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3f000000L
-#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x00000018
-#define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x0000003fL
-#define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x00000000
-#define UVD_MPC_SET_MUXB1__VARB_6_MASK 0x00000fc0L
-#define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x00000006
-#define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x0003f000L
-#define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0x0000000c
-#define UVD_MPC_SET_MUX__SET_0_MASK 0x00000007L
-#define UVD_MPC_SET_MUX__SET_0__SHIFT 0x00000000
-#define UVD_MPC_SET_MUX__SET_1_MASK 0x00000038L
-#define UVD_MPC_SET_MUX__SET_1__SHIFT 0x00000003
-#define UVD_MPC_SET_MUX__SET_2_MASK 0x000001c0L
-#define UVD_MPC_SET_MUX__SET_2__SHIFT 0x00000006
-#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x00000003L
-#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x00000000
-#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x00300000L
-#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x00000014
-#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0x00c00000L
-#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x00000016
-#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x03000000L
-#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x00000018
-#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0x0c000000L
-#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x0000001a
-#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000L
-#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x0000001c
-#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xc0000000L
-#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x0000001e
-#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0x0000000cL
-#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x00000002
-#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x00000030L
-#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x00000004
-#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0x000000c0L
-#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x00000006
-#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x00000300L
-#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x00000008
-#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0x00000c00L
-#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0x0000000a
-#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x00003000L
-#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0x0000000c
-#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0x0000c000L
-#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0x0000000e
-#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x00030000L
-#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x00000010
-#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0x000c0000L
-#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x00000012
-#define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK 0x000000ffL
-#define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR__SHIFT 0x00000000
-#define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK 0x00000400L
-#define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT__SHIFT 0x0000000a
-#define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT_MASK 0x00000800L
-#define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT__SHIFT 0x0000000b
-#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK 0x00000100L
-#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN__SHIFT 0x00000008
-#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK 0x00000200L
-#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP__SHIFT 0x00000009
-#define UVD_PGFSM_CONFIG__UVD_PGFSM_READ_MASK 0x00002000L
-#define UVD_PGFSM_CONFIG__UVD_PGFSM_READ__SHIFT 0x0000000d
-#define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR_MASK 0xf0000000L
-#define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR__SHIFT 0x0000001c
-#define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE_MASK 0x00001000L
-#define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE__SHIFT 0x0000000c
-#define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE_MASK 0x00ffffffL
-#define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE__SHIFT 0x00000000
-#define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE_MASK 0x00ffffffL
-#define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE__SHIFT 0x00000000
-#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000001L
-#define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x00000000
-#define UVD_RBC_IB_BASE__IB_BASE_MASK 0xffffffc0L
-#define UVD_RBC_IB_BASE__IB_BASE__SHIFT 0x00000006
-#define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x007ffff0L
-#define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x00000004
-#define UVD_RBC_RB_BASE__RB_BASE_MASK 0xffffffc0L
-#define UVD_RBC_RB_BASE__RB_BASE__SHIFT 0x00000006
-#define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x00001f00L
-#define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x00000008
-#define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x0000001fL
-#define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x00000000
-#define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x00010000L
-#define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x00000010
-#define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x01000000L
-#define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x00000018
-#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000L
-#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x0000001c
-#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x00100000L
-#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x00000014
-#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xffffffffL
-#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000000
-#define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x007ffff0L
-#define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x00000004
-#define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x007ffff0L
-#define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x00000004
-#define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0x000fffffL
-#define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x00000000
-#define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0x000fffffL
-#define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x00000000
-#define UVD_SEMA_CMD__MODE_MASK 0x00000040L
-#define UVD_SEMA_CMD__MODE__SHIFT 0x00000006
-#define UVD_SEMA_CMD__REQ_CMD_MASK 0x0000000fL
-#define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x00000000
-#define UVD_SEMA_CMD__VMID_EN_MASK 0x00000080L
-#define UVD_SEMA_CMD__VMID_EN__SHIFT 0x00000007
-#define UVD_SEMA_CMD__VMID_MASK 0x00000f00L
-#define UVD_SEMA_CMD__VMID__SHIFT 0x00000008
-#define UVD_SEMA_CMD__WR_PHASE_MASK 0x00000030L
-#define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x00000004
-#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x00000002L
-#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x00000001
-#define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x00000001L
-#define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x00000000
-#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L
-#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x00000018
-#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x001ffffeL
-#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x00000001
-#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x00000001L
-#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x00000000
-#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000004L
-#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x00000002
-#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x00000008L
-#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x00000003
-#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x00000002L
-#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x00000001
-#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000001L
-#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x00000000
-#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L
-#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x00000018
-#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x001ffffeL
-#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x00000001
-#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x00000001L
-#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x00000000
-#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L
-#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x00000018
-#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x001ffffeL
-#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x00000001
-#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x00000001L
-#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x00000000
-#define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK 0x00000020L
-#define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT 0x00000005
-#define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x00000040L
-#define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x00000006
-#define UVD_SOFT_RESET__FWV_SOFT_RESET_MASK 0x00000200L
-#define UVD_SOFT_RESET__FWV_SOFT_RESET__SHIFT 0x00000009
-#define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x00001000L
-#define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0x0000000c
-#define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x00000400L
-#define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0x0000000a
-#define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x00000002L
-#define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x00000001
-#define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x00010000L
-#define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x00000010
-#define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x00000004L
-#define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x00000002
-#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x00002000L
-#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0x0000000d
-#define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x00008000L
-#define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0x0000000f
-#define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x00000100L
-#define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x00000008
-#define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x00000800L
-#define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0x0000000b
-#define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x00000001L
-#define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x00000000
-#define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x00004000L
-#define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0x0000000e
-#define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000080L
-#define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x00000007
-#define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x00000010L
-#define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x00000004
-#define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x00000008L
-#define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x00000003
-#define UVD_STATUS__RBC_BUSY_MASK 0x00000001L
-#define UVD_STATUS__RBC_BUSY__SHIFT 0x00000000
-#define UVD_STATUS__VCPU_REPORT_MASK 0x000000feL
-#define UVD_STATUS__VCPU_REPORT__SHIFT 0x00000001
-#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
-#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008
-#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
-#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018
-#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L
-#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014
-#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
-#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e
-#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
-#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000
-#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L
-#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c
-#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L
-#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004
-#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
-#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c
-#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
-#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010
-#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
-#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008
-#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
-#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018
-#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L
-#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014
-#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
-#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e
-#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
-#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000
-#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L
-#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c
-#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L
-#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004
-#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
-#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c
-#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
-#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010
-#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
-#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008
-#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
-#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018
-#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L
-#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014
-#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
-#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e
-#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
-#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000
-#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L
-#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c
-#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L
-#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004
-#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
-#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c
-#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
-#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010
-#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x01ffffffL
-#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x00000000
-#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x01ffffffL
-#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x00000000
-#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x01ffffffL
-#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x00000000
-#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x001fffffL
-#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x00000000
-#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x001fffffL
-#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x00000000
-#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x001fffffL
-#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x00000000
-#define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x00000100L
-#define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x00000008
-#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4_MASK 0x00000010L
-#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4__SHIFT 0x00000004
-#define UVD_VCPU_CNTL__CABAC_MB_ACC_MASK 0x10000000L
-#define UVD_VCPU_CNTL__CABAC_MB_ACC__SHIFT 0x0000001c
-#define UVD_VCPU_CNTL__CLK_ACTIVE_MASK 0x00020000L
-#define UVD_VCPU_CNTL__CLK_ACTIVE__SHIFT 0x00000011
-#define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L
-#define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x00000009
-#define UVD_VCPU_CNTL__DBG_MUX_MASK 0x0000e000L
-#define UVD_VCPU_CNTL__DBG_MUX__SHIFT 0x0000000d
-#define UVD_VCPU_CNTL__ECPU_AM32_EN_MASK 0x20000000L
-#define UVD_VCPU_CNTL__ECPU_AM32_EN__SHIFT 0x0000001d
-#define UVD_VCPU_CNTL__IRQ_ERR_MASK 0x0000000fL
-#define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x00000000
-#define UVD_VCPU_CNTL__JTAG_EN_MASK 0x00010000L
-#define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x00000010
-#define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x00000020L
-#define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x00000005
-#define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x00000040L
-#define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x00000006
-#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0x0ff00000L
-#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x00000014
-#define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00000080L
-#define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x00000007
-#define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x00040000L
-#define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x00000012
-#define UVD_VCPU_CNTL__TRCE_EN_MASK 0x00000400L
-#define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0x0000000a
-#define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x00001800L
-#define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0x0000000b
-#define UVD_VCPU_CNTL__WMV9_EN_MASK 0x40000000L
-#define UVD_VCPU_CNTL__WMV9_EN__SHIFT 0x0000001e
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_enum.h
deleted file mode 100644
index 981086f8e..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_enum.h
+++ /dev/null
@@ -1,1211 +0,0 @@
-/*
- * UVD_5_0 Register documentation
- *
- * Copyright (C) 2014 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef UVD_5_0_ENUM_H
-#define UVD_5_0_ENUM_H
-
-typedef enum UVDFirmwareCommand {
- UVDFC_FENCE = 0x0,
- UVDFC_TRAP = 0x1,
- UVDFC_DECODED_ADDR = 0x2,
- UVDFC_MBLOCK_ADDR = 0x3,
- UVDFC_ITBUF_ADDR = 0x4,
- UVDFC_DISPLAY_ADDR = 0x5,
- UVDFC_EOD = 0x6,
- UVDFC_DISPLAY_PITCH = 0x7,
- UVDFC_DISPLAY_TILING = 0x8,
- UVDFC_BITSTREAM_ADDR = 0x9,
- UVDFC_BITSTREAM_SIZE = 0xa,
-} UVDFirmwareCommand;
-typedef enum SurfaceEndian {
- ENDIAN_NONE = 0x0,
- ENDIAN_8IN16 = 0x1,
- ENDIAN_8IN32 = 0x2,
- ENDIAN_8IN64 = 0x3,
-} SurfaceEndian;
-typedef enum ArrayMode {
- ARRAY_LINEAR_GENERAL = 0x0,
- ARRAY_LINEAR_ALIGNED = 0x1,
- ARRAY_1D_TILED_THIN1 = 0x2,
- ARRAY_1D_TILED_THICK = 0x3,
- ARRAY_2D_TILED_THIN1 = 0x4,
- ARRAY_PRT_TILED_THIN1 = 0x5,
- ARRAY_PRT_2D_TILED_THIN1 = 0x6,
- ARRAY_2D_TILED_THICK = 0x7,
- ARRAY_2D_TILED_XTHICK = 0x8,
- ARRAY_PRT_TILED_THICK = 0x9,
- ARRAY_PRT_2D_TILED_THICK = 0xa,
- ARRAY_PRT_3D_TILED_THIN1 = 0xb,
- ARRAY_3D_TILED_THIN1 = 0xc,
- ARRAY_3D_TILED_THICK = 0xd,
- ARRAY_3D_TILED_XTHICK = 0xe,
- ARRAY_PRT_3D_TILED_THICK = 0xf,
-} ArrayMode;
-typedef enum PipeTiling {
- CONFIG_1_PIPE = 0x0,
- CONFIG_2_PIPE = 0x1,
- CONFIG_4_PIPE = 0x2,
- CONFIG_8_PIPE = 0x3,
-} PipeTiling;
-typedef enum BankTiling {
- CONFIG_4_BANK = 0x0,
- CONFIG_8_BANK = 0x1,
-} BankTiling;
-typedef enum GroupInterleave {
- CONFIG_256B_GROUP = 0x0,
- CONFIG_512B_GROUP = 0x1,
-} GroupInterleave;
-typedef enum RowTiling {
- CONFIG_1KB_ROW = 0x0,
- CONFIG_2KB_ROW = 0x1,
- CONFIG_4KB_ROW = 0x2,
- CONFIG_8KB_ROW = 0x3,
- CONFIG_1KB_ROW_OPT = 0x4,
- CONFIG_2KB_ROW_OPT = 0x5,
- CONFIG_4KB_ROW_OPT = 0x6,
- CONFIG_8KB_ROW_OPT = 0x7,
-} RowTiling;
-typedef enum BankSwapBytes {
- CONFIG_128B_SWAPS = 0x0,
- CONFIG_256B_SWAPS = 0x1,
- CONFIG_512B_SWAPS = 0x2,
- CONFIG_1KB_SWAPS = 0x3,
-} BankSwapBytes;
-typedef enum SampleSplitBytes {
- CONFIG_1KB_SPLIT = 0x0,
- CONFIG_2KB_SPLIT = 0x1,
- CONFIG_4KB_SPLIT = 0x2,
- CONFIG_8KB_SPLIT = 0x3,
-} SampleSplitBytes;
-typedef enum NumPipes {
- ADDR_CONFIG_1_PIPE = 0x0,
- ADDR_CONFIG_2_PIPE = 0x1,
- ADDR_CONFIG_4_PIPE = 0x2,
- ADDR_CONFIG_8_PIPE = 0x3,
-} NumPipes;
-typedef enum PipeInterleaveSize {
- ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
- ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
-} PipeInterleaveSize;
-typedef enum BankInterleaveSize {
- ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
- ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
- ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
- ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
-} BankInterleaveSize;
-typedef enum NumShaderEngines {
- ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
- ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
-} NumShaderEngines;
-typedef enum ShaderEngineTileSize {
- ADDR_CONFIG_SE_TILE_16 = 0x0,
- ADDR_CONFIG_SE_TILE_32 = 0x1,
-} ShaderEngineTileSize;
-typedef enum NumGPUs {
- ADDR_CONFIG_1_GPU = 0x0,
- ADDR_CONFIG_2_GPU = 0x1,
- ADDR_CONFIG_4_GPU = 0x2,
-} NumGPUs;
-typedef enum MultiGPUTileSize {
- ADDR_CONFIG_GPU_TILE_16 = 0x0,
- ADDR_CONFIG_GPU_TILE_32 = 0x1,
- ADDR_CONFIG_GPU_TILE_64 = 0x2,
- ADDR_CONFIG_GPU_TILE_128 = 0x3,
-} MultiGPUTileSize;
-typedef enum RowSize {
- ADDR_CONFIG_1KB_ROW = 0x0,
- ADDR_CONFIG_2KB_ROW = 0x1,
- ADDR_CONFIG_4KB_ROW = 0x2,
-} RowSize;
-typedef enum NumLowerPipes {
- ADDR_CONFIG_1_LOWER_PIPES = 0x0,
- ADDR_CONFIG_2_LOWER_PIPES = 0x1,
-} NumLowerPipes;
-typedef enum DebugBlockId {
- DBG_CLIENT_BLKID_RESERVED = 0x0,
- DBG_CLIENT_BLKID_dbg = 0x1,
- DBG_CLIENT_BLKID_scf2 = 0x2,
- DBG_CLIENT_BLKID_mcd5 = 0x3,
- DBG_CLIENT_BLKID_vmc = 0x4,
- DBG_CLIENT_BLKID_sx30 = 0x5,
- DBG_CLIENT_BLKID_mcd2 = 0x6,
- DBG_CLIENT_BLKID_bci1 = 0x7,
- DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0x8,
- DBG_CLIENT_BLKID_mcc0 = 0x9,
- DBG_CLIENT_BLKID_uvdf_0 = 0xa,
- DBG_CLIENT_BLKID_uvdf_1 = 0xb,
- DBG_CLIENT_BLKID_uvdf_2 = 0xc,
- DBG_CLIENT_BLKID_uvdi_0 = 0xd,
- DBG_CLIENT_BLKID_bci0 = 0xe,
- DBG_CLIENT_BLKID_vcec0_0 = 0xf,
- DBG_CLIENT_BLKID_cb100 = 0x10,
- DBG_CLIENT_BLKID_cb001 = 0x11,
- DBG_CLIENT_BLKID_mcd4 = 0x12,
- DBG_CLIENT_BLKID_tmonw00 = 0x13,
- DBG_CLIENT_BLKID_cb101 = 0x14,
- DBG_CLIENT_BLKID_sx10 = 0x15,
- DBG_CLIENT_BLKID_cb301 = 0x16,
- DBG_CLIENT_BLKID_tmonw01 = 0x17,
- DBG_CLIENT_BLKID_vcea0_0 = 0x18,
- DBG_CLIENT_BLKID_vcea0_1 = 0x19,
- DBG_CLIENT_BLKID_vcea0_2 = 0x1a,
- DBG_CLIENT_BLKID_vcea0_3 = 0x1b,
- DBG_CLIENT_BLKID_scf1 = 0x1c,
- DBG_CLIENT_BLKID_sx20 = 0x1d,
- DBG_CLIENT_BLKID_spim1 = 0x1e,
- DBG_CLIENT_BLKID_pa10 = 0x1f,
- DBG_CLIENT_BLKID_pa00 = 0x20,
- DBG_CLIENT_BLKID_gmcon = 0x21,
- DBG_CLIENT_BLKID_mcb = 0x22,
- DBG_CLIENT_BLKID_vgt0 = 0x23,
- DBG_CLIENT_BLKID_pc0 = 0x24,
- DBG_CLIENT_BLKID_bci2 = 0x25,
- DBG_CLIENT_BLKID_uvdb_0 = 0x26,
- DBG_CLIENT_BLKID_spim3 = 0x27,
- DBG_CLIENT_BLKID_cpc_0 = 0x28,
- DBG_CLIENT_BLKID_cpc_1 = 0x29,
- DBG_CLIENT_BLKID_uvdm_0 = 0x2a,
- DBG_CLIENT_BLKID_uvdm_1 = 0x2b,
- DBG_CLIENT_BLKID_uvdm_2 = 0x2c,
- DBG_CLIENT_BLKID_uvdm_3 = 0x2d,
- DBG_CLIENT_BLKID_cb000 = 0x2e,
- DBG_CLIENT_BLKID_spim0 = 0x2f,
- DBG_CLIENT_BLKID_mcc2 = 0x30,
- DBG_CLIENT_BLKID_ds0 = 0x31,
- DBG_CLIENT_BLKID_srbm = 0x32,
- DBG_CLIENT_BLKID_ih = 0x33,
- DBG_CLIENT_BLKID_sem = 0x34,
- DBG_CLIENT_BLKID_sdma_0 = 0x35,
- DBG_CLIENT_BLKID_sdma_1 = 0x36,
- DBG_CLIENT_BLKID_hdp = 0x37,
- DBG_CLIENT_BLKID_acp_0 = 0x38,
- DBG_CLIENT_BLKID_acp_1 = 0x39,
- DBG_CLIENT_BLKID_cb200 = 0x3a,
- DBG_CLIENT_BLKID_scf3 = 0x3b,
- DBG_CLIENT_BLKID_vceb1_0 = 0x3c,
- DBG_CLIENT_BLKID_vcea1_0 = 0x3d,
- DBG_CLIENT_BLKID_vcea1_1 = 0x3e,
- DBG_CLIENT_BLKID_vcea1_2 = 0x3f,
- DBG_CLIENT_BLKID_vcea1_3 = 0x40,
- DBG_CLIENT_BLKID_bci3 = 0x41,
- DBG_CLIENT_BLKID_mcd0 = 0x42,
- DBG_CLIENT_BLKID_pa11 = 0x43,
- DBG_CLIENT_BLKID_pa01 = 0x44,
- DBG_CLIENT_BLKID_cb201 = 0x45,
- DBG_CLIENT_BLKID_spim2 = 0x46,
- DBG_CLIENT_BLKID_vgt2 = 0x47,
- DBG_CLIENT_BLKID_pc2 = 0x48,
- DBG_CLIENT_BLKID_smu_0 = 0x49,
- DBG_CLIENT_BLKID_smu_1 = 0x4a,
- DBG_CLIENT_BLKID_smu_2 = 0x4b,
- DBG_CLIENT_BLKID_cb1 = 0x4c,
- DBG_CLIENT_BLKID_ia0 = 0x4d,
- DBG_CLIENT_BLKID_wd = 0x4e,
- DBG_CLIENT_BLKID_ia1 = 0x4f,
- DBG_CLIENT_BLKID_vcec1_0 = 0x50,
- DBG_CLIENT_BLKID_scf0 = 0x51,
- DBG_CLIENT_BLKID_vgt1 = 0x52,
- DBG_CLIENT_BLKID_pc1 = 0x53,
- DBG_CLIENT_BLKID_cb0 = 0x54,
- DBG_CLIENT_BLKID_gdc_one_0 = 0x55,
- DBG_CLIENT_BLKID_gdc_one_1 = 0x56,
- DBG_CLIENT_BLKID_gdc_one_2 = 0x57,
- DBG_CLIENT_BLKID_gdc_one_3 = 0x58,
- DBG_CLIENT_BLKID_gdc_one_4 = 0x59,
- DBG_CLIENT_BLKID_gdc_one_5 = 0x5a,
- DBG_CLIENT_BLKID_gdc_one_6 = 0x5b,
- DBG_CLIENT_BLKID_gdc_one_7 = 0x5c,
- DBG_CLIENT_BLKID_gdc_one_8 = 0x5d,
- DBG_CLIENT_BLKID_gdc_one_9 = 0x5e,
- DBG_CLIENT_BLKID_gdc_one_10 = 0x5f,
- DBG_CLIENT_BLKID_gdc_one_11 = 0x60,
- DBG_CLIENT_BLKID_gdc_one_12 = 0x61,
- DBG_CLIENT_BLKID_gdc_one_13 = 0x62,
- DBG_CLIENT_BLKID_gdc_one_14 = 0x63,
- DBG_CLIENT_BLKID_gdc_one_15 = 0x64,
- DBG_CLIENT_BLKID_gdc_one_16 = 0x65,
- DBG_CLIENT_BLKID_gdc_one_17 = 0x66,
- DBG_CLIENT_BLKID_gdc_one_18 = 0x67,
- DBG_CLIENT_BLKID_gdc_one_19 = 0x68,
- DBG_CLIENT_BLKID_gdc_one_20 = 0x69,
- DBG_CLIENT_BLKID_gdc_one_21 = 0x6a,
- DBG_CLIENT_BLKID_gdc_one_22 = 0x6b,
- DBG_CLIENT_BLKID_gdc_one_23 = 0x6c,
- DBG_CLIENT_BLKID_gdc_one_24 = 0x6d,
- DBG_CLIENT_BLKID_gdc_one_25 = 0x6e,
- DBG_CLIENT_BLKID_gdc_one_26 = 0x6f,
- DBG_CLIENT_BLKID_gdc_one_27 = 0x70,
- DBG_CLIENT_BLKID_gdc_one_28 = 0x71,
- DBG_CLIENT_BLKID_gdc_one_29 = 0x72,
- DBG_CLIENT_BLKID_gdc_one_30 = 0x73,
- DBG_CLIENT_BLKID_gdc_one_31 = 0x74,
- DBG_CLIENT_BLKID_gdc_one_32 = 0x75,
- DBG_CLIENT_BLKID_gdc_one_33 = 0x76,
- DBG_CLIENT_BLKID_gdc_one_34 = 0x77,
- DBG_CLIENT_BLKID_gdc_one_35 = 0x78,
- DBG_CLIENT_BLKID_vceb0_0 = 0x79,
- DBG_CLIENT_BLKID_vgt3 = 0x7a,
- DBG_CLIENT_BLKID_pc3 = 0x7b,
- DBG_CLIENT_BLKID_mcd3 = 0x7c,
- DBG_CLIENT_BLKID_uvdu_0 = 0x7d,
- DBG_CLIENT_BLKID_uvdu_1 = 0x7e,
- DBG_CLIENT_BLKID_uvdu_2 = 0x7f,
- DBG_CLIENT_BLKID_uvdu_3 = 0x80,
- DBG_CLIENT_BLKID_uvdu_4 = 0x81,
- DBG_CLIENT_BLKID_uvdu_5 = 0x82,
- DBG_CLIENT_BLKID_uvdu_6 = 0x83,
- DBG_CLIENT_BLKID_cb300 = 0x84,
- DBG_CLIENT_BLKID_mcd1 = 0x85,
- DBG_CLIENT_BLKID_sx00 = 0x86,
- DBG_CLIENT_BLKID_uvdc_0 = 0x87,
- DBG_CLIENT_BLKID_uvdc_1 = 0x88,
- DBG_CLIENT_BLKID_mcc3 = 0x89,
- DBG_CLIENT_BLKID_cpg_0 = 0x8a,
- DBG_CLIENT_BLKID_cpg_1 = 0x8b,
- DBG_CLIENT_BLKID_gck = 0x8c,
- DBG_CLIENT_BLKID_mcc1 = 0x8d,
- DBG_CLIENT_BLKID_cpf_0 = 0x8e,
- DBG_CLIENT_BLKID_cpf_1 = 0x8f,
- DBG_CLIENT_BLKID_rlc = 0x90,
- DBG_CLIENT_BLKID_grbm = 0x91,
- DBG_CLIENT_BLKID_sammsp = 0x92,
- DBG_CLIENT_BLKID_dci_pg = 0x93,
- DBG_CLIENT_BLKID_dci_0 = 0x94,
- DBG_CLIENT_BLKID_dccg0_0 = 0x95,
- DBG_CLIENT_BLKID_dccg0_1 = 0x96,
- DBG_CLIENT_BLKID_dcfe01_0 = 0x97,
- DBG_CLIENT_BLKID_dcfe02_0 = 0x98,
- DBG_CLIENT_BLKID_dcfe03_0 = 0x99,
- DBG_CLIENT_BLKID_dcfe04_0 = 0x9a,
- DBG_CLIENT_BLKID_dcfe05_0 = 0x9b,
- DBG_CLIENT_BLKID_dcfe06_0 = 0x9c,
- DBG_CLIENT_BLKID_RESERVED_LAST = 0x9d,
-} DebugBlockId;
-typedef enum DebugBlockId_OLD {
- DBG_BLOCK_ID_RESERVED = 0x0,
- DBG_BLOCK_ID_DBG = 0x1,
- DBG_BLOCK_ID_VMC = 0x2,
- DBG_BLOCK_ID_PDMA = 0x3,
- DBG_BLOCK_ID_CG = 0x4,
- DBG_BLOCK_ID_SRBM = 0x5,
- DBG_BLOCK_ID_GRBM = 0x6,
- DBG_BLOCK_ID_RLC = 0x7,
- DBG_BLOCK_ID_CSC = 0x8,
- DBG_BLOCK_ID_SEM = 0x9,
- DBG_BLOCK_ID_IH = 0xa,
- DBG_BLOCK_ID_SC = 0xb,
- DBG_BLOCK_ID_SQ = 0xc,
- DBG_BLOCK_ID_AVP = 0xd,
- DBG_BLOCK_ID_GMCON = 0xe,
- DBG_BLOCK_ID_SMU = 0xf,
- DBG_BLOCK_ID_DMA0 = 0x10,
- DBG_BLOCK_ID_DMA1 = 0x11,
- DBG_BLOCK_ID_SPIM = 0x12,
- DBG_BLOCK_ID_GDS = 0x13,
- DBG_BLOCK_ID_SPIS = 0x14,
- DBG_BLOCK_ID_UNUSED0 = 0x15,
- DBG_BLOCK_ID_PA0 = 0x16,
- DBG_BLOCK_ID_PA1 = 0x17,
- DBG_BLOCK_ID_CP0 = 0x18,
- DBG_BLOCK_ID_CP1 = 0x19,
- DBG_BLOCK_ID_CP2 = 0x1a,
- DBG_BLOCK_ID_UNUSED1 = 0x1b,
- DBG_BLOCK_ID_UVDU = 0x1c,
- DBG_BLOCK_ID_UVDM = 0x1d,
- DBG_BLOCK_ID_VCE = 0x1e,
- DBG_BLOCK_ID_UNUSED2 = 0x1f,
- DBG_BLOCK_ID_VGT0 = 0x20,
- DBG_BLOCK_ID_VGT1 = 0x21,
- DBG_BLOCK_ID_IA = 0x22,
- DBG_BLOCK_ID_UNUSED3 = 0x23,
- DBG_BLOCK_ID_SCT0 = 0x24,
- DBG_BLOCK_ID_SCT1 = 0x25,
- DBG_BLOCK_ID_SPM0 = 0x26,
- DBG_BLOCK_ID_SPM1 = 0x27,
- DBG_BLOCK_ID_TCAA = 0x28,
- DBG_BLOCK_ID_TCAB = 0x29,
- DBG_BLOCK_ID_TCCA = 0x2a,
- DBG_BLOCK_ID_TCCB = 0x2b,
- DBG_BLOCK_ID_MCC0 = 0x2c,
- DBG_BLOCK_ID_MCC1 = 0x2d,
- DBG_BLOCK_ID_MCC2 = 0x2e,
- DBG_BLOCK_ID_MCC3 = 0x2f,
- DBG_BLOCK_ID_SX0 = 0x30,
- DBG_BLOCK_ID_SX1 = 0x31,
- DBG_BLOCK_ID_SX2 = 0x32,
- DBG_BLOCK_ID_SX3 = 0x33,
- DBG_BLOCK_ID_UNUSED4 = 0x34,
- DBG_BLOCK_ID_UNUSED5 = 0x35,
- DBG_BLOCK_ID_UNUSED6 = 0x36,
- DBG_BLOCK_ID_UNUSED7 = 0x37,
- DBG_BLOCK_ID_PC0 = 0x38,
- DBG_BLOCK_ID_PC1 = 0x39,
- DBG_BLOCK_ID_UNUSED8 = 0x3a,
- DBG_BLOCK_ID_UNUSED9 = 0x3b,
- DBG_BLOCK_ID_UNUSED10 = 0x3c,
- DBG_BLOCK_ID_UNUSED11 = 0x3d,
- DBG_BLOCK_ID_MCB = 0x3e,
- DBG_BLOCK_ID_UNUSED12 = 0x3f,
- DBG_BLOCK_ID_SCB0 = 0x40,
- DBG_BLOCK_ID_SCB1 = 0x41,
- DBG_BLOCK_ID_UNUSED13 = 0x42,
- DBG_BLOCK_ID_UNUSED14 = 0x43,
- DBG_BLOCK_ID_SCF0 = 0x44,
- DBG_BLOCK_ID_SCF1 = 0x45,
- DBG_BLOCK_ID_UNUSED15 = 0x46,
- DBG_BLOCK_ID_UNUSED16 = 0x47,
- DBG_BLOCK_ID_BCI0 = 0x48,
- DBG_BLOCK_ID_BCI1 = 0x49,
- DBG_BLOCK_ID_BCI2 = 0x4a,
- DBG_BLOCK_ID_BCI3 = 0x4b,
- DBG_BLOCK_ID_UNUSED17 = 0x4c,
- DBG_BLOCK_ID_UNUSED18 = 0x4d,
- DBG_BLOCK_ID_UNUSED19 = 0x4e,
- DBG_BLOCK_ID_UNUSED20 = 0x4f,
- DBG_BLOCK_ID_CB00 = 0x50,
- DBG_BLOCK_ID_CB01 = 0x51,
- DBG_BLOCK_ID_CB02 = 0x52,
- DBG_BLOCK_ID_CB03 = 0x53,
- DBG_BLOCK_ID_CB04 = 0x54,
- DBG_BLOCK_ID_UNUSED21 = 0x55,
- DBG_BLOCK_ID_UNUSED22 = 0x56,
- DBG_BLOCK_ID_UNUSED23 = 0x57,
- DBG_BLOCK_ID_CB10 = 0x58,
- DBG_BLOCK_ID_CB11 = 0x59,
- DBG_BLOCK_ID_CB12 = 0x5a,
- DBG_BLOCK_ID_CB13 = 0x5b,
- DBG_BLOCK_ID_CB14 = 0x5c,
- DBG_BLOCK_ID_UNUSED24 = 0x5d,
- DBG_BLOCK_ID_UNUSED25 = 0x5e,
- DBG_BLOCK_ID_UNUSED26 = 0x5f,
- DBG_BLOCK_ID_TCP0 = 0x60,
- DBG_BLOCK_ID_TCP1 = 0x61,
- DBG_BLOCK_ID_TCP2 = 0x62,
- DBG_BLOCK_ID_TCP3 = 0x63,
- DBG_BLOCK_ID_TCP4 = 0x64,
- DBG_BLOCK_ID_TCP5 = 0x65,
- DBG_BLOCK_ID_TCP6 = 0x66,
- DBG_BLOCK_ID_TCP7 = 0x67,
- DBG_BLOCK_ID_TCP8 = 0x68,
- DBG_BLOCK_ID_TCP9 = 0x69,
- DBG_BLOCK_ID_TCP10 = 0x6a,
- DBG_BLOCK_ID_TCP11 = 0x6b,
- DBG_BLOCK_ID_TCP12 = 0x6c,
- DBG_BLOCK_ID_TCP13 = 0x6d,
- DBG_BLOCK_ID_TCP14 = 0x6e,
- DBG_BLOCK_ID_TCP15 = 0x6f,
- DBG_BLOCK_ID_TCP16 = 0x70,
- DBG_BLOCK_ID_TCP17 = 0x71,
- DBG_BLOCK_ID_TCP18 = 0x72,
- DBG_BLOCK_ID_TCP19 = 0x73,
- DBG_BLOCK_ID_TCP20 = 0x74,
- DBG_BLOCK_ID_TCP21 = 0x75,
- DBG_BLOCK_ID_TCP22 = 0x76,
- DBG_BLOCK_ID_TCP23 = 0x77,
- DBG_BLOCK_ID_TCP_RESERVED0 = 0x78,
- DBG_BLOCK_ID_TCP_RESERVED1 = 0x79,
- DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a,
- DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b,
- DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c,
- DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d,
- DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e,
- DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f,
- DBG_BLOCK_ID_DB00 = 0x80,
- DBG_BLOCK_ID_DB01 = 0x81,
- DBG_BLOCK_ID_DB02 = 0x82,
- DBG_BLOCK_ID_DB03 = 0x83,
- DBG_BLOCK_ID_DB04 = 0x84,
- DBG_BLOCK_ID_UNUSED27 = 0x85,
- DBG_BLOCK_ID_UNUSED28 = 0x86,
- DBG_BLOCK_ID_UNUSED29 = 0x87,
- DBG_BLOCK_ID_DB10 = 0x88,
- DBG_BLOCK_ID_DB11 = 0x89,
- DBG_BLOCK_ID_DB12 = 0x8a,
- DBG_BLOCK_ID_DB13 = 0x8b,
- DBG_BLOCK_ID_DB14 = 0x8c,
- DBG_BLOCK_ID_UNUSED30 = 0x8d,
- DBG_BLOCK_ID_UNUSED31 = 0x8e,
- DBG_BLOCK_ID_UNUSED32 = 0x8f,
- DBG_BLOCK_ID_TCC0 = 0x90,
- DBG_BLOCK_ID_TCC1 = 0x91,
- DBG_BLOCK_ID_TCC2 = 0x92,
- DBG_BLOCK_ID_TCC3 = 0x93,
- DBG_BLOCK_ID_TCC4 = 0x94,
- DBG_BLOCK_ID_TCC5 = 0x95,
- DBG_BLOCK_ID_TCC6 = 0x96,
- DBG_BLOCK_ID_TCC7 = 0x97,
- DBG_BLOCK_ID_SPS00 = 0x98,
- DBG_BLOCK_ID_SPS01 = 0x99,
- DBG_BLOCK_ID_SPS02 = 0x9a,
- DBG_BLOCK_ID_SPS10 = 0x9b,
- DBG_BLOCK_ID_SPS11 = 0x9c,
- DBG_BLOCK_ID_SPS12 = 0x9d,
- DBG_BLOCK_ID_UNUSED33 = 0x9e,
- DBG_BLOCK_ID_UNUSED34 = 0x9f,
- DBG_BLOCK_ID_TA00 = 0xa0,
- DBG_BLOCK_ID_TA01 = 0xa1,
- DBG_BLOCK_ID_TA02 = 0xa2,
- DBG_BLOCK_ID_TA03 = 0xa3,
- DBG_BLOCK_ID_TA04 = 0xa4,
- DBG_BLOCK_ID_TA05 = 0xa5,
- DBG_BLOCK_ID_TA06 = 0xa6,
- DBG_BLOCK_ID_TA07 = 0xa7,
- DBG_BLOCK_ID_TA08 = 0xa8,
- DBG_BLOCK_ID_TA09 = 0xa9,
- DBG_BLOCK_ID_TA0A = 0xaa,
- DBG_BLOCK_ID_TA0B = 0xab,
- DBG_BLOCK_ID_UNUSED35 = 0xac,
- DBG_BLOCK_ID_UNUSED36 = 0xad,
- DBG_BLOCK_ID_UNUSED37 = 0xae,
- DBG_BLOCK_ID_UNUSED38 = 0xaf,
- DBG_BLOCK_ID_TA10 = 0xb0,
- DBG_BLOCK_ID_TA11 = 0xb1,
- DBG_BLOCK_ID_TA12 = 0xb2,
- DBG_BLOCK_ID_TA13 = 0xb3,
- DBG_BLOCK_ID_TA14 = 0xb4,
- DBG_BLOCK_ID_TA15 = 0xb5,
- DBG_BLOCK_ID_TA16 = 0xb6,
- DBG_BLOCK_ID_TA17 = 0xb7,
- DBG_BLOCK_ID_TA18 = 0xb8,
- DBG_BLOCK_ID_TA19 = 0xb9,
- DBG_BLOCK_ID_TA1A = 0xba,
- DBG_BLOCK_ID_TA1B = 0xbb,
- DBG_BLOCK_ID_UNUSED39 = 0xbc,
- DBG_BLOCK_ID_UNUSED40 = 0xbd,
- DBG_BLOCK_ID_UNUSED41 = 0xbe,
- DBG_BLOCK_ID_UNUSED42 = 0xbf,
- DBG_BLOCK_ID_TD00 = 0xc0,
- DBG_BLOCK_ID_TD01 = 0xc1,
- DBG_BLOCK_ID_TD02 = 0xc2,
- DBG_BLOCK_ID_TD03 = 0xc3,
- DBG_BLOCK_ID_TD04 = 0xc4,
- DBG_BLOCK_ID_TD05 = 0xc5,
- DBG_BLOCK_ID_TD06 = 0xc6,
- DBG_BLOCK_ID_TD07 = 0xc7,
- DBG_BLOCK_ID_TD08 = 0xc8,
- DBG_BLOCK_ID_TD09 = 0xc9,
- DBG_BLOCK_ID_TD0A = 0xca,
- DBG_BLOCK_ID_TD0B = 0xcb,
- DBG_BLOCK_ID_UNUSED43 = 0xcc,
- DBG_BLOCK_ID_UNUSED44 = 0xcd,
- DBG_BLOCK_ID_UNUSED45 = 0xce,
- DBG_BLOCK_ID_UNUSED46 = 0xcf,
- DBG_BLOCK_ID_TD10 = 0xd0,
- DBG_BLOCK_ID_TD11 = 0xd1,
- DBG_BLOCK_ID_TD12 = 0xd2,
- DBG_BLOCK_ID_TD13 = 0xd3,
- DBG_BLOCK_ID_TD14 = 0xd4,
- DBG_BLOCK_ID_TD15 = 0xd5,
- DBG_BLOCK_ID_TD16 = 0xd6,
- DBG_BLOCK_ID_TD17 = 0xd7,
- DBG_BLOCK_ID_TD18 = 0xd8,
- DBG_BLOCK_ID_TD19 = 0xd9,
- DBG_BLOCK_ID_TD1A = 0xda,
- DBG_BLOCK_ID_TD1B = 0xdb,
- DBG_BLOCK_ID_UNUSED47 = 0xdc,
- DBG_BLOCK_ID_UNUSED48 = 0xdd,
- DBG_BLOCK_ID_UNUSED49 = 0xde,
- DBG_BLOCK_ID_UNUSED50 = 0xdf,
- DBG_BLOCK_ID_MCD0 = 0xe0,
- DBG_BLOCK_ID_MCD1 = 0xe1,
- DBG_BLOCK_ID_MCD2 = 0xe2,
- DBG_BLOCK_ID_MCD3 = 0xe3,
- DBG_BLOCK_ID_MCD4 = 0xe4,
- DBG_BLOCK_ID_MCD5 = 0xe5,
- DBG_BLOCK_ID_UNUSED51 = 0xe6,
- DBG_BLOCK_ID_UNUSED52 = 0xe7,
-} DebugBlockId_OLD;
-typedef enum DebugBlockId_BY2 {
- DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
- DBG_BLOCK_ID_VMC_BY2 = 0x1,
- DBG_BLOCK_ID_CG_BY2 = 0x2,
- DBG_BLOCK_ID_GRBM_BY2 = 0x3,
- DBG_BLOCK_ID_CSC_BY2 = 0x4,
- DBG_BLOCK_ID_IH_BY2 = 0x5,
- DBG_BLOCK_ID_SQ_BY2 = 0x6,
- DBG_BLOCK_ID_GMCON_BY2 = 0x7,
- DBG_BLOCK_ID_DMA0_BY2 = 0x8,
- DBG_BLOCK_ID_SPIM_BY2 = 0x9,
- DBG_BLOCK_ID_SPIS_BY2 = 0xa,
- DBG_BLOCK_ID_PA0_BY2 = 0xb,
- DBG_BLOCK_ID_CP0_BY2 = 0xc,
- DBG_BLOCK_ID_CP2_BY2 = 0xd,
- DBG_BLOCK_ID_UVDU_BY2 = 0xe,
- DBG_BLOCK_ID_VCE_BY2 = 0xf,
- DBG_BLOCK_ID_VGT0_BY2 = 0x10,
- DBG_BLOCK_ID_IA_BY2 = 0x11,
- DBG_BLOCK_ID_SCT0_BY2 = 0x12,
- DBG_BLOCK_ID_SPM0_BY2 = 0x13,
- DBG_BLOCK_ID_TCAA_BY2 = 0x14,
- DBG_BLOCK_ID_TCCA_BY2 = 0x15,
- DBG_BLOCK_ID_MCC0_BY2 = 0x16,
- DBG_BLOCK_ID_MCC2_BY2 = 0x17,
- DBG_BLOCK_ID_SX0_BY2 = 0x18,
- DBG_BLOCK_ID_SX2_BY2 = 0x19,
- DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a,
- DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b,
- DBG_BLOCK_ID_PC0_BY2 = 0x1c,
- DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d,
- DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e,
- DBG_BLOCK_ID_MCB_BY2 = 0x1f,
- DBG_BLOCK_ID_SCB0_BY2 = 0x20,
- DBG_BLOCK_ID_UNUSED13_BY2 = 0x21,
- DBG_BLOCK_ID_SCF0_BY2 = 0x22,
- DBG_BLOCK_ID_UNUSED15_BY2 = 0x23,
- DBG_BLOCK_ID_BCI0_BY2 = 0x24,
- DBG_BLOCK_ID_BCI2_BY2 = 0x25,
- DBG_BLOCK_ID_UNUSED17_BY2 = 0x26,
- DBG_BLOCK_ID_UNUSED19_BY2 = 0x27,
- DBG_BLOCK_ID_CB00_BY2 = 0x28,
- DBG_BLOCK_ID_CB02_BY2 = 0x29,
- DBG_BLOCK_ID_CB04_BY2 = 0x2a,
- DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b,
- DBG_BLOCK_ID_CB10_BY2 = 0x2c,
- DBG_BLOCK_ID_CB12_BY2 = 0x2d,
- DBG_BLOCK_ID_CB14_BY2 = 0x2e,
- DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f,
- DBG_BLOCK_ID_TCP0_BY2 = 0x30,
- DBG_BLOCK_ID_TCP2_BY2 = 0x31,
- DBG_BLOCK_ID_TCP4_BY2 = 0x32,
- DBG_BLOCK_ID_TCP6_BY2 = 0x33,
- DBG_BLOCK_ID_TCP8_BY2 = 0x34,
- DBG_BLOCK_ID_TCP10_BY2 = 0x35,
- DBG_BLOCK_ID_TCP12_BY2 = 0x36,
- DBG_BLOCK_ID_TCP14_BY2 = 0x37,
- DBG_BLOCK_ID_TCP16_BY2 = 0x38,
- DBG_BLOCK_ID_TCP18_BY2 = 0x39,
- DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
- DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
- DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
- DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
- DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
- DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
- DBG_BLOCK_ID_DB00_BY2 = 0x40,
- DBG_BLOCK_ID_DB02_BY2 = 0x41,
- DBG_BLOCK_ID_DB04_BY2 = 0x42,
- DBG_BLOCK_ID_UNUSED28_BY2 = 0x43,
- DBG_BLOCK_ID_DB10_BY2 = 0x44,
- DBG_BLOCK_ID_DB12_BY2 = 0x45,
- DBG_BLOCK_ID_DB14_BY2 = 0x46,
- DBG_BLOCK_ID_UNUSED31_BY2 = 0x47,
- DBG_BLOCK_ID_TCC0_BY2 = 0x48,
- DBG_BLOCK_ID_TCC2_BY2 = 0x49,
- DBG_BLOCK_ID_TCC4_BY2 = 0x4a,
- DBG_BLOCK_ID_TCC6_BY2 = 0x4b,
- DBG_BLOCK_ID_SPS00_BY2 = 0x4c,
- DBG_BLOCK_ID_SPS02_BY2 = 0x4d,
- DBG_BLOCK_ID_SPS11_BY2 = 0x4e,
- DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f,
- DBG_BLOCK_ID_TA00_BY2 = 0x50,
- DBG_BLOCK_ID_TA02_BY2 = 0x51,
- DBG_BLOCK_ID_TA04_BY2 = 0x52,
- DBG_BLOCK_ID_TA06_BY2 = 0x53,
- DBG_BLOCK_ID_TA08_BY2 = 0x54,
- DBG_BLOCK_ID_TA0A_BY2 = 0x55,
- DBG_BLOCK_ID_UNUSED35_BY2 = 0x56,
- DBG_BLOCK_ID_UNUSED37_BY2 = 0x57,
- DBG_BLOCK_ID_TA10_BY2 = 0x58,
- DBG_BLOCK_ID_TA12_BY2 = 0x59,
- DBG_BLOCK_ID_TA14_BY2 = 0x5a,
- DBG_BLOCK_ID_TA16_BY2 = 0x5b,
- DBG_BLOCK_ID_TA18_BY2 = 0x5c,
- DBG_BLOCK_ID_TA1A_BY2 = 0x5d,
- DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e,
- DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f,
- DBG_BLOCK_ID_TD00_BY2 = 0x60,
- DBG_BLOCK_ID_TD02_BY2 = 0x61,
- DBG_BLOCK_ID_TD04_BY2 = 0x62,
- DBG_BLOCK_ID_TD06_BY2 = 0x63,
- DBG_BLOCK_ID_TD08_BY2 = 0x64,
- DBG_BLOCK_ID_TD0A_BY2 = 0x65,
- DBG_BLOCK_ID_UNUSED43_BY2 = 0x66,
- DBG_BLOCK_ID_UNUSED45_BY2 = 0x67,
- DBG_BLOCK_ID_TD10_BY2 = 0x68,
- DBG_BLOCK_ID_TD12_BY2 = 0x69,
- DBG_BLOCK_ID_TD14_BY2 = 0x6a,
- DBG_BLOCK_ID_TD16_BY2 = 0x6b,
- DBG_BLOCK_ID_TD18_BY2 = 0x6c,
- DBG_BLOCK_ID_TD1A_BY2 = 0x6d,
- DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e,
- DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f,
- DBG_BLOCK_ID_MCD0_BY2 = 0x70,
- DBG_BLOCK_ID_MCD2_BY2 = 0x71,
- DBG_BLOCK_ID_MCD4_BY2 = 0x72,
- DBG_BLOCK_ID_UNUSED51_BY2 = 0x73,
-} DebugBlockId_BY2;
-typedef enum DebugBlockId_BY4 {
- DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
- DBG_BLOCK_ID_CG_BY4 = 0x1,
- DBG_BLOCK_ID_CSC_BY4 = 0x2,
- DBG_BLOCK_ID_SQ_BY4 = 0x3,
- DBG_BLOCK_ID_DMA0_BY4 = 0x4,
- DBG_BLOCK_ID_SPIS_BY4 = 0x5,
- DBG_BLOCK_ID_CP0_BY4 = 0x6,
- DBG_BLOCK_ID_UVDU_BY4 = 0x7,
- DBG_BLOCK_ID_VGT0_BY4 = 0x8,
- DBG_BLOCK_ID_SCT0_BY4 = 0x9,
- DBG_BLOCK_ID_TCAA_BY4 = 0xa,
- DBG_BLOCK_ID_MCC0_BY4 = 0xb,
- DBG_BLOCK_ID_SX0_BY4 = 0xc,
- DBG_BLOCK_ID_UNUSED4_BY4 = 0xd,
- DBG_BLOCK_ID_PC0_BY4 = 0xe,
- DBG_BLOCK_ID_UNUSED10_BY4 = 0xf,
- DBG_BLOCK_ID_SCB0_BY4 = 0x10,
- DBG_BLOCK_ID_SCF0_BY4 = 0x11,
- DBG_BLOCK_ID_BCI0_BY4 = 0x12,
- DBG_BLOCK_ID_UNUSED17_BY4 = 0x13,
- DBG_BLOCK_ID_CB00_BY4 = 0x14,
- DBG_BLOCK_ID_CB04_BY4 = 0x15,
- DBG_BLOCK_ID_CB10_BY4 = 0x16,
- DBG_BLOCK_ID_CB14_BY4 = 0x17,
- DBG_BLOCK_ID_TCP0_BY4 = 0x18,
- DBG_BLOCK_ID_TCP4_BY4 = 0x19,
- DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
- DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
- DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
- DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
- DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
- DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
- DBG_BLOCK_ID_DB_BY4 = 0x20,
- DBG_BLOCK_ID_DB04_BY4 = 0x21,
- DBG_BLOCK_ID_DB10_BY4 = 0x22,
- DBG_BLOCK_ID_DB14_BY4 = 0x23,
- DBG_BLOCK_ID_TCC0_BY4 = 0x24,
- DBG_BLOCK_ID_TCC4_BY4 = 0x25,
- DBG_BLOCK_ID_SPS00_BY4 = 0x26,
- DBG_BLOCK_ID_SPS11_BY4 = 0x27,
- DBG_BLOCK_ID_TA00_BY4 = 0x28,
- DBG_BLOCK_ID_TA04_BY4 = 0x29,
- DBG_BLOCK_ID_TA08_BY4 = 0x2a,
- DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b,
- DBG_BLOCK_ID_TA10_BY4 = 0x2c,
- DBG_BLOCK_ID_TA14_BY4 = 0x2d,
- DBG_BLOCK_ID_TA18_BY4 = 0x2e,
- DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f,
- DBG_BLOCK_ID_TD00_BY4 = 0x30,
- DBG_BLOCK_ID_TD04_BY4 = 0x31,
- DBG_BLOCK_ID_TD08_BY4 = 0x32,
- DBG_BLOCK_ID_UNUSED43_BY4 = 0x33,
- DBG_BLOCK_ID_TD10_BY4 = 0x34,
- DBG_BLOCK_ID_TD14_BY4 = 0x35,
- DBG_BLOCK_ID_TD18_BY4 = 0x36,
- DBG_BLOCK_ID_UNUSED47_BY4 = 0x37,
- DBG_BLOCK_ID_MCD0_BY4 = 0x38,
- DBG_BLOCK_ID_MCD4_BY4 = 0x39,
-} DebugBlockId_BY4;
-typedef enum DebugBlockId_BY8 {
- DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
- DBG_BLOCK_ID_CSC_BY8 = 0x1,
- DBG_BLOCK_ID_DMA0_BY8 = 0x2,
- DBG_BLOCK_ID_CP0_BY8 = 0x3,
- DBG_BLOCK_ID_VGT0_BY8 = 0x4,
- DBG_BLOCK_ID_TCAA_BY8 = 0x5,
- DBG_BLOCK_ID_SX0_BY8 = 0x6,
- DBG_BLOCK_ID_PC0_BY8 = 0x7,
- DBG_BLOCK_ID_SCB0_BY8 = 0x8,
- DBG_BLOCK_ID_BCI0_BY8 = 0x9,
- DBG_BLOCK_ID_CB00_BY8 = 0xa,
- DBG_BLOCK_ID_CB10_BY8 = 0xb,
- DBG_BLOCK_ID_TCP0_BY8 = 0xc,
- DBG_BLOCK_ID_TCP8_BY8 = 0xd,
- DBG_BLOCK_ID_TCP16_BY8 = 0xe,
- DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
- DBG_BLOCK_ID_DB00_BY8 = 0x10,
- DBG_BLOCK_ID_DB10_BY8 = 0x11,
- DBG_BLOCK_ID_TCC0_BY8 = 0x12,
- DBG_BLOCK_ID_SPS00_BY8 = 0x13,
- DBG_BLOCK_ID_TA00_BY8 = 0x14,
- DBG_BLOCK_ID_TA08_BY8 = 0x15,
- DBG_BLOCK_ID_TA10_BY8 = 0x16,
- DBG_BLOCK_ID_TA18_BY8 = 0x17,
- DBG_BLOCK_ID_TD00_BY8 = 0x18,
- DBG_BLOCK_ID_TD08_BY8 = 0x19,
- DBG_BLOCK_ID_TD10_BY8 = 0x1a,
- DBG_BLOCK_ID_TD18_BY8 = 0x1b,
- DBG_BLOCK_ID_MCD0_BY8 = 0x1c,
-} DebugBlockId_BY8;
-typedef enum DebugBlockId_BY16 {
- DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
- DBG_BLOCK_ID_DMA0_BY16 = 0x1,
- DBG_BLOCK_ID_VGT0_BY16 = 0x2,
- DBG_BLOCK_ID_SX0_BY16 = 0x3,
- DBG_BLOCK_ID_SCB0_BY16 = 0x4,
- DBG_BLOCK_ID_CB00_BY16 = 0x5,
- DBG_BLOCK_ID_TCP0_BY16 = 0x6,
- DBG_BLOCK_ID_TCP16_BY16 = 0x7,
- DBG_BLOCK_ID_DB00_BY16 = 0x8,
- DBG_BLOCK_ID_TCC0_BY16 = 0x9,
- DBG_BLOCK_ID_TA00_BY16 = 0xa,
- DBG_BLOCK_ID_TA10_BY16 = 0xb,
- DBG_BLOCK_ID_TD00_BY16 = 0xc,
- DBG_BLOCK_ID_TD10_BY16 = 0xd,
- DBG_BLOCK_ID_MCD0_BY16 = 0xe,
-} DebugBlockId_BY16;
-typedef enum ColorTransform {
- DCC_CT_AUTO = 0x0,
- DCC_CT_NONE = 0x1,
- ABGR_TO_A_BG_G_RB = 0x2,
- BGRA_TO_BG_G_RB_A = 0x3,
-} ColorTransform;
-typedef enum CompareRef {
- REF_NEVER = 0x0,
- REF_LESS = 0x1,
- REF_EQUAL = 0x2,
- REF_LEQUAL = 0x3,
- REF_GREATER = 0x4,
- REF_NOTEQUAL = 0x5,
- REF_GEQUAL = 0x6,
- REF_ALWAYS = 0x7,
-} CompareRef;
-typedef enum ReadSize {
- READ_256_BITS = 0x0,
- READ_512_BITS = 0x1,
-} ReadSize;
-typedef enum DepthFormat {
- DEPTH_INVALID = 0x0,
- DEPTH_16 = 0x1,
- DEPTH_X8_24 = 0x2,
- DEPTH_8_24 = 0x3,
- DEPTH_X8_24_FLOAT = 0x4,
- DEPTH_8_24_FLOAT = 0x5,
- DEPTH_32_FLOAT = 0x6,
- DEPTH_X24_8_32_FLOAT = 0x7,
-} DepthFormat;
-typedef enum ZFormat {
- Z_INVALID = 0x0,
- Z_16 = 0x1,
- Z_24 = 0x2,
- Z_32_FLOAT = 0x3,
-} ZFormat;
-typedef enum StencilFormat {
- STENCIL_INVALID = 0x0,
- STENCIL_8 = 0x1,
-} StencilFormat;
-typedef enum CmaskMode {
- CMASK_CLEAR_NONE = 0x0,
- CMASK_CLEAR_ONE = 0x1,
- CMASK_CLEAR_ALL = 0x2,
- CMASK_ANY_EXPANDED = 0x3,
- CMASK_ALPHA0_FRAG1 = 0x4,
- CMASK_ALPHA0_FRAG2 = 0x5,
- CMASK_ALPHA0_FRAG4 = 0x6,
- CMASK_ALPHA0_FRAGS = 0x7,
- CMASK_ALPHA1_FRAG1 = 0x8,
- CMASK_ALPHA1_FRAG2 = 0x9,
- CMASK_ALPHA1_FRAG4 = 0xa,
- CMASK_ALPHA1_FRAGS = 0xb,
- CMASK_ALPHAX_FRAG1 = 0xc,
- CMASK_ALPHAX_FRAG2 = 0xd,
- CMASK_ALPHAX_FRAG4 = 0xe,
- CMASK_ALPHAX_FRAGS = 0xf,
-} CmaskMode;
-typedef enum QuadExportFormat {
- EXPORT_UNUSED = 0x0,
- EXPORT_32_R = 0x1,
- EXPORT_32_GR = 0x2,
- EXPORT_32_AR = 0x3,
- EXPORT_FP16_ABGR = 0x4,
- EXPORT_UNSIGNED16_ABGR = 0x5,
- EXPORT_SIGNED16_ABGR = 0x6,
- EXPORT_32_ABGR = 0x7,
-} QuadExportFormat;
-typedef enum QuadExportFormatOld {
- EXPORT_4P_32BPC_ABGR = 0x0,
- EXPORT_4P_16BPC_ABGR = 0x1,
- EXPORT_4P_32BPC_GR = 0x2,
- EXPORT_4P_32BPC_AR = 0x3,
- EXPORT_2P_32BPC_ABGR = 0x4,
- EXPORT_8P_32BPC_R = 0x5,
-} QuadExportFormatOld;
-typedef enum ColorFormat {
- COLOR_INVALID = 0x0,
- COLOR_8 = 0x1,
- COLOR_16 = 0x2,
- COLOR_8_8 = 0x3,
- COLOR_32 = 0x4,
- COLOR_16_16 = 0x5,
- COLOR_10_11_11 = 0x6,
- COLOR_11_11_10 = 0x7,
- COLOR_10_10_10_2 = 0x8,
- COLOR_2_10_10_10 = 0x9,
- COLOR_8_8_8_8 = 0xa,
- COLOR_32_32 = 0xb,
- COLOR_16_16_16_16 = 0xc,
- COLOR_RESERVED_13 = 0xd,
- COLOR_32_32_32_32 = 0xe,
- COLOR_RESERVED_15 = 0xf,
- COLOR_5_6_5 = 0x10,
- COLOR_1_5_5_5 = 0x11,
- COLOR_5_5_5_1 = 0x12,
- COLOR_4_4_4_4 = 0x13,
- COLOR_8_24 = 0x14,
- COLOR_24_8 = 0x15,
- COLOR_X24_8_32_FLOAT = 0x16,
- COLOR_RESERVED_23 = 0x17,
-} ColorFormat;
-typedef enum SurfaceFormat {
- FMT_INVALID = 0x0,
- FMT_8 = 0x1,
- FMT_16 = 0x2,
- FMT_8_8 = 0x3,
- FMT_32 = 0x4,
- FMT_16_16 = 0x5,
- FMT_10_11_11 = 0x6,
- FMT_11_11_10 = 0x7,
- FMT_10_10_10_2 = 0x8,
- FMT_2_10_10_10 = 0x9,
- FMT_8_8_8_8 = 0xa,
- FMT_32_32 = 0xb,
- FMT_16_16_16_16 = 0xc,
- FMT_32_32_32 = 0xd,
- FMT_32_32_32_32 = 0xe,
- FMT_RESERVED_4 = 0xf,
- FMT_5_6_5 = 0x10,
- FMT_1_5_5_5 = 0x11,
- FMT_5_5_5_1 = 0x12,
- FMT_4_4_4_4 = 0x13,
- FMT_8_24 = 0x14,
- FMT_24_8 = 0x15,
- FMT_X24_8_32_FLOAT = 0x16,
- FMT_RESERVED_33 = 0x17,
- FMT_11_11_10_FLOAT = 0x18,
- FMT_16_FLOAT = 0x19,
- FMT_32_FLOAT = 0x1a,
- FMT_16_16_FLOAT = 0x1b,
- FMT_8_24_FLOAT = 0x1c,
- FMT_24_8_FLOAT = 0x1d,
- FMT_32_32_FLOAT = 0x1e,
- FMT_10_11_11_FLOAT = 0x1f,
- FMT_16_16_16_16_FLOAT = 0x20,
- FMT_3_3_2 = 0x21,
- FMT_6_5_5 = 0x22,
- FMT_32_32_32_32_FLOAT = 0x23,
- FMT_RESERVED_36 = 0x24,
- FMT_1 = 0x25,
- FMT_1_REVERSED = 0x26,
- FMT_GB_GR = 0x27,
- FMT_BG_RG = 0x28,
- FMT_32_AS_8 = 0x29,
- FMT_32_AS_8_8 = 0x2a,
- FMT_5_9_9_9_SHAREDEXP = 0x2b,
- FMT_8_8_8 = 0x2c,
- FMT_16_16_16 = 0x2d,
- FMT_16_16_16_FLOAT = 0x2e,
- FMT_4_4 = 0x2f,
- FMT_32_32_32_FLOAT = 0x30,
- FMT_BC1 = 0x31,
- FMT_BC2 = 0x32,
- FMT_BC3 = 0x33,
- FMT_BC4 = 0x34,
- FMT_BC5 = 0x35,
- FMT_BC6 = 0x36,
- FMT_BC7 = 0x37,
- FMT_32_AS_32_32_32_32 = 0x38,
- FMT_APC3 = 0x39,
- FMT_APC4 = 0x3a,
- FMT_APC5 = 0x3b,
- FMT_APC6 = 0x3c,
- FMT_APC7 = 0x3d,
- FMT_CTX1 = 0x3e,
- FMT_RESERVED_63 = 0x3f,
-} SurfaceFormat;
-typedef enum BUF_DATA_FORMAT {
- BUF_DATA_FORMAT_INVALID = 0x0,
- BUF_DATA_FORMAT_8 = 0x1,
- BUF_DATA_FORMAT_16 = 0x2,
- BUF_DATA_FORMAT_8_8 = 0x3,
- BUF_DATA_FORMAT_32 = 0x4,
- BUF_DATA_FORMAT_16_16 = 0x5,
- BUF_DATA_FORMAT_10_11_11 = 0x6,
- BUF_DATA_FORMAT_11_11_10 = 0x7,
- BUF_DATA_FORMAT_10_10_10_2 = 0x8,
- BUF_DATA_FORMAT_2_10_10_10 = 0x9,
- BUF_DATA_FORMAT_8_8_8_8 = 0xa,
- BUF_DATA_FORMAT_32_32 = 0xb,
- BUF_DATA_FORMAT_16_16_16_16 = 0xc,
- BUF_DATA_FORMAT_32_32_32 = 0xd,
- BUF_DATA_FORMAT_32_32_32_32 = 0xe,
- BUF_DATA_FORMAT_RESERVED_15 = 0xf,
-} BUF_DATA_FORMAT;
-typedef enum IMG_DATA_FORMAT {
- IMG_DATA_FORMAT_INVALID = 0x0,
- IMG_DATA_FORMAT_8 = 0x1,
- IMG_DATA_FORMAT_16 = 0x2,
- IMG_DATA_FORMAT_8_8 = 0x3,
- IMG_DATA_FORMAT_32 = 0x4,
- IMG_DATA_FORMAT_16_16 = 0x5,
- IMG_DATA_FORMAT_10_11_11 = 0x6,
- IMG_DATA_FORMAT_11_11_10 = 0x7,
- IMG_DATA_FORMAT_10_10_10_2 = 0x8,
- IMG_DATA_FORMAT_2_10_10_10 = 0x9,
- IMG_DATA_FORMAT_8_8_8_8 = 0xa,
- IMG_DATA_FORMAT_32_32 = 0xb,
- IMG_DATA_FORMAT_16_16_16_16 = 0xc,
- IMG_DATA_FORMAT_32_32_32 = 0xd,
- IMG_DATA_FORMAT_32_32_32_32 = 0xe,
- IMG_DATA_FORMAT_RESERVED_15 = 0xf,
- IMG_DATA_FORMAT_5_6_5 = 0x10,
- IMG_DATA_FORMAT_1_5_5_5 = 0x11,
- IMG_DATA_FORMAT_5_5_5_1 = 0x12,
- IMG_DATA_FORMAT_4_4_4_4 = 0x13,
- IMG_DATA_FORMAT_8_24 = 0x14,
- IMG_DATA_FORMAT_24_8 = 0x15,
- IMG_DATA_FORMAT_X24_8_32 = 0x16,
- IMG_DATA_FORMAT_RESERVED_23 = 0x17,
- IMG_DATA_FORMAT_RESERVED_24 = 0x18,
- IMG_DATA_FORMAT_RESERVED_25 = 0x19,
- IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
- IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
- IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
- IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
- IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
- IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
- IMG_DATA_FORMAT_GB_GR = 0x20,
- IMG_DATA_FORMAT_BG_RG = 0x21,
- IMG_DATA_FORMAT_5_9_9_9 = 0x22,
- IMG_DATA_FORMAT_BC1 = 0x23,
- IMG_DATA_FORMAT_BC2 = 0x24,
- IMG_DATA_FORMAT_BC3 = 0x25,
- IMG_DATA_FORMAT_BC4 = 0x26,
- IMG_DATA_FORMAT_BC5 = 0x27,
- IMG_DATA_FORMAT_BC6 = 0x28,
- IMG_DATA_FORMAT_BC7 = 0x29,
- IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
- IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
- IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
- IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
- IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
- IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
- IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
- IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
- IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
- IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
- IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
- IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
- IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
- IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
- IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
- IMG_DATA_FORMAT_4_4 = 0x39,
- IMG_DATA_FORMAT_6_5_5 = 0x3a,
- IMG_DATA_FORMAT_1 = 0x3b,
- IMG_DATA_FORMAT_1_REVERSED = 0x3c,
- IMG_DATA_FORMAT_32_AS_8 = 0x3d,
- IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
- IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
-} IMG_DATA_FORMAT;
-typedef enum BUF_NUM_FORMAT {
- BUF_NUM_FORMAT_UNORM = 0x0,
- BUF_NUM_FORMAT_SNORM = 0x1,
- BUF_NUM_FORMAT_USCALED = 0x2,
- BUF_NUM_FORMAT_SSCALED = 0x3,
- BUF_NUM_FORMAT_UINT = 0x4,
- BUF_NUM_FORMAT_SINT = 0x5,
- BUF_NUM_FORMAT_RESERVED_6 = 0x6,
- BUF_NUM_FORMAT_FLOAT = 0x7,
-} BUF_NUM_FORMAT;
-typedef enum IMG_NUM_FORMAT {
- IMG_NUM_FORMAT_UNORM = 0x0,
- IMG_NUM_FORMAT_SNORM = 0x1,
- IMG_NUM_FORMAT_USCALED = 0x2,
- IMG_NUM_FORMAT_SSCALED = 0x3,
- IMG_NUM_FORMAT_UINT = 0x4,
- IMG_NUM_FORMAT_SINT = 0x5,
- IMG_NUM_FORMAT_RESERVED_6 = 0x6,
- IMG_NUM_FORMAT_FLOAT = 0x7,
- IMG_NUM_FORMAT_RESERVED_8 = 0x8,
- IMG_NUM_FORMAT_SRGB = 0x9,
- IMG_NUM_FORMAT_RESERVED_10 = 0xa,
- IMG_NUM_FORMAT_RESERVED_11 = 0xb,
- IMG_NUM_FORMAT_RESERVED_12 = 0xc,
- IMG_NUM_FORMAT_RESERVED_13 = 0xd,
- IMG_NUM_FORMAT_RESERVED_14 = 0xe,
- IMG_NUM_FORMAT_RESERVED_15 = 0xf,
-} IMG_NUM_FORMAT;
-typedef enum TileType {
- ARRAY_COLOR_TILE = 0x0,
- ARRAY_DEPTH_TILE = 0x1,
-} TileType;
-typedef enum NonDispTilingOrder {
- ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
- ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
-} NonDispTilingOrder;
-typedef enum MicroTileMode {
- ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
- ADDR_SURF_THIN_MICRO_TILING = 0x1,
- ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
- ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
- ADDR_SURF_THICK_MICRO_TILING = 0x4,
-} MicroTileMode;
-typedef enum TileSplit {
- ADDR_SURF_TILE_SPLIT_64B = 0x0,
- ADDR_SURF_TILE_SPLIT_128B = 0x1,
- ADDR_SURF_TILE_SPLIT_256B = 0x2,
- ADDR_SURF_TILE_SPLIT_512B = 0x3,
- ADDR_SURF_TILE_SPLIT_1KB = 0x4,
- ADDR_SURF_TILE_SPLIT_2KB = 0x5,
- ADDR_SURF_TILE_SPLIT_4KB = 0x6,
-} TileSplit;
-typedef enum SampleSplit {
- ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
- ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
- ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
- ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
-} SampleSplit;
-typedef enum PipeConfig {
- ADDR_SURF_P2 = 0x0,
- ADDR_SURF_P2_RESERVED0 = 0x1,
- ADDR_SURF_P2_RESERVED1 = 0x2,
- ADDR_SURF_P2_RESERVED2 = 0x3,
- ADDR_SURF_P4_8x16 = 0x4,
- ADDR_SURF_P4_16x16 = 0x5,
- ADDR_SURF_P4_16x32 = 0x6,
- ADDR_SURF_P4_32x32 = 0x7,
- ADDR_SURF_P8_16x16_8x16 = 0x8,
- ADDR_SURF_P8_16x32_8x16 = 0x9,
- ADDR_SURF_P8_32x32_8x16 = 0xa,
- ADDR_SURF_P8_16x32_16x16 = 0xb,
- ADDR_SURF_P8_32x32_16x16 = 0xc,
- ADDR_SURF_P8_32x32_16x32 = 0xd,
- ADDR_SURF_P8_32x64_32x32 = 0xe,
- ADDR_SURF_P8_RESERVED0 = 0xf,
- ADDR_SURF_P16_32x32_8x16 = 0x10,
- ADDR_SURF_P16_32x32_16x16 = 0x11,
-} PipeConfig;
-typedef enum NumBanks {
- ADDR_SURF_2_BANK = 0x0,
- ADDR_SURF_4_BANK = 0x1,
- ADDR_SURF_8_BANK = 0x2,
- ADDR_SURF_16_BANK = 0x3,
-} NumBanks;
-typedef enum BankWidth {
- ADDR_SURF_BANK_WIDTH_1 = 0x0,
- ADDR_SURF_BANK_WIDTH_2 = 0x1,
- ADDR_SURF_BANK_WIDTH_4 = 0x2,
- ADDR_SURF_BANK_WIDTH_8 = 0x3,
-} BankWidth;
-typedef enum BankHeight {
- ADDR_SURF_BANK_HEIGHT_1 = 0x0,
- ADDR_SURF_BANK_HEIGHT_2 = 0x1,
- ADDR_SURF_BANK_HEIGHT_4 = 0x2,
- ADDR_SURF_BANK_HEIGHT_8 = 0x3,
-} BankHeight;
-typedef enum BankWidthHeight {
- ADDR_SURF_BANK_WH_1 = 0x0,
- ADDR_SURF_BANK_WH_2 = 0x1,
- ADDR_SURF_BANK_WH_4 = 0x2,
- ADDR_SURF_BANK_WH_8 = 0x3,
-} BankWidthHeight;
-typedef enum MacroTileAspect {
- ADDR_SURF_MACRO_ASPECT_1 = 0x0,
- ADDR_SURF_MACRO_ASPECT_2 = 0x1,
- ADDR_SURF_MACRO_ASPECT_4 = 0x2,
- ADDR_SURF_MACRO_ASPECT_8 = 0x3,
-} MacroTileAspect;
-typedef enum GATCL1RequestType {
- GATCL1_TYPE_NORMAL = 0x0,
- GATCL1_TYPE_SHOOTDOWN = 0x1,
- GATCL1_TYPE_BYPASS = 0x2,
-} GATCL1RequestType;
-typedef enum TCC_CACHE_POLICIES {
- TCC_CACHE_POLICY_LRU = 0x0,
- TCC_CACHE_POLICY_STREAM = 0x1,
-} TCC_CACHE_POLICIES;
-typedef enum MTYPE {
- MTYPE_NC_NV = 0x0,
- MTYPE_NC = 0x1,
- MTYPE_CC = 0x2,
- MTYPE_UC = 0x3,
-} MTYPE;
-typedef enum PERFMON_COUNTER_MODE {
- PERFMON_COUNTER_MODE_ACCUM = 0x0,
- PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
- PERFMON_COUNTER_MODE_MAX = 0x2,
- PERFMON_COUNTER_MODE_DIRTY = 0x3,
- PERFMON_COUNTER_MODE_SAMPLE = 0x4,
- PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
- PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
- PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
- PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
- PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
- PERFMON_COUNTER_MODE_RESERVED = 0xf,
-} PERFMON_COUNTER_MODE;
-typedef enum PERFMON_SPM_MODE {
- PERFMON_SPM_MODE_OFF = 0x0,
- PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
- PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
- PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
- PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
- PERFMON_SPM_MODE_RESERVED_5 = 0x5,
- PERFMON_SPM_MODE_RESERVED_6 = 0x6,
- PERFMON_SPM_MODE_RESERVED_7 = 0x7,
- PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
- PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
- PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
-} PERFMON_SPM_MODE;
-typedef enum SurfaceTiling {
- ARRAY_LINEAR = 0x0,
- ARRAY_TILED = 0x1,
-} SurfaceTiling;
-typedef enum SurfaceArray {
- ARRAY_1D = 0x0,
- ARRAY_2D = 0x1,
- ARRAY_3D = 0x2,
- ARRAY_3D_SLICE = 0x3,
-} SurfaceArray;
-typedef enum ColorArray {
- ARRAY_2D_ALT_COLOR = 0x0,
- ARRAY_2D_COLOR = 0x1,
- ARRAY_3D_SLICE_COLOR = 0x3,
-} ColorArray;
-typedef enum DepthArray {
- ARRAY_2D_ALT_DEPTH = 0x0,
- ARRAY_2D_DEPTH = 0x1,
-} DepthArray;
-typedef enum ENUM_NUM_SIMD_PER_CU {
- NUM_SIMD_PER_CU = 0x4,
-} ENUM_NUM_SIMD_PER_CU;
-typedef enum MEM_PWR_FORCE_CTRL {
- NO_FORCE_REQUEST = 0x0,
- FORCE_LIGHT_SLEEP_REQUEST = 0x1,
- FORCE_DEEP_SLEEP_REQUEST = 0x2,
- FORCE_SHUT_DOWN_REQUEST = 0x3,
-} MEM_PWR_FORCE_CTRL;
-typedef enum MEM_PWR_FORCE_CTRL2 {
- NO_FORCE_REQ = 0x0,
- FORCE_LIGHT_SLEEP_REQ = 0x1,
-} MEM_PWR_FORCE_CTRL2;
-typedef enum MEM_PWR_DIS_CTRL {
- ENABLE_MEM_PWR_CTRL = 0x0,
- DISABLE_MEM_PWR_CTRL = 0x1,
-} MEM_PWR_DIS_CTRL;
-typedef enum MEM_PWR_SEL_CTRL {
- DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
- DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
- DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
-} MEM_PWR_SEL_CTRL;
-typedef enum MEM_PWR_SEL_CTRL2 {
- DYNAMIC_DEEP_SLEEP_EN = 0x0,
- DYNAMIC_LIGHT_SLEEP_EN = 0x1,
-} MEM_PWR_SEL_CTRL2;
-
-#endif /* UVD_5_0_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_enum.h
deleted file mode 100644
index ecf47ba55..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_enum.h
+++ /dev/null
@@ -1,1081 +0,0 @@
-/*
- * UVD_6_0 Register documentation
- *
- * Copyright (C) 2014 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef UVD_6_0_ENUM_H
-#define UVD_6_0_ENUM_H
-
-typedef enum UVDFirmwareCommand {
- UVDFC_FENCE = 0x0,
- UVDFC_TRAP = 0x1,
- UVDFC_DECODED_ADDR = 0x2,
- UVDFC_MBLOCK_ADDR = 0x3,
- UVDFC_ITBUF_ADDR = 0x4,
- UVDFC_DISPLAY_ADDR = 0x5,
- UVDFC_EOD = 0x6,
- UVDFC_DISPLAY_PITCH = 0x7,
- UVDFC_DISPLAY_TILING = 0x8,
- UVDFC_BITSTREAM_ADDR = 0x9,
- UVDFC_BITSTREAM_SIZE = 0xa,
-} UVDFirmwareCommand;
-typedef enum DebugBlockId {
- DBG_BLOCK_ID_RESERVED = 0x0,
- DBG_BLOCK_ID_DBG = 0x1,
- DBG_BLOCK_ID_VMC = 0x2,
- DBG_BLOCK_ID_PDMA = 0x3,
- DBG_BLOCK_ID_CG = 0x4,
- DBG_BLOCK_ID_SRBM = 0x5,
- DBG_BLOCK_ID_GRBM = 0x6,
- DBG_BLOCK_ID_RLC = 0x7,
- DBG_BLOCK_ID_CSC = 0x8,
- DBG_BLOCK_ID_SEM = 0x9,
- DBG_BLOCK_ID_IH = 0xa,
- DBG_BLOCK_ID_SC = 0xb,
- DBG_BLOCK_ID_SQ = 0xc,
- DBG_BLOCK_ID_UVDU = 0xd,
- DBG_BLOCK_ID_SQA = 0xe,
- DBG_BLOCK_ID_SDMA0 = 0xf,
- DBG_BLOCK_ID_SDMA1 = 0x10,
- DBG_BLOCK_ID_SPIM = 0x11,
- DBG_BLOCK_ID_GDS = 0x12,
- DBG_BLOCK_ID_VC0 = 0x13,
- DBG_BLOCK_ID_VC1 = 0x14,
- DBG_BLOCK_ID_PA0 = 0x15,
- DBG_BLOCK_ID_PA1 = 0x16,
- DBG_BLOCK_ID_CP0 = 0x17,
- DBG_BLOCK_ID_CP1 = 0x18,
- DBG_BLOCK_ID_CP2 = 0x19,
- DBG_BLOCK_ID_XBR = 0x1a,
- DBG_BLOCK_ID_UVDM = 0x1b,
- DBG_BLOCK_ID_VGT0 = 0x1c,
- DBG_BLOCK_ID_VGT1 = 0x1d,
- DBG_BLOCK_ID_IA = 0x1e,
- DBG_BLOCK_ID_SXM0 = 0x1f,
- DBG_BLOCK_ID_SXM1 = 0x20,
- DBG_BLOCK_ID_SCT0 = 0x21,
- DBG_BLOCK_ID_SCT1 = 0x22,
- DBG_BLOCK_ID_SPM0 = 0x23,
- DBG_BLOCK_ID_SPM1 = 0x24,
- DBG_BLOCK_ID_UNUSED0 = 0x25,
- DBG_BLOCK_ID_UNUSED1 = 0x26,
- DBG_BLOCK_ID_TCAA = 0x27,
- DBG_BLOCK_ID_TCAB = 0x28,
- DBG_BLOCK_ID_TCCA = 0x29,
- DBG_BLOCK_ID_TCCB = 0x2a,
- DBG_BLOCK_ID_MCC0 = 0x2b,
- DBG_BLOCK_ID_MCC1 = 0x2c,
- DBG_BLOCK_ID_MCC2 = 0x2d,
- DBG_BLOCK_ID_MCC3 = 0x2e,
- DBG_BLOCK_ID_SXS0 = 0x2f,
- DBG_BLOCK_ID_SXS1 = 0x30,
- DBG_BLOCK_ID_SXS2 = 0x31,
- DBG_BLOCK_ID_SXS3 = 0x32,
- DBG_BLOCK_ID_SXS4 = 0x33,
- DBG_BLOCK_ID_SXS5 = 0x34,
- DBG_BLOCK_ID_SXS6 = 0x35,
- DBG_BLOCK_ID_SXS7 = 0x36,
- DBG_BLOCK_ID_SXS8 = 0x37,
- DBG_BLOCK_ID_SXS9 = 0x38,
- DBG_BLOCK_ID_BCI0 = 0x39,
- DBG_BLOCK_ID_BCI1 = 0x3a,
- DBG_BLOCK_ID_BCI2 = 0x3b,
- DBG_BLOCK_ID_BCI3 = 0x3c,
- DBG_BLOCK_ID_MCB = 0x3d,
- DBG_BLOCK_ID_UNUSED6 = 0x3e,
- DBG_BLOCK_ID_SQA00 = 0x3f,
- DBG_BLOCK_ID_SQA01 = 0x40,
- DBG_BLOCK_ID_SQA02 = 0x41,
- DBG_BLOCK_ID_SQA10 = 0x42,
- DBG_BLOCK_ID_SQA11 = 0x43,
- DBG_BLOCK_ID_SQA12 = 0x44,
- DBG_BLOCK_ID_UNUSED7 = 0x45,
- DBG_BLOCK_ID_UNUSED8 = 0x46,
- DBG_BLOCK_ID_SQB00 = 0x47,
- DBG_BLOCK_ID_SQB01 = 0x48,
- DBG_BLOCK_ID_SQB10 = 0x49,
- DBG_BLOCK_ID_SQB11 = 0x4a,
- DBG_BLOCK_ID_SQ00 = 0x4b,
- DBG_BLOCK_ID_SQ01 = 0x4c,
- DBG_BLOCK_ID_SQ10 = 0x4d,
- DBG_BLOCK_ID_SQ11 = 0x4e,
- DBG_BLOCK_ID_CB00 = 0x4f,
- DBG_BLOCK_ID_CB01 = 0x50,
- DBG_BLOCK_ID_CB02 = 0x51,
- DBG_BLOCK_ID_CB03 = 0x52,
- DBG_BLOCK_ID_CB04 = 0x53,
- DBG_BLOCK_ID_UNUSED9 = 0x54,
- DBG_BLOCK_ID_UNUSED10 = 0x55,
- DBG_BLOCK_ID_UNUSED11 = 0x56,
- DBG_BLOCK_ID_CB10 = 0x57,
- DBG_BLOCK_ID_CB11 = 0x58,
- DBG_BLOCK_ID_CB12 = 0x59,
- DBG_BLOCK_ID_CB13 = 0x5a,
- DBG_BLOCK_ID_CB14 = 0x5b,
- DBG_BLOCK_ID_UNUSED12 = 0x5c,
- DBG_BLOCK_ID_UNUSED13 = 0x5d,
- DBG_BLOCK_ID_UNUSED14 = 0x5e,
- DBG_BLOCK_ID_TCP0 = 0x5f,
- DBG_BLOCK_ID_TCP1 = 0x60,
- DBG_BLOCK_ID_TCP2 = 0x61,
- DBG_BLOCK_ID_TCP3 = 0x62,
- DBG_BLOCK_ID_TCP4 = 0x63,
- DBG_BLOCK_ID_TCP5 = 0x64,
- DBG_BLOCK_ID_TCP6 = 0x65,
- DBG_BLOCK_ID_TCP7 = 0x66,
- DBG_BLOCK_ID_TCP8 = 0x67,
- DBG_BLOCK_ID_TCP9 = 0x68,
- DBG_BLOCK_ID_TCP10 = 0x69,
- DBG_BLOCK_ID_TCP11 = 0x6a,
- DBG_BLOCK_ID_TCP12 = 0x6b,
- DBG_BLOCK_ID_TCP13 = 0x6c,
- DBG_BLOCK_ID_TCP14 = 0x6d,
- DBG_BLOCK_ID_TCP15 = 0x6e,
- DBG_BLOCK_ID_TCP16 = 0x6f,
- DBG_BLOCK_ID_TCP17 = 0x70,
- DBG_BLOCK_ID_TCP18 = 0x71,
- DBG_BLOCK_ID_TCP19 = 0x72,
- DBG_BLOCK_ID_TCP20 = 0x73,
- DBG_BLOCK_ID_TCP21 = 0x74,
- DBG_BLOCK_ID_TCP22 = 0x75,
- DBG_BLOCK_ID_TCP23 = 0x76,
- DBG_BLOCK_ID_TCP_RESERVED0 = 0x77,
- DBG_BLOCK_ID_TCP_RESERVED1 = 0x78,
- DBG_BLOCK_ID_TCP_RESERVED2 = 0x79,
- DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a,
- DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b,
- DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c,
- DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d,
- DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e,
- DBG_BLOCK_ID_DB00 = 0x7f,
- DBG_BLOCK_ID_DB01 = 0x80,
- DBG_BLOCK_ID_DB02 = 0x81,
- DBG_BLOCK_ID_DB03 = 0x82,
- DBG_BLOCK_ID_DB04 = 0x83,
- DBG_BLOCK_ID_UNUSED15 = 0x84,
- DBG_BLOCK_ID_UNUSED16 = 0x85,
- DBG_BLOCK_ID_UNUSED17 = 0x86,
- DBG_BLOCK_ID_DB10 = 0x87,
- DBG_BLOCK_ID_DB11 = 0x88,
- DBG_BLOCK_ID_DB12 = 0x89,
- DBG_BLOCK_ID_DB13 = 0x8a,
- DBG_BLOCK_ID_DB14 = 0x8b,
- DBG_BLOCK_ID_UNUSED18 = 0x8c,
- DBG_BLOCK_ID_UNUSED19 = 0x8d,
- DBG_BLOCK_ID_UNUSED20 = 0x8e,
- DBG_BLOCK_ID_TCC0 = 0x8f,
- DBG_BLOCK_ID_TCC1 = 0x90,
- DBG_BLOCK_ID_TCC2 = 0x91,
- DBG_BLOCK_ID_TCC3 = 0x92,
- DBG_BLOCK_ID_TCC4 = 0x93,
- DBG_BLOCK_ID_TCC5 = 0x94,
- DBG_BLOCK_ID_TCC6 = 0x95,
- DBG_BLOCK_ID_TCC7 = 0x96,
- DBG_BLOCK_ID_SPS00 = 0x97,
- DBG_BLOCK_ID_SPS01 = 0x98,
- DBG_BLOCK_ID_SPS02 = 0x99,
- DBG_BLOCK_ID_SPS10 = 0x9a,
- DBG_BLOCK_ID_SPS11 = 0x9b,
- DBG_BLOCK_ID_SPS12 = 0x9c,
- DBG_BLOCK_ID_UNUSED21 = 0x9d,
- DBG_BLOCK_ID_UNUSED22 = 0x9e,
- DBG_BLOCK_ID_TA00 = 0x9f,
- DBG_BLOCK_ID_TA01 = 0xa0,
- DBG_BLOCK_ID_TA02 = 0xa1,
- DBG_BLOCK_ID_TA03 = 0xa2,
- DBG_BLOCK_ID_TA04 = 0xa3,
- DBG_BLOCK_ID_TA05 = 0xa4,
- DBG_BLOCK_ID_TA06 = 0xa5,
- DBG_BLOCK_ID_TA07 = 0xa6,
- DBG_BLOCK_ID_TA08 = 0xa7,
- DBG_BLOCK_ID_TA09 = 0xa8,
- DBG_BLOCK_ID_TA0A = 0xa9,
- DBG_BLOCK_ID_TA0B = 0xaa,
- DBG_BLOCK_ID_UNUSED23 = 0xab,
- DBG_BLOCK_ID_UNUSED24 = 0xac,
- DBG_BLOCK_ID_UNUSED25 = 0xad,
- DBG_BLOCK_ID_UNUSED26 = 0xae,
- DBG_BLOCK_ID_TA10 = 0xaf,
- DBG_BLOCK_ID_TA11 = 0xb0,
- DBG_BLOCK_ID_TA12 = 0xb1,
- DBG_BLOCK_ID_TA13 = 0xb2,
- DBG_BLOCK_ID_TA14 = 0xb3,
- DBG_BLOCK_ID_TA15 = 0xb4,
- DBG_BLOCK_ID_TA16 = 0xb5,
- DBG_BLOCK_ID_TA17 = 0xb6,
- DBG_BLOCK_ID_TA18 = 0xb7,
- DBG_BLOCK_ID_TA19 = 0xb8,
- DBG_BLOCK_ID_TA1A = 0xb9,
- DBG_BLOCK_ID_TA1B = 0xba,
- DBG_BLOCK_ID_UNUSED27 = 0xbb,
- DBG_BLOCK_ID_UNUSED28 = 0xbc,
- DBG_BLOCK_ID_UNUSED29 = 0xbd,
- DBG_BLOCK_ID_UNUSED30 = 0xbe,
- DBG_BLOCK_ID_TD00 = 0xbf,
- DBG_BLOCK_ID_TD01 = 0xc0,
- DBG_BLOCK_ID_TD02 = 0xc1,
- DBG_BLOCK_ID_TD03 = 0xc2,
- DBG_BLOCK_ID_TD04 = 0xc3,
- DBG_BLOCK_ID_TD05 = 0xc4,
- DBG_BLOCK_ID_TD06 = 0xc5,
- DBG_BLOCK_ID_TD07 = 0xc6,
- DBG_BLOCK_ID_TD08 = 0xc7,
- DBG_BLOCK_ID_TD09 = 0xc8,
- DBG_BLOCK_ID_TD0A = 0xc9,
- DBG_BLOCK_ID_TD0B = 0xca,
- DBG_BLOCK_ID_UNUSED31 = 0xcb,
- DBG_BLOCK_ID_UNUSED32 = 0xcc,
- DBG_BLOCK_ID_UNUSED33 = 0xcd,
- DBG_BLOCK_ID_UNUSED34 = 0xce,
- DBG_BLOCK_ID_TD10 = 0xcf,
- DBG_BLOCK_ID_TD11 = 0xd0,
- DBG_BLOCK_ID_TD12 = 0xd1,
- DBG_BLOCK_ID_TD13 = 0xd2,
- DBG_BLOCK_ID_TD14 = 0xd3,
- DBG_BLOCK_ID_TD15 = 0xd4,
- DBG_BLOCK_ID_TD16 = 0xd5,
- DBG_BLOCK_ID_TD17 = 0xd6,
- DBG_BLOCK_ID_TD18 = 0xd7,
- DBG_BLOCK_ID_TD19 = 0xd8,
- DBG_BLOCK_ID_TD1A = 0xd9,
- DBG_BLOCK_ID_TD1B = 0xda,
- DBG_BLOCK_ID_UNUSED35 = 0xdb,
- DBG_BLOCK_ID_UNUSED36 = 0xdc,
- DBG_BLOCK_ID_UNUSED37 = 0xdd,
- DBG_BLOCK_ID_UNUSED38 = 0xde,
- DBG_BLOCK_ID_LDS00 = 0xdf,
- DBG_BLOCK_ID_LDS01 = 0xe0,
- DBG_BLOCK_ID_LDS02 = 0xe1,
- DBG_BLOCK_ID_LDS03 = 0xe2,
- DBG_BLOCK_ID_LDS04 = 0xe3,
- DBG_BLOCK_ID_LDS05 = 0xe4,
- DBG_BLOCK_ID_LDS06 = 0xe5,
- DBG_BLOCK_ID_LDS07 = 0xe6,
- DBG_BLOCK_ID_LDS08 = 0xe7,
- DBG_BLOCK_ID_LDS09 = 0xe8,
- DBG_BLOCK_ID_LDS0A = 0xe9,
- DBG_BLOCK_ID_LDS0B = 0xea,
- DBG_BLOCK_ID_UNUSED39 = 0xeb,
- DBG_BLOCK_ID_UNUSED40 = 0xec,
- DBG_BLOCK_ID_UNUSED41 = 0xed,
- DBG_BLOCK_ID_UNUSED42 = 0xee,
- DBG_BLOCK_ID_LDS10 = 0xef,
- DBG_BLOCK_ID_LDS11 = 0xf0,
- DBG_BLOCK_ID_LDS12 = 0xf1,
- DBG_BLOCK_ID_LDS13 = 0xf2,
- DBG_BLOCK_ID_LDS14 = 0xf3,
- DBG_BLOCK_ID_LDS15 = 0xf4,
- DBG_BLOCK_ID_LDS16 = 0xf5,
- DBG_BLOCK_ID_LDS17 = 0xf6,
- DBG_BLOCK_ID_LDS18 = 0xf7,
- DBG_BLOCK_ID_LDS19 = 0xf8,
- DBG_BLOCK_ID_LDS1A = 0xf9,
- DBG_BLOCK_ID_LDS1B = 0xfa,
- DBG_BLOCK_ID_UNUSED43 = 0xfb,
- DBG_BLOCK_ID_UNUSED44 = 0xfc,
- DBG_BLOCK_ID_UNUSED45 = 0xfd,
- DBG_BLOCK_ID_UNUSED46 = 0xfe,
-} DebugBlockId;
-typedef enum DebugBlockId_BY2 {
- DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
- DBG_BLOCK_ID_VMC_BY2 = 0x1,
- DBG_BLOCK_ID_UNUSED0_BY2 = 0x2,
- DBG_BLOCK_ID_GRBM_BY2 = 0x3,
- DBG_BLOCK_ID_CSC_BY2 = 0x4,
- DBG_BLOCK_ID_IH_BY2 = 0x5,
- DBG_BLOCK_ID_SQ_BY2 = 0x6,
- DBG_BLOCK_ID_UVD_BY2 = 0x7,
- DBG_BLOCK_ID_SDMA0_BY2 = 0x8,
- DBG_BLOCK_ID_SPIM_BY2 = 0x9,
- DBG_BLOCK_ID_VC0_BY2 = 0xa,
- DBG_BLOCK_ID_PA_BY2 = 0xb,
- DBG_BLOCK_ID_CP0_BY2 = 0xc,
- DBG_BLOCK_ID_CP2_BY2 = 0xd,
- DBG_BLOCK_ID_PC0_BY2 = 0xe,
- DBG_BLOCK_ID_BCI0_BY2 = 0xf,
- DBG_BLOCK_ID_SXM0_BY2 = 0x10,
- DBG_BLOCK_ID_SCT0_BY2 = 0x11,
- DBG_BLOCK_ID_SPM0_BY2 = 0x12,
- DBG_BLOCK_ID_BCI2_BY2 = 0x13,
- DBG_BLOCK_ID_TCA_BY2 = 0x14,
- DBG_BLOCK_ID_TCCA_BY2 = 0x15,
- DBG_BLOCK_ID_MCC_BY2 = 0x16,
- DBG_BLOCK_ID_MCC2_BY2 = 0x17,
- DBG_BLOCK_ID_MCD_BY2 = 0x18,
- DBG_BLOCK_ID_MCD2_BY2 = 0x19,
- DBG_BLOCK_ID_MCD4_BY2 = 0x1a,
- DBG_BLOCK_ID_MCB_BY2 = 0x1b,
- DBG_BLOCK_ID_SQA_BY2 = 0x1c,
- DBG_BLOCK_ID_SQA02_BY2 = 0x1d,
- DBG_BLOCK_ID_SQA11_BY2 = 0x1e,
- DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f,
- DBG_BLOCK_ID_SQB_BY2 = 0x20,
- DBG_BLOCK_ID_SQB10_BY2 = 0x21,
- DBG_BLOCK_ID_UNUSED10_BY2 = 0x22,
- DBG_BLOCK_ID_UNUSED12_BY2 = 0x23,
- DBG_BLOCK_ID_CB_BY2 = 0x24,
- DBG_BLOCK_ID_CB02_BY2 = 0x25,
- DBG_BLOCK_ID_CB10_BY2 = 0x26,
- DBG_BLOCK_ID_CB12_BY2 = 0x27,
- DBG_BLOCK_ID_SXS_BY2 = 0x28,
- DBG_BLOCK_ID_SXS2_BY2 = 0x29,
- DBG_BLOCK_ID_SXS4_BY2 = 0x2a,
- DBG_BLOCK_ID_SXS6_BY2 = 0x2b,
- DBG_BLOCK_ID_DB_BY2 = 0x2c,
- DBG_BLOCK_ID_DB02_BY2 = 0x2d,
- DBG_BLOCK_ID_DB10_BY2 = 0x2e,
- DBG_BLOCK_ID_DB12_BY2 = 0x2f,
- DBG_BLOCK_ID_TCP_BY2 = 0x30,
- DBG_BLOCK_ID_TCP2_BY2 = 0x31,
- DBG_BLOCK_ID_TCP4_BY2 = 0x32,
- DBG_BLOCK_ID_TCP6_BY2 = 0x33,
- DBG_BLOCK_ID_TCP8_BY2 = 0x34,
- DBG_BLOCK_ID_TCP10_BY2 = 0x35,
- DBG_BLOCK_ID_TCP12_BY2 = 0x36,
- DBG_BLOCK_ID_TCP14_BY2 = 0x37,
- DBG_BLOCK_ID_TCP16_BY2 = 0x38,
- DBG_BLOCK_ID_TCP18_BY2 = 0x39,
- DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
- DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
- DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
- DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
- DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
- DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
- DBG_BLOCK_ID_TCC_BY2 = 0x40,
- DBG_BLOCK_ID_TCC2_BY2 = 0x41,
- DBG_BLOCK_ID_TCC4_BY2 = 0x42,
- DBG_BLOCK_ID_TCC6_BY2 = 0x43,
- DBG_BLOCK_ID_SPS_BY2 = 0x44,
- DBG_BLOCK_ID_SPS02_BY2 = 0x45,
- DBG_BLOCK_ID_SPS11_BY2 = 0x46,
- DBG_BLOCK_ID_UNUSED14_BY2 = 0x47,
- DBG_BLOCK_ID_TA_BY2 = 0x48,
- DBG_BLOCK_ID_TA02_BY2 = 0x49,
- DBG_BLOCK_ID_TA04_BY2 = 0x4a,
- DBG_BLOCK_ID_TA06_BY2 = 0x4b,
- DBG_BLOCK_ID_TA08_BY2 = 0x4c,
- DBG_BLOCK_ID_TA0A_BY2 = 0x4d,
- DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e,
- DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f,
- DBG_BLOCK_ID_TA10_BY2 = 0x50,
- DBG_BLOCK_ID_TA12_BY2 = 0x51,
- DBG_BLOCK_ID_TA14_BY2 = 0x52,
- DBG_BLOCK_ID_TA16_BY2 = 0x53,
- DBG_BLOCK_ID_TA18_BY2 = 0x54,
- DBG_BLOCK_ID_TA1A_BY2 = 0x55,
- DBG_BLOCK_ID_UNUSED24_BY2 = 0x56,
- DBG_BLOCK_ID_UNUSED26_BY2 = 0x57,
- DBG_BLOCK_ID_TD_BY2 = 0x58,
- DBG_BLOCK_ID_TD02_BY2 = 0x59,
- DBG_BLOCK_ID_TD04_BY2 = 0x5a,
- DBG_BLOCK_ID_TD06_BY2 = 0x5b,
- DBG_BLOCK_ID_TD08_BY2 = 0x5c,
- DBG_BLOCK_ID_TD0A_BY2 = 0x5d,
- DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e,
- DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f,
- DBG_BLOCK_ID_TD10_BY2 = 0x60,
- DBG_BLOCK_ID_TD12_BY2 = 0x61,
- DBG_BLOCK_ID_TD14_BY2 = 0x62,
- DBG_BLOCK_ID_TD16_BY2 = 0x63,
- DBG_BLOCK_ID_TD18_BY2 = 0x64,
- DBG_BLOCK_ID_TD1A_BY2 = 0x65,
- DBG_BLOCK_ID_UNUSED32_BY2 = 0x66,
- DBG_BLOCK_ID_UNUSED34_BY2 = 0x67,
- DBG_BLOCK_ID_LDS_BY2 = 0x68,
- DBG_BLOCK_ID_LDS02_BY2 = 0x69,
- DBG_BLOCK_ID_LDS04_BY2 = 0x6a,
- DBG_BLOCK_ID_LDS06_BY2 = 0x6b,
- DBG_BLOCK_ID_LDS08_BY2 = 0x6c,
- DBG_BLOCK_ID_LDS0A_BY2 = 0x6d,
- DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e,
- DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f,
- DBG_BLOCK_ID_LDS10_BY2 = 0x70,
- DBG_BLOCK_ID_LDS12_BY2 = 0x71,
- DBG_BLOCK_ID_LDS14_BY2 = 0x72,
- DBG_BLOCK_ID_LDS16_BY2 = 0x73,
- DBG_BLOCK_ID_LDS18_BY2 = 0x74,
- DBG_BLOCK_ID_LDS1A_BY2 = 0x75,
- DBG_BLOCK_ID_UNUSED40_BY2 = 0x76,
- DBG_BLOCK_ID_UNUSED42_BY2 = 0x77,
-} DebugBlockId_BY2;
-typedef enum DebugBlockId_BY4 {
- DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
- DBG_BLOCK_ID_UNUSED0_BY4 = 0x1,
- DBG_BLOCK_ID_CSC_BY4 = 0x2,
- DBG_BLOCK_ID_SQ_BY4 = 0x3,
- DBG_BLOCK_ID_SDMA0_BY4 = 0x4,
- DBG_BLOCK_ID_VC0_BY4 = 0x5,
- DBG_BLOCK_ID_CP0_BY4 = 0x6,
- DBG_BLOCK_ID_UNUSED1_BY4 = 0x7,
- DBG_BLOCK_ID_SXM0_BY4 = 0x8,
- DBG_BLOCK_ID_SPM0_BY4 = 0x9,
- DBG_BLOCK_ID_TCAA_BY4 = 0xa,
- DBG_BLOCK_ID_MCC_BY4 = 0xb,
- DBG_BLOCK_ID_MCD_BY4 = 0xc,
- DBG_BLOCK_ID_MCD4_BY4 = 0xd,
- DBG_BLOCK_ID_SQA_BY4 = 0xe,
- DBG_BLOCK_ID_SQA11_BY4 = 0xf,
- DBG_BLOCK_ID_SQB_BY4 = 0x10,
- DBG_BLOCK_ID_UNUSED10_BY4 = 0x11,
- DBG_BLOCK_ID_CB_BY4 = 0x12,
- DBG_BLOCK_ID_CB10_BY4 = 0x13,
- DBG_BLOCK_ID_SXS_BY4 = 0x14,
- DBG_BLOCK_ID_SXS4_BY4 = 0x15,
- DBG_BLOCK_ID_DB_BY4 = 0x16,
- DBG_BLOCK_ID_DB10_BY4 = 0x17,
- DBG_BLOCK_ID_TCP_BY4 = 0x18,
- DBG_BLOCK_ID_TCP4_BY4 = 0x19,
- DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
- DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
- DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
- DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
- DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
- DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
- DBG_BLOCK_ID_TCC_BY4 = 0x20,
- DBG_BLOCK_ID_TCC4_BY4 = 0x21,
- DBG_BLOCK_ID_SPS_BY4 = 0x22,
- DBG_BLOCK_ID_SPS11_BY4 = 0x23,
- DBG_BLOCK_ID_TA_BY4 = 0x24,
- DBG_BLOCK_ID_TA04_BY4 = 0x25,
- DBG_BLOCK_ID_TA08_BY4 = 0x26,
- DBG_BLOCK_ID_UNUSED20_BY4 = 0x27,
- DBG_BLOCK_ID_TA10_BY4 = 0x28,
- DBG_BLOCK_ID_TA14_BY4 = 0x29,
- DBG_BLOCK_ID_TA18_BY4 = 0x2a,
- DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b,
- DBG_BLOCK_ID_TD_BY4 = 0x2c,
- DBG_BLOCK_ID_TD04_BY4 = 0x2d,
- DBG_BLOCK_ID_TD08_BY4 = 0x2e,
- DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f,
- DBG_BLOCK_ID_TD10_BY4 = 0x30,
- DBG_BLOCK_ID_TD14_BY4 = 0x31,
- DBG_BLOCK_ID_TD18_BY4 = 0x32,
- DBG_BLOCK_ID_UNUSED32_BY4 = 0x33,
- DBG_BLOCK_ID_LDS_BY4 = 0x34,
- DBG_BLOCK_ID_LDS04_BY4 = 0x35,
- DBG_BLOCK_ID_LDS08_BY4 = 0x36,
- DBG_BLOCK_ID_UNUSED36_BY4 = 0x37,
- DBG_BLOCK_ID_LDS10_BY4 = 0x38,
- DBG_BLOCK_ID_LDS14_BY4 = 0x39,
- DBG_BLOCK_ID_LDS18_BY4 = 0x3a,
- DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b,
-} DebugBlockId_BY4;
-typedef enum DebugBlockId_BY8 {
- DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
- DBG_BLOCK_ID_CSC_BY8 = 0x1,
- DBG_BLOCK_ID_SDMA0_BY8 = 0x2,
- DBG_BLOCK_ID_CP0_BY8 = 0x3,
- DBG_BLOCK_ID_SXM0_BY8 = 0x4,
- DBG_BLOCK_ID_TCA_BY8 = 0x5,
- DBG_BLOCK_ID_MCD_BY8 = 0x6,
- DBG_BLOCK_ID_SQA_BY8 = 0x7,
- DBG_BLOCK_ID_SQB_BY8 = 0x8,
- DBG_BLOCK_ID_CB_BY8 = 0x9,
- DBG_BLOCK_ID_SXS_BY8 = 0xa,
- DBG_BLOCK_ID_DB_BY8 = 0xb,
- DBG_BLOCK_ID_TCP_BY8 = 0xc,
- DBG_BLOCK_ID_TCP8_BY8 = 0xd,
- DBG_BLOCK_ID_TCP16_BY8 = 0xe,
- DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
- DBG_BLOCK_ID_TCC_BY8 = 0x10,
- DBG_BLOCK_ID_SPS_BY8 = 0x11,
- DBG_BLOCK_ID_TA_BY8 = 0x12,
- DBG_BLOCK_ID_TA08_BY8 = 0x13,
- DBG_BLOCK_ID_TA10_BY8 = 0x14,
- DBG_BLOCK_ID_TA18_BY8 = 0x15,
- DBG_BLOCK_ID_TD_BY8 = 0x16,
- DBG_BLOCK_ID_TD08_BY8 = 0x17,
- DBG_BLOCK_ID_TD10_BY8 = 0x18,
- DBG_BLOCK_ID_TD18_BY8 = 0x19,
- DBG_BLOCK_ID_LDS_BY8 = 0x1a,
- DBG_BLOCK_ID_LDS08_BY8 = 0x1b,
- DBG_BLOCK_ID_LDS10_BY8 = 0x1c,
- DBG_BLOCK_ID_LDS18_BY8 = 0x1d,
-} DebugBlockId_BY8;
-typedef enum DebugBlockId_BY16 {
- DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
- DBG_BLOCK_ID_SDMA0_BY16 = 0x1,
- DBG_BLOCK_ID_SXM_BY16 = 0x2,
- DBG_BLOCK_ID_MCD_BY16 = 0x3,
- DBG_BLOCK_ID_SQB_BY16 = 0x4,
- DBG_BLOCK_ID_SXS_BY16 = 0x5,
- DBG_BLOCK_ID_TCP_BY16 = 0x6,
- DBG_BLOCK_ID_TCP16_BY16 = 0x7,
- DBG_BLOCK_ID_TCC_BY16 = 0x8,
- DBG_BLOCK_ID_TA_BY16 = 0x9,
- DBG_BLOCK_ID_TA10_BY16 = 0xa,
- DBG_BLOCK_ID_TD_BY16 = 0xb,
- DBG_BLOCK_ID_TD10_BY16 = 0xc,
- DBG_BLOCK_ID_LDS_BY16 = 0xd,
- DBG_BLOCK_ID_LDS10_BY16 = 0xe,
-} DebugBlockId_BY16;
-typedef enum SurfaceEndian {
- ENDIAN_NONE = 0x0,
- ENDIAN_8IN16 = 0x1,
- ENDIAN_8IN32 = 0x2,
- ENDIAN_8IN64 = 0x3,
-} SurfaceEndian;
-typedef enum ArrayMode {
- ARRAY_LINEAR_GENERAL = 0x0,
- ARRAY_LINEAR_ALIGNED = 0x1,
- ARRAY_1D_TILED_THIN1 = 0x2,
- ARRAY_1D_TILED_THICK = 0x3,
- ARRAY_2D_TILED_THIN1 = 0x4,
- ARRAY_PRT_TILED_THIN1 = 0x5,
- ARRAY_PRT_2D_TILED_THIN1 = 0x6,
- ARRAY_2D_TILED_THICK = 0x7,
- ARRAY_2D_TILED_XTHICK = 0x8,
- ARRAY_PRT_TILED_THICK = 0x9,
- ARRAY_PRT_2D_TILED_THICK = 0xa,
- ARRAY_PRT_3D_TILED_THIN1 = 0xb,
- ARRAY_3D_TILED_THIN1 = 0xc,
- ARRAY_3D_TILED_THICK = 0xd,
- ARRAY_3D_TILED_XTHICK = 0xe,
- ARRAY_PRT_3D_TILED_THICK = 0xf,
-} ArrayMode;
-typedef enum PipeTiling {
- CONFIG_1_PIPE = 0x0,
- CONFIG_2_PIPE = 0x1,
- CONFIG_4_PIPE = 0x2,
- CONFIG_8_PIPE = 0x3,
-} PipeTiling;
-typedef enum BankTiling {
- CONFIG_4_BANK = 0x0,
- CONFIG_8_BANK = 0x1,
-} BankTiling;
-typedef enum GroupInterleave {
- CONFIG_256B_GROUP = 0x0,
- CONFIG_512B_GROUP = 0x1,
-} GroupInterleave;
-typedef enum RowTiling {
- CONFIG_1KB_ROW = 0x0,
- CONFIG_2KB_ROW = 0x1,
- CONFIG_4KB_ROW = 0x2,
- CONFIG_8KB_ROW = 0x3,
- CONFIG_1KB_ROW_OPT = 0x4,
- CONFIG_2KB_ROW_OPT = 0x5,
- CONFIG_4KB_ROW_OPT = 0x6,
- CONFIG_8KB_ROW_OPT = 0x7,
-} RowTiling;
-typedef enum BankSwapBytes {
- CONFIG_128B_SWAPS = 0x0,
- CONFIG_256B_SWAPS = 0x1,
- CONFIG_512B_SWAPS = 0x2,
- CONFIG_1KB_SWAPS = 0x3,
-} BankSwapBytes;
-typedef enum SampleSplitBytes {
- CONFIG_1KB_SPLIT = 0x0,
- CONFIG_2KB_SPLIT = 0x1,
- CONFIG_4KB_SPLIT = 0x2,
- CONFIG_8KB_SPLIT = 0x3,
-} SampleSplitBytes;
-typedef enum NumPipes {
- ADDR_CONFIG_1_PIPE = 0x0,
- ADDR_CONFIG_2_PIPE = 0x1,
- ADDR_CONFIG_4_PIPE = 0x2,
- ADDR_CONFIG_8_PIPE = 0x3,
-} NumPipes;
-typedef enum PipeInterleaveSize {
- ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
- ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
-} PipeInterleaveSize;
-typedef enum BankInterleaveSize {
- ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
- ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
- ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
- ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
-} BankInterleaveSize;
-typedef enum NumShaderEngines {
- ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
- ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
-} NumShaderEngines;
-typedef enum ShaderEngineTileSize {
- ADDR_CONFIG_SE_TILE_16 = 0x0,
- ADDR_CONFIG_SE_TILE_32 = 0x1,
-} ShaderEngineTileSize;
-typedef enum NumGPUs {
- ADDR_CONFIG_1_GPU = 0x0,
- ADDR_CONFIG_2_GPU = 0x1,
- ADDR_CONFIG_4_GPU = 0x2,
-} NumGPUs;
-typedef enum MultiGPUTileSize {
- ADDR_CONFIG_GPU_TILE_16 = 0x0,
- ADDR_CONFIG_GPU_TILE_32 = 0x1,
- ADDR_CONFIG_GPU_TILE_64 = 0x2,
- ADDR_CONFIG_GPU_TILE_128 = 0x3,
-} MultiGPUTileSize;
-typedef enum RowSize {
- ADDR_CONFIG_1KB_ROW = 0x0,
- ADDR_CONFIG_2KB_ROW = 0x1,
- ADDR_CONFIG_4KB_ROW = 0x2,
-} RowSize;
-typedef enum NumLowerPipes {
- ADDR_CONFIG_1_LOWER_PIPES = 0x0,
- ADDR_CONFIG_2_LOWER_PIPES = 0x1,
-} NumLowerPipes;
-typedef enum ColorTransform {
- DCC_CT_AUTO = 0x0,
- DCC_CT_NONE = 0x1,
- ABGR_TO_A_BG_G_RB = 0x2,
- BGRA_TO_BG_G_RB_A = 0x3,
-} ColorTransform;
-typedef enum CompareRef {
- REF_NEVER = 0x0,
- REF_LESS = 0x1,
- REF_EQUAL = 0x2,
- REF_LEQUAL = 0x3,
- REF_GREATER = 0x4,
- REF_NOTEQUAL = 0x5,
- REF_GEQUAL = 0x6,
- REF_ALWAYS = 0x7,
-} CompareRef;
-typedef enum ReadSize {
- READ_256_BITS = 0x0,
- READ_512_BITS = 0x1,
-} ReadSize;
-typedef enum DepthFormat {
- DEPTH_INVALID = 0x0,
- DEPTH_16 = 0x1,
- DEPTH_X8_24 = 0x2,
- DEPTH_8_24 = 0x3,
- DEPTH_X8_24_FLOAT = 0x4,
- DEPTH_8_24_FLOAT = 0x5,
- DEPTH_32_FLOAT = 0x6,
- DEPTH_X24_8_32_FLOAT = 0x7,
-} DepthFormat;
-typedef enum ZFormat {
- Z_INVALID = 0x0,
- Z_16 = 0x1,
- Z_24 = 0x2,
- Z_32_FLOAT = 0x3,
-} ZFormat;
-typedef enum StencilFormat {
- STENCIL_INVALID = 0x0,
- STENCIL_8 = 0x1,
-} StencilFormat;
-typedef enum CmaskMode {
- CMASK_CLEAR_NONE = 0x0,
- CMASK_CLEAR_ONE = 0x1,
- CMASK_CLEAR_ALL = 0x2,
- CMASK_ANY_EXPANDED = 0x3,
- CMASK_ALPHA0_FRAG1 = 0x4,
- CMASK_ALPHA0_FRAG2 = 0x5,
- CMASK_ALPHA0_FRAG4 = 0x6,
- CMASK_ALPHA0_FRAGS = 0x7,
- CMASK_ALPHA1_FRAG1 = 0x8,
- CMASK_ALPHA1_FRAG2 = 0x9,
- CMASK_ALPHA1_FRAG4 = 0xa,
- CMASK_ALPHA1_FRAGS = 0xb,
- CMASK_ALPHAX_FRAG1 = 0xc,
- CMASK_ALPHAX_FRAG2 = 0xd,
- CMASK_ALPHAX_FRAG4 = 0xe,
- CMASK_ALPHAX_FRAGS = 0xf,
-} CmaskMode;
-typedef enum QuadExportFormat {
- EXPORT_UNUSED = 0x0,
- EXPORT_32_R = 0x1,
- EXPORT_32_GR = 0x2,
- EXPORT_32_AR = 0x3,
- EXPORT_FP16_ABGR = 0x4,
- EXPORT_UNSIGNED16_ABGR = 0x5,
- EXPORT_SIGNED16_ABGR = 0x6,
- EXPORT_32_ABGR = 0x7,
-} QuadExportFormat;
-typedef enum QuadExportFormatOld {
- EXPORT_4P_32BPC_ABGR = 0x0,
- EXPORT_4P_16BPC_ABGR = 0x1,
- EXPORT_4P_32BPC_GR = 0x2,
- EXPORT_4P_32BPC_AR = 0x3,
- EXPORT_2P_32BPC_ABGR = 0x4,
- EXPORT_8P_32BPC_R = 0x5,
-} QuadExportFormatOld;
-typedef enum ColorFormat {
- COLOR_INVALID = 0x0,
- COLOR_8 = 0x1,
- COLOR_16 = 0x2,
- COLOR_8_8 = 0x3,
- COLOR_32 = 0x4,
- COLOR_16_16 = 0x5,
- COLOR_10_11_11 = 0x6,
- COLOR_11_11_10 = 0x7,
- COLOR_10_10_10_2 = 0x8,
- COLOR_2_10_10_10 = 0x9,
- COLOR_8_8_8_8 = 0xa,
- COLOR_32_32 = 0xb,
- COLOR_16_16_16_16 = 0xc,
- COLOR_RESERVED_13 = 0xd,
- COLOR_32_32_32_32 = 0xe,
- COLOR_RESERVED_15 = 0xf,
- COLOR_5_6_5 = 0x10,
- COLOR_1_5_5_5 = 0x11,
- COLOR_5_5_5_1 = 0x12,
- COLOR_4_4_4_4 = 0x13,
- COLOR_8_24 = 0x14,
- COLOR_24_8 = 0x15,
- COLOR_X24_8_32_FLOAT = 0x16,
- COLOR_RESERVED_23 = 0x17,
-} ColorFormat;
-typedef enum SurfaceFormat {
- FMT_INVALID = 0x0,
- FMT_8 = 0x1,
- FMT_16 = 0x2,
- FMT_8_8 = 0x3,
- FMT_32 = 0x4,
- FMT_16_16 = 0x5,
- FMT_10_11_11 = 0x6,
- FMT_11_11_10 = 0x7,
- FMT_10_10_10_2 = 0x8,
- FMT_2_10_10_10 = 0x9,
- FMT_8_8_8_8 = 0xa,
- FMT_32_32 = 0xb,
- FMT_16_16_16_16 = 0xc,
- FMT_32_32_32 = 0xd,
- FMT_32_32_32_32 = 0xe,
- FMT_RESERVED_4 = 0xf,
- FMT_5_6_5 = 0x10,
- FMT_1_5_5_5 = 0x11,
- FMT_5_5_5_1 = 0x12,
- FMT_4_4_4_4 = 0x13,
- FMT_8_24 = 0x14,
- FMT_24_8 = 0x15,
- FMT_X24_8_32_FLOAT = 0x16,
- FMT_RESERVED_33 = 0x17,
- FMT_11_11_10_FLOAT = 0x18,
- FMT_16_FLOAT = 0x19,
- FMT_32_FLOAT = 0x1a,
- FMT_16_16_FLOAT = 0x1b,
- FMT_8_24_FLOAT = 0x1c,
- FMT_24_8_FLOAT = 0x1d,
- FMT_32_32_FLOAT = 0x1e,
- FMT_10_11_11_FLOAT = 0x1f,
- FMT_16_16_16_16_FLOAT = 0x20,
- FMT_3_3_2 = 0x21,
- FMT_6_5_5 = 0x22,
- FMT_32_32_32_32_FLOAT = 0x23,
- FMT_RESERVED_36 = 0x24,
- FMT_1 = 0x25,
- FMT_1_REVERSED = 0x26,
- FMT_GB_GR = 0x27,
- FMT_BG_RG = 0x28,
- FMT_32_AS_8 = 0x29,
- FMT_32_AS_8_8 = 0x2a,
- FMT_5_9_9_9_SHAREDEXP = 0x2b,
- FMT_8_8_8 = 0x2c,
- FMT_16_16_16 = 0x2d,
- FMT_16_16_16_FLOAT = 0x2e,
- FMT_4_4 = 0x2f,
- FMT_32_32_32_FLOAT = 0x30,
- FMT_BC1 = 0x31,
- FMT_BC2 = 0x32,
- FMT_BC3 = 0x33,
- FMT_BC4 = 0x34,
- FMT_BC5 = 0x35,
- FMT_BC6 = 0x36,
- FMT_BC7 = 0x37,
- FMT_32_AS_32_32_32_32 = 0x38,
- FMT_APC3 = 0x39,
- FMT_APC4 = 0x3a,
- FMT_APC5 = 0x3b,
- FMT_APC6 = 0x3c,
- FMT_APC7 = 0x3d,
- FMT_CTX1 = 0x3e,
- FMT_RESERVED_63 = 0x3f,
-} SurfaceFormat;
-typedef enum BUF_DATA_FORMAT {
- BUF_DATA_FORMAT_INVALID = 0x0,
- BUF_DATA_FORMAT_8 = 0x1,
- BUF_DATA_FORMAT_16 = 0x2,
- BUF_DATA_FORMAT_8_8 = 0x3,
- BUF_DATA_FORMAT_32 = 0x4,
- BUF_DATA_FORMAT_16_16 = 0x5,
- BUF_DATA_FORMAT_10_11_11 = 0x6,
- BUF_DATA_FORMAT_11_11_10 = 0x7,
- BUF_DATA_FORMAT_10_10_10_2 = 0x8,
- BUF_DATA_FORMAT_2_10_10_10 = 0x9,
- BUF_DATA_FORMAT_8_8_8_8 = 0xa,
- BUF_DATA_FORMAT_32_32 = 0xb,
- BUF_DATA_FORMAT_16_16_16_16 = 0xc,
- BUF_DATA_FORMAT_32_32_32 = 0xd,
- BUF_DATA_FORMAT_32_32_32_32 = 0xe,
- BUF_DATA_FORMAT_RESERVED_15 = 0xf,
-} BUF_DATA_FORMAT;
-typedef enum IMG_DATA_FORMAT {
- IMG_DATA_FORMAT_INVALID = 0x0,
- IMG_DATA_FORMAT_8 = 0x1,
- IMG_DATA_FORMAT_16 = 0x2,
- IMG_DATA_FORMAT_8_8 = 0x3,
- IMG_DATA_FORMAT_32 = 0x4,
- IMG_DATA_FORMAT_16_16 = 0x5,
- IMG_DATA_FORMAT_10_11_11 = 0x6,
- IMG_DATA_FORMAT_11_11_10 = 0x7,
- IMG_DATA_FORMAT_10_10_10_2 = 0x8,
- IMG_DATA_FORMAT_2_10_10_10 = 0x9,
- IMG_DATA_FORMAT_8_8_8_8 = 0xa,
- IMG_DATA_FORMAT_32_32 = 0xb,
- IMG_DATA_FORMAT_16_16_16_16 = 0xc,
- IMG_DATA_FORMAT_32_32_32 = 0xd,
- IMG_DATA_FORMAT_32_32_32_32 = 0xe,
- IMG_DATA_FORMAT_RESERVED_15 = 0xf,
- IMG_DATA_FORMAT_5_6_5 = 0x10,
- IMG_DATA_FORMAT_1_5_5_5 = 0x11,
- IMG_DATA_FORMAT_5_5_5_1 = 0x12,
- IMG_DATA_FORMAT_4_4_4_4 = 0x13,
- IMG_DATA_FORMAT_8_24 = 0x14,
- IMG_DATA_FORMAT_24_8 = 0x15,
- IMG_DATA_FORMAT_X24_8_32 = 0x16,
- IMG_DATA_FORMAT_RESERVED_23 = 0x17,
- IMG_DATA_FORMAT_RESERVED_24 = 0x18,
- IMG_DATA_FORMAT_RESERVED_25 = 0x19,
- IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
- IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
- IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
- IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
- IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
- IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
- IMG_DATA_FORMAT_GB_GR = 0x20,
- IMG_DATA_FORMAT_BG_RG = 0x21,
- IMG_DATA_FORMAT_5_9_9_9 = 0x22,
- IMG_DATA_FORMAT_BC1 = 0x23,
- IMG_DATA_FORMAT_BC2 = 0x24,
- IMG_DATA_FORMAT_BC3 = 0x25,
- IMG_DATA_FORMAT_BC4 = 0x26,
- IMG_DATA_FORMAT_BC5 = 0x27,
- IMG_DATA_FORMAT_BC6 = 0x28,
- IMG_DATA_FORMAT_BC7 = 0x29,
- IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
- IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
- IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
- IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
- IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
- IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
- IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
- IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
- IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
- IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
- IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
- IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
- IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
- IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
- IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
- IMG_DATA_FORMAT_4_4 = 0x39,
- IMG_DATA_FORMAT_6_5_5 = 0x3a,
- IMG_DATA_FORMAT_1 = 0x3b,
- IMG_DATA_FORMAT_1_REVERSED = 0x3c,
- IMG_DATA_FORMAT_32_AS_8 = 0x3d,
- IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
- IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
-} IMG_DATA_FORMAT;
-typedef enum BUF_NUM_FORMAT {
- BUF_NUM_FORMAT_UNORM = 0x0,
- BUF_NUM_FORMAT_SNORM = 0x1,
- BUF_NUM_FORMAT_USCALED = 0x2,
- BUF_NUM_FORMAT_SSCALED = 0x3,
- BUF_NUM_FORMAT_UINT = 0x4,
- BUF_NUM_FORMAT_SINT = 0x5,
- BUF_NUM_FORMAT_RESERVED_6 = 0x6,
- BUF_NUM_FORMAT_FLOAT = 0x7,
-} BUF_NUM_FORMAT;
-typedef enum IMG_NUM_FORMAT {
- IMG_NUM_FORMAT_UNORM = 0x0,
- IMG_NUM_FORMAT_SNORM = 0x1,
- IMG_NUM_FORMAT_USCALED = 0x2,
- IMG_NUM_FORMAT_SSCALED = 0x3,
- IMG_NUM_FORMAT_UINT = 0x4,
- IMG_NUM_FORMAT_SINT = 0x5,
- IMG_NUM_FORMAT_RESERVED_6 = 0x6,
- IMG_NUM_FORMAT_FLOAT = 0x7,
- IMG_NUM_FORMAT_RESERVED_8 = 0x8,
- IMG_NUM_FORMAT_SRGB = 0x9,
- IMG_NUM_FORMAT_RESERVED_10 = 0xa,
- IMG_NUM_FORMAT_RESERVED_11 = 0xb,
- IMG_NUM_FORMAT_RESERVED_12 = 0xc,
- IMG_NUM_FORMAT_RESERVED_13 = 0xd,
- IMG_NUM_FORMAT_RESERVED_14 = 0xe,
- IMG_NUM_FORMAT_RESERVED_15 = 0xf,
-} IMG_NUM_FORMAT;
-typedef enum TileType {
- ARRAY_COLOR_TILE = 0x0,
- ARRAY_DEPTH_TILE = 0x1,
-} TileType;
-typedef enum NonDispTilingOrder {
- ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
- ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
-} NonDispTilingOrder;
-typedef enum MicroTileMode {
- ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
- ADDR_SURF_THIN_MICRO_TILING = 0x1,
- ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
- ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
- ADDR_SURF_THICK_MICRO_TILING = 0x4,
-} MicroTileMode;
-typedef enum TileSplit {
- ADDR_SURF_TILE_SPLIT_64B = 0x0,
- ADDR_SURF_TILE_SPLIT_128B = 0x1,
- ADDR_SURF_TILE_SPLIT_256B = 0x2,
- ADDR_SURF_TILE_SPLIT_512B = 0x3,
- ADDR_SURF_TILE_SPLIT_1KB = 0x4,
- ADDR_SURF_TILE_SPLIT_2KB = 0x5,
- ADDR_SURF_TILE_SPLIT_4KB = 0x6,
-} TileSplit;
-typedef enum SampleSplit {
- ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
- ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
- ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
- ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
-} SampleSplit;
-typedef enum PipeConfig {
- ADDR_SURF_P2 = 0x0,
- ADDR_SURF_P2_RESERVED0 = 0x1,
- ADDR_SURF_P2_RESERVED1 = 0x2,
- ADDR_SURF_P2_RESERVED2 = 0x3,
- ADDR_SURF_P4_8x16 = 0x4,
- ADDR_SURF_P4_16x16 = 0x5,
- ADDR_SURF_P4_16x32 = 0x6,
- ADDR_SURF_P4_32x32 = 0x7,
- ADDR_SURF_P8_16x16_8x16 = 0x8,
- ADDR_SURF_P8_16x32_8x16 = 0x9,
- ADDR_SURF_P8_32x32_8x16 = 0xa,
- ADDR_SURF_P8_16x32_16x16 = 0xb,
- ADDR_SURF_P8_32x32_16x16 = 0xc,
- ADDR_SURF_P8_32x32_16x32 = 0xd,
- ADDR_SURF_P8_32x64_32x32 = 0xe,
- ADDR_SURF_P8_RESERVED0 = 0xf,
- ADDR_SURF_P16_32x32_8x16 = 0x10,
- ADDR_SURF_P16_32x32_16x16 = 0x11,
-} PipeConfig;
-typedef enum NumBanks {
- ADDR_SURF_2_BANK = 0x0,
- ADDR_SURF_4_BANK = 0x1,
- ADDR_SURF_8_BANK = 0x2,
- ADDR_SURF_16_BANK = 0x3,
-} NumBanks;
-typedef enum BankWidth {
- ADDR_SURF_BANK_WIDTH_1 = 0x0,
- ADDR_SURF_BANK_WIDTH_2 = 0x1,
- ADDR_SURF_BANK_WIDTH_4 = 0x2,
- ADDR_SURF_BANK_WIDTH_8 = 0x3,
-} BankWidth;
-typedef enum BankHeight {
- ADDR_SURF_BANK_HEIGHT_1 = 0x0,
- ADDR_SURF_BANK_HEIGHT_2 = 0x1,
- ADDR_SURF_BANK_HEIGHT_4 = 0x2,
- ADDR_SURF_BANK_HEIGHT_8 = 0x3,
-} BankHeight;
-typedef enum BankWidthHeight {
- ADDR_SURF_BANK_WH_1 = 0x0,
- ADDR_SURF_BANK_WH_2 = 0x1,
- ADDR_SURF_BANK_WH_4 = 0x2,
- ADDR_SURF_BANK_WH_8 = 0x3,
-} BankWidthHeight;
-typedef enum MacroTileAspect {
- ADDR_SURF_MACRO_ASPECT_1 = 0x0,
- ADDR_SURF_MACRO_ASPECT_2 = 0x1,
- ADDR_SURF_MACRO_ASPECT_4 = 0x2,
- ADDR_SURF_MACRO_ASPECT_8 = 0x3,
-} MacroTileAspect;
-typedef enum GATCL1RequestType {
- GATCL1_TYPE_NORMAL = 0x0,
- GATCL1_TYPE_SHOOTDOWN = 0x1,
- GATCL1_TYPE_BYPASS = 0x2,
-} GATCL1RequestType;
-typedef enum TCC_CACHE_POLICIES {
- TCC_CACHE_POLICY_LRU = 0x0,
- TCC_CACHE_POLICY_STREAM = 0x1,
-} TCC_CACHE_POLICIES;
-typedef enum MTYPE {
- MTYPE_NC_NV = 0x0,
- MTYPE_NC = 0x1,
- MTYPE_CC = 0x2,
- MTYPE_UC = 0x3,
-} MTYPE;
-typedef enum PERFMON_COUNTER_MODE {
- PERFMON_COUNTER_MODE_ACCUM = 0x0,
- PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
- PERFMON_COUNTER_MODE_MAX = 0x2,
- PERFMON_COUNTER_MODE_DIRTY = 0x3,
- PERFMON_COUNTER_MODE_SAMPLE = 0x4,
- PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
- PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
- PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
- PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
- PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
- PERFMON_COUNTER_MODE_RESERVED = 0xf,
-} PERFMON_COUNTER_MODE;
-typedef enum PERFMON_SPM_MODE {
- PERFMON_SPM_MODE_OFF = 0x0,
- PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
- PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
- PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
- PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
- PERFMON_SPM_MODE_RESERVED_5 = 0x5,
- PERFMON_SPM_MODE_RESERVED_6 = 0x6,
- PERFMON_SPM_MODE_RESERVED_7 = 0x7,
- PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
- PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
- PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
-} PERFMON_SPM_MODE;
-typedef enum SurfaceTiling {
- ARRAY_LINEAR = 0x0,
- ARRAY_TILED = 0x1,
-} SurfaceTiling;
-typedef enum SurfaceArray {
- ARRAY_1D = 0x0,
- ARRAY_2D = 0x1,
- ARRAY_3D = 0x2,
- ARRAY_3D_SLICE = 0x3,
-} SurfaceArray;
-typedef enum ColorArray {
- ARRAY_2D_ALT_COLOR = 0x0,
- ARRAY_2D_COLOR = 0x1,
- ARRAY_3D_SLICE_COLOR = 0x3,
-} ColorArray;
-typedef enum DepthArray {
- ARRAY_2D_ALT_DEPTH = 0x0,
- ARRAY_2D_DEPTH = 0x1,
-} DepthArray;
-typedef enum ENUM_NUM_SIMD_PER_CU {
- NUM_SIMD_PER_CU = 0x4,
-} ENUM_NUM_SIMD_PER_CU;
-typedef enum MEM_PWR_FORCE_CTRL {
- NO_FORCE_REQUEST = 0x0,
- FORCE_LIGHT_SLEEP_REQUEST = 0x1,
- FORCE_DEEP_SLEEP_REQUEST = 0x2,
- FORCE_SHUT_DOWN_REQUEST = 0x3,
-} MEM_PWR_FORCE_CTRL;
-typedef enum MEM_PWR_FORCE_CTRL2 {
- NO_FORCE_REQ = 0x0,
- FORCE_LIGHT_SLEEP_REQ = 0x1,
-} MEM_PWR_FORCE_CTRL2;
-typedef enum MEM_PWR_DIS_CTRL {
- ENABLE_MEM_PWR_CTRL = 0x0,
- DISABLE_MEM_PWR_CTRL = 0x1,
-} MEM_PWR_DIS_CTRL;
-typedef enum MEM_PWR_SEL_CTRL {
- DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
- DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
- DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
-} MEM_PWR_SEL_CTRL;
-typedef enum MEM_PWR_SEL_CTRL2 {
- DYNAMIC_DEEP_SLEEP_EN = 0x0,
- DYNAMIC_LIGHT_SLEEP_EN = 0x1,
-} MEM_PWR_SEL_CTRL2;
-
-#endif /* UVD_6_0_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_offset.h
deleted file mode 100644
index 98d22bd5b..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_offset.h
+++ /dev/null
@@ -1,1462 +0,0 @@
-/*
- * Copyright 2020 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef _vcn_2_6_0_OFFSET_HEADER
-#define _vcn_2_6_0_OFFSET_HEADER
-
-
-
-// addressBlock: uvd0_ecpudec
-// base address: 0x1fd00
-#define regUVD_VCPU_CACHE_OFFSET0 0x0140
-#define regUVD_VCPU_CACHE_OFFSET0_BASE_IDX 1
-#define regUVD_VCPU_CACHE_SIZE0 0x0141
-#define regUVD_VCPU_CACHE_SIZE0_BASE_IDX 1
-#define regUVD_VCPU_CACHE_OFFSET1 0x0142
-#define regUVD_VCPU_CACHE_OFFSET1_BASE_IDX 1
-#define regUVD_VCPU_CACHE_SIZE1 0x0143
-#define regUVD_VCPU_CACHE_SIZE1_BASE_IDX 1
-#define regUVD_VCPU_CACHE_OFFSET2 0x0144
-#define regUVD_VCPU_CACHE_OFFSET2_BASE_IDX 1
-#define regUVD_VCPU_CACHE_SIZE2 0x0145
-#define regUVD_VCPU_CACHE_SIZE2_BASE_IDX 1
-#define regUVD_VCPU_CACHE_OFFSET3 0x0146
-#define regUVD_VCPU_CACHE_OFFSET3_BASE_IDX 1
-#define regUVD_VCPU_CACHE_SIZE3 0x0147
-#define regUVD_VCPU_CACHE_SIZE3_BASE_IDX 1
-#define regUVD_VCPU_CACHE_OFFSET4 0x0148
-#define regUVD_VCPU_CACHE_OFFSET4_BASE_IDX 1
-#define regUVD_VCPU_CACHE_SIZE4 0x0149
-#define regUVD_VCPU_CACHE_SIZE4_BASE_IDX 1
-#define regUVD_VCPU_CACHE_OFFSET5 0x014a
-#define regUVD_VCPU_CACHE_OFFSET5_BASE_IDX 1
-#define regUVD_VCPU_CACHE_SIZE5 0x014b
-#define regUVD_VCPU_CACHE_SIZE5_BASE_IDX 1
-#define regUVD_VCPU_CACHE_OFFSET6 0x014c
-#define regUVD_VCPU_CACHE_OFFSET6_BASE_IDX 1
-#define regUVD_VCPU_CACHE_SIZE6 0x014d
-#define regUVD_VCPU_CACHE_SIZE6_BASE_IDX 1
-#define regUVD_VCPU_CACHE_OFFSET7 0x014e
-#define regUVD_VCPU_CACHE_OFFSET7_BASE_IDX 1
-#define regUVD_VCPU_CACHE_SIZE7 0x014f
-#define regUVD_VCPU_CACHE_SIZE7_BASE_IDX 1
-#define regUVD_VCPU_CACHE_OFFSET8 0x0150
-#define regUVD_VCPU_CACHE_OFFSET8_BASE_IDX 1
-#define regUVD_VCPU_CACHE_SIZE8 0x0151
-#define regUVD_VCPU_CACHE_SIZE8_BASE_IDX 1
-#define regUVD_VCPU_NONCACHE_OFFSET0 0x0152
-#define regUVD_VCPU_NONCACHE_OFFSET0_BASE_IDX 1
-#define regUVD_VCPU_NONCACHE_SIZE0 0x0153
-#define regUVD_VCPU_NONCACHE_SIZE0_BASE_IDX 1
-#define regUVD_VCPU_NONCACHE_OFFSET1 0x0154
-#define regUVD_VCPU_NONCACHE_OFFSET1_BASE_IDX 1
-#define regUVD_VCPU_NONCACHE_SIZE1 0x0155
-#define regUVD_VCPU_NONCACHE_SIZE1_BASE_IDX 1
-#define regUVD_VCPU_CNTL 0x0156
-#define regUVD_VCPU_CNTL_BASE_IDX 1
-#define regUVD_VCPU_PRID 0x0157
-#define regUVD_VCPU_PRID_BASE_IDX 1
-#define regUVD_VCPU_TRCE 0x0158
-#define regUVD_VCPU_TRCE_BASE_IDX 1
-#define regUVD_VCPU_TRCE_RD 0x0159
-#define regUVD_VCPU_TRCE_RD_BASE_IDX 1
-#define regUVD_VCPU_IND_INDEX 0x015b
-#define regUVD_VCPU_IND_INDEX_BASE_IDX 1
-#define regUVD_VCPU_IND_DATA 0x015c
-#define regUVD_VCPU_IND_DATA_BASE_IDX 1
-
-
-// addressBlock: uvd0_jpegnpdec
-// base address: 0x1e200
-#define regUVD_JPEG_CNTL 0x0080
-#define regUVD_JPEG_CNTL_BASE_IDX 0
-#define regUVD_JPEG_RB_BASE 0x0081
-#define regUVD_JPEG_RB_BASE_BASE_IDX 0
-#define regUVD_JPEG_RB_WPTR 0x0082
-#define regUVD_JPEG_RB_WPTR_BASE_IDX 0
-#define regUVD_JPEG_RB_RPTR 0x0083
-#define regUVD_JPEG_RB_RPTR_BASE_IDX 0
-#define regUVD_JPEG_RB_SIZE 0x0084
-#define regUVD_JPEG_RB_SIZE_BASE_IDX 0
-#define regUVD_JPEG_DEC_CNT 0x0085
-#define regUVD_JPEG_DEC_CNT_BASE_IDX 0
-#define regUVD_JPEG_SPS_INFO 0x0086
-#define regUVD_JPEG_SPS_INFO_BASE_IDX 0
-#define regUVD_JPEG_SPS1_INFO 0x0087
-#define regUVD_JPEG_SPS1_INFO_BASE_IDX 0
-#define regUVD_JPEG_RE_TIMER 0x0088
-#define regUVD_JPEG_RE_TIMER_BASE_IDX 0
-#define regUVD_JPEG_DEC_SCRATCH0 0x0089
-#define regUVD_JPEG_DEC_SCRATCH0_BASE_IDX 0
-#define regUVD_JPEG_INT_EN 0x008a
-#define regUVD_JPEG_INT_EN_BASE_IDX 0
-#define regUVD_JPEG_INT_STAT 0x008b
-#define regUVD_JPEG_INT_STAT_BASE_IDX 0
-#define regUVD_JPEG_TIER_CNTL0 0x008d
-#define regUVD_JPEG_TIER_CNTL0_BASE_IDX 0
-#define regUVD_JPEG_TIER_CNTL1 0x008e
-#define regUVD_JPEG_TIER_CNTL1_BASE_IDX 0
-#define regUVD_JPEG_TIER_CNTL2 0x008f
-#define regUVD_JPEG_TIER_CNTL2_BASE_IDX 0
-#define regUVD_JPEG_TIER_STATUS 0x0090
-#define regUVD_JPEG_TIER_STATUS_BASE_IDX 0
-#define regUVD_JPEG_OUTBUF_CNTL 0x009c
-#define regUVD_JPEG_OUTBUF_CNTL_BASE_IDX 0
-#define regUVD_JPEG_OUTBUF_WPTR 0x009d
-#define regUVD_JPEG_OUTBUF_WPTR_BASE_IDX 0
-#define regUVD_JPEG_OUTBUF_RPTR 0x009e
-#define regUVD_JPEG_OUTBUF_RPTR_BASE_IDX 0
-#define regUVD_JPEG_PITCH 0x009f
-#define regUVD_JPEG_PITCH_BASE_IDX 0
-#define regUVD_JPEG_UV_PITCH 0x00a0
-#define regUVD_JPEG_UV_PITCH_BASE_IDX 0
-#define regJPEG_DEC_Y_GFX8_TILING_SURFACE 0x00a1
-#define regJPEG_DEC_Y_GFX8_TILING_SURFACE_BASE_IDX 0
-#define regJPEG_DEC_UV_GFX8_TILING_SURFACE 0x00a2
-#define regJPEG_DEC_UV_GFX8_TILING_SURFACE_BASE_IDX 0
-#define regJPEG_DEC_GFX8_ADDR_CONFIG 0x00a3
-#define regJPEG_DEC_GFX8_ADDR_CONFIG_BASE_IDX 0
-#define regJPEG_DEC_Y_GFX10_TILING_SURFACE 0x00a4
-#define regJPEG_DEC_Y_GFX10_TILING_SURFACE_BASE_IDX 0
-#define regJPEG_DEC_UV_GFX10_TILING_SURFACE 0x00a5
-#define regJPEG_DEC_UV_GFX10_TILING_SURFACE_BASE_IDX 0
-#define regJPEG_DEC_GFX10_ADDR_CONFIG 0x00a6
-#define regJPEG_DEC_GFX10_ADDR_CONFIG_BASE_IDX 0
-#define regJPEG_DEC_ADDR_MODE 0x00a7
-#define regJPEG_DEC_ADDR_MODE_BASE_IDX 0
-#define regUVD_JPEG_OUTPUT_XY 0x00a8
-#define regUVD_JPEG_OUTPUT_XY_BASE_IDX 0
-#define regUVD_JPEG_GPCOM_CMD 0x00a9
-#define regUVD_JPEG_GPCOM_CMD_BASE_IDX 0
-#define regUVD_JPEG_GPCOM_DATA0 0x00aa
-#define regUVD_JPEG_GPCOM_DATA0_BASE_IDX 0
-#define regUVD_JPEG_GPCOM_DATA1 0x00ab
-#define regUVD_JPEG_GPCOM_DATA1_BASE_IDX 0
-#define regUVD_JPEG_INDEX 0x00ac
-#define regUVD_JPEG_INDEX_BASE_IDX 0
-#define regUVD_JPEG_DATA 0x00ad
-#define regUVD_JPEG_DATA_BASE_IDX 0
-#define regUVD_JPEG_SCRATCH1 0x00ae
-#define regUVD_JPEG_SCRATCH1_BASE_IDX 0
-#define regUVD_JPEG_DEC_SOFT_RST 0x00af
-#define regUVD_JPEG_DEC_SOFT_RST_BASE_IDX 0
-
-
-// addressBlock: uvd0_lmi_adpdec
-// base address: 0x20870
-#define regUVD_LMI_RE_64BIT_BAR_LOW 0x041c
-#define regUVD_LMI_RE_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_RE_64BIT_BAR_HIGH 0x041d
-#define regUVD_LMI_RE_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_IT_64BIT_BAR_LOW 0x041e
-#define regUVD_LMI_IT_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_IT_64BIT_BAR_HIGH 0x041f
-#define regUVD_LMI_IT_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_MP_64BIT_BAR_LOW 0x0420
-#define regUVD_LMI_MP_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_MP_64BIT_BAR_HIGH 0x0421
-#define regUVD_LMI_MP_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_CM_64BIT_BAR_LOW 0x0422
-#define regUVD_LMI_CM_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_CM_64BIT_BAR_HIGH 0x0423
-#define regUVD_LMI_CM_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_DB_64BIT_BAR_LOW 0x0424
-#define regUVD_LMI_DB_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_DB_64BIT_BAR_HIGH 0x0425
-#define regUVD_LMI_DB_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_DBW_64BIT_BAR_LOW 0x0426
-#define regUVD_LMI_DBW_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_DBW_64BIT_BAR_HIGH 0x0427
-#define regUVD_LMI_DBW_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_IDCT_64BIT_BAR_LOW 0x0428
-#define regUVD_LMI_IDCT_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_IDCT_64BIT_BAR_HIGH 0x0429
-#define regUVD_LMI_IDCT_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_MPRD_S0_64BIT_BAR_LOW 0x042a
-#define regUVD_LMI_MPRD_S0_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_MPRD_S0_64BIT_BAR_HIGH 0x042b
-#define regUVD_LMI_MPRD_S0_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_MPRD_S1_64BIT_BAR_LOW 0x042c
-#define regUVD_LMI_MPRD_S1_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_MPRD_S1_64BIT_BAR_HIGH 0x042d
-#define regUVD_LMI_MPRD_S1_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_MPRD_DBW_64BIT_BAR_LOW 0x042e
-#define regUVD_LMI_MPRD_DBW_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_MPRD_DBW_64BIT_BAR_HIGH 0x042f
-#define regUVD_LMI_MPRD_DBW_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_MPC_64BIT_BAR_LOW 0x0430
-#define regUVD_LMI_MPC_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_MPC_64BIT_BAR_HIGH 0x0431
-#define regUVD_LMI_MPC_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x0432
-#define regUVD_LMI_RBC_RB_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x0433
-#define regUVD_LMI_RBC_RB_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x0434
-#define regUVD_LMI_RBC_IB_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x0435
-#define regUVD_LMI_RBC_IB_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_LBSI_64BIT_BAR_LOW 0x0436
-#define regUVD_LMI_LBSI_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_LBSI_64BIT_BAR_HIGH 0x0437
-#define regUVD_LMI_LBSI_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW 0x0438
-#define regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH 0x0439
-#define regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_VCPU_NC1_64BIT_BAR_LOW 0x043a
-#define regUVD_LMI_VCPU_NC1_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH 0x043b
-#define regUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x043c
-#define regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x043d
-#define regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_CENC_64BIT_BAR_LOW 0x043e
-#define regUVD_LMI_CENC_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_CENC_64BIT_BAR_HIGH 0x043f
-#define regUVD_LMI_CENC_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_SRE_64BIT_BAR_LOW 0x0440
-#define regUVD_LMI_SRE_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_SRE_64BIT_BAR_HIGH 0x0441
-#define regUVD_LMI_SRE_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW 0x0442
-#define regUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH 0x0443
-#define regUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW 0x0444
-#define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH 0x0445
-#define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW 0x0446
-#define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH 0x0447
-#define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_MIF_REF_64BIT_BAR_LOW 0x0448
-#define regUVD_LMI_MIF_REF_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_MIF_REF_64BIT_BAR_HIGH 0x0449
-#define regUVD_LMI_MIF_REF_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_MIF_DBW_64BIT_BAR_LOW 0x044a
-#define regUVD_LMI_MIF_DBW_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_MIF_DBW_64BIT_BAR_HIGH 0x044b
-#define regUVD_LMI_MIF_DBW_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW 0x044c
-#define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH 0x044d
-#define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_MIF_BSP0_64BIT_BAR_LOW 0x044e
-#define regUVD_LMI_MIF_BSP0_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH 0x044f
-#define regUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_MIF_BSP1_64BIT_BAR_LOW 0x0450
-#define regUVD_LMI_MIF_BSP1_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH 0x0451
-#define regUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_MIF_BSP2_64BIT_BAR_LOW 0x0452
-#define regUVD_LMI_MIF_BSP2_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH 0x0453
-#define regUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_MIF_BSP3_64BIT_BAR_LOW 0x0454
-#define regUVD_LMI_MIF_BSP3_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH 0x0455
-#define regUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_MIF_BSD0_64BIT_BAR_LOW 0x0456
-#define regUVD_LMI_MIF_BSD0_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH 0x0457
-#define regUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_MIF_BSD1_64BIT_BAR_LOW 0x0458
-#define regUVD_LMI_MIF_BSD1_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH 0x0459
-#define regUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_MIF_BSD2_64BIT_BAR_LOW 0x045a
-#define regUVD_LMI_MIF_BSD2_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH 0x045b
-#define regUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_MIF_BSD3_64BIT_BAR_LOW 0x045c
-#define regUVD_LMI_MIF_BSD3_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH 0x045d
-#define regUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_MIF_BSD4_64BIT_BAR_LOW 0x045e
-#define regUVD_LMI_MIF_BSD4_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH 0x045f
-#define regUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 0x0468
-#define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 0x0469
-#define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW 0x046a
-#define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH 0x046b
-#define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 0x046c
-#define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 0x046d
-#define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW 0x046e
-#define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH 0x046f
-#define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW 0x0470
-#define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH 0x0471
-#define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW 0x0472
-#define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH 0x0473
-#define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW 0x0474
-#define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH 0x0475
-#define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW 0x0476
-#define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH 0x0477
-#define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_MIF_SCLR_64BIT_BAR_LOW 0x0478
-#define regUVD_LMI_MIF_SCLR_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH 0x0479
-#define regUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW 0x047a
-#define regUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH 0x047b
-#define regUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_SPH_64BIT_BAR_HIGH 0x047c
-#define regUVD_LMI_SPH_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW 0x047d
-#define regUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH 0x047e
-#define regUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW 0x047f
-#define regUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH 0x0480
-#define regUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW 0x0481
-#define regUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH 0x0482
-#define regUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW 0x0483
-#define regUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH 0x0484
-#define regUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW 0x0485
-#define regUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH 0x0486
-#define regUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW 0x0487
-#define regUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH 0x0488
-#define regUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW 0x0489
-#define regUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH 0x048a
-#define regUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW 0x048b
-#define regUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH 0x048c
-#define regUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_MMSCH_NC_VMID 0x048d
-#define regUVD_LMI_MMSCH_NC_VMID_BASE_IDX 1
-#define regUVD_LMI_MMSCH_CTRL 0x048e
-#define regUVD_LMI_MMSCH_CTRL_BASE_IDX 1
-#define regUVD_MMSCH_LMI_STATUS 0x048f
-#define regUVD_MMSCH_LMI_STATUS_BASE_IDX 1
-#define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW 0x0490
-#define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH 0x0491
-#define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW 0x0492
-#define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH 0x0493
-#define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW 0x0494
-#define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH 0x0495
-#define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW 0x0496
-#define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH 0x0497
-#define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_ADP_ATOMIC_CONFIG 0x0499
-#define regUVD_ADP_ATOMIC_CONFIG_BASE_IDX 1
-#define regUVD_LMI_ARB_CTRL2 0x049a
-#define regUVD_LMI_ARB_CTRL2_BASE_IDX 1
-#define regUVD_LMI_VCPU_CACHE_VMIDS_MULTI 0x049f
-#define regUVD_LMI_VCPU_CACHE_VMIDS_MULTI_BASE_IDX 1
-#define regUVD_LMI_VCPU_NC_VMIDS_MULTI 0x04a0
-#define regUVD_LMI_VCPU_NC_VMIDS_MULTI_BASE_IDX 1
-#define regUVD_LMI_LAT_CTRL 0x04a1
-#define regUVD_LMI_LAT_CTRL_BASE_IDX 1
-#define regUVD_LMI_LAT_CNTR 0x04a2
-#define regUVD_LMI_LAT_CNTR_BASE_IDX 1
-#define regUVD_LMI_AVG_LAT_CNTR 0x04a3
-#define regUVD_LMI_AVG_LAT_CNTR_BASE_IDX 1
-#define regUVD_LMI_SPH 0x04a4
-#define regUVD_LMI_SPH_BASE_IDX 1
-#define regUVD_LMI_VCPU_CACHE_VMID 0x04a5
-#define regUVD_LMI_VCPU_CACHE_VMID_BASE_IDX 1
-#define regUVD_LMI_CTRL2 0x04a6
-#define regUVD_LMI_CTRL2_BASE_IDX 1
-#define regUVD_LMI_URGENT_CTRL 0x04a7
-#define regUVD_LMI_URGENT_CTRL_BASE_IDX 1
-#define regUVD_LMI_CTRL 0x04a8
-#define regUVD_LMI_CTRL_BASE_IDX 1
-#define regUVD_LMI_STATUS 0x04a9
-#define regUVD_LMI_STATUS_BASE_IDX 1
-#define regUVD_LMI_PERFMON_CTRL 0x04ac
-#define regUVD_LMI_PERFMON_CTRL_BASE_IDX 1
-#define regUVD_LMI_PERFMON_COUNT_LO 0x04ad
-#define regUVD_LMI_PERFMON_COUNT_LO_BASE_IDX 1
-#define regUVD_LMI_PERFMON_COUNT_HI 0x04ae
-#define regUVD_LMI_PERFMON_COUNT_HI_BASE_IDX 1
-#define regUVD_LMI_ADP_SWAP_CNTL 0x04af
-#define regUVD_LMI_ADP_SWAP_CNTL_BASE_IDX 1
-#define regUVD_LMI_RBC_RB_VMID 0x04b0
-#define regUVD_LMI_RBC_RB_VMID_BASE_IDX 1
-#define regUVD_LMI_RBC_IB_VMID 0x04b1
-#define regUVD_LMI_RBC_IB_VMID_BASE_IDX 1
-#define regUVD_LMI_MC_CREDITS 0x04b2
-#define regUVD_LMI_MC_CREDITS_BASE_IDX 1
-#define regUVD_LMI_ADP_IND_INDEX 0x04b6
-#define regUVD_LMI_ADP_IND_INDEX_BASE_IDX 1
-#define regUVD_LMI_ADP_IND_DATA 0x04b7
-#define regUVD_LMI_ADP_IND_DATA_BASE_IDX 1
-#define regVCN_RAS_CNTL 0x04b9
-#define regVCN_RAS_CNTL_BASE_IDX 1
-
-
-// addressBlock: uvd0_mmsch_dec
-// base address: 0x1e000
-#define regMMSCH_UCODE_ADDR 0x0000
-#define regMMSCH_UCODE_ADDR_BASE_IDX 0
-#define regMMSCH_UCODE_DATA 0x0001
-#define regMMSCH_UCODE_DATA_BASE_IDX 0
-#define regMMSCH_SRAM_ADDR 0x0002
-#define regMMSCH_SRAM_ADDR_BASE_IDX 0
-#define regMMSCH_SRAM_DATA 0x0003
-#define regMMSCH_SRAM_DATA_BASE_IDX 0
-#define regMMSCH_VF_SRAM_OFFSET 0x0004
-#define regMMSCH_VF_SRAM_OFFSET_BASE_IDX 0
-#define regMMSCH_DB_SRAM_OFFSET 0x0005
-#define regMMSCH_DB_SRAM_OFFSET_BASE_IDX 0
-#define regMMSCH_CTX_SRAM_OFFSET 0x0006
-#define regMMSCH_CTX_SRAM_OFFSET_BASE_IDX 0
-#define regMMSCH_INTR 0x0008
-#define regMMSCH_INTR_BASE_IDX 0
-#define regMMSCH_INTR_ACK 0x0009
-#define regMMSCH_INTR_ACK_BASE_IDX 0
-#define regMMSCH_INTR_STATUS 0x000a
-#define regMMSCH_INTR_STATUS_BASE_IDX 0
-#define regMMSCH_VF_VMID 0x000b
-#define regMMSCH_VF_VMID_BASE_IDX 0
-#define regMMSCH_VF_CTX_ADDR_LO 0x000c
-#define regMMSCH_VF_CTX_ADDR_LO_BASE_IDX 0
-#define regMMSCH_VF_CTX_ADDR_HI 0x000d
-#define regMMSCH_VF_CTX_ADDR_HI_BASE_IDX 0
-#define regMMSCH_VF_CTX_SIZE 0x000e
-#define regMMSCH_VF_CTX_SIZE_BASE_IDX 0
-#define regMMSCH_VF_GPCOM_ADDR_LO 0x000f
-#define regMMSCH_VF_GPCOM_ADDR_LO_BASE_IDX 0
-#define regMMSCH_VF_GPCOM_ADDR_HI 0x0010
-#define regMMSCH_VF_GPCOM_ADDR_HI_BASE_IDX 0
-#define regMMSCH_VF_GPCOM_SIZE 0x0011
-#define regMMSCH_VF_GPCOM_SIZE_BASE_IDX 0
-#define regMMSCH_VF_MAILBOX_HOST 0x0012
-#define regMMSCH_VF_MAILBOX_HOST_BASE_IDX 0
-#define regMMSCH_VF_MAILBOX_RESP 0x0013
-#define regMMSCH_VF_MAILBOX_RESP_BASE_IDX 0
-#define regMMSCH_VF_MAILBOX_0 0x0014
-#define regMMSCH_VF_MAILBOX_0_BASE_IDX 0
-#define regMMSCH_VF_MAILBOX_0_RESP 0x0015
-#define regMMSCH_VF_MAILBOX_0_RESP_BASE_IDX 0
-#define regMMSCH_VF_MAILBOX_1 0x0016
-#define regMMSCH_VF_MAILBOX_1_BASE_IDX 0
-#define regMMSCH_VF_MAILBOX_1_RESP 0x0017
-#define regMMSCH_VF_MAILBOX_1_RESP_BASE_IDX 0
-#define regMMSCH_CNTL 0x001c
-#define regMMSCH_CNTL_BASE_IDX 0
-#define regMMSCH_NONCACHE_OFFSET0 0x001d
-#define regMMSCH_NONCACHE_OFFSET0_BASE_IDX 0
-#define regMMSCH_NONCACHE_SIZE0 0x001e
-#define regMMSCH_NONCACHE_SIZE0_BASE_IDX 0
-#define regMMSCH_NONCACHE_OFFSET1 0x001f
-#define regMMSCH_NONCACHE_OFFSET1_BASE_IDX 0
-#define regMMSCH_NONCACHE_SIZE1 0x0020
-#define regMMSCH_NONCACHE_SIZE1_BASE_IDX 0
-#define regMMSCH_PROC_STATE1 0x0026
-#define regMMSCH_PROC_STATE1_BASE_IDX 0
-#define regMMSCH_LAST_MC_ADDR 0x0027
-#define regMMSCH_LAST_MC_ADDR_BASE_IDX 0
-#define regMMSCH_LAST_MEM_ACCESS_HI 0x0028
-#define regMMSCH_LAST_MEM_ACCESS_HI_BASE_IDX 0
-#define regMMSCH_LAST_MEM_ACCESS_LO 0x0029
-#define regMMSCH_LAST_MEM_ACCESS_LO_BASE_IDX 0
-#define regMMSCH_SCRATCH_0 0x002b
-#define regMMSCH_SCRATCH_0_BASE_IDX 0
-#define regMMSCH_SCRATCH_1 0x002c
-#define regMMSCH_SCRATCH_1_BASE_IDX 0
-#define regMMSCH_GPUIOV_SCH_BLOCK_0 0x002d
-#define regMMSCH_GPUIOV_SCH_BLOCK_0_BASE_IDX 0
-#define regMMSCH_GPUIOV_CMD_CONTROL_0 0x002e
-#define regMMSCH_GPUIOV_CMD_CONTROL_0_BASE_IDX 0
-#define regMMSCH_GPUIOV_CMD_STATUS_0 0x002f
-#define regMMSCH_GPUIOV_CMD_STATUS_0_BASE_IDX 0
-#define regMMSCH_GPUIOV_VM_BUSY_STATUS_0 0x0030
-#define regMMSCH_GPUIOV_VM_BUSY_STATUS_0_BASE_IDX 0
-#define regMMSCH_GPUIOV_ACTIVE_FCNS_0 0x0031
-#define regMMSCH_GPUIOV_ACTIVE_FCNS_0_BASE_IDX 0
-#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_0 0x0032
-#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_0_BASE_IDX 0
-#define regMMSCH_GPUIOV_DW6_0 0x0033
-#define regMMSCH_GPUIOV_DW6_0_BASE_IDX 0
-#define regMMSCH_GPUIOV_DW7_0 0x0034
-#define regMMSCH_GPUIOV_DW7_0_BASE_IDX 0
-#define regMMSCH_GPUIOV_DW8_0 0x0035
-#define regMMSCH_GPUIOV_DW8_0_BASE_IDX 0
-#define regMMSCH_GPUIOV_SCH_BLOCK_1 0x0036
-#define regMMSCH_GPUIOV_SCH_BLOCK_1_BASE_IDX 0
-#define regMMSCH_GPUIOV_CMD_CONTROL_1 0x0037
-#define regMMSCH_GPUIOV_CMD_CONTROL_1_BASE_IDX 0
-#define regMMSCH_GPUIOV_CMD_STATUS_1 0x0038
-#define regMMSCH_GPUIOV_CMD_STATUS_1_BASE_IDX 0
-#define regMMSCH_GPUIOV_VM_BUSY_STATUS_1 0x0039
-#define regMMSCH_GPUIOV_VM_BUSY_STATUS_1_BASE_IDX 0
-#define regMMSCH_GPUIOV_ACTIVE_FCNS_1 0x003a
-#define regMMSCH_GPUIOV_ACTIVE_FCNS_1_BASE_IDX 0
-#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_1 0x003b
-#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_1_BASE_IDX 0
-#define regMMSCH_GPUIOV_DW6_1 0x003c
-#define regMMSCH_GPUIOV_DW6_1_BASE_IDX 0
-#define regMMSCH_GPUIOV_DW7_1 0x003d
-#define regMMSCH_GPUIOV_DW7_1_BASE_IDX 0
-#define regMMSCH_GPUIOV_DW8_1 0x003e
-#define regMMSCH_GPUIOV_DW8_1_BASE_IDX 0
-#define regMMSCH_GPUIOV_CNTXT 0x003f
-#define regMMSCH_GPUIOV_CNTXT_BASE_IDX 0
-#define regMMSCH_SCRATCH_2 0x0040
-#define regMMSCH_SCRATCH_2_BASE_IDX 0
-#define regMMSCH_SCRATCH_3 0x0041
-#define regMMSCH_SCRATCH_3_BASE_IDX 0
-#define regMMSCH_SCRATCH_4 0x0042
-#define regMMSCH_SCRATCH_4_BASE_IDX 0
-#define regMMSCH_SCRATCH_5 0x0043
-#define regMMSCH_SCRATCH_5_BASE_IDX 0
-#define regMMSCH_SCRATCH_6 0x0044
-#define regMMSCH_SCRATCH_6_BASE_IDX 0
-#define regMMSCH_SCRATCH_7 0x0045
-#define regMMSCH_SCRATCH_7_BASE_IDX 0
-#define regMMSCH_VFID_FIFO_HEAD_0 0x0046
-#define regMMSCH_VFID_FIFO_HEAD_0_BASE_IDX 0
-#define regMMSCH_VFID_FIFO_TAIL_0 0x0047
-#define regMMSCH_VFID_FIFO_TAIL_0_BASE_IDX 0
-#define regMMSCH_VFID_FIFO_HEAD_1 0x0048
-#define regMMSCH_VFID_FIFO_HEAD_1_BASE_IDX 0
-#define regMMSCH_VFID_FIFO_TAIL_1 0x0049
-#define regMMSCH_VFID_FIFO_TAIL_1_BASE_IDX 0
-#define regMMSCH_NACK_STATUS 0x004a
-#define regMMSCH_NACK_STATUS_BASE_IDX 0
-#define regMMSCH_VF_MAILBOX0_DATA 0x004b
-#define regMMSCH_VF_MAILBOX0_DATA_BASE_IDX 0
-#define regMMSCH_VF_MAILBOX1_DATA 0x004c
-#define regMMSCH_VF_MAILBOX1_DATA_BASE_IDX 0
-#define regMMSCH_GPUIOV_SCH_BLOCK_IP_0 0x004d
-#define regMMSCH_GPUIOV_SCH_BLOCK_IP_0_BASE_IDX 0
-#define regMMSCH_GPUIOV_CMD_STATUS_IP_0 0x004e
-#define regMMSCH_GPUIOV_CMD_STATUS_IP_0_BASE_IDX 0
-#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0 0x004f
-#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0_BASE_IDX 0
-#define regMMSCH_GPUIOV_SCH_BLOCK_IP_1 0x0050
-#define regMMSCH_GPUIOV_SCH_BLOCK_IP_1_BASE_IDX 0
-#define regMMSCH_GPUIOV_CMD_STATUS_IP_1 0x0051
-#define regMMSCH_GPUIOV_CMD_STATUS_IP_1_BASE_IDX 0
-#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1 0x0052
-#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1_BASE_IDX 0
-#define regMMSCH_GPUIOV_CNTXT_IP 0x0053
-#define regMMSCH_GPUIOV_CNTXT_IP_BASE_IDX 0
-#define regMMSCH_GPUIOV_SCH_BLOCK_2 0x0054
-#define regMMSCH_GPUIOV_SCH_BLOCK_2_BASE_IDX 0
-#define regMMSCH_GPUIOV_CMD_CONTROL_2 0x0055
-#define regMMSCH_GPUIOV_CMD_CONTROL_2_BASE_IDX 0
-#define regMMSCH_GPUIOV_CMD_STATUS_2 0x0056
-#define regMMSCH_GPUIOV_CMD_STATUS_2_BASE_IDX 0
-#define regMMSCH_GPUIOV_VM_BUSY_STATUS_2 0x0057
-#define regMMSCH_GPUIOV_VM_BUSY_STATUS_2_BASE_IDX 0
-#define regMMSCH_GPUIOV_ACTIVE_FCNS_2 0x0058
-#define regMMSCH_GPUIOV_ACTIVE_FCNS_2_BASE_IDX 0
-#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_2 0x0059
-#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_2_BASE_IDX 0
-#define regMMSCH_GPUIOV_DW6_2 0x005a
-#define regMMSCH_GPUIOV_DW6_2_BASE_IDX 0
-#define regMMSCH_GPUIOV_DW7_2 0x005b
-#define regMMSCH_GPUIOV_DW7_2_BASE_IDX 0
-#define regMMSCH_GPUIOV_DW8_2 0x005c
-#define regMMSCH_GPUIOV_DW8_2_BASE_IDX 0
-#define regMMSCH_GPUIOV_SCH_BLOCK_IP_2 0x005d
-#define regMMSCH_GPUIOV_SCH_BLOCK_IP_2_BASE_IDX 0
-#define regMMSCH_GPUIOV_CMD_STATUS_IP_2 0x005e
-#define regMMSCH_GPUIOV_CMD_STATUS_IP_2_BASE_IDX 0
-#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2 0x005f
-#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2_BASE_IDX 0
-#define regMMSCH_VFID_FIFO_HEAD_2 0x0060
-#define regMMSCH_VFID_FIFO_HEAD_2_BASE_IDX 0
-#define regMMSCH_VFID_FIFO_TAIL_2 0x0061
-#define regMMSCH_VFID_FIFO_TAIL_2_BASE_IDX 0
-#define regMMSCH_VM_BUSY_STATUS_0 0x0062
-#define regMMSCH_VM_BUSY_STATUS_0_BASE_IDX 0
-#define regMMSCH_VM_BUSY_STATUS_1 0x0063
-#define regMMSCH_VM_BUSY_STATUS_1_BASE_IDX 0
-#define regMMSCH_VM_BUSY_STATUS_2 0x0064
-#define regMMSCH_VM_BUSY_STATUS_2_BASE_IDX 0
-
-
-// addressBlock: uvd0_uvd_jmi_dec
-// base address: 0x1e500
-#define regUVD_JADP_MCIF_URGENT_CTRL 0x0141
-#define regUVD_JADP_MCIF_URGENT_CTRL_BASE_IDX 0
-#define regUVD_JMI_URGENT_CTRL 0x0142
-#define regUVD_JMI_URGENT_CTRL_BASE_IDX 0
-#define regUVD_JPEG_DEC_PF_CTRL 0x0143
-#define regUVD_JPEG_DEC_PF_CTRL_BASE_IDX 0
-#define regUVD_JPEG_ENC_PF_CTRL 0x0144
-#define regUVD_JPEG_ENC_PF_CTRL_BASE_IDX 0
-#define regUVD_JMI_CTRL 0x0145
-#define regUVD_JMI_CTRL_BASE_IDX 0
-#define regUVD_LMI_JRBC_CTRL 0x0146
-#define regUVD_LMI_JRBC_CTRL_BASE_IDX 0
-#define regUVD_LMI_JPEG_CTRL 0x0147
-#define regUVD_LMI_JPEG_CTRL_BASE_IDX 0
-#define regUVD_JMI_EJRBC_CTRL 0x0148
-#define regUVD_JMI_EJRBC_CTRL_BASE_IDX 0
-#define regUVD_LMI_EJPEG_CTRL 0x0149
-#define regUVD_LMI_EJPEG_CTRL_BASE_IDX 0
-#define regUVD_JMI_SCALER_CTRL 0x014a
-#define regUVD_JMI_SCALER_CTRL_BASE_IDX 0
-#define regJPEG_LMI_DROP 0x014b
-#define regJPEG_LMI_DROP_BASE_IDX 0
-#define regUVD_JMI_EJPEG_DROP 0x014c
-#define regUVD_JMI_EJPEG_DROP_BASE_IDX 0
-#define regJPEG_MEMCHECK_CLAMPING 0x014d
-#define regJPEG_MEMCHECK_CLAMPING_BASE_IDX 0
-#define regUVD_JMI_EJPEG_MEMCHECK_CLAMPING 0x014e
-#define regUVD_JMI_EJPEG_MEMCHECK_CLAMPING_BASE_IDX 0
-#define regUVD_LMI_JRBC_IB_VMID 0x014f
-#define regUVD_LMI_JRBC_IB_VMID_BASE_IDX 0
-#define regUVD_LMI_JRBC_RB_VMID 0x0150
-#define regUVD_LMI_JRBC_RB_VMID_BASE_IDX 0
-#define regUVD_LMI_JPEG_VMID 0x0151
-#define regUVD_LMI_JPEG_VMID_BASE_IDX 0
-#define regUVD_JMI_ENC_JRBC_IB_VMID 0x0152
-#define regUVD_JMI_ENC_JRBC_IB_VMID_BASE_IDX 0
-#define regUVD_JMI_ENC_JRBC_RB_VMID 0x0153
-#define regUVD_JMI_ENC_JRBC_RB_VMID_BASE_IDX 0
-#define regUVD_JMI_ENC_JPEG_VMID 0x0154
-#define regUVD_JMI_ENC_JPEG_VMID_BASE_IDX 0
-#define regUVD_JMI_EJPEG_RAS_CNTL 0x0156
-#define regUVD_JMI_EJPEG_RAS_CNTL_BASE_IDX 0
-#define regJPEG_MEMCHECK_SAFE_ADDR 0x0157
-#define regJPEG_MEMCHECK_SAFE_ADDR_BASE_IDX 0
-#define regJPEG_MEMCHECK_SAFE_ADDR_64BIT 0x0158
-#define regJPEG_MEMCHECK_SAFE_ADDR_64BIT_BASE_IDX 0
-#define regUVD_JMI_LAT_CTRL 0x0159
-#define regUVD_JMI_LAT_CTRL_BASE_IDX 0
-#define regUVD_JMI_LAT_CNTR 0x015a
-#define regUVD_JMI_LAT_CNTR_BASE_IDX 0
-#define regUVD_JMI_AVG_LAT_CNTR 0x015b
-#define regUVD_JMI_AVG_LAT_CNTR_BASE_IDX 0
-#define regUVD_JMI_PERFMON_CTRL 0x015c
-#define regUVD_JMI_PERFMON_CTRL_BASE_IDX 0
-#define regUVD_JMI_PERFMON_COUNT_LO 0x015d
-#define regUVD_JMI_PERFMON_COUNT_LO_BASE_IDX 0
-#define regUVD_JMI_PERFMON_COUNT_HI 0x015e
-#define regUVD_JMI_PERFMON_COUNT_HI_BASE_IDX 0
-#define regUVD_JMI_CLEAN_STATUS 0x015f
-#define regUVD_JMI_CLEAN_STATUS_BASE_IDX 0
-#define regUVD_LMI_JPEG_READ_64BIT_BAR_LOW 0x0160
-#define regUVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX 0
-#define regUVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x0161
-#define regUVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX 0
-#define regUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x0162
-#define regUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX 0
-#define regUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x0163
-#define regUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX 0
-#define regUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0x0164
-#define regUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX 0
-#define regUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0x0165
-#define regUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX 0
-#define regUVD_LMI_JRBC_RB_64BIT_BAR_LOW 0x0166
-#define regUVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX 0
-#define regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH 0x0167
-#define regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX 0
-#define regUVD_LMI_JRBC_IB_64BIT_BAR_LOW 0x0168
-#define regUVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX 0
-#define regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH 0x0169
-#define regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX 0
-#define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 0x016a
-#define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0
-#define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x016b
-#define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0
-#define regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW 0x016c
-#define regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0
-#define regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH 0x016d
-#define regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0
-#define regUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 0x016e
-#define regUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0
-#define regUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 0x016f
-#define regUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0
-#define regUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW 0x0170
-#define regUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0
-#define regUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH 0x0171
-#define regUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0
-#define regUVD_JMI_PEL_RD_64BIT_BAR_LOW 0x0172
-#define regUVD_JMI_PEL_RD_64BIT_BAR_LOW_BASE_IDX 0
-#define regUVD_JMI_PEL_RD_64BIT_BAR_HIGH 0x0173
-#define regUVD_JMI_PEL_RD_64BIT_BAR_HIGH_BASE_IDX 0
-#define regUVD_JMI_BS_WR_64BIT_BAR_LOW 0x0174
-#define regUVD_JMI_BS_WR_64BIT_BAR_LOW_BASE_IDX 0
-#define regUVD_JMI_BS_WR_64BIT_BAR_HIGH 0x0175
-#define regUVD_JMI_BS_WR_64BIT_BAR_HIGH_BASE_IDX 0
-#define regUVD_JMI_SCALAR_RD_64BIT_BAR_LOW 0x0176
-#define regUVD_JMI_SCALAR_RD_64BIT_BAR_LOW_BASE_IDX 0
-#define regUVD_JMI_SCALAR_RD_64BIT_BAR_HIGH 0x0177
-#define regUVD_JMI_SCALAR_RD_64BIT_BAR_HIGH_BASE_IDX 0
-#define regUVD_JMI_SCALAR_WR_64BIT_BAR_LOW 0x0178
-#define regUVD_JMI_SCALAR_WR_64BIT_BAR_LOW_BASE_IDX 0
-#define regUVD_JMI_SCALAR_WR_64BIT_BAR_HIGH 0x0179
-#define regUVD_JMI_SCALAR_WR_64BIT_BAR_HIGH_BASE_IDX 0
-#define regUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0x017a
-#define regUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX 0
-#define regUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0x017b
-#define regUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX 0
-#define regUVD_LMI_EJRBC_RB_64BIT_BAR_LOW 0x017c
-#define regUVD_LMI_EJRBC_RB_64BIT_BAR_LOW_BASE_IDX 0
-#define regUVD_LMI_EJRBC_RB_64BIT_BAR_HIGH 0x017d
-#define regUVD_LMI_EJRBC_RB_64BIT_BAR_HIGH_BASE_IDX 0
-#define regUVD_LMI_EJRBC_IB_64BIT_BAR_LOW 0x017e
-#define regUVD_LMI_EJRBC_IB_64BIT_BAR_LOW_BASE_IDX 0
-#define regUVD_LMI_EJRBC_IB_64BIT_BAR_HIGH 0x017f
-#define regUVD_LMI_EJRBC_IB_64BIT_BAR_HIGH_BASE_IDX 0
-#define regUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW 0x0180
-#define regUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0
-#define regUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x0181
-#define regUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0
-#define regUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW 0x0182
-#define regUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0
-#define regUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH 0x0183
-#define regUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0
-#define regUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW 0x0184
-#define regUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0
-#define regUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH 0x0185
-#define regUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0
-#define regUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW 0x0186
-#define regUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0
-#define regUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH 0x0187
-#define regUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0
-#define regUVD_LMI_JPEG_PREEMPT_VMID 0x0188
-#define regUVD_LMI_JPEG_PREEMPT_VMID_BASE_IDX 0
-#define regUVD_LMI_ENC_JPEG_PREEMPT_VMID 0x0189
-#define regUVD_LMI_ENC_JPEG_PREEMPT_VMID_BASE_IDX 0
-#define regUVD_LMI_JPEG2_VMID 0x018a
-#define regUVD_LMI_JPEG2_VMID_BASE_IDX 0
-#define regUVD_LMI_JPEG2_READ_64BIT_BAR_LOW 0x018b
-#define regUVD_LMI_JPEG2_READ_64BIT_BAR_LOW_BASE_IDX 0
-#define regUVD_LMI_JPEG2_READ_64BIT_BAR_HIGH 0x018c
-#define regUVD_LMI_JPEG2_READ_64BIT_BAR_HIGH_BASE_IDX 0
-#define regUVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW 0x018d
-#define regUVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW_BASE_IDX 0
-#define regUVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH 0x018e
-#define regUVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH_BASE_IDX 0
-#define regUVD_LMI_JPEG_CTRL2 0x018f
-#define regUVD_LMI_JPEG_CTRL2_BASE_IDX 0
-#define regUVD_JMI_DEC_SWAP_CNTL 0x0190
-#define regUVD_JMI_DEC_SWAP_CNTL_BASE_IDX 0
-#define regUVD_JMI_ENC_SWAP_CNTL 0x0191
-#define regUVD_JMI_ENC_SWAP_CNTL_BASE_IDX 0
-#define regUVD_JMI_CNTL 0x0192
-#define regUVD_JMI_CNTL_BASE_IDX 0
-#define regUVD_JMI_ATOMIC_CNTL 0x0193
-#define regUVD_JMI_ATOMIC_CNTL_BASE_IDX 0
-#define regUVD_JMI_ATOMIC_CNTL2 0x0194
-#define regUVD_JMI_ATOMIC_CNTL2_BASE_IDX 0
-#define regUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW 0x0195
-#define regUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW_BASE_IDX 0
-#define regUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH 0x0196
-#define regUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH_BASE_IDX 0
-#define regUVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW 0x0197
-#define regUVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW_BASE_IDX 0
-#define regUVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH 0x0198
-#define regUVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH_BASE_IDX 0
-#define regJPEG2_LMI_DROP 0x0199
-#define regJPEG2_LMI_DROP_BASE_IDX 0
-#define regUVD_JMI_HUFF_FENCE_64BIT_BAR_LOW 0x019a
-#define regUVD_JMI_HUFF_FENCE_64BIT_BAR_LOW_BASE_IDX 0
-#define regUVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH 0x019b
-#define regUVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH_BASE_IDX 0
-#define regUVD_JMI_DEC_SWAP_CNTL2 0x019c
-#define regUVD_JMI_DEC_SWAP_CNTL2_BASE_IDX 0
-#define regUVD_JMI_DJPEG_RAS_CNTL 0x019f
-#define regUVD_JMI_DJPEG_RAS_CNTL_BASE_IDX 0
-
-
-// addressBlock: uvd0_uvd_jpeg_common_dec
-// base address: 0x1e700
-#define regJPEG_SOFT_RESET_STATUS 0x01c0
-#define regJPEG_SOFT_RESET_STATUS_BASE_IDX 0
-#define regJPEG_SYS_INT_EN 0x01c1
-#define regJPEG_SYS_INT_EN_BASE_IDX 0
-#define regJPEG_SYS_INT_STATUS 0x01c2
-#define regJPEG_SYS_INT_STATUS_BASE_IDX 0
-#define regJPEG_SYS_INT_ACK 0x01c3
-#define regJPEG_SYS_INT_ACK_BASE_IDX 0
-#define regJPEG_MEMCHECK_SYS_INT_EN 0x01c4
-#define regJPEG_MEMCHECK_SYS_INT_EN_BASE_IDX 0
-#define regJPEG_MEMCHECK_SYS_INT_STAT 0x01c5
-#define regJPEG_MEMCHECK_SYS_INT_STAT_BASE_IDX 0
-#define regJPEG_MEMCHECK_SYS_INT_ACK 0x01c6
-#define regJPEG_MEMCHECK_SYS_INT_ACK_BASE_IDX 0
-#define regJPEG_MASTINT_EN 0x01c8
-#define regJPEG_MASTINT_EN_BASE_IDX 0
-#define regJPEG_IH_CTRL 0x01c9
-#define regJPEG_IH_CTRL_BASE_IDX 0
-#define regJRBBM_ARB_CTRL 0x01cb
-#define regJRBBM_ARB_CTRL_BASE_IDX 0
-
-
-// addressBlock: uvd0_uvd_jpeg_common_sclk_dec
-// base address: 0x1e780
-#define regJPEG_CGC_GATE 0x01e0
-#define regJPEG_CGC_GATE_BASE_IDX 0
-#define regJPEG_CGC_CTRL 0x01e1
-#define regJPEG_CGC_CTRL_BASE_IDX 0
-#define regJPEG_CGC_STATUS 0x01e2
-#define regJPEG_CGC_STATUS_BASE_IDX 0
-#define regJPEG_COMN_CGC_MEM_CTRL 0x01e3
-#define regJPEG_COMN_CGC_MEM_CTRL_BASE_IDX 0
-#define regJPEG_DEC_CGC_MEM_CTRL 0x01e4
-#define regJPEG_DEC_CGC_MEM_CTRL_BASE_IDX 0
-#define regJPEG2_DEC_CGC_MEM_CTRL 0x01e5
-#define regJPEG2_DEC_CGC_MEM_CTRL_BASE_IDX 0
-#define regJPEG_ENC_CGC_MEM_CTRL 0x01e6
-#define regJPEG_ENC_CGC_MEM_CTRL_BASE_IDX 0
-#define regJPEG_SOFT_RESET2 0x01e7
-#define regJPEG_SOFT_RESET2_BASE_IDX 0
-#define regJPEG_PERF_BANK_CONF 0x01e8
-#define regJPEG_PERF_BANK_CONF_BASE_IDX 0
-#define regJPEG_PERF_BANK_EVENT_SEL 0x01e9
-#define regJPEG_PERF_BANK_EVENT_SEL_BASE_IDX 0
-#define regJPEG_PERF_BANK_COUNT0 0x01ea
-#define regJPEG_PERF_BANK_COUNT0_BASE_IDX 0
-#define regJPEG_PERF_BANK_COUNT1 0x01eb
-#define regJPEG_PERF_BANK_COUNT1_BASE_IDX 0
-#define regJPEG_PERF_BANK_COUNT2 0x01ec
-#define regJPEG_PERF_BANK_COUNT2_BASE_IDX 0
-#define regJPEG_PERF_BANK_COUNT3 0x01ed
-#define regJPEG_PERF_BANK_COUNT3_BASE_IDX 0
-
-
-// addressBlock: uvd0_uvd_jpeg_enc_dec
-// base address: 0x1e300
-#define regUVD_JPEG_ENC_INT_EN 0x00c1
-#define regUVD_JPEG_ENC_INT_EN_BASE_IDX 0
-#define regUVD_JPEG_ENC_INT_STATUS 0x00c2
-#define regUVD_JPEG_ENC_INT_STATUS_BASE_IDX 0
-#define regUVD_JPEG_ENC_ENGINE_CNTL 0x00c5
-#define regUVD_JPEG_ENC_ENGINE_CNTL_BASE_IDX 0
-#define regUVD_JPEG_ENC_SCRATCH1 0x00ce
-#define regUVD_JPEG_ENC_SCRATCH1_BASE_IDX 0
-
-
-// addressBlock: uvd0_uvd_jpeg_enc_sclk_dec
-// base address: 0x1e380
-#define regUVD_JPEG_ENC_SPS_INFO 0x00e0
-#define regUVD_JPEG_ENC_SPS_INFO_BASE_IDX 0
-#define regUVD_JPEG_ENC_SPS_INFO1 0x00e1
-#define regUVD_JPEG_ENC_SPS_INFO1_BASE_IDX 0
-#define regUVD_JPEG_ENC_TBL_SIZE 0x00e2
-#define regUVD_JPEG_ENC_TBL_SIZE_BASE_IDX 0
-#define regUVD_JPEG_ENC_TBL_CNTL 0x00e3
-#define regUVD_JPEG_ENC_TBL_CNTL_BASE_IDX 0
-#define regUVD_JPEG_ENC_MC_REQ_CNTL 0x00e4
-#define regUVD_JPEG_ENC_MC_REQ_CNTL_BASE_IDX 0
-#define regUVD_JPEG_ENC_STATUS 0x00e5
-#define regUVD_JPEG_ENC_STATUS_BASE_IDX 0
-#define regUVD_JPEG_ENC_PITCH 0x00e6
-#define regUVD_JPEG_ENC_PITCH_BASE_IDX 0
-#define regUVD_JPEG_ENC_LUMA_BASE 0x00e7
-#define regUVD_JPEG_ENC_LUMA_BASE_BASE_IDX 0
-#define regUVD_JPEG_ENC_CHROMAU_BASE 0x00e8
-#define regUVD_JPEG_ENC_CHROMAU_BASE_BASE_IDX 0
-#define regUVD_JPEG_ENC_CHROMAV_BASE 0x00e9
-#define regUVD_JPEG_ENC_CHROMAV_BASE_BASE_IDX 0
-#define regJPEG_ENC_Y_GFX10_TILING_SURFACE 0x00ea
-#define regJPEG_ENC_Y_GFX10_TILING_SURFACE_BASE_IDX 0
-#define regJPEG_ENC_UV_GFX10_TILING_SURFACE 0x00eb
-#define regJPEG_ENC_UV_GFX10_TILING_SURFACE_BASE_IDX 0
-#define regJPEG_ENC_GFX10_ADDR_CONFIG 0x00ec
-#define regJPEG_ENC_GFX10_ADDR_CONFIG_BASE_IDX 0
-#define regJPEG_ENC_ADDR_MODE 0x00ed
-#define regJPEG_ENC_ADDR_MODE_BASE_IDX 0
-#define regUVD_JPEG_ENC_GPCOM_CMD 0x00ee
-#define regUVD_JPEG_ENC_GPCOM_CMD_BASE_IDX 0
-#define regUVD_JPEG_ENC_GPCOM_DATA0 0x00ef
-#define regUVD_JPEG_ENC_GPCOM_DATA0_BASE_IDX 0
-#define regUVD_JPEG_ENC_GPCOM_DATA1 0x00f0
-#define regUVD_JPEG_ENC_GPCOM_DATA1_BASE_IDX 0
-#define regUVD_JPEG_TBL_DAT0 0x00f1
-#define regUVD_JPEG_TBL_DAT0_BASE_IDX 0
-#define regUVD_JPEG_TBL_DAT1 0x00f2
-#define regUVD_JPEG_TBL_DAT1_BASE_IDX 0
-#define regUVD_JPEG_TBL_IDX 0x00f3
-#define regUVD_JPEG_TBL_IDX_BASE_IDX 0
-#define regUVD_JPEG_ENC_CGC_CNTL 0x00f5
-#define regUVD_JPEG_ENC_CGC_CNTL_BASE_IDX 0
-#define regUVD_JPEG_ENC_SCRATCH0 0x00f6
-#define regUVD_JPEG_ENC_SCRATCH0_BASE_IDX 0
-#define regUVD_JPEG_ENC_SOFT_RST 0x00f7
-#define regUVD_JPEG_ENC_SOFT_RST_BASE_IDX 0
-
-
-// addressBlock: uvd0_uvd_jrbc_dec
-// base address: 0x1e400
-#define regUVD_JRBC_RB_WPTR 0x0100
-#define regUVD_JRBC_RB_WPTR_BASE_IDX 0
-#define regUVD_JRBC_RB_CNTL 0x0101
-#define regUVD_JRBC_RB_CNTL_BASE_IDX 0
-#define regUVD_JRBC_IB_SIZE 0x0102
-#define regUVD_JRBC_IB_SIZE_BASE_IDX 0
-#define regUVD_JRBC_URGENT_CNTL 0x0103
-#define regUVD_JRBC_URGENT_CNTL_BASE_IDX 0
-#define regUVD_JRBC_RB_REF_DATA 0x0104
-#define regUVD_JRBC_RB_REF_DATA_BASE_IDX 0
-#define regUVD_JRBC_RB_COND_RD_TIMER 0x0105
-#define regUVD_JRBC_RB_COND_RD_TIMER_BASE_IDX 0
-#define regUVD_JRBC_SOFT_RESET 0x0108
-#define regUVD_JRBC_SOFT_RESET_BASE_IDX 0
-#define regUVD_JRBC_STATUS 0x0109
-#define regUVD_JRBC_STATUS_BASE_IDX 0
-#define regUVD_JRBC_RB_RPTR 0x010a
-#define regUVD_JRBC_RB_RPTR_BASE_IDX 0
-#define regUVD_JRBC_RB_BUF_STATUS 0x010b
-#define regUVD_JRBC_RB_BUF_STATUS_BASE_IDX 0
-#define regUVD_JRBC_IB_BUF_STATUS 0x010c
-#define regUVD_JRBC_IB_BUF_STATUS_BASE_IDX 0
-#define regUVD_JRBC_IB_SIZE_UPDATE 0x010d
-#define regUVD_JRBC_IB_SIZE_UPDATE_BASE_IDX 0
-#define regUVD_JRBC_IB_COND_RD_TIMER 0x010e
-#define regUVD_JRBC_IB_COND_RD_TIMER_BASE_IDX 0
-#define regUVD_JRBC_IB_REF_DATA 0x010f
-#define regUVD_JRBC_IB_REF_DATA_BASE_IDX 0
-#define regUVD_JPEG_PREEMPT_CMD 0x0110
-#define regUVD_JPEG_PREEMPT_CMD_BASE_IDX 0
-#define regUVD_JPEG_PREEMPT_FENCE_DATA0 0x0111
-#define regUVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX 0
-#define regUVD_JPEG_PREEMPT_FENCE_DATA1 0x0112
-#define regUVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX 0
-#define regUVD_JRBC_RB_SIZE 0x0113
-#define regUVD_JRBC_RB_SIZE_BASE_IDX 0
-#define regUVD_JRBC_SCRATCH0 0x0114
-#define regUVD_JRBC_SCRATCH0_BASE_IDX 0
-
-
-// addressBlock: uvd0_uvd_jrbc_enc_dec
-// base address: 0x1e480
-#define regUVD_JRBC_ENC_RB_WPTR 0x0120
-#define regUVD_JRBC_ENC_RB_WPTR_BASE_IDX 0
-#define regUVD_JRBC_ENC_RB_CNTL 0x0121
-#define regUVD_JRBC_ENC_RB_CNTL_BASE_IDX 0
-#define regUVD_JRBC_ENC_IB_SIZE 0x0122
-#define regUVD_JRBC_ENC_IB_SIZE_BASE_IDX 0
-#define regUVD_JRBC_ENC_URGENT_CNTL 0x0123
-#define regUVD_JRBC_ENC_URGENT_CNTL_BASE_IDX 0
-#define regUVD_JRBC_ENC_RB_REF_DATA 0x0124
-#define regUVD_JRBC_ENC_RB_REF_DATA_BASE_IDX 0
-#define regUVD_JRBC_ENC_RB_COND_RD_TIMER 0x0125
-#define regUVD_JRBC_ENC_RB_COND_RD_TIMER_BASE_IDX 0
-#define regUVD_JRBC_ENC_SOFT_RESET 0x0128
-#define regUVD_JRBC_ENC_SOFT_RESET_BASE_IDX 0
-#define regUVD_JRBC_ENC_STATUS 0x0129
-#define regUVD_JRBC_ENC_STATUS_BASE_IDX 0
-#define regUVD_JRBC_ENC_RB_RPTR 0x012a
-#define regUVD_JRBC_ENC_RB_RPTR_BASE_IDX 0
-#define regUVD_JRBC_ENC_RB_BUF_STATUS 0x012b
-#define regUVD_JRBC_ENC_RB_BUF_STATUS_BASE_IDX 0
-#define regUVD_JRBC_ENC_IB_BUF_STATUS 0x012c
-#define regUVD_JRBC_ENC_IB_BUF_STATUS_BASE_IDX 0
-#define regUVD_JRBC_ENC_IB_SIZE_UPDATE 0x012d
-#define regUVD_JRBC_ENC_IB_SIZE_UPDATE_BASE_IDX 0
-#define regUVD_JRBC_ENC_IB_COND_RD_TIMER 0x012e
-#define regUVD_JRBC_ENC_IB_COND_RD_TIMER_BASE_IDX 0
-#define regUVD_JRBC_ENC_IB_REF_DATA 0x012f
-#define regUVD_JRBC_ENC_IB_REF_DATA_BASE_IDX 0
-#define regUVD_JPEG_ENC_PREEMPT_CMD 0x0130
-#define regUVD_JPEG_ENC_PREEMPT_CMD_BASE_IDX 0
-#define regUVD_JPEG_ENC_PREEMPT_FENCE_DATA0 0x0131
-#define regUVD_JPEG_ENC_PREEMPT_FENCE_DATA0_BASE_IDX 0
-#define regUVD_JPEG_ENC_PREEMPT_FENCE_DATA1 0x0132
-#define regUVD_JPEG_ENC_PREEMPT_FENCE_DATA1_BASE_IDX 0
-#define regUVD_JRBC_ENC_RB_SIZE 0x0133
-#define regUVD_JRBC_ENC_RB_SIZE_BASE_IDX 0
-#define regUVD_JRBC_ENC_SCRATCH0 0x0134
-#define regUVD_JRBC_ENC_SCRATCH0_BASE_IDX 0
-
-
-// addressBlock: uvd0_uvd_mpcdec
-// base address: 0x20310
-#define regUVD_MP_SWAP_CNTL 0x02c4
-#define regUVD_MP_SWAP_CNTL_BASE_IDX 1
-#define regUVD_MP_SWAP_CNTL2 0x02c5
-#define regUVD_MP_SWAP_CNTL2_BASE_IDX 1
-#define regUVD_MPC_LUMA_SRCH 0x02c6
-#define regUVD_MPC_LUMA_SRCH_BASE_IDX 1
-#define regUVD_MPC_LUMA_HIT 0x02c7
-#define regUVD_MPC_LUMA_HIT_BASE_IDX 1
-#define regUVD_MPC_LUMA_HITPEND 0x02c8
-#define regUVD_MPC_LUMA_HITPEND_BASE_IDX 1
-#define regUVD_MPC_CHROMA_SRCH 0x02c9
-#define regUVD_MPC_CHROMA_SRCH_BASE_IDX 1
-#define regUVD_MPC_CHROMA_HIT 0x02ca
-#define regUVD_MPC_CHROMA_HIT_BASE_IDX 1
-#define regUVD_MPC_CHROMA_HITPEND 0x02cb
-#define regUVD_MPC_CHROMA_HITPEND_BASE_IDX 1
-#define regUVD_MPC_CNTL 0x02cc
-#define regUVD_MPC_CNTL_BASE_IDX 1
-#define regUVD_MPC_PITCH 0x02cd
-#define regUVD_MPC_PITCH_BASE_IDX 1
-#define regUVD_MPC_SET_MUXA0 0x02ce
-#define regUVD_MPC_SET_MUXA0_BASE_IDX 1
-#define regUVD_MPC_SET_MUXA1 0x02cf
-#define regUVD_MPC_SET_MUXA1_BASE_IDX 1
-#define regUVD_MPC_SET_MUXB0 0x02d0
-#define regUVD_MPC_SET_MUXB0_BASE_IDX 1
-#define regUVD_MPC_SET_MUXB1 0x02d1
-#define regUVD_MPC_SET_MUXB1_BASE_IDX 1
-#define regUVD_MPC_SET_MUX 0x02d2
-#define regUVD_MPC_SET_MUX_BASE_IDX 1
-#define regUVD_MPC_SET_ALU 0x02d3
-#define regUVD_MPC_SET_ALU_BASE_IDX 1
-#define regUVD_MPC_PERF0 0x02d4
-#define regUVD_MPC_PERF0_BASE_IDX 1
-#define regUVD_MPC_PERF1 0x02d5
-#define regUVD_MPC_PERF1_BASE_IDX 1
-#define regUVD_MPC_IND_INDEX 0x02d6
-#define regUVD_MPC_IND_INDEX_BASE_IDX 1
-#define regUVD_MPC_IND_DATA 0x02d7
-#define regUVD_MPC_IND_DATA_BASE_IDX 1
-
-
-// addressBlock: uvd0_uvd_pg_dec
-// base address: 0x1f800
-#define regUVD_PGFSM_CONFIG 0x0000
-#define regUVD_PGFSM_CONFIG_BASE_IDX 1
-#define regUVD_PGFSM_STATUS 0x0001
-#define regUVD_PGFSM_STATUS_BASE_IDX 1
-#define regUVD_POWER_STATUS 0x0004
-#define regUVD_POWER_STATUS_BASE_IDX 1
-#define regUVD_PG_IND_INDEX 0x0005
-#define regUVD_PG_IND_INDEX_BASE_IDX 1
-#define regUVD_PG_IND_DATA 0x0006
-#define regUVD_PG_IND_DATA_BASE_IDX 1
-#define regCC_UVD_HARVESTING 0x0007
-#define regCC_UVD_HARVESTING_BASE_IDX 1
-#define regUVD_JPEG_POWER_STATUS 0x000a
-#define regUVD_JPEG_POWER_STATUS_BASE_IDX 1
-#define regUVD_DPG_LMA_CTL 0x0011
-#define regUVD_DPG_LMA_CTL_BASE_IDX 1
-#define regUVD_DPG_LMA_DATA 0x0012
-#define regUVD_DPG_LMA_DATA_BASE_IDX 1
-#define regUVD_DPG_LMA_MASK 0x0013
-#define regUVD_DPG_LMA_MASK_BASE_IDX 1
-#define regUVD_DPG_PAUSE 0x0014
-#define regUVD_DPG_PAUSE_BASE_IDX 1
-#define regUVD_SCRATCH1 0x0015
-#define regUVD_SCRATCH1_BASE_IDX 1
-#define regUVD_SCRATCH2 0x0016
-#define regUVD_SCRATCH2_BASE_IDX 1
-#define regUVD_SCRATCH3 0x0017
-#define regUVD_SCRATCH3_BASE_IDX 1
-#define regUVD_SCRATCH4 0x0018
-#define regUVD_SCRATCH4_BASE_IDX 1
-#define regUVD_SCRATCH5 0x0019
-#define regUVD_SCRATCH5_BASE_IDX 1
-#define regUVD_SCRATCH6 0x001a
-#define regUVD_SCRATCH6_BASE_IDX 1
-#define regUVD_SCRATCH7 0x001b
-#define regUVD_SCRATCH7_BASE_IDX 1
-#define regUVD_SCRATCH8 0x001c
-#define regUVD_SCRATCH8_BASE_IDX 1
-#define regUVD_SCRATCH9 0x001d
-#define regUVD_SCRATCH9_BASE_IDX 1
-#define regUVD_SCRATCH10 0x001e
-#define regUVD_SCRATCH10_BASE_IDX 1
-#define regUVD_SCRATCH11 0x001f
-#define regUVD_SCRATCH11_BASE_IDX 1
-#define regUVD_SCRATCH12 0x0020
-#define regUVD_SCRATCH12_BASE_IDX 1
-#define regUVD_SCRATCH13 0x0021
-#define regUVD_SCRATCH13_BASE_IDX 1
-#define regUVD_SCRATCH14 0x0022
-#define regUVD_SCRATCH14_BASE_IDX 1
-#define regUVD_FREE_COUNTER_REG 0x0024
-#define regUVD_FREE_COUNTER_REG_BASE_IDX 1
-#define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x0025
-#define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1
-#define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x0026
-#define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1
-#define regUVD_DPG_VCPU_CACHE_OFFSET0 0x0027
-#define regUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX 1
-#define regUVD_DPG_LMI_VCPU_CACHE_VMID 0x0028
-#define regUVD_DPG_LMI_VCPU_CACHE_VMID_BASE_IDX 1
-#define regUVD_PF_STATUS 0x0039
-#define regUVD_PF_STATUS_BASE_IDX 1
-#define regUVD_FW_VERSION 0x003a
-#define regUVD_FW_VERSION_BASE_IDX 1
-#define regUVD_DPG_CLK_EN_VCPU_REPORT 0x003c
-#define regUVD_DPG_CLK_EN_VCPU_REPORT_BASE_IDX 1
-#define regUVD_GFX8_ADDR_CONFIG 0x0049
-#define regUVD_GFX8_ADDR_CONFIG_BASE_IDX 1
-#define regUVD_GFX10_ADDR_CONFIG 0x004a
-#define regUVD_GFX10_ADDR_CONFIG_BASE_IDX 1
-#define regUVD_GPCNT2_CNTL 0x004b
-#define regUVD_GPCNT2_CNTL_BASE_IDX 1
-#define regUVD_GPCNT2_TARGET_LOWER 0x004c
-#define regUVD_GPCNT2_TARGET_LOWER_BASE_IDX 1
-#define regUVD_GPCNT2_STATUS_LOWER 0x004d
-#define regUVD_GPCNT2_STATUS_LOWER_BASE_IDX 1
-#define regUVD_GPCNT2_TARGET_UPPER 0x004e
-#define regUVD_GPCNT2_TARGET_UPPER_BASE_IDX 1
-#define regUVD_GPCNT2_STATUS_UPPER 0x004f
-#define regUVD_GPCNT2_STATUS_UPPER_BASE_IDX 1
-#define regUVD_GPCNT3_CNTL 0x0050
-#define regUVD_GPCNT3_CNTL_BASE_IDX 1
-#define regUVD_GPCNT3_TARGET_LOWER 0x0051
-#define regUVD_GPCNT3_TARGET_LOWER_BASE_IDX 1
-#define regUVD_GPCNT3_STATUS_LOWER 0x0052
-#define regUVD_GPCNT3_STATUS_LOWER_BASE_IDX 1
-#define regUVD_GPCNT3_TARGET_UPPER 0x0053
-#define regUVD_GPCNT3_TARGET_UPPER_BASE_IDX 1
-#define regUVD_GPCNT3_STATUS_UPPER 0x0054
-#define regUVD_GPCNT3_STATUS_UPPER_BASE_IDX 1
-#define regUVD_VCLK_DS_CNTL 0x0055
-#define regUVD_VCLK_DS_CNTL_BASE_IDX 1
-#define regUVD_DCLK_DS_CNTL 0x0056
-#define regUVD_DCLK_DS_CNTL_BASE_IDX 1
-#define regUVD_RAS_VCPU_VCODEC_STATUS 0x0057
-#define regUVD_RAS_VCPU_VCODEC_STATUS_BASE_IDX 1
-#define regUVD_RAS_MMSCH_FATAL_ERROR 0x0058
-#define regUVD_RAS_MMSCH_FATAL_ERROR_BASE_IDX 1
-#define regUVD_RAS_JPEG0_STATUS 0x0059
-#define regUVD_RAS_JPEG0_STATUS_BASE_IDX 1
-#define regUVD_RAS_JPEG1_STATUS 0x005a
-#define regUVD_RAS_JPEG1_STATUS_BASE_IDX 1
-#define regUVD_RAS_CNTL_PMI_ARB 0x005b
-#define regUVD_RAS_CNTL_PMI_ARB_BASE_IDX 1
-
-
-// addressBlock: uvd0_uvd_rbcdec
-// base address: 0x20370
-#define regUVD_RBC_IB_SIZE 0x02dc
-#define regUVD_RBC_IB_SIZE_BASE_IDX 1
-#define regUVD_RBC_IB_SIZE_UPDATE 0x02dd
-#define regUVD_RBC_IB_SIZE_UPDATE_BASE_IDX 1
-#define regUVD_RBC_RB_CNTL 0x02de
-#define regUVD_RBC_RB_CNTL_BASE_IDX 1
-#define regUVD_RBC_RB_RPTR_ADDR 0x02df
-#define regUVD_RBC_RB_RPTR_ADDR_BASE_IDX 1
-#define regUVD_RBC_RB_RPTR 0x02e0
-#define regUVD_RBC_RB_RPTR_BASE_IDX 1
-#define regUVD_RBC_RB_WPTR 0x02e1
-#define regUVD_RBC_RB_WPTR_BASE_IDX 1
-#define regUVD_RBC_VCPU_ACCESS 0x02e2
-#define regUVD_RBC_VCPU_ACCESS_BASE_IDX 1
-#define regUVD_FW_SEMAPHORE_CNTL 0x02e3
-#define regUVD_FW_SEMAPHORE_CNTL_BASE_IDX 1
-#define regUVD_RBC_READ_REQ_URGENT_CNTL 0x02e5
-#define regUVD_RBC_READ_REQ_URGENT_CNTL_BASE_IDX 1
-#define regUVD_RBC_RB_WPTR_CNTL 0x02e6
-#define regUVD_RBC_RB_WPTR_CNTL_BASE_IDX 1
-#define regUVD_RBC_WPTR_STATUS 0x02e7
-#define regUVD_RBC_WPTR_STATUS_BASE_IDX 1
-#define regUVD_RBC_WPTR_POLL_CNTL 0x02e8
-#define regUVD_RBC_WPTR_POLL_CNTL_BASE_IDX 1
-#define regUVD_RBC_WPTR_POLL_ADDR 0x02e9
-#define regUVD_RBC_WPTR_POLL_ADDR_BASE_IDX 1
-#define regUVD_SEMA_CMD 0x02ea
-#define regUVD_SEMA_CMD_BASE_IDX 1
-#define regUVD_SEMA_ADDR_LOW 0x02eb
-#define regUVD_SEMA_ADDR_LOW_BASE_IDX 1
-#define regUVD_SEMA_ADDR_HIGH 0x02ec
-#define regUVD_SEMA_ADDR_HIGH_BASE_IDX 1
-#define regUVD_ENGINE_CNTL 0x02ed
-#define regUVD_ENGINE_CNTL_BASE_IDX 1
-#define regUVD_SEMA_TIMEOUT_STATUS 0x02ee
-#define regUVD_SEMA_TIMEOUT_STATUS_BASE_IDX 1
-#define regUVD_SEMA_CNTL 0x02ef
-#define regUVD_SEMA_CNTL_BASE_IDX 1
-#define regUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x02f0
-#define regUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX 1
-#define regUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x02f1
-#define regUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL_BASE_IDX 1
-#define regUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x02f2
-#define regUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX 1
-#define regUVD_JOB_START 0x02f3
-#define regUVD_JOB_START_BASE_IDX 1
-#define regUVD_RBC_BUF_STATUS 0x02f4
-#define regUVD_RBC_BUF_STATUS_BASE_IDX 1
-#define regUVD_RBC_SWAP_CNTL 0x02f5
-#define regUVD_RBC_SWAP_CNTL_BASE_IDX 1
-
-
-// addressBlock: uvd0_uvddec
-// base address: 0x1fa00
-#define regUVD_STATUS 0x0080
-#define regUVD_STATUS_BASE_IDX 1
-#define regUVD_ENC_PIPE_BUSY 0x0081
-#define regUVD_ENC_PIPE_BUSY_BASE_IDX 1
-#define regUVD_FW_POWER_STATUS 0x0082
-#define regUVD_FW_POWER_STATUS_BASE_IDX 1
-#define regUVD_CNTL 0x0083
-#define regUVD_CNTL_BASE_IDX 1
-#define regUVD_SOFT_RESET 0x0084
-#define regUVD_SOFT_RESET_BASE_IDX 1
-#define regUVD_SOFT_RESET2 0x0085
-#define regUVD_SOFT_RESET2_BASE_IDX 1
-#define regUVD_MMSCH_SOFT_RESET 0x0086
-#define regUVD_MMSCH_SOFT_RESET_BASE_IDX 1
-#define regUVD_WIG_CTRL 0x0087
-#define regUVD_WIG_CTRL_BASE_IDX 1
-#define regUVD_CGC_GATE 0x0088
-#define regUVD_CGC_GATE_BASE_IDX 1
-#define regUVD_CGC_STATUS 0x0089
-#define regUVD_CGC_STATUS_BASE_IDX 1
-#define regUVD_CGC_CTRL 0x008a
-#define regUVD_CGC_CTRL_BASE_IDX 1
-#define regUVD_CGC_UDEC_STATUS 0x008b
-#define regUVD_CGC_UDEC_STATUS_BASE_IDX 1
-#define regUVD_SUVD_CGC_GATE 0x008c
-#define regUVD_SUVD_CGC_GATE_BASE_IDX 1
-#define regUVD_SUVD_CGC_STATUS 0x008d
-#define regUVD_SUVD_CGC_STATUS_BASE_IDX 1
-#define regUVD_SUVD_CGC_CTRL 0x008e
-#define regUVD_SUVD_CGC_CTRL_BASE_IDX 1
-#define regUVD_GPCOM_VCPU_CMD 0x008f
-#define regUVD_GPCOM_VCPU_CMD_BASE_IDX 1
-#define regUVD_GPCOM_VCPU_DATA0 0x0090
-#define regUVD_GPCOM_VCPU_DATA0_BASE_IDX 1
-#define regUVD_GPCOM_VCPU_DATA1 0x0091
-#define regUVD_GPCOM_VCPU_DATA1_BASE_IDX 1
-#define regUVD_GPCOM_SYS_CMD 0x0092
-#define regUVD_GPCOM_SYS_CMD_BASE_IDX 1
-#define regUVD_GPCOM_SYS_DATA0 0x0093
-#define regUVD_GPCOM_SYS_DATA0_BASE_IDX 1
-#define regUVD_GPCOM_SYS_DATA1 0x0094
-#define regUVD_GPCOM_SYS_DATA1_BASE_IDX 1
-#define regUVD_VCPU_INT_EN 0x0095
-#define regUVD_VCPU_INT_EN_BASE_IDX 1
-#define regUVD_VCPU_INT_STATUS 0x0096
-#define regUVD_VCPU_INT_STATUS_BASE_IDX 1
-#define regUVD_VCPU_INT_ACK 0x0097
-#define regUVD_VCPU_INT_ACK_BASE_IDX 1
-#define regUVD_VCPU_INT_ROUTE 0x0098
-#define regUVD_VCPU_INT_ROUTE_BASE_IDX 1
-#define regUVD_DRV_FW_MSG 0x0099
-#define regUVD_DRV_FW_MSG_BASE_IDX 1
-#define regUVD_FW_DRV_MSG_ACK 0x009a
-#define regUVD_FW_DRV_MSG_ACK_BASE_IDX 1
-#define regUVD_SUVD_INT_EN 0x009b
-#define regUVD_SUVD_INT_EN_BASE_IDX 1
-#define regUVD_SUVD_INT_STATUS 0x009c
-#define regUVD_SUVD_INT_STATUS_BASE_IDX 1
-#define regUVD_SUVD_INT_ACK 0x009d
-#define regUVD_SUVD_INT_ACK_BASE_IDX 1
-#define regUVD_ENC_VCPU_INT_EN 0x009e
-#define regUVD_ENC_VCPU_INT_EN_BASE_IDX 1
-#define regUVD_ENC_VCPU_INT_STATUS 0x009f
-#define regUVD_ENC_VCPU_INT_STATUS_BASE_IDX 1
-#define regUVD_ENC_VCPU_INT_ACK 0x00a0
-#define regUVD_ENC_VCPU_INT_ACK_BASE_IDX 1
-#define regUVD_MASTINT_EN 0x00a1
-#define regUVD_MASTINT_EN_BASE_IDX 1
-#define regUVD_SYS_INT_EN 0x00a2
-#define regUVD_SYS_INT_EN_BASE_IDX 1
-#define regUVD_SYS_INT_STATUS 0x00a3
-#define regUVD_SYS_INT_STATUS_BASE_IDX 1
-#define regUVD_SYS_INT_ACK 0x00a4
-#define regUVD_SYS_INT_ACK_BASE_IDX 1
-#define regUVD_JOB_DONE 0x00a5
-#define regUVD_JOB_DONE_BASE_IDX 1
-#define regUVD_CBUF_ID 0x00a6
-#define regUVD_CBUF_ID_BASE_IDX 1
-#define regUVD_CONTEXT_ID 0x00a7
-#define regUVD_CONTEXT_ID_BASE_IDX 1
-#define regUVD_CONTEXT_ID2 0x00a8
-#define regUVD_CONTEXT_ID2_BASE_IDX 1
-#define regUVD_NO_OP 0x00a9
-#define regUVD_NO_OP_BASE_IDX 1
-#define regUVD_RB_BASE_LO 0x00aa
-#define regUVD_RB_BASE_LO_BASE_IDX 1
-#define regUVD_RB_BASE_HI 0x00ab
-#define regUVD_RB_BASE_HI_BASE_IDX 1
-#define regUVD_RB_SIZE 0x00ac
-#define regUVD_RB_SIZE_BASE_IDX 1
-#define regUVD_RB_RPTR 0x00ad
-#define regUVD_RB_RPTR_BASE_IDX 1
-#define regUVD_RB_WPTR 0x00ae
-#define regUVD_RB_WPTR_BASE_IDX 1
-#define regUVD_RB_BASE_LO2 0x00af
-#define regUVD_RB_BASE_LO2_BASE_IDX 1
-#define regUVD_RB_BASE_HI2 0x00b0
-#define regUVD_RB_BASE_HI2_BASE_IDX 1
-#define regUVD_RB_SIZE2 0x00b1
-#define regUVD_RB_SIZE2_BASE_IDX 1
-#define regUVD_RB_RPTR2 0x00b2
-#define regUVD_RB_RPTR2_BASE_IDX 1
-#define regUVD_RB_WPTR2 0x00b3
-#define regUVD_RB_WPTR2_BASE_IDX 1
-#define regUVD_RB_BASE_LO3 0x00b4
-#define regUVD_RB_BASE_LO3_BASE_IDX 1
-#define regUVD_RB_BASE_HI3 0x00b5
-#define regUVD_RB_BASE_HI3_BASE_IDX 1
-#define regUVD_RB_SIZE3 0x00b6
-#define regUVD_RB_SIZE3_BASE_IDX 1
-#define regUVD_RB_RPTR3 0x00b7
-#define regUVD_RB_RPTR3_BASE_IDX 1
-#define regUVD_RB_WPTR3 0x00b8
-#define regUVD_RB_WPTR3_BASE_IDX 1
-#define regUVD_RB_BASE_LO4 0x00b9
-#define regUVD_RB_BASE_LO4_BASE_IDX 1
-#define regUVD_RB_BASE_HI4 0x00ba
-#define regUVD_RB_BASE_HI4_BASE_IDX 1
-#define regUVD_RB_SIZE4 0x00bb
-#define regUVD_RB_SIZE4_BASE_IDX 1
-#define regUVD_RB_RPTR4 0x00bc
-#define regUVD_RB_RPTR4_BASE_IDX 1
-#define regUVD_RB_WPTR4 0x00bd
-#define regUVD_RB_WPTR4_BASE_IDX 1
-#define regUVD_OUT_RB_BASE_LO 0x00be
-#define regUVD_OUT_RB_BASE_LO_BASE_IDX 1
-#define regUVD_OUT_RB_BASE_HI 0x00bf
-#define regUVD_OUT_RB_BASE_HI_BASE_IDX 1
-#define regUVD_OUT_RB_SIZE 0x00c0
-#define regUVD_OUT_RB_SIZE_BASE_IDX 1
-#define regUVD_OUT_RB_RPTR 0x00c1
-#define regUVD_OUT_RB_RPTR_BASE_IDX 1
-#define regUVD_OUT_RB_WPTR 0x00c2
-#define regUVD_OUT_RB_WPTR_BASE_IDX 1
-#define regUVD_IOV_MAILBOX 0x00c4
-#define regUVD_IOV_MAILBOX_BASE_IDX 1
-#define regUVD_IOV_MAILBOX_RESP 0x00c5
-#define regUVD_IOV_MAILBOX_RESP_BASE_IDX 1
-#define regUVD_RB_ARB_CTRL 0x00c6
-#define regUVD_RB_ARB_CTRL_BASE_IDX 1
-#define regUVD_CTX_INDEX 0x00c7
-#define regUVD_CTX_INDEX_BASE_IDX 1
-#define regUVD_CTX_DATA 0x00c8
-#define regUVD_CTX_DATA_BASE_IDX 1
-#define regUVD_CXW_WR 0x00c9
-#define regUVD_CXW_WR_BASE_IDX 1
-#define regUVD_CXW_WR_INT_ID 0x00ca
-#define regUVD_CXW_WR_INT_ID_BASE_IDX 1
-#define regUVD_CXW_WR_INT_CTX_ID 0x00cb
-#define regUVD_CXW_WR_INT_CTX_ID_BASE_IDX 1
-#define regUVD_CXW_INT_ID 0x00cc
-#define regUVD_CXW_INT_ID_BASE_IDX 1
-#define regUVD_MPEG2_ERROR 0x00cd
-#define regUVD_MPEG2_ERROR_BASE_IDX 1
-#define regUVD_TOP_CTRL 0x00cf
-#define regUVD_TOP_CTRL_BASE_IDX 1
-#define regUVD_YBASE 0x00d0
-#define regUVD_YBASE_BASE_IDX 1
-#define regUVD_UVBASE 0x00d1
-#define regUVD_UVBASE_BASE_IDX 1
-#define regUVD_PITCH 0x00d2
-#define regUVD_PITCH_BASE_IDX 1
-#define regUVD_WIDTH 0x00d3
-#define regUVD_WIDTH_BASE_IDX 1
-#define regUVD_HEIGHT 0x00d4
-#define regUVD_HEIGHT_BASE_IDX 1
-#define regUVD_PICCOUNT 0x00d5
-#define regUVD_PICCOUNT_BASE_IDX 1
-#define regUVD_MPRD_INITIAL_XY 0x00d6
-#define regUVD_MPRD_INITIAL_XY_BASE_IDX 1
-#define regUVD_MPEG2_CTRL 0x00d7
-#define regUVD_MPEG2_CTRL_BASE_IDX 1
-#define regUVD_MB_CTL_BUF_BASE 0x00d8
-#define regUVD_MB_CTL_BUF_BASE_BASE_IDX 1
-#define regUVD_PIC_CTL_BUF_BASE 0x00d9
-#define regUVD_PIC_CTL_BUF_BASE_BASE_IDX 1
-#define regUVD_DXVA_BUF_SIZE 0x00da
-#define regUVD_DXVA_BUF_SIZE_BASE_IDX 1
-#define regUVD_SCRATCH_NP 0x00db
-#define regUVD_SCRATCH_NP_BASE_IDX 1
-#define regUVD_CLK_SWT_HANDSHAKE 0x00dc
-#define regUVD_CLK_SWT_HANDSHAKE_BASE_IDX 1
-#define regUVD_VERSION 0x00dd
-#define regUVD_VERSION_BASE_IDX 1
-#define regUVD_GP_SCRATCH0 0x00de
-#define regUVD_GP_SCRATCH0_BASE_IDX 1
-#define regUVD_GP_SCRATCH1 0x00df
-#define regUVD_GP_SCRATCH1_BASE_IDX 1
-#define regUVD_GP_SCRATCH2 0x00e0
-#define regUVD_GP_SCRATCH2_BASE_IDX 1
-#define regUVD_GP_SCRATCH3 0x00e1
-#define regUVD_GP_SCRATCH3_BASE_IDX 1
-#define regUVD_GP_SCRATCH4 0x00e2
-#define regUVD_GP_SCRATCH4_BASE_IDX 1
-#define regUVD_GP_SCRATCH5 0x00e3
-#define regUVD_GP_SCRATCH5_BASE_IDX 1
-#define regUVD_GP_SCRATCH6 0x00e4
-#define regUVD_GP_SCRATCH6_BASE_IDX 1
-#define regUVD_GP_SCRATCH7 0x00e5
-#define regUVD_GP_SCRATCH7_BASE_IDX 1
-#define regUVD_GP_SCRATCH8 0x00e6
-#define regUVD_GP_SCRATCH8_BASE_IDX 1
-#define regUVD_GP_SCRATCH9 0x00e7
-#define regUVD_GP_SCRATCH9_BASE_IDX 1
-#define regUVD_GP_SCRATCH10 0x00e8
-#define regUVD_GP_SCRATCH10_BASE_IDX 1
-#define regUVD_GP_SCRATCH11 0x00e9
-#define regUVD_GP_SCRATCH11_BASE_IDX 1
-#define regUVD_GP_SCRATCH12 0x00ea
-#define regUVD_GP_SCRATCH12_BASE_IDX 1
-#define regUVD_GP_SCRATCH13 0x00eb
-#define regUVD_GP_SCRATCH13_BASE_IDX 1
-#define regUVD_GP_SCRATCH14 0x00ec
-#define regUVD_GP_SCRATCH14_BASE_IDX 1
-#define regUVD_GP_SCRATCH15 0x00ed
-#define regUVD_GP_SCRATCH15_BASE_IDX 1
-#define regUVD_GP_SCRATCH16 0x00ee
-#define regUVD_GP_SCRATCH16_BASE_IDX 1
-#define regUVD_GP_SCRATCH17 0x00ef
-#define regUVD_GP_SCRATCH17_BASE_IDX 1
-#define regUVD_GP_SCRATCH18 0x00f0
-#define regUVD_GP_SCRATCH18_BASE_IDX 1
-#define regUVD_GP_SCRATCH19 0x00f1
-#define regUVD_GP_SCRATCH19_BASE_IDX 1
-#define regUVD_GP_SCRATCH20 0x00f2
-#define regUVD_GP_SCRATCH20_BASE_IDX 1
-#define regUVD_GP_SCRATCH21 0x00f3
-#define regUVD_GP_SCRATCH21_BASE_IDX 1
-#define regUVD_GP_SCRATCH22 0x00f4
-#define regUVD_GP_SCRATCH22_BASE_IDX 1
-#define regUVD_GP_SCRATCH23 0x00f5
-#define regUVD_GP_SCRATCH23_BASE_IDX 1
-
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h
deleted file mode 100644
index f61a5bbb1..000000000
--- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h
+++ /dev/null
@@ -1,4535 +0,0 @@
-/*
- * Copyright 2020 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef _vcn_2_6_0_SH_MASK_HEADER
-#define _vcn_2_6_0_SH_MASK_HEADER
-
-
-// addressBlock: uvd0_ecpudec
-//UVD_VCPU_CACHE_OFFSET0
-#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0
-#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x001FFFFFL
-//UVD_VCPU_CACHE_SIZE0
-#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0
-#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x001FFFFFL
-//UVD_VCPU_CACHE_OFFSET1
-#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0
-#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x001FFFFFL
-//UVD_VCPU_CACHE_SIZE1
-#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0
-#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x001FFFFFL
-//UVD_VCPU_CACHE_OFFSET2
-#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0
-#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x001FFFFFL
-//UVD_VCPU_CACHE_SIZE2
-#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0
-#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x001FFFFFL
-//UVD_VCPU_CACHE_OFFSET3
-#define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3__SHIFT 0x0
-#define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3_MASK 0x001FFFFFL
-//UVD_VCPU_CACHE_SIZE3
-#define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3__SHIFT 0x0
-#define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3_MASK 0x001FFFFFL
-//UVD_VCPU_CACHE_OFFSET4
-#define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4__SHIFT 0x0
-#define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4_MASK 0x001FFFFFL
-//UVD_VCPU_CACHE_SIZE4
-#define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4__SHIFT 0x0
-#define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4_MASK 0x001FFFFFL
-//UVD_VCPU_CACHE_OFFSET5
-#define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5__SHIFT 0x0
-#define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5_MASK 0x001FFFFFL
-//UVD_VCPU_CACHE_SIZE5
-#define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5__SHIFT 0x0
-#define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5_MASK 0x001FFFFFL
-//UVD_VCPU_CACHE_OFFSET6
-#define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6__SHIFT 0x0
-#define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6_MASK 0x001FFFFFL
-//UVD_VCPU_CACHE_SIZE6
-#define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6__SHIFT 0x0
-#define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6_MASK 0x001FFFFFL
-//UVD_VCPU_CACHE_OFFSET7
-#define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7__SHIFT 0x0
-#define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7_MASK 0x001FFFFFL
-//UVD_VCPU_CACHE_SIZE7
-#define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7__SHIFT 0x0
-#define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7_MASK 0x001FFFFFL
-//UVD_VCPU_CACHE_OFFSET8
-#define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8__SHIFT 0x0
-#define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8_MASK 0x001FFFFFL
-//UVD_VCPU_CACHE_SIZE8
-#define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8__SHIFT 0x0
-#define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8_MASK 0x001FFFFFL
-//UVD_VCPU_NONCACHE_OFFSET0
-#define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0__SHIFT 0x0
-#define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0_MASK 0x01FFFFFFL
-//UVD_VCPU_NONCACHE_SIZE0
-#define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0__SHIFT 0x0
-#define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0_MASK 0x001FFFFFL
-//UVD_VCPU_NONCACHE_OFFSET1
-#define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1__SHIFT 0x0
-#define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1_MASK 0x01FFFFFFL
-//UVD_VCPU_NONCACHE_SIZE1
-#define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1__SHIFT 0x0
-#define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1_MASK 0x001FFFFFL
-//UVD_VCPU_CNTL
-#define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0
-#define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5
-#define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6
-#define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7
-#define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8
-#define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9
-#define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa
-#define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb
-#define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10
-#define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12
-#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14
-#define UVD_VCPU_CNTL__BLK_RST__SHIFT 0x1c
-#define UVD_VCPU_CNTL__IRQ_ERR_MASK 0x0000000FL
-#define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x00000020L
-#define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x00000040L
-#define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00000080L
-#define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x00000100L
-#define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L
-#define UVD_VCPU_CNTL__TRCE_EN_MASK 0x00000400L
-#define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x00001800L
-#define UVD_VCPU_CNTL__JTAG_EN_MASK 0x00010000L
-#define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x00040000L
-#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L
-#define UVD_VCPU_CNTL__BLK_RST_MASK 0x10000000L
-//UVD_VCPU_PRID
-#define UVD_VCPU_PRID__PRID__SHIFT 0x0
-#define UVD_VCPU_PRID__PRID_MASK 0x0000FFFFL
-//UVD_VCPU_TRCE
-#define UVD_VCPU_TRCE__PC__SHIFT 0x0
-#define UVD_VCPU_TRCE__PC_MASK 0x0FFFFFFFL
-//UVD_VCPU_TRCE_RD
-#define UVD_VCPU_TRCE_RD__DATA__SHIFT 0x0
-#define UVD_VCPU_TRCE_RD__DATA_MASK 0xFFFFFFFFL
-//UVD_VCPU_IND_INDEX
-#define UVD_VCPU_IND_INDEX__INDEX__SHIFT 0x0
-#define UVD_VCPU_IND_INDEX__INDEX_MASK 0x000001FFL
-//UVD_VCPU_IND_DATA
-#define UVD_VCPU_IND_DATA__DATA__SHIFT 0x0
-#define UVD_VCPU_IND_DATA__DATA_MASK 0xFFFFFFFFL
-
-
-// addressBlock: uvd0_jpegnpdec
-//UVD_JPEG_CNTL
-#define UVD_JPEG_CNTL__REQUEST_EN__SHIFT 0x1
-#define UVD_JPEG_CNTL__ERR_RST_EN__SHIFT 0x2
-#define UVD_JPEG_CNTL__HUFF_SPEED_EN__SHIFT 0x3
-#define UVD_JPEG_CNTL__HUFF_SPEED_STATUS__SHIFT 0x4
-#define UVD_JPEG_CNTL__REQUEST_EN_MASK 0x00000002L
-#define UVD_JPEG_CNTL__ERR_RST_EN_MASK 0x00000004L
-#define UVD_JPEG_CNTL__HUFF_SPEED_EN_MASK 0x00000008L
-#define UVD_JPEG_CNTL__HUFF_SPEED_STATUS_MASK 0x00000010L
-//UVD_JPEG_RB_BASE
-#define UVD_JPEG_RB_BASE__RB_BYTE_OFF__SHIFT 0x0
-#define UVD_JPEG_RB_BASE__RB_BASE__SHIFT 0x6
-#define UVD_JPEG_RB_BASE__RB_BYTE_OFF_MASK 0x0000003FL
-#define UVD_JPEG_RB_BASE__RB_BASE_MASK 0xFFFFFFC0L
-//UVD_JPEG_RB_WPTR
-#define UVD_JPEG_RB_WPTR__RB_WPTR__SHIFT 0x4
-#define UVD_JPEG_RB_WPTR__RB_WPTR_MASK 0x3FFFFFF0L
-//UVD_JPEG_RB_RPTR
-#define UVD_JPEG_RB_RPTR__RB_RPTR__SHIFT 0x4
-#define UVD_JPEG_RB_RPTR__RB_RPTR_MASK 0x3FFFFFF0L
-//UVD_JPEG_RB_SIZE
-#define UVD_JPEG_RB_SIZE__RB_SIZE__SHIFT 0x4
-#define UVD_JPEG_RB_SIZE__RB_SIZE_MASK 0x3FFFFFF0L
-//UVD_JPEG_DEC_CNT
-#define UVD_JPEG_DEC_CNT__DECODE_COUNT__SHIFT 0x0
-#define UVD_JPEG_DEC_CNT__DECODE_COUNT_MASK 0xFFFFFFFFL
-//UVD_JPEG_SPS_INFO
-#define UVD_JPEG_SPS_INFO__PIC_WIDTH__SHIFT 0x0
-#define UVD_JPEG_SPS_INFO__PIC_HEIGHT__SHIFT 0x10
-#define UVD_JPEG_SPS_INFO__PIC_WIDTH_MASK 0x0000FFFFL
-#define UVD_JPEG_SPS_INFO__PIC_HEIGHT_MASK 0xFFFF0000L
-//UVD_JPEG_SPS1_INFO
-#define UVD_JPEG_SPS1_INFO__CHROMA_FORMAT_IDC__SHIFT 0x0
-#define UVD_JPEG_SPS1_INFO__YUV422_SUBFORMAT__SHIFT 0x3
-#define UVD_JPEG_SPS1_INFO__OUT_FMT_422__SHIFT 0x4
-#define UVD_JPEG_SPS1_INFO__CHROMA_FORMAT_IDC_MASK 0x00000007L
-#define UVD_JPEG_SPS1_INFO__YUV422_SUBFORMAT_MASK 0x00000008L
-#define UVD_JPEG_SPS1_INFO__OUT_FMT_422_MASK 0x00000010L
-//UVD_JPEG_RE_TIMER
-#define UVD_JPEG_RE_TIMER__TIMER_OUT__SHIFT 0x0
-#define UVD_JPEG_RE_TIMER__TIMER_OUT_EN__SHIFT 0x10
-#define UVD_JPEG_RE_TIMER__TIMER_OUT_MASK 0x000000FFL
-#define UVD_JPEG_RE_TIMER__TIMER_OUT_EN_MASK 0x00010000L
-//UVD_JPEG_DEC_SCRATCH0
-#define UVD_JPEG_DEC_SCRATCH0__SCRATCH0__SHIFT 0x0
-#define UVD_JPEG_DEC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL
-//UVD_JPEG_INT_EN
-#define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN__SHIFT 0x0
-#define UVD_JPEG_INT_EN__JOB_AVAIL_EN__SHIFT 0x1
-#define UVD_JPEG_INT_EN__FENCE_VAL_EN__SHIFT 0x2
-#define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN__SHIFT 0x6
-#define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN__SHIFT 0x7
-#define UVD_JPEG_INT_EN__EOI_ERR_EN__SHIFT 0x8
-#define UVD_JPEG_INT_EN__HFM_ERR_EN__SHIFT 0x9
-#define UVD_JPEG_INT_EN__RST_ERR_EN__SHIFT 0xa
-#define UVD_JPEG_INT_EN__ECS_MK_ERR_EN__SHIFT 0xb
-#define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN__SHIFT 0xc
-#define UVD_JPEG_INT_EN__MARKER_ERR_EN__SHIFT 0xd
-#define UVD_JPEG_INT_EN__FMT_ERR_EN__SHIFT 0xe
-#define UVD_JPEG_INT_EN__PROFILE_ERR_EN__SHIFT 0xf
-#define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN_MASK 0x00000001L
-#define UVD_JPEG_INT_EN__JOB_AVAIL_EN_MASK 0x00000002L
-#define UVD_JPEG_INT_EN__FENCE_VAL_EN_MASK 0x00000004L
-#define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN_MASK 0x00000040L
-#define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN_MASK 0x00000080L
-#define UVD_JPEG_INT_EN__EOI_ERR_EN_MASK 0x00000100L
-#define UVD_JPEG_INT_EN__HFM_ERR_EN_MASK 0x00000200L
-#define UVD_JPEG_INT_EN__RST_ERR_EN_MASK 0x00000400L
-#define UVD_JPEG_INT_EN__ECS_MK_ERR_EN_MASK 0x00000800L
-#define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN_MASK 0x00001000L
-#define UVD_JPEG_INT_EN__MARKER_ERR_EN_MASK 0x00002000L
-#define UVD_JPEG_INT_EN__FMT_ERR_EN_MASK 0x00004000L
-#define UVD_JPEG_INT_EN__PROFILE_ERR_EN_MASK 0x00008000L
-//UVD_JPEG_INT_STAT
-#define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT__SHIFT 0x0
-#define UVD_JPEG_INT_STAT__JOB_AVAIL_INT__SHIFT 0x1
-#define UVD_JPEG_INT_STAT__FENCE_VAL_INT__SHIFT 0x2
-#define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT__SHIFT 0x6
-#define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT__SHIFT 0x7
-#define UVD_JPEG_INT_STAT__EOI_ERR_INT__SHIFT 0x8
-#define UVD_JPEG_INT_STAT__HFM_ERR_INT__SHIFT 0x9
-#define UVD_JPEG_INT_STAT__RST_ERR_INT__SHIFT 0xa
-#define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT__SHIFT 0xb
-#define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT__SHIFT 0xc
-#define UVD_JPEG_INT_STAT__MARKER_ERR_INT__SHIFT 0xd
-#define UVD_JPEG_INT_STAT__FMT_ERR_INT__SHIFT 0xe
-#define UVD_JPEG_INT_STAT__PROFILE_ERR_INT__SHIFT 0xf
-#define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT_MASK 0x00000001L
-#define UVD_JPEG_INT_STAT__JOB_AVAIL_INT_MASK 0x00000002L
-#define UVD_JPEG_INT_STAT__FENCE_VAL_INT_MASK 0x00000004L
-#define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT_MASK 0x00000040L
-#define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT_MASK 0x00000080L
-#define UVD_JPEG_INT_STAT__EOI_ERR_INT_MASK 0x00000100L
-#define UVD_JPEG_INT_STAT__HFM_ERR_INT_MASK 0x00000200L
-#define UVD_JPEG_INT_STAT__RST_ERR_INT_MASK 0x00000400L
-#define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT_MASK 0x00000800L
-#define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT_MASK 0x00001000L
-#define UVD_JPEG_INT_STAT__MARKER_ERR_INT_MASK 0x00002000L
-#define UVD_JPEG_INT_STAT__FMT_ERR_INT_MASK 0x00004000L
-#define UVD_JPEG_INT_STAT__PROFILE_ERR_INT_MASK 0x00008000L
-//UVD_JPEG_TIER_CNTL0
-#define UVD_JPEG_TIER_CNTL0__TIER_SEL__SHIFT 0x0
-#define UVD_JPEG_TIER_CNTL0__Y_COMP_ID__SHIFT 0x2
-#define UVD_JPEG_TIER_CNTL0__U_COMP_ID__SHIFT 0x4
-#define UVD_JPEG_TIER_CNTL0__V_COMP_ID__SHIFT 0x6
-#define UVD_JPEG_TIER_CNTL0__Y_H_SAMP_FAC__SHIFT 0x8
-#define UVD_JPEG_TIER_CNTL0__Y_V_SAMP_FAC__SHIFT 0xb
-#define UVD_JPEG_TIER_CNTL0__U_H_SAMP_FAC__SHIFT 0xe
-#define UVD_JPEG_TIER_CNTL0__U_V_SAMP_FAC__SHIFT 0x11
-#define UVD_JPEG_TIER_CNTL0__V_H_SAMP_FAC__SHIFT 0x14
-#define UVD_JPEG_TIER_CNTL0__V_V_SAMP_FAC__SHIFT 0x17
-#define UVD_JPEG_TIER_CNTL0__Y_TQ__SHIFT 0x1a
-#define UVD_JPEG_TIER_CNTL0__U_TQ__SHIFT 0x1c
-#define UVD_JPEG_TIER_CNTL0__V_TQ__SHIFT 0x1e
-#define UVD_JPEG_TIER_CNTL0__TIER_SEL_MASK 0x00000003L
-#define UVD_JPEG_TIER_CNTL0__Y_COMP_ID_MASK 0x0000000CL
-#define UVD_JPEG_TIER_CNTL0__U_COMP_ID_MASK 0x00000030L
-#define UVD_JPEG_TIER_CNTL0__V_COMP_ID_MASK 0x000000C0L
-#define UVD_JPEG_TIER_CNTL0__Y_H_SAMP_FAC_MASK 0x00000700L
-#define UVD_JPEG_TIER_CNTL0__Y_V_SAMP_FAC_MASK 0x00003800L
-#define UVD_JPEG_TIER_CNTL0__U_H_SAMP_FAC_MASK 0x0001C000L
-#define UVD_JPEG_TIER_CNTL0__U_V_SAMP_FAC_MASK 0x000E0000L
-#define UVD_JPEG_TIER_CNTL0__V_H_SAMP_FAC_MASK 0x00700000L
-#define UVD_JPEG_TIER_CNTL0__V_V_SAMP_FAC_MASK 0x03800000L
-#define UVD_JPEG_TIER_CNTL0__Y_TQ_MASK 0x0C000000L
-#define UVD_JPEG_TIER_CNTL0__U_TQ_MASK 0x30000000L
-#define UVD_JPEG_TIER_CNTL0__V_TQ_MASK 0xC0000000L
-//UVD_JPEG_TIER_CNTL1
-#define UVD_JPEG_TIER_CNTL1__SRC_WIDTH__SHIFT 0x0
-#define UVD_JPEG_TIER_CNTL1__SRC_HEIGHT__SHIFT 0x10
-#define UVD_JPEG_TIER_CNTL1__SRC_WIDTH_MASK 0x0000FFFFL
-#define UVD_JPEG_TIER_CNTL1__SRC_HEIGHT_MASK 0xFFFF0000L
-//UVD_JPEG_TIER_CNTL2
-#define UVD_JPEG_TIER_CNTL2__TBL_ECS_SEL__SHIFT 0x0
-#define UVD_JPEG_TIER_CNTL2__TBL_TYPE__SHIFT 0x1
-#define UVD_JPEG_TIER_CNTL2__TQ__SHIFT 0x2
-#define UVD_JPEG_TIER_CNTL2__TH__SHIFT 0x4
-#define UVD_JPEG_TIER_CNTL2__TC__SHIFT 0x6
-#define UVD_JPEG_TIER_CNTL2__TD__SHIFT 0x7
-#define UVD_JPEG_TIER_CNTL2__TA__SHIFT 0xa
-#define UVD_JPEG_TIER_CNTL2__TIER2_HTBL_CNTLEN__SHIFT 0xe
-#define UVD_JPEG_TIER_CNTL2__DRI_VAL__SHIFT 0x10
-#define UVD_JPEG_TIER_CNTL2__TBL_ECS_SEL_MASK 0x00000001L
-#define UVD_JPEG_TIER_CNTL2__TBL_TYPE_MASK 0x00000002L
-#define UVD_JPEG_TIER_CNTL2__TQ_MASK 0x0000000CL
-#define UVD_JPEG_TIER_CNTL2__TH_MASK 0x00000030L
-#define UVD_JPEG_TIER_CNTL2__TC_MASK 0x00000040L
-#define UVD_JPEG_TIER_CNTL2__TD_MASK 0x00000380L
-#define UVD_JPEG_TIER_CNTL2__TA_MASK 0x00001C00L
-#define UVD_JPEG_TIER_CNTL2__TIER2_HTBL_CNTLEN_MASK 0x00004000L
-#define UVD_JPEG_TIER_CNTL2__DRI_VAL_MASK 0xFFFF0000L
-//UVD_JPEG_TIER_STATUS
-#define UVD_JPEG_TIER_STATUS__BSI_FETCH_DONE__SHIFT 0x0
-#define UVD_JPEG_TIER_STATUS__DECODE_DONE__SHIFT 0x1
-#define UVD_JPEG_TIER_STATUS__BSI_FETCH_DONE_MASK 0x00000001L
-#define UVD_JPEG_TIER_STATUS__DECODE_DONE_MASK 0x00000002L
-//UVD_JPEG_OUTBUF_CNTL
-#define UVD_JPEG_OUTBUF_CNTL__OUTBUF_CNT__SHIFT 0x0
-#define UVD_JPEG_OUTBUF_CNTL__HGT_ALIGN__SHIFT 0x2
-#define UVD_JPEG_OUTBUF_CNTL__JPEG0_DECODE_DONE_FIX__SHIFT 0x6
-#define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_MAX_CNT__SHIFT 0x7
-#define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_TIMER__SHIFT 0x9
-#define UVD_JPEG_OUTBUF_CNTL__OUTBUF_CNT_MASK 0x00000003L
-#define UVD_JPEG_OUTBUF_CNTL__HGT_ALIGN_MASK 0x00000004L
-#define UVD_JPEG_OUTBUF_CNTL__JPEG0_DECODE_DONE_FIX_MASK 0x00000040L
-#define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_MAX_CNT_MASK 0x00000180L
-#define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_TIMER_MASK 0x00001E00L
-//UVD_JPEG_OUTBUF_WPTR
-#define UVD_JPEG_OUTBUF_WPTR__OUTBUF_WPTR__SHIFT 0x0
-#define UVD_JPEG_OUTBUF_WPTR__OUTBUF_WPTR_MASK 0xFFFFFFFFL
-//UVD_JPEG_OUTBUF_RPTR
-#define UVD_JPEG_OUTBUF_RPTR__OUTBUF_RPTR__SHIFT 0x0
-#define UVD_JPEG_OUTBUF_RPTR__OUTBUF_RPTR_MASK 0xFFFFFFFFL
-//UVD_JPEG_PITCH
-#define UVD_JPEG_PITCH__PITCH__SHIFT 0x0
-#define UVD_JPEG_PITCH__PITCH_MASK 0xFFFFFFFFL
-//UVD_JPEG_UV_PITCH
-#define UVD_JPEG_UV_PITCH__UV_PITCH__SHIFT 0x0
-#define UVD_JPEG_UV_PITCH__UV_PITCH_MASK 0xFFFFFFFFL
-//JPEG_DEC_Y_GFX8_TILING_SURFACE
-#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_WIDTH__SHIFT 0x0
-#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_HEIGHT__SHIFT 0x2
-#define JPEG_DEC_Y_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT__SHIFT 0x4
-#define JPEG_DEC_Y_GFX8_TILING_SURFACE__NUM_BANKS__SHIFT 0x6
-#define JPEG_DEC_Y_GFX8_TILING_SURFACE__PIPE_CONFIG__SHIFT 0x8
-#define JPEG_DEC_Y_GFX8_TILING_SURFACE__TILE_SPLIT__SHIFT 0xd
-#define JPEG_DEC_Y_GFX8_TILING_SURFACE__ARRAY_MODE__SHIFT 0x10
-#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_WIDTH_MASK 0x00000003L
-#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_HEIGHT_MASK 0x0000000CL
-#define JPEG_DEC_Y_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT_MASK 0x00000030L
-#define JPEG_DEC_Y_GFX8_TILING_SURFACE__NUM_BANKS_MASK 0x000000C0L
-#define JPEG_DEC_Y_GFX8_TILING_SURFACE__PIPE_CONFIG_MASK 0x00001F00L
-#define JPEG_DEC_Y_GFX8_TILING_SURFACE__TILE_SPLIT_MASK 0x0000E000L
-#define JPEG_DEC_Y_GFX8_TILING_SURFACE__ARRAY_MODE_MASK 0x000F0000L
-//JPEG_DEC_UV_GFX8_TILING_SURFACE
-#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_WIDTH__SHIFT 0x0
-#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_HEIGHT__SHIFT 0x2
-#define JPEG_DEC_UV_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT__SHIFT 0x4
-#define JPEG_DEC_UV_GFX8_TILING_SURFACE__NUM_BANKS__SHIFT 0x6
-#define JPEG_DEC_UV_GFX8_TILING_SURFACE__PIPE_CONFIG__SHIFT 0x8
-#define JPEG_DEC_UV_GFX8_TILING_SURFACE__TILE_SPLIT__SHIFT 0xd
-#define JPEG_DEC_UV_GFX8_TILING_SURFACE__ARRAY_MODE__SHIFT 0x10
-#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_WIDTH_MASK 0x00000003L
-#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_HEIGHT_MASK 0x0000000CL
-#define JPEG_DEC_UV_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT_MASK 0x00000030L
-#define JPEG_DEC_UV_GFX8_TILING_SURFACE__NUM_BANKS_MASK 0x000000C0L
-#define JPEG_DEC_UV_GFX8_TILING_SURFACE__PIPE_CONFIG_MASK 0x00001F00L
-#define JPEG_DEC_UV_GFX8_TILING_SURFACE__TILE_SPLIT_MASK 0x0000E000L
-#define JPEG_DEC_UV_GFX8_TILING_SURFACE__ARRAY_MODE_MASK 0x000F0000L
-//JPEG_DEC_GFX8_ADDR_CONFIG
-#define JPEG_DEC_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
-#define JPEG_DEC_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L
-//JPEG_DEC_Y_GFX10_TILING_SURFACE
-#define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0
-#define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL
-//JPEG_DEC_UV_GFX10_TILING_SURFACE
-#define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0
-#define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL
-//JPEG_DEC_GFX10_ADDR_CONFIG
-#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
-#define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
-#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
-#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
-#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
-#define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
-#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
-#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
-//JPEG_DEC_ADDR_MODE
-#define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y__SHIFT 0x0
-#define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV__SHIFT 0x2
-#define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL__SHIFT 0xc
-#define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y_MASK 0x00000003L
-#define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV_MASK 0x0000000CL
-#define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL_MASK 0x00007000L
-//UVD_JPEG_OUTPUT_XY
-#define UVD_JPEG_OUTPUT_XY__OUTPUT_X__SHIFT 0x0
-#define UVD_JPEG_OUTPUT_XY__OUTPUT_Y__SHIFT 0x10
-#define UVD_JPEG_OUTPUT_XY__OUTPUT_X_MASK 0x00003FFFL
-#define UVD_JPEG_OUTPUT_XY__OUTPUT_Y_MASK 0x3FFF0000L
-//UVD_JPEG_GPCOM_CMD
-#define UVD_JPEG_GPCOM_CMD__CMD__SHIFT 0x1
-#define UVD_JPEG_GPCOM_CMD__CMD_MASK 0x0000000EL
-//UVD_JPEG_GPCOM_DATA0
-#define UVD_JPEG_GPCOM_DATA0__DATA0__SHIFT 0x0
-#define UVD_JPEG_GPCOM_DATA0__DATA0_MASK 0xFFFFFFFFL
-//UVD_JPEG_GPCOM_DATA1
-#define UVD_JPEG_GPCOM_DATA1__DATA1__SHIFT 0x0
-#define UVD_JPEG_GPCOM_DATA1__DATA1_MASK 0xFFFFFFFFL
-//UVD_JPEG_INDEX
-#define UVD_JPEG_INDEX__INDEX__SHIFT 0x0
-#define UVD_JPEG_INDEX__INDEX_MASK 0x000001FFL
-//UVD_JPEG_DATA
-#define UVD_JPEG_DATA__DATA__SHIFT 0x0
-#define UVD_JPEG_DATA__DATA_MASK 0xFFFFFFFFL
-//UVD_JPEG_SCRATCH1
-#define UVD_JPEG_SCRATCH1__SCRATCH1__SHIFT 0x0
-#define UVD_JPEG_SCRATCH1__SCRATCH1_MASK 0xFFFFFFFFL
-//UVD_JPEG_DEC_SOFT_RST
-#define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET__SHIFT 0x0
-#define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS__SHIFT 0x10
-#define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET_MASK 0x00000001L
-#define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS_MASK 0x00010000L
-
-
-// addressBlock: uvd0_lmi_adpdec
-//UVD_LMI_RE_64BIT_BAR_LOW
-#define UVD_LMI_RE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_RE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_RE_64BIT_BAR_HIGH
-#define UVD_LMI_RE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_RE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_IT_64BIT_BAR_LOW
-#define UVD_LMI_IT_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_IT_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_IT_64BIT_BAR_HIGH
-#define UVD_LMI_IT_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_IT_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_MP_64BIT_BAR_LOW
-#define UVD_LMI_MP_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_MP_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_MP_64BIT_BAR_HIGH
-#define UVD_LMI_MP_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_MP_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_CM_64BIT_BAR_LOW
-#define UVD_LMI_CM_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_CM_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_CM_64BIT_BAR_HIGH
-#define UVD_LMI_CM_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_CM_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_DB_64BIT_BAR_LOW
-#define UVD_LMI_DB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_DB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_DB_64BIT_BAR_HIGH
-#define UVD_LMI_DB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_DB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_DBW_64BIT_BAR_LOW
-#define UVD_LMI_DBW_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_DBW_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_DBW_64BIT_BAR_HIGH
-#define UVD_LMI_DBW_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_DBW_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_IDCT_64BIT_BAR_LOW
-#define UVD_LMI_IDCT_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_IDCT_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_IDCT_64BIT_BAR_HIGH
-#define UVD_LMI_IDCT_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_IDCT_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_MPRD_S0_64BIT_BAR_LOW
-#define UVD_LMI_MPRD_S0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_MPRD_S0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_MPRD_S0_64BIT_BAR_HIGH
-#define UVD_LMI_MPRD_S0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_MPRD_S0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_MPRD_S1_64BIT_BAR_LOW
-#define UVD_LMI_MPRD_S1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_MPRD_S1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_MPRD_S1_64BIT_BAR_HIGH
-#define UVD_LMI_MPRD_S1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_MPRD_S1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_MPRD_DBW_64BIT_BAR_LOW
-#define UVD_LMI_MPRD_DBW_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_MPRD_DBW_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_MPRD_DBW_64BIT_BAR_HIGH
-#define UVD_LMI_MPRD_DBW_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_MPRD_DBW_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_MPC_64BIT_BAR_LOW
-#define UVD_LMI_MPC_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_MPC_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_MPC_64BIT_BAR_HIGH
-#define UVD_LMI_MPC_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_MPC_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_RBC_RB_64BIT_BAR_LOW
-#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_RBC_RB_64BIT_BAR_HIGH
-#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_RBC_IB_64BIT_BAR_LOW
-#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_RBC_IB_64BIT_BAR_HIGH
-#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_LBSI_64BIT_BAR_LOW
-#define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_LBSI_64BIT_BAR_HIGH
-#define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_VCPU_NC0_64BIT_BAR_LOW
-#define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH
-#define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_VCPU_NC1_64BIT_BAR_LOW
-#define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH
-#define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW
-#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH
-#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_CENC_64BIT_BAR_LOW
-#define UVD_LMI_CENC_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_CENC_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_CENC_64BIT_BAR_HIGH
-#define UVD_LMI_CENC_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_CENC_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_SRE_64BIT_BAR_LOW
-#define UVD_LMI_SRE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_SRE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_SRE_64BIT_BAR_HIGH
-#define UVD_LMI_SRE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_SRE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_GPGPU_64BIT_BAR_LOW
-#define UVD_LMI_MIF_GPGPU_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_MIF_GPGPU_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH
-#define UVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW
-#define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH
-#define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW
-#define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH
-#define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_REF_64BIT_BAR_LOW
-#define UVD_LMI_MIF_REF_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_MIF_REF_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_REF_64BIT_BAR_HIGH
-#define UVD_LMI_MIF_REF_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_MIF_REF_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_DBW_64BIT_BAR_LOW
-#define UVD_LMI_MIF_DBW_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_MIF_DBW_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_DBW_64BIT_BAR_HIGH
-#define UVD_LMI_MIF_DBW_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_MIF_DBW_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW
-#define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH
-#define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_BSP0_64BIT_BAR_LOW
-#define UVD_LMI_MIF_BSP0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_MIF_BSP0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_BSP0_64BIT_BAR_HIGH
-#define UVD_LMI_MIF_BSP0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_MIF_BSP0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_BSP1_64BIT_BAR_LOW
-#define UVD_LMI_MIF_BSP1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_MIF_BSP1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_BSP1_64BIT_BAR_HIGH
-#define UVD_LMI_MIF_BSP1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_MIF_BSP1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_BSP2_64BIT_BAR_LOW
-#define UVD_LMI_MIF_BSP2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_MIF_BSP2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_BSP2_64BIT_BAR_HIGH
-#define UVD_LMI_MIF_BSP2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_MIF_BSP2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_BSP3_64BIT_BAR_LOW
-#define UVD_LMI_MIF_BSP3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_MIF_BSP3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_BSP3_64BIT_BAR_HIGH
-#define UVD_LMI_MIF_BSP3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_MIF_BSP3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_BSD0_64BIT_BAR_LOW
-#define UVD_LMI_MIF_BSD0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_MIF_BSD0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_BSD0_64BIT_BAR_HIGH
-#define UVD_LMI_MIF_BSD0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_MIF_BSD0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_BSD1_64BIT_BAR_LOW
-#define UVD_LMI_MIF_BSD1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_MIF_BSD1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_BSD1_64BIT_BAR_HIGH
-#define UVD_LMI_MIF_BSD1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_MIF_BSD1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_BSD2_64BIT_BAR_LOW
-#define UVD_LMI_MIF_BSD2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_MIF_BSD2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_BSD2_64BIT_BAR_HIGH
-#define UVD_LMI_MIF_BSD2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_MIF_BSD2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_BSD3_64BIT_BAR_LOW
-#define UVD_LMI_MIF_BSD3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_MIF_BSD3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_BSD3_64BIT_BAR_HIGH
-#define UVD_LMI_MIF_BSD3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_MIF_BSD3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_BSD4_64BIT_BAR_LOW
-#define UVD_LMI_MIF_BSD4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_MIF_BSD4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_BSD4_64BIT_BAR_HIGH
-#define UVD_LMI_MIF_BSD4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_MIF_BSD4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW
-#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH
-#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW
-#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH
-#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW
-#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH
-#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW
-#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH
-#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW
-#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH
-#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW
-#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH
-#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW
-#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH
-#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW
-#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH
-#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_SCLR_64BIT_BAR_LOW
-#define UVD_LMI_MIF_SCLR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_MIF_SCLR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_SCLR_64BIT_BAR_HIGH
-#define UVD_LMI_MIF_SCLR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_MIF_SCLR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_SCLR2_64BIT_BAR_LOW
-#define UVD_LMI_MIF_SCLR2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_MIF_SCLR2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH
-#define UVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_SPH_64BIT_BAR_HIGH
-#define UVD_LMI_SPH_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_SPH_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW
-#define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH
-#define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW
-#define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH
-#define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW
-#define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH
-#define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW
-#define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH
-#define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW
-#define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH
-#define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW
-#define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH
-#define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW
-#define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH
-#define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW
-#define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH
-#define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_MMSCH_NC_VMID
-#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID__SHIFT 0x0
-#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID__SHIFT 0x4
-#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID__SHIFT 0x8
-#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID__SHIFT 0xc
-#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID__SHIFT 0x10
-#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID__SHIFT 0x14
-#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID__SHIFT 0x18
-#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID__SHIFT 0x1c
-#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID_MASK 0x0000000FL
-#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID_MASK 0x000000F0L
-#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID_MASK 0x00000F00L
-#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID_MASK 0x0000F000L
-#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID_MASK 0x000F0000L
-#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID_MASK 0x00F00000L
-#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID_MASK 0x0F000000L
-#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID_MASK 0xF0000000L
-//UVD_LMI_MMSCH_CTRL
-#define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN__SHIFT 0x0
-#define UVD_LMI_MMSCH_CTRL__MMSCH_VM__SHIFT 0x1
-#define UVD_LMI_MMSCH_CTRL__PRIV_CLIENT_MMSCH__SHIFT 0x2
-#define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP__SHIFT 0x3
-#define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP__SHIFT 0x5
-#define UVD_LMI_MMSCH_CTRL__MMSCH_RD__SHIFT 0x7
-#define UVD_LMI_MMSCH_CTRL__MMSCH_WR__SHIFT 0x9
-#define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP__SHIFT 0xb
-#define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP__SHIFT 0xc
-#define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN_MASK 0x00000001L
-#define UVD_LMI_MMSCH_CTRL__MMSCH_VM_MASK 0x00000002L
-#define UVD_LMI_MMSCH_CTRL__PRIV_CLIENT_MMSCH_MASK 0x00000004L
-#define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP_MASK 0x00000018L
-#define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP_MASK 0x00000060L
-#define UVD_LMI_MMSCH_CTRL__MMSCH_RD_MASK 0x00000180L
-#define UVD_LMI_MMSCH_CTRL__MMSCH_WR_MASK 0x00000600L
-#define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP_MASK 0x00000800L
-#define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP_MASK 0x00001000L
-//UVD_MMSCH_LMI_STATUS
-#define UVD_MMSCH_LMI_STATUS__MMSCH_LMI_WRITE_CLEAN__SHIFT 0x2
-#define UVD_MMSCH_LMI_STATUS__MMSCH_RD_CLEAN__SHIFT 0xd
-#define UVD_MMSCH_LMI_STATUS__MMSCH_WR_CLEAN__SHIFT 0xe
-#define UVD_MMSCH_LMI_STATUS__MMSCH_LMI_WRITE_CLEAN_MASK 0x00000004L
-#define UVD_MMSCH_LMI_STATUS__MMSCH_RD_CLEAN_MASK 0x00002000L
-#define UVD_MMSCH_LMI_STATUS__MMSCH_WR_CLEAN_MASK 0x00004000L
-//UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW
-#define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH
-#define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW
-#define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH
-#define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW
-#define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH
-#define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW
-#define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH
-#define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_ADP_ATOMIC_CONFIG
-#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER0_WR_CACHE__SHIFT 0x0
-#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER1_WR_CACHE__SHIFT 0x4
-#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER2_WR_CACHE__SHIFT 0x8
-#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER3_WR_CACHE__SHIFT 0xc
-#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_RD_URG__SHIFT 0x10
-#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER0_WR_CACHE_MASK 0x0000000FL
-#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER1_WR_CACHE_MASK 0x000000F0L
-#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER2_WR_CACHE_MASK 0x00000F00L
-#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER3_WR_CACHE_MASK 0x0000F000L
-#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_RD_URG_MASK 0x000F0000L
-//UVD_LMI_ARB_CTRL2
-#define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN__SHIFT 0x0
-#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN__SHIFT 0x1
-#define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST__SHIFT 0x2
-#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST__SHIFT 0x6
-#define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX__SHIFT 0xa
-#define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX__SHIFT 0x14
-#define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN_MASK 0x00000001L
-#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN_MASK 0x00000002L
-#define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST_MASK 0x0000003CL
-#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST_MASK 0x000003C0L
-#define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX_MASK 0x000FFC00L
-#define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX_MASK 0xFFF00000L
-//UVD_LMI_VCPU_CACHE_VMIDS_MULTI
-#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID__SHIFT 0x0
-#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID__SHIFT 0x4
-#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID__SHIFT 0x8
-#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID__SHIFT 0xc
-#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID__SHIFT 0x10
-#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID__SHIFT 0x14
-#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID__SHIFT 0x18
-#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID__SHIFT 0x1c
-#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID_MASK 0x0000000FL
-#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID_MASK 0x000000F0L
-#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID_MASK 0x00000F00L
-#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID_MASK 0x0000F000L
-#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID_MASK 0x000F0000L
-#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID_MASK 0x00F00000L
-#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID_MASK 0x0F000000L
-#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID_MASK 0xF0000000L
-//UVD_LMI_VCPU_NC_VMIDS_MULTI
-#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID__SHIFT 0x4
-#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID__SHIFT 0x8
-#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID__SHIFT 0xc
-#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID__SHIFT 0x10
-#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID__SHIFT 0x14
-#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID__SHIFT 0x18
-#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID_MASK 0x000000F0L
-#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID_MASK 0x00000F00L
-#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID_MASK 0x0000F000L
-#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID_MASK 0x000F0000L
-#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID_MASK 0x00F00000L
-#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID_MASK 0x0F000000L
-//UVD_LMI_LAT_CTRL
-#define UVD_LMI_LAT_CTRL__SCALE__SHIFT 0x0
-#define UVD_LMI_LAT_CTRL__MAX_START__SHIFT 0x8
-#define UVD_LMI_LAT_CTRL__MIN_START__SHIFT 0x9
-#define UVD_LMI_LAT_CTRL__AVG_START__SHIFT 0xa
-#define UVD_LMI_LAT_CTRL__PERFMON_SYNC__SHIFT 0xb
-#define UVD_LMI_LAT_CTRL__SKIP__SHIFT 0x10
-#define UVD_LMI_LAT_CTRL__SCALE_MASK 0x000000FFL
-#define UVD_LMI_LAT_CTRL__MAX_START_MASK 0x00000100L
-#define UVD_LMI_LAT_CTRL__MIN_START_MASK 0x00000200L
-#define UVD_LMI_LAT_CTRL__AVG_START_MASK 0x00000400L
-#define UVD_LMI_LAT_CTRL__PERFMON_SYNC_MASK 0x00000800L
-#define UVD_LMI_LAT_CTRL__SKIP_MASK 0x000F0000L
-//UVD_LMI_LAT_CNTR
-#define UVD_LMI_LAT_CNTR__MAX_LAT__SHIFT 0x0
-#define UVD_LMI_LAT_CNTR__MIN_LAT__SHIFT 0x8
-#define UVD_LMI_LAT_CNTR__MAX_LAT_MASK 0x000000FFL
-#define UVD_LMI_LAT_CNTR__MIN_LAT_MASK 0x0000FF00L
-//UVD_LMI_AVG_LAT_CNTR
-#define UVD_LMI_AVG_LAT_CNTR__ENV_LOW__SHIFT 0x0
-#define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH__SHIFT 0x8
-#define UVD_LMI_AVG_LAT_CNTR__ENV_HIT__SHIFT 0x10
-#define UVD_LMI_AVG_LAT_CNTR__ENV_LOW_MASK 0x000000FFL
-#define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH_MASK 0x0000FF00L
-#define UVD_LMI_AVG_LAT_CNTR__ENV_HIT_MASK 0xFFFF0000L
-//UVD_LMI_SPH
-#define UVD_LMI_SPH__ADDR__SHIFT 0x0
-#define UVD_LMI_SPH__STS__SHIFT 0x1c
-#define UVD_LMI_SPH__STS_VALID__SHIFT 0x1e
-#define UVD_LMI_SPH__STS_OVERFLOW__SHIFT 0x1f
-#define UVD_LMI_SPH__ADDR_MASK 0x0FFFFFFFL
-#define UVD_LMI_SPH__STS_MASK 0x30000000L
-#define UVD_LMI_SPH__STS_VALID_MASK 0x40000000L
-#define UVD_LMI_SPH__STS_OVERFLOW_MASK 0x80000000L
-//UVD_LMI_VCPU_CACHE_VMID
-#define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0
-#define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL
-//UVD_LMI_CTRL2
-#define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0
-#define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1
-#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2
-#define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3
-#define UVD_LMI_CTRL2__CRC1_RESET__SHIFT 0x4
-#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7
-#define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8
-#define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9
-#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb
-#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd
-#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe
-#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf
-#define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10
-#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11
-#define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP__SHIFT 0x19
-#define UVD_LMI_CTRL2__NJ_MIF_GATING__SHIFT 0x1a
-#define UVD_LMI_CTRL2__CRC1_SEL__SHIFT 0x1b
-#define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L
-#define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L
-#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L
-#define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x00000008L
-#define UVD_LMI_CTRL2__CRC1_RESET_MASK 0x00000010L
-#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x00000080L
-#define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L
-#define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L
-#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L
-#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x00002000L
-#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x00004000L
-#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x00008000L
-#define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x00010000L
-#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x01FE0000L
-#define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP_MASK 0x02000000L
-#define UVD_LMI_CTRL2__NJ_MIF_GATING_MASK 0x04000000L
-#define UVD_LMI_CTRL2__CRC1_SEL_MASK 0xF8000000L
-//UVD_LMI_URGENT_CTRL
-#define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL__SHIFT 0x0
-#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL__SHIFT 0x1
-#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT__SHIFT 0x2
-#define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL__SHIFT 0x8
-#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL__SHIFT 0x9
-#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT 0xa
-#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL__SHIFT 0x10
-#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL__SHIFT 0x11
-#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT__SHIFT 0x12
-#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL__SHIFT 0x18
-#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL__SHIFT 0x19
-#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT__SHIFT 0x1a
-#define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL_MASK 0x00000001L
-#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL_MASK 0x00000002L
-#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT_MASK 0x0000003CL
-#define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL_MASK 0x00000100L
-#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL_MASK 0x00000200L
-#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT_MASK 0x00003C00L
-#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL_MASK 0x00010000L
-#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL_MASK 0x00020000L
-#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT_MASK 0x003C0000L
-#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL_MASK 0x01000000L
-#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL_MASK 0x02000000L
-#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT_MASK 0x3C000000L
-//UVD_LMI_CTRL
-#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0
-#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8
-#define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9
-#define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb
-#define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc
-#define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd
-#define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe
-#define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf
-#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14
-#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15
-#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16
-#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17
-#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18
-#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19
-#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a
-#define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ__SHIFT 0x1b
-#define UVD_LMI_CTRL__MC_BLK_RST__SHIFT 0x1c
-#define UVD_LMI_CTRL__UMC_BLK_RST__SHIFT 0x1d
-#define UVD_LMI_CTRL__RFU__SHIFT 0x1e
-#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0x000000FFL
-#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L
-#define UVD_LMI_CTRL__REQ_MODE_MASK 0x00000200L
-#define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000800L
-#define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x00001000L
-#define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x00002000L
-#define UVD_LMI_CTRL__CRC_RESET_MASK 0x00004000L
-#define UVD_LMI_CTRL__CRC_SEL_MASK 0x000F8000L
-#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x00100000L
-#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L
-#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x00400000L
-#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x00800000L
-#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L
-#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L
-#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x04000000L
-#define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ_MASK 0x08000000L
-#define UVD_LMI_CTRL__MC_BLK_RST_MASK 0x10000000L
-#define UVD_LMI_CTRL__UMC_BLK_RST_MASK 0x20000000L
-#define UVD_LMI_CTRL__RFU_MASK 0xC0000000L
-//UVD_LMI_STATUS
-#define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0
-#define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1
-#define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2
-#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3
-#define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4
-#define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5
-#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6
-#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7
-#define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8
-#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9
-#define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa
-#define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb
-#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc
-#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd
-#define UVD_LMI_STATUS__BSP0_WRITE_CLEAN__SHIFT 0x12
-#define UVD_LMI_STATUS__BSP1_WRITE_CLEAN__SHIFT 0x13
-#define UVD_LMI_STATUS__BSP2_WRITE_CLEAN__SHIFT 0x14
-#define UVD_LMI_STATUS__BSP3_WRITE_CLEAN__SHIFT 0x15
-#define UVD_LMI_STATUS__CENC_READ_CLEAN__SHIFT 0x16
-#define UVD_LMI_STATUS__READ_CLEAN_MASK 0x00000001L
-#define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x00000002L
-#define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x00000004L
-#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x00000008L
-#define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x00000010L
-#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x00000020L
-#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x00000040L
-#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x00000080L
-#define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x00000100L
-#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x00000200L
-#define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x00000400L
-#define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x00000800L
-#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x00001000L
-#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x00002000L
-#define UVD_LMI_STATUS__BSP0_WRITE_CLEAN_MASK 0x00040000L
-#define UVD_LMI_STATUS__BSP1_WRITE_CLEAN_MASK 0x00080000L
-#define UVD_LMI_STATUS__BSP2_WRITE_CLEAN_MASK 0x00100000L
-#define UVD_LMI_STATUS__BSP3_WRITE_CLEAN_MASK 0x00200000L
-#define UVD_LMI_STATUS__CENC_READ_CLEAN_MASK 0x00400000L
-//UVD_LMI_PERFMON_CTRL
-#define UVD_LMI_PERFMON_CTRL__PERFMON_STATE__SHIFT 0x0
-#define UVD_LMI_PERFMON_CTRL__PERFMON_SEL__SHIFT 0x8
-#define UVD_LMI_PERFMON_CTRL__PERFMON_STATE_MASK 0x00000003L
-#define UVD_LMI_PERFMON_CTRL__PERFMON_SEL_MASK 0x00001F00L
-//UVD_LMI_PERFMON_COUNT_LO
-#define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT 0x0
-#define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK 0xFFFFFFFFL
-//UVD_LMI_PERFMON_COUNT_HI
-#define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT 0x0
-#define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK 0x0000FFFFL
-//UVD_LMI_ADP_SWAP_CNTL
-#define UVD_LMI_ADP_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6
-#define UVD_LMI_ADP_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8
-#define UVD_LMI_ADP_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa
-#define UVD_LMI_ADP_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc
-#define UVD_LMI_ADP_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe
-#define UVD_LMI_ADP_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10
-#define UVD_LMI_ADP_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12
-#define UVD_LMI_ADP_SWAP_CNTL__ACAP_MC_SWAP__SHIFT 0x14
-#define UVD_LMI_ADP_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18
-#define UVD_LMI_ADP_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c
-#define UVD_LMI_ADP_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e
-#define UVD_LMI_ADP_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0x000000C0L
-#define UVD_LMI_ADP_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x00000300L
-#define UVD_LMI_ADP_SWAP_CNTL__CM_MC_SWAP_MASK 0x00000C00L
-#define UVD_LMI_ADP_SWAP_CNTL__IT_MC_SWAP_MASK 0x00003000L
-#define UVD_LMI_ADP_SWAP_CNTL__DB_R_MC_SWAP_MASK 0x0000C000L
-#define UVD_LMI_ADP_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x00030000L
-#define UVD_LMI_ADP_SWAP_CNTL__CSM_MC_SWAP_MASK 0x000C0000L
-#define UVD_LMI_ADP_SWAP_CNTL__ACAP_MC_SWAP_MASK 0x00300000L
-#define UVD_LMI_ADP_SWAP_CNTL__DBW_MC_SWAP_MASK 0x03000000L
-#define UVD_LMI_ADP_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000L
-#define UVD_LMI_ADP_SWAP_CNTL__MP_MC_SWAP_MASK 0xC0000000L
-//UVD_LMI_RBC_RB_VMID
-#define UVD_LMI_RBC_RB_VMID__RB_VMID__SHIFT 0x0
-#define UVD_LMI_RBC_RB_VMID__RB_VMID_MASK 0x0000000FL
-//UVD_LMI_RBC_IB_VMID
-#define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0
-#define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0x0000000FL
-//UVD_LMI_MC_CREDITS
-#define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS__SHIFT 0x0
-#define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS__SHIFT 0x8
-#define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS__SHIFT 0x10
-#define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS__SHIFT 0x18
-#define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS_MASK 0x0000003FL
-#define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS_MASK 0x00003F00L
-#define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS_MASK 0x003F0000L
-#define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS_MASK 0x3F000000L
-//UVD_LMI_ADP_IND_INDEX
-#define UVD_LMI_ADP_IND_INDEX__INDEX__SHIFT 0x0
-#define UVD_LMI_ADP_IND_INDEX__INDEX_MASK 0x00001FFFL
-//UVD_LMI_ADP_IND_DATA
-#define UVD_LMI_ADP_IND_DATA__DATA__SHIFT 0x0
-#define UVD_LMI_ADP_IND_DATA__DATA_MASK 0xFFFFFFFFL
-//VCN_RAS_CNTL
-#define VCN_RAS_CNTL__VCPU_VCODEC_IH_EN__SHIFT 0x0
-#define VCN_RAS_CNTL__MMSCH_FATAL_ERROR_EN__SHIFT 0x1
-#define VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN__SHIFT 0x4
-#define VCN_RAS_CNTL__MMSCH_PMI_EN__SHIFT 0x5
-#define VCN_RAS_CNTL__VCPU_VCODEC_REARM__SHIFT 0x8
-#define VCN_RAS_CNTL__MMSCH_REARM__SHIFT 0x9
-#define VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN__SHIFT 0xc
-#define VCN_RAS_CNTL__VCPU_VCODEC_READY__SHIFT 0x10
-#define VCN_RAS_CNTL__MMSCH_READY__SHIFT 0x11
-#define VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK 0x00000001L
-#define VCN_RAS_CNTL__MMSCH_FATAL_ERROR_EN_MASK 0x00000002L
-#define VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK 0x00000010L
-#define VCN_RAS_CNTL__MMSCH_PMI_EN_MASK 0x00000020L
-#define VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK 0x00000100L
-#define VCN_RAS_CNTL__MMSCH_REARM_MASK 0x00000200L
-#define VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK 0x00001000L
-#define VCN_RAS_CNTL__VCPU_VCODEC_READY_MASK 0x00010000L
-#define VCN_RAS_CNTL__MMSCH_READY_MASK 0x00020000L
-
-
-// addressBlock: uvd0_mmsch_dec
-//MMSCH_UCODE_ADDR
-#define MMSCH_UCODE_ADDR__UCODE_ADDR__SHIFT 0x2
-#define MMSCH_UCODE_ADDR__UCODE_LOCK__SHIFT 0x1f
-#define MMSCH_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFCL
-#define MMSCH_UCODE_ADDR__UCODE_LOCK_MASK 0x80000000L
-//MMSCH_UCODE_DATA
-#define MMSCH_UCODE_DATA__UCODE_DATA__SHIFT 0x0
-#define MMSCH_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
-//MMSCH_SRAM_ADDR
-#define MMSCH_SRAM_ADDR__SRAM_ADDR__SHIFT 0x2
-#define MMSCH_SRAM_ADDR__SRAM_LOCK__SHIFT 0x1f
-#define MMSCH_SRAM_ADDR__SRAM_ADDR_MASK 0x00001FFCL
-#define MMSCH_SRAM_ADDR__SRAM_LOCK_MASK 0x80000000L
-//MMSCH_SRAM_DATA
-#define MMSCH_SRAM_DATA__SRAM_DATA__SHIFT 0x0
-#define MMSCH_SRAM_DATA__SRAM_DATA_MASK 0xFFFFFFFFL
-//MMSCH_VF_SRAM_OFFSET
-#define MMSCH_VF_SRAM_OFFSET__VF_SRAM_OFFSET__SHIFT 0x2
-#define MMSCH_VF_SRAM_OFFSET__VF_SRAM_NUM_DW_PER_VF__SHIFT 0x10
-#define MMSCH_VF_SRAM_OFFSET__VF_SRAM_OFFSET_MASK 0x00001FFCL
-#define MMSCH_VF_SRAM_OFFSET__VF_SRAM_NUM_DW_PER_VF_MASK 0x00FF0000L
-//MMSCH_DB_SRAM_OFFSET
-#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_OFFSET__SHIFT 0x2
-#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_ENG__SHIFT 0x10
-#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_RING_PER_ENG__SHIFT 0x18
-#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_OFFSET_MASK 0x00001FFCL
-#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_ENG_MASK 0x00FF0000L
-#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_RING_PER_ENG_MASK 0xFF000000L
-//MMSCH_CTX_SRAM_OFFSET
-#define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_OFFSET__SHIFT 0x2
-#define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_SIZE__SHIFT 0x10
-#define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_OFFSET_MASK 0x00001FFCL
-#define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_SIZE_MASK 0xFFFF0000L
-//MMSCH_INTR
-#define MMSCH_INTR__INTR__SHIFT 0x0
-#define MMSCH_INTR__INTR_MASK 0x00001FFFL
-//MMSCH_INTR_ACK
-#define MMSCH_INTR_ACK__INTR__SHIFT 0x0
-#define MMSCH_INTR_ACK__INTR_MASK 0x00001FFFL
-//MMSCH_INTR_STATUS
-#define MMSCH_INTR_STATUS__INTR__SHIFT 0x0
-#define MMSCH_INTR_STATUS__INTR_MASK 0x00001FFFL
-//MMSCH_VF_VMID
-#define MMSCH_VF_VMID__VF_CTX_VMID__SHIFT 0x0
-#define MMSCH_VF_VMID__VF_GPCOM_VMID__SHIFT 0x5
-#define MMSCH_VF_VMID__VF_CTX_VMID_MASK 0x0000001FL
-#define MMSCH_VF_VMID__VF_GPCOM_VMID_MASK 0x000003E0L
-//MMSCH_VF_CTX_ADDR_LO
-#define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO__SHIFT 0x6
-#define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO_MASK 0xFFFFFFC0L
-//MMSCH_VF_CTX_ADDR_HI
-#define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI__SHIFT 0x0
-#define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI_MASK 0xFFFFFFFFL
-//MMSCH_VF_CTX_SIZE
-#define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE__SHIFT 0x0
-#define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE_MASK 0xFFFFFFFFL
-//MMSCH_VF_GPCOM_ADDR_LO
-#define MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO__SHIFT 0x6
-#define MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO_MASK 0xFFFFFFC0L
-//MMSCH_VF_GPCOM_ADDR_HI
-#define MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI__SHIFT 0x0
-#define MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI_MASK 0xFFFFFFFFL
-//MMSCH_VF_GPCOM_SIZE
-#define MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE__SHIFT 0x0
-#define MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE_MASK 0xFFFFFFFFL
-//MMSCH_VF_MAILBOX_HOST
-#define MMSCH_VF_MAILBOX_HOST__DATA__SHIFT 0x0
-#define MMSCH_VF_MAILBOX_HOST__DATA_MASK 0xFFFFFFFFL
-//MMSCH_VF_MAILBOX_RESP
-#define MMSCH_VF_MAILBOX_RESP__RESP__SHIFT 0x0
-#define MMSCH_VF_MAILBOX_RESP__RESP_MASK 0xFFFFFFFFL
-//MMSCH_VF_MAILBOX_0
-#define MMSCH_VF_MAILBOX_0__DATA__SHIFT 0x0
-#define MMSCH_VF_MAILBOX_0__DATA_MASK 0xFFFFFFFFL
-//MMSCH_VF_MAILBOX_0_RESP
-#define MMSCH_VF_MAILBOX_0_RESP__RESP__SHIFT 0x0
-#define MMSCH_VF_MAILBOX_0_RESP__RESP_MASK 0xFFFFFFFFL
-//MMSCH_VF_MAILBOX_1
-#define MMSCH_VF_MAILBOX_1__DATA__SHIFT 0x0
-#define MMSCH_VF_MAILBOX_1__DATA_MASK 0xFFFFFFFFL
-//MMSCH_VF_MAILBOX_1_RESP
-#define MMSCH_VF_MAILBOX_1_RESP__RESP__SHIFT 0x0
-#define MMSCH_VF_MAILBOX_1_RESP__RESP_MASK 0xFFFFFFFFL
-//MMSCH_CNTL
-#define MMSCH_CNTL__CLK_EN__SHIFT 0x0
-#define MMSCH_CNTL__ED_ENABLE__SHIFT 0x1
-#define MMSCH_CNTL__MMSCH_IRQ_ERR__SHIFT 0x5
-#define MMSCH_CNTL__MMSCH_NACK_INTR_EN__SHIFT 0x9
-#define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN__SHIFT 0xa
-#define MMSCH_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14
-#define MMSCH_CNTL__TIMEOUT_DIS__SHIFT 0x1c
-#define MMSCH_CNTL__CLK_EN_MASK 0x00000001L
-#define MMSCH_CNTL__ED_ENABLE_MASK 0x00000002L
-#define MMSCH_CNTL__MMSCH_IRQ_ERR_MASK 0x000001E0L
-#define MMSCH_CNTL__MMSCH_NACK_INTR_EN_MASK 0x00000200L
-#define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN_MASK 0x00000400L
-#define MMSCH_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L
-#define MMSCH_CNTL__TIMEOUT_DIS_MASK 0x10000000L
-//MMSCH_NONCACHE_OFFSET0
-#define MMSCH_NONCACHE_OFFSET0__OFFSET__SHIFT 0x0
-#define MMSCH_NONCACHE_OFFSET0__OFFSET_MASK 0x0FFFFFFFL
-//MMSCH_NONCACHE_SIZE0
-#define MMSCH_NONCACHE_SIZE0__SIZE__SHIFT 0x0
-#define MMSCH_NONCACHE_SIZE0__SIZE_MASK 0x00FFFFFFL
-//MMSCH_NONCACHE_OFFSET1
-#define MMSCH_NONCACHE_OFFSET1__OFFSET__SHIFT 0x0
-#define MMSCH_NONCACHE_OFFSET1__OFFSET_MASK 0x0FFFFFFFL
-//MMSCH_NONCACHE_SIZE1
-#define MMSCH_NONCACHE_SIZE1__SIZE__SHIFT 0x0
-#define MMSCH_NONCACHE_SIZE1__SIZE_MASK 0x00FFFFFFL
-//MMSCH_PROC_STATE1
-#define MMSCH_PROC_STATE1__PC__SHIFT 0x0
-#define MMSCH_PROC_STATE1__PC_MASK 0xFFFFFFFFL
-//MMSCH_LAST_MC_ADDR
-#define MMSCH_LAST_MC_ADDR__MC_ADDR__SHIFT 0x0
-#define MMSCH_LAST_MC_ADDR__RW__SHIFT 0x1f
-#define MMSCH_LAST_MC_ADDR__MC_ADDR_MASK 0x0FFFFFFFL
-#define MMSCH_LAST_MC_ADDR__RW_MASK 0x80000000L
-//MMSCH_LAST_MEM_ACCESS_HI
-#define MMSCH_LAST_MEM_ACCESS_HI__PROC_CMD__SHIFT 0x0
-#define MMSCH_LAST_MEM_ACCESS_HI__FIFO_RPTR__SHIFT 0x8
-#define MMSCH_LAST_MEM_ACCESS_HI__FIFO_WPTR__SHIFT 0xc
-#define MMSCH_LAST_MEM_ACCESS_HI__PROC_CMD_MASK 0x00000007L
-#define MMSCH_LAST_MEM_ACCESS_HI__FIFO_RPTR_MASK 0x00000700L
-#define MMSCH_LAST_MEM_ACCESS_HI__FIFO_WPTR_MASK 0x00007000L
-//MMSCH_LAST_MEM_ACCESS_LO
-#define MMSCH_LAST_MEM_ACCESS_LO__PROC_ADDR__SHIFT 0x0
-#define MMSCH_LAST_MEM_ACCESS_LO__PROC_ADDR_MASK 0xFFFFFFFFL
-//MMSCH_SCRATCH_0
-#define MMSCH_SCRATCH_0__SCRATCH_0__SHIFT 0x0
-#define MMSCH_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL
-//MMSCH_SCRATCH_1
-#define MMSCH_SCRATCH_1__SCRATCH_1__SHIFT 0x0
-#define MMSCH_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL
-//MMSCH_GPUIOV_SCH_BLOCK_0
-#define MMSCH_GPUIOV_SCH_BLOCK_0__ID__SHIFT 0x0
-#define MMSCH_GPUIOV_SCH_BLOCK_0__VERSION__SHIFT 0x4
-#define MMSCH_GPUIOV_SCH_BLOCK_0__SIZE__SHIFT 0x8
-#define MMSCH_GPUIOV_SCH_BLOCK_0__ID_MASK 0x0000000FL
-#define MMSCH_GPUIOV_SCH_BLOCK_0__VERSION_MASK 0x000000F0L
-#define MMSCH_GPUIOV_SCH_BLOCK_0__SIZE_MASK 0x0000FF00L
-//MMSCH_GPUIOV_CMD_CONTROL_0
-#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_TYPE__SHIFT 0x0
-#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE__SHIFT 0x4
-#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_INTR_EN__SHIFT 0x5
-#define MMSCH_GPUIOV_CMD_CONTROL_0__VM_BUSY_INTR_EN__SHIFT 0x6
-#define MMSCH_GPUIOV_CMD_CONTROL_0__FUNCTINO_ID__SHIFT 0x8
-#define MMSCH_GPUIOV_CMD_CONTROL_0__NEXT_FUNCTINO_ID__SHIFT 0x10
-#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_TYPE_MASK 0x0000000FL
-#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_MASK 0x00000010L
-#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_INTR_EN_MASK 0x00000020L
-#define MMSCH_GPUIOV_CMD_CONTROL_0__VM_BUSY_INTR_EN_MASK 0x00000040L
-#define MMSCH_GPUIOV_CMD_CONTROL_0__FUNCTINO_ID_MASK 0x0000FF00L
-#define MMSCH_GPUIOV_CMD_CONTROL_0__NEXT_FUNCTINO_ID_MASK 0x00FF0000L
-//MMSCH_GPUIOV_CMD_STATUS_0
-#define MMSCH_GPUIOV_CMD_STATUS_0__CMD_STATUS__SHIFT 0x0
-#define MMSCH_GPUIOV_CMD_STATUS_0__CMD_STATUS_MASK 0x0000000FL
-//MMSCH_GPUIOV_VM_BUSY_STATUS_0
-#define MMSCH_GPUIOV_VM_BUSY_STATUS_0__BUSY__SHIFT 0x0
-#define MMSCH_GPUIOV_VM_BUSY_STATUS_0__BUSY_MASK 0xFFFFFFFFL
-//MMSCH_GPUIOV_ACTIVE_FCNS_0
-#define MMSCH_GPUIOV_ACTIVE_FCNS_0__ACTIVE_FCNS__SHIFT 0x0
-#define MMSCH_GPUIOV_ACTIVE_FCNS_0__ACTIVE_FCNS_MASK 0xFFFFFFFFL
-//MMSCH_GPUIOV_ACTIVE_FCN_ID_0
-#define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID__SHIFT 0x0
-#define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_STATUS__SHIFT 0x8
-#define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_MASK 0x000000FFL
-#define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_STATUS_MASK 0x00000F00L
-//MMSCH_GPUIOV_DW6_0
-#define MMSCH_GPUIOV_DW6_0__DATA__SHIFT 0x0
-#define MMSCH_GPUIOV_DW6_0__DATA_MASK 0xFFFFFFFFL
-//MMSCH_GPUIOV_DW7_0
-#define MMSCH_GPUIOV_DW7_0__DATA__SHIFT 0x0
-#define MMSCH_GPUIOV_DW7_0__DATA_MASK 0xFFFFFFFFL
-//MMSCH_GPUIOV_DW8_0
-#define MMSCH_GPUIOV_DW8_0__DATA__SHIFT 0x0
-#define MMSCH_GPUIOV_DW8_0__DATA_MASK 0xFFFFFFFFL
-//MMSCH_GPUIOV_SCH_BLOCK_1
-#define MMSCH_GPUIOV_SCH_BLOCK_1__ID__SHIFT 0x0
-#define MMSCH_GPUIOV_SCH_BLOCK_1__VERSION__SHIFT 0x4
-#define MMSCH_GPUIOV_SCH_BLOCK_1__SIZE__SHIFT 0x8
-#define MMSCH_GPUIOV_SCH_BLOCK_1__ID_MASK 0x0000000FL
-#define MMSCH_GPUIOV_SCH_BLOCK_1__VERSION_MASK 0x000000F0L
-#define MMSCH_GPUIOV_SCH_BLOCK_1__SIZE_MASK 0x0000FF00L
-//MMSCH_GPUIOV_CMD_CONTROL_1
-#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_TYPE__SHIFT 0x0
-#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE__SHIFT 0x4
-#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_INTR_EN__SHIFT 0x5
-#define MMSCH_GPUIOV_CMD_CONTROL_1__VM_BUSY_INTR_EN__SHIFT 0x6
-#define MMSCH_GPUIOV_CMD_CONTROL_1__FUNCTINO_ID__SHIFT 0x8
-#define MMSCH_GPUIOV_CMD_CONTROL_1__NEXT_FUNCTINO_ID__SHIFT 0x10
-#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_TYPE_MASK 0x0000000FL
-#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_MASK 0x00000010L
-#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L
-#define MMSCH_GPUIOV_CMD_CONTROL_1__VM_BUSY_INTR_EN_MASK 0x00000040L
-#define MMSCH_GPUIOV_CMD_CONTROL_1__FUNCTINO_ID_MASK 0x0000FF00L
-#define MMSCH_GPUIOV_CMD_CONTROL_1__NEXT_FUNCTINO_ID_MASK 0x00FF0000L
-//MMSCH_GPUIOV_CMD_STATUS_1
-#define MMSCH_GPUIOV_CMD_STATUS_1__CMD_STATUS__SHIFT 0x0
-#define MMSCH_GPUIOV_CMD_STATUS_1__CMD_STATUS_MASK 0x0000000FL
-//MMSCH_GPUIOV_VM_BUSY_STATUS_1
-#define MMSCH_GPUIOV_VM_BUSY_STATUS_1__BUSY__SHIFT 0x0
-#define MMSCH_GPUIOV_VM_BUSY_STATUS_1__BUSY_MASK 0xFFFFFFFFL
-//MMSCH_GPUIOV_ACTIVE_FCNS_1
-#define MMSCH_GPUIOV_ACTIVE_FCNS_1__ACTIVE_FCNS__SHIFT 0x0
-#define MMSCH_GPUIOV_ACTIVE_FCNS_1__ACTIVE_FCNS_MASK 0xFFFFFFFFL
-//MMSCH_GPUIOV_ACTIVE_FCN_ID_1
-#define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID__SHIFT 0x0
-#define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_STATUS__SHIFT 0x8
-#define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_MASK 0x000000FFL
-#define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_STATUS_MASK 0x00000F00L
-//MMSCH_GPUIOV_DW6_1
-#define MMSCH_GPUIOV_DW6_1__DATA__SHIFT 0x0
-#define MMSCH_GPUIOV_DW6_1__DATA_MASK 0xFFFFFFFFL
-//MMSCH_GPUIOV_DW7_1
-#define MMSCH_GPUIOV_DW7_1__DATA__SHIFT 0x0
-#define MMSCH_GPUIOV_DW7_1__DATA_MASK 0xFFFFFFFFL
-//MMSCH_GPUIOV_DW8_1
-#define MMSCH_GPUIOV_DW8_1__DATA__SHIFT 0x0
-#define MMSCH_GPUIOV_DW8_1__DATA_MASK 0xFFFFFFFFL
-//MMSCH_GPUIOV_CNTXT
-#define MMSCH_GPUIOV_CNTXT__CNTXT_SIZE__SHIFT 0x0
-#define MMSCH_GPUIOV_CNTXT__CNTXT_LOCATION__SHIFT 0x7
-#define MMSCH_GPUIOV_CNTXT__CNTXT_OFFSET__SHIFT 0xa
-#define MMSCH_GPUIOV_CNTXT__CNTXT_SIZE_MASK 0x0000007FL
-#define MMSCH_GPUIOV_CNTXT__CNTXT_LOCATION_MASK 0x00000080L
-#define MMSCH_GPUIOV_CNTXT__CNTXT_OFFSET_MASK 0xFFFFFC00L
-//MMSCH_SCRATCH_2
-#define MMSCH_SCRATCH_2__SCRATCH_2__SHIFT 0x0
-#define MMSCH_SCRATCH_2__SCRATCH_2_MASK 0xFFFFFFFFL
-//MMSCH_SCRATCH_3
-#define MMSCH_SCRATCH_3__SCRATCH_3__SHIFT 0x0
-#define MMSCH_SCRATCH_3__SCRATCH_3_MASK 0xFFFFFFFFL
-//MMSCH_SCRATCH_4
-#define MMSCH_SCRATCH_4__SCRATCH_4__SHIFT 0x0
-#define MMSCH_SCRATCH_4__SCRATCH_4_MASK 0xFFFFFFFFL
-//MMSCH_SCRATCH_5
-#define MMSCH_SCRATCH_5__SCRATCH_5__SHIFT 0x0
-#define MMSCH_SCRATCH_5__SCRATCH_5_MASK 0xFFFFFFFFL
-//MMSCH_SCRATCH_6
-#define MMSCH_SCRATCH_6__SCRATCH_6__SHIFT 0x0
-#define MMSCH_SCRATCH_6__SCRATCH_6_MASK 0xFFFFFFFFL
-//MMSCH_SCRATCH_7
-#define MMSCH_SCRATCH_7__SCRATCH_7__SHIFT 0x0
-#define MMSCH_SCRATCH_7__SCRATCH_7_MASK 0xFFFFFFFFL
-//MMSCH_VFID_FIFO_HEAD_0
-#define MMSCH_VFID_FIFO_HEAD_0__HEAD__SHIFT 0x0
-#define MMSCH_VFID_FIFO_HEAD_0__HEAD_MASK 0x0000003FL
-//MMSCH_VFID_FIFO_TAIL_0
-#define MMSCH_VFID_FIFO_TAIL_0__TAIL__SHIFT 0x0
-#define MMSCH_VFID_FIFO_TAIL_0__TAIL_MASK 0x0000003FL
-//MMSCH_VFID_FIFO_HEAD_1
-#define MMSCH_VFID_FIFO_HEAD_1__HEAD__SHIFT 0x0
-#define MMSCH_VFID_FIFO_HEAD_1__HEAD_MASK 0x0000003FL
-//MMSCH_VFID_FIFO_TAIL_1
-#define MMSCH_VFID_FIFO_TAIL_1__TAIL__SHIFT 0x0
-#define MMSCH_VFID_FIFO_TAIL_1__TAIL_MASK 0x0000003FL
-//MMSCH_NACK_STATUS
-#define MMSCH_NACK_STATUS__WR_NACK_STATUS__SHIFT 0x0
-#define MMSCH_NACK_STATUS__RD_NACK_STATUS__SHIFT 0x2
-#define MMSCH_NACK_STATUS__WR_NACK_STATUS_MASK 0x00000003L
-#define MMSCH_NACK_STATUS__RD_NACK_STATUS_MASK 0x0000000CL
-//MMSCH_VF_MAILBOX0_DATA
-#define MMSCH_VF_MAILBOX0_DATA__DATA__SHIFT 0x0
-#define MMSCH_VF_MAILBOX0_DATA__DATA_MASK 0xFFFFFFFFL
-//MMSCH_VF_MAILBOX1_DATA
-#define MMSCH_VF_MAILBOX1_DATA__DATA__SHIFT 0x0
-#define MMSCH_VF_MAILBOX1_DATA__DATA_MASK 0xFFFFFFFFL
-//MMSCH_GPUIOV_SCH_BLOCK_IP_0
-#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__ID__SHIFT 0x0
-#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__VERSION__SHIFT 0x4
-#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__SIZE__SHIFT 0x8
-#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__ID_MASK 0x0000000FL
-#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__VERSION_MASK 0x000000F0L
-#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__SIZE_MASK 0x0000FF00L
-//MMSCH_GPUIOV_CMD_STATUS_IP_0
-#define MMSCH_GPUIOV_CMD_STATUS_IP_0__CMD_STATUS__SHIFT 0x0
-#define MMSCH_GPUIOV_CMD_STATUS_IP_0__CMD_STATUS_MASK 0x0000000FL
-//MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0
-#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID__SHIFT 0x0
-#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_STATUS__SHIFT 0x8
-#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_MASK 0x000000FFL
-#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_STATUS_MASK 0x00000F00L
-//MMSCH_GPUIOV_SCH_BLOCK_IP_1
-#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__ID__SHIFT 0x0
-#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__VERSION__SHIFT 0x4
-#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__SIZE__SHIFT 0x8
-#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__ID_MASK 0x0000000FL
-#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__VERSION_MASK 0x000000F0L
-#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__SIZE_MASK 0x0000FF00L
-//MMSCH_GPUIOV_CMD_STATUS_IP_1
-#define MMSCH_GPUIOV_CMD_STATUS_IP_1__CMD_STATUS__SHIFT 0x0
-#define MMSCH_GPUIOV_CMD_STATUS_IP_1__CMD_STATUS_MASK 0x0000000FL
-//MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1
-#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID__SHIFT 0x0
-#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_STATUS__SHIFT 0x8
-#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_MASK 0x000000FFL
-#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_STATUS_MASK 0x00000F00L
-//MMSCH_GPUIOV_CNTXT_IP
-#define MMSCH_GPUIOV_CNTXT_IP__CNTXT_SIZE__SHIFT 0x0
-#define MMSCH_GPUIOV_CNTXT_IP__CNTXT_LOCATION__SHIFT 0x7
-#define MMSCH_GPUIOV_CNTXT_IP__CNTXT_SIZE_MASK 0x0000007FL
-#define MMSCH_GPUIOV_CNTXT_IP__CNTXT_LOCATION_MASK 0x00000080L
-//MMSCH_GPUIOV_SCH_BLOCK_2
-#define MMSCH_GPUIOV_SCH_BLOCK_2__ID__SHIFT 0x0
-#define MMSCH_GPUIOV_SCH_BLOCK_2__VERSION__SHIFT 0x4
-#define MMSCH_GPUIOV_SCH_BLOCK_2__SIZE__SHIFT 0x8
-#define MMSCH_GPUIOV_SCH_BLOCK_2__ID_MASK 0x0000000FL
-#define MMSCH_GPUIOV_SCH_BLOCK_2__VERSION_MASK 0x000000F0L
-#define MMSCH_GPUIOV_SCH_BLOCK_2__SIZE_MASK 0x0000FF00L
-//MMSCH_GPUIOV_CMD_CONTROL_2
-#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_TYPE__SHIFT 0x0
-#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE__SHIFT 0x4
-#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_INTR_EN__SHIFT 0x5
-#define MMSCH_GPUIOV_CMD_CONTROL_2__VM_BUSY_INTR_EN__SHIFT 0x6
-#define MMSCH_GPUIOV_CMD_CONTROL_2__FUNCTINO_ID__SHIFT 0x8
-#define MMSCH_GPUIOV_CMD_CONTROL_2__NEXT_FUNCTINO_ID__SHIFT 0x10
-#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_TYPE_MASK 0x0000000FL
-#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_MASK 0x00000010L
-#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_INTR_EN_MASK 0x00000020L
-#define MMSCH_GPUIOV_CMD_CONTROL_2__VM_BUSY_INTR_EN_MASK 0x00000040L
-#define MMSCH_GPUIOV_CMD_CONTROL_2__FUNCTINO_ID_MASK 0x0000FF00L
-#define MMSCH_GPUIOV_CMD_CONTROL_2__NEXT_FUNCTINO_ID_MASK 0x00FF0000L
-//MMSCH_GPUIOV_CMD_STATUS_2
-#define MMSCH_GPUIOV_CMD_STATUS_2__CMD_STATUS__SHIFT 0x0
-#define MMSCH_GPUIOV_CMD_STATUS_2__CMD_STATUS_MASK 0x0000000FL
-//MMSCH_GPUIOV_VM_BUSY_STATUS_2
-#define MMSCH_GPUIOV_VM_BUSY_STATUS_2__BUSY__SHIFT 0x0
-#define MMSCH_GPUIOV_VM_BUSY_STATUS_2__BUSY_MASK 0xFFFFFFFFL
-//MMSCH_GPUIOV_ACTIVE_FCNS_2
-#define MMSCH_GPUIOV_ACTIVE_FCNS_2__ACTIVE_FCNS__SHIFT 0x0
-#define MMSCH_GPUIOV_ACTIVE_FCNS_2__ACTIVE_FCNS_MASK 0xFFFFFFFFL
-//MMSCH_GPUIOV_ACTIVE_FCN_ID_2
-#define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID__SHIFT 0x0
-#define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_STATUS__SHIFT 0x8
-#define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_MASK 0x000000FFL
-#define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_STATUS_MASK 0x00000F00L
-//MMSCH_GPUIOV_DW6_2
-#define MMSCH_GPUIOV_DW6_2__DATA__SHIFT 0x0
-#define MMSCH_GPUIOV_DW6_2__DATA_MASK 0xFFFFFFFFL
-//MMSCH_GPUIOV_DW7_2
-#define MMSCH_GPUIOV_DW7_2__DATA__SHIFT 0x0
-#define MMSCH_GPUIOV_DW7_2__DATA_MASK 0xFFFFFFFFL
-//MMSCH_GPUIOV_DW8_2
-#define MMSCH_GPUIOV_DW8_2__DATA__SHIFT 0x0
-#define MMSCH_GPUIOV_DW8_2__DATA_MASK 0xFFFFFFFFL
-//MMSCH_GPUIOV_SCH_BLOCK_IP_2
-#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__ID__SHIFT 0x0
-#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__VERSION__SHIFT 0x4
-#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE__SHIFT 0x8
-#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__ID_MASK 0x0000000FL
-#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__VERSION_MASK 0x000000F0L
-#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE_MASK 0x0000FF00L
-//MMSCH_GPUIOV_CMD_STATUS_IP_2
-#define MMSCH_GPUIOV_CMD_STATUS_IP_2__CMD_STATUS__SHIFT 0x0
-#define MMSCH_GPUIOV_CMD_STATUS_IP_2__CMD_STATUS_MASK 0x0000000FL
-//MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2
-#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID__SHIFT 0x0
-#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_STATUS__SHIFT 0x8
-#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_MASK 0x000000FFL
-#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_STATUS_MASK 0x00000F00L
-//MMSCH_VFID_FIFO_HEAD_2
-#define MMSCH_VFID_FIFO_HEAD_2__HEAD__SHIFT 0x0
-#define MMSCH_VFID_FIFO_HEAD_2__HEAD_MASK 0x0000003FL
-//MMSCH_VFID_FIFO_TAIL_2
-#define MMSCH_VFID_FIFO_TAIL_2__TAIL__SHIFT 0x0
-#define MMSCH_VFID_FIFO_TAIL_2__TAIL_MASK 0x0000003FL
-//MMSCH_VM_BUSY_STATUS_0
-#define MMSCH_VM_BUSY_STATUS_0__BUSY__SHIFT 0x0
-#define MMSCH_VM_BUSY_STATUS_0__BUSY_MASK 0xFFFFFFFFL
-//MMSCH_VM_BUSY_STATUS_1
-#define MMSCH_VM_BUSY_STATUS_1__BUSY__SHIFT 0x0
-#define MMSCH_VM_BUSY_STATUS_1__BUSY_MASK 0xFFFFFFFFL
-//MMSCH_VM_BUSY_STATUS_2
-#define MMSCH_VM_BUSY_STATUS_2__BUSY__SHIFT 0x0
-#define MMSCH_VM_BUSY_STATUS_2__BUSY_MASK 0xFFFFFFFFL
-
-
-// addressBlock: uvd0_uvd_jmi_dec
-//UVD_JADP_MCIF_URGENT_CTRL
-#define UVD_JADP_MCIF_URGENT_CTRL__WR_WATERMARK__SHIFT 0x0
-#define UVD_JADP_MCIF_URGENT_CTRL__RD_WATERMARK__SHIFT 0x6
-#define UVD_JADP_MCIF_URGENT_CTRL__WR_RD_URGENT_TIMER__SHIFT 0xb
-#define UVD_JADP_MCIF_URGENT_CTRL__WR_URGENT_PROG_STEP__SHIFT 0x11
-#define UVD_JADP_MCIF_URGENT_CTRL__RD_URGENT_PROG_STEP__SHIFT 0x15
-#define UVD_JADP_MCIF_URGENT_CTRL__WR_QOS_EN__SHIFT 0x19
-#define UVD_JADP_MCIF_URGENT_CTRL__RD_QOS_EN__SHIFT 0x1a
-#define UVD_JADP_MCIF_URGENT_CTRL__WR_WATERMARK_MASK 0x0000003FL
-#define UVD_JADP_MCIF_URGENT_CTRL__RD_WATERMARK_MASK 0x000007C0L
-#define UVD_JADP_MCIF_URGENT_CTRL__WR_RD_URGENT_TIMER_MASK 0x0001F800L
-#define UVD_JADP_MCIF_URGENT_CTRL__WR_URGENT_PROG_STEP_MASK 0x001E0000L
-#define UVD_JADP_MCIF_URGENT_CTRL__RD_URGENT_PROG_STEP_MASK 0x01E00000L
-#define UVD_JADP_MCIF_URGENT_CTRL__WR_QOS_EN_MASK 0x02000000L
-#define UVD_JADP_MCIF_URGENT_CTRL__RD_QOS_EN_MASK 0x04000000L
-//UVD_JMI_URGENT_CTRL
-#define UVD_JMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL__SHIFT 0x0
-#define UVD_JMI_URGENT_CTRL__ASSERT_MC_RD_URGENT__SHIFT 0x4
-#define UVD_JMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL__SHIFT 0x10
-#define UVD_JMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT 0x14
-#define UVD_JMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL_MASK 0x00000001L
-#define UVD_JMI_URGENT_CTRL__ASSERT_MC_RD_URGENT_MASK 0x000000F0L
-#define UVD_JMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL_MASK 0x00010000L
-#define UVD_JMI_URGENT_CTRL__ASSERT_MC_WR_URGENT_MASK 0x00F00000L
-//UVD_JPEG_DEC_PF_CTRL
-#define UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS__SHIFT 0x0
-#define UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING__SHIFT 0x1
-#define UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS_MASK 0x00000001L
-#define UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING_MASK 0x00000002L
-//UVD_JPEG_ENC_PF_CTRL
-#define UVD_JPEG_ENC_PF_CTRL__ENC_PF_HANDLING_DIS__SHIFT 0x0
-#define UVD_JPEG_ENC_PF_CTRL__ENC_PF_SW_GATING__SHIFT 0x1
-#define UVD_JPEG_ENC_PF_CTRL__ENC_PF_HANDLING_DIS_MASK 0x00000001L
-#define UVD_JPEG_ENC_PF_CTRL__ENC_PF_SW_GATING_MASK 0x00000002L
-//UVD_JMI_CTRL
-#define UVD_JMI_CTRL__STALL_MC_ARB__SHIFT 0x0
-#define UVD_JMI_CTRL__MASK_MC_URGENT__SHIFT 0x1
-#define UVD_JMI_CTRL__ASSERT_MC_URGENT__SHIFT 0x2
-#define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER__SHIFT 0x8
-#define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER__SHIFT 0x10
-#define UVD_JMI_CTRL__CRC_RESET__SHIFT 0x18
-#define UVD_JMI_CTRL__CRC_SEL__SHIFT 0x19
-#define UVD_JMI_CTRL__STALL_MC_ARB_MASK 0x00000001L
-#define UVD_JMI_CTRL__MASK_MC_URGENT_MASK 0x00000002L
-#define UVD_JMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000004L
-#define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER_MASK 0x0000FF00L
-#define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER_MASK 0x00FF0000L
-#define UVD_JMI_CTRL__CRC_RESET_MASK 0x01000000L
-#define UVD_JMI_CTRL__CRC_SEL_MASK 0x1E000000L
-//UVD_LMI_JRBC_CTRL
-#define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0
-#define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1
-#define UVD_LMI_JRBC_CTRL__RD_MAX_BURST__SHIFT 0x4
-#define UVD_LMI_JRBC_CTRL__WR_MAX_BURST__SHIFT 0x8
-#define UVD_LMI_JRBC_CTRL__RD_SWAP__SHIFT 0x14
-#define UVD_LMI_JRBC_CTRL__WR_SWAP__SHIFT 0x16
-#define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L
-#define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L
-#define UVD_LMI_JRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L
-#define UVD_LMI_JRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L
-#define UVD_LMI_JRBC_CTRL__RD_SWAP_MASK 0x00300000L
-#define UVD_LMI_JRBC_CTRL__WR_SWAP_MASK 0x00C00000L
-//UVD_LMI_JPEG_CTRL
-#define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0
-#define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1
-#define UVD_LMI_JPEG_CTRL__RD_MAX_BURST__SHIFT 0x4
-#define UVD_LMI_JPEG_CTRL__WR_MAX_BURST__SHIFT 0x8
-#define UVD_LMI_JPEG_CTRL__RD_SWAP__SHIFT 0x14
-#define UVD_LMI_JPEG_CTRL__WR_SWAP__SHIFT 0x16
-#define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L
-#define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L
-#define UVD_LMI_JPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L
-#define UVD_LMI_JPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L
-#define UVD_LMI_JPEG_CTRL__RD_SWAP_MASK 0x00300000L
-#define UVD_LMI_JPEG_CTRL__WR_SWAP_MASK 0x00C00000L
-//UVD_JMI_EJRBC_CTRL
-#define UVD_JMI_EJRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0
-#define UVD_JMI_EJRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1
-#define UVD_JMI_EJRBC_CTRL__RD_MAX_BURST__SHIFT 0x4
-#define UVD_JMI_EJRBC_CTRL__WR_MAX_BURST__SHIFT 0x8
-#define UVD_JMI_EJRBC_CTRL__RD_SWAP__SHIFT 0x14
-#define UVD_JMI_EJRBC_CTRL__WR_SWAP__SHIFT 0x16
-#define UVD_JMI_EJRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L
-#define UVD_JMI_EJRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L
-#define UVD_JMI_EJRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L
-#define UVD_JMI_EJRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L
-#define UVD_JMI_EJRBC_CTRL__RD_SWAP_MASK 0x00300000L
-#define UVD_JMI_EJRBC_CTRL__WR_SWAP_MASK 0x00C00000L
-//UVD_LMI_EJPEG_CTRL
-#define UVD_LMI_EJPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0
-#define UVD_LMI_EJPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1
-#define UVD_LMI_EJPEG_CTRL__RD_MAX_BURST__SHIFT 0x4
-#define UVD_LMI_EJPEG_CTRL__WR_MAX_BURST__SHIFT 0x8
-#define UVD_LMI_EJPEG_CTRL__RD_SWAP__SHIFT 0x14
-#define UVD_LMI_EJPEG_CTRL__WR_SWAP__SHIFT 0x16
-#define UVD_LMI_EJPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L
-#define UVD_LMI_EJPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L
-#define UVD_LMI_EJPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L
-#define UVD_LMI_EJPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L
-#define UVD_LMI_EJPEG_CTRL__RD_SWAP_MASK 0x00300000L
-#define UVD_LMI_EJPEG_CTRL__WR_SWAP_MASK 0x00C00000L
-//UVD_JMI_SCALER_CTRL
-#define UVD_JMI_SCALER_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0
-#define UVD_JMI_SCALER_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1
-#define UVD_JMI_SCALER_CTRL__RD_MAX_BURST__SHIFT 0x4
-#define UVD_JMI_SCALER_CTRL__WR_MAX_BURST__SHIFT 0x8
-#define UVD_JMI_SCALER_CTRL__RD_SWAP__SHIFT 0x14
-#define UVD_JMI_SCALER_CTRL__WR_SWAP__SHIFT 0x16
-#define UVD_JMI_SCALER_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L
-#define UVD_JMI_SCALER_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L
-#define UVD_JMI_SCALER_CTRL__RD_MAX_BURST_MASK 0x000000F0L
-#define UVD_JMI_SCALER_CTRL__WR_MAX_BURST_MASK 0x00000F00L
-#define UVD_JMI_SCALER_CTRL__RD_SWAP_MASK 0x00300000L
-#define UVD_JMI_SCALER_CTRL__WR_SWAP_MASK 0x00C00000L
-//JPEG_LMI_DROP
-#define JPEG_LMI_DROP__JPEG_WR_DROP__SHIFT 0x0
-#define JPEG_LMI_DROP__JRBC_WR_DROP__SHIFT 0x1
-#define JPEG_LMI_DROP__JPEG_RD_DROP__SHIFT 0x2
-#define JPEG_LMI_DROP__JRBC_RD_DROP__SHIFT 0x3
-#define JPEG_LMI_DROP__JPEG_WR_DROP_MASK 0x00000001L
-#define JPEG_LMI_DROP__JRBC_WR_DROP_MASK 0x00000002L
-#define JPEG_LMI_DROP__JPEG_RD_DROP_MASK 0x00000004L
-#define JPEG_LMI_DROP__JRBC_RD_DROP_MASK 0x00000008L
-//UVD_JMI_EJPEG_DROP
-#define UVD_JMI_EJPEG_DROP__EJRBC_RD_DROP__SHIFT 0x0
-#define UVD_JMI_EJPEG_DROP__EJRBC_WR_DROP__SHIFT 0x1
-#define UVD_JMI_EJPEG_DROP__EJPEG_RD_DROP__SHIFT 0x2
-#define UVD_JMI_EJPEG_DROP__EJPEG_WR_DROP__SHIFT 0x3
-#define UVD_JMI_EJPEG_DROP__SCALAR_RD_DROP__SHIFT 0x4
-#define UVD_JMI_EJPEG_DROP__SCALAR_WR_DROP__SHIFT 0x5
-#define UVD_JMI_EJPEG_DROP__EJRBC_RD_DROP_MASK 0x00000001L
-#define UVD_JMI_EJPEG_DROP__EJRBC_WR_DROP_MASK 0x00000002L
-#define UVD_JMI_EJPEG_DROP__EJPEG_RD_DROP_MASK 0x00000004L
-#define UVD_JMI_EJPEG_DROP__EJPEG_WR_DROP_MASK 0x00000008L
-#define UVD_JMI_EJPEG_DROP__SCALAR_RD_DROP_MASK 0x00000010L
-#define UVD_JMI_EJPEG_DROP__SCALAR_WR_DROP_MASK 0x00000020L
-//JPEG_MEMCHECK_CLAMPING
-#define JPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN__SHIFT 0xd
-#define JPEG_MEMCHECK_CLAMPING__JPEG2_WR_CLAMPING_EN__SHIFT 0xe
-#define JPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN__SHIFT 0x16
-#define JPEG_MEMCHECK_CLAMPING__JPEG2_RD_CLAMPING_EN__SHIFT 0x17
-#define JPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN__SHIFT 0x19
-#define JPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN__SHIFT 0x1a
-#define JPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN__SHIFT 0x1f
-#define JPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN_MASK 0x00002000L
-#define JPEG_MEMCHECK_CLAMPING__JPEG2_WR_CLAMPING_EN_MASK 0x00004000L
-#define JPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN_MASK 0x00400000L
-#define JPEG_MEMCHECK_CLAMPING__JPEG2_RD_CLAMPING_EN_MASK 0x00800000L
-#define JPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN_MASK 0x02000000L
-#define JPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN_MASK 0x04000000L
-#define JPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN_MASK 0x80000000L
-//UVD_JMI_EJPEG_MEMCHECK_CLAMPING
-#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN__SHIFT 0x0
-#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN__SHIFT 0x1
-#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN__SHIFT 0x2
-#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN__SHIFT 0x3
-#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_RD_CLAMPING_EN__SHIFT 0x4
-#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_WR_CLAMPING_EN__SHIFT 0x5
-#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN__SHIFT 0x1f
-#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_RD_CLAMPING_EN_MASK 0x00000001L
-#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JRBC_WR_CLAMPING_EN_MASK 0x00000002L
-#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_RD_CLAMPING_EN_MASK 0x00000004L
-#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__JPEG_WR_CLAMPING_EN_MASK 0x00000008L
-#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_RD_CLAMPING_EN_MASK 0x00000010L
-#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_WR_CLAMPING_EN_MASK 0x00000020L
-#define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__CLAMP_TO_SAFE_ADDR_EN_MASK 0x80000000L
-//UVD_LMI_JRBC_IB_VMID
-#define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0
-#define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4
-#define UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8
-#define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL
-#define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L
-#define UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L
-//UVD_LMI_JRBC_RB_VMID
-#define UVD_LMI_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0
-#define UVD_LMI_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4
-#define UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8
-#define UVD_LMI_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL
-#define UVD_LMI_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L
-#define UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L
-//UVD_LMI_JPEG_VMID
-#define UVD_LMI_JPEG_VMID__JPEG_RD_VMID__SHIFT 0x0
-#define UVD_LMI_JPEG_VMID__JPEG_WR_VMID__SHIFT 0x4
-#define UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID__SHIFT 0x8
-#define UVD_LMI_JPEG_VMID__JPEG_RD_VMID_MASK 0x0000000FL
-#define UVD_LMI_JPEG_VMID__JPEG_WR_VMID_MASK 0x000000F0L
-#define UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID_MASK 0x00000F00L
-//UVD_JMI_ENC_JRBC_IB_VMID
-#define UVD_JMI_ENC_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0
-#define UVD_JMI_ENC_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4
-#define UVD_JMI_ENC_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8
-#define UVD_JMI_ENC_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL
-#define UVD_JMI_ENC_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L
-#define UVD_JMI_ENC_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L
-//UVD_JMI_ENC_JRBC_RB_VMID
-#define UVD_JMI_ENC_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0
-#define UVD_JMI_ENC_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4
-#define UVD_JMI_ENC_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8
-#define UVD_JMI_ENC_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL
-#define UVD_JMI_ENC_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L
-#define UVD_JMI_ENC_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L
-//UVD_JMI_ENC_JPEG_VMID
-#define UVD_JMI_ENC_JPEG_VMID__PEL_RD_VMID__SHIFT 0x0
-#define UVD_JMI_ENC_JPEG_VMID__BS_WR_VMID__SHIFT 0x5
-#define UVD_JMI_ENC_JPEG_VMID__SCALAR_RD_VMID__SHIFT 0xa
-#define UVD_JMI_ENC_JPEG_VMID__SCALAR_WR_VMID__SHIFT 0xf
-#define UVD_JMI_ENC_JPEG_VMID__HUFF_FENCE_VMID__SHIFT 0x13
-#define UVD_JMI_ENC_JPEG_VMID__ATOMIC_USER1_WR_VMID__SHIFT 0x17
-#define UVD_JMI_ENC_JPEG_VMID__PEL_RD_VMID_MASK 0x0000000FL
-#define UVD_JMI_ENC_JPEG_VMID__BS_WR_VMID_MASK 0x000001E0L
-#define UVD_JMI_ENC_JPEG_VMID__SCALAR_RD_VMID_MASK 0x00003C00L
-#define UVD_JMI_ENC_JPEG_VMID__SCALAR_WR_VMID_MASK 0x00078000L
-#define UVD_JMI_ENC_JPEG_VMID__HUFF_FENCE_VMID_MASK 0x00780000L
-#define UVD_JMI_ENC_JPEG_VMID__ATOMIC_USER1_WR_VMID_MASK 0x07800000L
-//UVD_JMI_EJPEG_RAS_CNTL
-#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_IH_EN__SHIFT 0x0
-#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_PMI_EN__SHIFT 0x1
-#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_REARM__SHIFT 0x2
-#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_STALL_EN__SHIFT 0x3
-#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_READY__SHIFT 0x4
-#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_IH_EN_MASK 0x00000001L
-#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_PMI_EN_MASK 0x00000002L
-#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_REARM_MASK 0x00000004L
-#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_STALL_EN_MASK 0x00000008L
-#define UVD_JMI_EJPEG_RAS_CNTL__EJPEG_READY_MASK 0x00000010L
-//JPEG_MEMCHECK_SAFE_ADDR
-#define JPEG_MEMCHECK_SAFE_ADDR__MEMCHECK_SAFE_ADDR__SHIFT 0x0
-#define JPEG_MEMCHECK_SAFE_ADDR__MEMCHECK_SAFE_ADDR_MASK 0xFFFFFFFFL
-//JPEG_MEMCHECK_SAFE_ADDR_64BIT
-#define JPEG_MEMCHECK_SAFE_ADDR_64BIT__MEMCHECK_SAFE_ADDR_64BIT__SHIFT 0x0
-#define JPEG_MEMCHECK_SAFE_ADDR_64BIT__MEMCHECK_SAFE_ADDR_64BIT_MASK 0xFFFFFFFFL
-//UVD_JMI_LAT_CTRL
-#define UVD_JMI_LAT_CTRL__SCALE__SHIFT 0x0
-#define UVD_JMI_LAT_CTRL__MAX_START__SHIFT 0x8
-#define UVD_JMI_LAT_CTRL__MIN_START__SHIFT 0x9
-#define UVD_JMI_LAT_CTRL__AVG_START__SHIFT 0xa
-#define UVD_JMI_LAT_CTRL__PERFMON_SYNC__SHIFT 0xb
-#define UVD_JMI_LAT_CTRL__SKIP__SHIFT 0x10
-#define UVD_JMI_LAT_CTRL__SCALE_MASK 0x000000FFL
-#define UVD_JMI_LAT_CTRL__MAX_START_MASK 0x00000100L
-#define UVD_JMI_LAT_CTRL__MIN_START_MASK 0x00000200L
-#define UVD_JMI_LAT_CTRL__AVG_START_MASK 0x00000400L
-#define UVD_JMI_LAT_CTRL__PERFMON_SYNC_MASK 0x00000800L
-#define UVD_JMI_LAT_CTRL__SKIP_MASK 0x000F0000L
-//UVD_JMI_LAT_CNTR
-#define UVD_JMI_LAT_CNTR__MAX_LAT__SHIFT 0x0
-#define UVD_JMI_LAT_CNTR__MIN_LAT__SHIFT 0x8
-#define UVD_JMI_LAT_CNTR__MAX_LAT_MASK 0x000000FFL
-#define UVD_JMI_LAT_CNTR__MIN_LAT_MASK 0x0000FF00L
-//UVD_JMI_AVG_LAT_CNTR
-#define UVD_JMI_AVG_LAT_CNTR__ENV_LOW__SHIFT 0x0
-#define UVD_JMI_AVG_LAT_CNTR__ENV_HIGH__SHIFT 0x8
-#define UVD_JMI_AVG_LAT_CNTR__ENV_HIT__SHIFT 0x10
-#define UVD_JMI_AVG_LAT_CNTR__ENV_LOW_MASK 0x000000FFL
-#define UVD_JMI_AVG_LAT_CNTR__ENV_HIGH_MASK 0x0000FF00L
-#define UVD_JMI_AVG_LAT_CNTR__ENV_HIT_MASK 0xFFFF0000L
-//UVD_JMI_PERFMON_CTRL
-#define UVD_JMI_PERFMON_CTRL__PERFMON_STATE__SHIFT 0x0
-#define UVD_JMI_PERFMON_CTRL__PERFMON_SEL__SHIFT 0x8
-#define UVD_JMI_PERFMON_CTRL__PERFMON_STATE_MASK 0x00000003L
-#define UVD_JMI_PERFMON_CTRL__PERFMON_SEL_MASK 0x00000F00L
-//UVD_JMI_PERFMON_COUNT_LO
-#define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT 0x0
-#define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK 0xFFFFFFFFL
-//UVD_JMI_PERFMON_COUNT_HI
-#define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT 0x0
-#define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK 0x0000FFFFL
-//UVD_JMI_CLEAN_STATUS
-#define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN__SHIFT 0x0
-#define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN_RAW__SHIFT 0x1
-#define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN__SHIFT 0x2
-#define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN_RAW__SHIFT 0x3
-#define UVD_JMI_CLEAN_STATUS__DJRBC_READ_CLEAN__SHIFT 0x4
-#define UVD_JMI_CLEAN_STATUS__EJRBC_READ_CLEAN__SHIFT 0x5
-#define UVD_JMI_CLEAN_STATUS__JPEG_READ_CLEAN__SHIFT 0x6
-#define UVD_JMI_CLEAN_STATUS__PEL_READ_CLEAN__SHIFT 0x7
-#define UVD_JMI_CLEAN_STATUS__SCALAR_READ_CLEAN__SHIFT 0x8
-#define UVD_JMI_CLEAN_STATUS__DJRBC_WRITE_CLEAN__SHIFT 0x9
-#define UVD_JMI_CLEAN_STATUS__EJRBC_WRITE_CLEAN__SHIFT 0xa
-#define UVD_JMI_CLEAN_STATUS__BS_WRITE_CLEAN__SHIFT 0xb
-#define UVD_JMI_CLEAN_STATUS__JPEG_WRITE_CLEAN__SHIFT 0xc
-#define UVD_JMI_CLEAN_STATUS__SCALAR_WRITE_CLEAN__SHIFT 0xd
-#define UVD_JMI_CLEAN_STATUS__MC_WRITE_PENDING__SHIFT 0xe
-#define UVD_JMI_CLEAN_STATUS__JPEG2_WRITE_CLEAN__SHIFT 0xf
-#define UVD_JMI_CLEAN_STATUS__JPEG2_READ_CLEAN__SHIFT 0x10
-#define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN_MASK 0x00000001L
-#define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN_RAW_MASK 0x00000002L
-#define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN_MASK 0x00000004L
-#define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN_RAW_MASK 0x00000008L
-#define UVD_JMI_CLEAN_STATUS__DJRBC_READ_CLEAN_MASK 0x00000010L
-#define UVD_JMI_CLEAN_STATUS__EJRBC_READ_CLEAN_MASK 0x00000020L
-#define UVD_JMI_CLEAN_STATUS__JPEG_READ_CLEAN_MASK 0x00000040L
-#define UVD_JMI_CLEAN_STATUS__PEL_READ_CLEAN_MASK 0x00000080L
-#define UVD_JMI_CLEAN_STATUS__SCALAR_READ_CLEAN_MASK 0x00000100L
-#define UVD_JMI_CLEAN_STATUS__DJRBC_WRITE_CLEAN_MASK 0x00000200L
-#define UVD_JMI_CLEAN_STATUS__EJRBC_WRITE_CLEAN_MASK 0x00000400L
-#define UVD_JMI_CLEAN_STATUS__BS_WRITE_CLEAN_MASK 0x00000800L
-#define UVD_JMI_CLEAN_STATUS__JPEG_WRITE_CLEAN_MASK 0x00001000L
-#define UVD_JMI_CLEAN_STATUS__SCALAR_WRITE_CLEAN_MASK 0x00002000L
-#define UVD_JMI_CLEAN_STATUS__MC_WRITE_PENDING_MASK 0x00004000L
-#define UVD_JMI_CLEAN_STATUS__JPEG2_WRITE_CLEAN_MASK 0x00008000L
-#define UVD_JMI_CLEAN_STATUS__JPEG2_READ_CLEAN_MASK 0x00010000L
-//UVD_LMI_JPEG_READ_64BIT_BAR_LOW
-#define UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_JPEG_READ_64BIT_BAR_HIGH
-#define UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW
-#define UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH
-#define UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW
-#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH
-#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_JRBC_RB_64BIT_BAR_LOW
-#define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_JRBC_RB_64BIT_BAR_HIGH
-#define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_JRBC_IB_64BIT_BAR_LOW
-#define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_JRBC_IB_64BIT_BAR_HIGH
-#define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW
-#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH
-#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW
-#define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH
-#define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW
-#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH
-#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW
-#define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH
-#define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_JMI_PEL_RD_64BIT_BAR_LOW
-#define UVD_JMI_PEL_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_JMI_PEL_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_JMI_PEL_RD_64BIT_BAR_HIGH
-#define UVD_JMI_PEL_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_JMI_PEL_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_JMI_BS_WR_64BIT_BAR_LOW
-#define UVD_JMI_BS_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_JMI_BS_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_JMI_BS_WR_64BIT_BAR_HIGH
-#define UVD_JMI_BS_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_JMI_BS_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_JMI_SCALAR_RD_64BIT_BAR_LOW
-#define UVD_JMI_SCALAR_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_JMI_SCALAR_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_JMI_SCALAR_RD_64BIT_BAR_HIGH
-#define UVD_JMI_SCALAR_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_JMI_SCALAR_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_JMI_SCALAR_WR_64BIT_BAR_LOW
-#define UVD_JMI_SCALAR_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_JMI_SCALAR_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_JMI_SCALAR_WR_64BIT_BAR_HIGH
-#define UVD_JMI_SCALAR_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_JMI_SCALAR_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW
-#define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH
-#define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_EJRBC_RB_64BIT_BAR_LOW
-#define UVD_LMI_EJRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_EJRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH
-#define UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_EJRBC_IB_64BIT_BAR_LOW
-#define UVD_LMI_EJRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_EJRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH
-#define UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW
-#define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH
-#define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW
-#define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH
-#define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW
-#define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH
-#define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW
-#define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH
-#define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_JPEG_PREEMPT_VMID
-#define UVD_LMI_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0
-#define UVD_LMI_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL
-//UVD_LMI_ENC_JPEG_PREEMPT_VMID
-#define UVD_LMI_ENC_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0
-#define UVD_LMI_ENC_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL
-//UVD_LMI_JPEG2_VMID
-#define UVD_LMI_JPEG2_VMID__JPEG2_RD_VMID__SHIFT 0x0
-#define UVD_LMI_JPEG2_VMID__JPEG2_WR_VMID__SHIFT 0x4
-#define UVD_LMI_JPEG2_VMID__JPEG2_RD_VMID_MASK 0x0000000FL
-#define UVD_LMI_JPEG2_VMID__JPEG2_WR_VMID_MASK 0x000000F0L
-//UVD_LMI_JPEG2_READ_64BIT_BAR_LOW
-#define UVD_LMI_JPEG2_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_JPEG2_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH
-#define UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW
-#define UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH
-#define UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_LMI_JPEG_CTRL2
-#define UVD_LMI_JPEG_CTRL2__ARB_RD_WAIT_EN__SHIFT 0x0
-#define UVD_LMI_JPEG_CTRL2__ARB_WR_WAIT_EN__SHIFT 0x1
-#define UVD_LMI_JPEG_CTRL2__RD_MAX_BURST__SHIFT 0x4
-#define UVD_LMI_JPEG_CTRL2__WR_MAX_BURST__SHIFT 0x8
-#define UVD_LMI_JPEG_CTRL2__RD_SWAP__SHIFT 0x14
-#define UVD_LMI_JPEG_CTRL2__WR_SWAP__SHIFT 0x16
-#define UVD_LMI_JPEG_CTRL2__ARB_RD_WAIT_EN_MASK 0x00000001L
-#define UVD_LMI_JPEG_CTRL2__ARB_WR_WAIT_EN_MASK 0x00000002L
-#define UVD_LMI_JPEG_CTRL2__RD_MAX_BURST_MASK 0x000000F0L
-#define UVD_LMI_JPEG_CTRL2__WR_MAX_BURST_MASK 0x00000F00L
-#define UVD_LMI_JPEG_CTRL2__RD_SWAP_MASK 0x00300000L
-#define UVD_LMI_JPEG_CTRL2__WR_SWAP_MASK 0x00C00000L
-//UVD_JMI_DEC_SWAP_CNTL
-#define UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0
-#define UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2
-#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4
-#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6
-#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8
-#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa
-#define UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc
-#define UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP__SHIFT 0xe
-#define UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP__SHIFT 0x10
-#define UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L
-#define UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL
-#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L
-#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L
-#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L
-#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L
-#define UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L
-#define UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP_MASK 0x0000C000L
-#define UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP_MASK 0x00030000L
-//UVD_JMI_ENC_SWAP_CNTL
-#define UVD_JMI_ENC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0
-#define UVD_JMI_ENC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2
-#define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4
-#define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6
-#define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8
-#define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa
-#define UVD_JMI_ENC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc
-#define UVD_JMI_ENC_SWAP_CNTL__PEL_RD_MC_SWAP__SHIFT 0xe
-#define UVD_JMI_ENC_SWAP_CNTL__BS_WR_MC_SWAP__SHIFT 0x10
-#define UVD_JMI_ENC_SWAP_CNTL__SCALAR_RD_MC_SWAP__SHIFT 0x12
-#define UVD_JMI_ENC_SWAP_CNTL__SCALAR_WR_MC_SWAP__SHIFT 0x14
-#define UVD_JMI_ENC_SWAP_CNTL__HUFF_FENCE_MC_SWAP__SHIFT 0x16
-#define UVD_JMI_ENC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L
-#define UVD_JMI_ENC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL
-#define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L
-#define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L
-#define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L
-#define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L
-#define UVD_JMI_ENC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L
-#define UVD_JMI_ENC_SWAP_CNTL__PEL_RD_MC_SWAP_MASK 0x0000C000L
-#define UVD_JMI_ENC_SWAP_CNTL__BS_WR_MC_SWAP_MASK 0x00030000L
-#define UVD_JMI_ENC_SWAP_CNTL__SCALAR_RD_MC_SWAP_MASK 0x000C0000L
-#define UVD_JMI_ENC_SWAP_CNTL__SCALAR_WR_MC_SWAP_MASK 0x00300000L
-#define UVD_JMI_ENC_SWAP_CNTL__HUFF_FENCE_MC_SWAP_MASK 0x00C00000L
-//UVD_JMI_CNTL
-#define UVD_JMI_CNTL__SOFT_RESET__SHIFT 0x0
-#define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX__SHIFT 0x8
-#define UVD_JMI_CNTL__SOFT_RESET_MASK 0x00000001L
-#define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX_MASK 0x0003FF00L
-//UVD_JMI_ATOMIC_CNTL
-#define UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en__SHIFT 0x0
-#define UVD_JMI_ATOMIC_CNTL__atomic_max_burst__SHIFT 0x1
-#define UVD_JMI_ATOMIC_CNTL__atomic_wr_drop__SHIFT 0x5
-#define UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en__SHIFT 0x6
-#define UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG__SHIFT 0x7
-#define UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE__SHIFT 0xb
-#define UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en_MASK 0x00000001L
-#define UVD_JMI_ATOMIC_CNTL__atomic_max_burst_MASK 0x0000001EL
-#define UVD_JMI_ATOMIC_CNTL__atomic_wr_drop_MASK 0x00000020L
-#define UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en_MASK 0x00000040L
-#define UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG_MASK 0x00000780L
-#define UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE_MASK 0x00000800L
-//UVD_JMI_ATOMIC_CNTL2
-#define UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap__SHIFT 0x10
-#define UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP__SHIFT 0x18
-#define UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap_MASK 0x00FF0000L
-#define UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP_MASK 0xFF000000L
-//UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW
-#define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH
-#define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW
-#define UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH
-#define UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//JPEG2_LMI_DROP
-#define JPEG2_LMI_DROP__JPEG2_WR_DROP__SHIFT 0x0
-#define JPEG2_LMI_DROP__JPEG2_RD_DROP__SHIFT 0x1
-#define JPEG2_LMI_DROP__JPEG2_WR_DROP_MASK 0x00000001L
-#define JPEG2_LMI_DROP__JPEG2_RD_DROP_MASK 0x00000002L
-//UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW
-#define UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH
-#define UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_JMI_DEC_SWAP_CNTL2
-#define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_RD_MC_SWAP__SHIFT 0x0
-#define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_WR_MC_SWAP__SHIFT 0x2
-#define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_RD_MC_SWAP_MASK 0x00000003L
-#define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_WR_MC_SWAP_MASK 0x0000000CL
-//UVD_JMI_DJPEG_RAS_CNTL
-#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_IH_EN__SHIFT 0x0
-#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_PMI_EN__SHIFT 0x1
-#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_REARM__SHIFT 0x2
-#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_STALL_EN__SHIFT 0x3
-#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_READY__SHIFT 0x4
-#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_IH_EN_MASK 0x00000001L
-#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_PMI_EN_MASK 0x00000002L
-#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_REARM_MASK 0x00000004L
-#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_STALL_EN_MASK 0x00000008L
-#define UVD_JMI_DJPEG_RAS_CNTL__DJPEG_READY_MASK 0x00000010L
-
-
-// addressBlock: uvd0_uvd_jpeg_common_dec
-//JPEG_SOFT_RESET_STATUS
-#define JPEG_SOFT_RESET_STATUS__JPEG_DEC_RESET_STATUS__SHIFT 0x0
-#define JPEG_SOFT_RESET_STATUS__JPEG2_DEC_RESET_STATUS__SHIFT 0x1
-#define JPEG_SOFT_RESET_STATUS__DJRBC_RESET_STATUS__SHIFT 0x2
-#define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS__SHIFT 0x3
-#define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS__SHIFT 0x4
-#define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS__SHIFT 0x5
-#define JPEG_SOFT_RESET_STATUS__JPEG_DEC_RESET_STATUS_MASK 0x00000001L
-#define JPEG_SOFT_RESET_STATUS__JPEG2_DEC_RESET_STATUS_MASK 0x00000002L
-#define JPEG_SOFT_RESET_STATUS__DJRBC_RESET_STATUS_MASK 0x00000004L
-#define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS_MASK 0x00000008L
-#define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS_MASK 0x00000010L
-#define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS_MASK 0x00000020L
-//JPEG_SYS_INT_EN
-#define JPEG_SYS_INT_EN__DJPEG_CORE__SHIFT 0x0
-#define JPEG_SYS_INT_EN__DJRBC__SHIFT 0x1
-#define JPEG_SYS_INT_EN__DJPEG_PF_RPT__SHIFT 0x2
-#define JPEG_SYS_INT_EN__EJPEG_PF_RPT__SHIFT 0x3
-#define JPEG_SYS_INT_EN__EJPEG_CORE__SHIFT 0x4
-#define JPEG_SYS_INT_EN__EJRBC__SHIFT 0x5
-#define JPEG_SYS_INT_EN__DJPEG_CORE2__SHIFT 0x6
-#define JPEG_SYS_INT_EN__DJPEG_RAS_CNTL__SHIFT 0x7
-#define JPEG_SYS_INT_EN__EJPEG_RAS_CNTL__SHIFT 0x8
-#define JPEG_SYS_INT_EN__DJPEG_CORE_MASK 0x00000001L
-#define JPEG_SYS_INT_EN__DJRBC_MASK 0x00000002L
-#define JPEG_SYS_INT_EN__DJPEG_PF_RPT_MASK 0x00000004L
-#define JPEG_SYS_INT_EN__EJPEG_PF_RPT_MASK 0x00000008L
-#define JPEG_SYS_INT_EN__EJPEG_CORE_MASK 0x00000010L
-#define JPEG_SYS_INT_EN__EJRBC_MASK 0x00000020L
-#define JPEG_SYS_INT_EN__DJPEG_CORE2_MASK 0x00000040L
-#define JPEG_SYS_INT_EN__DJPEG_RAS_CNTL_MASK 0x00000080L
-#define JPEG_SYS_INT_EN__EJPEG_RAS_CNTL_MASK 0x00000100L
-//JPEG_SYS_INT_STATUS
-#define JPEG_SYS_INT_STATUS__DJPEG_CORE__SHIFT 0x0
-#define JPEG_SYS_INT_STATUS__DJRBC__SHIFT 0x1
-#define JPEG_SYS_INT_STATUS__DJPEG_PF_RPT__SHIFT 0x2
-#define JPEG_SYS_INT_STATUS__EJPEG_PF_RPT__SHIFT 0x3
-#define JPEG_SYS_INT_STATUS__EJPEG_CORE__SHIFT 0x4
-#define JPEG_SYS_INT_STATUS__EJRBC__SHIFT 0x5
-#define JPEG_SYS_INT_STATUS__DJPEG_CORE2__SHIFT 0x6
-#define JPEG_SYS_INT_STATUS__DJPEG_RAS_CNTL__SHIFT 0x7
-#define JPEG_SYS_INT_STATUS__EJPEG_RAS_CNTL__SHIFT 0x8
-#define JPEG_SYS_INT_STATUS__DJPEG_CORE_MASK 0x00000001L
-#define JPEG_SYS_INT_STATUS__DJRBC_MASK 0x00000002L
-#define JPEG_SYS_INT_STATUS__DJPEG_PF_RPT_MASK 0x00000004L
-#define JPEG_SYS_INT_STATUS__EJPEG_PF_RPT_MASK 0x00000008L
-#define JPEG_SYS_INT_STATUS__EJPEG_CORE_MASK 0x00000010L
-#define JPEG_SYS_INT_STATUS__EJRBC_MASK 0x00000020L
-#define JPEG_SYS_INT_STATUS__DJPEG_CORE2_MASK 0x00000040L
-#define JPEG_SYS_INT_STATUS__DJPEG_RAS_CNTL_MASK 0x00000080L
-#define JPEG_SYS_INT_STATUS__EJPEG_RAS_CNTL_MASK 0x00000100L
-//JPEG_SYS_INT_ACK
-#define JPEG_SYS_INT_ACK__DJPEG_CORE__SHIFT 0x0
-#define JPEG_SYS_INT_ACK__DJRBC__SHIFT 0x1
-#define JPEG_SYS_INT_ACK__DJPEG_PF_RPT__SHIFT 0x2
-#define JPEG_SYS_INT_ACK__EJPEG_PF_RPT__SHIFT 0x3
-#define JPEG_SYS_INT_ACK__EJPEG_CORE__SHIFT 0x4
-#define JPEG_SYS_INT_ACK__EJRBC__SHIFT 0x5
-#define JPEG_SYS_INT_ACK__DJPEG_CORE2__SHIFT 0x6
-#define JPEG_SYS_INT_ACK__DJPEG_RAS_CNTL__SHIFT 0x7
-#define JPEG_SYS_INT_ACK__EJPEG_RAS_CNTL__SHIFT 0x8
-#define JPEG_SYS_INT_ACK__DJPEG_CORE_MASK 0x00000001L
-#define JPEG_SYS_INT_ACK__DJRBC_MASK 0x00000002L
-#define JPEG_SYS_INT_ACK__DJPEG_PF_RPT_MASK 0x00000004L
-#define JPEG_SYS_INT_ACK__EJPEG_PF_RPT_MASK 0x00000008L
-#define JPEG_SYS_INT_ACK__EJPEG_CORE_MASK 0x00000010L
-#define JPEG_SYS_INT_ACK__EJRBC_MASK 0x00000020L
-#define JPEG_SYS_INT_ACK__DJPEG_CORE2_MASK 0x00000040L
-#define JPEG_SYS_INT_ACK__DJPEG_RAS_CNTL_MASK 0x00000080L
-#define JPEG_SYS_INT_ACK__EJPEG_RAS_CNTL_MASK 0x00000100L
-//JPEG_MEMCHECK_SYS_INT_EN
-#define JPEG_MEMCHECK_SYS_INT_EN__DJRBC_RD_ERR_EN__SHIFT 0x0
-#define JPEG_MEMCHECK_SYS_INT_EN__EJRBC_RD_ERR_EN__SHIFT 0x1
-#define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH_RD_ERR_EN__SHIFT 0x2
-#define JPEG_MEMCHECK_SYS_INT_EN__PELFETCH_RD_ERR_EN__SHIFT 0x3
-#define JPEG_MEMCHECK_SYS_INT_EN__SCALAR_RD_ERR_EN__SHIFT 0x4
-#define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_RD_ERR_EN__SHIFT 0x5
-#define JPEG_MEMCHECK_SYS_INT_EN__DJRBC_WR_ERR_EN__SHIFT 0x6
-#define JPEG_MEMCHECK_SYS_INT_EN__EJRBC_WR_ERR_EN__SHIFT 0x7
-#define JPEG_MEMCHECK_SYS_INT_EN__BS_WR_ERR_EN__SHIFT 0x8
-#define JPEG_MEMCHECK_SYS_INT_EN__OBUF_WR_ERR_EN__SHIFT 0x9
-#define JPEG_MEMCHECK_SYS_INT_EN__SCALAR_WR_ERR_EN__SHIFT 0xa
-#define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_WR_ERR_EN__SHIFT 0xb
-#define JPEG_MEMCHECK_SYS_INT_EN__DJRBC_RD_ERR_EN_MASK 0x00000001L
-#define JPEG_MEMCHECK_SYS_INT_EN__EJRBC_RD_ERR_EN_MASK 0x00000002L
-#define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH_RD_ERR_EN_MASK 0x00000004L
-#define JPEG_MEMCHECK_SYS_INT_EN__PELFETCH_RD_ERR_EN_MASK 0x00000008L
-#define JPEG_MEMCHECK_SYS_INT_EN__SCALAR_RD_ERR_EN_MASK 0x00000010L
-#define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_RD_ERR_EN_MASK 0x00000020L
-#define JPEG_MEMCHECK_SYS_INT_EN__DJRBC_WR_ERR_EN_MASK 0x00000040L
-#define JPEG_MEMCHECK_SYS_INT_EN__EJRBC_WR_ERR_EN_MASK 0x00000080L
-#define JPEG_MEMCHECK_SYS_INT_EN__BS_WR_ERR_EN_MASK 0x00000100L
-#define JPEG_MEMCHECK_SYS_INT_EN__OBUF_WR_ERR_EN_MASK 0x00000200L
-#define JPEG_MEMCHECK_SYS_INT_EN__SCALAR_WR_ERR_EN_MASK 0x00000400L
-#define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_WR_ERR_EN_MASK 0x00000800L
-//JPEG_MEMCHECK_SYS_INT_STAT
-#define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_RD_HI_ERR__SHIFT 0x0
-#define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_RD_LO_ERR__SHIFT 0x1
-#define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_RD_HI_ERR__SHIFT 0x2
-#define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_RD_LO_ERR__SHIFT 0x3
-#define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_HI_ERR__SHIFT 0x4
-#define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_LO_ERR__SHIFT 0x5
-#define JPEG_MEMCHECK_SYS_INT_STAT__PELFETCH_RD_HI_ERR__SHIFT 0x6
-#define JPEG_MEMCHECK_SYS_INT_STAT__PELFETCH_RD_LO_ERR__SHIFT 0x7
-#define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_RD_HI_ERR__SHIFT 0x8
-#define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_RD_LO_ERR__SHIFT 0x9
-#define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_RD_HI_ERR__SHIFT 0xa
-#define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_RD_LO_ERR__SHIFT 0xb
-#define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_WR_HI_ERR__SHIFT 0xc
-#define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_WR_LO_ERR__SHIFT 0xd
-#define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_WR_HI_ERR__SHIFT 0xe
-#define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_WR_LO_ERR__SHIFT 0xf
-#define JPEG_MEMCHECK_SYS_INT_STAT__BS_WR_HI_ERR__SHIFT 0x10
-#define JPEG_MEMCHECK_SYS_INT_STAT__BS_WR_LO_ERR__SHIFT 0x11
-#define JPEG_MEMCHECK_SYS_INT_STAT__OBUF_WR_HI_ERR__SHIFT 0x12
-#define JPEG_MEMCHECK_SYS_INT_STAT__OBUF_WR_LO_ERR__SHIFT 0x13
-#define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_WR_HI_ERR__SHIFT 0x14
-#define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_WR_LO_ERR__SHIFT 0x15
-#define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_WR_HI_ERR__SHIFT 0x16
-#define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_WR_LO_ERR__SHIFT 0x17
-#define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_RD_HI_ERR_MASK 0x00000001L
-#define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_RD_LO_ERR_MASK 0x00000002L
-#define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_RD_HI_ERR_MASK 0x00000004L
-#define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_RD_LO_ERR_MASK 0x00000008L
-#define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_HI_ERR_MASK 0x00000010L
-#define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_LO_ERR_MASK 0x00000020L
-#define JPEG_MEMCHECK_SYS_INT_STAT__PELFETCH_RD_HI_ERR_MASK 0x00000040L
-#define JPEG_MEMCHECK_SYS_INT_STAT__PELFETCH_RD_LO_ERR_MASK 0x00000080L
-#define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_RD_HI_ERR_MASK 0x00000100L
-#define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_RD_LO_ERR_MASK 0x00000200L
-#define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_RD_HI_ERR_MASK 0x00000400L
-#define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_RD_LO_ERR_MASK 0x00000800L
-#define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_WR_HI_ERR_MASK 0x00001000L
-#define JPEG_MEMCHECK_SYS_INT_STAT__DJRBC_WR_LO_ERR_MASK 0x00002000L
-#define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_WR_HI_ERR_MASK 0x00004000L
-#define JPEG_MEMCHECK_SYS_INT_STAT__EJRBC_WR_LO_ERR_MASK 0x00008000L
-#define JPEG_MEMCHECK_SYS_INT_STAT__BS_WR_HI_ERR_MASK 0x00010000L
-#define JPEG_MEMCHECK_SYS_INT_STAT__BS_WR_LO_ERR_MASK 0x00020000L
-#define JPEG_MEMCHECK_SYS_INT_STAT__OBUF_WR_HI_ERR_MASK 0x00040000L
-#define JPEG_MEMCHECK_SYS_INT_STAT__OBUF_WR_LO_ERR_MASK 0x00080000L
-#define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_WR_HI_ERR_MASK 0x00100000L
-#define JPEG_MEMCHECK_SYS_INT_STAT__SCALAR_WR_LO_ERR_MASK 0x00200000L
-#define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_WR_HI_ERR_MASK 0x00400000L
-#define JPEG_MEMCHECK_SYS_INT_STAT__JPEG2_WR_LO_ERR_MASK 0x00800000L
-//JPEG_MEMCHECK_SYS_INT_ACK
-#define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_RD_HI_ERR__SHIFT 0x0
-#define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_RD_LO_ERR__SHIFT 0x1
-#define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_RD_HI_ERR__SHIFT 0x2
-#define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_RD_LO_ERR__SHIFT 0x3
-#define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_HI_ERR__SHIFT 0x4
-#define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_LO_ERR__SHIFT 0x5
-#define JPEG_MEMCHECK_SYS_INT_ACK__PELFETCH_RD_HI_ERR__SHIFT 0x6
-#define JPEG_MEMCHECK_SYS_INT_ACK__PELFETCH_RD_LO_ERR__SHIFT 0x7
-#define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_RD_HI_ERR__SHIFT 0x8
-#define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_RD_LO_ERR__SHIFT 0x9
-#define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_RD_HI_ERR__SHIFT 0xa
-#define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_RD_LO_ERR__SHIFT 0xb
-#define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_WR_HI_ERR__SHIFT 0xc
-#define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_WR_LO_ERR__SHIFT 0xd
-#define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_WR_HI_ERR__SHIFT 0xe
-#define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_WR_LO_ERR__SHIFT 0xf
-#define JPEG_MEMCHECK_SYS_INT_ACK__BS_WR_HI_ERR__SHIFT 0x10
-#define JPEG_MEMCHECK_SYS_INT_ACK__BS_WR_LO_ERR__SHIFT 0x11
-#define JPEG_MEMCHECK_SYS_INT_ACK__OBUF_WR_HI_ERR__SHIFT 0x12
-#define JPEG_MEMCHECK_SYS_INT_ACK__OBUF_WR_LO_ERR__SHIFT 0x13
-#define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_WR_HI_ERR__SHIFT 0x14
-#define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_WR_LO_ERR__SHIFT 0x15
-#define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_WR_HI_ERR__SHIFT 0x16
-#define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_WR_LO_ERR__SHIFT 0x17
-#define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_RD_HI_ERR_MASK 0x00000001L
-#define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_RD_LO_ERR_MASK 0x00000002L
-#define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_RD_HI_ERR_MASK 0x00000004L
-#define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_RD_LO_ERR_MASK 0x00000008L
-#define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_HI_ERR_MASK 0x00000010L
-#define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_LO_ERR_MASK 0x00000020L
-#define JPEG_MEMCHECK_SYS_INT_ACK__PELFETCH_RD_HI_ERR_MASK 0x00000040L
-#define JPEG_MEMCHECK_SYS_INT_ACK__PELFETCH_RD_LO_ERR_MASK 0x00000080L
-#define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_RD_HI_ERR_MASK 0x00000100L
-#define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_RD_LO_ERR_MASK 0x00000200L
-#define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_RD_HI_ERR_MASK 0x00000400L
-#define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_RD_LO_ERR_MASK 0x00000800L
-#define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_WR_HI_ERR_MASK 0x00001000L
-#define JPEG_MEMCHECK_SYS_INT_ACK__DJRBC_WR_LO_ERR_MASK 0x00002000L
-#define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_WR_HI_ERR_MASK 0x00004000L
-#define JPEG_MEMCHECK_SYS_INT_ACK__EJRBC_WR_LO_ERR_MASK 0x00008000L
-#define JPEG_MEMCHECK_SYS_INT_ACK__BS_WR_HI_ERR_MASK 0x00010000L
-#define JPEG_MEMCHECK_SYS_INT_ACK__BS_WR_LO_ERR_MASK 0x00020000L
-#define JPEG_MEMCHECK_SYS_INT_ACK__OBUF_WR_HI_ERR_MASK 0x00040000L
-#define JPEG_MEMCHECK_SYS_INT_ACK__OBUF_WR_LO_ERR_MASK 0x00080000L
-#define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_WR_HI_ERR_MASK 0x00100000L
-#define JPEG_MEMCHECK_SYS_INT_ACK__SCALAR_WR_LO_ERR_MASK 0x00200000L
-#define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_WR_HI_ERR_MASK 0x00400000L
-#define JPEG_MEMCHECK_SYS_INT_ACK__JPEG2_WR_LO_ERR_MASK 0x00800000L
-//JPEG_MASTINT_EN
-#define JPEG_MASTINT_EN__OVERRUN_RST__SHIFT 0x0
-#define JPEG_MASTINT_EN__INT_OVERRUN__SHIFT 0x4
-#define JPEG_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L
-#define JPEG_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L
-//JPEG_IH_CTRL
-#define JPEG_IH_CTRL__IH_SOFT_RESET__SHIFT 0x0
-#define JPEG_IH_CTRL__IH_STALL_EN__SHIFT 0x1
-#define JPEG_IH_CTRL__IH_STATUS_CLEAN__SHIFT 0x2
-#define JPEG_IH_CTRL__IH_VMID__SHIFT 0x3
-#define JPEG_IH_CTRL__IH_USER_DATA__SHIFT 0x7
-#define JPEG_IH_CTRL__IH_RINGID__SHIFT 0x13
-#define JPEG_IH_CTRL__IH_SOFT_RESET_MASK 0x00000001L
-#define JPEG_IH_CTRL__IH_STALL_EN_MASK 0x00000002L
-#define JPEG_IH_CTRL__IH_STATUS_CLEAN_MASK 0x00000004L
-#define JPEG_IH_CTRL__IH_VMID_MASK 0x00000078L
-#define JPEG_IH_CTRL__IH_USER_DATA_MASK 0x0007FF80L
-#define JPEG_IH_CTRL__IH_RINGID_MASK 0x07F80000L
-//JRBBM_ARB_CTRL
-#define JRBBM_ARB_CTRL__DJRBC_DROP__SHIFT 0x0
-#define JRBBM_ARB_CTRL__EJRBC_DROP__SHIFT 0x1
-#define JRBBM_ARB_CTRL__SRBM_DROP__SHIFT 0x2
-#define JRBBM_ARB_CTRL__DJRBC_DROP_MASK 0x00000001L
-#define JRBBM_ARB_CTRL__EJRBC_DROP_MASK 0x00000002L
-#define JRBBM_ARB_CTRL__SRBM_DROP_MASK 0x00000004L
-
-
-// addressBlock: uvd0_uvd_jpeg_common_sclk_dec
-//JPEG_CGC_GATE
-#define JPEG_CGC_GATE__JPEG_DEC__SHIFT 0x0
-#define JPEG_CGC_GATE__JPEG2_DEC__SHIFT 0x1
-#define JPEG_CGC_GATE__JPEG_ENC__SHIFT 0x2
-#define JPEG_CGC_GATE__JMCIF__SHIFT 0x3
-#define JPEG_CGC_GATE__JRBBM__SHIFT 0x4
-#define JPEG_CGC_GATE__JPEG_DEC_MASK 0x00000001L
-#define JPEG_CGC_GATE__JPEG2_DEC_MASK 0x00000002L
-#define JPEG_CGC_GATE__JPEG_ENC_MASK 0x00000004L
-#define JPEG_CGC_GATE__JMCIF_MASK 0x00000008L
-#define JPEG_CGC_GATE__JRBBM_MASK 0x00000010L
-//JPEG_CGC_CTRL
-#define JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0
-#define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x1
-#define JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x5
-#define JPEG_CGC_CTRL__DYN_OCLK_RAMP_EN__SHIFT 0xa
-#define JPEG_CGC_CTRL__DYN_RCLK_RAMP_EN__SHIFT 0xb
-#define JPEG_CGC_CTRL__GATER_DIV_ID__SHIFT 0xc
-#define JPEG_CGC_CTRL__JPEG_DEC_MODE__SHIFT 0x10
-#define JPEG_CGC_CTRL__JPEG2_DEC_MODE__SHIFT 0x11
-#define JPEG_CGC_CTRL__JPEG_ENC_MODE__SHIFT 0x12
-#define JPEG_CGC_CTRL__JMCIF_MODE__SHIFT 0x13
-#define JPEG_CGC_CTRL__JRBBM_MODE__SHIFT 0x14
-#define JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L
-#define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000001EL
-#define JPEG_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000003E0L
-#define JPEG_CGC_CTRL__DYN_OCLK_RAMP_EN_MASK 0x00000400L
-#define JPEG_CGC_CTRL__DYN_RCLK_RAMP_EN_MASK 0x00000800L
-#define JPEG_CGC_CTRL__GATER_DIV_ID_MASK 0x00007000L
-#define JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK 0x00010000L
-#define JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK 0x00020000L
-#define JPEG_CGC_CTRL__JPEG_ENC_MODE_MASK 0x00040000L
-#define JPEG_CGC_CTRL__JMCIF_MODE_MASK 0x00080000L
-#define JPEG_CGC_CTRL__JRBBM_MODE_MASK 0x00100000L
-//JPEG_CGC_STATUS
-#define JPEG_CGC_STATUS__JPEG_DEC_VCLK_ACTIVE__SHIFT 0x0
-#define JPEG_CGC_STATUS__JPEG_DEC_SCLK_ACTIVE__SHIFT 0x1
-#define JPEG_CGC_STATUS__JPEG2_DEC_VCLK_ACTIVE__SHIFT 0x2
-#define JPEG_CGC_STATUS__JPEG2_DEC_SCLK_ACTIVE__SHIFT 0x3
-#define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE__SHIFT 0x4
-#define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE__SHIFT 0x5
-#define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE__SHIFT 0x6
-#define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE__SHIFT 0x7
-#define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE__SHIFT 0x8
-#define JPEG_CGC_STATUS__JPEG_DEC_VCLK_ACTIVE_MASK 0x00000001L
-#define JPEG_CGC_STATUS__JPEG_DEC_SCLK_ACTIVE_MASK 0x00000002L
-#define JPEG_CGC_STATUS__JPEG2_DEC_VCLK_ACTIVE_MASK 0x00000004L
-#define JPEG_CGC_STATUS__JPEG2_DEC_SCLK_ACTIVE_MASK 0x00000008L
-#define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE_MASK 0x00000010L
-#define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE_MASK 0x00000020L
-#define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE_MASK 0x00000040L
-#define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE_MASK 0x00000080L
-#define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE_MASK 0x00000100L
-//JPEG_COMN_CGC_MEM_CTRL
-#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN__SHIFT 0x0
-#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN__SHIFT 0x1
-#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN__SHIFT 0x2
-#define JPEG_COMN_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10
-#define JPEG_COMN_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14
-#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN_MASK 0x00000001L
-#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN_MASK 0x00000002L
-#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN_MASK 0x00000004L
-#define JPEG_COMN_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0x000F0000L
-#define JPEG_COMN_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0x00F00000L
-//JPEG_DEC_CGC_MEM_CTRL
-#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_LS_EN__SHIFT 0x0
-#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_DS_EN__SHIFT 0x1
-#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_SD_EN__SHIFT 0x2
-#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_LS_EN_MASK 0x00000001L
-#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_DS_EN_MASK 0x00000002L
-#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_SD_EN_MASK 0x00000004L
-//JPEG2_DEC_CGC_MEM_CTRL
-#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_EN__SHIFT 0x0
-#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_DS_EN__SHIFT 0x1
-#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_SD_EN__SHIFT 0x2
-#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_EN_MASK 0x00000001L
-#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_DS_EN_MASK 0x00000002L
-#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_SD_EN_MASK 0x00000004L
-//JPEG_ENC_CGC_MEM_CTRL
-#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN__SHIFT 0x0
-#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN__SHIFT 0x1
-#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN__SHIFT 0x2
-#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN_MASK 0x00000001L
-#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN_MASK 0x00000002L
-#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN_MASK 0x00000004L
-//JPEG_SOFT_RESET2
-#define JPEG_SOFT_RESET2__ATOMIC_SOFT_RESET__SHIFT 0x0
-#define JPEG_SOFT_RESET2__ATOMIC_SOFT_RESET_MASK 0x00000001L
-//JPEG_PERF_BANK_CONF
-#define JPEG_PERF_BANK_CONF__RESET__SHIFT 0x0
-#define JPEG_PERF_BANK_CONF__PEEK__SHIFT 0x8
-#define JPEG_PERF_BANK_CONF__CONCATENATE__SHIFT 0x10
-#define JPEG_PERF_BANK_CONF__RESET_MASK 0x0000000FL
-#define JPEG_PERF_BANK_CONF__PEEK_MASK 0x00000F00L
-#define JPEG_PERF_BANK_CONF__CONCATENATE_MASK 0x00030000L
-//JPEG_PERF_BANK_EVENT_SEL
-#define JPEG_PERF_BANK_EVENT_SEL__SEL0__SHIFT 0x0
-#define JPEG_PERF_BANK_EVENT_SEL__SEL1__SHIFT 0x8
-#define JPEG_PERF_BANK_EVENT_SEL__SEL2__SHIFT 0x10
-#define JPEG_PERF_BANK_EVENT_SEL__SEL3__SHIFT 0x18
-#define JPEG_PERF_BANK_EVENT_SEL__SEL0_MASK 0x000000FFL
-#define JPEG_PERF_BANK_EVENT_SEL__SEL1_MASK 0x0000FF00L
-#define JPEG_PERF_BANK_EVENT_SEL__SEL2_MASK 0x00FF0000L
-#define JPEG_PERF_BANK_EVENT_SEL__SEL3_MASK 0xFF000000L
-//JPEG_PERF_BANK_COUNT0
-#define JPEG_PERF_BANK_COUNT0__COUNT__SHIFT 0x0
-#define JPEG_PERF_BANK_COUNT0__COUNT_MASK 0xFFFFFFFFL
-//JPEG_PERF_BANK_COUNT1
-#define JPEG_PERF_BANK_COUNT1__COUNT__SHIFT 0x0
-#define JPEG_PERF_BANK_COUNT1__COUNT_MASK 0xFFFFFFFFL
-//JPEG_PERF_BANK_COUNT2
-#define JPEG_PERF_BANK_COUNT2__COUNT__SHIFT 0x0
-#define JPEG_PERF_BANK_COUNT2__COUNT_MASK 0xFFFFFFFFL
-//JPEG_PERF_BANK_COUNT3
-#define JPEG_PERF_BANK_COUNT3__COUNT__SHIFT 0x0
-#define JPEG_PERF_BANK_COUNT3__COUNT_MASK 0xFFFFFFFFL
-
-
-// addressBlock: uvd0_uvd_jpeg_enc_dec
-//UVD_JPEG_ENC_INT_EN
-#define UVD_JPEG_ENC_INT_EN__HUFF_JOB_DONE_INT_EN__SHIFT 0x0
-#define UVD_JPEG_ENC_INT_EN__SCLR_JOB_DONE_INT_EN__SHIFT 0x1
-#define UVD_JPEG_ENC_INT_EN__HUFF_ERROR_INT_EN__SHIFT 0x2
-#define UVD_JPEG_ENC_INT_EN__SCLR_ERROR_INT_EN__SHIFT 0x3
-#define UVD_JPEG_ENC_INT_EN__QTBL_ERROR_INT_EN__SHIFT 0x4
-#define UVD_JPEG_ENC_INT_EN__PIC_SIZE_ERROR_INT_EN__SHIFT 0x5
-#define UVD_JPEG_ENC_INT_EN__FENCE_VAL_INT_EN__SHIFT 0x6
-#define UVD_JPEG_ENC_INT_EN__HUFF_JOB_DONE_INT_EN_MASK 0x00000001L
-#define UVD_JPEG_ENC_INT_EN__SCLR_JOB_DONE_INT_EN_MASK 0x00000002L
-#define UVD_JPEG_ENC_INT_EN__HUFF_ERROR_INT_EN_MASK 0x00000004L
-#define UVD_JPEG_ENC_INT_EN__SCLR_ERROR_INT_EN_MASK 0x00000008L
-#define UVD_JPEG_ENC_INT_EN__QTBL_ERROR_INT_EN_MASK 0x00000010L
-#define UVD_JPEG_ENC_INT_EN__PIC_SIZE_ERROR_INT_EN_MASK 0x00000020L
-#define UVD_JPEG_ENC_INT_EN__FENCE_VAL_INT_EN_MASK 0x00000040L
-//UVD_JPEG_ENC_INT_STATUS
-#define UVD_JPEG_ENC_INT_STATUS__HUFF_JOB_DONE_STATUS__SHIFT 0x0
-#define UVD_JPEG_ENC_INT_STATUS__SCLR_JOB_DONE_STATUS__SHIFT 0x1
-#define UVD_JPEG_ENC_INT_STATUS__HUFF_ERROR_STATUS__SHIFT 0x2
-#define UVD_JPEG_ENC_INT_STATUS__SCLR_ERROR_STATUS__SHIFT 0x3
-#define UVD_JPEG_ENC_INT_STATUS__QTBL_ERROR_STATUS__SHIFT 0x4
-#define UVD_JPEG_ENC_INT_STATUS__PIC_SIZE_ERROR_STATUS__SHIFT 0x5
-#define UVD_JPEG_ENC_INT_STATUS__FENCE_VAL_STATUS__SHIFT 0x6
-#define UVD_JPEG_ENC_INT_STATUS__HUFF_JOB_DONE_STATUS_MASK 0x00000001L
-#define UVD_JPEG_ENC_INT_STATUS__SCLR_JOB_DONE_STATUS_MASK 0x00000002L
-#define UVD_JPEG_ENC_INT_STATUS__HUFF_ERROR_STATUS_MASK 0x00000004L
-#define UVD_JPEG_ENC_INT_STATUS__SCLR_ERROR_STATUS_MASK 0x00000008L
-#define UVD_JPEG_ENC_INT_STATUS__QTBL_ERROR_STATUS_MASK 0x00000010L
-#define UVD_JPEG_ENC_INT_STATUS__PIC_SIZE_ERROR_STATUS_MASK 0x00000020L
-#define UVD_JPEG_ENC_INT_STATUS__FENCE_VAL_STATUS_MASK 0x00000040L
-//UVD_JPEG_ENC_ENGINE_CNTL
-#define UVD_JPEG_ENC_ENGINE_CNTL__HUFF_WR_COMB_DIS__SHIFT 0x0
-#define UVD_JPEG_ENC_ENGINE_CNTL__DISTINCT_CHROMA_QUANT_TABLES__SHIFT 0x1
-#define UVD_JPEG_ENC_ENGINE_CNTL__SCALAR_EN__SHIFT 0x2
-#define UVD_JPEG_ENC_ENGINE_CNTL__ENCODE_EN__SHIFT 0x3
-#define UVD_JPEG_ENC_ENGINE_CNTL__CMP_NEEDED__SHIFT 0x4
-#define UVD_JPEG_ENC_ENGINE_CNTL__ECS_RESTRICT_32B_EN__SHIFT 0x9
-#define UVD_JPEG_ENC_ENGINE_CNTL__HUFF_WR_COMB_DIS_MASK 0x00000001L
-#define UVD_JPEG_ENC_ENGINE_CNTL__DISTINCT_CHROMA_QUANT_TABLES_MASK 0x00000002L
-#define UVD_JPEG_ENC_ENGINE_CNTL__SCALAR_EN_MASK 0x00000004L
-#define UVD_JPEG_ENC_ENGINE_CNTL__ENCODE_EN_MASK 0x00000008L
-#define UVD_JPEG_ENC_ENGINE_CNTL__CMP_NEEDED_MASK 0x00000010L
-#define UVD_JPEG_ENC_ENGINE_CNTL__ECS_RESTRICT_32B_EN_MASK 0x00000200L
-//UVD_JPEG_ENC_SCRATCH1
-#define UVD_JPEG_ENC_SCRATCH1__SCRATCH1__SHIFT 0x0
-#define UVD_JPEG_ENC_SCRATCH1__SCRATCH1_MASK 0xFFFFFFFFL
-
-
-// addressBlock: uvd0_uvd_jpeg_enc_sclk_dec
-//UVD_JPEG_ENC_SPS_INFO
-#define UVD_JPEG_ENC_SPS_INFO__SRC_FORMAT__SHIFT 0x0
-#define UVD_JPEG_ENC_SPS_INFO__YUY2_SUBFORMAT__SHIFT 0x3
-#define UVD_JPEG_ENC_SPS_INFO__OUT_FMT_422__SHIFT 0x4
-#define UVD_JPEG_ENC_SPS_INFO__SRC_FORMAT_MASK 0x00000007L
-#define UVD_JPEG_ENC_SPS_INFO__YUY2_SUBFORMAT_MASK 0x00000008L
-#define UVD_JPEG_ENC_SPS_INFO__OUT_FMT_422_MASK 0x00000010L
-//UVD_JPEG_ENC_SPS_INFO1
-#define UVD_JPEG_ENC_SPS_INFO1__SRC_WIDTH__SHIFT 0x0
-#define UVD_JPEG_ENC_SPS_INFO1__SRC_HEIGHT__SHIFT 0x10
-#define UVD_JPEG_ENC_SPS_INFO1__SRC_WIDTH_MASK 0x0000FFFFL
-#define UVD_JPEG_ENC_SPS_INFO1__SRC_HEIGHT_MASK 0xFFFF0000L
-//UVD_JPEG_ENC_TBL_SIZE
-#define UVD_JPEG_ENC_TBL_SIZE__TBL_SIZE__SHIFT 0x6
-#define UVD_JPEG_ENC_TBL_SIZE__TBL_SIZE_MASK 0x00000FC0L
-//UVD_JPEG_ENC_TBL_CNTL
-#define UVD_JPEG_ENC_TBL_CNTL__TBL_PEL_SEL__SHIFT 0x0
-#define UVD_JPEG_ENC_TBL_CNTL__TBL_TYPE__SHIFT 0x1
-#define UVD_JPEG_ENC_TBL_CNTL__TBL_SUBTYPE__SHIFT 0x2
-#define UVD_JPEG_ENC_TBL_CNTL__HTBL_CNTLEN__SHIFT 0x4
-#define UVD_JPEG_ENC_TBL_CNTL__TBL_PEL_SEL_MASK 0x00000001L
-#define UVD_JPEG_ENC_TBL_CNTL__TBL_TYPE_MASK 0x00000002L
-#define UVD_JPEG_ENC_TBL_CNTL__TBL_SUBTYPE_MASK 0x0000000CL
-#define UVD_JPEG_ENC_TBL_CNTL__HTBL_CNTLEN_MASK 0x00000010L
-//UVD_JPEG_ENC_MC_REQ_CNTL
-#define UVD_JPEG_ENC_MC_REQ_CNTL__RD_REQ_PRIORITY_MARK__SHIFT 0x0
-#define UVD_JPEG_ENC_MC_REQ_CNTL__RD_REQ_PRIORITY_MARK_MASK 0x0000003FL
-//UVD_JPEG_ENC_STATUS
-#define UVD_JPEG_ENC_STATUS__PEL_FETCH_IDLE__SHIFT 0x0
-#define UVD_JPEG_ENC_STATUS__HUFF_CORE_IDLE__SHIFT 0x1
-#define UVD_JPEG_ENC_STATUS__FDCT_IDLE__SHIFT 0x2
-#define UVD_JPEG_ENC_STATUS__SCALAR_IDLE__SHIFT 0x3
-#define UVD_JPEG_ENC_STATUS__PEL_FETCH_IDLE_MASK 0x00000001L
-#define UVD_JPEG_ENC_STATUS__HUFF_CORE_IDLE_MASK 0x00000002L
-#define UVD_JPEG_ENC_STATUS__FDCT_IDLE_MASK 0x00000004L
-#define UVD_JPEG_ENC_STATUS__SCALAR_IDLE_MASK 0x00000008L
-//UVD_JPEG_ENC_PITCH
-#define UVD_JPEG_ENC_PITCH__PITCH_Y__SHIFT 0x0
-#define UVD_JPEG_ENC_PITCH__PITCH_UV__SHIFT 0x10
-#define UVD_JPEG_ENC_PITCH__PITCH_Y_MASK 0x00000FFFL
-#define UVD_JPEG_ENC_PITCH__PITCH_UV_MASK 0x0FFF0000L
-//UVD_JPEG_ENC_LUMA_BASE
-#define UVD_JPEG_ENC_LUMA_BASE__LUMA_BASE__SHIFT 0x0
-#define UVD_JPEG_ENC_LUMA_BASE__LUMA_BASE_MASK 0xFFFFFFFFL
-//UVD_JPEG_ENC_CHROMAU_BASE
-#define UVD_JPEG_ENC_CHROMAU_BASE__CHROMAU_BASE__SHIFT 0x0
-#define UVD_JPEG_ENC_CHROMAU_BASE__CHROMAU_BASE_MASK 0xFFFFFFFFL
-//UVD_JPEG_ENC_CHROMAV_BASE
-#define UVD_JPEG_ENC_CHROMAV_BASE__CHROMAV_BASE__SHIFT 0x0
-#define UVD_JPEG_ENC_CHROMAV_BASE__CHROMAV_BASE_MASK 0xFFFFFFFFL
-//JPEG_ENC_Y_GFX10_TILING_SURFACE
-#define JPEG_ENC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0
-#define JPEG_ENC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL
-//JPEG_ENC_UV_GFX10_TILING_SURFACE
-#define JPEG_ENC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0
-#define JPEG_ENC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL
-//JPEG_ENC_GFX10_ADDR_CONFIG
-#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
-#define JPEG_ENC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
-#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
-#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
-#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
-#define JPEG_ENC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
-#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
-#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
-//JPEG_ENC_ADDR_MODE
-#define JPEG_ENC_ADDR_MODE__ADDR_MODE_Y__SHIFT 0x0
-#define JPEG_ENC_ADDR_MODE__ADDR_MODE_UV__SHIFT 0x2
-#define JPEG_ENC_ADDR_MODE__ADDR_LIB_SEL__SHIFT 0xc
-#define JPEG_ENC_ADDR_MODE__ADDR_MODE_Y_MASK 0x00000003L
-#define JPEG_ENC_ADDR_MODE__ADDR_MODE_UV_MASK 0x0000000CL
-#define JPEG_ENC_ADDR_MODE__ADDR_LIB_SEL_MASK 0x00007000L
-//UVD_JPEG_ENC_GPCOM_CMD
-#define UVD_JPEG_ENC_GPCOM_CMD__CMD__SHIFT 0x1
-#define UVD_JPEG_ENC_GPCOM_CMD__CMD_MASK 0x0000000EL
-//UVD_JPEG_ENC_GPCOM_DATA0
-#define UVD_JPEG_ENC_GPCOM_DATA0__DATA0__SHIFT 0x0
-#define UVD_JPEG_ENC_GPCOM_DATA0__DATA0_MASK 0xFFFFFFFFL
-//UVD_JPEG_ENC_GPCOM_DATA1
-#define UVD_JPEG_ENC_GPCOM_DATA1__DATA1__SHIFT 0x0
-#define UVD_JPEG_ENC_GPCOM_DATA1__DATA1_MASK 0xFFFFFFFFL
-//UVD_JPEG_TBL_DAT0
-#define UVD_JPEG_TBL_DAT0__TBL_DAT_31_0__SHIFT 0x0
-#define UVD_JPEG_TBL_DAT0__TBL_DAT_31_0_MASK 0xFFFFFFFFL
-//UVD_JPEG_TBL_DAT1
-#define UVD_JPEG_TBL_DAT1__TBL_DAT_63_32__SHIFT 0x0
-#define UVD_JPEG_TBL_DAT1__TBL_DAT_63_32_MASK 0xFFFFFFFFL
-//UVD_JPEG_TBL_IDX
-#define UVD_JPEG_TBL_IDX__TBL_IDX__SHIFT 0x0
-#define UVD_JPEG_TBL_IDX__TBL_IDX_MASK 0x000000FFL
-//UVD_JPEG_ENC_CGC_CNTL
-#define UVD_JPEG_ENC_CGC_CNTL__CGC_EN__SHIFT 0x0
-#define UVD_JPEG_ENC_CGC_CNTL__CGC_EN_MASK 0x00000001L
-//UVD_JPEG_ENC_SCRATCH0
-#define UVD_JPEG_ENC_SCRATCH0__SCRATCH0__SHIFT 0x0
-#define UVD_JPEG_ENC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL
-//UVD_JPEG_ENC_SOFT_RST
-#define UVD_JPEG_ENC_SOFT_RST__SOFT_RST__SHIFT 0x0
-#define UVD_JPEG_ENC_SOFT_RST__RESET_STATUS__SHIFT 0x10
-#define UVD_JPEG_ENC_SOFT_RST__SOFT_RST_MASK 0x00000001L
-#define UVD_JPEG_ENC_SOFT_RST__RESET_STATUS_MASK 0x00010000L
-
-
-// addressBlock: uvd0_uvd_jrbc_dec
-//UVD_JRBC_RB_WPTR
-#define UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT 0x4
-#define UVD_JRBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L
-//UVD_JRBC_RB_CNTL
-#define UVD_JRBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0
-#define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1
-#define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4
-#define UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L
-#define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L
-#define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L
-//UVD_JRBC_IB_SIZE
-#define UVD_JRBC_IB_SIZE__IB_SIZE__SHIFT 0x4
-#define UVD_JRBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L
-//UVD_JRBC_URGENT_CNTL
-#define UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0
-#define UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L
-//UVD_JRBC_RB_REF_DATA
-#define UVD_JRBC_RB_REF_DATA__REF_DATA__SHIFT 0x0
-#define UVD_JRBC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL
-//UVD_JRBC_RB_COND_RD_TIMER
-#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0
-#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10
-#define UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18
-#define UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19
-#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL
-#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L
-#define UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L
-#define UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L
-//UVD_JRBC_SOFT_RESET
-#define UVD_JRBC_SOFT_RESET__RESET__SHIFT 0x0
-#define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11
-#define UVD_JRBC_SOFT_RESET__RESET_MASK 0x00000001L
-#define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L
-//UVD_JRBC_STATUS
-#define UVD_JRBC_STATUS__RB_JOB_DONE__SHIFT 0x0
-#define UVD_JRBC_STATUS__IB_JOB_DONE__SHIFT 0x1
-#define UVD_JRBC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2
-#define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3
-#define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4
-#define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5
-#define UVD_JRBC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6
-#define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7
-#define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8
-#define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9
-#define UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa
-#define UVD_JRBC_STATUS__PREEMPT_STATUS__SHIFT 0xb
-#define UVD_JRBC_STATUS__IB_TRAP_STATUS__SHIFT 0xc
-#define UVD_JRBC_STATUS__INT_EN__SHIFT 0x10
-#define UVD_JRBC_STATUS__INT_ACK__SHIFT 0x11
-#define UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L
-#define UVD_JRBC_STATUS__IB_JOB_DONE_MASK 0x00000002L
-#define UVD_JRBC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L
-#define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L
-#define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L
-#define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L
-#define UVD_JRBC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L
-#define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L
-#define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L
-#define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L
-#define UVD_JRBC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L
-#define UVD_JRBC_STATUS__PREEMPT_STATUS_MASK 0x00000800L
-#define UVD_JRBC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L
-#define UVD_JRBC_STATUS__INT_EN_MASK 0x00010000L
-#define UVD_JRBC_STATUS__INT_ACK_MASK 0x00020000L
-//UVD_JRBC_RB_RPTR
-#define UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT 0x4
-#define UVD_JRBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L
-//UVD_JRBC_RB_BUF_STATUS
-#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0
-#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10
-#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18
-#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL
-#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L
-#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L
-//UVD_JRBC_IB_BUF_STATUS
-#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0
-#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10
-#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18
-#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL
-#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L
-#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L
-//UVD_JRBC_IB_SIZE_UPDATE
-#define UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4
-#define UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L
-//UVD_JRBC_IB_COND_RD_TIMER
-#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0
-#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10
-#define UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18
-#define UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19
-#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL
-#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L
-#define UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L
-#define UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L
-//UVD_JRBC_IB_REF_DATA
-#define UVD_JRBC_IB_REF_DATA__REF_DATA__SHIFT 0x0
-#define UVD_JRBC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL
-//UVD_JPEG_PREEMPT_CMD
-#define UVD_JPEG_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0
-#define UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1
-#define UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2
-#define UVD_JPEG_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L
-#define UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L
-#define UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L
-//UVD_JPEG_PREEMPT_FENCE_DATA0
-#define UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0
-#define UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL
-//UVD_JPEG_PREEMPT_FENCE_DATA1
-#define UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0
-#define UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL
-//UVD_JRBC_RB_SIZE
-#define UVD_JRBC_RB_SIZE__RB_SIZE__SHIFT 0x4
-#define UVD_JRBC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L
-//UVD_JRBC_SCRATCH0
-#define UVD_JRBC_SCRATCH0__SCRATCH0__SHIFT 0x0
-#define UVD_JRBC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL
-
-
-// addressBlock: uvd0_uvd_jrbc_enc_dec
-//UVD_JRBC_ENC_RB_WPTR
-#define UVD_JRBC_ENC_RB_WPTR__RB_WPTR__SHIFT 0x4
-#define UVD_JRBC_ENC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L
-//UVD_JRBC_ENC_RB_CNTL
-#define UVD_JRBC_ENC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0
-#define UVD_JRBC_ENC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1
-#define UVD_JRBC_ENC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4
-#define UVD_JRBC_ENC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L
-#define UVD_JRBC_ENC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L
-#define UVD_JRBC_ENC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L
-//UVD_JRBC_ENC_IB_SIZE
-#define UVD_JRBC_ENC_IB_SIZE__IB_SIZE__SHIFT 0x4
-#define UVD_JRBC_ENC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L
-//UVD_JRBC_ENC_URGENT_CNTL
-#define UVD_JRBC_ENC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0
-#define UVD_JRBC_ENC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L
-//UVD_JRBC_ENC_RB_REF_DATA
-#define UVD_JRBC_ENC_RB_REF_DATA__REF_DATA__SHIFT 0x0
-#define UVD_JRBC_ENC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL
-//UVD_JRBC_ENC_RB_COND_RD_TIMER
-#define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0
-#define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10
-#define UVD_JRBC_ENC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18
-#define UVD_JRBC_ENC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19
-#define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL
-#define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L
-#define UVD_JRBC_ENC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L
-#define UVD_JRBC_ENC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L
-//UVD_JRBC_ENC_SOFT_RESET
-#define UVD_JRBC_ENC_SOFT_RESET__RESET__SHIFT 0x0
-#define UVD_JRBC_ENC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11
-#define UVD_JRBC_ENC_SOFT_RESET__RESET_MASK 0x00000001L
-#define UVD_JRBC_ENC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L
-//UVD_JRBC_ENC_STATUS
-#define UVD_JRBC_ENC_STATUS__RB_JOB_DONE__SHIFT 0x0
-#define UVD_JRBC_ENC_STATUS__IB_JOB_DONE__SHIFT 0x1
-#define UVD_JRBC_ENC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2
-#define UVD_JRBC_ENC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3
-#define UVD_JRBC_ENC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4
-#define UVD_JRBC_ENC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5
-#define UVD_JRBC_ENC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6
-#define UVD_JRBC_ENC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7
-#define UVD_JRBC_ENC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8
-#define UVD_JRBC_ENC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9
-#define UVD_JRBC_ENC_STATUS__RB_TRAP_STATUS__SHIFT 0xa
-#define UVD_JRBC_ENC_STATUS__PREEMPT_STATUS__SHIFT 0xb
-#define UVD_JRBC_ENC_STATUS__IB_TRAP_STATUS__SHIFT 0xc
-#define UVD_JRBC_ENC_STATUS__INT_EN__SHIFT 0x10
-#define UVD_JRBC_ENC_STATUS__INT_ACK__SHIFT 0x11
-#define UVD_JRBC_ENC_STATUS__RB_JOB_DONE_MASK 0x00000001L
-#define UVD_JRBC_ENC_STATUS__IB_JOB_DONE_MASK 0x00000002L
-#define UVD_JRBC_ENC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L
-#define UVD_JRBC_ENC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L
-#define UVD_JRBC_ENC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L
-#define UVD_JRBC_ENC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L
-#define UVD_JRBC_ENC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L
-#define UVD_JRBC_ENC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L
-#define UVD_JRBC_ENC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L
-#define UVD_JRBC_ENC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L
-#define UVD_JRBC_ENC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L
-#define UVD_JRBC_ENC_STATUS__PREEMPT_STATUS_MASK 0x00000800L
-#define UVD_JRBC_ENC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L
-#define UVD_JRBC_ENC_STATUS__INT_EN_MASK 0x00010000L
-#define UVD_JRBC_ENC_STATUS__INT_ACK_MASK 0x00020000L
-//UVD_JRBC_ENC_RB_RPTR
-#define UVD_JRBC_ENC_RB_RPTR__RB_RPTR__SHIFT 0x4
-#define UVD_JRBC_ENC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L
-//UVD_JRBC_ENC_RB_BUF_STATUS
-#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0
-#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10
-#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18
-#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL
-#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L
-#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L
-//UVD_JRBC_ENC_IB_BUF_STATUS
-#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0
-#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10
-#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18
-#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL
-#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L
-#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L
-//UVD_JRBC_ENC_IB_SIZE_UPDATE
-#define UVD_JRBC_ENC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4
-#define UVD_JRBC_ENC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L
-//UVD_JRBC_ENC_IB_COND_RD_TIMER
-#define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0
-#define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10
-#define UVD_JRBC_ENC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18
-#define UVD_JRBC_ENC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19
-#define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL
-#define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L
-#define UVD_JRBC_ENC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L
-#define UVD_JRBC_ENC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L
-//UVD_JRBC_ENC_IB_REF_DATA
-#define UVD_JRBC_ENC_IB_REF_DATA__REF_DATA__SHIFT 0x0
-#define UVD_JRBC_ENC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL
-//UVD_JPEG_ENC_PREEMPT_CMD
-#define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0
-#define UVD_JPEG_ENC_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1
-#define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2
-#define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L
-#define UVD_JPEG_ENC_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L
-#define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L
-//UVD_JPEG_ENC_PREEMPT_FENCE_DATA0
-#define UVD_JPEG_ENC_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0
-#define UVD_JPEG_ENC_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL
-//UVD_JPEG_ENC_PREEMPT_FENCE_DATA1
-#define UVD_JPEG_ENC_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0
-#define UVD_JPEG_ENC_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL
-//UVD_JRBC_ENC_RB_SIZE
-#define UVD_JRBC_ENC_RB_SIZE__RB_SIZE__SHIFT 0x4
-#define UVD_JRBC_ENC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L
-//UVD_JRBC_ENC_SCRATCH0
-#define UVD_JRBC_ENC_SCRATCH0__SCRATCH0__SHIFT 0x0
-#define UVD_JRBC_ENC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL
-
-
-// addressBlock: uvd0_uvd_mpcdec
-//UVD_MP_SWAP_CNTL
-#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0
-#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2
-#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4
-#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6
-#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8
-#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa
-#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc
-#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe
-#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10
-#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12
-#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14
-#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16
-#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18
-#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a
-#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c
-#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e
-#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x00000003L
-#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0x0000000CL
-#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x00000030L
-#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0x000000C0L
-#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x00000300L
-#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0x00000C00L
-#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x00003000L
-#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0x0000C000L
-#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x00030000L
-#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0x000C0000L
-#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x00300000L
-#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0x00C00000L
-#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x03000000L
-#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0x0C000000L
-#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000L
-#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xC0000000L
-//UVD_MP_SWAP_CNTL2
-#define UVD_MP_SWAP_CNTL2__MP_REF16_MC_SWAP__SHIFT 0x0
-#define UVD_MP_SWAP_CNTL2__MP_REF16_MC_SWAP_MASK 0x00000003L
-//UVD_MPC_LUMA_SRCH
-#define UVD_MPC_LUMA_SRCH__CNTR__SHIFT 0x0
-#define UVD_MPC_LUMA_SRCH__CNTR_MASK 0xFFFFFFFFL
-//UVD_MPC_LUMA_HIT
-#define UVD_MPC_LUMA_HIT__CNTR__SHIFT 0x0
-#define UVD_MPC_LUMA_HIT__CNTR_MASK 0xFFFFFFFFL
-//UVD_MPC_LUMA_HITPEND
-#define UVD_MPC_LUMA_HITPEND__CNTR__SHIFT 0x0
-#define UVD_MPC_LUMA_HITPEND__CNTR_MASK 0xFFFFFFFFL
-//UVD_MPC_CHROMA_SRCH
-#define UVD_MPC_CHROMA_SRCH__CNTR__SHIFT 0x0
-#define UVD_MPC_CHROMA_SRCH__CNTR_MASK 0xFFFFFFFFL
-//UVD_MPC_CHROMA_HIT
-#define UVD_MPC_CHROMA_HIT__CNTR__SHIFT 0x0
-#define UVD_MPC_CHROMA_HIT__CNTR_MASK 0xFFFFFFFFL
-//UVD_MPC_CHROMA_HITPEND
-#define UVD_MPC_CHROMA_HITPEND__CNTR__SHIFT 0x0
-#define UVD_MPC_CHROMA_HITPEND__CNTR_MASK 0xFFFFFFFFL
-//UVD_MPC_CNTL
-#define UVD_MPC_CNTL__BLK_RST__SHIFT 0x0
-#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3
-#define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6
-#define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10
-#define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12
-#define UVD_MPC_CNTL__SMPAT_REQ_SPEED_UP__SHIFT 0x13
-#define UVD_MPC_CNTL__TEST_MODE_EN__SHIFT 0x14
-#define UVD_MPC_CNTL__BLK_RST_MASK 0x00000001L
-#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L
-#define UVD_MPC_CNTL__PERF_RST_MASK 0x00000040L
-#define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x00030000L
-#define UVD_MPC_CNTL__URGENT_EN_MASK 0x00040000L
-#define UVD_MPC_CNTL__SMPAT_REQ_SPEED_UP_MASK 0x00080000L
-#define UVD_MPC_CNTL__TEST_MODE_EN_MASK 0x00100000L
-//UVD_MPC_PITCH
-#define UVD_MPC_PITCH__LUMA_PITCH__SHIFT 0x0
-#define UVD_MPC_PITCH__LUMA_PITCH_MASK 0x000007FFL
-//UVD_MPC_SET_MUXA0
-#define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0
-#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6
-#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc
-#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12
-#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18
-#define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x0000003FL
-#define UVD_MPC_SET_MUXA0__VARA_1_MASK 0x00000FC0L
-#define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x0003F000L
-#define UVD_MPC_SET_MUXA0__VARA_3_MASK 0x00FC0000L
-#define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3F000000L
-//UVD_MPC_SET_MUXA1
-#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0
-#define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6
-#define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc
-#define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x0000003FL
-#define UVD_MPC_SET_MUXA1__VARA_6_MASK 0x00000FC0L
-#define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x0003F000L
-//UVD_MPC_SET_MUXB0
-#define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0
-#define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6
-#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc
-#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12
-#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18
-#define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x0000003FL
-#define UVD_MPC_SET_MUXB0__VARB_1_MASK 0x00000FC0L
-#define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x0003F000L
-#define UVD_MPC_SET_MUXB0__VARB_3_MASK 0x00FC0000L
-#define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3F000000L
-//UVD_MPC_SET_MUXB1
-#define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0
-#define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6
-#define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc
-#define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x0000003FL
-#define UVD_MPC_SET_MUXB1__VARB_6_MASK 0x00000FC0L
-#define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x0003F000L
-//UVD_MPC_SET_MUX
-#define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0
-#define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3
-#define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6
-#define UVD_MPC_SET_MUX__SET_0_MASK 0x00000007L
-#define UVD_MPC_SET_MUX__SET_1_MASK 0x00000038L
-#define UVD_MPC_SET_MUX__SET_2_MASK 0x000001C0L
-//UVD_MPC_SET_ALU
-#define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0
-#define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4
-#define UVD_MPC_SET_ALU__FUNCT_MASK 0x00000007L
-#define UVD_MPC_SET_ALU__OPERAND_MASK 0x00000FF0L
-//UVD_MPC_PERF0
-#define UVD_MPC_PERF0__MAX_LAT__SHIFT 0x0
-#define UVD_MPC_PERF0__MAX_LAT_MASK 0x000003FFL
-//UVD_MPC_PERF1
-#define UVD_MPC_PERF1__AVE_LAT__SHIFT 0x0
-#define UVD_MPC_PERF1__AVE_LAT_MASK 0x000003FFL
-//UVD_MPC_IND_INDEX
-#define UVD_MPC_IND_INDEX__INDEX__SHIFT 0x0
-#define UVD_MPC_IND_INDEX__INDEX_MASK 0x000001FFL
-//UVD_MPC_IND_DATA
-#define UVD_MPC_IND_DATA__DATA__SHIFT 0x0
-#define UVD_MPC_IND_DATA__DATA_MASK 0xFFFFFFFFL
-
-
-// addressBlock: uvd0_uvd_pg_dec
-//UVD_PGFSM_CONFIG
-#define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 0x0
-#define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 0x2
-#define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 0x4
-#define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 0x6
-#define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 0x8
-#define UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 0xa
-#define UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 0xc
-#define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 0xe
-#define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 0x10
-#define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 0x12
-#define UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT 0x14
-#define UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT 0x16
-#define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG_MASK 0x00000003L
-#define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG_MASK 0x0000000CL
-#define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG_MASK 0x00000030L
-#define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG_MASK 0x000000C0L
-#define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG_MASK 0x00000300L
-#define UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG_MASK 0x00000C00L
-#define UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG_MASK 0x00003000L
-#define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG_MASK 0x0000C000L
-#define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG_MASK 0x00030000L
-#define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG_MASK 0x000C0000L
-#define UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG_MASK 0x00300000L
-#define UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG_MASK 0x00C00000L
-//UVD_PGFSM_STATUS
-#define UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 0x0
-#define UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 0x2
-#define UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 0x4
-#define UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 0x6
-#define UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 0x8
-#define UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT 0xa
-#define UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT 0xc
-#define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 0xe
-#define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 0x10
-#define UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 0x12
-#define UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT 0x14
-#define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT 0x16
-#define UVD_PGFSM_STATUS__UVDM_PWR_STATUS_MASK 0x00000003L
-#define UVD_PGFSM_STATUS__UVDU_PWR_STATUS_MASK 0x0000000CL
-#define UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK 0x00000030L
-#define UVD_PGFSM_STATUS__UVDC_PWR_STATUS_MASK 0x000000C0L
-#define UVD_PGFSM_STATUS__UVDB_PWR_STATUS_MASK 0x00000300L
-#define UVD_PGFSM_STATUS__UVDIL_PWR_STATUS_MASK 0x00000C00L
-#define UVD_PGFSM_STATUS__UVDIR_PWR_STATUS_MASK 0x00003000L
-#define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS_MASK 0x0000C000L
-#define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS_MASK 0x00030000L
-#define UVD_PGFSM_STATUS__UVDE_PWR_STATUS_MASK 0x000C0000L
-#define UVD_PGFSM_STATUS__UVDW_PWR_STATUS_MASK 0x00300000L
-#define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK 0x00C00000L
-//UVD_POWER_STATUS
-#define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0
-#define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2
-#define UVD_POWER_STATUS__UVD_CG_MODE__SHIFT 0x4
-#define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8
-#define UVD_POWER_STATUS__RBC_SNOOP_DIS__SHIFT 0x9
-#define UVD_POWER_STATUS__SW_RB_SNOOP_DIS__SHIFT 0xb
-#define UVD_POWER_STATUS__STALL_DPG_POWER_UP__SHIFT 0x1f
-#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000003L
-#define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L
-#define UVD_POWER_STATUS__UVD_CG_MODE_MASK 0x00000030L
-#define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L
-#define UVD_POWER_STATUS__RBC_SNOOP_DIS_MASK 0x00000200L
-#define UVD_POWER_STATUS__SW_RB_SNOOP_DIS_MASK 0x00000800L
-#define UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK 0x80000000L
-//UVD_PG_IND_INDEX
-#define UVD_PG_IND_INDEX__INDEX__SHIFT 0x0
-#define UVD_PG_IND_INDEX__INDEX_MASK 0x0000003FL
-//UVD_PG_IND_DATA
-#define UVD_PG_IND_DATA__DATA__SHIFT 0x0
-#define UVD_PG_IND_DATA__DATA_MASK 0xFFFFFFFFL
-//CC_UVD_HARVESTING
-#define CC_UVD_HARVESTING__MMSCH_DISABLE__SHIFT 0x0
-#define CC_UVD_HARVESTING__UVD_DISABLE__SHIFT 0x1
-#define CC_UVD_HARVESTING__MMSCH_DISABLE_MASK 0x00000001L
-#define CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L
-//UVD_JPEG_POWER_STATUS
-#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS__SHIFT 0x0
-#define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE__SHIFT 0x4
-#define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS__SHIFT 0x8
-#define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS__SHIFT 0x9
-#define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP__SHIFT 0x1f
-#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK 0x00000001L
-#define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK 0x00000010L
-#define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS_MASK 0x00000100L
-#define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS_MASK 0x00000200L
-#define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP_MASK 0x80000000L
-//UVD_DPG_LMA_CTL
-#define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0
-#define UVD_DPG_LMA_CTL__MASK_EN__SHIFT 0x1
-#define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT__SHIFT 0x2
-#define UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT 0x4
-#define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0x10
-#define UVD_DPG_LMA_CTL__READ_WRITE_MASK 0x00000001L
-#define UVD_DPG_LMA_CTL__MASK_EN_MASK 0x00000002L
-#define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT_MASK 0x00000004L
-#define UVD_DPG_LMA_CTL__SRAM_SEL_MASK 0x00000010L
-#define UVD_DPG_LMA_CTL__READ_WRITE_ADDR_MASK 0xFFFF0000L
-//UVD_DPG_LMA_DATA
-#define UVD_DPG_LMA_DATA__LMA_DATA__SHIFT 0x0
-#define UVD_DPG_LMA_DATA__LMA_DATA_MASK 0xFFFFFFFFL
-//UVD_DPG_LMA_MASK
-#define UVD_DPG_LMA_MASK__LMA_MASK__SHIFT 0x0
-#define UVD_DPG_LMA_MASK__LMA_MASK_MASK 0xFFFFFFFFL
-//UVD_DPG_PAUSE
-#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ__SHIFT 0x0
-#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT 0x1
-#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT 0x2
-#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK__SHIFT 0x3
-#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK 0x00000001L
-#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK 0x00000002L
-#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK 0x00000004L
-#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK 0x00000008L
-//UVD_SCRATCH1
-#define UVD_SCRATCH1__SCRATCH1_DATA__SHIFT 0x0
-#define UVD_SCRATCH1__SCRATCH1_DATA_MASK 0xFFFFFFFFL
-//UVD_SCRATCH2
-#define UVD_SCRATCH2__SCRATCH2_DATA__SHIFT 0x0
-#define UVD_SCRATCH2__SCRATCH2_DATA_MASK 0xFFFFFFFFL
-//UVD_SCRATCH3
-#define UVD_SCRATCH3__SCRATCH3_DATA__SHIFT 0x0
-#define UVD_SCRATCH3__SCRATCH3_DATA_MASK 0xFFFFFFFFL
-//UVD_SCRATCH4
-#define UVD_SCRATCH4__SCRATCH4_DATA__SHIFT 0x0
-#define UVD_SCRATCH4__SCRATCH4_DATA_MASK 0xFFFFFFFFL
-//UVD_SCRATCH5
-#define UVD_SCRATCH5__SCRATCH5_DATA__SHIFT 0x0
-#define UVD_SCRATCH5__SCRATCH5_DATA_MASK 0xFFFFFFFFL
-//UVD_SCRATCH6
-#define UVD_SCRATCH6__SCRATCH6_DATA__SHIFT 0x0
-#define UVD_SCRATCH6__SCRATCH6_DATA_MASK 0xFFFFFFFFL
-//UVD_SCRATCH7
-#define UVD_SCRATCH7__SCRATCH7_DATA__SHIFT 0x0
-#define UVD_SCRATCH7__SCRATCH7_DATA_MASK 0xFFFFFFFFL
-//UVD_SCRATCH8
-#define UVD_SCRATCH8__SCRATCH8_DATA__SHIFT 0x0
-#define UVD_SCRATCH8__SCRATCH8_DATA_MASK 0xFFFFFFFFL
-//UVD_SCRATCH9
-#define UVD_SCRATCH9__SCRATCH9_DATA__SHIFT 0x0
-#define UVD_SCRATCH9__SCRATCH9_DATA_MASK 0xFFFFFFFFL
-//UVD_SCRATCH10
-#define UVD_SCRATCH10__SCRATCH10_DATA__SHIFT 0x0
-#define UVD_SCRATCH10__SCRATCH10_DATA_MASK 0xFFFFFFFFL
-//UVD_SCRATCH11
-#define UVD_SCRATCH11__SCRATCH11_DATA__SHIFT 0x0
-#define UVD_SCRATCH11__SCRATCH11_DATA_MASK 0xFFFFFFFFL
-//UVD_SCRATCH12
-#define UVD_SCRATCH12__SCRATCH12_DATA__SHIFT 0x0
-#define UVD_SCRATCH12__SCRATCH12_DATA_MASK 0xFFFFFFFFL
-//UVD_SCRATCH13
-#define UVD_SCRATCH13__SCRATCH13_DATA__SHIFT 0x0
-#define UVD_SCRATCH13__SCRATCH13_DATA_MASK 0xFFFFFFFFL
-//UVD_SCRATCH14
-#define UVD_SCRATCH14__SCRATCH14_DATA__SHIFT 0x0
-#define UVD_SCRATCH14__SCRATCH14_DATA_MASK 0xFFFFFFFFL
-//UVD_FREE_COUNTER_REG
-#define UVD_FREE_COUNTER_REG__FREE_COUNTER__SHIFT 0x0
-#define UVD_FREE_COUNTER_REG__FREE_COUNTER_MASK 0xFFFFFFFFL
-//UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW
-#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
-#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
-//UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH
-#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
-#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
-//UVD_DPG_VCPU_CACHE_OFFSET0
-#define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0
-#define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x01FFFFFFL
-//UVD_DPG_LMI_VCPU_CACHE_VMID
-#define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0
-#define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL
-//UVD_PF_STATUS
-#define UVD_PF_STATUS__JPEG_PF_OCCURED__SHIFT 0x0
-#define UVD_PF_STATUS__NJ_PF_OCCURED__SHIFT 0x1
-#define UVD_PF_STATUS__ENCODER0_PF_OCCURED__SHIFT 0x2
-#define UVD_PF_STATUS__ENCODER1_PF_OCCURED__SHIFT 0x3
-#define UVD_PF_STATUS__ENCODER2_PF_OCCURED__SHIFT 0x4
-#define UVD_PF_STATUS__ENCODER3_PF_OCCURED__SHIFT 0x5
-#define UVD_PF_STATUS__ENCODER4_PF_OCCURED__SHIFT 0x6
-#define UVD_PF_STATUS__EJPEG_PF_OCCURED__SHIFT 0x7
-#define UVD_PF_STATUS__JPEG_PF_CLEAR__SHIFT 0x8
-#define UVD_PF_STATUS__NJ_PF_CLEAR__SHIFT 0x9
-#define UVD_PF_STATUS__ENCODER0_PF_CLEAR__SHIFT 0xa
-#define UVD_PF_STATUS__ENCODER1_PF_CLEAR__SHIFT 0xb
-#define UVD_PF_STATUS__ENCODER2_PF_CLEAR__SHIFT 0xc
-#define UVD_PF_STATUS__ENCODER3_PF_CLEAR__SHIFT 0xd
-#define UVD_PF_STATUS__ENCODER4_PF_CLEAR__SHIFT 0xe
-#define UVD_PF_STATUS__EJPEG_PF_CLEAR__SHIFT 0xf
-#define UVD_PF_STATUS__NJ_ATM_PF_OCCURED__SHIFT 0x10
-#define UVD_PF_STATUS__DJ_ATM_PF_OCCURED__SHIFT 0x11
-#define UVD_PF_STATUS__EJ_ATM_PF_OCCURED__SHIFT 0x12
-#define UVD_PF_STATUS__JPEG_PF_OCCURED_MASK 0x00000001L
-#define UVD_PF_STATUS__NJ_PF_OCCURED_MASK 0x00000002L
-#define UVD_PF_STATUS__ENCODER0_PF_OCCURED_MASK 0x00000004L
-#define UVD_PF_STATUS__ENCODER1_PF_OCCURED_MASK 0x00000008L
-#define UVD_PF_STATUS__ENCODER2_PF_OCCURED_MASK 0x00000010L
-#define UVD_PF_STATUS__ENCODER3_PF_OCCURED_MASK 0x00000020L
-#define UVD_PF_STATUS__ENCODER4_PF_OCCURED_MASK 0x00000040L
-#define UVD_PF_STATUS__EJPEG_PF_OCCURED_MASK 0x00000080L
-#define UVD_PF_STATUS__JPEG_PF_CLEAR_MASK 0x00000100L
-#define UVD_PF_STATUS__NJ_PF_CLEAR_MASK 0x00000200L
-#define UVD_PF_STATUS__ENCODER0_PF_CLEAR_MASK 0x00000400L
-#define UVD_PF_STATUS__ENCODER1_PF_CLEAR_MASK 0x00000800L
-#define UVD_PF_STATUS__ENCODER2_PF_CLEAR_MASK 0x00001000L
-#define UVD_PF_STATUS__ENCODER3_PF_CLEAR_MASK 0x00002000L
-#define UVD_PF_STATUS__ENCODER4_PF_CLEAR_MASK 0x00004000L
-#define UVD_PF_STATUS__EJPEG_PF_CLEAR_MASK 0x00008000L
-#define UVD_PF_STATUS__NJ_ATM_PF_OCCURED_MASK 0x00010000L
-#define UVD_PF_STATUS__DJ_ATM_PF_OCCURED_MASK 0x00020000L
-#define UVD_PF_STATUS__EJ_ATM_PF_OCCURED_MASK 0x00040000L
-//UVD_FW_VERSION
-#define UVD_FW_VERSION__FW_VERSION__SHIFT 0x0
-#define UVD_FW_VERSION__FW_VERSION_MASK 0xFFFFFFFFL
-//UVD_DPG_CLK_EN_VCPU_REPORT
-#define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN__SHIFT 0x0
-#define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT__SHIFT 0x1
-#define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN_MASK 0x00000001L
-#define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT_MASK 0x000000FEL
-//UVD_GFX8_ADDR_CONFIG
-#define UVD_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
-#define UVD_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L
-//UVD_GFX10_ADDR_CONFIG
-#define UVD_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
-#define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
-#define UVD_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
-#define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
-#define UVD_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
-#define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
-#define UVD_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
-#define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
-//UVD_GPCNT2_CNTL
-#define UVD_GPCNT2_CNTL__CLR__SHIFT 0x0
-#define UVD_GPCNT2_CNTL__START__SHIFT 0x1
-#define UVD_GPCNT2_CNTL__COUNTUP__SHIFT 0x2
-#define UVD_GPCNT2_CNTL__CLR_MASK 0x00000001L
-#define UVD_GPCNT2_CNTL__START_MASK 0x00000002L
-#define UVD_GPCNT2_CNTL__COUNTUP_MASK 0x00000004L
-//UVD_GPCNT2_TARGET_LOWER
-#define UVD_GPCNT2_TARGET_LOWER__TARGET__SHIFT 0x0
-#define UVD_GPCNT2_TARGET_LOWER__TARGET_MASK 0xFFFFFFFFL
-//UVD_GPCNT2_STATUS_LOWER
-#define UVD_GPCNT2_STATUS_LOWER__COUNT__SHIFT 0x0
-#define UVD_GPCNT2_STATUS_LOWER__COUNT_MASK 0xFFFFFFFFL
-//UVD_GPCNT2_TARGET_UPPER
-#define UVD_GPCNT2_TARGET_UPPER__TARGET__SHIFT 0x0
-#define UVD_GPCNT2_TARGET_UPPER__TARGET_MASK 0x0000FFFFL
-//UVD_GPCNT2_STATUS_UPPER
-#define UVD_GPCNT2_STATUS_UPPER__COUNT__SHIFT 0x0
-#define UVD_GPCNT2_STATUS_UPPER__COUNT_MASK 0x0000FFFFL
-//UVD_GPCNT3_CNTL
-#define UVD_GPCNT3_CNTL__CLR__SHIFT 0x0
-#define UVD_GPCNT3_CNTL__START__SHIFT 0x1
-#define UVD_GPCNT3_CNTL__COUNTUP__SHIFT 0x2
-#define UVD_GPCNT3_CNTL__FREQ__SHIFT 0x3
-#define UVD_GPCNT3_CNTL__DIV__SHIFT 0xa
-#define UVD_GPCNT3_CNTL__CLR_MASK 0x00000001L
-#define UVD_GPCNT3_CNTL__START_MASK 0x00000002L
-#define UVD_GPCNT3_CNTL__COUNTUP_MASK 0x00000004L
-#define UVD_GPCNT3_CNTL__FREQ_MASK 0x000003F8L
-#define UVD_GPCNT3_CNTL__DIV_MASK 0x0001FC00L
-//UVD_GPCNT3_TARGET_LOWER
-#define UVD_GPCNT3_TARGET_LOWER__TARGET__SHIFT 0x0
-#define UVD_GPCNT3_TARGET_LOWER__TARGET_MASK 0xFFFFFFFFL
-//UVD_GPCNT3_STATUS_LOWER
-#define UVD_GPCNT3_STATUS_LOWER__COUNT__SHIFT 0x0
-#define UVD_GPCNT3_STATUS_LOWER__COUNT_MASK 0xFFFFFFFFL
-//UVD_GPCNT3_TARGET_UPPER
-#define UVD_GPCNT3_TARGET_UPPER__TARGET__SHIFT 0x0
-#define UVD_GPCNT3_TARGET_UPPER__TARGET_MASK 0x0000FFFFL
-//UVD_GPCNT3_STATUS_UPPER
-#define UVD_GPCNT3_STATUS_UPPER__COUNT__SHIFT 0x0
-#define UVD_GPCNT3_STATUS_UPPER__COUNT_MASK 0x0000FFFFL
-//UVD_VCLK_DS_CNTL
-#define UVD_VCLK_DS_CNTL__VCLK_DS_EN__SHIFT 0x0
-#define UVD_VCLK_DS_CNTL__VCLK_DS_STATUS__SHIFT 0x4
-#define UVD_VCLK_DS_CNTL__VCLK_DS_HYSTERESIS_CNT__SHIFT 0x10
-#define UVD_VCLK_DS_CNTL__VCLK_DS_EN_MASK 0x00000001L
-#define UVD_VCLK_DS_CNTL__VCLK_DS_STATUS_MASK 0x00000010L
-#define UVD_VCLK_DS_CNTL__VCLK_DS_HYSTERESIS_CNT_MASK 0xFFFF0000L
-//UVD_DCLK_DS_CNTL
-#define UVD_DCLK_DS_CNTL__DCLK_DS_EN__SHIFT 0x0
-#define UVD_DCLK_DS_CNTL__DCLK_DS_STATUS__SHIFT 0x4
-#define UVD_DCLK_DS_CNTL__DCLK_DS_HYSTERESIS_CNT__SHIFT 0x10
-#define UVD_DCLK_DS_CNTL__DCLK_DS_EN_MASK 0x00000001L
-#define UVD_DCLK_DS_CNTL__DCLK_DS_STATUS_MASK 0x00000010L
-#define UVD_DCLK_DS_CNTL__DCLK_DS_HYSTERESIS_CNT_MASK 0xFFFF0000L
-//UVD_RAS_VCPU_VCODEC_STATUS
-#define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_VF__SHIFT 0x0
-#define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_PF__SHIFT 0x1f
-#define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_VF_MASK 0x7FFFFFFFL
-#define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_PF_MASK 0x80000000L
-//UVD_RAS_MMSCH_FATAL_ERROR
-#define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_VF__SHIFT 0x0
-#define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_PF__SHIFT 0x1f
-#define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_VF_MASK 0x7FFFFFFFL
-#define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_PF_MASK 0x80000000L
-//UVD_RAS_JPEG0_STATUS
-#define UVD_RAS_JPEG0_STATUS__POISONED_VF__SHIFT 0x0
-#define UVD_RAS_JPEG0_STATUS__POISONED_PF__SHIFT 0x1f
-#define UVD_RAS_JPEG0_STATUS__POISONED_VF_MASK 0x7FFFFFFFL
-#define UVD_RAS_JPEG0_STATUS__POISONED_PF_MASK 0x80000000L
-//UVD_RAS_JPEG1_STATUS
-#define UVD_RAS_JPEG1_STATUS__POISONED_VF__SHIFT 0x0
-#define UVD_RAS_JPEG1_STATUS__POISONED_PF__SHIFT 0x1f
-#define UVD_RAS_JPEG1_STATUS__POISONED_VF_MASK 0x7FFFFFFFL
-#define UVD_RAS_JPEG1_STATUS__POISONED_PF_MASK 0x80000000L
-//UVD_RAS_CNTL_PMI_ARB
-#define UVD_RAS_CNTL_PMI_ARB__STAT_VCPU_VCODEC__SHIFT 0x0
-#define UVD_RAS_CNTL_PMI_ARB__ACK_VCPU_VCODEC__SHIFT 0x1
-#define UVD_RAS_CNTL_PMI_ARB__STAT_MMSCH__SHIFT 0x2
-#define UVD_RAS_CNTL_PMI_ARB__ACK_MMSCH__SHIFT 0x3
-#define UVD_RAS_CNTL_PMI_ARB__STAT_JPEG0__SHIFT 0x4
-#define UVD_RAS_CNTL_PMI_ARB__ACK_JPEG0__SHIFT 0x5
-#define UVD_RAS_CNTL_PMI_ARB__STAT_JPEG1__SHIFT 0x6
-#define UVD_RAS_CNTL_PMI_ARB__ACK_JPEG1__SHIFT 0x7
-#define UVD_RAS_CNTL_PMI_ARB__STAT_VCPU_VCODEC_MASK 0x00000001L
-#define UVD_RAS_CNTL_PMI_ARB__ACK_VCPU_VCODEC_MASK 0x00000002L
-#define UVD_RAS_CNTL_PMI_ARB__STAT_MMSCH_MASK 0x00000004L
-#define UVD_RAS_CNTL_PMI_ARB__ACK_MMSCH_MASK 0x00000008L
-#define UVD_RAS_CNTL_PMI_ARB__STAT_JPEG0_MASK 0x00000010L
-#define UVD_RAS_CNTL_PMI_ARB__ACK_JPEG0_MASK 0x00000020L
-#define UVD_RAS_CNTL_PMI_ARB__STAT_JPEG1_MASK 0x00000040L
-#define UVD_RAS_CNTL_PMI_ARB__ACK_JPEG1_MASK 0x00000080L
-
-
-// addressBlock: uvd0_uvd_rbcdec
-//UVD_RBC_IB_SIZE
-#define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4
-#define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L
-//UVD_RBC_IB_SIZE_UPDATE
-#define UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4
-#define UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L
-//UVD_RBC_RB_CNTL
-#define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0
-#define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8
-#define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10
-#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14
-#define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18
-#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c
-#define UVD_RBC_RB_CNTL__BLK_RST__SHIFT 0x1d
-#define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x0000001FL
-#define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x00001F00L
-#define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x00010000L
-#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x00100000L
-#define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x01000000L
-#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000L
-#define UVD_RBC_RB_CNTL__BLK_RST_MASK 0x20000000L
-//UVD_RBC_RB_RPTR_ADDR
-#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0
-#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFFL
-//UVD_RBC_RB_RPTR
-#define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4
-#define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L
-//UVD_RBC_RB_WPTR
-#define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4
-#define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L
-//UVD_RBC_VCPU_ACCESS
-#define UVD_RBC_VCPU_ACCESS__ENABLE_RBC__SHIFT 0x0
-#define UVD_RBC_VCPU_ACCESS__ENABLE_RBC_MASK 0x00000001L
-//UVD_FW_SEMAPHORE_CNTL
-#define UVD_FW_SEMAPHORE_CNTL__START__SHIFT 0x0
-#define UVD_FW_SEMAPHORE_CNTL__BUSY__SHIFT 0x8
-#define UVD_FW_SEMAPHORE_CNTL__PASS__SHIFT 0x9
-#define UVD_FW_SEMAPHORE_CNTL__START_MASK 0x00000001L
-#define UVD_FW_SEMAPHORE_CNTL__BUSY_MASK 0x00000100L
-#define UVD_FW_SEMAPHORE_CNTL__PASS_MASK 0x00000200L
-//UVD_RBC_READ_REQ_URGENT_CNTL
-#define UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0
-#define UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L
-//UVD_RBC_RB_WPTR_CNTL
-#define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x0
-#define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK 0x00007FFFL
-//UVD_RBC_WPTR_STATUS
-#define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE__SHIFT 0x4
-#define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE_MASK 0x007FFFF0L
-//UVD_RBC_WPTR_POLL_CNTL
-#define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ__SHIFT 0x0
-#define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
-#define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ_MASK 0x0000FFFFL
-#define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
-//UVD_RBC_WPTR_POLL_ADDR
-#define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR__SHIFT 0x2
-#define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR_MASK 0xFFFFFFFCL
-//UVD_SEMA_CMD
-#define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
-#define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
-#define UVD_SEMA_CMD__MODE__SHIFT 0x6
-#define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7
-#define UVD_SEMA_CMD__VMID__SHIFT 0x8
-#define UVD_SEMA_CMD__REQ_CMD_MASK 0x0000000FL
-#define UVD_SEMA_CMD__WR_PHASE_MASK 0x00000030L
-#define UVD_SEMA_CMD__MODE_MASK 0x00000040L
-#define UVD_SEMA_CMD__VMID_EN_MASK 0x00000080L
-#define UVD_SEMA_CMD__VMID_MASK 0x00000F00L
-//UVD_SEMA_ADDR_LOW
-#define UVD_SEMA_ADDR_LOW__ADDR_26_3__SHIFT 0x0
-#define UVD_SEMA_ADDR_LOW__ADDR_26_3_MASK 0x00FFFFFFL
-//UVD_SEMA_ADDR_HIGH
-#define UVD_SEMA_ADDR_HIGH__ADDR_47_27__SHIFT 0x0
-#define UVD_SEMA_ADDR_HIGH__ADDR_47_27_MASK 0x001FFFFFL
-//UVD_ENGINE_CNTL
-#define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0
-#define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1
-#define UVD_ENGINE_CNTL__NJ_PF_HANDLE_DISABLE__SHIFT 0x2
-#define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x00000001L
-#define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x00000002L
-#define UVD_ENGINE_CNTL__NJ_PF_HANDLE_DISABLE_MASK 0x00000004L
-//UVD_SEMA_TIMEOUT_STATUS
-#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0
-#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1
-#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2
-#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3
-#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000001L
-#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x00000002L
-#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000004L
-#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x00000008L
-//UVD_SEMA_CNTL
-#define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0
-#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1
-#define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x00000001L
-#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x00000002L
-//UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL
-#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0
-#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1
-#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
-#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x00000001L
-#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x001FFFFEL
-#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L
-//UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL
-#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0
-#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1
-#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
-#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x00000001L
-#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x001FFFFEL
-#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L
-//UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL
-#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0
-#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1
-#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
-#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x00000001L
-#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x001FFFFEL
-#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L
-//UVD_JOB_START
-#define UVD_JOB_START__JOB_START__SHIFT 0x0
-#define UVD_JOB_START__JOB_START_MASK 0x00000001L
-//UVD_RBC_BUF_STATUS
-#define UVD_RBC_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0
-#define UVD_RBC_BUF_STATUS__IB_BUF_VALID__SHIFT 0x8
-#define UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10
-#define UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x13
-#define UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x16
-#define UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x19
-#define UVD_RBC_BUF_STATUS__RB_BUF_VALID_MASK 0x000000FFL
-#define UVD_RBC_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FF00L
-#define UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x00070000L
-#define UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x00380000L
-#define UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x01C00000L
-#define UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x0E000000L
-//UVD_RBC_SWAP_CNTL
-#define UVD_RBC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0
-#define UVD_RBC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2
-#define UVD_RBC_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4
-#define UVD_RBC_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a
-#define UVD_RBC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L
-#define UVD_RBC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL
-#define UVD_RBC_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x00000030L
-#define UVD_RBC_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0x0C000000L
-
-
-// addressBlock: uvd0_uvddec
-//UVD_STATUS
-#define UVD_STATUS__RBC_BUSY__SHIFT 0x0
-#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1
-#define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT 0x10
-#define UVD_STATUS__SYS_GPCOM_REQ__SHIFT 0x1f
-#define UVD_STATUS__RBC_BUSY_MASK 0x00000001L
-#define UVD_STATUS__VCPU_REPORT_MASK 0x000000FEL
-#define UVD_STATUS__RBC_ACCESS_GPCOM_MASK 0x00010000L
-#define UVD_STATUS__SYS_GPCOM_REQ_MASK 0x80000000L
-//UVD_ENC_PIPE_BUSY
-#define UVD_ENC_PIPE_BUSY__IME_BUSY__SHIFT 0x0
-#define UVD_ENC_PIPE_BUSY__SMP_BUSY__SHIFT 0x1
-#define UVD_ENC_PIPE_BUSY__SIT_BUSY__SHIFT 0x2
-#define UVD_ENC_PIPE_BUSY__SDB_BUSY__SHIFT 0x3
-#define UVD_ENC_PIPE_BUSY__ENT_BUSY__SHIFT 0x4
-#define UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY__SHIFT 0x5
-#define UVD_ENC_PIPE_BUSY__LCM_BUSY__SHIFT 0x6
-#define UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY__SHIFT 0x7
-#define UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY__SHIFT 0x8
-#define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY__SHIFT 0xa
-#define UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY__SHIFT 0x10
-#define UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY__SHIFT 0x11
-#define UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY__SHIFT 0x12
-#define UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY__SHIFT 0x13
-#define UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY__SHIFT 0x14
-#define UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY__SHIFT 0x15
-#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY__SHIFT 0x16
-#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY__SHIFT 0x17
-#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY__SHIFT 0x18
-#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY__SHIFT 0x19
-#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY__SHIFT 0x1a
-#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY__SHIFT 0x1b
-#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY__SHIFT 0x1c
-#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY__SHIFT 0x1d
-#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY__SHIFT 0x1e
-#define UVD_ENC_PIPE_BUSY__IME_BUSY_MASK 0x00000001L
-#define UVD_ENC_PIPE_BUSY__SMP_BUSY_MASK 0x00000002L
-#define UVD_ENC_PIPE_BUSY__SIT_BUSY_MASK 0x00000004L
-#define UVD_ENC_PIPE_BUSY__SDB_BUSY_MASK 0x00000008L
-#define UVD_ENC_PIPE_BUSY__ENT_BUSY_MASK 0x00000010L
-#define UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY_MASK 0x00000020L
-#define UVD_ENC_PIPE_BUSY__LCM_BUSY_MASK 0x00000040L
-#define UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY_MASK 0x00000080L
-#define UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY_MASK 0x00000100L
-#define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY_MASK 0x00000400L
-#define UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY_MASK 0x00010000L
-#define UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY_MASK 0x00020000L
-#define UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY_MASK 0x00040000L
-#define UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY_MASK 0x00080000L
-#define UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY_MASK 0x00100000L
-#define UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY_MASK 0x00200000L
-#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY_MASK 0x00400000L
-#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY_MASK 0x00800000L
-#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY_MASK 0x01000000L
-#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY_MASK 0x02000000L
-#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY_MASK 0x04000000L
-#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY_MASK 0x08000000L
-#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY_MASK 0x10000000L
-#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY_MASK 0x20000000L
-#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY_MASK 0x40000000L
-//UVD_FW_POWER_STATUS
-#define UVD_FW_POWER_STATUS__UVDF_PWR_OFF__SHIFT 0x0
-#define UVD_FW_POWER_STATUS__UVDC_PWR_OFF__SHIFT 0x1
-#define UVD_FW_POWER_STATUS__UVDB_PWR_OFF__SHIFT 0x2
-#define UVD_FW_POWER_STATUS__UVDIL_PWR_OFF__SHIFT 0x3
-#define UVD_FW_POWER_STATUS__UVDIR_PWR_OFF__SHIFT 0x4
-#define UVD_FW_POWER_STATUS__UVDTD_PWR_OFF__SHIFT 0x5
-#define UVD_FW_POWER_STATUS__UVDTE_PWR_OFF__SHIFT 0x6
-#define UVD_FW_POWER_STATUS__UVDE_PWR_OFF__SHIFT 0x7
-#define UVD_FW_POWER_STATUS__UVDW_PWR_OFF__SHIFT 0x8
-#define UVD_FW_POWER_STATUS__UVDF_PWR_OFF_MASK 0x00000001L
-#define UVD_FW_POWER_STATUS__UVDC_PWR_OFF_MASK 0x00000002L
-#define UVD_FW_POWER_STATUS__UVDB_PWR_OFF_MASK 0x00000004L
-#define UVD_FW_POWER_STATUS__UVDIL_PWR_OFF_MASK 0x00000008L
-#define UVD_FW_POWER_STATUS__UVDIR_PWR_OFF_MASK 0x00000010L
-#define UVD_FW_POWER_STATUS__UVDTD_PWR_OFF_MASK 0x00000020L
-#define UVD_FW_POWER_STATUS__UVDTE_PWR_OFF_MASK 0x00000040L
-#define UVD_FW_POWER_STATUS__UVDE_PWR_OFF_MASK 0x00000080L
-#define UVD_FW_POWER_STATUS__UVDW_PWR_OFF_MASK 0x00000100L
-//UVD_CNTL
-#define UVD_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT 0x11
-#define UVD_CNTL__SUVD_EN__SHIFT 0x13
-#define UVD_CNTL__CABAC_MB_ACC__SHIFT 0x1c
-#define UVD_CNTL__LRBBM_SAFE_SYNC_DIS__SHIFT 0x1f
-#define UVD_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x00020000L
-#define UVD_CNTL__SUVD_EN_MASK 0x00080000L
-#define UVD_CNTL__CABAC_MB_ACC_MASK 0x10000000L
-#define UVD_CNTL__LRBBM_SAFE_SYNC_DIS_MASK 0x80000000L
-//UVD_SOFT_RESET
-#define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0
-#define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1
-#define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2
-#define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3
-#define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4
-#define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6
-#define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7
-#define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8
-#define UVD_SOFT_RESET__EFC_SOFT_RESET__SHIFT 0x9
-#define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa
-#define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb
-#define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc
-#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd
-#define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe
-#define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf
-#define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10
-#define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11
-#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12
-#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13
-#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14
-#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15
-#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16
-#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS__SHIFT 0x17
-#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS__SHIFT 0x18
-#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS__SHIFT 0x19
-#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a
-#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b
-#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c
-#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d
-#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e
-#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f
-#define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x00000001L
-#define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x00000002L
-#define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x00000004L
-#define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x00000008L
-#define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x00000010L
-#define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x00000040L
-#define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000080L
-#define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x00000100L
-#define UVD_SOFT_RESET__EFC_SOFT_RESET_MASK 0x00000200L
-#define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x00000400L
-#define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x00000800L
-#define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x00001000L
-#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x00002000L
-#define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x00004000L
-#define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x00008000L
-#define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x00010000L
-#define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x00020000L
-#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x00040000L
-#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x00080000L
-#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x00100000L
-#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x00200000L
-#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x00400000L
-#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS_MASK 0x00800000L
-#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS_MASK 0x01000000L
-#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS_MASK 0x02000000L
-#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x04000000L
-#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x08000000L
-#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000L
-#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000L
-#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000L
-#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000L
-//UVD_SOFT_RESET2
-#define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET__SHIFT 0x0
-#define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS__SHIFT 0x10
-#define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS__SHIFT 0x11
-#define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET_MASK 0x00000001L
-#define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS_MASK 0x00010000L
-#define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS_MASK 0x00020000L
-//UVD_MMSCH_SOFT_RESET
-#define UVD_MMSCH_SOFT_RESET__MMSCH_RESET__SHIFT 0x0
-#define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x1
-#define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK__SHIFT 0x1f
-#define UVD_MMSCH_SOFT_RESET__MMSCH_RESET_MASK 0x00000001L
-#define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000002L
-#define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK_MASK 0x80000000L
-//UVD_WIG_CTRL
-#define UVD_WIG_CTRL__AVM_SOFT_RESET__SHIFT 0x0
-#define UVD_WIG_CTRL__ACAP_SOFT_RESET__SHIFT 0x1
-#define UVD_WIG_CTRL__WIG_SOFT_RESET__SHIFT 0x2
-#define UVD_WIG_CTRL__WIG_REGCLK_FORCE_ON__SHIFT 0x3
-#define UVD_WIG_CTRL__AVM_REGCLK_FORCE_ON__SHIFT 0x4
-#define UVD_WIG_CTRL__AVM_SOFT_RESET_MASK 0x00000001L
-#define UVD_WIG_CTRL__ACAP_SOFT_RESET_MASK 0x00000002L
-#define UVD_WIG_CTRL__WIG_SOFT_RESET_MASK 0x00000004L
-#define UVD_WIG_CTRL__WIG_REGCLK_FORCE_ON_MASK 0x00000008L
-#define UVD_WIG_CTRL__AVM_REGCLK_FORCE_ON_MASK 0x00000010L
-//UVD_CGC_GATE
-#define UVD_CGC_GATE__SYS__SHIFT 0x0
-#define UVD_CGC_GATE__UDEC__SHIFT 0x1
-#define UVD_CGC_GATE__MPEG2__SHIFT 0x2
-#define UVD_CGC_GATE__REGS__SHIFT 0x3
-#define UVD_CGC_GATE__RBC__SHIFT 0x4
-#define UVD_CGC_GATE__LMI_MC__SHIFT 0x5
-#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6
-#define UVD_CGC_GATE__IDCT__SHIFT 0x7
-#define UVD_CGC_GATE__MPRD__SHIFT 0x8
-#define UVD_CGC_GATE__MPC__SHIFT 0x9
-#define UVD_CGC_GATE__LBSI__SHIFT 0xa
-#define UVD_CGC_GATE__LRBBM__SHIFT 0xb
-#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc
-#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd
-#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe
-#define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf
-#define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10
-#define UVD_CGC_GATE__WCB__SHIFT 0x11
-#define UVD_CGC_GATE__VCPU__SHIFT 0x12
-#define UVD_CGC_GATE__MMSCH__SHIFT 0x14
-#define UVD_CGC_GATE__SYS_MASK 0x00000001L
-#define UVD_CGC_GATE__UDEC_MASK 0x00000002L
-#define UVD_CGC_GATE__MPEG2_MASK 0x00000004L
-#define UVD_CGC_GATE__REGS_MASK 0x00000008L
-#define UVD_CGC_GATE__RBC_MASK 0x00000010L
-#define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L
-#define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L
-#define UVD_CGC_GATE__IDCT_MASK 0x00000080L
-#define UVD_CGC_GATE__MPRD_MASK 0x00000100L
-#define UVD_CGC_GATE__MPC_MASK 0x00000200L
-#define UVD_CGC_GATE__LBSI_MASK 0x00000400L
-#define UVD_CGC_GATE__LRBBM_MASK 0x00000800L
-#define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L
-#define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L
-#define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L
-#define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L
-#define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L
-#define UVD_CGC_GATE__WCB_MASK 0x00020000L
-#define UVD_CGC_GATE__VCPU_MASK 0x00040000L
-#define UVD_CGC_GATE__MMSCH_MASK 0x00100000L
-//UVD_CGC_STATUS
-#define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0
-#define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1
-#define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2
-#define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3
-#define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4
-#define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5
-#define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6
-#define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7
-#define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8
-#define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9
-#define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa
-#define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb
-#define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc
-#define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd
-#define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe
-#define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf
-#define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10
-#define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11
-#define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12
-#define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13
-#define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14
-#define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15
-#define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16
-#define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17
-#define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18
-#define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19
-#define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a
-#define UVD_CGC_STATUS__MMSCH_SCLK__SHIFT 0x1b
-#define UVD_CGC_STATUS__MMSCH_VCLK__SHIFT 0x1c
-#define UVD_CGC_STATUS__ALL_ENC_ACTIVE__SHIFT 0x1d
-#define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT 0x1f
-#define UVD_CGC_STATUS__SYS_SCLK_MASK 0x00000001L
-#define UVD_CGC_STATUS__SYS_DCLK_MASK 0x00000002L
-#define UVD_CGC_STATUS__SYS_VCLK_MASK 0x00000004L
-#define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x00000008L
-#define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x00000010L
-#define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x00000020L
-#define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x00000040L
-#define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x00000080L
-#define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x00000100L
-#define UVD_CGC_STATUS__REGS_SCLK_MASK 0x00000200L
-#define UVD_CGC_STATUS__REGS_VCLK_MASK 0x00000400L
-#define UVD_CGC_STATUS__RBC_SCLK_MASK 0x00000800L
-#define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x00001000L
-#define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x00002000L
-#define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x00004000L
-#define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x00008000L
-#define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x00010000L
-#define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x00020000L
-#define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x00040000L
-#define UVD_CGC_STATUS__MPC_SCLK_MASK 0x00080000L
-#define UVD_CGC_STATUS__MPC_DCLK_MASK 0x00100000L
-#define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x00200000L
-#define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x00400000L
-#define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x00800000L
-#define UVD_CGC_STATUS__WCB_SCLK_MASK 0x01000000L
-#define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x02000000L
-#define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x04000000L
-#define UVD_CGC_STATUS__MMSCH_SCLK_MASK 0x08000000L
-#define UVD_CGC_STATUS__MMSCH_VCLK_MASK 0x10000000L
-#define UVD_CGC_STATUS__ALL_ENC_ACTIVE_MASK 0x20000000L
-#define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK 0x80000000L
-//UVD_CGC_CTRL
-#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0
-#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2
-#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6
-#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb
-#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc
-#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd
-#define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe
-#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf
-#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10
-#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11
-#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12
-#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13
-#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14
-#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15
-#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16
-#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17
-#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18
-#define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19
-#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a
-#define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b
-#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c
-#define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d
-#define UVD_CGC_CTRL__MMSCH_MODE__SHIFT 0x1f
-#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L
-#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL
-#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L
-#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L
-#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L
-#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L
-#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L
-#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L
-#define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L
-#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L
-#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L
-#define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L
-#define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L
-#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L
-#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L
-#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L
-#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L
-#define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L
-#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L
-#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L
-#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L
-#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L
-#define UVD_CGC_CTRL__MMSCH_MODE_MASK 0x80000000L
-//UVD_CGC_UDEC_STATUS
-#define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0
-#define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1
-#define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2
-#define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3
-#define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4
-#define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5
-#define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6
-#define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7
-#define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8
-#define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9
-#define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa
-#define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb
-#define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc
-#define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd
-#define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe
-#define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x00000001L
-#define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x00000002L
-#define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x00000004L
-#define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x00000008L
-#define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x00000010L
-#define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x00000020L
-#define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x00000040L
-#define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x00000080L
-#define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x00000100L
-#define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x00000200L
-#define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x00000400L
-#define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x00000800L
-#define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x00001000L
-#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x00002000L
-#define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x00004000L
-//UVD_SUVD_CGC_GATE
-#define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0
-#define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1
-#define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2
-#define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3
-#define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4
-#define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
-#define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6
-#define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7
-#define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8
-#define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9
-#define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
-#define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb
-#define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc
-#define UVD_SUVD_CGC_GATE__SCLR__SHIFT 0xd
-#define UVD_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe
-#define UVD_SUVD_CGC_GATE__ENT__SHIFT 0xf
-#define UVD_SUVD_CGC_GATE__IME__SHIFT 0x10
-#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11
-#define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12
-#define UVD_SUVD_CGC_GATE__SITE__SHIFT 0x13
-#define UVD_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14
-#define UVD_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15
-#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16
-#define UVD_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17
-#define UVD_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18
-#define UVD_SUVD_CGC_GATE__EFC__SHIFT 0x19
-#define UVD_SUVD_CGC_GATE__SRE_MASK 0x00000001L
-#define UVD_SUVD_CGC_GATE__SIT_MASK 0x00000002L
-#define UVD_SUVD_CGC_GATE__SMP_MASK 0x00000004L
-#define UVD_SUVD_CGC_GATE__SCM_MASK 0x00000008L
-#define UVD_SUVD_CGC_GATE__SDB_MASK 0x00000010L
-#define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L
-#define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L
-#define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L
-#define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L
-#define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L
-#define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L
-#define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L
-#define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L
-#define UVD_SUVD_CGC_GATE__SCLR_MASK 0x00002000L
-#define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L
-#define UVD_SUVD_CGC_GATE__ENT_MASK 0x00008000L
-#define UVD_SUVD_CGC_GATE__IME_MASK 0x00010000L
-#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L
-#define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L
-#define UVD_SUVD_CGC_GATE__SITE_MASK 0x00080000L
-#define UVD_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L
-#define UVD_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L
-#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L
-#define UVD_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L
-#define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L
-#define UVD_SUVD_CGC_GATE__EFC_MASK 0x02000000L
-//UVD_SUVD_CGC_STATUS
-#define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT 0x0
-#define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT 0x1
-#define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2
-#define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3
-#define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT 0x4
-#define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5
-#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6
-#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT 0x7
-#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT 0x8
-#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9
-#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa
-#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb
-#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT 0xc
-#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd
-#define UVD_SUVD_CGC_STATUS__SCLR_DCLK__SHIFT 0xe
-#define UVD_SUVD_CGC_STATUS__UVD_SC__SHIFT 0xf
-#define UVD_SUVD_CGC_STATUS__ENT_DCLK__SHIFT 0x10
-#define UVD_SUVD_CGC_STATUS__IME_DCLK__SHIFT 0x11
-#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK__SHIFT 0x12
-#define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK__SHIFT 0x13
-#define UVD_SUVD_CGC_STATUS__SITE_DCLK__SHIFT 0x14
-#define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK__SHIFT 0x15
-#define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK__SHIFT 0x16
-#define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK__SHIFT 0x17
-#define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK__SHIFT 0x18
-#define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK__SHIFT 0x19
-#define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK__SHIFT 0x1a
-#define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK__SHIFT 0x1b
-#define UVD_SUVD_CGC_STATUS__EFC_DCLK__SHIFT 0x1c
-#define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x00000001L
-#define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x00000002L
-#define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x00000004L
-#define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x00000008L
-#define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x00000010L
-#define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x00000020L
-#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x00000040L
-#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x00000080L
-#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x00000100L
-#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x00000200L
-#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK 0x00000400L
-#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x00000800L
-#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK 0x00001000L
-#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x00002000L
-#define UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK 0x00004000L
-#define UVD_SUVD_CGC_STATUS__UVD_SC_MASK 0x00008000L
-#define UVD_SUVD_CGC_STATUS__ENT_DCLK_MASK 0x00010000L
-#define UVD_SUVD_CGC_STATUS__IME_DCLK_MASK 0x00020000L
-#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK_MASK 0x00040000L
-#define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK_MASK 0x00080000L
-#define UVD_SUVD_CGC_STATUS__SITE_DCLK_MASK 0x00100000L
-#define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK_MASK 0x00200000L
-#define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK_MASK 0x00400000L
-#define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK_MASK 0x00800000L
-#define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK_MASK 0x01000000L
-#define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK_MASK 0x02000000L
-#define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK_MASK 0x04000000L
-#define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK_MASK 0x08000000L
-#define UVD_SUVD_CGC_STATUS__EFC_DCLK_MASK 0x10000000L
-//UVD_SUVD_CGC_CTRL
-#define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0
-#define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1
-#define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2
-#define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3
-#define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4
-#define UVD_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5
-#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6
-#define UVD_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7
-#define UVD_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8
-#define UVD_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9
-#define UVD_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa
-#define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L
-#define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L
-#define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L
-#define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L
-#define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L
-#define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L
-#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L
-#define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L
-#define UVD_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L
-#define UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L
-#define UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L
-//UVD_GPCOM_VCPU_CMD
-#define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0
-#define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1
-#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f
-#define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x00000001L
-#define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7FFFFFFEL
-#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000L
-//UVD_GPCOM_VCPU_DATA0
-#define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0
-#define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xFFFFFFFFL
-//UVD_GPCOM_VCPU_DATA1
-#define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0
-#define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xFFFFFFFFL
-//UVD_GPCOM_SYS_CMD
-#define UVD_GPCOM_SYS_CMD__CMD_SEND__SHIFT 0x0
-#define UVD_GPCOM_SYS_CMD__CMD__SHIFT 0x1
-#define UVD_GPCOM_SYS_CMD__CMD_SOURCE__SHIFT 0x1f
-#define UVD_GPCOM_SYS_CMD__CMD_SEND_MASK 0x00000001L
-#define UVD_GPCOM_SYS_CMD__CMD_MASK 0x7FFFFFFEL
-#define UVD_GPCOM_SYS_CMD__CMD_SOURCE_MASK 0x80000000L
-//UVD_GPCOM_SYS_DATA0
-#define UVD_GPCOM_SYS_DATA0__DATA0__SHIFT 0x0
-#define UVD_GPCOM_SYS_DATA0__DATA0_MASK 0xFFFFFFFFL
-//UVD_GPCOM_SYS_DATA1
-#define UVD_GPCOM_SYS_DATA1__DATA1__SHIFT 0x0
-#define UVD_GPCOM_SYS_DATA1__DATA1_MASK 0xFFFFFFFFL
-//UVD_VCPU_INT_EN
-#define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN__SHIFT 0x0
-#define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT 0x1
-#define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT 0x2
-#define UVD_VCPU_INT_EN__NJ_PF_RPT_EN__SHIFT 0x3
-#define UVD_VCPU_INT_EN__SW_RB1_INT_EN__SHIFT 0x4
-#define UVD_VCPU_INT_EN__SW_RB2_INT_EN__SHIFT 0x5
-#define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT 0x6
-#define UVD_VCPU_INT_EN__SW_RB3_INT_EN__SHIFT 0x7
-#define UVD_VCPU_INT_EN__SW_RB4_INT_EN__SHIFT 0x9
-#define UVD_VCPU_INT_EN__SW_RB5_INT_EN__SHIFT 0xa
-#define UVD_VCPU_INT_EN__LBSI_EN__SHIFT 0xb
-#define UVD_VCPU_INT_EN__UDEC_EN__SHIFT 0xc
-#define UVD_VCPU_INT_EN__SUVD_EN__SHIFT 0xf
-#define UVD_VCPU_INT_EN__RPTR_WR_EN__SHIFT 0x10
-#define UVD_VCPU_INT_EN__JOB_START_EN__SHIFT 0x11
-#define UVD_VCPU_INT_EN__NJ_PF_EN__SHIFT 0x12
-#define UVD_VCPU_INT_EN__RASCNTL_VCPU_VCODEC_EN__SHIFT 0x16
-#define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT 0x17
-#define UVD_VCPU_INT_EN__IDCT_EN__SHIFT 0x18
-#define UVD_VCPU_INT_EN__MPRD_EN__SHIFT 0x19
-#define UVD_VCPU_INT_EN__AVM_INT_EN__SHIFT 0x1a
-#define UVD_VCPU_INT_EN__CLK_SWT_EN__SHIFT 0x1b
-#define UVD_VCPU_INT_EN__MIF_HWINT_EN__SHIFT 0x1c
-#define UVD_VCPU_INT_EN__MPRD_ERR_EN__SHIFT 0x1d
-#define UVD_VCPU_INT_EN__DRV_FW_REQ_EN__SHIFT 0x1e
-#define UVD_VCPU_INT_EN__DRV_FW_ACK_EN__SHIFT 0x1f
-#define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN_MASK 0x00000001L
-#define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK 0x00000002L
-#define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK 0x00000004L
-#define UVD_VCPU_INT_EN__NJ_PF_RPT_EN_MASK 0x00000008L
-#define UVD_VCPU_INT_EN__SW_RB1_INT_EN_MASK 0x00000010L
-#define UVD_VCPU_INT_EN__SW_RB2_INT_EN_MASK 0x00000020L
-#define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK 0x00000040L
-#define UVD_VCPU_INT_EN__SW_RB3_INT_EN_MASK 0x00000080L
-#define UVD_VCPU_INT_EN__SW_RB4_INT_EN_MASK 0x00000200L
-#define UVD_VCPU_INT_EN__SW_RB5_INT_EN_MASK 0x00000400L
-#define UVD_VCPU_INT_EN__LBSI_EN_MASK 0x00000800L
-#define UVD_VCPU_INT_EN__UDEC_EN_MASK 0x00001000L
-#define UVD_VCPU_INT_EN__SUVD_EN_MASK 0x00008000L
-#define UVD_VCPU_INT_EN__RPTR_WR_EN_MASK 0x00010000L
-#define UVD_VCPU_INT_EN__JOB_START_EN_MASK 0x00020000L
-#define UVD_VCPU_INT_EN__NJ_PF_EN_MASK 0x00040000L
-#define UVD_VCPU_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK 0x00400000L
-#define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK 0x00800000L
-#define UVD_VCPU_INT_EN__IDCT_EN_MASK 0x01000000L
-#define UVD_VCPU_INT_EN__MPRD_EN_MASK 0x02000000L
-#define UVD_VCPU_INT_EN__AVM_INT_EN_MASK 0x04000000L
-#define UVD_VCPU_INT_EN__CLK_SWT_EN_MASK 0x08000000L
-#define UVD_VCPU_INT_EN__MIF_HWINT_EN_MASK 0x10000000L
-#define UVD_VCPU_INT_EN__MPRD_ERR_EN_MASK 0x20000000L
-#define UVD_VCPU_INT_EN__DRV_FW_REQ_EN_MASK 0x40000000L
-#define UVD_VCPU_INT_EN__DRV_FW_ACK_EN_MASK 0x80000000L
-//UVD_VCPU_INT_STATUS
-#define UVD_VCPU_INT_STATUS__PIF_ADDR_ERR_INT__SHIFT 0x0
-#define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT__SHIFT 0x1
-#define UVD_VCPU_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT__SHIFT 0x2
-#define UVD_VCPU_INT_STATUS__NJ_PF_RPT_INT__SHIFT 0x3
-#define UVD_VCPU_INT_STATUS__SW_RB1_INT__SHIFT 0x4
-#define UVD_VCPU_INT_STATUS__SW_RB2_INT__SHIFT 0x5
-#define UVD_VCPU_INT_STATUS__RBC_REG_PRIV_FAULT_INT__SHIFT 0x6
-#define UVD_VCPU_INT_STATUS__SW_RB3_INT__SHIFT 0x7
-#define UVD_VCPU_INT_STATUS__SW_RB4_INT__SHIFT 0x9
-#define UVD_VCPU_INT_STATUS__SW_RB5_INT__SHIFT 0xa
-#define UVD_VCPU_INT_STATUS__LBSI_INT__SHIFT 0xb
-#define UVD_VCPU_INT_STATUS__UDEC_INT__SHIFT 0xc
-#define UVD_VCPU_INT_STATUS__SUVD_INT__SHIFT 0xf
-#define UVD_VCPU_INT_STATUS__RPTR_WR_INT__SHIFT 0x10
-#define UVD_VCPU_INT_STATUS__JOB_START_INT__SHIFT 0x11
-#define UVD_VCPU_INT_STATUS__NJ_PF_INT__SHIFT 0x12
-#define UVD_VCPU_INT_STATUS__GPCOM_INT__SHIFT 0x14
-#define UVD_VCPU_INT_STATUS__RASCNTL_VCPU_VCODEC_INT__SHIFT 0x15
-#define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT__SHIFT 0x17
-#define UVD_VCPU_INT_STATUS__IDCT_INT__SHIFT 0x18
-#define UVD_VCPU_INT_STATUS__MPRD_INT__SHIFT 0x19
-#define UVD_VCPU_INT_STATUS__AVM_INT__SHIFT 0x1a
-#define UVD_VCPU_INT_STATUS__CLK_SWT_INT__SHIFT 0x1b
-#define UVD_VCPU_INT_STATUS__MIF_HWINT__SHIFT 0x1c
-#define UVD_VCPU_INT_STATUS__MPRD_ERR_INT__SHIFT 0x1d
-#define UVD_VCPU_INT_STATUS__DRV_FW_REQ_INT__SHIFT 0x1e
-#define UVD_VCPU_INT_STATUS__DRV_FW_ACK_INT__SHIFT 0x1f
-#define UVD_VCPU_INT_STATUS__PIF_ADDR_ERR_INT_MASK 0x00000001L
-#define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT_MASK 0x00000002L
-#define UVD_VCPU_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT_MASK 0x00000004L
-#define UVD_VCPU_INT_STATUS__NJ_PF_RPT_INT_MASK 0x00000008L
-#define UVD_VCPU_INT_STATUS__SW_RB1_INT_MASK 0x00000010L
-#define UVD_VCPU_INT_STATUS__SW_RB2_INT_MASK 0x00000020L
-#define UVD_VCPU_INT_STATUS__RBC_REG_PRIV_FAULT_INT_MASK 0x00000040L
-#define UVD_VCPU_INT_STATUS__SW_RB3_INT_MASK 0x00000080L
-#define UVD_VCPU_INT_STATUS__SW_RB4_INT_MASK 0x00000200L
-#define UVD_VCPU_INT_STATUS__SW_RB5_INT_MASK 0x00000400L
-#define UVD_VCPU_INT_STATUS__LBSI_INT_MASK 0x00000800L
-#define UVD_VCPU_INT_STATUS__UDEC_INT_MASK 0x00001000L
-#define UVD_VCPU_INT_STATUS__SUVD_INT_MASK 0x00008000L
-#define UVD_VCPU_INT_STATUS__RPTR_WR_INT_MASK 0x00010000L
-#define UVD_VCPU_INT_STATUS__JOB_START_INT_MASK 0x00020000L
-#define UVD_VCPU_INT_STATUS__NJ_PF_INT_MASK 0x00040000L
-#define UVD_VCPU_INT_STATUS__GPCOM_INT_MASK 0x00100000L
-#define UVD_VCPU_INT_STATUS__RASCNTL_VCPU_VCODEC_INT_MASK 0x00200000L
-#define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT_MASK 0x00800000L
-#define UVD_VCPU_INT_STATUS__IDCT_INT_MASK 0x01000000L
-#define UVD_VCPU_INT_STATUS__MPRD_INT_MASK 0x02000000L
-#define UVD_VCPU_INT_STATUS__AVM_INT_MASK 0x04000000L
-#define UVD_VCPU_INT_STATUS__CLK_SWT_INT_MASK 0x08000000L
-#define UVD_VCPU_INT_STATUS__MIF_HWINT_MASK 0x10000000L
-#define UVD_VCPU_INT_STATUS__MPRD_ERR_INT_MASK 0x20000000L
-#define UVD_VCPU_INT_STATUS__DRV_FW_REQ_INT_MASK 0x40000000L
-#define UVD_VCPU_INT_STATUS__DRV_FW_ACK_INT_MASK 0x80000000L
-//UVD_VCPU_INT_ACK
-#define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT 0x0
-#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT 0x1
-#define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT 0x2
-#define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK__SHIFT 0x3
-#define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK__SHIFT 0x4
-#define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK__SHIFT 0x5
-#define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT 0x6
-#define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK__SHIFT 0x7
-#define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK__SHIFT 0x9
-#define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK__SHIFT 0xa
-#define UVD_VCPU_INT_ACK__LBSI_ACK__SHIFT 0xb
-#define UVD_VCPU_INT_ACK__UDEC_ACK__SHIFT 0xc
-#define UVD_VCPU_INT_ACK__SUVD_ACK__SHIFT 0xf
-#define UVD_VCPU_INT_ACK__RPTR_WR_ACK__SHIFT 0x10
-#define UVD_VCPU_INT_ACK__JOB_START_ACK__SHIFT 0x11
-#define UVD_VCPU_INT_ACK__NJ_PF_ACK__SHIFT 0x12
-#define UVD_VCPU_INT_ACK__RASCNTL_VCPU_VCODEC_ACK__SHIFT 0x16
-#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT 0x17
-#define UVD_VCPU_INT_ACK__IDCT_ACK__SHIFT 0x18
-#define UVD_VCPU_INT_ACK__MPRD_ACK__SHIFT 0x19
-#define UVD_VCPU_INT_ACK__AVM_INT_ACK__SHIFT 0x1a
-#define UVD_VCPU_INT_ACK__CLK_SWT_ACK__SHIFT 0x1b
-#define UVD_VCPU_INT_ACK__MIF_HWINT_ACK__SHIFT 0x1c
-#define UVD_VCPU_INT_ACK__MPRD_ERR_ACK__SHIFT 0x1d
-#define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK__SHIFT 0x1e
-#define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK__SHIFT 0x1f
-#define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK_MASK 0x00000001L
-#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK 0x00000002L
-#define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK 0x00000004L
-#define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK_MASK 0x00000008L
-#define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK_MASK 0x00000010L
-#define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK_MASK 0x00000020L
-#define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK 0x00000040L
-#define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK_MASK 0x00000080L
-#define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK_MASK 0x00000200L
-#define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK_MASK 0x00000400L
-#define UVD_VCPU_INT_ACK__LBSI_ACK_MASK 0x00000800L
-#define UVD_VCPU_INT_ACK__UDEC_ACK_MASK 0x00001000L
-#define UVD_VCPU_INT_ACK__SUVD_ACK_MASK 0x00008000L
-#define UVD_VCPU_INT_ACK__RPTR_WR_ACK_MASK 0x00010000L
-#define UVD_VCPU_INT_ACK__JOB_START_ACK_MASK 0x00020000L
-#define UVD_VCPU_INT_ACK__NJ_PF_ACK_MASK 0x00040000L
-#define UVD_VCPU_INT_ACK__RASCNTL_VCPU_VCODEC_ACK_MASK 0x00400000L
-#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK 0x00800000L
-#define UVD_VCPU_INT_ACK__IDCT_ACK_MASK 0x01000000L
-#define UVD_VCPU_INT_ACK__MPRD_ACK_MASK 0x02000000L
-#define UVD_VCPU_INT_ACK__AVM_INT_ACK_MASK 0x04000000L
-#define UVD_VCPU_INT_ACK__CLK_SWT_ACK_MASK 0x08000000L
-#define UVD_VCPU_INT_ACK__MIF_HWINT_ACK_MASK 0x10000000L
-#define UVD_VCPU_INT_ACK__MPRD_ERR_ACK_MASK 0x20000000L
-#define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK_MASK 0x40000000L
-#define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK_MASK 0x80000000L
-//UVD_VCPU_INT_ROUTE
-#define UVD_VCPU_INT_ROUTE__DRV_FW_MSG__SHIFT 0x0
-#define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK__SHIFT 0x1
-#define UVD_VCPU_INT_ROUTE__VCPU_GPCOM__SHIFT 0x2
-#define UVD_VCPU_INT_ROUTE__DRV_FW_MSG_MASK 0x00000001L
-#define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK_MASK 0x00000002L
-#define UVD_VCPU_INT_ROUTE__VCPU_GPCOM_MASK 0x00000004L
-//UVD_DRV_FW_MSG
-#define UVD_DRV_FW_MSG__MSG__SHIFT 0x0
-#define UVD_DRV_FW_MSG__MSG_MASK 0xFFFFFFFFL
-//UVD_FW_DRV_MSG_ACK
-#define UVD_FW_DRV_MSG_ACK__ACK__SHIFT 0x0
-#define UVD_FW_DRV_MSG_ACK__ACK_MASK 0x00000001L
-//UVD_SUVD_INT_EN
-#define UVD_SUVD_INT_EN__SRE_FUNC_INT_EN__SHIFT 0x0
-#define UVD_SUVD_INT_EN__SRE_ERR_INT_EN__SHIFT 0x5
-#define UVD_SUVD_INT_EN__SIT_FUNC_INT_EN__SHIFT 0x6
-#define UVD_SUVD_INT_EN__SIT_ERR_INT_EN__SHIFT 0xb
-#define UVD_SUVD_INT_EN__SMP_FUNC_INT_EN__SHIFT 0xc
-#define UVD_SUVD_INT_EN__SMP_ERR_INT_EN__SHIFT 0x11
-#define UVD_SUVD_INT_EN__SCM_FUNC_INT_EN__SHIFT 0x12
-#define UVD_SUVD_INT_EN__SCM_ERR_INT_EN__SHIFT 0x17
-#define UVD_SUVD_INT_EN__SDB_FUNC_INT_EN__SHIFT 0x18
-#define UVD_SUVD_INT_EN__SDB_ERR_INT_EN__SHIFT 0x1d
-#define UVD_SUVD_INT_EN__SRE_FUNC_INT_EN_MASK 0x0000001FL
-#define UVD_SUVD_INT_EN__SRE_ERR_INT_EN_MASK 0x00000020L
-#define UVD_SUVD_INT_EN__SIT_FUNC_INT_EN_MASK 0x000007C0L
-#define UVD_SUVD_INT_EN__SIT_ERR_INT_EN_MASK 0x00000800L
-#define UVD_SUVD_INT_EN__SMP_FUNC_INT_EN_MASK 0x0001F000L
-#define UVD_SUVD_INT_EN__SMP_ERR_INT_EN_MASK 0x00020000L
-#define UVD_SUVD_INT_EN__SCM_FUNC_INT_EN_MASK 0x007C0000L
-#define UVD_SUVD_INT_EN__SCM_ERR_INT_EN_MASK 0x00800000L
-#define UVD_SUVD_INT_EN__SDB_FUNC_INT_EN_MASK 0x1F000000L
-#define UVD_SUVD_INT_EN__SDB_ERR_INT_EN_MASK 0x20000000L
-//UVD_SUVD_INT_STATUS
-#define UVD_SUVD_INT_STATUS__SRE_FUNC_INT__SHIFT 0x0
-#define UVD_SUVD_INT_STATUS__SRE_ERR_INT__SHIFT 0x5
-#define UVD_SUVD_INT_STATUS__SIT_FUNC_INT__SHIFT 0x6
-#define UVD_SUVD_INT_STATUS__SIT_ERR_INT__SHIFT 0xb
-#define UVD_SUVD_INT_STATUS__SMP_FUNC_INT__SHIFT 0xc
-#define UVD_SUVD_INT_STATUS__SMP_ERR_INT__SHIFT 0x11
-#define UVD_SUVD_INT_STATUS__SCM_FUNC_INT__SHIFT 0x12
-#define UVD_SUVD_INT_STATUS__SCM_ERR_INT__SHIFT 0x17
-#define UVD_SUVD_INT_STATUS__SDB_FUNC_INT__SHIFT 0x18
-#define UVD_SUVD_INT_STATUS__SDB_ERR_INT__SHIFT 0x1d
-#define UVD_SUVD_INT_STATUS__SRE_FUNC_INT_MASK 0x0000001FL
-#define UVD_SUVD_INT_STATUS__SRE_ERR_INT_MASK 0x00000020L
-#define UVD_SUVD_INT_STATUS__SIT_FUNC_INT_MASK 0x000007C0L
-#define UVD_SUVD_INT_STATUS__SIT_ERR_INT_MASK 0x00000800L
-#define UVD_SUVD_INT_STATUS__SMP_FUNC_INT_MASK 0x0001F000L
-#define UVD_SUVD_INT_STATUS__SMP_ERR_INT_MASK 0x00020000L
-#define UVD_SUVD_INT_STATUS__SCM_FUNC_INT_MASK 0x007C0000L
-#define UVD_SUVD_INT_STATUS__SCM_ERR_INT_MASK 0x00800000L
-#define UVD_SUVD_INT_STATUS__SDB_FUNC_INT_MASK 0x1F000000L
-#define UVD_SUVD_INT_STATUS__SDB_ERR_INT_MASK 0x20000000L
-//UVD_SUVD_INT_ACK
-#define UVD_SUVD_INT_ACK__SRE_FUNC_INT_ACK__SHIFT 0x0
-#define UVD_SUVD_INT_ACK__SRE_ERR_INT_ACK__SHIFT 0x5
-#define UVD_SUVD_INT_ACK__SIT_FUNC_INT_ACK__SHIFT 0x6
-#define UVD_SUVD_INT_ACK__SIT_ERR_INT_ACK__SHIFT 0xb
-#define UVD_SUVD_INT_ACK__SMP_FUNC_INT_ACK__SHIFT 0xc
-#define UVD_SUVD_INT_ACK__SMP_ERR_INT_ACK__SHIFT 0x11
-#define UVD_SUVD_INT_ACK__SCM_FUNC_INT_ACK__SHIFT 0x12
-#define UVD_SUVD_INT_ACK__SCM_ERR_INT_ACK__SHIFT 0x17
-#define UVD_SUVD_INT_ACK__SDB_FUNC_INT_ACK__SHIFT 0x18
-#define UVD_SUVD_INT_ACK__SDB_ERR_INT_ACK__SHIFT 0x1d
-#define UVD_SUVD_INT_ACK__SRE_FUNC_INT_ACK_MASK 0x0000001FL
-#define UVD_SUVD_INT_ACK__SRE_ERR_INT_ACK_MASK 0x00000020L
-#define UVD_SUVD_INT_ACK__SIT_FUNC_INT_ACK_MASK 0x000007C0L
-#define UVD_SUVD_INT_ACK__SIT_ERR_INT_ACK_MASK 0x00000800L
-#define UVD_SUVD_INT_ACK__SMP_FUNC_INT_ACK_MASK 0x0001F000L
-#define UVD_SUVD_INT_ACK__SMP_ERR_INT_ACK_MASK 0x00020000L
-#define UVD_SUVD_INT_ACK__SCM_FUNC_INT_ACK_MASK 0x007C0000L
-#define UVD_SUVD_INT_ACK__SCM_ERR_INT_ACK_MASK 0x00800000L
-#define UVD_SUVD_INT_ACK__SDB_FUNC_INT_ACK_MASK 0x1F000000L
-#define UVD_SUVD_INT_ACK__SDB_ERR_INT_ACK_MASK 0x20000000L
-//UVD_ENC_VCPU_INT_EN
-#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN__SHIFT 0x0
-#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN__SHIFT 0x1
-#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN__SHIFT 0x2
-#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN_MASK 0x00000001L
-#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN_MASK 0x00000002L
-#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN_MASK 0x00000004L
-//UVD_ENC_VCPU_INT_STATUS
-#define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR_INT__SHIFT 0x0
-#define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR2_INT__SHIFT 0x1
-#define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR3_INT__SHIFT 0x2
-#define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR_INT_MASK 0x00000001L
-#define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR2_INT_MASK 0x00000002L
-#define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR3_INT_MASK 0x00000004L
-//UVD_ENC_VCPU_INT_ACK
-#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK__SHIFT 0x0
-#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK__SHIFT 0x1
-#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK__SHIFT 0x2
-#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK_MASK 0x00000001L
-#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK_MASK 0x00000002L
-#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK_MASK 0x00000004L
-//UVD_MASTINT_EN
-#define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0
-#define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1
-#define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2
-#define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4
-#define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L
-#define UVD_MASTINT_EN__VCPU_EN_MASK 0x00000002L
-#define UVD_MASTINT_EN__SYS_EN_MASK 0x00000004L
-#define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x00FFFFF0L
-//UVD_SYS_INT_EN
-#define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN__SHIFT 0x0
-#define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT 0x1
-#define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT 0x2
-#define UVD_SYS_INT_EN__CXW_WR_EN__SHIFT 0x3
-#define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT 0x6
-#define UVD_SYS_INT_EN__LBSI_EN__SHIFT 0xb
-#define UVD_SYS_INT_EN__UDEC_EN__SHIFT 0xc
-#define UVD_SYS_INT_EN__SUVD_EN__SHIFT 0xf
-#define UVD_SYS_INT_EN__JOB_DONE_EN__SHIFT 0x10
-#define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT 0x17
-#define UVD_SYS_INT_EN__IDCT_EN__SHIFT 0x18
-#define UVD_SYS_INT_EN__MPRD_EN__SHIFT 0x19
-#define UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN__SHIFT 0x1a
-#define UVD_SYS_INT_EN__CLK_SWT_EN__SHIFT 0x1b
-#define UVD_SYS_INT_EN__MIF_HWINT_EN__SHIFT 0x1c
-#define UVD_SYS_INT_EN__MPRD_ERR_EN__SHIFT 0x1d
-#define UVD_SYS_INT_EN__AVM_INT_EN__SHIFT 0x1f
-#define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN_MASK 0x00000001L
-#define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK 0x00000002L
-#define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK 0x00000004L
-#define UVD_SYS_INT_EN__CXW_WR_EN_MASK 0x00000008L
-#define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK 0x00000040L
-#define UVD_SYS_INT_EN__LBSI_EN_MASK 0x00000800L
-#define UVD_SYS_INT_EN__UDEC_EN_MASK 0x00001000L
-#define UVD_SYS_INT_EN__SUVD_EN_MASK 0x00008000L
-#define UVD_SYS_INT_EN__JOB_DONE_EN_MASK 0x00010000L
-#define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK 0x00800000L
-#define UVD_SYS_INT_EN__IDCT_EN_MASK 0x01000000L
-#define UVD_SYS_INT_EN__MPRD_EN_MASK 0x02000000L
-#define UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK 0x04000000L
-#define UVD_SYS_INT_EN__CLK_SWT_EN_MASK 0x08000000L
-#define UVD_SYS_INT_EN__MIF_HWINT_EN_MASK 0x10000000L
-#define UVD_SYS_INT_EN__MPRD_ERR_EN_MASK 0x20000000L
-#define UVD_SYS_INT_EN__AVM_INT_EN_MASK 0x80000000L
-//UVD_SYS_INT_STATUS
-#define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT__SHIFT 0x0
-#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT__SHIFT 0x1
-#define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT__SHIFT 0x2
-#define UVD_SYS_INT_STATUS__CXW_WR_INT__SHIFT 0x3
-#define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT__SHIFT 0x6
-#define UVD_SYS_INT_STATUS__LBSI_INT__SHIFT 0xb
-#define UVD_SYS_INT_STATUS__UDEC_INT__SHIFT 0xc
-#define UVD_SYS_INT_STATUS__SUVD_INT__SHIFT 0xf
-#define UVD_SYS_INT_STATUS__JOB_DONE_INT__SHIFT 0x10
-#define UVD_SYS_INT_STATUS__GPCOM_INT__SHIFT 0x12
-#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT__SHIFT 0x17
-#define UVD_SYS_INT_STATUS__IDCT_INT__SHIFT 0x18
-#define UVD_SYS_INT_STATUS__MPRD_INT__SHIFT 0x19
-#define UVD_SYS_INT_STATUS__CLK_SWT_INT__SHIFT 0x1b
-#define UVD_SYS_INT_STATUS__MIF_HWINT__SHIFT 0x1c
-#define UVD_SYS_INT_STATUS__MPRD_ERR_INT__SHIFT 0x1d
-#define UVD_SYS_INT_STATUS__RASCNTL_VCPU_VCODEC_INT__SHIFT 0x1e
-#define UVD_SYS_INT_STATUS__AVM_INT__SHIFT 0x1f
-#define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT_MASK 0x00000001L
-#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT_MASK 0x00000002L
-#define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT_MASK 0x00000004L
-#define UVD_SYS_INT_STATUS__CXW_WR_INT_MASK 0x00000008L
-#define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT_MASK 0x00000040L
-#define UVD_SYS_INT_STATUS__LBSI_INT_MASK 0x00000800L
-#define UVD_SYS_INT_STATUS__UDEC_INT_MASK 0x00001000L
-#define UVD_SYS_INT_STATUS__SUVD_INT_MASK 0x00008000L
-#define UVD_SYS_INT_STATUS__JOB_DONE_INT_MASK 0x00010000L
-#define UVD_SYS_INT_STATUS__GPCOM_INT_MASK 0x00040000L
-#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT_MASK 0x00800000L
-#define UVD_SYS_INT_STATUS__IDCT_INT_MASK 0x01000000L
-#define UVD_SYS_INT_STATUS__MPRD_INT_MASK 0x02000000L
-#define UVD_SYS_INT_STATUS__CLK_SWT_INT_MASK 0x08000000L
-#define UVD_SYS_INT_STATUS__MIF_HWINT_MASK 0x10000000L
-#define UVD_SYS_INT_STATUS__MPRD_ERR_INT_MASK 0x20000000L
-#define UVD_SYS_INT_STATUS__RASCNTL_VCPU_VCODEC_INT_MASK 0x40000000L
-#define UVD_SYS_INT_STATUS__AVM_INT_MASK 0x80000000L
-//UVD_SYS_INT_ACK
-#define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT 0x0
-#define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT 0x1
-#define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT 0x2
-#define UVD_SYS_INT_ACK__CXW_WR_ACK__SHIFT 0x3
-#define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT 0x6
-#define UVD_SYS_INT_ACK__LBSI_ACK__SHIFT 0xb
-#define UVD_SYS_INT_ACK__UDEC_ACK__SHIFT 0xc
-#define UVD_SYS_INT_ACK__SUVD_ACK__SHIFT 0xf
-#define UVD_SYS_INT_ACK__JOB_DONE_ACK__SHIFT 0x10
-#define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT 0x17
-#define UVD_SYS_INT_ACK__IDCT_ACK__SHIFT 0x18
-#define UVD_SYS_INT_ACK__MPRD_ACK__SHIFT 0x19
-#define UVD_SYS_INT_ACK__CLK_SWT_ACK__SHIFT 0x1b
-#define UVD_SYS_INT_ACK__MIF_HWINT_ACK__SHIFT 0x1c
-#define UVD_SYS_INT_ACK__MPRD_ERR_ACK__SHIFT 0x1d
-#define UVD_SYS_INT_ACK__RASCNTL_VCPU_VCODEC_ACK__SHIFT 0x1e
-#define UVD_SYS_INT_ACK__AVM_INT_ACK__SHIFT 0x1f
-#define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK_MASK 0x00000001L
-#define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK 0x00000002L
-#define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK 0x00000004L
-#define UVD_SYS_INT_ACK__CXW_WR_ACK_MASK 0x00000008L
-#define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK 0x00000040L
-#define UVD_SYS_INT_ACK__LBSI_ACK_MASK 0x00000800L
-#define UVD_SYS_INT_ACK__UDEC_ACK_MASK 0x00001000L
-#define UVD_SYS_INT_ACK__SUVD_ACK_MASK 0x00008000L
-#define UVD_SYS_INT_ACK__JOB_DONE_ACK_MASK 0x00010000L
-#define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK 0x00800000L
-#define UVD_SYS_INT_ACK__IDCT_ACK_MASK 0x01000000L
-#define UVD_SYS_INT_ACK__MPRD_ACK_MASK 0x02000000L
-#define UVD_SYS_INT_ACK__CLK_SWT_ACK_MASK 0x08000000L
-#define UVD_SYS_INT_ACK__MIF_HWINT_ACK_MASK 0x10000000L
-#define UVD_SYS_INT_ACK__MPRD_ERR_ACK_MASK 0x20000000L
-#define UVD_SYS_INT_ACK__RASCNTL_VCPU_VCODEC_ACK_MASK 0x40000000L
-#define UVD_SYS_INT_ACK__AVM_INT_ACK_MASK 0x80000000L
-//UVD_JOB_DONE
-#define UVD_JOB_DONE__JOB_DONE__SHIFT 0x0
-#define UVD_JOB_DONE__JOB_DONE_MASK 0x00000003L
-//UVD_CBUF_ID
-#define UVD_CBUF_ID__CBUF_ID__SHIFT 0x0
-#define UVD_CBUF_ID__CBUF_ID_MASK 0xFFFFFFFFL
-//UVD_CONTEXT_ID
-#define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0
-#define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xFFFFFFFFL
-//UVD_CONTEXT_ID2
-#define UVD_CONTEXT_ID2__CONTEXT_ID2__SHIFT 0x0
-#define UVD_CONTEXT_ID2__CONTEXT_ID2_MASK 0xFFFFFFFFL
-//UVD_NO_OP
-#define UVD_NO_OP__NO_OP__SHIFT 0x0
-#define UVD_NO_OP__NO_OP_MASK 0xFFFFFFFFL
-//UVD_RB_BASE_LO
-#define UVD_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6
-#define UVD_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L
-//UVD_RB_BASE_HI
-#define UVD_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0
-#define UVD_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL
-//UVD_RB_SIZE
-#define UVD_RB_SIZE__RB_SIZE__SHIFT 0x4
-#define UVD_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L
-//UVD_RB_RPTR
-#define UVD_RB_RPTR__RB_RPTR__SHIFT 0x4
-#define UVD_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L
-//UVD_RB_WPTR
-#define UVD_RB_WPTR__RB_WPTR__SHIFT 0x4
-#define UVD_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L
-//UVD_RB_BASE_LO2
-#define UVD_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6
-#define UVD_RB_BASE_LO2__RB_BASE_LO_MASK 0xFFFFFFC0L
-//UVD_RB_BASE_HI2
-#define UVD_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0
-#define UVD_RB_BASE_HI2__RB_BASE_HI_MASK 0xFFFFFFFFL
-//UVD_RB_SIZE2
-#define UVD_RB_SIZE2__RB_SIZE__SHIFT 0x4
-#define UVD_RB_SIZE2__RB_SIZE_MASK 0x007FFFF0L
-//UVD_RB_RPTR2
-#define UVD_RB_RPTR2__RB_RPTR__SHIFT 0x4
-#define UVD_RB_RPTR2__RB_RPTR_MASK 0x007FFFF0L
-//UVD_RB_WPTR2
-#define UVD_RB_WPTR2__RB_WPTR__SHIFT 0x4
-#define UVD_RB_WPTR2__RB_WPTR_MASK 0x007FFFF0L
-//UVD_RB_BASE_LO3
-#define UVD_RB_BASE_LO3__RB_BASE_LO__SHIFT 0x6
-#define UVD_RB_BASE_LO3__RB_BASE_LO_MASK 0xFFFFFFC0L
-//UVD_RB_BASE_HI3
-#define UVD_RB_BASE_HI3__RB_BASE_HI__SHIFT 0x0
-#define UVD_RB_BASE_HI3__RB_BASE_HI_MASK 0xFFFFFFFFL
-//UVD_RB_SIZE3
-#define UVD_RB_SIZE3__RB_SIZE__SHIFT 0x4
-#define UVD_RB_SIZE3__RB_SIZE_MASK 0x007FFFF0L
-//UVD_RB_RPTR3
-#define UVD_RB_RPTR3__RB_RPTR__SHIFT 0x4
-#define UVD_RB_RPTR3__RB_RPTR_MASK 0x007FFFF0L
-//UVD_RB_WPTR3
-#define UVD_RB_WPTR3__RB_WPTR__SHIFT 0x4
-#define UVD_RB_WPTR3__RB_WPTR_MASK 0x007FFFF0L
-//UVD_RB_BASE_LO4
-#define UVD_RB_BASE_LO4__RB_BASE_LO__SHIFT 0x6
-#define UVD_RB_BASE_LO4__RB_BASE_LO_MASK 0xFFFFFFC0L
-//UVD_RB_BASE_HI4
-#define UVD_RB_BASE_HI4__RB_BASE_HI__SHIFT 0x0
-#define UVD_RB_BASE_HI4__RB_BASE_HI_MASK 0xFFFFFFFFL
-//UVD_RB_SIZE4
-#define UVD_RB_SIZE4__RB_SIZE__SHIFT 0x4
-#define UVD_RB_SIZE4__RB_SIZE_MASK 0x007FFFF0L
-//UVD_RB_RPTR4
-#define UVD_RB_RPTR4__RB_RPTR__SHIFT 0x4
-#define UVD_RB_RPTR4__RB_RPTR_MASK 0x007FFFF0L
-//UVD_RB_WPTR4
-#define UVD_RB_WPTR4__RB_WPTR__SHIFT 0x4
-#define UVD_RB_WPTR4__RB_WPTR_MASK 0x007FFFF0L
-//UVD_OUT_RB_BASE_LO
-#define UVD_OUT_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6
-#define UVD_OUT_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L
-//UVD_OUT_RB_BASE_HI
-#define UVD_OUT_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0
-#define UVD_OUT_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL
-//UVD_OUT_RB_SIZE
-#define UVD_OUT_RB_SIZE__RB_SIZE__SHIFT 0x4
-#define UVD_OUT_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L
-//UVD_OUT_RB_RPTR
-#define UVD_OUT_RB_RPTR__RB_RPTR__SHIFT 0x4
-#define UVD_OUT_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L
-//UVD_OUT_RB_WPTR
-#define UVD_OUT_RB_WPTR__RB_WPTR__SHIFT 0x4
-#define UVD_OUT_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L
-//UVD_IOV_MAILBOX
-#define UVD_IOV_MAILBOX__MAILBOX__SHIFT 0x0
-#define UVD_IOV_MAILBOX__MAILBOX_MASK 0xFFFFFFFFL
-//UVD_IOV_MAILBOX_RESP
-#define UVD_IOV_MAILBOX_RESP__RESP__SHIFT 0x0
-#define UVD_IOV_MAILBOX_RESP__RESP_MASK 0xFFFFFFFFL
-//UVD_RB_ARB_CTRL
-#define UVD_RB_ARB_CTRL__SRBM_DROP__SHIFT 0x0
-#define UVD_RB_ARB_CTRL__SRBM_DIS__SHIFT 0x1
-#define UVD_RB_ARB_CTRL__VCPU_DROP__SHIFT 0x2
-#define UVD_RB_ARB_CTRL__VCPU_DIS__SHIFT 0x3
-#define UVD_RB_ARB_CTRL__RBC_DROP__SHIFT 0x4
-#define UVD_RB_ARB_CTRL__RBC_DIS__SHIFT 0x5
-#define UVD_RB_ARB_CTRL__FWOFLD_DROP__SHIFT 0x6
-#define UVD_RB_ARB_CTRL__FWOFLD_DIS__SHIFT 0x7
-#define UVD_RB_ARB_CTRL__FAST_PATH_EN__SHIFT 0x8
-#define UVD_RB_ARB_CTRL__SRBM_DROP_MASK 0x00000001L
-#define UVD_RB_ARB_CTRL__SRBM_DIS_MASK 0x00000002L
-#define UVD_RB_ARB_CTRL__VCPU_DROP_MASK 0x00000004L
-#define UVD_RB_ARB_CTRL__VCPU_DIS_MASK 0x00000008L
-#define UVD_RB_ARB_CTRL__RBC_DROP_MASK 0x00000010L
-#define UVD_RB_ARB_CTRL__RBC_DIS_MASK 0x00000020L
-#define UVD_RB_ARB_CTRL__FWOFLD_DROP_MASK 0x00000040L
-#define UVD_RB_ARB_CTRL__FWOFLD_DIS_MASK 0x00000080L
-#define UVD_RB_ARB_CTRL__FAST_PATH_EN_MASK 0x00000100L
-//UVD_CTX_INDEX
-#define UVD_CTX_INDEX__INDEX__SHIFT 0x0
-#define UVD_CTX_INDEX__INDEX_MASK 0x000001FFL
-//UVD_CTX_DATA
-#define UVD_CTX_DATA__DATA__SHIFT 0x0
-#define UVD_CTX_DATA__DATA_MASK 0xFFFFFFFFL
-//UVD_CXW_WR
-#define UVD_CXW_WR__DAT__SHIFT 0x0
-#define UVD_CXW_WR__STAT__SHIFT 0x1f
-#define UVD_CXW_WR__DAT_MASK 0x0FFFFFFFL
-#define UVD_CXW_WR__STAT_MASK 0x80000000L
-//UVD_CXW_WR_INT_ID
-#define UVD_CXW_WR_INT_ID__ID__SHIFT 0x0
-#define UVD_CXW_WR_INT_ID__ID_MASK 0x000000FFL
-//UVD_CXW_WR_INT_CTX_ID
-#define UVD_CXW_WR_INT_CTX_ID__ID__SHIFT 0x0
-#define UVD_CXW_WR_INT_CTX_ID__ID_MASK 0x0FFFFFFFL
-//UVD_CXW_INT_ID
-#define UVD_CXW_INT_ID__ID__SHIFT 0x0
-#define UVD_CXW_INT_ID__ID_MASK 0x000000FFL
-//UVD_MPEG2_ERROR
-#define UVD_MPEG2_ERROR__STATUS__SHIFT 0x0
-#define UVD_MPEG2_ERROR__STATUS_MASK 0xFFFFFFFFL
-//UVD_TOP_CTRL
-#define UVD_TOP_CTRL__STANDARD__SHIFT 0x0
-#define UVD_TOP_CTRL__STD_VERSION__SHIFT 0x4
-#define UVD_TOP_CTRL__STANDARD_MASK 0x0000000FL
-#define UVD_TOP_CTRL__STD_VERSION_MASK 0x000000F0L
-//UVD_YBASE
-#define UVD_YBASE__DUM__SHIFT 0x0
-#define UVD_YBASE__DUM_MASK 0xFFFFFFFFL
-//UVD_UVBASE
-#define UVD_UVBASE__DUM__SHIFT 0x0
-#define UVD_UVBASE__DUM_MASK 0xFFFFFFFFL
-//UVD_PITCH
-#define UVD_PITCH__DUM__SHIFT 0x0
-#define UVD_PITCH__DUM_MASK 0xFFFFFFFFL
-//UVD_WIDTH
-#define UVD_WIDTH__DUM__SHIFT 0x0
-#define UVD_WIDTH__DUM_MASK 0xFFFFFFFFL
-//UVD_HEIGHT
-#define UVD_HEIGHT__DUM__SHIFT 0x0
-#define UVD_HEIGHT__DUM_MASK 0xFFFFFFFFL
-//UVD_PICCOUNT
-#define UVD_PICCOUNT__DUM__SHIFT 0x0
-#define UVD_PICCOUNT__DUM_MASK 0xFFFFFFFFL
-//UVD_MPRD_INITIAL_XY
-#define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_X__SHIFT 0x0
-#define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_Y__SHIFT 0x10
-#define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_X_MASK 0x00000FFFL
-#define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_Y_MASK 0x0FFF0000L
-//UVD_MPEG2_CTRL
-#define UVD_MPEG2_CTRL__EN__SHIFT 0x0
-#define UVD_MPEG2_CTRL__TRICK_MODE__SHIFT 0x1
-#define UVD_MPEG2_CTRL__NUM_MB_PER_JOB__SHIFT 0x10
-#define UVD_MPEG2_CTRL__EN_MASK 0x00000001L
-#define UVD_MPEG2_CTRL__TRICK_MODE_MASK 0x00000002L
-#define UVD_MPEG2_CTRL__NUM_MB_PER_JOB_MASK 0xFFFF0000L
-//UVD_MB_CTL_BUF_BASE
-#define UVD_MB_CTL_BUF_BASE__BASE__SHIFT 0x0
-#define UVD_MB_CTL_BUF_BASE__BASE_MASK 0xFFFFFFFFL
-//UVD_PIC_CTL_BUF_BASE
-#define UVD_PIC_CTL_BUF_BASE__BASE__SHIFT 0x0
-#define UVD_PIC_CTL_BUF_BASE__BASE_MASK 0xFFFFFFFFL
-//UVD_DXVA_BUF_SIZE
-#define UVD_DXVA_BUF_SIZE__PIC_SIZE__SHIFT 0x0
-#define UVD_DXVA_BUF_SIZE__MB_SIZE__SHIFT 0x10
-#define UVD_DXVA_BUF_SIZE__PIC_SIZE_MASK 0x0000FFFFL
-#define UVD_DXVA_BUF_SIZE__MB_SIZE_MASK 0xFFFF0000L
-//UVD_SCRATCH_NP
-#define UVD_SCRATCH_NP__DATA__SHIFT 0x0
-#define UVD_SCRATCH_NP__DATA_MASK 0xFFFFFFFFL
-//UVD_CLK_SWT_HANDSHAKE
-#define UVD_CLK_SWT_HANDSHAKE__CLK_SWT_TYPE__SHIFT 0x0
-#define UVD_CLK_SWT_HANDSHAKE__CLK_DOMAIN_SWT__SHIFT 0x8
-#define UVD_CLK_SWT_HANDSHAKE__CLK_SWT_TYPE_MASK 0x00000003L
-#define UVD_CLK_SWT_HANDSHAKE__CLK_DOMAIN_SWT_MASK 0x00000300L
-//UVD_VERSION
-#define UVD_VERSION__MINOR_VERSION__SHIFT 0x0
-#define UVD_VERSION__MAJOR_VERSION__SHIFT 0x10
-#define UVD_VERSION__INSTANCE_ID__SHIFT 0x1c
-#define UVD_VERSION__MINOR_VERSION_MASK 0x0000FFFFL
-#define UVD_VERSION__MAJOR_VERSION_MASK 0x0FFF0000L
-#define UVD_VERSION__INSTANCE_ID_MASK 0xF0000000L
-//UVD_GP_SCRATCH0
-#define UVD_GP_SCRATCH0__DATA__SHIFT 0x0
-#define UVD_GP_SCRATCH0__DATA_MASK 0xFFFFFFFFL
-//UVD_GP_SCRATCH1
-#define UVD_GP_SCRATCH1__DATA__SHIFT 0x0
-#define UVD_GP_SCRATCH1__DATA_MASK 0xFFFFFFFFL
-//UVD_GP_SCRATCH2
-#define UVD_GP_SCRATCH2__DATA__SHIFT 0x0
-#define UVD_GP_SCRATCH2__DATA_MASK 0xFFFFFFFFL
-//UVD_GP_SCRATCH3
-#define UVD_GP_SCRATCH3__DATA__SHIFT 0x0
-#define UVD_GP_SCRATCH3__DATA_MASK 0xFFFFFFFFL
-//UVD_GP_SCRATCH4
-#define UVD_GP_SCRATCH4__DATA__SHIFT 0x0
-#define UVD_GP_SCRATCH4__DATA_MASK 0xFFFFFFFFL
-//UVD_GP_SCRATCH5
-#define UVD_GP_SCRATCH5__DATA__SHIFT 0x0
-#define UVD_GP_SCRATCH5__DATA_MASK 0xFFFFFFFFL
-//UVD_GP_SCRATCH6
-#define UVD_GP_SCRATCH6__DATA__SHIFT 0x0
-#define UVD_GP_SCRATCH6__DATA_MASK 0xFFFFFFFFL
-//UVD_GP_SCRATCH7
-#define UVD_GP_SCRATCH7__DATA__SHIFT 0x0
-#define UVD_GP_SCRATCH7__DATA_MASK 0xFFFFFFFFL
-//UVD_GP_SCRATCH8
-#define UVD_GP_SCRATCH8__DATA__SHIFT 0x0
-#define UVD_GP_SCRATCH8__DATA_MASK 0xFFFFFFFFL
-//UVD_GP_SCRATCH9
-#define UVD_GP_SCRATCH9__DATA__SHIFT 0x0
-#define UVD_GP_SCRATCH9__DATA_MASK 0xFFFFFFFFL
-//UVD_GP_SCRATCH10
-#define UVD_GP_SCRATCH10__DATA__SHIFT 0x0
-#define UVD_GP_SCRATCH10__DATA_MASK 0xFFFFFFFFL
-//UVD_GP_SCRATCH11
-#define UVD_GP_SCRATCH11__DATA__SHIFT 0x0
-#define UVD_GP_SCRATCH11__DATA_MASK 0xFFFFFFFFL
-//UVD_GP_SCRATCH12
-#define UVD_GP_SCRATCH12__DATA__SHIFT 0x0
-#define UVD_GP_SCRATCH12__DATA_MASK 0xFFFFFFFFL
-//UVD_GP_SCRATCH13
-#define UVD_GP_SCRATCH13__DATA__SHIFT 0x0
-#define UVD_GP_SCRATCH13__DATA_MASK 0xFFFFFFFFL
-//UVD_GP_SCRATCH14
-#define UVD_GP_SCRATCH14__DATA__SHIFT 0x0
-#define UVD_GP_SCRATCH14__DATA_MASK 0xFFFFFFFFL
-//UVD_GP_SCRATCH15
-#define UVD_GP_SCRATCH15__DATA__SHIFT 0x0
-#define UVD_GP_SCRATCH15__DATA_MASK 0xFFFFFFFFL
-//UVD_GP_SCRATCH16
-#define UVD_GP_SCRATCH16__DATA__SHIFT 0x0
-#define UVD_GP_SCRATCH16__DATA_MASK 0xFFFFFFFFL
-//UVD_GP_SCRATCH17
-#define UVD_GP_SCRATCH17__DATA__SHIFT 0x0
-#define UVD_GP_SCRATCH17__DATA_MASK 0xFFFFFFFFL
-//UVD_GP_SCRATCH18
-#define UVD_GP_SCRATCH18__DATA__SHIFT 0x0
-#define UVD_GP_SCRATCH18__DATA_MASK 0xFFFFFFFFL
-//UVD_GP_SCRATCH19
-#define UVD_GP_SCRATCH19__DATA__SHIFT 0x0
-#define UVD_GP_SCRATCH19__DATA_MASK 0xFFFFFFFFL
-//UVD_GP_SCRATCH20
-#define UVD_GP_SCRATCH20__DATA__SHIFT 0x0
-#define UVD_GP_SCRATCH20__DATA_MASK 0xFFFFFFFFL
-//UVD_GP_SCRATCH21
-#define UVD_GP_SCRATCH21__DATA__SHIFT 0x0
-#define UVD_GP_SCRATCH21__DATA_MASK 0xFFFFFFFFL
-//UVD_GP_SCRATCH22
-#define UVD_GP_SCRATCH22__DATA__SHIFT 0x0
-#define UVD_GP_SCRATCH22__DATA_MASK 0xFFFFFFFFL
-//UVD_GP_SCRATCH23
-#define UVD_GP_SCRATCH23__DATA__SHIFT 0x0
-#define UVD_GP_SCRATCH23__DATA_MASK 0xFFFFFFFFL
-
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/beige_goby_ip_offset.h b/drivers/gpu/drm/amd/include/beige_goby_ip_offset.h
deleted file mode 100644
index 48542ea68..000000000
--- a/drivers/gpu/drm/amd/include/beige_goby_ip_offset.h
+++ /dev/null
@@ -1,1272 +0,0 @@
-/*
- * Copyright (C) 2020 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _beige_goby_ip_offset_HEADER
-#define _beige_goby_ip_offset_HEADER
-
-
-#define MAX_INSTANCE 7
-#define MAX_SEGMENT 6
-
-
-struct IP_BASE_INSTANCE {
- unsigned int segment[MAX_SEGMENT];
-};
-
-struct IP_BASE {
- struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
-};
-
-
-static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x02408C00, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } },
- { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } },
- { { 0x00017000, 0x02402000, 0, 0, 0, 0 } },
- { { 0x00017200, 0x02402400, 0, 0, 0, 0 } },
- { { 0x0001B000, 0x0242D800, 0, 0, 0, 0 } },
- { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0 } },
- { { 0x00017E00, 0x0240BC00, 0, 0, 0, 0 } } } };
-static const struct IP_BASE DBGU_IO0_BASE = { { { { 0x000001E0, 0x0240B400, 0, 0, 0, 0 } },
- { { 0x00000260, 0x02413C00, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE DIO_BASE = { { { { 0x02404000, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE DPCS_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE GC_BASE = { { { { 0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE HDA_BASE = { { { { 0x004C0000, 0x02404800, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0x02408800, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE PCIE0_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x00440000, 0x02401000, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x02425800, 0, 0, 0, 0 } },
- { { 0x00054000, 0x02425C00, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE VCN0_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0, 0 } } } };
-
-
-#define ATHUB_BASE__INST0_SEG0 0x00000C00
-#define ATHUB_BASE__INST0_SEG1 0x02408C00
-#define ATHUB_BASE__INST0_SEG2 0
-#define ATHUB_BASE__INST0_SEG3 0
-#define ATHUB_BASE__INST0_SEG4 0
-#define ATHUB_BASE__INST0_SEG5 0
-
-#define ATHUB_BASE__INST1_SEG0 0
-#define ATHUB_BASE__INST1_SEG1 0
-#define ATHUB_BASE__INST1_SEG2 0
-#define ATHUB_BASE__INST1_SEG3 0
-#define ATHUB_BASE__INST1_SEG4 0
-#define ATHUB_BASE__INST1_SEG5 0
-
-#define ATHUB_BASE__INST2_SEG0 0
-#define ATHUB_BASE__INST2_SEG1 0
-#define ATHUB_BASE__INST2_SEG2 0
-#define ATHUB_BASE__INST2_SEG3 0
-#define ATHUB_BASE__INST2_SEG4 0
-#define ATHUB_BASE__INST2_SEG5 0
-
-#define ATHUB_BASE__INST3_SEG0 0
-#define ATHUB_BASE__INST3_SEG1 0
-#define ATHUB_BASE__INST3_SEG2 0
-#define ATHUB_BASE__INST3_SEG3 0
-#define ATHUB_BASE__INST3_SEG4 0
-#define ATHUB_BASE__INST3_SEG5 0
-
-#define ATHUB_BASE__INST4_SEG0 0
-#define ATHUB_BASE__INST4_SEG1 0
-#define ATHUB_BASE__INST4_SEG2 0
-#define ATHUB_BASE__INST4_SEG3 0
-#define ATHUB_BASE__INST4_SEG4 0
-#define ATHUB_BASE__INST4_SEG5 0
-
-#define ATHUB_BASE__INST5_SEG0 0
-#define ATHUB_BASE__INST5_SEG1 0
-#define ATHUB_BASE__INST5_SEG2 0
-#define ATHUB_BASE__INST5_SEG3 0
-#define ATHUB_BASE__INST5_SEG4 0
-#define ATHUB_BASE__INST5_SEG5 0
-
-#define ATHUB_BASE__INST6_SEG0 0
-#define ATHUB_BASE__INST6_SEG1 0
-#define ATHUB_BASE__INST6_SEG2 0
-#define ATHUB_BASE__INST6_SEG3 0
-#define ATHUB_BASE__INST6_SEG4 0
-#define ATHUB_BASE__INST6_SEG5 0
-
-#define CLK_BASE__INST0_SEG0 0x00016C00
-#define CLK_BASE__INST0_SEG1 0x02401800
-#define CLK_BASE__INST0_SEG2 0
-#define CLK_BASE__INST0_SEG3 0
-#define CLK_BASE__INST0_SEG4 0
-#define CLK_BASE__INST0_SEG5 0
-
-#define CLK_BASE__INST1_SEG0 0x00016E00
-#define CLK_BASE__INST1_SEG1 0x02401C00
-#define CLK_BASE__INST1_SEG2 0
-#define CLK_BASE__INST1_SEG3 0
-#define CLK_BASE__INST1_SEG4 0
-#define CLK_BASE__INST1_SEG5 0
-
-#define CLK_BASE__INST2_SEG0 0x00017000
-#define CLK_BASE__INST2_SEG1 0x02402000
-#define CLK_BASE__INST2_SEG2 0
-#define CLK_BASE__INST2_SEG3 0
-#define CLK_BASE__INST2_SEG4 0
-#define CLK_BASE__INST2_SEG5 0
-
-#define CLK_BASE__INST3_SEG0 0x00017200
-#define CLK_BASE__INST3_SEG1 0x02402400
-#define CLK_BASE__INST3_SEG2 0
-#define CLK_BASE__INST3_SEG3 0
-#define CLK_BASE__INST3_SEG4 0
-#define CLK_BASE__INST3_SEG5 0
-
-#define CLK_BASE__INST4_SEG0 0x0001B000
-#define CLK_BASE__INST4_SEG1 0x0242D800
-#define CLK_BASE__INST4_SEG2 0
-#define CLK_BASE__INST4_SEG3 0
-#define CLK_BASE__INST4_SEG4 0
-#define CLK_BASE__INST4_SEG5 0
-
-#define CLK_BASE__INST5_SEG0 0x0001B200
-#define CLK_BASE__INST5_SEG1 0x0242DC00
-#define CLK_BASE__INST5_SEG2 0
-#define CLK_BASE__INST5_SEG3 0
-#define CLK_BASE__INST5_SEG4 0
-#define CLK_BASE__INST5_SEG5 0
-
-#define CLK_BASE__INST6_SEG0 0x00017E00
-#define CLK_BASE__INST6_SEG1 0x0240BC00
-#define CLK_BASE__INST6_SEG2 0
-#define CLK_BASE__INST6_SEG3 0
-#define CLK_BASE__INST6_SEG4 0
-#define CLK_BASE__INST6_SEG5 0
-
-#define DBGU_IO0_BASE__INST0_SEG0 0x000001E0
-#define DBGU_IO0_BASE__INST0_SEG1 0x0240B400
-#define DBGU_IO0_BASE__INST0_SEG2 0
-#define DBGU_IO0_BASE__INST0_SEG3 0
-#define DBGU_IO0_BASE__INST0_SEG4 0
-#define DBGU_IO0_BASE__INST0_SEG5 0
-
-#define DBGU_IO0_BASE__INST1_SEG0 0x00000260
-#define DBGU_IO0_BASE__INST1_SEG1 0x02413C00
-#define DBGU_IO0_BASE__INST1_SEG2 0
-#define DBGU_IO0_BASE__INST1_SEG3 0
-#define DBGU_IO0_BASE__INST1_SEG4 0
-#define DBGU_IO0_BASE__INST1_SEG5 0
-
-#define DBGU_IO0_BASE__INST2_SEG0 0
-#define DBGU_IO0_BASE__INST2_SEG1 0
-#define DBGU_IO0_BASE__INST2_SEG2 0
-#define DBGU_IO0_BASE__INST2_SEG3 0
-#define DBGU_IO0_BASE__INST2_SEG4 0
-#define DBGU_IO0_BASE__INST2_SEG5 0
-
-#define DBGU_IO0_BASE__INST3_SEG0 0
-#define DBGU_IO0_BASE__INST3_SEG1 0
-#define DBGU_IO0_BASE__INST3_SEG2 0
-#define DBGU_IO0_BASE__INST3_SEG3 0
-#define DBGU_IO0_BASE__INST3_SEG4 0
-#define DBGU_IO0_BASE__INST3_SEG5 0
-
-#define DBGU_IO0_BASE__INST4_SEG0 0
-#define DBGU_IO0_BASE__INST4_SEG1 0
-#define DBGU_IO0_BASE__INST4_SEG2 0
-#define DBGU_IO0_BASE__INST4_SEG3 0
-#define DBGU_IO0_BASE__INST4_SEG4 0
-#define DBGU_IO0_BASE__INST4_SEG5 0
-
-#define DBGU_IO0_BASE__INST5_SEG0 0
-#define DBGU_IO0_BASE__INST5_SEG1 0
-#define DBGU_IO0_BASE__INST5_SEG2 0
-#define DBGU_IO0_BASE__INST5_SEG3 0
-#define DBGU_IO0_BASE__INST5_SEG4 0
-#define DBGU_IO0_BASE__INST5_SEG5 0
-
-#define DBGU_IO0_BASE__INST6_SEG0 0
-#define DBGU_IO0_BASE__INST6_SEG1 0
-#define DBGU_IO0_BASE__INST6_SEG2 0
-#define DBGU_IO0_BASE__INST6_SEG3 0
-#define DBGU_IO0_BASE__INST6_SEG4 0
-#define DBGU_IO0_BASE__INST6_SEG5 0
-
-#define DF_BASE__INST0_SEG0 0x00007000
-#define DF_BASE__INST0_SEG1 0x0240B800
-#define DF_BASE__INST0_SEG2 0
-#define DF_BASE__INST0_SEG3 0
-#define DF_BASE__INST0_SEG4 0
-#define DF_BASE__INST0_SEG5 0
-
-#define DF_BASE__INST1_SEG0 0
-#define DF_BASE__INST1_SEG1 0
-#define DF_BASE__INST1_SEG2 0
-#define DF_BASE__INST1_SEG3 0
-#define DF_BASE__INST1_SEG4 0
-#define DF_BASE__INST1_SEG5 0
-
-#define DF_BASE__INST2_SEG0 0
-#define DF_BASE__INST2_SEG1 0
-#define DF_BASE__INST2_SEG2 0
-#define DF_BASE__INST2_SEG3 0
-#define DF_BASE__INST2_SEG4 0
-#define DF_BASE__INST2_SEG5 0
-
-#define DF_BASE__INST3_SEG0 0
-#define DF_BASE__INST3_SEG1 0
-#define DF_BASE__INST3_SEG2 0
-#define DF_BASE__INST3_SEG3 0
-#define DF_BASE__INST3_SEG4 0
-#define DF_BASE__INST3_SEG5 0
-
-#define DF_BASE__INST4_SEG0 0
-#define DF_BASE__INST4_SEG1 0
-#define DF_BASE__INST4_SEG2 0
-#define DF_BASE__INST4_SEG3 0
-#define DF_BASE__INST4_SEG4 0
-#define DF_BASE__INST4_SEG5 0
-
-#define DF_BASE__INST5_SEG0 0
-#define DF_BASE__INST5_SEG1 0
-#define DF_BASE__INST5_SEG2 0
-#define DF_BASE__INST5_SEG3 0
-#define DF_BASE__INST5_SEG4 0
-#define DF_BASE__INST5_SEG5 0
-
-#define DF_BASE__INST6_SEG0 0
-#define DF_BASE__INST6_SEG1 0
-#define DF_BASE__INST6_SEG2 0
-#define DF_BASE__INST6_SEG3 0
-#define DF_BASE__INST6_SEG4 0
-#define DF_BASE__INST6_SEG5 0
-
-#define DIO_BASE__INST0_SEG0 0x02404000
-#define DIO_BASE__INST0_SEG1 0
-#define DIO_BASE__INST0_SEG2 0
-#define DIO_BASE__INST0_SEG3 0
-#define DIO_BASE__INST0_SEG4 0
-#define DIO_BASE__INST0_SEG5 0
-
-#define DIO_BASE__INST1_SEG0 0
-#define DIO_BASE__INST1_SEG1 0
-#define DIO_BASE__INST1_SEG2 0
-#define DIO_BASE__INST1_SEG3 0
-#define DIO_BASE__INST1_SEG4 0
-#define DIO_BASE__INST1_SEG5 0
-
-#define DIO_BASE__INST2_SEG0 0
-#define DIO_BASE__INST2_SEG1 0
-#define DIO_BASE__INST2_SEG2 0
-#define DIO_BASE__INST2_SEG3 0
-#define DIO_BASE__INST2_SEG4 0
-#define DIO_BASE__INST2_SEG5 0
-
-#define DIO_BASE__INST3_SEG0 0
-#define DIO_BASE__INST3_SEG1 0
-#define DIO_BASE__INST3_SEG2 0
-#define DIO_BASE__INST3_SEG3 0
-#define DIO_BASE__INST3_SEG4 0
-#define DIO_BASE__INST3_SEG5 0
-
-#define DIO_BASE__INST4_SEG0 0
-#define DIO_BASE__INST4_SEG1 0
-#define DIO_BASE__INST4_SEG2 0
-#define DIO_BASE__INST4_SEG3 0
-#define DIO_BASE__INST4_SEG4 0
-#define DIO_BASE__INST4_SEG5 0
-
-#define DIO_BASE__INST5_SEG0 0
-#define DIO_BASE__INST5_SEG1 0
-#define DIO_BASE__INST5_SEG2 0
-#define DIO_BASE__INST5_SEG3 0
-#define DIO_BASE__INST5_SEG4 0
-#define DIO_BASE__INST5_SEG5 0
-
-#define DIO_BASE__INST6_SEG0 0
-#define DIO_BASE__INST6_SEG1 0
-#define DIO_BASE__INST6_SEG2 0
-#define DIO_BASE__INST6_SEG3 0
-#define DIO_BASE__INST6_SEG4 0
-#define DIO_BASE__INST6_SEG5 0
-
-#define DCN_BASE__INST0_SEG0 0x00000012
-#define DCN_BASE__INST0_SEG1 0x000000C0
-#define DCN_BASE__INST0_SEG2 0x000034C0
-#define DCN_BASE__INST0_SEG3 0x00009000
-#define DCN_BASE__INST0_SEG4 0x02403C00
-#define DCN_BASE__INST0_SEG5 0
-
-#define DCN_BASE__INST1_SEG0 0
-#define DCN_BASE__INST1_SEG1 0
-#define DCN_BASE__INST1_SEG2 0
-#define DCN_BASE__INST1_SEG3 0
-#define DCN_BASE__INST1_SEG4 0
-#define DCN_BASE__INST1_SEG5 0
-
-#define DCN_BASE__INST2_SEG0 0
-#define DCN_BASE__INST2_SEG1 0
-#define DCN_BASE__INST2_SEG2 0
-#define DCN_BASE__INST2_SEG3 0
-#define DCN_BASE__INST2_SEG4 0
-#define DCN_BASE__INST2_SEG5 0
-
-#define DCN_BASE__INST3_SEG0 0
-#define DCN_BASE__INST3_SEG1 0
-#define DCN_BASE__INST3_SEG2 0
-#define DCN_BASE__INST3_SEG3 0
-#define DCN_BASE__INST3_SEG4 0
-#define DCN_BASE__INST3_SEG5 0
-
-#define DCN_BASE__INST4_SEG0 0
-#define DCN_BASE__INST4_SEG1 0
-#define DCN_BASE__INST4_SEG2 0
-#define DCN_BASE__INST4_SEG3 0
-#define DCN_BASE__INST4_SEG4 0
-#define DCN_BASE__INST4_SEG5 0
-
-#define DCN_BASE__INST5_SEG0 0
-#define DCN_BASE__INST5_SEG1 0
-#define DCN_BASE__INST5_SEG2 0
-#define DCN_BASE__INST5_SEG3 0
-#define DCN_BASE__INST5_SEG4 0
-#define DCN_BASE__INST5_SEG5 0
-
-#define DCN_BASE__INST6_SEG0 0
-#define DCN_BASE__INST6_SEG1 0
-#define DCN_BASE__INST6_SEG2 0
-#define DCN_BASE__INST6_SEG3 0
-#define DCN_BASE__INST6_SEG4 0
-#define DCN_BASE__INST6_SEG5 0
-
-#define DPCS_BASE__INST0_SEG0 0x00000012
-#define DPCS_BASE__INST0_SEG1 0x000000C0
-#define DPCS_BASE__INST0_SEG2 0x000034C0
-#define DPCS_BASE__INST0_SEG3 0x00009000
-#define DPCS_BASE__INST0_SEG4 0x02403C00
-#define DPCS_BASE__INST0_SEG5 0
-
-#define DPCS_BASE__INST1_SEG0 0
-#define DPCS_BASE__INST1_SEG1 0
-#define DPCS_BASE__INST1_SEG2 0
-#define DPCS_BASE__INST1_SEG3 0
-#define DPCS_BASE__INST1_SEG4 0
-#define DPCS_BASE__INST1_SEG5 0
-
-#define DPCS_BASE__INST2_SEG0 0
-#define DPCS_BASE__INST2_SEG1 0
-#define DPCS_BASE__INST2_SEG2 0
-#define DPCS_BASE__INST2_SEG3 0
-#define DPCS_BASE__INST2_SEG4 0
-#define DPCS_BASE__INST2_SEG5 0
-
-#define DPCS_BASE__INST3_SEG0 0
-#define DPCS_BASE__INST3_SEG1 0
-#define DPCS_BASE__INST3_SEG2 0
-#define DPCS_BASE__INST3_SEG3 0
-#define DPCS_BASE__INST3_SEG4 0
-#define DPCS_BASE__INST3_SEG5 0
-
-#define DPCS_BASE__INST4_SEG0 0
-#define DPCS_BASE__INST4_SEG1 0
-#define DPCS_BASE__INST4_SEG2 0
-#define DPCS_BASE__INST4_SEG3 0
-#define DPCS_BASE__INST4_SEG4 0
-#define DPCS_BASE__INST4_SEG5 0
-
-#define DPCS_BASE__INST5_SEG0 0
-#define DPCS_BASE__INST5_SEG1 0
-#define DPCS_BASE__INST5_SEG2 0
-#define DPCS_BASE__INST5_SEG3 0
-#define DPCS_BASE__INST5_SEG4 0
-#define DPCS_BASE__INST5_SEG5 0
-
-#define DPCS_BASE__INST6_SEG0 0
-#define DPCS_BASE__INST6_SEG1 0
-#define DPCS_BASE__INST6_SEG2 0
-#define DPCS_BASE__INST6_SEG3 0
-#define DPCS_BASE__INST6_SEG4 0
-#define DPCS_BASE__INST6_SEG5 0
-
-#define FUSE_BASE__INST0_SEG0 0x00017400
-#define FUSE_BASE__INST0_SEG1 0x02401400
-#define FUSE_BASE__INST0_SEG2 0
-#define FUSE_BASE__INST0_SEG3 0
-#define FUSE_BASE__INST0_SEG4 0
-#define FUSE_BASE__INST0_SEG5 0
-
-#define FUSE_BASE__INST1_SEG0 0
-#define FUSE_BASE__INST1_SEG1 0
-#define FUSE_BASE__INST1_SEG2 0
-#define FUSE_BASE__INST1_SEG3 0
-#define FUSE_BASE__INST1_SEG4 0
-#define FUSE_BASE__INST1_SEG5 0
-
-#define FUSE_BASE__INST2_SEG0 0
-#define FUSE_BASE__INST2_SEG1 0
-#define FUSE_BASE__INST2_SEG2 0
-#define FUSE_BASE__INST2_SEG3 0
-#define FUSE_BASE__INST2_SEG4 0
-#define FUSE_BASE__INST2_SEG5 0
-
-#define FUSE_BASE__INST3_SEG0 0
-#define FUSE_BASE__INST3_SEG1 0
-#define FUSE_BASE__INST3_SEG2 0
-#define FUSE_BASE__INST3_SEG3 0
-#define FUSE_BASE__INST3_SEG4 0
-#define FUSE_BASE__INST3_SEG5 0
-
-#define FUSE_BASE__INST4_SEG0 0
-#define FUSE_BASE__INST4_SEG1 0
-#define FUSE_BASE__INST4_SEG2 0
-#define FUSE_BASE__INST4_SEG3 0
-#define FUSE_BASE__INST4_SEG4 0
-#define FUSE_BASE__INST4_SEG5 0
-
-#define FUSE_BASE__INST5_SEG0 0
-#define FUSE_BASE__INST5_SEG1 0
-#define FUSE_BASE__INST5_SEG2 0
-#define FUSE_BASE__INST5_SEG3 0
-#define FUSE_BASE__INST5_SEG4 0
-#define FUSE_BASE__INST5_SEG5 0
-
-#define FUSE_BASE__INST6_SEG0 0
-#define FUSE_BASE__INST6_SEG1 0
-#define FUSE_BASE__INST6_SEG2 0
-#define FUSE_BASE__INST6_SEG3 0
-#define FUSE_BASE__INST6_SEG4 0
-#define FUSE_BASE__INST6_SEG5 0
-
-#define GC_BASE__INST0_SEG0 0x00001260
-#define GC_BASE__INST0_SEG1 0x0000A000
-#define GC_BASE__INST0_SEG2 0x0001C000
-#define GC_BASE__INST0_SEG3 0x02402C00
-#define GC_BASE__INST0_SEG4 0
-#define GC_BASE__INST0_SEG5 0
-
-#define GC_BASE__INST1_SEG0 0
-#define GC_BASE__INST1_SEG1 0
-#define GC_BASE__INST1_SEG2 0
-#define GC_BASE__INST1_SEG3 0
-#define GC_BASE__INST1_SEG4 0
-#define GC_BASE__INST1_SEG5 0
-
-#define GC_BASE__INST2_SEG0 0
-#define GC_BASE__INST2_SEG1 0
-#define GC_BASE__INST2_SEG2 0
-#define GC_BASE__INST2_SEG3 0
-#define GC_BASE__INST2_SEG4 0
-#define GC_BASE__INST2_SEG5 0
-
-#define GC_BASE__INST3_SEG0 0
-#define GC_BASE__INST3_SEG1 0
-#define GC_BASE__INST3_SEG2 0
-#define GC_BASE__INST3_SEG3 0
-#define GC_BASE__INST3_SEG4 0
-#define GC_BASE__INST3_SEG5 0
-
-#define GC_BASE__INST4_SEG0 0
-#define GC_BASE__INST4_SEG1 0
-#define GC_BASE__INST4_SEG2 0
-#define GC_BASE__INST4_SEG3 0
-#define GC_BASE__INST4_SEG4 0
-#define GC_BASE__INST4_SEG5 0
-
-#define GC_BASE__INST5_SEG0 0
-#define GC_BASE__INST5_SEG1 0
-#define GC_BASE__INST5_SEG2 0
-#define GC_BASE__INST5_SEG3 0
-#define GC_BASE__INST5_SEG4 0
-#define GC_BASE__INST5_SEG5 0
-
-#define GC_BASE__INST6_SEG0 0
-#define GC_BASE__INST6_SEG1 0
-#define GC_BASE__INST6_SEG2 0
-#define GC_BASE__INST6_SEG3 0
-#define GC_BASE__INST6_SEG4 0
-#define GC_BASE__INST6_SEG5 0
-
-#define HDA_BASE__INST0_SEG0 0x004C0000
-#define HDA_BASE__INST0_SEG1 0x02404800
-#define HDA_BASE__INST0_SEG2 0
-#define HDA_BASE__INST0_SEG3 0
-#define HDA_BASE__INST0_SEG4 0
-#define HDA_BASE__INST0_SEG5 0
-
-#define HDA_BASE__INST1_SEG0 0
-#define HDA_BASE__INST1_SEG1 0
-#define HDA_BASE__INST1_SEG2 0
-#define HDA_BASE__INST1_SEG3 0
-#define HDA_BASE__INST1_SEG4 0
-#define HDA_BASE__INST1_SEG5 0
-
-#define HDA_BASE__INST2_SEG0 0
-#define HDA_BASE__INST2_SEG1 0
-#define HDA_BASE__INST2_SEG2 0
-#define HDA_BASE__INST2_SEG3 0
-#define HDA_BASE__INST2_SEG4 0
-#define HDA_BASE__INST2_SEG5 0
-
-#define HDA_BASE__INST3_SEG0 0
-#define HDA_BASE__INST3_SEG1 0
-#define HDA_BASE__INST3_SEG2 0
-#define HDA_BASE__INST3_SEG3 0
-#define HDA_BASE__INST3_SEG4 0
-#define HDA_BASE__INST3_SEG5 0
-
-#define HDA_BASE__INST4_SEG0 0
-#define HDA_BASE__INST4_SEG1 0
-#define HDA_BASE__INST4_SEG2 0
-#define HDA_BASE__INST4_SEG3 0
-#define HDA_BASE__INST4_SEG4 0
-#define HDA_BASE__INST4_SEG5 0
-
-#define HDA_BASE__INST5_SEG0 0
-#define HDA_BASE__INST5_SEG1 0
-#define HDA_BASE__INST5_SEG2 0
-#define HDA_BASE__INST5_SEG3 0
-#define HDA_BASE__INST5_SEG4 0
-#define HDA_BASE__INST5_SEG5 0
-
-#define HDA_BASE__INST6_SEG0 0
-#define HDA_BASE__INST6_SEG1 0
-#define HDA_BASE__INST6_SEG2 0
-#define HDA_BASE__INST6_SEG3 0
-#define HDA_BASE__INST6_SEG4 0
-#define HDA_BASE__INST6_SEG5 0
-
-#define HDP_BASE__INST0_SEG0 0x00000F20
-#define HDP_BASE__INST0_SEG1 0x0240A400
-#define HDP_BASE__INST0_SEG2 0
-#define HDP_BASE__INST0_SEG3 0
-#define HDP_BASE__INST0_SEG4 0
-#define HDP_BASE__INST0_SEG5 0
-
-#define HDP_BASE__INST1_SEG0 0
-#define HDP_BASE__INST1_SEG1 0
-#define HDP_BASE__INST1_SEG2 0
-#define HDP_BASE__INST1_SEG3 0
-#define HDP_BASE__INST1_SEG4 0
-#define HDP_BASE__INST1_SEG5 0
-
-#define HDP_BASE__INST2_SEG0 0
-#define HDP_BASE__INST2_SEG1 0
-#define HDP_BASE__INST2_SEG2 0
-#define HDP_BASE__INST2_SEG3 0
-#define HDP_BASE__INST2_SEG4 0
-#define HDP_BASE__INST2_SEG5 0
-
-#define HDP_BASE__INST3_SEG0 0
-#define HDP_BASE__INST3_SEG1 0
-#define HDP_BASE__INST3_SEG2 0
-#define HDP_BASE__INST3_SEG3 0
-#define HDP_BASE__INST3_SEG4 0
-#define HDP_BASE__INST3_SEG5 0
-
-#define HDP_BASE__INST4_SEG0 0
-#define HDP_BASE__INST4_SEG1 0
-#define HDP_BASE__INST4_SEG2 0
-#define HDP_BASE__INST4_SEG3 0
-#define HDP_BASE__INST4_SEG4 0
-#define HDP_BASE__INST4_SEG5 0
-
-#define HDP_BASE__INST5_SEG0 0
-#define HDP_BASE__INST5_SEG1 0
-#define HDP_BASE__INST5_SEG2 0
-#define HDP_BASE__INST5_SEG3 0
-#define HDP_BASE__INST5_SEG4 0
-#define HDP_BASE__INST5_SEG5 0
-
-#define HDP_BASE__INST6_SEG0 0
-#define HDP_BASE__INST6_SEG1 0
-#define HDP_BASE__INST6_SEG2 0
-#define HDP_BASE__INST6_SEG3 0
-#define HDP_BASE__INST6_SEG4 0
-#define HDP_BASE__INST6_SEG5 0
-
-#define MMHUB_BASE__INST0_SEG0 0x0001A000
-#define MMHUB_BASE__INST0_SEG1 0x02408800
-#define MMHUB_BASE__INST0_SEG2 0
-#define MMHUB_BASE__INST0_SEG3 0
-#define MMHUB_BASE__INST0_SEG4 0
-#define MMHUB_BASE__INST0_SEG5 0
-
-#define MMHUB_BASE__INST1_SEG0 0
-#define MMHUB_BASE__INST1_SEG1 0
-#define MMHUB_BASE__INST1_SEG2 0
-#define MMHUB_BASE__INST1_SEG3 0
-#define MMHUB_BASE__INST1_SEG4 0
-#define MMHUB_BASE__INST1_SEG5 0
-
-#define MMHUB_BASE__INST2_SEG0 0
-#define MMHUB_BASE__INST2_SEG1 0
-#define MMHUB_BASE__INST2_SEG2 0
-#define MMHUB_BASE__INST2_SEG3 0
-#define MMHUB_BASE__INST2_SEG4 0
-#define MMHUB_BASE__INST2_SEG5 0
-
-#define MMHUB_BASE__INST3_SEG0 0
-#define MMHUB_BASE__INST3_SEG1 0
-#define MMHUB_BASE__INST3_SEG2 0
-#define MMHUB_BASE__INST3_SEG3 0
-#define MMHUB_BASE__INST3_SEG4 0
-#define MMHUB_BASE__INST3_SEG5 0
-
-#define MMHUB_BASE__INST4_SEG0 0
-#define MMHUB_BASE__INST4_SEG1 0
-#define MMHUB_BASE__INST4_SEG2 0
-#define MMHUB_BASE__INST4_SEG3 0
-#define MMHUB_BASE__INST4_SEG4 0
-#define MMHUB_BASE__INST4_SEG5 0
-
-#define MMHUB_BASE__INST5_SEG0 0
-#define MMHUB_BASE__INST5_SEG1 0
-#define MMHUB_BASE__INST5_SEG2 0
-#define MMHUB_BASE__INST5_SEG3 0
-#define MMHUB_BASE__INST5_SEG4 0
-#define MMHUB_BASE__INST5_SEG5 0
-
-#define MMHUB_BASE__INST6_SEG0 0
-#define MMHUB_BASE__INST6_SEG1 0
-#define MMHUB_BASE__INST6_SEG2 0
-#define MMHUB_BASE__INST6_SEG3 0
-#define MMHUB_BASE__INST6_SEG4 0
-#define MMHUB_BASE__INST6_SEG5 0
-
-#define MP0_BASE__INST0_SEG0 0x00016000
-#define MP0_BASE__INST0_SEG1 0x00DC0000
-#define MP0_BASE__INST0_SEG2 0x00E00000
-#define MP0_BASE__INST0_SEG3 0x00E40000
-#define MP0_BASE__INST0_SEG4 0x0243FC00
-#define MP0_BASE__INST0_SEG5 0
-
-#define MP0_BASE__INST1_SEG0 0
-#define MP0_BASE__INST1_SEG1 0
-#define MP0_BASE__INST1_SEG2 0
-#define MP0_BASE__INST1_SEG3 0
-#define MP0_BASE__INST1_SEG4 0
-#define MP0_BASE__INST1_SEG5 0
-
-#define MP0_BASE__INST2_SEG0 0
-#define MP0_BASE__INST2_SEG1 0
-#define MP0_BASE__INST2_SEG2 0
-#define MP0_BASE__INST2_SEG3 0
-#define MP0_BASE__INST2_SEG4 0
-#define MP0_BASE__INST2_SEG5 0
-
-#define MP0_BASE__INST3_SEG0 0
-#define MP0_BASE__INST3_SEG1 0
-#define MP0_BASE__INST3_SEG2 0
-#define MP0_BASE__INST3_SEG3 0
-#define MP0_BASE__INST3_SEG4 0
-#define MP0_BASE__INST3_SEG5 0
-
-#define MP0_BASE__INST4_SEG0 0
-#define MP0_BASE__INST4_SEG1 0
-#define MP0_BASE__INST4_SEG2 0
-#define MP0_BASE__INST4_SEG3 0
-#define MP0_BASE__INST4_SEG4 0
-#define MP0_BASE__INST4_SEG5 0
-
-#define MP0_BASE__INST5_SEG0 0
-#define MP0_BASE__INST5_SEG1 0
-#define MP0_BASE__INST5_SEG2 0
-#define MP0_BASE__INST5_SEG3 0
-#define MP0_BASE__INST5_SEG4 0
-#define MP0_BASE__INST5_SEG5 0
-
-#define MP0_BASE__INST6_SEG0 0
-#define MP0_BASE__INST6_SEG1 0
-#define MP0_BASE__INST6_SEG2 0
-#define MP0_BASE__INST6_SEG3 0
-#define MP0_BASE__INST6_SEG4 0
-#define MP0_BASE__INST6_SEG5 0
-
-#define MP1_BASE__INST0_SEG0 0x00016000
-#define MP1_BASE__INST0_SEG1 0x00DC0000
-#define MP1_BASE__INST0_SEG2 0x00E00000
-#define MP1_BASE__INST0_SEG3 0x00E40000
-#define MP1_BASE__INST0_SEG4 0x0243FC00
-#define MP1_BASE__INST0_SEG5 0
-
-#define MP1_BASE__INST1_SEG0 0
-#define MP1_BASE__INST1_SEG1 0
-#define MP1_BASE__INST1_SEG2 0
-#define MP1_BASE__INST1_SEG3 0
-#define MP1_BASE__INST1_SEG4 0
-#define MP1_BASE__INST1_SEG5 0
-
-#define MP1_BASE__INST2_SEG0 0
-#define MP1_BASE__INST2_SEG1 0
-#define MP1_BASE__INST2_SEG2 0
-#define MP1_BASE__INST2_SEG3 0
-#define MP1_BASE__INST2_SEG4 0
-#define MP1_BASE__INST2_SEG5 0
-
-#define MP1_BASE__INST3_SEG0 0
-#define MP1_BASE__INST3_SEG1 0
-#define MP1_BASE__INST3_SEG2 0
-#define MP1_BASE__INST3_SEG3 0
-#define MP1_BASE__INST3_SEG4 0
-#define MP1_BASE__INST3_SEG5 0
-
-#define MP1_BASE__INST4_SEG0 0
-#define MP1_BASE__INST4_SEG1 0
-#define MP1_BASE__INST4_SEG2 0
-#define MP1_BASE__INST4_SEG3 0
-#define MP1_BASE__INST4_SEG4 0
-#define MP1_BASE__INST4_SEG5 0
-
-#define MP1_BASE__INST5_SEG0 0
-#define MP1_BASE__INST5_SEG1 0
-#define MP1_BASE__INST5_SEG2 0
-#define MP1_BASE__INST5_SEG3 0
-#define MP1_BASE__INST5_SEG4 0
-#define MP1_BASE__INST5_SEG5 0
-
-#define MP1_BASE__INST6_SEG0 0
-#define MP1_BASE__INST6_SEG1 0
-#define MP1_BASE__INST6_SEG2 0
-#define MP1_BASE__INST6_SEG3 0
-#define MP1_BASE__INST6_SEG4 0
-#define MP1_BASE__INST6_SEG5 0
-
-#define NBIO_BASE__INST0_SEG0 0x00000000
-#define NBIO_BASE__INST0_SEG1 0x00000014
-#define NBIO_BASE__INST0_SEG2 0x00000D20
-#define NBIO_BASE__INST0_SEG3 0x00010400
-#define NBIO_BASE__INST0_SEG4 0x0241B000
-#define NBIO_BASE__INST0_SEG5 0x04040000
-
-#define NBIO_BASE__INST1_SEG0 0
-#define NBIO_BASE__INST1_SEG1 0
-#define NBIO_BASE__INST1_SEG2 0
-#define NBIO_BASE__INST1_SEG3 0
-#define NBIO_BASE__INST1_SEG4 0
-#define NBIO_BASE__INST1_SEG5 0
-
-#define NBIO_BASE__INST2_SEG0 0
-#define NBIO_BASE__INST2_SEG1 0
-#define NBIO_BASE__INST2_SEG2 0
-#define NBIO_BASE__INST2_SEG3 0
-#define NBIO_BASE__INST2_SEG4 0
-#define NBIO_BASE__INST2_SEG5 0
-
-#define NBIO_BASE__INST3_SEG0 0
-#define NBIO_BASE__INST3_SEG1 0
-#define NBIO_BASE__INST3_SEG2 0
-#define NBIO_BASE__INST3_SEG3 0
-#define NBIO_BASE__INST3_SEG4 0
-#define NBIO_BASE__INST3_SEG5 0
-
-#define NBIO_BASE__INST4_SEG0 0
-#define NBIO_BASE__INST4_SEG1 0
-#define NBIO_BASE__INST4_SEG2 0
-#define NBIO_BASE__INST4_SEG3 0
-#define NBIO_BASE__INST4_SEG4 0
-#define NBIO_BASE__INST4_SEG5 0
-
-#define NBIO_BASE__INST5_SEG0 0
-#define NBIO_BASE__INST5_SEG1 0
-#define NBIO_BASE__INST5_SEG2 0
-#define NBIO_BASE__INST5_SEG3 0
-#define NBIO_BASE__INST5_SEG4 0
-#define NBIO_BASE__INST5_SEG5 0
-
-#define NBIO_BASE__INST6_SEG0 0
-#define NBIO_BASE__INST6_SEG1 0
-#define NBIO_BASE__INST6_SEG2 0
-#define NBIO_BASE__INST6_SEG3 0
-#define NBIO_BASE__INST6_SEG4 0
-#define NBIO_BASE__INST6_SEG5 0
-
-#define OSSSYS_BASE__INST0_SEG0 0x000010A0
-#define OSSSYS_BASE__INST0_SEG1 0x0240A000
-#define OSSSYS_BASE__INST0_SEG2 0
-#define OSSSYS_BASE__INST0_SEG3 0
-#define OSSSYS_BASE__INST0_SEG4 0
-#define OSSSYS_BASE__INST0_SEG5 0
-
-#define OSSSYS_BASE__INST1_SEG0 0
-#define OSSSYS_BASE__INST1_SEG1 0
-#define OSSSYS_BASE__INST1_SEG2 0
-#define OSSSYS_BASE__INST1_SEG3 0
-#define OSSSYS_BASE__INST1_SEG4 0
-#define OSSSYS_BASE__INST1_SEG5 0
-
-#define OSSSYS_BASE__INST2_SEG0 0
-#define OSSSYS_BASE__INST2_SEG1 0
-#define OSSSYS_BASE__INST2_SEG2 0
-#define OSSSYS_BASE__INST2_SEG3 0
-#define OSSSYS_BASE__INST2_SEG4 0
-#define OSSSYS_BASE__INST2_SEG5 0
-
-#define OSSSYS_BASE__INST3_SEG0 0
-#define OSSSYS_BASE__INST3_SEG1 0
-#define OSSSYS_BASE__INST3_SEG2 0
-#define OSSSYS_BASE__INST3_SEG3 0
-#define OSSSYS_BASE__INST3_SEG4 0
-#define OSSSYS_BASE__INST3_SEG5 0
-
-#define OSSSYS_BASE__INST4_SEG0 0
-#define OSSSYS_BASE__INST4_SEG1 0
-#define OSSSYS_BASE__INST4_SEG2 0
-#define OSSSYS_BASE__INST4_SEG3 0
-#define OSSSYS_BASE__INST4_SEG4 0
-#define OSSSYS_BASE__INST4_SEG5 0
-
-#define OSSSYS_BASE__INST5_SEG0 0
-#define OSSSYS_BASE__INST5_SEG1 0
-#define OSSSYS_BASE__INST5_SEG2 0
-#define OSSSYS_BASE__INST5_SEG3 0
-#define OSSSYS_BASE__INST5_SEG4 0
-#define OSSSYS_BASE__INST5_SEG5 0
-
-#define OSSSYS_BASE__INST6_SEG0 0
-#define OSSSYS_BASE__INST6_SEG1 0
-#define OSSSYS_BASE__INST6_SEG2 0
-#define OSSSYS_BASE__INST6_SEG3 0
-#define OSSSYS_BASE__INST6_SEG4 0
-#define OSSSYS_BASE__INST6_SEG5 0
-
-#define PCIE0_BASE__INST0_SEG0 0x00000000
-#define PCIE0_BASE__INST0_SEG1 0x00000014
-#define PCIE0_BASE__INST0_SEG2 0x00000D20
-#define PCIE0_BASE__INST0_SEG3 0x00010400
-#define PCIE0_BASE__INST0_SEG4 0x0241B000
-#define PCIE0_BASE__INST0_SEG5 0x04040000
-
-#define PCIE0_BASE__INST1_SEG0 0
-#define PCIE0_BASE__INST1_SEG1 0
-#define PCIE0_BASE__INST1_SEG2 0
-#define PCIE0_BASE__INST1_SEG3 0
-#define PCIE0_BASE__INST1_SEG4 0
-#define PCIE0_BASE__INST1_SEG5 0
-
-#define PCIE0_BASE__INST2_SEG0 0
-#define PCIE0_BASE__INST2_SEG1 0
-#define PCIE0_BASE__INST2_SEG2 0
-#define PCIE0_BASE__INST2_SEG3 0
-#define PCIE0_BASE__INST2_SEG4 0
-#define PCIE0_BASE__INST2_SEG5 0
-
-#define PCIE0_BASE__INST3_SEG0 0
-#define PCIE0_BASE__INST3_SEG1 0
-#define PCIE0_BASE__INST3_SEG2 0
-#define PCIE0_BASE__INST3_SEG3 0
-#define PCIE0_BASE__INST3_SEG4 0
-#define PCIE0_BASE__INST3_SEG5 0
-
-#define PCIE0_BASE__INST4_SEG0 0
-#define PCIE0_BASE__INST4_SEG1 0
-#define PCIE0_BASE__INST4_SEG2 0
-#define PCIE0_BASE__INST4_SEG3 0
-#define PCIE0_BASE__INST4_SEG4 0
-#define PCIE0_BASE__INST4_SEG5 0
-
-#define PCIE0_BASE__INST5_SEG0 0
-#define PCIE0_BASE__INST5_SEG1 0
-#define PCIE0_BASE__INST5_SEG2 0
-#define PCIE0_BASE__INST5_SEG3 0
-#define PCIE0_BASE__INST5_SEG4 0
-#define PCIE0_BASE__INST5_SEG5 0
-
-#define PCIE0_BASE__INST6_SEG0 0
-#define PCIE0_BASE__INST6_SEG1 0
-#define PCIE0_BASE__INST6_SEG2 0
-#define PCIE0_BASE__INST6_SEG3 0
-#define PCIE0_BASE__INST6_SEG4 0
-#define PCIE0_BASE__INST6_SEG5 0
-
-#define SDMA0_BASE__INST0_SEG0 0x00001260
-#define SDMA0_BASE__INST0_SEG1 0x0000A000
-#define SDMA0_BASE__INST0_SEG2 0x0001C000
-#define SDMA0_BASE__INST0_SEG3 0x02402C00
-#define SDMA0_BASE__INST0_SEG4 0
-#define SDMA0_BASE__INST0_SEG5 0
-
-#define SDMA0_BASE__INST1_SEG0 0
-#define SDMA0_BASE__INST1_SEG1 0
-#define SDMA0_BASE__INST1_SEG2 0
-#define SDMA0_BASE__INST1_SEG3 0
-#define SDMA0_BASE__INST1_SEG4 0
-#define SDMA0_BASE__INST1_SEG5 0
-
-#define SDMA0_BASE__INST2_SEG0 0
-#define SDMA0_BASE__INST2_SEG1 0
-#define SDMA0_BASE__INST2_SEG2 0
-#define SDMA0_BASE__INST2_SEG3 0
-#define SDMA0_BASE__INST2_SEG4 0
-#define SDMA0_BASE__INST2_SEG5 0
-
-#define SDMA0_BASE__INST3_SEG0 0
-#define SDMA0_BASE__INST3_SEG1 0
-#define SDMA0_BASE__INST3_SEG2 0
-#define SDMA0_BASE__INST3_SEG3 0
-#define SDMA0_BASE__INST3_SEG4 0
-#define SDMA0_BASE__INST3_SEG5 0
-
-#define SDMA0_BASE__INST4_SEG0 0
-#define SDMA0_BASE__INST4_SEG1 0
-#define SDMA0_BASE__INST4_SEG2 0
-#define SDMA0_BASE__INST4_SEG3 0
-#define SDMA0_BASE__INST4_SEG4 0
-#define SDMA0_BASE__INST4_SEG5 0
-
-#define SDMA0_BASE__INST5_SEG0 0
-#define SDMA0_BASE__INST5_SEG1 0
-#define SDMA0_BASE__INST5_SEG2 0
-#define SDMA0_BASE__INST5_SEG3 0
-#define SDMA0_BASE__INST5_SEG4 0
-#define SDMA0_BASE__INST5_SEG5 0
-
-#define SDMA0_BASE__INST6_SEG0 0
-#define SDMA0_BASE__INST6_SEG1 0
-#define SDMA0_BASE__INST6_SEG2 0
-#define SDMA0_BASE__INST6_SEG3 0
-#define SDMA0_BASE__INST6_SEG4 0
-#define SDMA0_BASE__INST6_SEG5 0
-
-#define SMUIO_BASE__INST0_SEG0 0x00016800
-#define SMUIO_BASE__INST0_SEG1 0x00016A00
-#define SMUIO_BASE__INST0_SEG2 0x00440000
-#define SMUIO_BASE__INST0_SEG3 0x02401000
-#define SMUIO_BASE__INST0_SEG4 0
-#define SMUIO_BASE__INST0_SEG5 0
-
-#define SMUIO_BASE__INST1_SEG0 0
-#define SMUIO_BASE__INST1_SEG1 0
-#define SMUIO_BASE__INST1_SEG2 0
-#define SMUIO_BASE__INST1_SEG3 0
-#define SMUIO_BASE__INST1_SEG4 0
-#define SMUIO_BASE__INST1_SEG5 0
-
-#define SMUIO_BASE__INST2_SEG0 0
-#define SMUIO_BASE__INST2_SEG1 0
-#define SMUIO_BASE__INST2_SEG2 0
-#define SMUIO_BASE__INST2_SEG3 0
-#define SMUIO_BASE__INST2_SEG4 0
-#define SMUIO_BASE__INST2_SEG5 0
-
-#define SMUIO_BASE__INST3_SEG0 0
-#define SMUIO_BASE__INST3_SEG1 0
-#define SMUIO_BASE__INST3_SEG2 0
-#define SMUIO_BASE__INST3_SEG3 0
-#define SMUIO_BASE__INST3_SEG4 0
-#define SMUIO_BASE__INST3_SEG5 0
-
-#define SMUIO_BASE__INST4_SEG0 0
-#define SMUIO_BASE__INST4_SEG1 0
-#define SMUIO_BASE__INST4_SEG2 0
-#define SMUIO_BASE__INST4_SEG3 0
-#define SMUIO_BASE__INST4_SEG4 0
-#define SMUIO_BASE__INST4_SEG5 0
-
-#define SMUIO_BASE__INST5_SEG0 0
-#define SMUIO_BASE__INST5_SEG1 0
-#define SMUIO_BASE__INST5_SEG2 0
-#define SMUIO_BASE__INST5_SEG3 0
-#define SMUIO_BASE__INST5_SEG4 0
-#define SMUIO_BASE__INST5_SEG5 0
-
-#define SMUIO_BASE__INST6_SEG0 0
-#define SMUIO_BASE__INST6_SEG1 0
-#define SMUIO_BASE__INST6_SEG2 0
-#define SMUIO_BASE__INST6_SEG3 0
-#define SMUIO_BASE__INST6_SEG4 0
-#define SMUIO_BASE__INST6_SEG5 0
-
-#define THM_BASE__INST0_SEG0 0x00016600
-#define THM_BASE__INST0_SEG1 0x02400C00
-#define THM_BASE__INST0_SEG2 0
-#define THM_BASE__INST0_SEG3 0
-#define THM_BASE__INST0_SEG4 0
-#define THM_BASE__INST0_SEG5 0
-
-#define THM_BASE__INST1_SEG0 0
-#define THM_BASE__INST1_SEG1 0
-#define THM_BASE__INST1_SEG2 0
-#define THM_BASE__INST1_SEG3 0
-#define THM_BASE__INST1_SEG4 0
-#define THM_BASE__INST1_SEG5 0
-
-#define THM_BASE__INST2_SEG0 0
-#define THM_BASE__INST2_SEG1 0
-#define THM_BASE__INST2_SEG2 0
-#define THM_BASE__INST2_SEG3 0
-#define THM_BASE__INST2_SEG4 0
-#define THM_BASE__INST2_SEG5 0
-
-#define THM_BASE__INST3_SEG0 0
-#define THM_BASE__INST3_SEG1 0
-#define THM_BASE__INST3_SEG2 0
-#define THM_BASE__INST3_SEG3 0
-#define THM_BASE__INST3_SEG4 0
-#define THM_BASE__INST3_SEG5 0
-
-#define THM_BASE__INST4_SEG0 0
-#define THM_BASE__INST4_SEG1 0
-#define THM_BASE__INST4_SEG2 0
-#define THM_BASE__INST4_SEG3 0
-#define THM_BASE__INST4_SEG4 0
-#define THM_BASE__INST4_SEG5 0
-
-#define THM_BASE__INST5_SEG0 0
-#define THM_BASE__INST5_SEG1 0
-#define THM_BASE__INST5_SEG2 0
-#define THM_BASE__INST5_SEG3 0
-#define THM_BASE__INST5_SEG4 0
-#define THM_BASE__INST5_SEG5 0
-
-#define THM_BASE__INST6_SEG0 0
-#define THM_BASE__INST6_SEG1 0
-#define THM_BASE__INST6_SEG2 0
-#define THM_BASE__INST6_SEG3 0
-#define THM_BASE__INST6_SEG4 0
-#define THM_BASE__INST6_SEG5 0
-
-#define UMC_BASE__INST0_SEG0 0x00014000
-#define UMC_BASE__INST0_SEG1 0x02425800
-#define UMC_BASE__INST0_SEG2 0
-#define UMC_BASE__INST0_SEG3 0
-#define UMC_BASE__INST0_SEG4 0
-#define UMC_BASE__INST0_SEG5 0
-
-#define UMC_BASE__INST1_SEG0 0x00054000
-#define UMC_BASE__INST1_SEG1 0x02425C00
-#define UMC_BASE__INST1_SEG2 0
-#define UMC_BASE__INST1_SEG3 0
-#define UMC_BASE__INST1_SEG4 0
-#define UMC_BASE__INST1_SEG5 0
-
-#define UMC_BASE__INST2_SEG0 0
-#define UMC_BASE__INST2_SEG1 0
-#define UMC_BASE__INST2_SEG2 0
-#define UMC_BASE__INST2_SEG3 0
-#define UMC_BASE__INST2_SEG4 0
-#define UMC_BASE__INST2_SEG5 0
-
-#define UMC_BASE__INST3_SEG0 0
-#define UMC_BASE__INST3_SEG1 0
-#define UMC_BASE__INST3_SEG2 0
-#define UMC_BASE__INST3_SEG3 0
-#define UMC_BASE__INST3_SEG4 0
-#define UMC_BASE__INST3_SEG5 0
-
-#define UMC_BASE__INST4_SEG0 0
-#define UMC_BASE__INST4_SEG1 0
-#define UMC_BASE__INST4_SEG2 0
-#define UMC_BASE__INST4_SEG3 0
-#define UMC_BASE__INST4_SEG4 0
-#define UMC_BASE__INST4_SEG5 0
-
-#define UMC_BASE__INST5_SEG0 0
-#define UMC_BASE__INST5_SEG1 0
-#define UMC_BASE__INST5_SEG2 0
-#define UMC_BASE__INST5_SEG3 0
-#define UMC_BASE__INST5_SEG4 0
-#define UMC_BASE__INST5_SEG5 0
-
-#define UMC_BASE__INST6_SEG0 0
-#define UMC_BASE__INST6_SEG1 0
-#define UMC_BASE__INST6_SEG2 0
-#define UMC_BASE__INST6_SEG3 0
-#define UMC_BASE__INST6_SEG4 0
-#define UMC_BASE__INST6_SEG5 0
-
-#define VCN0_BASE__INST0_SEG0 0x00007800
-#define VCN0_BASE__INST0_SEG1 0x00007E00
-#define VCN0_BASE__INST0_SEG2 0x02403000
-#define VCN0_BASE__INST0_SEG3 0
-#define VCN0_BASE__INST0_SEG4 0
-#define VCN0_BASE__INST0_SEG5 0
-
-#define VCN0_BASE__INST1_SEG0 0
-#define VCN0_BASE__INST1_SEG1 0
-#define VCN0_BASE__INST1_SEG2 0
-#define VCN0_BASE__INST1_SEG3 0
-#define VCN0_BASE__INST1_SEG4 0
-#define VCN0_BASE__INST1_SEG5 0
-
-#define VCN0_BASE__INST2_SEG0 0
-#define VCN0_BASE__INST2_SEG1 0
-#define VCN0_BASE__INST2_SEG2 0
-#define VCN0_BASE__INST2_SEG3 0
-#define VCN0_BASE__INST2_SEG4 0
-#define VCN0_BASE__INST2_SEG5 0
-
-#define VCN0_BASE__INST3_SEG0 0
-#define VCN0_BASE__INST3_SEG1 0
-#define VCN0_BASE__INST3_SEG2 0
-#define VCN0_BASE__INST3_SEG3 0
-#define VCN0_BASE__INST3_SEG4 0
-#define VCN0_BASE__INST3_SEG5 0
-
-#define VCN0_BASE__INST4_SEG0 0
-#define VCN0_BASE__INST4_SEG1 0
-#define VCN0_BASE__INST4_SEG2 0
-#define VCN0_BASE__INST4_SEG3 0
-#define VCN0_BASE__INST4_SEG4 0
-#define VCN0_BASE__INST4_SEG5 0
-
-#define VCN0_BASE__INST5_SEG0 0
-#define VCN0_BASE__INST5_SEG1 0
-#define VCN0_BASE__INST5_SEG2 0
-#define VCN0_BASE__INST5_SEG3 0
-#define VCN0_BASE__INST5_SEG4 0
-#define VCN0_BASE__INST5_SEG5 0
-
-#define VCN0_BASE__INST6_SEG0 0
-#define VCN0_BASE__INST6_SEG1 0
-#define VCN0_BASE__INST6_SEG2 0
-#define VCN0_BASE__INST6_SEG3 0
-#define VCN0_BASE__INST6_SEG4 0
-#define VCN0_BASE__INST6_SEG5 0
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/displayobject.h b/drivers/gpu/drm/amd/include/displayobject.h
deleted file mode 100644
index 67e23ff9c..000000000
--- a/drivers/gpu/drm/amd/include/displayobject.h
+++ /dev/null
@@ -1,249 +0,0 @@
-/****************************************************************************\
-*
-* Module Name displayobjectsoc15.h
-* Project
-* Device
-*
-* Description Contains the common definitions for display objects for SoC15 products.
-*
-* Copyright 2014 Advanced Micro Devices, Inc.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
-* and associated documentation files (the "Software"), to deal in the Software without restriction,
-* including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
-* and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so,
-* subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in all copies or substantial
-* portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-* OTHER DEALINGS IN THE SOFTWARE.
-*
-\****************************************************************************/
-#ifndef _DISPLAY_OBJECT_SOC15_H_
-#define _DISPLAY_OBJECT_SOC15_H_
-
-#if defined(_X86_)
-#pragma pack(1)
-#endif
-
-
-/****************************************************
-* Display Object Type Definition
-*****************************************************/
-enum display_object_type{
-DISPLAY_OBJECT_TYPE_NONE =0x00,
-DISPLAY_OBJECT_TYPE_GPU =0x01,
-DISPLAY_OBJECT_TYPE_ENCODER =0x02,
-DISPLAY_OBJECT_TYPE_CONNECTOR =0x03
-};
-
-/****************************************************
-* Encorder Object Type Definition
-*****************************************************/
-enum encoder_object_type{
-ENCODER_OBJECT_ID_NONE =0x00,
-ENCODER_OBJECT_ID_INTERNAL_UNIPHY =0x01,
-ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 =0x02,
-ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 =0x03,
-};
-
-
-/****************************************************
-* Connector Object ID Definition
-*****************************************************/
-
-enum connector_object_type{
-CONNECTOR_OBJECT_ID_NONE =0x00,
-CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D =0x01,
-CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D =0x02,
-CONNECTOR_OBJECT_ID_HDMI_TYPE_A =0x03,
-CONNECTOR_OBJECT_ID_LVDS =0x04,
-CONNECTOR_OBJECT_ID_DISPLAYPORT =0x05,
-CONNECTOR_OBJECT_ID_eDP =0x06,
-CONNECTOR_OBJECT_ID_OPM =0x07
-};
-
-
-/****************************************************
-* Protection Object ID Definition
-*****************************************************/
-//No need
-
-/****************************************************
-* Object ENUM ID Definition
-*****************************************************/
-
-enum object_enum_id{
-OBJECT_ENUM_ID1 =0x01,
-OBJECT_ENUM_ID2 =0x02,
-OBJECT_ENUM_ID3 =0x03,
-OBJECT_ENUM_ID4 =0x04,
-OBJECT_ENUM_ID5 =0x05,
-OBJECT_ENUM_ID6 =0x06
-};
-
-/****************************************************
-*Object ID Bit definition
-*****************************************************/
-enum object_id_bit{
-OBJECT_ID_MASK =0x00FF,
-ENUM_ID_MASK =0x0F00,
-OBJECT_TYPE_MASK =0xF000,
-OBJECT_ID_SHIFT =0x00,
-ENUM_ID_SHIFT =0x08,
-OBJECT_TYPE_SHIFT =0x0C
-};
-
-
-/****************************************************
-* GPU Object definition - Shared with BIOS
-*****************************************************/
-enum gpu_objet_def{
-GPU_ENUM_ID1 =( DISPLAY_OBJECT_TYPE_GPU << OBJECT_TYPE_SHIFT | OBJECT_ENUM_ID1 << ENUM_ID_SHIFT)
-};
-
-/****************************************************
-* Encoder Object definition - Shared with BIOS
-*****************************************************/
-
-enum encoder_objet_def{
-ENCODER_INTERNAL_UNIPHY_ENUM_ID1 =( DISPLAY_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT),
-
-ENCODER_INTERNAL_UNIPHY_ENUM_ID2 =( DISPLAY_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT),
-
-ENCODER_INTERNAL_UNIPHY1_ENUM_ID1 =( DISPLAY_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 << OBJECT_ID_SHIFT),
-
-ENCODER_INTERNAL_UNIPHY1_ENUM_ID2 =( DISPLAY_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 << OBJECT_ID_SHIFT),
-
-ENCODER_INTERNAL_UNIPHY2_ENUM_ID1 =( DISPLAY_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT),
-
-ENCODER_INTERNAL_UNIPHY2_ENUM_ID2 =( DISPLAY_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT)
-};
-
-
-/****************************************************
-* Connector Object definition - Shared with BIOS
-*****************************************************/
-
-
-enum connector_objet_def{
-CONNECTOR_LVDS_ENUM_ID1 =( DISPLAY_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_LVDS << OBJECT_ID_SHIFT),
-
-
-CONNECTOR_eDP_ENUM_ID1 =( DISPLAY_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_eDP << OBJECT_ID_SHIFT),
-
-CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1 =( DISPLAY_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT),
-
-CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID2 =( DISPLAY_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT),
-
-
-CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 =( DISPLAY_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT),
-
-CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID2 =( DISPLAY_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT),
-
-CONNECTOR_HDMI_TYPE_A_ENUM_ID1 =( DISPLAY_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT),
-
-CONNECTOR_HDMI_TYPE_A_ENUM_ID2 =( DISPLAY_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT),
-
-CONNECTOR_DISPLAYPORT_ENUM_ID1 =( DISPLAY_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT),
-
-CONNECTOR_DISPLAYPORT_ENUM_ID2 =( DISPLAY_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT),
-
-CONNECTOR_DISPLAYPORT_ENUM_ID3 =( DISPLAY_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT),
-
-CONNECTOR_DISPLAYPORT_ENUM_ID4 =( DISPLAY_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT),
-
-CONNECTOR_OPM_ENUM_ID1 =( DISPLAY_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_OPM << OBJECT_ID_SHIFT), //Mapping to MXM_DP_A
-
-CONNECTOR_OPM_ENUM_ID2 =( DISPLAY_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_OPM << OBJECT_ID_SHIFT), //Mapping to MXM_DP_B
-
-CONNECTOR_OPM_ENUM_ID3 =( DISPLAY_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_OPM << OBJECT_ID_SHIFT), //Mapping to MXM_DP_C
-
-CONNECTOR_OPM_ENUM_ID4 =( DISPLAY_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_OPM << OBJECT_ID_SHIFT), //Mapping to MXM_DP_D
-
-CONNECTOR_OPM_ENUM_ID5 =( DISPLAY_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- OBJECT_ENUM_ID5 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_OPM << OBJECT_ID_SHIFT), //Mapping to MXM_LVDS_TXxx
-
-
-CONNECTOR_OPM_ENUM_ID6 =( DISPLAY_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- OBJECT_ENUM_ID6 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_OPM << OBJECT_ID_SHIFT) //Mapping to MXM_LVDS_TXxx
-};
-
-/****************************************************
-* Router Object ID definition - Shared with BIOS
-*****************************************************/
-//No Need, in future we ever need, we can define a record in atomfirwareSoC15.h associated with an object that has this router
-
-
-/****************************************************
-* PROTECTION Object ID definition - Shared with BIOS
-*****************************************************/
-//No need,in future we ever need, all display path are capable of protection now.
-
-/****************************************************
-* Generic Object ID definition - Shared with BIOS
-*****************************************************/
-//No need, in future we ever need like GLsync, we can define a record in atomfirwareSoC15.h associated with an object.
-
-
-#if defined(_X86_)
-#pragma pack()
-#endif
-
-#endif
-
-
-
diff --git a/drivers/gpu/drm/amd/include/navi12_ip_offset.h b/drivers/gpu/drm/amd/include/navi12_ip_offset.h
deleted file mode 100644
index e94d80ec8..000000000
--- a/drivers/gpu/drm/amd/include/navi12_ip_offset.h
+++ /dev/null
@@ -1,1117 +0,0 @@
-/*
- * Copyright (C) 2019 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _navi12_ip_offset_HEADER
-#define _navi12_ip_offset_HEADER
-
-#define MAX_INSTANCE 7
-#define MAX_SEGMENT 5
-
-
-struct IP_BASE_INSTANCE {
- unsigned int segment[MAX_SEGMENT];
-};
-
-struct IP_BASE {
- struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
-} __maybe_unused;
-
-
-static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C00, 0x02408C00, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x02401800, 0, 0, 0 } },
- { { 0x00016E00, 0x02401C00, 0, 0, 0 } },
- { { 0x00017000, 0x02402000, 0, 0, 0 } },
- { { 0x00017200, 0x02402400, 0, 0, 0 } },
- { { 0x0001B000, 0x0242D800, 0, 0, 0 } },
- { { 0x00017E00, 0x0240BC00, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x0240B800, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE DIO_BASE ={ { { { 0x02404000, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE DPCS_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0x02401400, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE GC_BASE ={ { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE HDA_BASE ={ { { { 0x004C0000, 0x02404800, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x0240A400, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0x00E80000, 0x00EC0000, 0x00F00000, 0x02400400 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x0240A000, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE PCIE0_BASE ={ { { { 0x02411800, 0x04440000, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE SDMA_BASE ={ { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } },
- { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0x00440000, 0x02401000, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0x02425800, 0, 0, 0 } },
- { { 0x00054000, 0x02425C00, 0, 0, 0 } },
- { { 0x00094000, 0x02426000, 0, 0, 0 } },
- { { 0x000D4000, 0x02426400, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE USB0_BASE ={ { { { 0x0242A800, 0x05B00000, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-
-
-#define ATHUB_BASE__INST0_SEG0 0x00000C00
-#define ATHUB_BASE__INST0_SEG1 0x02408C00
-#define ATHUB_BASE__INST0_SEG2 0
-#define ATHUB_BASE__INST0_SEG3 0
-#define ATHUB_BASE__INST0_SEG4 0
-
-#define ATHUB_BASE__INST1_SEG0 0
-#define ATHUB_BASE__INST1_SEG1 0
-#define ATHUB_BASE__INST1_SEG2 0
-#define ATHUB_BASE__INST1_SEG3 0
-#define ATHUB_BASE__INST1_SEG4 0
-
-#define ATHUB_BASE__INST2_SEG0 0
-#define ATHUB_BASE__INST2_SEG1 0
-#define ATHUB_BASE__INST2_SEG2 0
-#define ATHUB_BASE__INST2_SEG3 0
-#define ATHUB_BASE__INST2_SEG4 0
-
-#define ATHUB_BASE__INST3_SEG0 0
-#define ATHUB_BASE__INST3_SEG1 0
-#define ATHUB_BASE__INST3_SEG2 0
-#define ATHUB_BASE__INST3_SEG3 0
-#define ATHUB_BASE__INST3_SEG4 0
-
-#define ATHUB_BASE__INST4_SEG0 0
-#define ATHUB_BASE__INST4_SEG1 0
-#define ATHUB_BASE__INST4_SEG2 0
-#define ATHUB_BASE__INST4_SEG3 0
-#define ATHUB_BASE__INST4_SEG4 0
-
-#define ATHUB_BASE__INST5_SEG0 0
-#define ATHUB_BASE__INST5_SEG1 0
-#define ATHUB_BASE__INST5_SEG2 0
-#define ATHUB_BASE__INST5_SEG3 0
-#define ATHUB_BASE__INST5_SEG4 0
-
-#define ATHUB_BASE__INST6_SEG0 0
-#define ATHUB_BASE__INST6_SEG1 0
-#define ATHUB_BASE__INST6_SEG2 0
-#define ATHUB_BASE__INST6_SEG3 0
-#define ATHUB_BASE__INST6_SEG4 0
-
-#define CLK_BASE__INST0_SEG0 0x00016C00
-#define CLK_BASE__INST0_SEG1 0x02401800
-#define CLK_BASE__INST0_SEG2 0
-#define CLK_BASE__INST0_SEG3 0
-#define CLK_BASE__INST0_SEG4 0
-
-#define CLK_BASE__INST1_SEG0 0x00016E00
-#define CLK_BASE__INST1_SEG1 0x02401C00
-#define CLK_BASE__INST1_SEG2 0
-#define CLK_BASE__INST1_SEG3 0
-#define CLK_BASE__INST1_SEG4 0
-
-#define CLK_BASE__INST2_SEG0 0x00017000
-#define CLK_BASE__INST2_SEG1 0x02402000
-#define CLK_BASE__INST2_SEG2 0
-#define CLK_BASE__INST2_SEG3 0
-#define CLK_BASE__INST2_SEG4 0
-
-#define CLK_BASE__INST3_SEG0 0x00017200
-#define CLK_BASE__INST3_SEG1 0x02402400
-#define CLK_BASE__INST3_SEG2 0
-#define CLK_BASE__INST3_SEG3 0
-#define CLK_BASE__INST3_SEG4 0
-
-#define CLK_BASE__INST4_SEG0 0x0001B000
-#define CLK_BASE__INST4_SEG1 0x0242D800
-#define CLK_BASE__INST4_SEG2 0
-#define CLK_BASE__INST4_SEG3 0
-#define CLK_BASE__INST4_SEG4 0
-
-#define CLK_BASE__INST5_SEG0 0x00017E00
-#define CLK_BASE__INST5_SEG1 0x0240BC00
-#define CLK_BASE__INST5_SEG2 0
-#define CLK_BASE__INST5_SEG3 0
-#define CLK_BASE__INST5_SEG4 0
-
-#define CLK_BASE__INST6_SEG0 0
-#define CLK_BASE__INST6_SEG1 0
-#define CLK_BASE__INST6_SEG2 0
-#define CLK_BASE__INST6_SEG3 0
-#define CLK_BASE__INST6_SEG4 0
-
-#define DF_BASE__INST0_SEG0 0x00007000
-#define DF_BASE__INST0_SEG1 0x0240B800
-#define DF_BASE__INST0_SEG2 0
-#define DF_BASE__INST0_SEG3 0
-#define DF_BASE__INST0_SEG4 0
-
-#define DF_BASE__INST1_SEG0 0
-#define DF_BASE__INST1_SEG1 0
-#define DF_BASE__INST1_SEG2 0
-#define DF_BASE__INST1_SEG3 0
-#define DF_BASE__INST1_SEG4 0
-
-#define DF_BASE__INST2_SEG0 0
-#define DF_BASE__INST2_SEG1 0
-#define DF_BASE__INST2_SEG2 0
-#define DF_BASE__INST2_SEG3 0
-#define DF_BASE__INST2_SEG4 0
-
-#define DF_BASE__INST3_SEG0 0
-#define DF_BASE__INST3_SEG1 0
-#define DF_BASE__INST3_SEG2 0
-#define DF_BASE__INST3_SEG3 0
-#define DF_BASE__INST3_SEG4 0
-
-#define DF_BASE__INST4_SEG0 0
-#define DF_BASE__INST4_SEG1 0
-#define DF_BASE__INST4_SEG2 0
-#define DF_BASE__INST4_SEG3 0
-#define DF_BASE__INST4_SEG4 0
-
-#define DF_BASE__INST5_SEG0 0
-#define DF_BASE__INST5_SEG1 0
-#define DF_BASE__INST5_SEG2 0
-#define DF_BASE__INST5_SEG3 0
-#define DF_BASE__INST5_SEG4 0
-
-#define DF_BASE__INST6_SEG0 0
-#define DF_BASE__INST6_SEG1 0
-#define DF_BASE__INST6_SEG2 0
-#define DF_BASE__INST6_SEG3 0
-#define DF_BASE__INST6_SEG4 0
-
-#define DIO_BASE__INST0_SEG0 0x02404000
-#define DIO_BASE__INST0_SEG1 0
-#define DIO_BASE__INST0_SEG2 0
-#define DIO_BASE__INST0_SEG3 0
-#define DIO_BASE__INST0_SEG4 0
-
-#define DIO_BASE__INST1_SEG0 0
-#define DIO_BASE__INST1_SEG1 0
-#define DIO_BASE__INST1_SEG2 0
-#define DIO_BASE__INST1_SEG3 0
-#define DIO_BASE__INST1_SEG4 0
-
-#define DIO_BASE__INST2_SEG0 0
-#define DIO_BASE__INST2_SEG1 0
-#define DIO_BASE__INST2_SEG2 0
-#define DIO_BASE__INST2_SEG3 0
-#define DIO_BASE__INST2_SEG4 0
-
-#define DIO_BASE__INST3_SEG0 0
-#define DIO_BASE__INST3_SEG1 0
-#define DIO_BASE__INST3_SEG2 0
-#define DIO_BASE__INST3_SEG3 0
-#define DIO_BASE__INST3_SEG4 0
-
-#define DIO_BASE__INST4_SEG0 0
-#define DIO_BASE__INST4_SEG1 0
-#define DIO_BASE__INST4_SEG2 0
-#define DIO_BASE__INST4_SEG3 0
-#define DIO_BASE__INST4_SEG4 0
-
-#define DIO_BASE__INST5_SEG0 0
-#define DIO_BASE__INST5_SEG1 0
-#define DIO_BASE__INST5_SEG2 0
-#define DIO_BASE__INST5_SEG3 0
-#define DIO_BASE__INST5_SEG4 0
-
-#define DIO_BASE__INST6_SEG0 0
-#define DIO_BASE__INST6_SEG1 0
-#define DIO_BASE__INST6_SEG2 0
-#define DIO_BASE__INST6_SEG3 0
-#define DIO_BASE__INST6_SEG4 0
-
-#define DMU_BASE__INST0_SEG0 0x00000012
-#define DMU_BASE__INST0_SEG1 0x000000C0
-#define DMU_BASE__INST0_SEG2 0x000034C0
-#define DMU_BASE__INST0_SEG3 0x00009000
-#define DMU_BASE__INST0_SEG4 0x02403C00
-
-#define DMU_BASE__INST1_SEG0 0
-#define DMU_BASE__INST1_SEG1 0
-#define DMU_BASE__INST1_SEG2 0
-#define DMU_BASE__INST1_SEG3 0
-#define DMU_BASE__INST1_SEG4 0
-
-#define DMU_BASE__INST2_SEG0 0
-#define DMU_BASE__INST2_SEG1 0
-#define DMU_BASE__INST2_SEG2 0
-#define DMU_BASE__INST2_SEG3 0
-#define DMU_BASE__INST2_SEG4 0
-
-#define DMU_BASE__INST3_SEG0 0
-#define DMU_BASE__INST3_SEG1 0
-#define DMU_BASE__INST3_SEG2 0
-#define DMU_BASE__INST3_SEG3 0
-#define DMU_BASE__INST3_SEG4 0
-
-#define DMU_BASE__INST4_SEG0 0
-#define DMU_BASE__INST4_SEG1 0
-#define DMU_BASE__INST4_SEG2 0
-#define DMU_BASE__INST4_SEG3 0
-#define DMU_BASE__INST4_SEG4 0
-
-#define DMU_BASE__INST5_SEG0 0
-#define DMU_BASE__INST5_SEG1 0
-#define DMU_BASE__INST5_SEG2 0
-#define DMU_BASE__INST5_SEG3 0
-#define DMU_BASE__INST5_SEG4 0
-
-#define DMU_BASE__INST6_SEG0 0
-#define DMU_BASE__INST6_SEG1 0
-#define DMU_BASE__INST6_SEG2 0
-#define DMU_BASE__INST6_SEG3 0
-#define DMU_BASE__INST6_SEG4 0
-
-#define DPCS_BASE__INST0_SEG0 0x00000012
-#define DPCS_BASE__INST0_SEG1 0x000000C0
-#define DPCS_BASE__INST0_SEG2 0x000034C0
-#define DPCS_BASE__INST0_SEG3 0x00009000
-#define DPCS_BASE__INST0_SEG4 0x02403C00
-
-#define DPCS_BASE__INST1_SEG0 0
-#define DPCS_BASE__INST1_SEG1 0
-#define DPCS_BASE__INST1_SEG2 0
-#define DPCS_BASE__INST1_SEG3 0
-#define DPCS_BASE__INST1_SEG4 0
-
-#define DPCS_BASE__INST2_SEG0 0
-#define DPCS_BASE__INST2_SEG1 0
-#define DPCS_BASE__INST2_SEG2 0
-#define DPCS_BASE__INST2_SEG3 0
-#define DPCS_BASE__INST2_SEG4 0
-
-#define DPCS_BASE__INST3_SEG0 0
-#define DPCS_BASE__INST3_SEG1 0
-#define DPCS_BASE__INST3_SEG2 0
-#define DPCS_BASE__INST3_SEG3 0
-#define DPCS_BASE__INST3_SEG4 0
-
-#define DPCS_BASE__INST4_SEG0 0
-#define DPCS_BASE__INST4_SEG1 0
-#define DPCS_BASE__INST4_SEG2 0
-#define DPCS_BASE__INST4_SEG3 0
-#define DPCS_BASE__INST4_SEG4 0
-
-#define DPCS_BASE__INST5_SEG0 0
-#define DPCS_BASE__INST5_SEG1 0
-#define DPCS_BASE__INST5_SEG2 0
-#define DPCS_BASE__INST5_SEG3 0
-#define DPCS_BASE__INST5_SEG4 0
-
-#define DPCS_BASE__INST6_SEG0 0
-#define DPCS_BASE__INST6_SEG1 0
-#define DPCS_BASE__INST6_SEG2 0
-#define DPCS_BASE__INST6_SEG3 0
-#define DPCS_BASE__INST6_SEG4 0
-
-#define FUSE_BASE__INST0_SEG0 0x00017400
-#define FUSE_BASE__INST0_SEG1 0x02401400
-#define FUSE_BASE__INST0_SEG2 0
-#define FUSE_BASE__INST0_SEG3 0
-#define FUSE_BASE__INST0_SEG4 0
-
-#define FUSE_BASE__INST1_SEG0 0
-#define FUSE_BASE__INST1_SEG1 0
-#define FUSE_BASE__INST1_SEG2 0
-#define FUSE_BASE__INST1_SEG3 0
-#define FUSE_BASE__INST1_SEG4 0
-
-#define FUSE_BASE__INST2_SEG0 0
-#define FUSE_BASE__INST2_SEG1 0
-#define FUSE_BASE__INST2_SEG2 0
-#define FUSE_BASE__INST2_SEG3 0
-#define FUSE_BASE__INST2_SEG4 0
-
-#define FUSE_BASE__INST3_SEG0 0
-#define FUSE_BASE__INST3_SEG1 0
-#define FUSE_BASE__INST3_SEG2 0
-#define FUSE_BASE__INST3_SEG3 0
-#define FUSE_BASE__INST3_SEG4 0
-
-#define FUSE_BASE__INST4_SEG0 0
-#define FUSE_BASE__INST4_SEG1 0
-#define FUSE_BASE__INST4_SEG2 0
-#define FUSE_BASE__INST4_SEG3 0
-#define FUSE_BASE__INST4_SEG4 0
-
-#define FUSE_BASE__INST5_SEG0 0
-#define FUSE_BASE__INST5_SEG1 0
-#define FUSE_BASE__INST5_SEG2 0
-#define FUSE_BASE__INST5_SEG3 0
-#define FUSE_BASE__INST5_SEG4 0
-
-#define FUSE_BASE__INST6_SEG0 0
-#define FUSE_BASE__INST6_SEG1 0
-#define FUSE_BASE__INST6_SEG2 0
-#define FUSE_BASE__INST6_SEG3 0
-#define FUSE_BASE__INST6_SEG4 0
-
-#define GC_BASE__INST0_SEG0 0x00001260
-#define GC_BASE__INST0_SEG1 0x0000A000
-#define GC_BASE__INST0_SEG2 0x02402C00
-#define GC_BASE__INST0_SEG3 0
-#define GC_BASE__INST0_SEG4 0
-
-#define GC_BASE__INST1_SEG0 0
-#define GC_BASE__INST1_SEG1 0
-#define GC_BASE__INST1_SEG2 0
-#define GC_BASE__INST1_SEG3 0
-#define GC_BASE__INST1_SEG4 0
-
-#define GC_BASE__INST2_SEG0 0
-#define GC_BASE__INST2_SEG1 0
-#define GC_BASE__INST2_SEG2 0
-#define GC_BASE__INST2_SEG3 0
-#define GC_BASE__INST2_SEG4 0
-
-#define GC_BASE__INST3_SEG0 0
-#define GC_BASE__INST3_SEG1 0
-#define GC_BASE__INST3_SEG2 0
-#define GC_BASE__INST3_SEG3 0
-#define GC_BASE__INST3_SEG4 0
-
-#define GC_BASE__INST4_SEG0 0
-#define GC_BASE__INST4_SEG1 0
-#define GC_BASE__INST4_SEG2 0
-#define GC_BASE__INST4_SEG3 0
-#define GC_BASE__INST4_SEG4 0
-
-#define GC_BASE__INST5_SEG0 0
-#define GC_BASE__INST5_SEG1 0
-#define GC_BASE__INST5_SEG2 0
-#define GC_BASE__INST5_SEG3 0
-#define GC_BASE__INST5_SEG4 0
-
-#define GC_BASE__INST6_SEG0 0
-#define GC_BASE__INST6_SEG1 0
-#define GC_BASE__INST6_SEG2 0
-#define GC_BASE__INST6_SEG3 0
-#define GC_BASE__INST6_SEG4 0
-
-#define HDA_BASE__INST0_SEG0 0x004C0000
-#define HDA_BASE__INST0_SEG1 0x02404800
-#define HDA_BASE__INST0_SEG2 0
-#define HDA_BASE__INST0_SEG3 0
-#define HDA_BASE__INST0_SEG4 0
-
-#define HDA_BASE__INST1_SEG0 0
-#define HDA_BASE__INST1_SEG1 0
-#define HDA_BASE__INST1_SEG2 0
-#define HDA_BASE__INST1_SEG3 0
-#define HDA_BASE__INST1_SEG4 0
-
-#define HDA_BASE__INST2_SEG0 0
-#define HDA_BASE__INST2_SEG1 0
-#define HDA_BASE__INST2_SEG2 0
-#define HDA_BASE__INST2_SEG3 0
-#define HDA_BASE__INST2_SEG4 0
-
-#define HDA_BASE__INST3_SEG0 0
-#define HDA_BASE__INST3_SEG1 0
-#define HDA_BASE__INST3_SEG2 0
-#define HDA_BASE__INST3_SEG3 0
-#define HDA_BASE__INST3_SEG4 0
-
-#define HDA_BASE__INST4_SEG0 0
-#define HDA_BASE__INST4_SEG1 0
-#define HDA_BASE__INST4_SEG2 0
-#define HDA_BASE__INST4_SEG3 0
-#define HDA_BASE__INST4_SEG4 0
-
-#define HDA_BASE__INST5_SEG0 0
-#define HDA_BASE__INST5_SEG1 0
-#define HDA_BASE__INST5_SEG2 0
-#define HDA_BASE__INST5_SEG3 0
-#define HDA_BASE__INST5_SEG4 0
-
-#define HDA_BASE__INST6_SEG0 0
-#define HDA_BASE__INST6_SEG1 0
-#define HDA_BASE__INST6_SEG2 0
-#define HDA_BASE__INST6_SEG3 0
-#define HDA_BASE__INST6_SEG4 0
-
-#define HDP_BASE__INST0_SEG0 0x00000F20
-#define HDP_BASE__INST0_SEG1 0x0240A400
-#define HDP_BASE__INST0_SEG2 0
-#define HDP_BASE__INST0_SEG3 0
-#define HDP_BASE__INST0_SEG4 0
-
-#define HDP_BASE__INST1_SEG0 0
-#define HDP_BASE__INST1_SEG1 0
-#define HDP_BASE__INST1_SEG2 0
-#define HDP_BASE__INST1_SEG3 0
-#define HDP_BASE__INST1_SEG4 0
-
-#define HDP_BASE__INST2_SEG0 0
-#define HDP_BASE__INST2_SEG1 0
-#define HDP_BASE__INST2_SEG2 0
-#define HDP_BASE__INST2_SEG3 0
-#define HDP_BASE__INST2_SEG4 0
-
-#define HDP_BASE__INST3_SEG0 0
-#define HDP_BASE__INST3_SEG1 0
-#define HDP_BASE__INST3_SEG2 0
-#define HDP_BASE__INST3_SEG3 0
-#define HDP_BASE__INST3_SEG4 0
-
-#define HDP_BASE__INST4_SEG0 0
-#define HDP_BASE__INST4_SEG1 0
-#define HDP_BASE__INST4_SEG2 0
-#define HDP_BASE__INST4_SEG3 0
-#define HDP_BASE__INST4_SEG4 0
-
-#define HDP_BASE__INST5_SEG0 0
-#define HDP_BASE__INST5_SEG1 0
-#define HDP_BASE__INST5_SEG2 0
-#define HDP_BASE__INST5_SEG3 0
-#define HDP_BASE__INST5_SEG4 0
-
-#define HDP_BASE__INST6_SEG0 0
-#define HDP_BASE__INST6_SEG1 0
-#define HDP_BASE__INST6_SEG2 0
-#define HDP_BASE__INST6_SEG3 0
-#define HDP_BASE__INST6_SEG4 0
-
-#define MMHUB_BASE__INST0_SEG0 0x0001A000
-#define MMHUB_BASE__INST0_SEG1 0x02408800
-#define MMHUB_BASE__INST0_SEG2 0
-#define MMHUB_BASE__INST0_SEG3 0
-#define MMHUB_BASE__INST0_SEG4 0
-
-#define MMHUB_BASE__INST1_SEG0 0
-#define MMHUB_BASE__INST1_SEG1 0
-#define MMHUB_BASE__INST1_SEG2 0
-#define MMHUB_BASE__INST1_SEG3 0
-#define MMHUB_BASE__INST1_SEG4 0
-
-#define MMHUB_BASE__INST2_SEG0 0
-#define MMHUB_BASE__INST2_SEG1 0
-#define MMHUB_BASE__INST2_SEG2 0
-#define MMHUB_BASE__INST2_SEG3 0
-#define MMHUB_BASE__INST2_SEG4 0
-
-#define MMHUB_BASE__INST3_SEG0 0
-#define MMHUB_BASE__INST3_SEG1 0
-#define MMHUB_BASE__INST3_SEG2 0
-#define MMHUB_BASE__INST3_SEG3 0
-#define MMHUB_BASE__INST3_SEG4 0
-
-#define MMHUB_BASE__INST4_SEG0 0
-#define MMHUB_BASE__INST4_SEG1 0
-#define MMHUB_BASE__INST4_SEG2 0
-#define MMHUB_BASE__INST4_SEG3 0
-#define MMHUB_BASE__INST4_SEG4 0
-
-#define MMHUB_BASE__INST5_SEG0 0
-#define MMHUB_BASE__INST5_SEG1 0
-#define MMHUB_BASE__INST5_SEG2 0
-#define MMHUB_BASE__INST5_SEG3 0
-#define MMHUB_BASE__INST5_SEG4 0
-
-#define MMHUB_BASE__INST6_SEG0 0
-#define MMHUB_BASE__INST6_SEG1 0
-#define MMHUB_BASE__INST6_SEG2 0
-#define MMHUB_BASE__INST6_SEG3 0
-#define MMHUB_BASE__INST6_SEG4 0
-
-#define MP0_BASE__INST0_SEG0 0x00016000
-#define MP0_BASE__INST0_SEG1 0x00DC0000
-#define MP0_BASE__INST0_SEG2 0x00E00000
-#define MP0_BASE__INST0_SEG3 0x00E40000
-#define MP0_BASE__INST0_SEG4 0x0243FC00
-
-#define MP0_BASE__INST1_SEG0 0
-#define MP0_BASE__INST1_SEG1 0
-#define MP0_BASE__INST1_SEG2 0
-#define MP0_BASE__INST1_SEG3 0
-#define MP0_BASE__INST1_SEG4 0
-
-#define MP0_BASE__INST2_SEG0 0
-#define MP0_BASE__INST2_SEG1 0
-#define MP0_BASE__INST2_SEG2 0
-#define MP0_BASE__INST2_SEG3 0
-#define MP0_BASE__INST2_SEG4 0
-
-#define MP0_BASE__INST3_SEG0 0
-#define MP0_BASE__INST3_SEG1 0
-#define MP0_BASE__INST3_SEG2 0
-#define MP0_BASE__INST3_SEG3 0
-#define MP0_BASE__INST3_SEG4 0
-
-#define MP0_BASE__INST4_SEG0 0
-#define MP0_BASE__INST4_SEG1 0
-#define MP0_BASE__INST4_SEG2 0
-#define MP0_BASE__INST4_SEG3 0
-#define MP0_BASE__INST4_SEG4 0
-
-#define MP0_BASE__INST5_SEG0 0
-#define MP0_BASE__INST5_SEG1 0
-#define MP0_BASE__INST5_SEG2 0
-#define MP0_BASE__INST5_SEG3 0
-#define MP0_BASE__INST5_SEG4 0
-
-#define MP0_BASE__INST6_SEG0 0
-#define MP0_BASE__INST6_SEG1 0
-#define MP0_BASE__INST6_SEG2 0
-#define MP0_BASE__INST6_SEG3 0
-#define MP0_BASE__INST6_SEG4 0
-
-#define MP1_BASE__INST0_SEG0 0x00016200
-#define MP1_BASE__INST0_SEG1 0x00E80000
-#define MP1_BASE__INST0_SEG2 0x00EC0000
-#define MP1_BASE__INST0_SEG3 0x00F00000
-#define MP1_BASE__INST0_SEG4 0x02400400
-
-#define MP1_BASE__INST1_SEG0 0
-#define MP1_BASE__INST1_SEG1 0
-#define MP1_BASE__INST1_SEG2 0
-#define MP1_BASE__INST1_SEG3 0
-#define MP1_BASE__INST1_SEG4 0
-
-#define MP1_BASE__INST2_SEG0 0
-#define MP1_BASE__INST2_SEG1 0
-#define MP1_BASE__INST2_SEG2 0
-#define MP1_BASE__INST2_SEG3 0
-#define MP1_BASE__INST2_SEG4 0
-
-#define MP1_BASE__INST3_SEG0 0
-#define MP1_BASE__INST3_SEG1 0
-#define MP1_BASE__INST3_SEG2 0
-#define MP1_BASE__INST3_SEG3 0
-#define MP1_BASE__INST3_SEG4 0
-
-#define MP1_BASE__INST4_SEG0 0
-#define MP1_BASE__INST4_SEG1 0
-#define MP1_BASE__INST4_SEG2 0
-#define MP1_BASE__INST4_SEG3 0
-#define MP1_BASE__INST4_SEG4 0
-
-#define MP1_BASE__INST5_SEG0 0
-#define MP1_BASE__INST5_SEG1 0
-#define MP1_BASE__INST5_SEG2 0
-#define MP1_BASE__INST5_SEG3 0
-#define MP1_BASE__INST5_SEG4 0
-
-#define MP1_BASE__INST6_SEG0 0
-#define MP1_BASE__INST6_SEG1 0
-#define MP1_BASE__INST6_SEG2 0
-#define MP1_BASE__INST6_SEG3 0
-#define MP1_BASE__INST6_SEG4 0
-
-#define NBIF0_BASE__INST0_SEG0 0x00000000
-#define NBIF0_BASE__INST0_SEG1 0x00000014
-#define NBIF0_BASE__INST0_SEG2 0x00000D20
-#define NBIF0_BASE__INST0_SEG3 0x00010400
-#define NBIF0_BASE__INST0_SEG4 0x0241B000
-
-#define NBIF0_BASE__INST1_SEG0 0
-#define NBIF0_BASE__INST1_SEG1 0
-#define NBIF0_BASE__INST1_SEG2 0
-#define NBIF0_BASE__INST1_SEG3 0
-#define NBIF0_BASE__INST1_SEG4 0
-
-#define NBIF0_BASE__INST2_SEG0 0
-#define NBIF0_BASE__INST2_SEG1 0
-#define NBIF0_BASE__INST2_SEG2 0
-#define NBIF0_BASE__INST2_SEG3 0
-#define NBIF0_BASE__INST2_SEG4 0
-
-#define NBIF0_BASE__INST3_SEG0 0
-#define NBIF0_BASE__INST3_SEG1 0
-#define NBIF0_BASE__INST3_SEG2 0
-#define NBIF0_BASE__INST3_SEG3 0
-#define NBIF0_BASE__INST3_SEG4 0
-
-#define NBIF0_BASE__INST4_SEG0 0
-#define NBIF0_BASE__INST4_SEG1 0
-#define NBIF0_BASE__INST4_SEG2 0
-#define NBIF0_BASE__INST4_SEG3 0
-#define NBIF0_BASE__INST4_SEG4 0
-
-#define NBIF0_BASE__INST5_SEG0 0
-#define NBIF0_BASE__INST5_SEG1 0
-#define NBIF0_BASE__INST5_SEG2 0
-#define NBIF0_BASE__INST5_SEG3 0
-#define NBIF0_BASE__INST5_SEG4 0
-
-#define NBIF0_BASE__INST6_SEG0 0
-#define NBIF0_BASE__INST6_SEG1 0
-#define NBIF0_BASE__INST6_SEG2 0
-#define NBIF0_BASE__INST6_SEG3 0
-#define NBIF0_BASE__INST6_SEG4 0
-
-#define OSSSYS_BASE__INST0_SEG0 0x000010A0
-#define OSSSYS_BASE__INST0_SEG1 0x0240A000
-#define OSSSYS_BASE__INST0_SEG2 0
-#define OSSSYS_BASE__INST0_SEG3 0
-#define OSSSYS_BASE__INST0_SEG4 0
-
-#define OSSSYS_BASE__INST1_SEG0 0
-#define OSSSYS_BASE__INST1_SEG1 0
-#define OSSSYS_BASE__INST1_SEG2 0
-#define OSSSYS_BASE__INST1_SEG3 0
-#define OSSSYS_BASE__INST1_SEG4 0
-
-#define OSSSYS_BASE__INST2_SEG0 0
-#define OSSSYS_BASE__INST2_SEG1 0
-#define OSSSYS_BASE__INST2_SEG2 0
-#define OSSSYS_BASE__INST2_SEG3 0
-#define OSSSYS_BASE__INST2_SEG4 0
-
-#define OSSSYS_BASE__INST3_SEG0 0
-#define OSSSYS_BASE__INST3_SEG1 0
-#define OSSSYS_BASE__INST3_SEG2 0
-#define OSSSYS_BASE__INST3_SEG3 0
-#define OSSSYS_BASE__INST3_SEG4 0
-
-#define OSSSYS_BASE__INST4_SEG0 0
-#define OSSSYS_BASE__INST4_SEG1 0
-#define OSSSYS_BASE__INST4_SEG2 0
-#define OSSSYS_BASE__INST4_SEG3 0
-#define OSSSYS_BASE__INST4_SEG4 0
-
-#define OSSSYS_BASE__INST5_SEG0 0
-#define OSSSYS_BASE__INST5_SEG1 0
-#define OSSSYS_BASE__INST5_SEG2 0
-#define OSSSYS_BASE__INST5_SEG3 0
-#define OSSSYS_BASE__INST5_SEG4 0
-
-#define OSSSYS_BASE__INST6_SEG0 0
-#define OSSSYS_BASE__INST6_SEG1 0
-#define OSSSYS_BASE__INST6_SEG2 0
-#define OSSSYS_BASE__INST6_SEG3 0
-#define OSSSYS_BASE__INST6_SEG4 0
-
-#define PCIE0_BASE__INST0_SEG0 0x02411800
-#define PCIE0_BASE__INST0_SEG1 0x04440000
-#define PCIE0_BASE__INST0_SEG2 0
-#define PCIE0_BASE__INST0_SEG3 0
-#define PCIE0_BASE__INST0_SEG4 0
-
-#define PCIE0_BASE__INST1_SEG0 0
-#define PCIE0_BASE__INST1_SEG1 0
-#define PCIE0_BASE__INST1_SEG2 0
-#define PCIE0_BASE__INST1_SEG3 0
-#define PCIE0_BASE__INST1_SEG4 0
-
-#define PCIE0_BASE__INST2_SEG0 0
-#define PCIE0_BASE__INST2_SEG1 0
-#define PCIE0_BASE__INST2_SEG2 0
-#define PCIE0_BASE__INST2_SEG3 0
-#define PCIE0_BASE__INST2_SEG4 0
-
-#define PCIE0_BASE__INST3_SEG0 0
-#define PCIE0_BASE__INST3_SEG1 0
-#define PCIE0_BASE__INST3_SEG2 0
-#define PCIE0_BASE__INST3_SEG3 0
-#define PCIE0_BASE__INST3_SEG4 0
-
-#define PCIE0_BASE__INST4_SEG0 0
-#define PCIE0_BASE__INST4_SEG1 0
-#define PCIE0_BASE__INST4_SEG2 0
-#define PCIE0_BASE__INST4_SEG3 0
-#define PCIE0_BASE__INST4_SEG4 0
-
-#define PCIE0_BASE__INST5_SEG0 0
-#define PCIE0_BASE__INST5_SEG1 0
-#define PCIE0_BASE__INST5_SEG2 0
-#define PCIE0_BASE__INST5_SEG3 0
-#define PCIE0_BASE__INST5_SEG4 0
-
-#define PCIE0_BASE__INST6_SEG0 0
-#define PCIE0_BASE__INST6_SEG1 0
-#define PCIE0_BASE__INST6_SEG2 0
-#define PCIE0_BASE__INST6_SEG3 0
-#define PCIE0_BASE__INST6_SEG4 0
-
-#define SDMA_BASE__INST0_SEG0 0x00001260
-#define SDMA_BASE__INST0_SEG1 0x0000A000
-#define SDMA_BASE__INST0_SEG2 0x02402C00
-#define SDMA_BASE__INST0_SEG3 0
-#define SDMA_BASE__INST0_SEG4 0
-
-#define SDMA_BASE__INST1_SEG0 0x00001260
-#define SDMA_BASE__INST1_SEG1 0x0000A000
-#define SDMA_BASE__INST1_SEG2 0x02402C00
-#define SDMA_BASE__INST1_SEG3 0
-#define SDMA_BASE__INST1_SEG4 0
-
-#define SDMA_BASE__INST2_SEG0 0
-#define SDMA_BASE__INST2_SEG1 0
-#define SDMA_BASE__INST2_SEG2 0
-#define SDMA_BASE__INST2_SEG3 0
-#define SDMA_BASE__INST2_SEG4 0
-
-#define SDMA_BASE__INST3_SEG0 0
-#define SDMA_BASE__INST3_SEG1 0
-#define SDMA_BASE__INST3_SEG2 0
-#define SDMA_BASE__INST3_SEG3 0
-#define SDMA_BASE__INST3_SEG4 0
-
-#define SDMA_BASE__INST4_SEG0 0
-#define SDMA_BASE__INST4_SEG1 0
-#define SDMA_BASE__INST4_SEG2 0
-#define SDMA_BASE__INST4_SEG3 0
-#define SDMA_BASE__INST4_SEG4 0
-
-#define SDMA_BASE__INST5_SEG0 0
-#define SDMA_BASE__INST5_SEG1 0
-#define SDMA_BASE__INST5_SEG2 0
-#define SDMA_BASE__INST5_SEG3 0
-#define SDMA_BASE__INST5_SEG4 0
-
-#define SDMA_BASE__INST6_SEG0 0
-#define SDMA_BASE__INST6_SEG1 0
-#define SDMA_BASE__INST6_SEG2 0
-#define SDMA_BASE__INST6_SEG3 0
-#define SDMA_BASE__INST6_SEG4 0
-
-#define SMUIO_BASE__INST0_SEG0 0x00016800
-#define SMUIO_BASE__INST0_SEG1 0x00016A00
-#define SMUIO_BASE__INST0_SEG2 0x00440000
-#define SMUIO_BASE__INST0_SEG3 0x02401000
-#define SMUIO_BASE__INST0_SEG4 0
-
-#define SMUIO_BASE__INST1_SEG0 0
-#define SMUIO_BASE__INST1_SEG1 0
-#define SMUIO_BASE__INST1_SEG2 0
-#define SMUIO_BASE__INST1_SEG3 0
-#define SMUIO_BASE__INST1_SEG4 0
-
-#define SMUIO_BASE__INST2_SEG0 0
-#define SMUIO_BASE__INST2_SEG1 0
-#define SMUIO_BASE__INST2_SEG2 0
-#define SMUIO_BASE__INST2_SEG3 0
-#define SMUIO_BASE__INST2_SEG4 0
-
-#define SMUIO_BASE__INST3_SEG0 0
-#define SMUIO_BASE__INST3_SEG1 0
-#define SMUIO_BASE__INST3_SEG2 0
-#define SMUIO_BASE__INST3_SEG3 0
-#define SMUIO_BASE__INST3_SEG4 0
-
-#define SMUIO_BASE__INST4_SEG0 0
-#define SMUIO_BASE__INST4_SEG1 0
-#define SMUIO_BASE__INST4_SEG2 0
-#define SMUIO_BASE__INST4_SEG3 0
-#define SMUIO_BASE__INST4_SEG4 0
-
-#define SMUIO_BASE__INST5_SEG0 0
-#define SMUIO_BASE__INST5_SEG1 0
-#define SMUIO_BASE__INST5_SEG2 0
-#define SMUIO_BASE__INST5_SEG3 0
-#define SMUIO_BASE__INST5_SEG4 0
-
-#define SMUIO_BASE__INST6_SEG0 0
-#define SMUIO_BASE__INST6_SEG1 0
-#define SMUIO_BASE__INST6_SEG2 0
-#define SMUIO_BASE__INST6_SEG3 0
-#define SMUIO_BASE__INST6_SEG4 0
-
-#define THM_BASE__INST0_SEG0 0x00016600
-#define THM_BASE__INST0_SEG1 0x02400C00
-#define THM_BASE__INST0_SEG2 0
-#define THM_BASE__INST0_SEG3 0
-#define THM_BASE__INST0_SEG4 0
-
-#define THM_BASE__INST1_SEG0 0
-#define THM_BASE__INST1_SEG1 0
-#define THM_BASE__INST1_SEG2 0
-#define THM_BASE__INST1_SEG3 0
-#define THM_BASE__INST1_SEG4 0
-
-#define THM_BASE__INST2_SEG0 0
-#define THM_BASE__INST2_SEG1 0
-#define THM_BASE__INST2_SEG2 0
-#define THM_BASE__INST2_SEG3 0
-#define THM_BASE__INST2_SEG4 0
-
-#define THM_BASE__INST3_SEG0 0
-#define THM_BASE__INST3_SEG1 0
-#define THM_BASE__INST3_SEG2 0
-#define THM_BASE__INST3_SEG3 0
-#define THM_BASE__INST3_SEG4 0
-
-#define THM_BASE__INST4_SEG0 0
-#define THM_BASE__INST4_SEG1 0
-#define THM_BASE__INST4_SEG2 0
-#define THM_BASE__INST4_SEG3 0
-#define THM_BASE__INST4_SEG4 0
-
-#define THM_BASE__INST5_SEG0 0
-#define THM_BASE__INST5_SEG1 0
-#define THM_BASE__INST5_SEG2 0
-#define THM_BASE__INST5_SEG3 0
-#define THM_BASE__INST5_SEG4 0
-
-#define THM_BASE__INST6_SEG0 0
-#define THM_BASE__INST6_SEG1 0
-#define THM_BASE__INST6_SEG2 0
-#define THM_BASE__INST6_SEG3 0
-#define THM_BASE__INST6_SEG4 0
-
-#define UMC_BASE__INST0_SEG0 0x00014000
-#define UMC_BASE__INST0_SEG1 0x02425800
-#define UMC_BASE__INST0_SEG2 0
-#define UMC_BASE__INST0_SEG3 0
-#define UMC_BASE__INST0_SEG4 0
-
-#define UMC_BASE__INST1_SEG0 0x00054000
-#define UMC_BASE__INST1_SEG1 0x02425C00
-#define UMC_BASE__INST1_SEG2 0
-#define UMC_BASE__INST1_SEG3 0
-#define UMC_BASE__INST1_SEG4 0
-
-#define UMC_BASE__INST2_SEG0 0x00094000
-#define UMC_BASE__INST2_SEG1 0x02426000
-#define UMC_BASE__INST2_SEG2 0
-#define UMC_BASE__INST2_SEG3 0
-#define UMC_BASE__INST2_SEG4 0
-
-#define UMC_BASE__INST3_SEG0 0x000D4000
-#define UMC_BASE__INST3_SEG1 0x02426400
-#define UMC_BASE__INST3_SEG2 0
-#define UMC_BASE__INST3_SEG3 0
-#define UMC_BASE__INST3_SEG4 0
-
-#define UMC_BASE__INST4_SEG0 0
-#define UMC_BASE__INST4_SEG1 0
-#define UMC_BASE__INST4_SEG2 0
-#define UMC_BASE__INST4_SEG3 0
-#define UMC_BASE__INST4_SEG4 0
-
-#define UMC_BASE__INST5_SEG0 0
-#define UMC_BASE__INST5_SEG1 0
-#define UMC_BASE__INST5_SEG2 0
-#define UMC_BASE__INST5_SEG3 0
-#define UMC_BASE__INST5_SEG4 0
-
-#define UMC_BASE__INST6_SEG0 0
-#define UMC_BASE__INST6_SEG1 0
-#define UMC_BASE__INST6_SEG2 0
-#define UMC_BASE__INST6_SEG3 0
-#define UMC_BASE__INST6_SEG4 0
-
-#define USB0_BASE__INST0_SEG0 0x0242A800
-#define USB0_BASE__INST0_SEG1 0x05B00000
-#define USB0_BASE__INST0_SEG2 0
-#define USB0_BASE__INST0_SEG3 0
-#define USB0_BASE__INST0_SEG4 0
-
-#define USB0_BASE__INST1_SEG0 0
-#define USB0_BASE__INST1_SEG1 0
-#define USB0_BASE__INST1_SEG2 0
-#define USB0_BASE__INST1_SEG3 0
-#define USB0_BASE__INST1_SEG4 0
-
-#define USB0_BASE__INST2_SEG0 0
-#define USB0_BASE__INST2_SEG1 0
-#define USB0_BASE__INST2_SEG2 0
-#define USB0_BASE__INST2_SEG3 0
-#define USB0_BASE__INST2_SEG4 0
-
-#define USB0_BASE__INST3_SEG0 0
-#define USB0_BASE__INST3_SEG1 0
-#define USB0_BASE__INST3_SEG2 0
-#define USB0_BASE__INST3_SEG3 0
-#define USB0_BASE__INST3_SEG4 0
-
-#define USB0_BASE__INST4_SEG0 0
-#define USB0_BASE__INST4_SEG1 0
-#define USB0_BASE__INST4_SEG2 0
-#define USB0_BASE__INST4_SEG3 0
-#define USB0_BASE__INST4_SEG4 0
-
-#define USB0_BASE__INST5_SEG0 0
-#define USB0_BASE__INST5_SEG1 0
-#define USB0_BASE__INST5_SEG2 0
-#define USB0_BASE__INST5_SEG3 0
-#define USB0_BASE__INST5_SEG4 0
-
-#define USB0_BASE__INST6_SEG0 0
-#define USB0_BASE__INST6_SEG1 0
-#define USB0_BASE__INST6_SEG2 0
-#define USB0_BASE__INST6_SEG3 0
-#define USB0_BASE__INST6_SEG4 0
-
-#define UVD0_BASE__INST0_SEG0 0x00007800
-#define UVD0_BASE__INST0_SEG1 0x00007E00
-#define UVD0_BASE__INST0_SEG2 0x02403000
-#define UVD0_BASE__INST0_SEG3 0
-#define UVD0_BASE__INST0_SEG4 0
-
-#define UVD0_BASE__INST1_SEG0 0
-#define UVD0_BASE__INST1_SEG1 0
-#define UVD0_BASE__INST1_SEG2 0
-#define UVD0_BASE__INST1_SEG3 0
-#define UVD0_BASE__INST1_SEG4 0
-
-#define UVD0_BASE__INST2_SEG0 0
-#define UVD0_BASE__INST2_SEG1 0
-#define UVD0_BASE__INST2_SEG2 0
-#define UVD0_BASE__INST2_SEG3 0
-#define UVD0_BASE__INST2_SEG4 0
-
-#define UVD0_BASE__INST3_SEG0 0
-#define UVD0_BASE__INST3_SEG1 0
-#define UVD0_BASE__INST3_SEG2 0
-#define UVD0_BASE__INST3_SEG3 0
-#define UVD0_BASE__INST3_SEG4 0
-
-#define UVD0_BASE__INST4_SEG0 0
-#define UVD0_BASE__INST4_SEG1 0
-#define UVD0_BASE__INST4_SEG2 0
-#define UVD0_BASE__INST4_SEG3 0
-#define UVD0_BASE__INST4_SEG4 0
-
-#define UVD0_BASE__INST5_SEG0 0
-#define UVD0_BASE__INST5_SEG1 0
-#define UVD0_BASE__INST5_SEG2 0
-#define UVD0_BASE__INST5_SEG3 0
-#define UVD0_BASE__INST5_SEG4 0
-
-#define UVD0_BASE__INST6_SEG0 0
-#define UVD0_BASE__INST6_SEG1 0
-#define UVD0_BASE__INST6_SEG2 0
-#define UVD0_BASE__INST6_SEG3 0
-#define UVD0_BASE__INST6_SEG4 0
-
-#endif
diff --git a/drivers/gpu/drm/amd/include/navi14_ip_offset.h b/drivers/gpu/drm/amd/include/navi14_ip_offset.h
deleted file mode 100644
index 508011288..000000000
--- a/drivers/gpu/drm/amd/include/navi14_ip_offset.h
+++ /dev/null
@@ -1,1117 +0,0 @@
-/*
- * Copyright (C) 2018 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _navi14_ip_offset_HEADER
-#define _navi14_ip_offset_HEADER
-
-#define MAX_INSTANCE 7
-#define MAX_SEGMENT 5
-
-
-struct IP_BASE_INSTANCE {
- unsigned int segment[MAX_SEGMENT];
-};
-
-struct IP_BASE {
- struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
-} __maybe_unused;
-
-
-static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C00, 0x02408C00, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x02401800, 0, 0, 0 } },
- { { 0x00016E00, 0x02401C00, 0, 0, 0 } },
- { { 0x00017000, 0x02402000, 0, 0, 0 } },
- { { 0x00017200, 0x02402400, 0, 0, 0 } },
- { { 0x0001B000, 0x0242D800, 0, 0, 0 } },
- { { 0x00017E00, 0x0240BC00, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x0240B800, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE DIO_BASE ={ { { { 0x02404000, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE DPCS_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0x02401400, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE GC_BASE ={ { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE HDA_BASE ={ { { { 0x004C0000, 0x02404800, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x0240A400, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x0240A000, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE PCIE0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE SDMA_BASE ={ { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } },
- { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0x00440000, 0x02401000, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0x02425800, 0, 0, 0 } },
- { { 0x00054000, 0x02425C00, 0, 0, 0 } },
- { { 0x00094000, 0x02426000, 0, 0, 0 } },
- { { 0x000D4000, 0x02426400, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE USB0_BASE ={ { { { 0x0242A800, 0x05B00000, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-
-
-#define ATHUB_BASE__INST0_SEG0 0x00000C00
-#define ATHUB_BASE__INST0_SEG1 0x02408C00
-#define ATHUB_BASE__INST0_SEG2 0
-#define ATHUB_BASE__INST0_SEG3 0
-#define ATHUB_BASE__INST0_SEG4 0
-
-#define ATHUB_BASE__INST1_SEG0 0
-#define ATHUB_BASE__INST1_SEG1 0
-#define ATHUB_BASE__INST1_SEG2 0
-#define ATHUB_BASE__INST1_SEG3 0
-#define ATHUB_BASE__INST1_SEG4 0
-
-#define ATHUB_BASE__INST2_SEG0 0
-#define ATHUB_BASE__INST2_SEG1 0
-#define ATHUB_BASE__INST2_SEG2 0
-#define ATHUB_BASE__INST2_SEG3 0
-#define ATHUB_BASE__INST2_SEG4 0
-
-#define ATHUB_BASE__INST3_SEG0 0
-#define ATHUB_BASE__INST3_SEG1 0
-#define ATHUB_BASE__INST3_SEG2 0
-#define ATHUB_BASE__INST3_SEG3 0
-#define ATHUB_BASE__INST3_SEG4 0
-
-#define ATHUB_BASE__INST4_SEG0 0
-#define ATHUB_BASE__INST4_SEG1 0
-#define ATHUB_BASE__INST4_SEG2 0
-#define ATHUB_BASE__INST4_SEG3 0
-#define ATHUB_BASE__INST4_SEG4 0
-
-#define ATHUB_BASE__INST5_SEG0 0
-#define ATHUB_BASE__INST5_SEG1 0
-#define ATHUB_BASE__INST5_SEG2 0
-#define ATHUB_BASE__INST5_SEG3 0
-#define ATHUB_BASE__INST5_SEG4 0
-
-#define ATHUB_BASE__INST6_SEG0 0
-#define ATHUB_BASE__INST6_SEG1 0
-#define ATHUB_BASE__INST6_SEG2 0
-#define ATHUB_BASE__INST6_SEG3 0
-#define ATHUB_BASE__INST6_SEG4 0
-
-#define CLK_BASE__INST0_SEG0 0x00016C00
-#define CLK_BASE__INST0_SEG1 0x02401800
-#define CLK_BASE__INST0_SEG2 0
-#define CLK_BASE__INST0_SEG3 0
-#define CLK_BASE__INST0_SEG4 0
-
-#define CLK_BASE__INST1_SEG0 0x00016E00
-#define CLK_BASE__INST1_SEG1 0x02401C00
-#define CLK_BASE__INST1_SEG2 0
-#define CLK_BASE__INST1_SEG3 0
-#define CLK_BASE__INST1_SEG4 0
-
-#define CLK_BASE__INST2_SEG0 0x00017000
-#define CLK_BASE__INST2_SEG1 0x02402000
-#define CLK_BASE__INST2_SEG2 0
-#define CLK_BASE__INST2_SEG3 0
-#define CLK_BASE__INST2_SEG4 0
-
-#define CLK_BASE__INST3_SEG0 0x00017200
-#define CLK_BASE__INST3_SEG1 0x02402400
-#define CLK_BASE__INST3_SEG2 0
-#define CLK_BASE__INST3_SEG3 0
-#define CLK_BASE__INST3_SEG4 0
-
-#define CLK_BASE__INST4_SEG0 0x0001B000
-#define CLK_BASE__INST4_SEG1 0x0242D800
-#define CLK_BASE__INST4_SEG2 0
-#define CLK_BASE__INST4_SEG3 0
-#define CLK_BASE__INST4_SEG4 0
-
-#define CLK_BASE__INST5_SEG0 0x00017E00
-#define CLK_BASE__INST5_SEG1 0x0240BC00
-#define CLK_BASE__INST5_SEG2 0
-#define CLK_BASE__INST5_SEG3 0
-#define CLK_BASE__INST5_SEG4 0
-
-#define CLK_BASE__INST6_SEG0 0
-#define CLK_BASE__INST6_SEG1 0
-#define CLK_BASE__INST6_SEG2 0
-#define CLK_BASE__INST6_SEG3 0
-#define CLK_BASE__INST6_SEG4 0
-
-#define DF_BASE__INST0_SEG0 0x00007000
-#define DF_BASE__INST0_SEG1 0x0240B800
-#define DF_BASE__INST0_SEG2 0
-#define DF_BASE__INST0_SEG3 0
-#define DF_BASE__INST0_SEG4 0
-
-#define DF_BASE__INST1_SEG0 0
-#define DF_BASE__INST1_SEG1 0
-#define DF_BASE__INST1_SEG2 0
-#define DF_BASE__INST1_SEG3 0
-#define DF_BASE__INST1_SEG4 0
-
-#define DF_BASE__INST2_SEG0 0
-#define DF_BASE__INST2_SEG1 0
-#define DF_BASE__INST2_SEG2 0
-#define DF_BASE__INST2_SEG3 0
-#define DF_BASE__INST2_SEG4 0
-
-#define DF_BASE__INST3_SEG0 0
-#define DF_BASE__INST3_SEG1 0
-#define DF_BASE__INST3_SEG2 0
-#define DF_BASE__INST3_SEG3 0
-#define DF_BASE__INST3_SEG4 0
-
-#define DF_BASE__INST4_SEG0 0
-#define DF_BASE__INST4_SEG1 0
-#define DF_BASE__INST4_SEG2 0
-#define DF_BASE__INST4_SEG3 0
-#define DF_BASE__INST4_SEG4 0
-
-#define DF_BASE__INST5_SEG0 0
-#define DF_BASE__INST5_SEG1 0
-#define DF_BASE__INST5_SEG2 0
-#define DF_BASE__INST5_SEG3 0
-#define DF_BASE__INST5_SEG4 0
-
-#define DF_BASE__INST6_SEG0 0
-#define DF_BASE__INST6_SEG1 0
-#define DF_BASE__INST6_SEG2 0
-#define DF_BASE__INST6_SEG3 0
-#define DF_BASE__INST6_SEG4 0
-
-#define DIO_BASE__INST0_SEG0 0x02404000
-#define DIO_BASE__INST0_SEG1 0
-#define DIO_BASE__INST0_SEG2 0
-#define DIO_BASE__INST0_SEG3 0
-#define DIO_BASE__INST0_SEG4 0
-
-#define DIO_BASE__INST1_SEG0 0
-#define DIO_BASE__INST1_SEG1 0
-#define DIO_BASE__INST1_SEG2 0
-#define DIO_BASE__INST1_SEG3 0
-#define DIO_BASE__INST1_SEG4 0
-
-#define DIO_BASE__INST2_SEG0 0
-#define DIO_BASE__INST2_SEG1 0
-#define DIO_BASE__INST2_SEG2 0
-#define DIO_BASE__INST2_SEG3 0
-#define DIO_BASE__INST2_SEG4 0
-
-#define DIO_BASE__INST3_SEG0 0
-#define DIO_BASE__INST3_SEG1 0
-#define DIO_BASE__INST3_SEG2 0
-#define DIO_BASE__INST3_SEG3 0
-#define DIO_BASE__INST3_SEG4 0
-
-#define DIO_BASE__INST4_SEG0 0
-#define DIO_BASE__INST4_SEG1 0
-#define DIO_BASE__INST4_SEG2 0
-#define DIO_BASE__INST4_SEG3 0
-#define DIO_BASE__INST4_SEG4 0
-
-#define DIO_BASE__INST5_SEG0 0
-#define DIO_BASE__INST5_SEG1 0
-#define DIO_BASE__INST5_SEG2 0
-#define DIO_BASE__INST5_SEG3 0
-#define DIO_BASE__INST5_SEG4 0
-
-#define DIO_BASE__INST6_SEG0 0
-#define DIO_BASE__INST6_SEG1 0
-#define DIO_BASE__INST6_SEG2 0
-#define DIO_BASE__INST6_SEG3 0
-#define DIO_BASE__INST6_SEG4 0
-
-#define DMU_BASE__INST0_SEG0 0x00000012
-#define DMU_BASE__INST0_SEG1 0x000000C0
-#define DMU_BASE__INST0_SEG2 0x000034C0
-#define DMU_BASE__INST0_SEG3 0x00009000
-#define DMU_BASE__INST0_SEG4 0x02403C00
-
-#define DMU_BASE__INST1_SEG0 0
-#define DMU_BASE__INST1_SEG1 0
-#define DMU_BASE__INST1_SEG2 0
-#define DMU_BASE__INST1_SEG3 0
-#define DMU_BASE__INST1_SEG4 0
-
-#define DMU_BASE__INST2_SEG0 0
-#define DMU_BASE__INST2_SEG1 0
-#define DMU_BASE__INST2_SEG2 0
-#define DMU_BASE__INST2_SEG3 0
-#define DMU_BASE__INST2_SEG4 0
-
-#define DMU_BASE__INST3_SEG0 0
-#define DMU_BASE__INST3_SEG1 0
-#define DMU_BASE__INST3_SEG2 0
-#define DMU_BASE__INST3_SEG3 0
-#define DMU_BASE__INST3_SEG4 0
-
-#define DMU_BASE__INST4_SEG0 0
-#define DMU_BASE__INST4_SEG1 0
-#define DMU_BASE__INST4_SEG2 0
-#define DMU_BASE__INST4_SEG3 0
-#define DMU_BASE__INST4_SEG4 0
-
-#define DMU_BASE__INST5_SEG0 0
-#define DMU_BASE__INST5_SEG1 0
-#define DMU_BASE__INST5_SEG2 0
-#define DMU_BASE__INST5_SEG3 0
-#define DMU_BASE__INST5_SEG4 0
-
-#define DMU_BASE__INST6_SEG0 0
-#define DMU_BASE__INST6_SEG1 0
-#define DMU_BASE__INST6_SEG2 0
-#define DMU_BASE__INST6_SEG3 0
-#define DMU_BASE__INST6_SEG4 0
-
-#define DPCS_BASE__INST0_SEG0 0x00000012
-#define DPCS_BASE__INST0_SEG1 0x000000C0
-#define DPCS_BASE__INST0_SEG2 0x000034C0
-#define DPCS_BASE__INST0_SEG3 0x00009000
-#define DPCS_BASE__INST0_SEG4 0x02403C00
-
-#define DPCS_BASE__INST1_SEG0 0
-#define DPCS_BASE__INST1_SEG1 0
-#define DPCS_BASE__INST1_SEG2 0
-#define DPCS_BASE__INST1_SEG3 0
-#define DPCS_BASE__INST1_SEG4 0
-
-#define DPCS_BASE__INST2_SEG0 0
-#define DPCS_BASE__INST2_SEG1 0
-#define DPCS_BASE__INST2_SEG2 0
-#define DPCS_BASE__INST2_SEG3 0
-#define DPCS_BASE__INST2_SEG4 0
-
-#define DPCS_BASE__INST3_SEG0 0
-#define DPCS_BASE__INST3_SEG1 0
-#define DPCS_BASE__INST3_SEG2 0
-#define DPCS_BASE__INST3_SEG3 0
-#define DPCS_BASE__INST3_SEG4 0
-
-#define DPCS_BASE__INST4_SEG0 0
-#define DPCS_BASE__INST4_SEG1 0
-#define DPCS_BASE__INST4_SEG2 0
-#define DPCS_BASE__INST4_SEG3 0
-#define DPCS_BASE__INST4_SEG4 0
-
-#define DPCS_BASE__INST5_SEG0 0
-#define DPCS_BASE__INST5_SEG1 0
-#define DPCS_BASE__INST5_SEG2 0
-#define DPCS_BASE__INST5_SEG3 0
-#define DPCS_BASE__INST5_SEG4 0
-
-#define DPCS_BASE__INST6_SEG0 0
-#define DPCS_BASE__INST6_SEG1 0
-#define DPCS_BASE__INST6_SEG2 0
-#define DPCS_BASE__INST6_SEG3 0
-#define DPCS_BASE__INST6_SEG4 0
-
-#define FUSE_BASE__INST0_SEG0 0x00017400
-#define FUSE_BASE__INST0_SEG1 0x02401400
-#define FUSE_BASE__INST0_SEG2 0
-#define FUSE_BASE__INST0_SEG3 0
-#define FUSE_BASE__INST0_SEG4 0
-
-#define FUSE_BASE__INST1_SEG0 0
-#define FUSE_BASE__INST1_SEG1 0
-#define FUSE_BASE__INST1_SEG2 0
-#define FUSE_BASE__INST1_SEG3 0
-#define FUSE_BASE__INST1_SEG4 0
-
-#define FUSE_BASE__INST2_SEG0 0
-#define FUSE_BASE__INST2_SEG1 0
-#define FUSE_BASE__INST2_SEG2 0
-#define FUSE_BASE__INST2_SEG3 0
-#define FUSE_BASE__INST2_SEG4 0
-
-#define FUSE_BASE__INST3_SEG0 0
-#define FUSE_BASE__INST3_SEG1 0
-#define FUSE_BASE__INST3_SEG2 0
-#define FUSE_BASE__INST3_SEG3 0
-#define FUSE_BASE__INST3_SEG4 0
-
-#define FUSE_BASE__INST4_SEG0 0
-#define FUSE_BASE__INST4_SEG1 0
-#define FUSE_BASE__INST4_SEG2 0
-#define FUSE_BASE__INST4_SEG3 0
-#define FUSE_BASE__INST4_SEG4 0
-
-#define FUSE_BASE__INST5_SEG0 0
-#define FUSE_BASE__INST5_SEG1 0
-#define FUSE_BASE__INST5_SEG2 0
-#define FUSE_BASE__INST5_SEG3 0
-#define FUSE_BASE__INST5_SEG4 0
-
-#define FUSE_BASE__INST6_SEG0 0
-#define FUSE_BASE__INST6_SEG1 0
-#define FUSE_BASE__INST6_SEG2 0
-#define FUSE_BASE__INST6_SEG3 0
-#define FUSE_BASE__INST6_SEG4 0
-
-#define GC_BASE__INST0_SEG0 0x00001260
-#define GC_BASE__INST0_SEG1 0x0000A000
-#define GC_BASE__INST0_SEG2 0x02402C00
-#define GC_BASE__INST0_SEG3 0
-#define GC_BASE__INST0_SEG4 0
-
-#define GC_BASE__INST1_SEG0 0
-#define GC_BASE__INST1_SEG1 0
-#define GC_BASE__INST1_SEG2 0
-#define GC_BASE__INST1_SEG3 0
-#define GC_BASE__INST1_SEG4 0
-
-#define GC_BASE__INST2_SEG0 0
-#define GC_BASE__INST2_SEG1 0
-#define GC_BASE__INST2_SEG2 0
-#define GC_BASE__INST2_SEG3 0
-#define GC_BASE__INST2_SEG4 0
-
-#define GC_BASE__INST3_SEG0 0
-#define GC_BASE__INST3_SEG1 0
-#define GC_BASE__INST3_SEG2 0
-#define GC_BASE__INST3_SEG3 0
-#define GC_BASE__INST3_SEG4 0
-
-#define GC_BASE__INST4_SEG0 0
-#define GC_BASE__INST4_SEG1 0
-#define GC_BASE__INST4_SEG2 0
-#define GC_BASE__INST4_SEG3 0
-#define GC_BASE__INST4_SEG4 0
-
-#define GC_BASE__INST5_SEG0 0
-#define GC_BASE__INST5_SEG1 0
-#define GC_BASE__INST5_SEG2 0
-#define GC_BASE__INST5_SEG3 0
-#define GC_BASE__INST5_SEG4 0
-
-#define GC_BASE__INST6_SEG0 0
-#define GC_BASE__INST6_SEG1 0
-#define GC_BASE__INST6_SEG2 0
-#define GC_BASE__INST6_SEG3 0
-#define GC_BASE__INST6_SEG4 0
-
-#define HDA_BASE__INST0_SEG0 0x004C0000
-#define HDA_BASE__INST0_SEG1 0x02404800
-#define HDA_BASE__INST0_SEG2 0
-#define HDA_BASE__INST0_SEG3 0
-#define HDA_BASE__INST0_SEG4 0
-
-#define HDA_BASE__INST1_SEG0 0
-#define HDA_BASE__INST1_SEG1 0
-#define HDA_BASE__INST1_SEG2 0
-#define HDA_BASE__INST1_SEG3 0
-#define HDA_BASE__INST1_SEG4 0
-
-#define HDA_BASE__INST2_SEG0 0
-#define HDA_BASE__INST2_SEG1 0
-#define HDA_BASE__INST2_SEG2 0
-#define HDA_BASE__INST2_SEG3 0
-#define HDA_BASE__INST2_SEG4 0
-
-#define HDA_BASE__INST3_SEG0 0
-#define HDA_BASE__INST3_SEG1 0
-#define HDA_BASE__INST3_SEG2 0
-#define HDA_BASE__INST3_SEG3 0
-#define HDA_BASE__INST3_SEG4 0
-
-#define HDA_BASE__INST4_SEG0 0
-#define HDA_BASE__INST4_SEG1 0
-#define HDA_BASE__INST4_SEG2 0
-#define HDA_BASE__INST4_SEG3 0
-#define HDA_BASE__INST4_SEG4 0
-
-#define HDA_BASE__INST5_SEG0 0
-#define HDA_BASE__INST5_SEG1 0
-#define HDA_BASE__INST5_SEG2 0
-#define HDA_BASE__INST5_SEG3 0
-#define HDA_BASE__INST5_SEG4 0
-
-#define HDA_BASE__INST6_SEG0 0
-#define HDA_BASE__INST6_SEG1 0
-#define HDA_BASE__INST6_SEG2 0
-#define HDA_BASE__INST6_SEG3 0
-#define HDA_BASE__INST6_SEG4 0
-
-#define HDP_BASE__INST0_SEG0 0x00000F20
-#define HDP_BASE__INST0_SEG1 0x0240A400
-#define HDP_BASE__INST0_SEG2 0
-#define HDP_BASE__INST0_SEG3 0
-#define HDP_BASE__INST0_SEG4 0
-
-#define HDP_BASE__INST1_SEG0 0
-#define HDP_BASE__INST1_SEG1 0
-#define HDP_BASE__INST1_SEG2 0
-#define HDP_BASE__INST1_SEG3 0
-#define HDP_BASE__INST1_SEG4 0
-
-#define HDP_BASE__INST2_SEG0 0
-#define HDP_BASE__INST2_SEG1 0
-#define HDP_BASE__INST2_SEG2 0
-#define HDP_BASE__INST2_SEG3 0
-#define HDP_BASE__INST2_SEG4 0
-
-#define HDP_BASE__INST3_SEG0 0
-#define HDP_BASE__INST3_SEG1 0
-#define HDP_BASE__INST3_SEG2 0
-#define HDP_BASE__INST3_SEG3 0
-#define HDP_BASE__INST3_SEG4 0
-
-#define HDP_BASE__INST4_SEG0 0
-#define HDP_BASE__INST4_SEG1 0
-#define HDP_BASE__INST4_SEG2 0
-#define HDP_BASE__INST4_SEG3 0
-#define HDP_BASE__INST4_SEG4 0
-
-#define HDP_BASE__INST5_SEG0 0
-#define HDP_BASE__INST5_SEG1 0
-#define HDP_BASE__INST5_SEG2 0
-#define HDP_BASE__INST5_SEG3 0
-#define HDP_BASE__INST5_SEG4 0
-
-#define HDP_BASE__INST6_SEG0 0
-#define HDP_BASE__INST6_SEG1 0
-#define HDP_BASE__INST6_SEG2 0
-#define HDP_BASE__INST6_SEG3 0
-#define HDP_BASE__INST6_SEG4 0
-
-#define MMHUB_BASE__INST0_SEG0 0x0001A000
-#define MMHUB_BASE__INST0_SEG1 0x02408800
-#define MMHUB_BASE__INST0_SEG2 0
-#define MMHUB_BASE__INST0_SEG3 0
-#define MMHUB_BASE__INST0_SEG4 0
-
-#define MMHUB_BASE__INST1_SEG0 0
-#define MMHUB_BASE__INST1_SEG1 0
-#define MMHUB_BASE__INST1_SEG2 0
-#define MMHUB_BASE__INST1_SEG3 0
-#define MMHUB_BASE__INST1_SEG4 0
-
-#define MMHUB_BASE__INST2_SEG0 0
-#define MMHUB_BASE__INST2_SEG1 0
-#define MMHUB_BASE__INST2_SEG2 0
-#define MMHUB_BASE__INST2_SEG3 0
-#define MMHUB_BASE__INST2_SEG4 0
-
-#define MMHUB_BASE__INST3_SEG0 0
-#define MMHUB_BASE__INST3_SEG1 0
-#define MMHUB_BASE__INST3_SEG2 0
-#define MMHUB_BASE__INST3_SEG3 0
-#define MMHUB_BASE__INST3_SEG4 0
-
-#define MMHUB_BASE__INST4_SEG0 0
-#define MMHUB_BASE__INST4_SEG1 0
-#define MMHUB_BASE__INST4_SEG2 0
-#define MMHUB_BASE__INST4_SEG3 0
-#define MMHUB_BASE__INST4_SEG4 0
-
-#define MMHUB_BASE__INST5_SEG0 0
-#define MMHUB_BASE__INST5_SEG1 0
-#define MMHUB_BASE__INST5_SEG2 0
-#define MMHUB_BASE__INST5_SEG3 0
-#define MMHUB_BASE__INST5_SEG4 0
-
-#define MMHUB_BASE__INST6_SEG0 0
-#define MMHUB_BASE__INST6_SEG1 0
-#define MMHUB_BASE__INST6_SEG2 0
-#define MMHUB_BASE__INST6_SEG3 0
-#define MMHUB_BASE__INST6_SEG4 0
-
-#define MP0_BASE__INST0_SEG0 0x00016000
-#define MP0_BASE__INST0_SEG1 0x00DC0000
-#define MP0_BASE__INST0_SEG2 0x00E00000
-#define MP0_BASE__INST0_SEG3 0x00E40000
-#define MP0_BASE__INST0_SEG4 0x0243FC00
-
-#define MP0_BASE__INST1_SEG0 0
-#define MP0_BASE__INST1_SEG1 0
-#define MP0_BASE__INST1_SEG2 0
-#define MP0_BASE__INST1_SEG3 0
-#define MP0_BASE__INST1_SEG4 0
-
-#define MP0_BASE__INST2_SEG0 0
-#define MP0_BASE__INST2_SEG1 0
-#define MP0_BASE__INST2_SEG2 0
-#define MP0_BASE__INST2_SEG3 0
-#define MP0_BASE__INST2_SEG4 0
-
-#define MP0_BASE__INST3_SEG0 0
-#define MP0_BASE__INST3_SEG1 0
-#define MP0_BASE__INST3_SEG2 0
-#define MP0_BASE__INST3_SEG3 0
-#define MP0_BASE__INST3_SEG4 0
-
-#define MP0_BASE__INST4_SEG0 0
-#define MP0_BASE__INST4_SEG1 0
-#define MP0_BASE__INST4_SEG2 0
-#define MP0_BASE__INST4_SEG3 0
-#define MP0_BASE__INST4_SEG4 0
-
-#define MP0_BASE__INST5_SEG0 0
-#define MP0_BASE__INST5_SEG1 0
-#define MP0_BASE__INST5_SEG2 0
-#define MP0_BASE__INST5_SEG3 0
-#define MP0_BASE__INST5_SEG4 0
-
-#define MP0_BASE__INST6_SEG0 0
-#define MP0_BASE__INST6_SEG1 0
-#define MP0_BASE__INST6_SEG2 0
-#define MP0_BASE__INST6_SEG3 0
-#define MP0_BASE__INST6_SEG4 0
-
-#define MP1_BASE__INST0_SEG0 0x00016000
-#define MP1_BASE__INST0_SEG1 0x00DC0000
-#define MP1_BASE__INST0_SEG2 0x00E00000
-#define MP1_BASE__INST0_SEG3 0x00E40000
-#define MP1_BASE__INST0_SEG4 0x0243FC00
-
-#define MP1_BASE__INST1_SEG0 0
-#define MP1_BASE__INST1_SEG1 0
-#define MP1_BASE__INST1_SEG2 0
-#define MP1_BASE__INST1_SEG3 0
-#define MP1_BASE__INST1_SEG4 0
-
-#define MP1_BASE__INST2_SEG0 0
-#define MP1_BASE__INST2_SEG1 0
-#define MP1_BASE__INST2_SEG2 0
-#define MP1_BASE__INST2_SEG3 0
-#define MP1_BASE__INST2_SEG4 0
-
-#define MP1_BASE__INST3_SEG0 0
-#define MP1_BASE__INST3_SEG1 0
-#define MP1_BASE__INST3_SEG2 0
-#define MP1_BASE__INST3_SEG3 0
-#define MP1_BASE__INST3_SEG4 0
-
-#define MP1_BASE__INST4_SEG0 0
-#define MP1_BASE__INST4_SEG1 0
-#define MP1_BASE__INST4_SEG2 0
-#define MP1_BASE__INST4_SEG3 0
-#define MP1_BASE__INST4_SEG4 0
-
-#define MP1_BASE__INST5_SEG0 0
-#define MP1_BASE__INST5_SEG1 0
-#define MP1_BASE__INST5_SEG2 0
-#define MP1_BASE__INST5_SEG3 0
-#define MP1_BASE__INST5_SEG4 0
-
-#define MP1_BASE__INST6_SEG0 0
-#define MP1_BASE__INST6_SEG1 0
-#define MP1_BASE__INST6_SEG2 0
-#define MP1_BASE__INST6_SEG3 0
-#define MP1_BASE__INST6_SEG4 0
-
-#define NBIF0_BASE__INST0_SEG0 0x00000000
-#define NBIF0_BASE__INST0_SEG1 0x00000014
-#define NBIF0_BASE__INST0_SEG2 0x00000D20
-#define NBIF0_BASE__INST0_SEG3 0x00010400
-#define NBIF0_BASE__INST0_SEG4 0x0241B000
-
-#define NBIF0_BASE__INST1_SEG0 0
-#define NBIF0_BASE__INST1_SEG1 0
-#define NBIF0_BASE__INST1_SEG2 0
-#define NBIF0_BASE__INST1_SEG3 0
-#define NBIF0_BASE__INST1_SEG4 0
-
-#define NBIF0_BASE__INST2_SEG0 0
-#define NBIF0_BASE__INST2_SEG1 0
-#define NBIF0_BASE__INST2_SEG2 0
-#define NBIF0_BASE__INST2_SEG3 0
-#define NBIF0_BASE__INST2_SEG4 0
-
-#define NBIF0_BASE__INST3_SEG0 0
-#define NBIF0_BASE__INST3_SEG1 0
-#define NBIF0_BASE__INST3_SEG2 0
-#define NBIF0_BASE__INST3_SEG3 0
-#define NBIF0_BASE__INST3_SEG4 0
-
-#define NBIF0_BASE__INST4_SEG0 0
-#define NBIF0_BASE__INST4_SEG1 0
-#define NBIF0_BASE__INST4_SEG2 0
-#define NBIF0_BASE__INST4_SEG3 0
-#define NBIF0_BASE__INST4_SEG4 0
-
-#define NBIF0_BASE__INST5_SEG0 0
-#define NBIF0_BASE__INST5_SEG1 0
-#define NBIF0_BASE__INST5_SEG2 0
-#define NBIF0_BASE__INST5_SEG3 0
-#define NBIF0_BASE__INST5_SEG4 0
-
-#define NBIF0_BASE__INST6_SEG0 0
-#define NBIF0_BASE__INST6_SEG1 0
-#define NBIF0_BASE__INST6_SEG2 0
-#define NBIF0_BASE__INST6_SEG3 0
-#define NBIF0_BASE__INST6_SEG4 0
-
-#define OSSSYS_BASE__INST0_SEG0 0x000010A0
-#define OSSSYS_BASE__INST0_SEG1 0x0240A000
-#define OSSSYS_BASE__INST0_SEG2 0
-#define OSSSYS_BASE__INST0_SEG3 0
-#define OSSSYS_BASE__INST0_SEG4 0
-
-#define OSSSYS_BASE__INST1_SEG0 0
-#define OSSSYS_BASE__INST1_SEG1 0
-#define OSSSYS_BASE__INST1_SEG2 0
-#define OSSSYS_BASE__INST1_SEG3 0
-#define OSSSYS_BASE__INST1_SEG4 0
-
-#define OSSSYS_BASE__INST2_SEG0 0
-#define OSSSYS_BASE__INST2_SEG1 0
-#define OSSSYS_BASE__INST2_SEG2 0
-#define OSSSYS_BASE__INST2_SEG3 0
-#define OSSSYS_BASE__INST2_SEG4 0
-
-#define OSSSYS_BASE__INST3_SEG0 0
-#define OSSSYS_BASE__INST3_SEG1 0
-#define OSSSYS_BASE__INST3_SEG2 0
-#define OSSSYS_BASE__INST3_SEG3 0
-#define OSSSYS_BASE__INST3_SEG4 0
-
-#define OSSSYS_BASE__INST4_SEG0 0
-#define OSSSYS_BASE__INST4_SEG1 0
-#define OSSSYS_BASE__INST4_SEG2 0
-#define OSSSYS_BASE__INST4_SEG3 0
-#define OSSSYS_BASE__INST4_SEG4 0
-
-#define OSSSYS_BASE__INST5_SEG0 0
-#define OSSSYS_BASE__INST5_SEG1 0
-#define OSSSYS_BASE__INST5_SEG2 0
-#define OSSSYS_BASE__INST5_SEG3 0
-#define OSSSYS_BASE__INST5_SEG4 0
-
-#define OSSSYS_BASE__INST6_SEG0 0
-#define OSSSYS_BASE__INST6_SEG1 0
-#define OSSSYS_BASE__INST6_SEG2 0
-#define OSSSYS_BASE__INST6_SEG3 0
-#define OSSSYS_BASE__INST6_SEG4 0
-
-#define PCIE0_BASE__INST0_SEG0 0x00000000
-#define PCIE0_BASE__INST0_SEG1 0x00000014
-#define PCIE0_BASE__INST0_SEG2 0x00000D20
-#define PCIE0_BASE__INST0_SEG3 0x00010400
-#define PCIE0_BASE__INST0_SEG4 0x0241B000
-
-#define PCIE0_BASE__INST1_SEG0 0
-#define PCIE0_BASE__INST1_SEG1 0
-#define PCIE0_BASE__INST1_SEG2 0
-#define PCIE0_BASE__INST1_SEG3 0
-#define PCIE0_BASE__INST1_SEG4 0
-
-#define PCIE0_BASE__INST2_SEG0 0
-#define PCIE0_BASE__INST2_SEG1 0
-#define PCIE0_BASE__INST2_SEG2 0
-#define PCIE0_BASE__INST2_SEG3 0
-#define PCIE0_BASE__INST2_SEG4 0
-
-#define PCIE0_BASE__INST3_SEG0 0
-#define PCIE0_BASE__INST3_SEG1 0
-#define PCIE0_BASE__INST3_SEG2 0
-#define PCIE0_BASE__INST3_SEG3 0
-#define PCIE0_BASE__INST3_SEG4 0
-
-#define PCIE0_BASE__INST4_SEG0 0
-#define PCIE0_BASE__INST4_SEG1 0
-#define PCIE0_BASE__INST4_SEG2 0
-#define PCIE0_BASE__INST4_SEG3 0
-#define PCIE0_BASE__INST4_SEG4 0
-
-#define PCIE0_BASE__INST5_SEG0 0
-#define PCIE0_BASE__INST5_SEG1 0
-#define PCIE0_BASE__INST5_SEG2 0
-#define PCIE0_BASE__INST5_SEG3 0
-#define PCIE0_BASE__INST5_SEG4 0
-
-#define PCIE0_BASE__INST6_SEG0 0
-#define PCIE0_BASE__INST6_SEG1 0
-#define PCIE0_BASE__INST6_SEG2 0
-#define PCIE0_BASE__INST6_SEG3 0
-#define PCIE0_BASE__INST6_SEG4 0
-
-#define SDMA_BASE__INST0_SEG0 0x00001260
-#define SDMA_BASE__INST0_SEG1 0x0000A000
-#define SDMA_BASE__INST0_SEG2 0x02402C00
-#define SDMA_BASE__INST0_SEG3 0
-#define SDMA_BASE__INST0_SEG4 0
-
-#define SDMA_BASE__INST1_SEG0 0x00001260
-#define SDMA_BASE__INST1_SEG1 0x0000A000
-#define SDMA_BASE__INST1_SEG2 0x02402C00
-#define SDMA_BASE__INST1_SEG3 0
-#define SDMA_BASE__INST1_SEG4 0
-
-#define SDMA_BASE__INST2_SEG0 0
-#define SDMA_BASE__INST2_SEG1 0
-#define SDMA_BASE__INST2_SEG2 0
-#define SDMA_BASE__INST2_SEG3 0
-#define SDMA_BASE__INST2_SEG4 0
-
-#define SDMA_BASE__INST3_SEG0 0
-#define SDMA_BASE__INST3_SEG1 0
-#define SDMA_BASE__INST3_SEG2 0
-#define SDMA_BASE__INST3_SEG3 0
-#define SDMA_BASE__INST3_SEG4 0
-
-#define SDMA_BASE__INST4_SEG0 0
-#define SDMA_BASE__INST4_SEG1 0
-#define SDMA_BASE__INST4_SEG2 0
-#define SDMA_BASE__INST4_SEG3 0
-#define SDMA_BASE__INST4_SEG4 0
-
-#define SDMA_BASE__INST5_SEG0 0
-#define SDMA_BASE__INST5_SEG1 0
-#define SDMA_BASE__INST5_SEG2 0
-#define SDMA_BASE__INST5_SEG3 0
-#define SDMA_BASE__INST5_SEG4 0
-
-#define SDMA_BASE__INST6_SEG0 0
-#define SDMA_BASE__INST6_SEG1 0
-#define SDMA_BASE__INST6_SEG2 0
-#define SDMA_BASE__INST6_SEG3 0
-#define SDMA_BASE__INST6_SEG4 0
-
-#define SMUIO_BASE__INST0_SEG0 0x00016800
-#define SMUIO_BASE__INST0_SEG1 0x00016A00
-#define SMUIO_BASE__INST0_SEG2 0x00440000
-#define SMUIO_BASE__INST0_SEG3 0x02401000
-#define SMUIO_BASE__INST0_SEG4 0
-
-#define SMUIO_BASE__INST1_SEG0 0
-#define SMUIO_BASE__INST1_SEG1 0
-#define SMUIO_BASE__INST1_SEG2 0
-#define SMUIO_BASE__INST1_SEG3 0
-#define SMUIO_BASE__INST1_SEG4 0
-
-#define SMUIO_BASE__INST2_SEG0 0
-#define SMUIO_BASE__INST2_SEG1 0
-#define SMUIO_BASE__INST2_SEG2 0
-#define SMUIO_BASE__INST2_SEG3 0
-#define SMUIO_BASE__INST2_SEG4 0
-
-#define SMUIO_BASE__INST3_SEG0 0
-#define SMUIO_BASE__INST3_SEG1 0
-#define SMUIO_BASE__INST3_SEG2 0
-#define SMUIO_BASE__INST3_SEG3 0
-#define SMUIO_BASE__INST3_SEG4 0
-
-#define SMUIO_BASE__INST4_SEG0 0
-#define SMUIO_BASE__INST4_SEG1 0
-#define SMUIO_BASE__INST4_SEG2 0
-#define SMUIO_BASE__INST4_SEG3 0
-#define SMUIO_BASE__INST4_SEG4 0
-
-#define SMUIO_BASE__INST5_SEG0 0
-#define SMUIO_BASE__INST5_SEG1 0
-#define SMUIO_BASE__INST5_SEG2 0
-#define SMUIO_BASE__INST5_SEG3 0
-#define SMUIO_BASE__INST5_SEG4 0
-
-#define SMUIO_BASE__INST6_SEG0 0
-#define SMUIO_BASE__INST6_SEG1 0
-#define SMUIO_BASE__INST6_SEG2 0
-#define SMUIO_BASE__INST6_SEG3 0
-#define SMUIO_BASE__INST6_SEG4 0
-
-#define THM_BASE__INST0_SEG0 0x00016600
-#define THM_BASE__INST0_SEG1 0x02400C00
-#define THM_BASE__INST0_SEG2 0
-#define THM_BASE__INST0_SEG3 0
-#define THM_BASE__INST0_SEG4 0
-
-#define THM_BASE__INST1_SEG0 0
-#define THM_BASE__INST1_SEG1 0
-#define THM_BASE__INST1_SEG2 0
-#define THM_BASE__INST1_SEG3 0
-#define THM_BASE__INST1_SEG4 0
-
-#define THM_BASE__INST2_SEG0 0
-#define THM_BASE__INST2_SEG1 0
-#define THM_BASE__INST2_SEG2 0
-#define THM_BASE__INST2_SEG3 0
-#define THM_BASE__INST2_SEG4 0
-
-#define THM_BASE__INST3_SEG0 0
-#define THM_BASE__INST3_SEG1 0
-#define THM_BASE__INST3_SEG2 0
-#define THM_BASE__INST3_SEG3 0
-#define THM_BASE__INST3_SEG4 0
-
-#define THM_BASE__INST4_SEG0 0
-#define THM_BASE__INST4_SEG1 0
-#define THM_BASE__INST4_SEG2 0
-#define THM_BASE__INST4_SEG3 0
-#define THM_BASE__INST4_SEG4 0
-
-#define THM_BASE__INST5_SEG0 0
-#define THM_BASE__INST5_SEG1 0
-#define THM_BASE__INST5_SEG2 0
-#define THM_BASE__INST5_SEG3 0
-#define THM_BASE__INST5_SEG4 0
-
-#define THM_BASE__INST6_SEG0 0
-#define THM_BASE__INST6_SEG1 0
-#define THM_BASE__INST6_SEG2 0
-#define THM_BASE__INST6_SEG3 0
-#define THM_BASE__INST6_SEG4 0
-
-#define UMC_BASE__INST0_SEG0 0x00014000
-#define UMC_BASE__INST0_SEG1 0x02425800
-#define UMC_BASE__INST0_SEG2 0
-#define UMC_BASE__INST0_SEG3 0
-#define UMC_BASE__INST0_SEG4 0
-
-#define UMC_BASE__INST1_SEG0 0x00054000
-#define UMC_BASE__INST1_SEG1 0x02425C00
-#define UMC_BASE__INST1_SEG2 0
-#define UMC_BASE__INST1_SEG3 0
-#define UMC_BASE__INST1_SEG4 0
-
-#define UMC_BASE__INST2_SEG0 0x00094000
-#define UMC_BASE__INST2_SEG1 0x02426000
-#define UMC_BASE__INST2_SEG2 0
-#define UMC_BASE__INST2_SEG3 0
-#define UMC_BASE__INST2_SEG4 0
-
-#define UMC_BASE__INST3_SEG0 0x000D4000
-#define UMC_BASE__INST3_SEG1 0x02426400
-#define UMC_BASE__INST3_SEG2 0
-#define UMC_BASE__INST3_SEG3 0
-#define UMC_BASE__INST3_SEG4 0
-
-#define UMC_BASE__INST4_SEG0 0
-#define UMC_BASE__INST4_SEG1 0
-#define UMC_BASE__INST4_SEG2 0
-#define UMC_BASE__INST4_SEG3 0
-#define UMC_BASE__INST4_SEG4 0
-
-#define UMC_BASE__INST5_SEG0 0
-#define UMC_BASE__INST5_SEG1 0
-#define UMC_BASE__INST5_SEG2 0
-#define UMC_BASE__INST5_SEG3 0
-#define UMC_BASE__INST5_SEG4 0
-
-#define UMC_BASE__INST6_SEG0 0
-#define UMC_BASE__INST6_SEG1 0
-#define UMC_BASE__INST6_SEG2 0
-#define UMC_BASE__INST6_SEG3 0
-#define UMC_BASE__INST6_SEG4 0
-
-#define USB0_BASE__INST0_SEG0 0x0242A800
-#define USB0_BASE__INST0_SEG1 0x05B00000
-#define USB0_BASE__INST0_SEG2 0
-#define USB0_BASE__INST0_SEG3 0
-#define USB0_BASE__INST0_SEG4 0
-
-#define USB0_BASE__INST1_SEG0 0
-#define USB0_BASE__INST1_SEG1 0
-#define USB0_BASE__INST1_SEG2 0
-#define USB0_BASE__INST1_SEG3 0
-#define USB0_BASE__INST1_SEG4 0
-
-#define USB0_BASE__INST2_SEG0 0
-#define USB0_BASE__INST2_SEG1 0
-#define USB0_BASE__INST2_SEG2 0
-#define USB0_BASE__INST2_SEG3 0
-#define USB0_BASE__INST2_SEG4 0
-
-#define USB0_BASE__INST3_SEG0 0
-#define USB0_BASE__INST3_SEG1 0
-#define USB0_BASE__INST3_SEG2 0
-#define USB0_BASE__INST3_SEG3 0
-#define USB0_BASE__INST3_SEG4 0
-
-#define USB0_BASE__INST4_SEG0 0
-#define USB0_BASE__INST4_SEG1 0
-#define USB0_BASE__INST4_SEG2 0
-#define USB0_BASE__INST4_SEG3 0
-#define USB0_BASE__INST4_SEG4 0
-
-#define USB0_BASE__INST5_SEG0 0
-#define USB0_BASE__INST5_SEG1 0
-#define USB0_BASE__INST5_SEG2 0
-#define USB0_BASE__INST5_SEG3 0
-#define USB0_BASE__INST5_SEG4 0
-
-#define USB0_BASE__INST6_SEG0 0
-#define USB0_BASE__INST6_SEG1 0
-#define USB0_BASE__INST6_SEG2 0
-#define USB0_BASE__INST6_SEG3 0
-#define USB0_BASE__INST6_SEG4 0
-
-#define UVD0_BASE__INST0_SEG0 0x00007800
-#define UVD0_BASE__INST0_SEG1 0x00007E00
-#define UVD0_BASE__INST0_SEG2 0x02403000
-#define UVD0_BASE__INST0_SEG3 0
-#define UVD0_BASE__INST0_SEG4 0
-
-#define UVD0_BASE__INST1_SEG0 0
-#define UVD0_BASE__INST1_SEG1 0
-#define UVD0_BASE__INST1_SEG2 0
-#define UVD0_BASE__INST1_SEG3 0
-#define UVD0_BASE__INST1_SEG4 0
-
-#define UVD0_BASE__INST2_SEG0 0
-#define UVD0_BASE__INST2_SEG1 0
-#define UVD0_BASE__INST2_SEG2 0
-#define UVD0_BASE__INST2_SEG3 0
-#define UVD0_BASE__INST2_SEG4 0
-
-#define UVD0_BASE__INST3_SEG0 0
-#define UVD0_BASE__INST3_SEG1 0
-#define UVD0_BASE__INST3_SEG2 0
-#define UVD0_BASE__INST3_SEG3 0
-#define UVD0_BASE__INST3_SEG4 0
-
-#define UVD0_BASE__INST4_SEG0 0
-#define UVD0_BASE__INST4_SEG1 0
-#define UVD0_BASE__INST4_SEG2 0
-#define UVD0_BASE__INST4_SEG3 0
-#define UVD0_BASE__INST4_SEG4 0
-
-#define UVD0_BASE__INST5_SEG0 0
-#define UVD0_BASE__INST5_SEG1 0
-#define UVD0_BASE__INST5_SEG2 0
-#define UVD0_BASE__INST5_SEG3 0
-#define UVD0_BASE__INST5_SEG4 0
-
-#define UVD0_BASE__INST6_SEG0 0
-#define UVD0_BASE__INST6_SEG1 0
-#define UVD0_BASE__INST6_SEG2 0
-#define UVD0_BASE__INST6_SEG3 0
-#define UVD0_BASE__INST6_SEG4 0
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl502d.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl502d.h
deleted file mode 100644
index 47fe91b67..000000000
--- a/drivers/gpu/drm/nouveau/include/nvhw/class/cl502d.h
+++ /dev/null
@@ -1,337 +0,0 @@
-/*
- * Copyright (c) 2003 - 2004, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _cl_nv50_twod_h_
-#define _cl_nv50_twod_h_
-
-#define NV502D_SET_OBJECT 0x0000
-#define NV502D_SET_OBJECT_POINTER 15:0
-
-#define NV502D_WAIT_FOR_IDLE 0x0110
-#define NV502D_WAIT_FOR_IDLE_V 31:0
-
-#define NV502D_SET_DST_CONTEXT_DMA 0x0184
-#define NV502D_SET_DST_CONTEXT_DMA_HANDLE 31:0
-
-#define NV502D_SET_SRC_CONTEXT_DMA 0x0188
-#define NV502D_SET_SRC_CONTEXT_DMA_HANDLE 31:0
-
-#define NV502D_SET_SEMAPHORE_CONTEXT_DMA 0x018c
-#define NV502D_SET_SEMAPHORE_CONTEXT_DMA_HANDLE 31:0
-
-#define NV502D_SET_DST_FORMAT 0x0200
-#define NV502D_SET_DST_FORMAT_V 7:0
-#define NV502D_SET_DST_FORMAT_V_A8R8G8B8 0x000000CF
-#define NV502D_SET_DST_FORMAT_V_A8RL8GL8BL8 0x000000D0
-#define NV502D_SET_DST_FORMAT_V_A2R10G10B10 0x000000DF
-#define NV502D_SET_DST_FORMAT_V_A8B8G8R8 0x000000D5
-#define NV502D_SET_DST_FORMAT_V_A8BL8GL8RL8 0x000000D6
-#define NV502D_SET_DST_FORMAT_V_A2B10G10R10 0x000000D1
-#define NV502D_SET_DST_FORMAT_V_X8R8G8B8 0x000000E6
-#define NV502D_SET_DST_FORMAT_V_X8RL8GL8BL8 0x000000E7
-#define NV502D_SET_DST_FORMAT_V_X8B8G8R8 0x000000F9
-#define NV502D_SET_DST_FORMAT_V_X8BL8GL8RL8 0x000000FA
-#define NV502D_SET_DST_FORMAT_V_R5G6B5 0x000000E8
-#define NV502D_SET_DST_FORMAT_V_A1R5G5B5 0x000000E9
-#define NV502D_SET_DST_FORMAT_V_X1R5G5B5 0x000000F8
-#define NV502D_SET_DST_FORMAT_V_Y8 0x000000F3
-#define NV502D_SET_DST_FORMAT_V_Y16 0x000000EE
-#define NV502D_SET_DST_FORMAT_V_Y32 0x000000FF
-#define NV502D_SET_DST_FORMAT_V_Z1R5G5B5 0x000000FB
-#define NV502D_SET_DST_FORMAT_V_O1R5G5B5 0x000000FC
-#define NV502D_SET_DST_FORMAT_V_Z8R8G8B8 0x000000FD
-#define NV502D_SET_DST_FORMAT_V_O8R8G8B8 0x000000FE
-#define NV502D_SET_DST_FORMAT_V_Y1_8X8 0x0000001C
-#define NV502D_SET_DST_FORMAT_V_RF16 0x000000F2
-#define NV502D_SET_DST_FORMAT_V_RF32 0x000000E5
-#define NV502D_SET_DST_FORMAT_V_RF32_GF32 0x000000CB
-#define NV502D_SET_DST_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA
-#define NV502D_SET_DST_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE
-#define NV502D_SET_DST_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0
-#define NV502D_SET_DST_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3
-
-#define NV502D_SET_DST_MEMORY_LAYOUT 0x0204
-#define NV502D_SET_DST_MEMORY_LAYOUT_V 0:0
-#define NV502D_SET_DST_MEMORY_LAYOUT_V_BLOCKLINEAR 0x00000000
-#define NV502D_SET_DST_MEMORY_LAYOUT_V_PITCH 0x00000001
-
-#define NV502D_SET_DST_PITCH 0x0214
-#define NV502D_SET_DST_PITCH_V 31:0
-
-#define NV502D_SET_DST_WIDTH 0x0218
-#define NV502D_SET_DST_WIDTH_V 31:0
-
-#define NV502D_SET_DST_HEIGHT 0x021c
-#define NV502D_SET_DST_HEIGHT_V 31:0
-
-#define NV502D_SET_DST_OFFSET_UPPER 0x0220
-#define NV502D_SET_DST_OFFSET_UPPER_V 7:0
-
-#define NV502D_SET_DST_OFFSET_LOWER 0x0224
-#define NV502D_SET_DST_OFFSET_LOWER_V 31:0
-
-#define NV502D_SET_SRC_FORMAT 0x0230
-#define NV502D_SET_SRC_FORMAT_V 7:0
-#define NV502D_SET_SRC_FORMAT_V_A8R8G8B8 0x000000CF
-#define NV502D_SET_SRC_FORMAT_V_A8RL8GL8BL8 0x000000D0
-#define NV502D_SET_SRC_FORMAT_V_A2R10G10B10 0x000000DF
-#define NV502D_SET_SRC_FORMAT_V_A8B8G8R8 0x000000D5
-#define NV502D_SET_SRC_FORMAT_V_A8BL8GL8RL8 0x000000D6
-#define NV502D_SET_SRC_FORMAT_V_A2B10G10R10 0x000000D1
-#define NV502D_SET_SRC_FORMAT_V_X8R8G8B8 0x000000E6
-#define NV502D_SET_SRC_FORMAT_V_X8RL8GL8BL8 0x000000E7
-#define NV502D_SET_SRC_FORMAT_V_X8B8G8R8 0x000000F9
-#define NV502D_SET_SRC_FORMAT_V_X8BL8GL8RL8 0x000000FA
-#define NV502D_SET_SRC_FORMAT_V_R5G6B5 0x000000E8
-#define NV502D_SET_SRC_FORMAT_V_A1R5G5B5 0x000000E9
-#define NV502D_SET_SRC_FORMAT_V_X1R5G5B5 0x000000F8
-#define NV502D_SET_SRC_FORMAT_V_Y8 0x000000F3
-#define NV502D_SET_SRC_FORMAT_V_AY8 0x0000001D
-#define NV502D_SET_SRC_FORMAT_V_Y16 0x000000EE
-#define NV502D_SET_SRC_FORMAT_V_Y32 0x000000FF
-#define NV502D_SET_SRC_FORMAT_V_Z1R5G5B5 0x000000FB
-#define NV502D_SET_SRC_FORMAT_V_O1R5G5B5 0x000000FC
-#define NV502D_SET_SRC_FORMAT_V_Z8R8G8B8 0x000000FD
-#define NV502D_SET_SRC_FORMAT_V_O8R8G8B8 0x000000FE
-#define NV502D_SET_SRC_FORMAT_V_Y1_8X8 0x0000001C
-#define NV502D_SET_SRC_FORMAT_V_RF16 0x000000F2
-#define NV502D_SET_SRC_FORMAT_V_RF32 0x000000E5
-#define NV502D_SET_SRC_FORMAT_V_RF32_GF32 0x000000CB
-#define NV502D_SET_SRC_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA
-#define NV502D_SET_SRC_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE
-#define NV502D_SET_SRC_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0
-#define NV502D_SET_SRC_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3
-
-#define NV502D_SET_SRC_MEMORY_LAYOUT 0x0234
-#define NV502D_SET_SRC_MEMORY_LAYOUT_V 0:0
-#define NV502D_SET_SRC_MEMORY_LAYOUT_V_BLOCKLINEAR 0x00000000
-#define NV502D_SET_SRC_MEMORY_LAYOUT_V_PITCH 0x00000001
-
-#define NV502D_SET_SRC_PITCH 0x0244
-#define NV502D_SET_SRC_PITCH_V 31:0
-
-#define NV502D_SET_SRC_WIDTH 0x0248
-#define NV502D_SET_SRC_WIDTH_V 31:0
-
-#define NV502D_SET_SRC_HEIGHT 0x024c
-#define NV502D_SET_SRC_HEIGHT_V 31:0
-
-#define NV502D_SET_SRC_OFFSET_UPPER 0x0250
-#define NV502D_SET_SRC_OFFSET_UPPER_V 7:0
-
-#define NV502D_SET_SRC_OFFSET_LOWER 0x0254
-#define NV502D_SET_SRC_OFFSET_LOWER_V 31:0
-
-#define NV502D_SET_CLIP_ENABLE 0x0290
-#define NV502D_SET_CLIP_ENABLE_V 0:0
-#define NV502D_SET_CLIP_ENABLE_V_FALSE 0x00000000
-#define NV502D_SET_CLIP_ENABLE_V_TRUE 0x00000001
-
-#define NV502D_SET_ROP 0x02a0
-#define NV502D_SET_ROP_V 7:0
-
-#define NV502D_SET_OPERATION 0x02ac
-#define NV502D_SET_OPERATION_V 2:0
-#define NV502D_SET_OPERATION_V_SRCCOPY_AND 0x00000000
-#define NV502D_SET_OPERATION_V_ROP_AND 0x00000001
-#define NV502D_SET_OPERATION_V_BLEND_AND 0x00000002
-#define NV502D_SET_OPERATION_V_SRCCOPY 0x00000003
-#define NV502D_SET_OPERATION_V_ROP 0x00000004
-#define NV502D_SET_OPERATION_V_SRCCOPY_PREMULT 0x00000005
-#define NV502D_SET_OPERATION_V_BLEND_PREMULT 0x00000006
-
-#define NV502D_SET_MONOCHROME_PATTERN_COLOR_FORMAT 0x02e8
-#define NV502D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V 2:0
-#define NV502D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8X8R5G6B5 0x00000000
-#define NV502D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A1R5G5B5 0x00000001
-#define NV502D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8R8G8B8 0x00000002
-#define NV502D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8Y8 0x00000003
-#define NV502D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8X8Y16 0x00000004
-#define NV502D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_Y32 0x00000005
-
-#define NV502D_SET_MONOCHROME_PATTERN_FORMAT 0x02ec
-#define NV502D_SET_MONOCHROME_PATTERN_FORMAT_V 0:0
-#define NV502D_SET_MONOCHROME_PATTERN_FORMAT_V_CGA6_M1 0x00000000
-#define NV502D_SET_MONOCHROME_PATTERN_FORMAT_V_LE_M1 0x00000001
-
-#define NV502D_RENDER_SOLID_PRIM_MODE 0x0580
-#define NV502D_RENDER_SOLID_PRIM_MODE_V 2:0
-#define NV502D_RENDER_SOLID_PRIM_MODE_V_POINTS 0x00000000
-#define NV502D_RENDER_SOLID_PRIM_MODE_V_LINES 0x00000001
-#define NV502D_RENDER_SOLID_PRIM_MODE_V_POLYLINE 0x00000002
-#define NV502D_RENDER_SOLID_PRIM_MODE_V_TRIANGLES 0x00000003
-#define NV502D_RENDER_SOLID_PRIM_MODE_V_RECTS 0x00000004
-
-#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT 0x0584
-#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V 7:0
-#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A8R8G8B8 0x000000CF
-#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A2R10G10B10 0x000000DF
-#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A8B8G8R8 0x000000D5
-#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A2B10G10R10 0x000000D1
-#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_X8R8G8B8 0x000000E6
-#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_X8B8G8R8 0x000000F9
-#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_R5G6B5 0x000000E8
-#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A1R5G5B5 0x000000E9
-#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_X1R5G5B5 0x000000F8
-#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Y8 0x000000F3
-#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Y16 0x000000EE
-#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Y32 0x000000FF
-#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Z1R5G5B5 0x000000FB
-#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_O1R5G5B5 0x000000FC
-#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Z8R8G8B8 0x000000FD
-#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_O8R8G8B8 0x000000FE
-
-#define NV502D_SET_RENDER_SOLID_PRIM_COLOR 0x0588
-#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_V 31:0
-
-#define NV502D_RENDER_SOLID_PRIM_POINT_SET_X(j) (0x0600+(j)*8)
-#define NV502D_RENDER_SOLID_PRIM_POINT_SET_X_V 31:0
-
-#define NV502D_RENDER_SOLID_PRIM_POINT_Y(j) (0x0604+(j)*8)
-#define NV502D_RENDER_SOLID_PRIM_POINT_Y_V 31:0
-
-#define NV502D_SET_PIXELS_FROM_CPU_DATA_TYPE 0x0800
-#define NV502D_SET_PIXELS_FROM_CPU_DATA_TYPE_V 0:0
-#define NV502D_SET_PIXELS_FROM_CPU_DATA_TYPE_V_COLOR 0x00000000
-#define NV502D_SET_PIXELS_FROM_CPU_DATA_TYPE_V_INDEX 0x00000001
-
-#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT 0x0804
-#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V 7:0
-#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A8R8G8B8 0x000000CF
-#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A2R10G10B10 0x000000DF
-#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A8B8G8R8 0x000000D5
-#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A2B10G10R10 0x000000D1
-#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_X8R8G8B8 0x000000E6
-#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_X8B8G8R8 0x000000F9
-#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_R5G6B5 0x000000E8
-#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A1R5G5B5 0x000000E9
-#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_X1R5G5B5 0x000000F8
-#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Y8 0x000000F3
-#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Y16 0x000000EE
-#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Y32 0x000000FF
-#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Z1R5G5B5 0x000000FB
-#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_O1R5G5B5 0x000000FC
-#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Z8R8G8B8 0x000000FD
-#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_O8R8G8B8 0x000000FE
-
-#define NV502D_SET_PIXELS_FROM_CPU_INDEX_FORMAT 0x0808
-#define NV502D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V 1:0
-#define NV502D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V_I1 0x00000000
-#define NV502D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V_I4 0x00000001
-#define NV502D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V_I8 0x00000002
-
-#define NV502D_SET_PIXELS_FROM_CPU_MONO_FORMAT 0x080c
-#define NV502D_SET_PIXELS_FROM_CPU_MONO_FORMAT_V 0:0
-#define NV502D_SET_PIXELS_FROM_CPU_MONO_FORMAT_V_CGA6_M1 0x00000000
-#define NV502D_SET_PIXELS_FROM_CPU_MONO_FORMAT_V_LE_M1 0x00000001
-
-#define NV502D_SET_PIXELS_FROM_CPU_WRAP 0x0810
-#define NV502D_SET_PIXELS_FROM_CPU_WRAP_V 1:0
-#define NV502D_SET_PIXELS_FROM_CPU_WRAP_V_WRAP_PIXEL 0x00000000
-#define NV502D_SET_PIXELS_FROM_CPU_WRAP_V_WRAP_BYTE 0x00000001
-#define NV502D_SET_PIXELS_FROM_CPU_WRAP_V_WRAP_DWORD 0x00000002
-
-#define NV502D_SET_PIXELS_FROM_CPU_COLOR0 0x0814
-#define NV502D_SET_PIXELS_FROM_CPU_COLOR0_V 31:0
-
-#define NV502D_SET_PIXELS_FROM_CPU_COLOR1 0x0818
-#define NV502D_SET_PIXELS_FROM_CPU_COLOR1_V 31:0
-
-#define NV502D_SET_PIXELS_FROM_CPU_MONO_OPACITY 0x081c
-#define NV502D_SET_PIXELS_FROM_CPU_MONO_OPACITY_V 0:0
-#define NV502D_SET_PIXELS_FROM_CPU_MONO_OPACITY_V_TRANSPARENT 0x00000000
-#define NV502D_SET_PIXELS_FROM_CPU_MONO_OPACITY_V_OPAQUE 0x00000001
-
-#define NV502D_SET_PIXELS_FROM_CPU_SRC_WIDTH 0x0838
-#define NV502D_SET_PIXELS_FROM_CPU_SRC_WIDTH_V 31:0
-
-#define NV502D_SET_PIXELS_FROM_CPU_SRC_HEIGHT 0x083c
-#define NV502D_SET_PIXELS_FROM_CPU_SRC_HEIGHT_V 31:0
-
-#define NV502D_SET_PIXELS_FROM_CPU_DX_DU_FRAC 0x0840
-#define NV502D_SET_PIXELS_FROM_CPU_DX_DU_FRAC_V 31:0
-
-#define NV502D_SET_PIXELS_FROM_CPU_DX_DU_INT 0x0844
-#define NV502D_SET_PIXELS_FROM_CPU_DX_DU_INT_V 31:0
-
-#define NV502D_SET_PIXELS_FROM_CPU_DY_DV_FRAC 0x0848
-#define NV502D_SET_PIXELS_FROM_CPU_DY_DV_FRAC_V 31:0
-
-#define NV502D_SET_PIXELS_FROM_CPU_DY_DV_INT 0x084c
-#define NV502D_SET_PIXELS_FROM_CPU_DY_DV_INT_V 31:0
-
-#define NV502D_SET_PIXELS_FROM_CPU_DST_X0_FRAC 0x0850
-#define NV502D_SET_PIXELS_FROM_CPU_DST_X0_FRAC_V 31:0
-
-#define NV502D_SET_PIXELS_FROM_CPU_DST_X0_INT 0x0854
-#define NV502D_SET_PIXELS_FROM_CPU_DST_X0_INT_V 31:0
-
-#define NV502D_SET_PIXELS_FROM_CPU_DST_Y0_FRAC 0x0858
-#define NV502D_SET_PIXELS_FROM_CPU_DST_Y0_FRAC_V 31:0
-
-#define NV502D_SET_PIXELS_FROM_CPU_DST_Y0_INT 0x085c
-#define NV502D_SET_PIXELS_FROM_CPU_DST_Y0_INT_V 31:0
-
-#define NV502D_PIXELS_FROM_CPU_DATA 0x0860
-#define NV502D_PIXELS_FROM_CPU_DATA_V 31:0
-
-#define NV502D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP 0x0888
-#define NV502D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP_V 0:0
-#define NV502D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP_V_FALSE 0x00000000
-#define NV502D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP_V_TRUE 0x00000001
-
-#define NV502D_SET_PIXELS_FROM_MEMORY_DST_X0 0x08b0
-#define NV502D_SET_PIXELS_FROM_MEMORY_DST_X0_V 31:0
-
-#define NV502D_SET_PIXELS_FROM_MEMORY_DST_Y0 0x08b4
-#define NV502D_SET_PIXELS_FROM_MEMORY_DST_Y0_V 31:0
-
-#define NV502D_SET_PIXELS_FROM_MEMORY_DST_WIDTH 0x08b8
-#define NV502D_SET_PIXELS_FROM_MEMORY_DST_WIDTH_V 31:0
-
-#define NV502D_SET_PIXELS_FROM_MEMORY_DST_HEIGHT 0x08bc
-#define NV502D_SET_PIXELS_FROM_MEMORY_DST_HEIGHT_V 31:0
-
-#define NV502D_SET_PIXELS_FROM_MEMORY_DU_DX_FRAC 0x08c0
-#define NV502D_SET_PIXELS_FROM_MEMORY_DU_DX_FRAC_V 31:0
-
-#define NV502D_SET_PIXELS_FROM_MEMORY_DU_DX_INT 0x08c4
-#define NV502D_SET_PIXELS_FROM_MEMORY_DU_DX_INT_V 31:0
-
-#define NV502D_SET_PIXELS_FROM_MEMORY_DV_DY_FRAC 0x08c8
-#define NV502D_SET_PIXELS_FROM_MEMORY_DV_DY_FRAC_V 31:0
-
-#define NV502D_SET_PIXELS_FROM_MEMORY_DV_DY_INT 0x08cc
-#define NV502D_SET_PIXELS_FROM_MEMORY_DV_DY_INT_V 31:0
-
-#define NV502D_SET_PIXELS_FROM_MEMORY_SRC_X0_FRAC 0x08d0
-#define NV502D_SET_PIXELS_FROM_MEMORY_SRC_X0_FRAC_V 31:0
-
-#define NV502D_SET_PIXELS_FROM_MEMORY_SRC_X0_INT 0x08d4
-#define NV502D_SET_PIXELS_FROM_MEMORY_SRC_X0_INT_V 31:0
-
-#define NV502D_SET_PIXELS_FROM_MEMORY_SRC_Y0_FRAC 0x08d8
-#define NV502D_SET_PIXELS_FROM_MEMORY_SRC_Y0_FRAC_V 31:0
-
-#define NV502D_PIXELS_FROM_MEMORY_SRC_Y0_INT 0x08dc
-#define NV502D_PIXELS_FROM_MEMORY_SRC_Y0_INT_V 31:0
-#endif /* _cl_nv50_twod_h_ */
diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl902d.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl902d.h
deleted file mode 100644
index 8d0b42c04..000000000
--- a/drivers/gpu/drm/nouveau/include/nvhw/class/cl902d.h
+++ /dev/null
@@ -1,357 +0,0 @@
-/*
- * Copyright (c) 2003 - 2004, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _cl_fermi_twod_a_h_
-#define _cl_fermi_twod_a_h_
-
-#define NV902D_SET_OBJECT 0x0000
-#define NV902D_SET_OBJECT_CLASS_ID 15:0
-#define NV902D_SET_OBJECT_ENGINE_ID 20:16
-
-#define NV902D_WAIT_FOR_IDLE 0x0110
-#define NV902D_WAIT_FOR_IDLE_V 31:0
-
-#define NV902D_SET_DST_FORMAT 0x0200
-#define NV902D_SET_DST_FORMAT_V 7:0
-#define NV902D_SET_DST_FORMAT_V_A8R8G8B8 0x000000CF
-#define NV902D_SET_DST_FORMAT_V_A8RL8GL8BL8 0x000000D0
-#define NV902D_SET_DST_FORMAT_V_A2R10G10B10 0x000000DF
-#define NV902D_SET_DST_FORMAT_V_A8B8G8R8 0x000000D5
-#define NV902D_SET_DST_FORMAT_V_A8BL8GL8RL8 0x000000D6
-#define NV902D_SET_DST_FORMAT_V_A2B10G10R10 0x000000D1
-#define NV902D_SET_DST_FORMAT_V_X8R8G8B8 0x000000E6
-#define NV902D_SET_DST_FORMAT_V_X8RL8GL8BL8 0x000000E7
-#define NV902D_SET_DST_FORMAT_V_X8B8G8R8 0x000000F9
-#define NV902D_SET_DST_FORMAT_V_X8BL8GL8RL8 0x000000FA
-#define NV902D_SET_DST_FORMAT_V_R5G6B5 0x000000E8
-#define NV902D_SET_DST_FORMAT_V_A1R5G5B5 0x000000E9
-#define NV902D_SET_DST_FORMAT_V_X1R5G5B5 0x000000F8
-#define NV902D_SET_DST_FORMAT_V_Y8 0x000000F3
-#define NV902D_SET_DST_FORMAT_V_Y16 0x000000EE
-#define NV902D_SET_DST_FORMAT_V_Y32 0x000000FF
-#define NV902D_SET_DST_FORMAT_V_Z1R5G5B5 0x000000FB
-#define NV902D_SET_DST_FORMAT_V_O1R5G5B5 0x000000FC
-#define NV902D_SET_DST_FORMAT_V_Z8R8G8B8 0x000000FD
-#define NV902D_SET_DST_FORMAT_V_O8R8G8B8 0x000000FE
-#define NV902D_SET_DST_FORMAT_V_Y1_8X8 0x0000001C
-#define NV902D_SET_DST_FORMAT_V_RF16 0x000000F2
-#define NV902D_SET_DST_FORMAT_V_RF32 0x000000E5
-#define NV902D_SET_DST_FORMAT_V_RF32_GF32 0x000000CB
-#define NV902D_SET_DST_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA
-#define NV902D_SET_DST_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE
-#define NV902D_SET_DST_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0
-#define NV902D_SET_DST_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3
-#define NV902D_SET_DST_FORMAT_V_R16_G16_B16_A16 0x000000C6
-#define NV902D_SET_DST_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7
-#define NV902D_SET_DST_FORMAT_V_BF10GF11RF11 0x000000E0
-#define NV902D_SET_DST_FORMAT_V_AN8BN8GN8RN8 0x000000D7
-#define NV902D_SET_DST_FORMAT_V_RF16_GF16 0x000000DE
-#define NV902D_SET_DST_FORMAT_V_R16_G16 0x000000DA
-#define NV902D_SET_DST_FORMAT_V_RN16_GN16 0x000000DB
-#define NV902D_SET_DST_FORMAT_V_G8R8 0x000000EA
-#define NV902D_SET_DST_FORMAT_V_GN8RN8 0x000000EB
-#define NV902D_SET_DST_FORMAT_V_RN16 0x000000EF
-#define NV902D_SET_DST_FORMAT_V_RN8 0x000000F4
-#define NV902D_SET_DST_FORMAT_V_A8 0x000000F7
-
-#define NV902D_SET_DST_MEMORY_LAYOUT 0x0204
-#define NV902D_SET_DST_MEMORY_LAYOUT_V 0:0
-#define NV902D_SET_DST_MEMORY_LAYOUT_V_BLOCKLINEAR 0x00000000
-#define NV902D_SET_DST_MEMORY_LAYOUT_V_PITCH 0x00000001
-
-#define NV902D_SET_DST_PITCH 0x0214
-#define NV902D_SET_DST_PITCH_V 31:0
-
-#define NV902D_SET_DST_WIDTH 0x0218
-#define NV902D_SET_DST_WIDTH_V 31:0
-
-#define NV902D_SET_DST_HEIGHT 0x021c
-#define NV902D_SET_DST_HEIGHT_V 31:0
-
-#define NV902D_SET_DST_OFFSET_UPPER 0x0220
-#define NV902D_SET_DST_OFFSET_UPPER_V 7:0
-
-#define NV902D_SET_DST_OFFSET_LOWER 0x0224
-#define NV902D_SET_DST_OFFSET_LOWER_V 31:0
-
-#define NV902D_SET_SRC_FORMAT 0x0230
-#define NV902D_SET_SRC_FORMAT_V 7:0
-#define NV902D_SET_SRC_FORMAT_V_A8R8G8B8 0x000000CF
-#define NV902D_SET_SRC_FORMAT_V_A8RL8GL8BL8 0x000000D0
-#define NV902D_SET_SRC_FORMAT_V_A2R10G10B10 0x000000DF
-#define NV902D_SET_SRC_FORMAT_V_A8B8G8R8 0x000000D5
-#define NV902D_SET_SRC_FORMAT_V_A8BL8GL8RL8 0x000000D6
-#define NV902D_SET_SRC_FORMAT_V_A2B10G10R10 0x000000D1
-#define NV902D_SET_SRC_FORMAT_V_X8R8G8B8 0x000000E6
-#define NV902D_SET_SRC_FORMAT_V_X8RL8GL8BL8 0x000000E7
-#define NV902D_SET_SRC_FORMAT_V_X8B8G8R8 0x000000F9
-#define NV902D_SET_SRC_FORMAT_V_X8BL8GL8RL8 0x000000FA
-#define NV902D_SET_SRC_FORMAT_V_R5G6B5 0x000000E8
-#define NV902D_SET_SRC_FORMAT_V_A1R5G5B5 0x000000E9
-#define NV902D_SET_SRC_FORMAT_V_X1R5G5B5 0x000000F8
-#define NV902D_SET_SRC_FORMAT_V_Y8 0x000000F3
-#define NV902D_SET_SRC_FORMAT_V_AY8 0x0000001D
-#define NV902D_SET_SRC_FORMAT_V_Y16 0x000000EE
-#define NV902D_SET_SRC_FORMAT_V_Y32 0x000000FF
-#define NV902D_SET_SRC_FORMAT_V_Z1R5G5B5 0x000000FB
-#define NV902D_SET_SRC_FORMAT_V_O1R5G5B5 0x000000FC
-#define NV902D_SET_SRC_FORMAT_V_Z8R8G8B8 0x000000FD
-#define NV902D_SET_SRC_FORMAT_V_O8R8G8B8 0x000000FE
-#define NV902D_SET_SRC_FORMAT_V_Y1_8X8 0x0000001C
-#define NV902D_SET_SRC_FORMAT_V_RF16 0x000000F2
-#define NV902D_SET_SRC_FORMAT_V_RF32 0x000000E5
-#define NV902D_SET_SRC_FORMAT_V_RF32_GF32 0x000000CB
-#define NV902D_SET_SRC_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA
-#define NV902D_SET_SRC_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE
-#define NV902D_SET_SRC_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0
-#define NV902D_SET_SRC_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3
-#define NV902D_SET_SRC_FORMAT_V_R16_G16_B16_A16 0x000000C6
-#define NV902D_SET_SRC_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7
-#define NV902D_SET_SRC_FORMAT_V_BF10GF11RF11 0x000000E0
-#define NV902D_SET_SRC_FORMAT_V_AN8BN8GN8RN8 0x000000D7
-#define NV902D_SET_SRC_FORMAT_V_RF16_GF16 0x000000DE
-#define NV902D_SET_SRC_FORMAT_V_R16_G16 0x000000DA
-#define NV902D_SET_SRC_FORMAT_V_RN16_GN16 0x000000DB
-#define NV902D_SET_SRC_FORMAT_V_G8R8 0x000000EA
-#define NV902D_SET_SRC_FORMAT_V_GN8RN8 0x000000EB
-#define NV902D_SET_SRC_FORMAT_V_RN16 0x000000EF
-#define NV902D_SET_SRC_FORMAT_V_RN8 0x000000F4
-#define NV902D_SET_SRC_FORMAT_V_A8 0x000000F7
-
-#define NV902D_SET_SRC_MEMORY_LAYOUT 0x0234
-#define NV902D_SET_SRC_MEMORY_LAYOUT_V 0:0
-#define NV902D_SET_SRC_MEMORY_LAYOUT_V_BLOCKLINEAR 0x00000000
-#define NV902D_SET_SRC_MEMORY_LAYOUT_V_PITCH 0x00000001
-
-#define NV902D_SET_SRC_PITCH 0x0244
-#define NV902D_SET_SRC_PITCH_V 31:0
-
-#define NV902D_SET_SRC_WIDTH 0x0248
-#define NV902D_SET_SRC_WIDTH_V 31:0
-
-#define NV902D_SET_SRC_HEIGHT 0x024c
-#define NV902D_SET_SRC_HEIGHT_V 31:0
-
-#define NV902D_SET_SRC_OFFSET_UPPER 0x0250
-#define NV902D_SET_SRC_OFFSET_UPPER_V 7:0
-
-#define NV902D_SET_SRC_OFFSET_LOWER 0x0254
-#define NV902D_SET_SRC_OFFSET_LOWER_V 31:0
-
-#define NV902D_SET_CLIP_ENABLE 0x0290
-#define NV902D_SET_CLIP_ENABLE_V 0:0
-#define NV902D_SET_CLIP_ENABLE_V_FALSE 0x00000000
-#define NV902D_SET_CLIP_ENABLE_V_TRUE 0x00000001
-
-#define NV902D_SET_ROP 0x02a0
-#define NV902D_SET_ROP_V 7:0
-
-#define NV902D_SET_OPERATION 0x02ac
-#define NV902D_SET_OPERATION_V 2:0
-#define NV902D_SET_OPERATION_V_SRCCOPY_AND 0x00000000
-#define NV902D_SET_OPERATION_V_ROP_AND 0x00000001
-#define NV902D_SET_OPERATION_V_BLEND_AND 0x00000002
-#define NV902D_SET_OPERATION_V_SRCCOPY 0x00000003
-#define NV902D_SET_OPERATION_V_ROP 0x00000004
-#define NV902D_SET_OPERATION_V_SRCCOPY_PREMULT 0x00000005
-#define NV902D_SET_OPERATION_V_BLEND_PREMULT 0x00000006
-
-#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT 0x02e8
-#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V 2:0
-#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8X8R5G6B5 0x00000000
-#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A1R5G5B5 0x00000001
-#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8R8G8B8 0x00000002
-#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8Y8 0x00000003
-#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8X8Y16 0x00000004
-#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_Y32 0x00000005
-#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_BYTE_EXPAND 0x00000006
-
-#define NV902D_SET_MONOCHROME_PATTERN_FORMAT 0x02ec
-#define NV902D_SET_MONOCHROME_PATTERN_FORMAT_V 0:0
-#define NV902D_SET_MONOCHROME_PATTERN_FORMAT_V_CGA6_M1 0x00000000
-#define NV902D_SET_MONOCHROME_PATTERN_FORMAT_V_LE_M1 0x00000001
-
-#define NV902D_RENDER_SOLID_PRIM_MODE 0x0580
-#define NV902D_RENDER_SOLID_PRIM_MODE_V 2:0
-#define NV902D_RENDER_SOLID_PRIM_MODE_V_POINTS 0x00000000
-#define NV902D_RENDER_SOLID_PRIM_MODE_V_LINES 0x00000001
-#define NV902D_RENDER_SOLID_PRIM_MODE_V_POLYLINE 0x00000002
-#define NV902D_RENDER_SOLID_PRIM_MODE_V_TRIANGLES 0x00000003
-#define NV902D_RENDER_SOLID_PRIM_MODE_V_RECTS 0x00000004
-
-#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT 0x0584
-#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V 7:0
-#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0
-#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA
-#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_RF32_GF32 0x000000CB
-#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A8R8G8B8 0x000000CF
-#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A2R10G10B10 0x000000DF
-#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A8B8G8R8 0x000000D5
-#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A2B10G10R10 0x000000D1
-#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_X8R8G8B8 0x000000E6
-#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_X8B8G8R8 0x000000F9
-#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_R5G6B5 0x000000E8
-#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A1R5G5B5 0x000000E9
-#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_X1R5G5B5 0x000000F8
-#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Y8 0x000000F3
-#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Y16 0x000000EE
-#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Y32 0x000000FF
-#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Z1R5G5B5 0x000000FB
-#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_O1R5G5B5 0x000000FC
-#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Z8R8G8B8 0x000000FD
-#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_O8R8G8B8 0x000000FE
-
-#define NV902D_SET_RENDER_SOLID_PRIM_COLOR 0x0588
-#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_V 31:0
-
-#define NV902D_RENDER_SOLID_PRIM_POINT_SET_X(j) (0x0600+(j)*8)
-#define NV902D_RENDER_SOLID_PRIM_POINT_SET_X_V 31:0
-
-#define NV902D_RENDER_SOLID_PRIM_POINT_Y(j) (0x0604+(j)*8)
-#define NV902D_RENDER_SOLID_PRIM_POINT_Y_V 31:0
-
-#define NV902D_SET_PIXELS_FROM_CPU_DATA_TYPE 0x0800
-#define NV902D_SET_PIXELS_FROM_CPU_DATA_TYPE_V 0:0
-#define NV902D_SET_PIXELS_FROM_CPU_DATA_TYPE_V_COLOR 0x00000000
-#define NV902D_SET_PIXELS_FROM_CPU_DATA_TYPE_V_INDEX 0x00000001
-
-#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT 0x0804
-#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V 7:0
-#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A8R8G8B8 0x000000CF
-#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A2R10G10B10 0x000000DF
-#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A8B8G8R8 0x000000D5
-#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A2B10G10R10 0x000000D1
-#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_X8R8G8B8 0x000000E6
-#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_X8B8G8R8 0x000000F9
-#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_R5G6B5 0x000000E8
-#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A1R5G5B5 0x000000E9
-#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_X1R5G5B5 0x000000F8
-#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Y8 0x000000F3
-#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Y16 0x000000EE
-#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Y32 0x000000FF
-#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Z1R5G5B5 0x000000FB
-#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_O1R5G5B5 0x000000FC
-#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Z8R8G8B8 0x000000FD
-#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_O8R8G8B8 0x000000FE
-
-#define NV902D_SET_PIXELS_FROM_CPU_INDEX_FORMAT 0x0808
-#define NV902D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V 1:0
-#define NV902D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V_I1 0x00000000
-#define NV902D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V_I4 0x00000001
-#define NV902D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V_I8 0x00000002
-
-#define NV902D_SET_PIXELS_FROM_CPU_MONO_FORMAT 0x080c
-#define NV902D_SET_PIXELS_FROM_CPU_MONO_FORMAT_V 0:0
-#define NV902D_SET_PIXELS_FROM_CPU_MONO_FORMAT_V_CGA6_M1 0x00000000
-#define NV902D_SET_PIXELS_FROM_CPU_MONO_FORMAT_V_LE_M1 0x00000001
-
-#define NV902D_SET_PIXELS_FROM_CPU_WRAP 0x0810
-#define NV902D_SET_PIXELS_FROM_CPU_WRAP_V 1:0
-#define NV902D_SET_PIXELS_FROM_CPU_WRAP_V_WRAP_PIXEL 0x00000000
-#define NV902D_SET_PIXELS_FROM_CPU_WRAP_V_WRAP_BYTE 0x00000001
-#define NV902D_SET_PIXELS_FROM_CPU_WRAP_V_WRAP_DWORD 0x00000002
-
-#define NV902D_SET_PIXELS_FROM_CPU_COLOR0 0x0814
-#define NV902D_SET_PIXELS_FROM_CPU_COLOR0_V 31:0
-
-#define NV902D_SET_PIXELS_FROM_CPU_COLOR1 0x0818
-#define NV902D_SET_PIXELS_FROM_CPU_COLOR1_V 31:0
-
-#define NV902D_SET_PIXELS_FROM_CPU_MONO_OPACITY 0x081c
-#define NV902D_SET_PIXELS_FROM_CPU_MONO_OPACITY_V 0:0
-#define NV902D_SET_PIXELS_FROM_CPU_MONO_OPACITY_V_TRANSPARENT 0x00000000
-#define NV902D_SET_PIXELS_FROM_CPU_MONO_OPACITY_V_OPAQUE 0x00000001
-
-#define NV902D_SET_PIXELS_FROM_CPU_SRC_WIDTH 0x0838
-#define NV902D_SET_PIXELS_FROM_CPU_SRC_WIDTH_V 31:0
-
-#define NV902D_SET_PIXELS_FROM_CPU_SRC_HEIGHT 0x083c
-#define NV902D_SET_PIXELS_FROM_CPU_SRC_HEIGHT_V 31:0
-
-#define NV902D_SET_PIXELS_FROM_CPU_DX_DU_FRAC 0x0840
-#define NV902D_SET_PIXELS_FROM_CPU_DX_DU_FRAC_V 31:0
-
-#define NV902D_SET_PIXELS_FROM_CPU_DX_DU_INT 0x0844
-#define NV902D_SET_PIXELS_FROM_CPU_DX_DU_INT_V 31:0
-
-#define NV902D_SET_PIXELS_FROM_CPU_DY_DV_FRAC 0x0848
-#define NV902D_SET_PIXELS_FROM_CPU_DY_DV_FRAC_V 31:0
-
-#define NV902D_SET_PIXELS_FROM_CPU_DY_DV_INT 0x084c
-#define NV902D_SET_PIXELS_FROM_CPU_DY_DV_INT_V 31:0
-
-#define NV902D_SET_PIXELS_FROM_CPU_DST_X0_FRAC 0x0850
-#define NV902D_SET_PIXELS_FROM_CPU_DST_X0_FRAC_V 31:0
-
-#define NV902D_SET_PIXELS_FROM_CPU_DST_X0_INT 0x0854
-#define NV902D_SET_PIXELS_FROM_CPU_DST_X0_INT_V 31:0
-
-#define NV902D_SET_PIXELS_FROM_CPU_DST_Y0_FRAC 0x0858
-#define NV902D_SET_PIXELS_FROM_CPU_DST_Y0_FRAC_V 31:0
-
-#define NV902D_SET_PIXELS_FROM_CPU_DST_Y0_INT 0x085c
-#define NV902D_SET_PIXELS_FROM_CPU_DST_Y0_INT_V 31:0
-
-#define NV902D_PIXELS_FROM_CPU_DATA 0x0860
-#define NV902D_PIXELS_FROM_CPU_DATA_V 31:0
-
-#define NV902D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP 0x0888
-#define NV902D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP_V 0:0
-#define NV902D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP_V_FALSE 0x00000000
-#define NV902D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP_V_TRUE 0x00000001
-
-#define NV902D_SET_PIXELS_FROM_MEMORY_DST_X0 0x08b0
-#define NV902D_SET_PIXELS_FROM_MEMORY_DST_X0_V 31:0
-
-#define NV902D_SET_PIXELS_FROM_MEMORY_DST_Y0 0x08b4
-#define NV902D_SET_PIXELS_FROM_MEMORY_DST_Y0_V 31:0
-
-#define NV902D_SET_PIXELS_FROM_MEMORY_DST_WIDTH 0x08b8
-#define NV902D_SET_PIXELS_FROM_MEMORY_DST_WIDTH_V 31:0
-
-#define NV902D_SET_PIXELS_FROM_MEMORY_DST_HEIGHT 0x08bc
-#define NV902D_SET_PIXELS_FROM_MEMORY_DST_HEIGHT_V 31:0
-
-#define NV902D_SET_PIXELS_FROM_MEMORY_DU_DX_FRAC 0x08c0
-#define NV902D_SET_PIXELS_FROM_MEMORY_DU_DX_FRAC_V 31:0
-
-#define NV902D_SET_PIXELS_FROM_MEMORY_DU_DX_INT 0x08c4
-#define NV902D_SET_PIXELS_FROM_MEMORY_DU_DX_INT_V 31:0
-
-#define NV902D_SET_PIXELS_FROM_MEMORY_DV_DY_FRAC 0x08c8
-#define NV902D_SET_PIXELS_FROM_MEMORY_DV_DY_FRAC_V 31:0
-
-#define NV902D_SET_PIXELS_FROM_MEMORY_DV_DY_INT 0x08cc
-#define NV902D_SET_PIXELS_FROM_MEMORY_DV_DY_INT_V 31:0
-
-#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_X0_FRAC 0x08d0
-#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_X0_FRAC_V 31:0
-
-#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_X0_INT 0x08d4
-#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_X0_INT_V 31:0
-
-#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_Y0_FRAC 0x08d8
-#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_Y0_FRAC_V 31:0
-
-#define NV902D_PIXELS_FROM_MEMORY_SRC_Y0_INT 0x08dc
-#define NV902D_PIXELS_FROM_MEMORY_SRC_Y0_INT_V 31:0
-#endif /* _cl_fermi_twod_a_h_ */
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/msenc.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/msenc.h
deleted file mode 100644
index 08fbe7b3c..000000000
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/msenc.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/* SPDX-License-Identifier: MIT */
-#ifndef __NVKM_MSENC_H__
-#define __NVKM_MSENC_H__
-#include <core/engine.h>
-#endif
diff --git a/drivers/gpu/host1x/hw/hw_host1x08_channel.h b/drivers/gpu/host1x/hw/hw_host1x08_channel.h
deleted file mode 100644
index c9272d2ab..000000000
--- a/drivers/gpu/host1x/hw/hw_host1x08_channel.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2022 NVIDIA Corporation.
- */
-
-#ifndef HOST1X_HW_HOST1X08_CHANNEL_H
-#define HOST1X_HW_HOST1X08_CHANNEL_H
-
-#define HOST1X_CHANNEL_SMMU_STREAMID 0x084
-
-#endif
diff --git a/drivers/net/ethernet/smsc/smc9194.h b/drivers/net/ethernet/smsc/smc9194.h
deleted file mode 100644
index cf69d0a5a..000000000
--- a/drivers/net/ethernet/smsc/smc9194.h
+++ /dev/null
@@ -1,241 +0,0 @@
-/*------------------------------------------------------------------------
- . smc9194.h
- . Copyright (C) 1996 by Erik Stahlman
- .
- . This software may be used and distributed according to the terms
- . of the GNU General Public License, incorporated herein by reference.
- .
- . This file contains register information and access macros for
- . the SMC91xxx chipset.
- .
- . Information contained in this file was obtained from the SMC91C94
- . manual from SMC. To get a copy, if you really want one, you can find
- . information under www.smc.com in the components division.
- . ( this thanks to advice from Donald Becker ).
- .
- . Authors
- . Erik Stahlman ( erik@vt.edu )
- .
- . History
- . 01/06/96 Erik Stahlman moved definitions here from main .c file
- . 01/19/96 Erik Stahlman polished this up some, and added better
- . error handling
- .
- ---------------------------------------------------------------------------*/
-#ifndef _SMC9194_H_
-#define _SMC9194_H_
-
-/* I want some simple types */
-
-typedef unsigned char byte;
-typedef unsigned short word;
-typedef unsigned long int dword;
-
-
-/* Because of bank switching, the SMC91xxx uses only 16 I/O ports */
-
-#define SMC_IO_EXTENT 16
-
-
-/*---------------------------------------------------------------
- .
- . A description of the SMC registers is probably in order here,
- . although for details, the SMC datasheet is invaluable.
- .
- . Basically, the chip has 4 banks of registers ( 0 to 3 ), which
- . are accessed by writing a number into the BANK_SELECT register
- . ( I also use a SMC_SELECT_BANK macro for this ).
- .
- . The banks are configured so that for most purposes, bank 2 is all
- . that is needed for simple run time tasks.
- -----------------------------------------------------------------------*/
-
-/*
- . Bank Select Register:
- .
- . yyyy yyyy 0000 00xx
- . xx = bank number
- . yyyy yyyy = 0x33, for identification purposes.
-*/
-#define BANK_SELECT 14
-
-/* BANK 0 */
-
-#define TCR 0 /* transmit control register */
-#define TCR_ENABLE 0x0001 /* if this is 1, we can transmit */
-#define TCR_FDUPLX 0x0800 /* receive packets sent out */
-#define TCR_STP_SQET 0x1000 /* stop transmitting if Signal quality error */
-#define TCR_MON_CNS 0x0400 /* monitors the carrier status */
-#define TCR_PAD_ENABLE 0x0080 /* pads short packets to 64 bytes */
-
-#define TCR_CLEAR 0 /* do NOTHING */
-/* the normal settings for the TCR register : */
-/* QUESTION: do I want to enable padding of short packets ? */
-#define TCR_NORMAL TCR_ENABLE
-
-
-#define EPH_STATUS 2
-#define ES_LINK_OK 0x4000 /* is the link integrity ok ? */
-
-#define RCR 4
-#define RCR_SOFTRESET 0x8000 /* resets the chip */
-#define RCR_STRIP_CRC 0x200 /* strips CRC */
-#define RCR_ENABLE 0x100 /* IFF this is set, we can receive packets */
-#define RCR_ALMUL 0x4 /* receive all multicast packets */
-#define RCR_PROMISC 0x2 /* enable promiscuous mode */
-
-/* the normal settings for the RCR register : */
-#define RCR_NORMAL (RCR_STRIP_CRC | RCR_ENABLE)
-#define RCR_CLEAR 0x0 /* set it to a base state */
-
-#define COUNTER 6
-#define MIR 8
-#define MCR 10
-/* 12 is reserved */
-
-/* BANK 1 */
-#define CONFIG 0
-#define CFG_AUI_SELECT 0x100
-#define BASE 2
-#define ADDR0 4
-#define ADDR1 6
-#define ADDR2 8
-#define GENERAL 10
-#define CONTROL 12
-#define CTL_POWERDOWN 0x2000
-#define CTL_LE_ENABLE 0x80
-#define CTL_CR_ENABLE 0x40
-#define CTL_TE_ENABLE 0x0020
-#define CTL_AUTO_RELEASE 0x0800
-#define CTL_EPROM_ACCESS 0x0003 /* high if Eprom is being read */
-
-/* BANK 2 */
-#define MMU_CMD 0
-#define MC_BUSY 1 /* only readable bit in the register */
-#define MC_NOP 0
-#define MC_ALLOC 0x20 /* or with number of 256 byte packets */
-#define MC_RESET 0x40
-#define MC_REMOVE 0x60 /* remove the current rx packet */
-#define MC_RELEASE 0x80 /* remove and release the current rx packet */
-#define MC_FREEPKT 0xA0 /* Release packet in PNR register */
-#define MC_ENQUEUE 0xC0 /* Enqueue the packet for transmit */
-
-#define PNR_ARR 2
-#define FIFO_PORTS 4
-
-#define FP_RXEMPTY 0x8000
-#define FP_TXEMPTY 0x80
-
-#define POINTER 6
-#define PTR_READ 0x2000
-#define PTR_RCV 0x8000
-#define PTR_AUTOINC 0x4000
-#define PTR_AUTO_INC 0x0040
-
-#define DATA_1 8
-#define DATA_2 10
-#define INTERRUPT 12
-
-#define INT_MASK 13
-#define IM_RCV_INT 0x1
-#define IM_TX_INT 0x2
-#define IM_TX_EMPTY_INT 0x4
-#define IM_ALLOC_INT 0x8
-#define IM_RX_OVRN_INT 0x10
-#define IM_EPH_INT 0x20
-#define IM_ERCV_INT 0x40 /* not on SMC9192 */
-
-/* BANK 3 */
-#define MULTICAST1 0
-#define MULTICAST2 2
-#define MULTICAST3 4
-#define MULTICAST4 6
-#define MGMT 8
-#define REVISION 10 /* ( hi: chip id low: rev # ) */
-
-
-/* this is NOT on SMC9192 */
-#define ERCV 12
-
-#define CHIP_9190 3
-#define CHIP_9194 4
-#define CHIP_9195 5
-#define CHIP_91100 7
-
-static const char * chip_ids[ 15 ] = {
- NULL, NULL, NULL,
- /* 3 */ "SMC91C90/91C92",
- /* 4 */ "SMC91C94",
- /* 5 */ "SMC91C95",
- NULL,
- /* 7 */ "SMC91C100",
- /* 8 */ "SMC91C100FD",
- NULL, NULL, NULL,
- NULL, NULL, NULL};
-
-/*
- . Transmit status bits
-*/
-#define TS_SUCCESS 0x0001
-#define TS_LOSTCAR 0x0400
-#define TS_LATCOL 0x0200
-#define TS_16COL 0x0010
-
-/*
- . Receive status bits
-*/
-#define RS_ALGNERR 0x8000
-#define RS_BADCRC 0x2000
-#define RS_ODDFRAME 0x1000
-#define RS_TOOLONG 0x0800
-#define RS_TOOSHORT 0x0400
-#define RS_MULTICAST 0x0001
-#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
-
-static const char * interfaces[ 2 ] = { "TP", "AUI" };
-
-/*-------------------------------------------------------------------------
- . I define some macros to make it easier to do somewhat common
- . or slightly complicated, repeated tasks.
- --------------------------------------------------------------------------*/
-
-/* select a register bank, 0 to 3 */
-
-#define SMC_SELECT_BANK(x) { outw( x, ioaddr + BANK_SELECT ); }
-
-/* define a small delay for the reset */
-#define SMC_DELAY() { inw( ioaddr + RCR );\
- inw( ioaddr + RCR );\
- inw( ioaddr + RCR ); }
-
-/* this enables an interrupt in the interrupt mask register */
-#define SMC_ENABLE_INT(x) {\
- unsigned char mask;\
- SMC_SELECT_BANK(2);\
- mask = inb( ioaddr + INT_MASK );\
- mask |= (x);\
- outb( mask, ioaddr + INT_MASK ); \
-}
-
-/* this disables an interrupt from the interrupt mask register */
-
-#define SMC_DISABLE_INT(x) {\
- unsigned char mask;\
- SMC_SELECT_BANK(2);\
- mask = inb( ioaddr + INT_MASK );\
- mask &= ~(x);\
- outb( mask, ioaddr + INT_MASK ); \
-}
-
-/*----------------------------------------------------------------------
- . Define the interrupts that I want to receive from the card
- .
- . I want:
- . IM_EPH_INT, for nasty errors
- . IM_RCV_INT, for happy received packets
- . IM_RX_OVRN_INT, because I have to kick the receiver
- --------------------------------------------------------------------------*/
-#define SMC_INTERRUPT_MASK (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT)
-
-#endif /* _SMC_9194_H_ */
-
diff --git a/drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8822bwifionly.c b/drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8822bwifionly.c
deleted file mode 100644
index 145d6f9c0..000000000
--- a/drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8822bwifionly.c
+++ /dev/null
@@ -1,44 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/* Copyright(c) 2016-2017 Realtek Corporation.*/
-
-#include "halbt_precomp.h"
-
-void ex_hal8822b_wifi_only_hw_config(struct wifi_only_cfg *wifionlycfg)
-{
- /*BB control*/
- halwifionly_phy_set_bb_reg(wifionlycfg, 0x4c, 0x01800000, 0x2);
- /*SW control*/
- halwifionly_phy_set_bb_reg(wifionlycfg, 0xcb4, 0xff, 0x77);
- /*antenna mux switch */
- halwifionly_phy_set_bb_reg(wifionlycfg, 0x974, 0x300, 0x3);
-
- halwifionly_phy_set_bb_reg(wifionlycfg, 0x1990, 0x300, 0x0);
-
- halwifionly_phy_set_bb_reg(wifionlycfg, 0xcbc, 0x80000, 0x0);
- /*switch to WL side controller and gnt_wl gnt_bt debug signal */
- halwifionly_phy_set_bb_reg(wifionlycfg, 0x70, 0xff000000, 0x0e);
- /*gnt_wl=1 , gnt_bt=0*/
- halwifionly_phy_set_bb_reg(wifionlycfg, 0x1704, 0xffffffff, 0x7700);
- halwifionly_phy_set_bb_reg(wifionlycfg, 0x1700, 0xffffffff, 0xc00f0038);
-}
-
-void ex_hal8822b_wifi_only_scannotify(struct wifi_only_cfg *wifionlycfg,
- u8 is_5g)
-{
- hal8822b_wifi_only_switch_antenna(wifionlycfg, is_5g);
-}
-
-void ex_hal8822b_wifi_only_switchbandnotify(struct wifi_only_cfg *wifionlycfg,
- u8 is_5g)
-{
- hal8822b_wifi_only_switch_antenna(wifionlycfg, is_5g);
-}
-
-void hal8822b_wifi_only_switch_antenna(struct wifi_only_cfg *wifionlycfg,
- u8 is_5g)
-{
- if (is_5g)
- halwifionly_phy_set_bb_reg(wifionlycfg, 0xcbc, 0x300, 0x1);
- else
- halwifionly_phy_set_bb_reg(wifionlycfg, 0xcbc, 0x300, 0x2);
-}
diff --git a/drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8822bwifionly.h b/drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8822bwifionly.h
deleted file mode 100644
index 5fc66cea7..000000000
--- a/drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8822bwifionly.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright(c) 2016-2017 Realtek Corporation.*/
-
-#ifndef __INC_HAL8822BWIFIONLYHWCFG_H
-#define __INC_HAL8822BWIFIONLYHWCFG_H
-
-void ex_hal8822b_wifi_only_hw_config(struct wifi_only_cfg *wifionlycfg);
-void ex_hal8822b_wifi_only_scannotify(struct wifi_only_cfg *wifionlycfg,
- u8 is_5g);
-void ex_hal8822b_wifi_only_switchbandnotify(struct wifi_only_cfg *wifionlycfg,
- u8 is_5g);
-void hal8822b_wifi_only_switch_antenna(struct wifi_only_cfg *wifionlycfg,
- u8 is_5g);
-#endif
diff --git a/drivers/pcmcia/vg468.h b/drivers/pcmcia/vg468.h
deleted file mode 100644
index 88c2b487f..000000000
--- a/drivers/pcmcia/vg468.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * vg468.h 1.11 1999/10/25 20:03:34
- *
- * The contents of this file are subject to the Mozilla Public License
- * Version 1.1 (the "License"); you may not use this file except in
- * compliance with the License. You may obtain a copy of the License
- * at http://www.mozilla.org/MPL/
- *
- * Software distributed under the License is distributed on an "AS IS"
- * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
- * the License for the specific language governing rights and
- * limitations under the License.
- *
- * The initial developer of the original code is David A. Hinds
- * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
- * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
- *
- * Alternatively, the contents of this file may be used under the
- * terms of the GNU General Public License version 2 (the "GPL"), in which
- * case the provisions of the GPL are applicable instead of the
- * above. If you wish to allow the use of your version of this file
- * only under the terms of the GPL and not to allow others to use
- * your version of this file under the MPL, indicate your decision by
- * deleting the provisions above and replace them with the notice and
- * other provisions required by the GPL. If you do not delete the
- * provisions above, a recipient may use your version of this file
- * under either the MPL or the GPL.
- */
-
-#ifndef _LINUX_VG468_H
-#define _LINUX_VG468_H
-
-/* Special bit in I365_IDENT used for Vadem chip detection */
-#define I365_IDENT_VADEM 0x08
-
-/* Special definitions in I365_POWER */
-#define VG468_VPP2_MASK 0x0c
-#define VG468_VPP2_5V 0x04
-#define VG468_VPP2_12V 0x08
-
-/* Unique Vadem registers */
-#define VG469_VSENSE 0x1f /* Card voltage sense */
-#define VG469_VSELECT 0x2f /* Card voltage select */
-#define VG468_CTL 0x38 /* Control register */
-#define VG468_TIMER 0x39 /* Timer control */
-#define VG468_MISC 0x3a /* Miscellaneous */
-#define VG468_GPIO_CFG 0x3b /* GPIO configuration */
-#define VG469_EXT_MODE 0x3c /* Extended mode register */
-#define VG468_SELECT 0x3d /* Programmable chip select */
-#define VG468_SELECT_CFG 0x3e /* Chip select configuration */
-#define VG468_ATA 0x3f /* ATA control */
-
-/* Flags for VG469_VSENSE */
-#define VG469_VSENSE_A_VS1 0x01
-#define VG469_VSENSE_A_VS2 0x02
-#define VG469_VSENSE_B_VS1 0x04
-#define VG469_VSENSE_B_VS2 0x08
-
-/* Flags for VG469_VSELECT */
-#define VG469_VSEL_VCC 0x03
-#define VG469_VSEL_5V 0x00
-#define VG469_VSEL_3V 0x03
-#define VG469_VSEL_MAX 0x0c
-#define VG469_VSEL_EXT_STAT 0x10
-#define VG469_VSEL_EXT_BUS 0x20
-#define VG469_VSEL_MIXED 0x40
-#define VG469_VSEL_ISA 0x80
-
-/* Flags for VG468_CTL */
-#define VG468_CTL_SLOW 0x01 /* 600ns memory timing */
-#define VG468_CTL_ASYNC 0x02 /* Asynchronous bus clocking */
-#define VG468_CTL_TSSI 0x08 /* Tri-state some outputs */
-#define VG468_CTL_DELAY 0x10 /* Card detect debounce */
-#define VG468_CTL_INPACK 0x20 /* Obey INPACK signal? */
-#define VG468_CTL_POLARITY 0x40 /* VCCEN polarity */
-#define VG468_CTL_COMPAT 0x80 /* Compatibility stuff */
-
-#define VG469_CTL_WS_COMPAT 0x04 /* Wait state compatibility */
-#define VG469_CTL_STRETCH 0x10 /* LED stretch */
-
-/* Flags for VG468_TIMER */
-#define VG468_TIMER_ZEROPWR 0x10 /* Zero power control */
-#define VG468_TIMER_SIGEN 0x20 /* Power up */
-#define VG468_TIMER_STATUS 0x40 /* Activity timer status */
-#define VG468_TIMER_RES 0x80 /* Timer resolution */
-#define VG468_TIMER_MASK 0x0f /* Activity timer timeout */
-
-/* Flags for VG468_MISC */
-#define VG468_MISC_GPIO 0x04 /* General-purpose IO */
-#define VG468_MISC_DMAWSB 0x08 /* DMA wait state control */
-#define VG469_MISC_LEDENA 0x10 /* LED enable */
-#define VG468_MISC_VADEMREV 0x40 /* Vadem revision control */
-#define VG468_MISC_UNLOCK 0x80 /* Unique register lock */
-
-/* Flags for VG469_EXT_MODE_A */
-#define VG469_MODE_VPPST 0x03 /* Vpp steering control */
-#define VG469_MODE_INT_SENSE 0x04 /* Internal voltage sense */
-#define VG469_MODE_CABLE 0x08
-#define VG469_MODE_COMPAT 0x10 /* i82365sl B or DF step */
-#define VG469_MODE_TEST 0x20
-#define VG469_MODE_RIO 0x40 /* Steer RIO to INTR? */
-
-/* Flags for VG469_EXT_MODE_B */
-#define VG469_MODE_B_3V 0x01 /* 3.3v for socket B */
-
-#endif /* _LINUX_VG468_H */
diff --git a/drivers/platform/raspberrypi/vchiq-mmal/mmal-encodings.h b/drivers/platform/raspberrypi/vchiq-mmal/mmal-encodings.h
deleted file mode 100644
index e15ae7b24..000000000
--- a/drivers/platform/raspberrypi/vchiq-mmal/mmal-encodings.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Broadcom BCM2835 V4L2 driver
- *
- * Copyright © 2013 Raspberry Pi (Trading) Ltd.
- *
- * Authors: Vincent Sanders @ Collabora
- * Dave Stevenson @ Broadcom
- * (now dave.stevenson@raspberrypi.org)
- * Simon Mellor @ Broadcom
- * Luke Diamand @ Broadcom
- */
-#ifndef MMAL_ENCODINGS_H
-#define MMAL_ENCODINGS_H
-
-#define MMAL_ENCODING_H264 MMAL_FOURCC('H', '2', '6', '4')
-#define MMAL_ENCODING_H263 MMAL_FOURCC('H', '2', '6', '3')
-#define MMAL_ENCODING_MP4V MMAL_FOURCC('M', 'P', '4', 'V')
-#define MMAL_ENCODING_MP2V MMAL_FOURCC('M', 'P', '2', 'V')
-#define MMAL_ENCODING_MP1V MMAL_FOURCC('M', 'P', '1', 'V')
-#define MMAL_ENCODING_WMV3 MMAL_FOURCC('W', 'M', 'V', '3')
-#define MMAL_ENCODING_WMV2 MMAL_FOURCC('W', 'M', 'V', '2')
-#define MMAL_ENCODING_WMV1 MMAL_FOURCC('W', 'M', 'V', '1')
-#define MMAL_ENCODING_WVC1 MMAL_FOURCC('W', 'V', 'C', '1')
-#define MMAL_ENCODING_VP8 MMAL_FOURCC('V', 'P', '8', ' ')
-#define MMAL_ENCODING_VP7 MMAL_FOURCC('V', 'P', '7', ' ')
-#define MMAL_ENCODING_VP6 MMAL_FOURCC('V', 'P', '6', ' ')
-#define MMAL_ENCODING_THEORA MMAL_FOURCC('T', 'H', 'E', 'O')
-#define MMAL_ENCODING_SPARK MMAL_FOURCC('S', 'P', 'R', 'K')
-#define MMAL_ENCODING_MJPEG MMAL_FOURCC('M', 'J', 'P', 'G')
-
-#define MMAL_ENCODING_JPEG MMAL_FOURCC('J', 'P', 'E', 'G')
-#define MMAL_ENCODING_GIF MMAL_FOURCC('G', 'I', 'F', ' ')
-#define MMAL_ENCODING_PNG MMAL_FOURCC('P', 'N', 'G', ' ')
-#define MMAL_ENCODING_PPM MMAL_FOURCC('P', 'P', 'M', ' ')
-#define MMAL_ENCODING_TGA MMAL_FOURCC('T', 'G', 'A', ' ')
-#define MMAL_ENCODING_BMP MMAL_FOURCC('B', 'M', 'P', ' ')
-
-#define MMAL_ENCODING_I420 MMAL_FOURCC('I', '4', '2', '0')
-#define MMAL_ENCODING_I420_SLICE MMAL_FOURCC('S', '4', '2', '0')
-#define MMAL_ENCODING_YV12 MMAL_FOURCC('Y', 'V', '1', '2')
-#define MMAL_ENCODING_I422 MMAL_FOURCC('I', '4', '2', '2')
-#define MMAL_ENCODING_I422_SLICE MMAL_FOURCC('S', '4', '2', '2')
-#define MMAL_ENCODING_YUYV MMAL_FOURCC('Y', 'U', 'Y', 'V')
-#define MMAL_ENCODING_YVYU MMAL_FOURCC('Y', 'V', 'Y', 'U')
-#define MMAL_ENCODING_UYVY MMAL_FOURCC('U', 'Y', 'V', 'Y')
-#define MMAL_ENCODING_VYUY MMAL_FOURCC('V', 'Y', 'U', 'Y')
-#define MMAL_ENCODING_NV12 MMAL_FOURCC('N', 'V', '1', '2')
-#define MMAL_ENCODING_NV21 MMAL_FOURCC('N', 'V', '2', '1')
-#define MMAL_ENCODING_ARGB MMAL_FOURCC('A', 'R', 'G', 'B')
-#define MMAL_ENCODING_RGBA MMAL_FOURCC('R', 'G', 'B', 'A')
-#define MMAL_ENCODING_ABGR MMAL_FOURCC('A', 'B', 'G', 'R')
-#define MMAL_ENCODING_BGRA MMAL_FOURCC('B', 'G', 'R', 'A')
-#define MMAL_ENCODING_RGB16 MMAL_FOURCC('R', 'G', 'B', '2')
-#define MMAL_ENCODING_RGB24 MMAL_FOURCC('R', 'G', 'B', '3')
-#define MMAL_ENCODING_RGB32 MMAL_FOURCC('R', 'G', 'B', '4')
-#define MMAL_ENCODING_BGR16 MMAL_FOURCC('B', 'G', 'R', '2')
-#define MMAL_ENCODING_BGR24 MMAL_FOURCC('B', 'G', 'R', '3')
-#define MMAL_ENCODING_BGR32 MMAL_FOURCC('B', 'G', 'R', '4')
-
-/** SAND Video (YUVUV128) format, native format understood by VideoCore.
- * This format is *not* opaque - if requested you will receive full frames
- * of YUV_UV video.
- */
-#define MMAL_ENCODING_YUVUV128 MMAL_FOURCC('S', 'A', 'N', 'D')
-
-/** VideoCore opaque image format, image handles are returned to
- * the host but not the actual image data.
- */
-#define MMAL_ENCODING_OPAQUE MMAL_FOURCC('O', 'P', 'Q', 'V')
-
-/** An EGL image handle
- */
-#define MMAL_ENCODING_EGL_IMAGE MMAL_FOURCC('E', 'G', 'L', 'I')
-
-/* }@ */
-
-/** \name Pre-defined audio encodings */
-/* @{ */
-#define MMAL_ENCODING_PCM_UNSIGNED_BE MMAL_FOURCC('P', 'C', 'M', 'U')
-#define MMAL_ENCODING_PCM_UNSIGNED_LE MMAL_FOURCC('p', 'c', 'm', 'u')
-#define MMAL_ENCODING_PCM_SIGNED_BE MMAL_FOURCC('P', 'C', 'M', 'S')
-#define MMAL_ENCODING_PCM_SIGNED_LE MMAL_FOURCC('p', 'c', 'm', 's')
-#define MMAL_ENCODING_PCM_FLOAT_BE MMAL_FOURCC('P', 'C', 'M', 'F')
-#define MMAL_ENCODING_PCM_FLOAT_LE MMAL_FOURCC('p', 'c', 'm', 'f')
-
-/* Pre-defined H264 encoding variants */
-
-/** ISO 14496-10 Annex B byte stream format */
-#define MMAL_ENCODING_VARIANT_H264_DEFAULT 0
-/** ISO 14496-15 AVC stream format */
-#define MMAL_ENCODING_VARIANT_H264_AVC1 MMAL_FOURCC('A', 'V', 'C', '1')
-/** Implicitly delineated NAL units without emulation prevention */
-#define MMAL_ENCODING_VARIANT_H264_RAW MMAL_FOURCC('R', 'A', 'W', ' ')
-
-/** \defgroup MmalColorSpace List of pre-defined video color spaces
- * This defines a list of common color spaces. This list isn't exhaustive and
- * is only provided as a convenience to avoid clients having to use FourCC
- * codes directly. However components are allowed to define and use their own
- * FourCC codes.
- */
-/* @{ */
-
-/** Unknown color space */
-#define MMAL_COLOR_SPACE_UNKNOWN 0
-/** ITU-R BT.601-5 [SDTV] */
-#define MMAL_COLOR_SPACE_ITUR_BT601 MMAL_FOURCC('Y', '6', '0', '1')
-/** ITU-R BT.709-3 [HDTV] */
-#define MMAL_COLOR_SPACE_ITUR_BT709 MMAL_FOURCC('Y', '7', '0', '9')
-/** JPEG JFIF */
-#define MMAL_COLOR_SPACE_JPEG_JFIF MMAL_FOURCC('Y', 'J', 'F', 'I')
-/** Title 47 Code of Federal Regulations (2003) 73.682 (a) (20) */
-#define MMAL_COLOR_SPACE_FCC MMAL_FOURCC('Y', 'F', 'C', 'C')
-/** Society of Motion Picture and Television Engineers 240M (1999) */
-#define MMAL_COLOR_SPACE_SMPTE240M MMAL_FOURCC('Y', '2', '4', '0')
-/** ITU-R BT.470-2 System M */
-#define MMAL_COLOR_SPACE_BT470_2_M MMAL_FOURCC('Y', '_', '_', 'M')
-/** ITU-R BT.470-2 System BG */
-#define MMAL_COLOR_SPACE_BT470_2_BG MMAL_FOURCC('Y', '_', 'B', 'G')
-/** JPEG JFIF, but with 16..255 luma */
-#define MMAL_COLOR_SPACE_JFIF_Y16_255 MMAL_FOURCC('Y', 'Y', '1', '6')
-/* @} MmalColorSpace List */
-
-#endif /* MMAL_ENCODINGS_H */
diff --git a/drivers/platform/raspberrypi/vchiq-mmal/mmal-parameters.h b/drivers/platform/raspberrypi/vchiq-mmal/mmal-parameters.h
deleted file mode 100644
index a0cdd2810..000000000
--- a/drivers/platform/raspberrypi/vchiq-mmal/mmal-parameters.h
+++ /dev/null
@@ -1,752 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Broadcom BCM2835 V4L2 driver
- *
- * Copyright © 2013 Raspberry Pi (Trading) Ltd.
- *
- * Authors: Vincent Sanders @ Collabora
- * Dave Stevenson @ Broadcom
- * (now dave.stevenson@raspberrypi.org)
- * Simon Mellor @ Broadcom
- * Luke Diamand @ Broadcom
- */
-
-/* common parameters */
-
-/** @name Parameter groups
- * Parameters are divided into groups, and then allocated sequentially within
- * a group using an enum.
- * @{
- */
-
-#ifndef MMAL_PARAMETERS_H
-#define MMAL_PARAMETERS_H
-
-#include <linux/math.h>
-
-/** Common parameter ID group, used with many types of component. */
-#define MMAL_PARAMETER_GROUP_COMMON (0 << 16)
-/** Camera-specific parameter ID group. */
-#define MMAL_PARAMETER_GROUP_CAMERA (1 << 16)
-/** Video-specific parameter ID group. */
-#define MMAL_PARAMETER_GROUP_VIDEO (2 << 16)
-/** Audio-specific parameter ID group. */
-#define MMAL_PARAMETER_GROUP_AUDIO (3 << 16)
-/** Clock-specific parameter ID group. */
-#define MMAL_PARAMETER_GROUP_CLOCK (4 << 16)
-/** Miracast-specific parameter ID group. */
-#define MMAL_PARAMETER_GROUP_MIRACAST (5 << 16)
-
-/* Common parameters */
-enum mmal_parameter_common_type {
- /**< Never a valid parameter ID */
- MMAL_PARAMETER_UNUSED = MMAL_PARAMETER_GROUP_COMMON,
-
- /**< MMAL_PARAMETER_ENCODING_T */
- MMAL_PARAMETER_SUPPORTED_ENCODINGS,
- /**< MMAL_PARAMETER_URI_T */
- MMAL_PARAMETER_URI,
- /** MMAL_PARAMETER_CHANGE_EVENT_REQUEST_T */
- MMAL_PARAMETER_CHANGE_EVENT_REQUEST,
- /** MMAL_PARAMETER_BOOLEAN_T */
- MMAL_PARAMETER_ZERO_COPY,
- /**< MMAL_PARAMETER_BUFFER_REQUIREMENTS_T */
- MMAL_PARAMETER_BUFFER_REQUIREMENTS,
- /**< MMAL_PARAMETER_STATISTICS_T */
- MMAL_PARAMETER_STATISTICS,
- /**< MMAL_PARAMETER_CORE_STATISTICS_T */
- MMAL_PARAMETER_CORE_STATISTICS,
- /**< MMAL_PARAMETER_MEM_USAGE_T */
- MMAL_PARAMETER_MEM_USAGE,
- /**< MMAL_PARAMETER_UINT32_T */
- MMAL_PARAMETER_BUFFER_FLAG_FILTER,
- /**< MMAL_PARAMETER_SEEK_T */
- MMAL_PARAMETER_SEEK,
- /**< MMAL_PARAMETER_BOOLEAN_T */
- MMAL_PARAMETER_POWERMON_ENABLE,
- /**< MMAL_PARAMETER_LOGGING_T */
- MMAL_PARAMETER_LOGGING,
- /**< MMAL_PARAMETER_UINT64_T */
- MMAL_PARAMETER_SYSTEM_TIME,
- /**< MMAL_PARAMETER_BOOLEAN_T */
- MMAL_PARAMETER_NO_IMAGE_PADDING,
-};
-
-/* camera parameters */
-
-enum mmal_parameter_camera_type {
- /* 0 */
- /** @ref MMAL_PARAMETER_THUMBNAIL_CONFIG_T */
- MMAL_PARAMETER_THUMBNAIL_CONFIGURATION =
- MMAL_PARAMETER_GROUP_CAMERA,
- /**< Unused? */
- MMAL_PARAMETER_CAPTURE_QUALITY,
- /**< @ref MMAL_PARAMETER_INT32_T */
- MMAL_PARAMETER_ROTATION,
- /**< @ref MMAL_PARAMETER_BOOLEAN_T */
- MMAL_PARAMETER_EXIF_DISABLE,
- /**< @ref MMAL_PARAMETER_EXIF_T */
- MMAL_PARAMETER_EXIF,
- /**< @ref MMAL_PARAM_AWBMODE_T */
- MMAL_PARAMETER_AWB_MODE,
- /**< @ref MMAL_PARAMETER_IMAGEFX_T */
- MMAL_PARAMETER_IMAGE_EFFECT,
- /**< @ref MMAL_PARAMETER_COLOURFX_T */
- MMAL_PARAMETER_COLOUR_EFFECT,
- /**< @ref MMAL_PARAMETER_FLICKERAVOID_T */
- MMAL_PARAMETER_FLICKER_AVOID,
- /**< @ref MMAL_PARAMETER_FLASH_T */
- MMAL_PARAMETER_FLASH,
- /**< @ref MMAL_PARAMETER_REDEYE_T */
- MMAL_PARAMETER_REDEYE,
- /**< @ref MMAL_PARAMETER_FOCUS_T */
- MMAL_PARAMETER_FOCUS,
- /**< Unused? */
- MMAL_PARAMETER_FOCAL_LENGTHS,
- /**< @ref MMAL_PARAMETER_INT32_T */
- MMAL_PARAMETER_EXPOSURE_COMP,
- /**< @ref MMAL_PARAMETER_SCALEFACTOR_T */
- MMAL_PARAMETER_ZOOM,
- /**< @ref MMAL_PARAMETER_MIRROR_T */
- MMAL_PARAMETER_MIRROR,
-
- /* 0x10 */
- /**< @ref MMAL_PARAMETER_UINT32_T */
- MMAL_PARAMETER_CAMERA_NUM,
- /**< @ref MMAL_PARAMETER_BOOLEAN_T */
- MMAL_PARAMETER_CAPTURE,
- /**< @ref MMAL_PARAMETER_EXPOSUREMODE_T */
- MMAL_PARAMETER_EXPOSURE_MODE,
- /**< @ref MMAL_PARAMETER_EXPOSUREMETERINGMODE_T */
- MMAL_PARAMETER_EXP_METERING_MODE,
- /**< @ref MMAL_PARAMETER_FOCUS_STATUS_T */
- MMAL_PARAMETER_FOCUS_STATUS,
- /**< @ref MMAL_PARAMETER_CAMERA_CONFIG_T */
- MMAL_PARAMETER_CAMERA_CONFIG,
- /**< @ref MMAL_PARAMETER_CAPTURE_STATUS_T */
- MMAL_PARAMETER_CAPTURE_STATUS,
- /**< @ref MMAL_PARAMETER_FACE_TRACK_T */
- MMAL_PARAMETER_FACE_TRACK,
- /**< @ref MMAL_PARAMETER_BOOLEAN_T */
- MMAL_PARAMETER_DRAW_BOX_FACES_AND_FOCUS,
- /**< @ref MMAL_PARAMETER_UINT32_T */
- MMAL_PARAMETER_JPEG_Q_FACTOR,
- /**< @ref MMAL_PARAMETER_FRAME_RATE_T */
- MMAL_PARAMETER_FRAME_RATE,
- /**< @ref MMAL_PARAMETER_CAMERA_STC_MODE_T */
- MMAL_PARAMETER_USE_STC,
- /**< @ref MMAL_PARAMETER_CAMERA_INFO_T */
- MMAL_PARAMETER_CAMERA_INFO,
- /**< @ref MMAL_PARAMETER_BOOLEAN_T */
- MMAL_PARAMETER_VIDEO_STABILISATION,
- /**< @ref MMAL_PARAMETER_FACE_TRACK_RESULTS_T */
- MMAL_PARAMETER_FACE_TRACK_RESULTS,
- /**< @ref MMAL_PARAMETER_BOOLEAN_T */
- MMAL_PARAMETER_ENABLE_RAW_CAPTURE,
-
- /* 0x20 */
- /**< @ref MMAL_PARAMETER_URI_T */
- MMAL_PARAMETER_DPF_FILE,
- /**< @ref MMAL_PARAMETER_BOOLEAN_T */
- MMAL_PARAMETER_ENABLE_DPF_FILE,
- /**< @ref MMAL_PARAMETER_BOOLEAN_T */
- MMAL_PARAMETER_DPF_FAIL_IS_FATAL,
- /**< @ref MMAL_PARAMETER_CAPTUREMODE_T */
- MMAL_PARAMETER_CAPTURE_MODE,
- /**< @ref MMAL_PARAMETER_FOCUS_REGIONS_T */
- MMAL_PARAMETER_FOCUS_REGIONS,
- /**< @ref MMAL_PARAMETER_INPUT_CROP_T */
- MMAL_PARAMETER_INPUT_CROP,
- /**< @ref MMAL_PARAMETER_SENSOR_INFORMATION_T */
- MMAL_PARAMETER_SENSOR_INFORMATION,
- /**< @ref MMAL_PARAMETER_FLASH_SELECT_T */
- MMAL_PARAMETER_FLASH_SELECT,
- /**< @ref MMAL_PARAMETER_FIELD_OF_VIEW_T */
- MMAL_PARAMETER_FIELD_OF_VIEW,
- /**< @ref MMAL_PARAMETER_BOOLEAN_T */
- MMAL_PARAMETER_HIGH_DYNAMIC_RANGE,
- /**< @ref MMAL_PARAMETER_DRC_T */
- MMAL_PARAMETER_DYNAMIC_RANGE_COMPRESSION,
- /**< @ref MMAL_PARAMETER_ALGORITHM_CONTROL_T */
- MMAL_PARAMETER_ALGORITHM_CONTROL,
- /**< @ref MMAL_PARAMETER_RATIONAL_T */
- MMAL_PARAMETER_SHARPNESS,
- /**< @ref MMAL_PARAMETER_RATIONAL_T */
- MMAL_PARAMETER_CONTRAST,
- /**< @ref MMAL_PARAMETER_RATIONAL_T */
- MMAL_PARAMETER_BRIGHTNESS,
- /**< @ref MMAL_PARAMETER_RATIONAL_T */
- MMAL_PARAMETER_SATURATION,
-
- /* 0x30 */
- /**< @ref MMAL_PARAMETER_UINT32_T */
- MMAL_PARAMETER_ISO,
- /**< @ref MMAL_PARAMETER_BOOLEAN_T */
- MMAL_PARAMETER_ANTISHAKE,
- /** @ref MMAL_PARAMETER_IMAGEFX_PARAMETERS_T */
- MMAL_PARAMETER_IMAGE_EFFECT_PARAMETERS,
- /** @ref MMAL_PARAMETER_BOOLEAN_T */
- MMAL_PARAMETER_CAMERA_BURST_CAPTURE,
- /** @ref MMAL_PARAMETER_UINT32_T */
- MMAL_PARAMETER_CAMERA_MIN_ISO,
- /** @ref MMAL_PARAMETER_CAMERA_USE_CASE_T */
- MMAL_PARAMETER_CAMERA_USE_CASE,
- /**< @ref MMAL_PARAMETER_BOOLEAN_T */
- MMAL_PARAMETER_CAPTURE_STATS_PASS,
- /** @ref MMAL_PARAMETER_UINT32_T */
- MMAL_PARAMETER_CAMERA_CUSTOM_SENSOR_CONFIG,
- /** @ref MMAL_PARAMETER_BOOLEAN_T */
- MMAL_PARAMETER_ENABLE_REGISTER_FILE,
- /** @ref MMAL_PARAMETER_BOOLEAN_T */
- MMAL_PARAMETER_REGISTER_FAIL_IS_FATAL,
- /** @ref MMAL_PARAMETER_CONFIGFILE_T */
- MMAL_PARAMETER_CONFIGFILE_REGISTERS,
- /** @ref MMAL_PARAMETER_CONFIGFILE_CHUNK_T */
- MMAL_PARAMETER_CONFIGFILE_CHUNK_REGISTERS,
- /**< @ref MMAL_PARAMETER_BOOLEAN_T */
- MMAL_PARAMETER_JPEG_ATTACH_LOG,
- /**< @ref MMAL_PARAMETER_ZEROSHUTTERLAG_T */
- MMAL_PARAMETER_ZERO_SHUTTER_LAG,
- /**< @ref MMAL_PARAMETER_FPS_RANGE_T */
- MMAL_PARAMETER_FPS_RANGE,
- /**< @ref MMAL_PARAMETER_INT32_T */
- MMAL_PARAMETER_CAPTURE_EXPOSURE_COMP,
-
- /* 0x40 */
- /**< @ref MMAL_PARAMETER_BOOLEAN_T */
- MMAL_PARAMETER_SW_SHARPEN_DISABLE,
- /**< @ref MMAL_PARAMETER_BOOLEAN_T */
- MMAL_PARAMETER_FLASH_REQUIRED,
- /**< @ref MMAL_PARAMETER_BOOLEAN_T */
- MMAL_PARAMETER_SW_SATURATION_DISABLE,
- /**< Takes a @ref MMAL_PARAMETER_UINT32_T */
- MMAL_PARAMETER_SHUTTER_SPEED,
- /**< Takes a @ref MMAL_PARAMETER_AWB_GAINS_T */
- MMAL_PARAMETER_CUSTOM_AWB_GAINS,
-};
-
-enum mmal_parameter_camera_config_timestamp_mode {
- MMAL_PARAM_TIMESTAMP_MODE_ZERO = 0, /* Always timestamp frames as 0 */
- MMAL_PARAM_TIMESTAMP_MODE_RAW_STC, /* Use the raw STC value
- * for the frame timestamp
- */
- MMAL_PARAM_TIMESTAMP_MODE_RESET_STC, /* Use the STC timestamp
- * but subtract the
- * timestamp of the first
- * frame sent to give a
- * zero based timestamp.
- */
-};
-
-struct mmal_parameter_fps_range {
- /**< Low end of the permitted framerate range */
- struct s32_fract fps_low;
- /**< High end of the permitted framerate range */
- struct s32_fract fps_high;
-};
-
-/* camera configuration parameter */
-struct mmal_parameter_camera_config {
- /* Parameters for setting up the image pools */
- u32 max_stills_w; /* Max size of stills capture */
- u32 max_stills_h;
- u32 stills_yuv422; /* Allow YUV422 stills capture */
- u32 one_shot_stills; /* Continuous or one shot stills captures. */
-
- u32 max_preview_video_w; /* Max size of the preview or video
- * capture frames
- */
- u32 max_preview_video_h;
- u32 num_preview_video_frames;
-
- /** Sets the height of the circular buffer for stills capture. */
- u32 stills_capture_circular_buffer_height;
-
- /** Allows preview/encode to resume as fast as possible after the stills
- * input frame has been received, and then processes the still frame in
- * the background whilst preview/encode has resumed.
- * Actual mode is controlled by MMAL_PARAMETER_CAPTURE_MODE.
- */
- u32 fast_preview_resume;
-
- /** Selects algorithm for timestamping frames if
- * there is no clock component connected.
- * enum mmal_parameter_camera_config_timestamp_mode
- */
- s32 use_stc_timestamp;
-};
-
-enum mmal_parameter_exposuremode {
- MMAL_PARAM_EXPOSUREMODE_OFF,
- MMAL_PARAM_EXPOSUREMODE_AUTO,
- MMAL_PARAM_EXPOSUREMODE_NIGHT,
- MMAL_PARAM_EXPOSUREMODE_NIGHTPREVIEW,
- MMAL_PARAM_EXPOSUREMODE_BACKLIGHT,
- MMAL_PARAM_EXPOSUREMODE_SPOTLIGHT,
- MMAL_PARAM_EXPOSUREMODE_SPORTS,
- MMAL_PARAM_EXPOSUREMODE_SNOW,
- MMAL_PARAM_EXPOSUREMODE_BEACH,
- MMAL_PARAM_EXPOSUREMODE_VERYLONG,
- MMAL_PARAM_EXPOSUREMODE_FIXEDFPS,
- MMAL_PARAM_EXPOSUREMODE_ANTISHAKE,
- MMAL_PARAM_EXPOSUREMODE_FIREWORKS,
-};
-
-enum mmal_parameter_exposuremeteringmode {
- MMAL_PARAM_EXPOSUREMETERINGMODE_AVERAGE,
- MMAL_PARAM_EXPOSUREMETERINGMODE_SPOT,
- MMAL_PARAM_EXPOSUREMETERINGMODE_BACKLIT,
- MMAL_PARAM_EXPOSUREMETERINGMODE_MATRIX,
-};
-
-enum mmal_parameter_awbmode {
- MMAL_PARAM_AWBMODE_OFF,
- MMAL_PARAM_AWBMODE_AUTO,
- MMAL_PARAM_AWBMODE_SUNLIGHT,
- MMAL_PARAM_AWBMODE_CLOUDY,
- MMAL_PARAM_AWBMODE_SHADE,
- MMAL_PARAM_AWBMODE_TUNGSTEN,
- MMAL_PARAM_AWBMODE_FLUORESCENT,
- MMAL_PARAM_AWBMODE_INCANDESCENT,
- MMAL_PARAM_AWBMODE_FLASH,
- MMAL_PARAM_AWBMODE_HORIZON,
-};
-
-enum mmal_parameter_imagefx {
- MMAL_PARAM_IMAGEFX_NONE,
- MMAL_PARAM_IMAGEFX_NEGATIVE,
- MMAL_PARAM_IMAGEFX_SOLARIZE,
- MMAL_PARAM_IMAGEFX_POSTERIZE,
- MMAL_PARAM_IMAGEFX_WHITEBOARD,
- MMAL_PARAM_IMAGEFX_BLACKBOARD,
- MMAL_PARAM_IMAGEFX_SKETCH,
- MMAL_PARAM_IMAGEFX_DENOISE,
- MMAL_PARAM_IMAGEFX_EMBOSS,
- MMAL_PARAM_IMAGEFX_OILPAINT,
- MMAL_PARAM_IMAGEFX_HATCH,
- MMAL_PARAM_IMAGEFX_GPEN,
- MMAL_PARAM_IMAGEFX_PASTEL,
- MMAL_PARAM_IMAGEFX_WATERCOLOUR,
- MMAL_PARAM_IMAGEFX_FILM,
- MMAL_PARAM_IMAGEFX_BLUR,
- MMAL_PARAM_IMAGEFX_SATURATION,
- MMAL_PARAM_IMAGEFX_COLOURSWAP,
- MMAL_PARAM_IMAGEFX_WASHEDOUT,
- MMAL_PARAM_IMAGEFX_POSTERISE,
- MMAL_PARAM_IMAGEFX_COLOURPOINT,
- MMAL_PARAM_IMAGEFX_COLOURBALANCE,
- MMAL_PARAM_IMAGEFX_CARTOON,
-};
-
-enum MMAL_PARAM_FLICKERAVOID {
- MMAL_PARAM_FLICKERAVOID_OFF,
- MMAL_PARAM_FLICKERAVOID_AUTO,
- MMAL_PARAM_FLICKERAVOID_50HZ,
- MMAL_PARAM_FLICKERAVOID_60HZ,
- MMAL_PARAM_FLICKERAVOID_MAX = 0x7FFFFFFF
-};
-
-struct mmal_parameter_awbgains {
- struct s32_fract r_gain; /**< Red gain */
- struct s32_fract b_gain; /**< Blue gain */
-};
-
-/** Manner of video rate control */
-enum mmal_parameter_rate_control_mode {
- MMAL_VIDEO_RATECONTROL_DEFAULT,
- MMAL_VIDEO_RATECONTROL_VARIABLE,
- MMAL_VIDEO_RATECONTROL_CONSTANT,
- MMAL_VIDEO_RATECONTROL_VARIABLE_SKIP_FRAMES,
- MMAL_VIDEO_RATECONTROL_CONSTANT_SKIP_FRAMES
-};
-
-enum mmal_video_profile {
- MMAL_VIDEO_PROFILE_H263_BASELINE,
- MMAL_VIDEO_PROFILE_H263_H320CODING,
- MMAL_VIDEO_PROFILE_H263_BACKWARDCOMPATIBLE,
- MMAL_VIDEO_PROFILE_H263_ISWV2,
- MMAL_VIDEO_PROFILE_H263_ISWV3,
- MMAL_VIDEO_PROFILE_H263_HIGHCOMPRESSION,
- MMAL_VIDEO_PROFILE_H263_INTERNET,
- MMAL_VIDEO_PROFILE_H263_INTERLACE,
- MMAL_VIDEO_PROFILE_H263_HIGHLATENCY,
- MMAL_VIDEO_PROFILE_MP4V_SIMPLE,
- MMAL_VIDEO_PROFILE_MP4V_SIMPLESCALABLE,
- MMAL_VIDEO_PROFILE_MP4V_CORE,
- MMAL_VIDEO_PROFILE_MP4V_MAIN,
- MMAL_VIDEO_PROFILE_MP4V_NBIT,
- MMAL_VIDEO_PROFILE_MP4V_SCALABLETEXTURE,
- MMAL_VIDEO_PROFILE_MP4V_SIMPLEFACE,
- MMAL_VIDEO_PROFILE_MP4V_SIMPLEFBA,
- MMAL_VIDEO_PROFILE_MP4V_BASICANIMATED,
- MMAL_VIDEO_PROFILE_MP4V_HYBRID,
- MMAL_VIDEO_PROFILE_MP4V_ADVANCEDREALTIME,
- MMAL_VIDEO_PROFILE_MP4V_CORESCALABLE,
- MMAL_VIDEO_PROFILE_MP4V_ADVANCEDCODING,
- MMAL_VIDEO_PROFILE_MP4V_ADVANCEDCORE,
- MMAL_VIDEO_PROFILE_MP4V_ADVANCEDSCALABLE,
- MMAL_VIDEO_PROFILE_MP4V_ADVANCEDSIMPLE,
- MMAL_VIDEO_PROFILE_H264_BASELINE,
- MMAL_VIDEO_PROFILE_H264_MAIN,
- MMAL_VIDEO_PROFILE_H264_EXTENDED,
- MMAL_VIDEO_PROFILE_H264_HIGH,
- MMAL_VIDEO_PROFILE_H264_HIGH10,
- MMAL_VIDEO_PROFILE_H264_HIGH422,
- MMAL_VIDEO_PROFILE_H264_HIGH444,
- MMAL_VIDEO_PROFILE_H264_CONSTRAINED_BASELINE,
- MMAL_VIDEO_PROFILE_DUMMY = 0x7FFFFFFF
-};
-
-enum mmal_video_level {
- MMAL_VIDEO_LEVEL_H263_10,
- MMAL_VIDEO_LEVEL_H263_20,
- MMAL_VIDEO_LEVEL_H263_30,
- MMAL_VIDEO_LEVEL_H263_40,
- MMAL_VIDEO_LEVEL_H263_45,
- MMAL_VIDEO_LEVEL_H263_50,
- MMAL_VIDEO_LEVEL_H263_60,
- MMAL_VIDEO_LEVEL_H263_70,
- MMAL_VIDEO_LEVEL_MP4V_0,
- MMAL_VIDEO_LEVEL_MP4V_0b,
- MMAL_VIDEO_LEVEL_MP4V_1,
- MMAL_VIDEO_LEVEL_MP4V_2,
- MMAL_VIDEO_LEVEL_MP4V_3,
- MMAL_VIDEO_LEVEL_MP4V_4,
- MMAL_VIDEO_LEVEL_MP4V_4a,
- MMAL_VIDEO_LEVEL_MP4V_5,
- MMAL_VIDEO_LEVEL_MP4V_6,
- MMAL_VIDEO_LEVEL_H264_1,
- MMAL_VIDEO_LEVEL_H264_1b,
- MMAL_VIDEO_LEVEL_H264_11,
- MMAL_VIDEO_LEVEL_H264_12,
- MMAL_VIDEO_LEVEL_H264_13,
- MMAL_VIDEO_LEVEL_H264_2,
- MMAL_VIDEO_LEVEL_H264_21,
- MMAL_VIDEO_LEVEL_H264_22,
- MMAL_VIDEO_LEVEL_H264_3,
- MMAL_VIDEO_LEVEL_H264_31,
- MMAL_VIDEO_LEVEL_H264_32,
- MMAL_VIDEO_LEVEL_H264_4,
- MMAL_VIDEO_LEVEL_H264_41,
- MMAL_VIDEO_LEVEL_H264_42,
- MMAL_VIDEO_LEVEL_H264_5,
- MMAL_VIDEO_LEVEL_H264_51,
- MMAL_VIDEO_LEVEL_DUMMY = 0x7FFFFFFF
-};
-
-struct mmal_parameter_video_profile {
- enum mmal_video_profile profile;
- enum mmal_video_level level;
-};
-
-/* video parameters */
-
-enum mmal_parameter_video_type {
- /** @ref MMAL_DISPLAYREGION_T */
- MMAL_PARAMETER_DISPLAYREGION = MMAL_PARAMETER_GROUP_VIDEO,
-
- /** @ref MMAL_PARAMETER_VIDEO_PROFILE_T */
- MMAL_PARAMETER_SUPPORTED_PROFILES,
-
- /** @ref MMAL_PARAMETER_VIDEO_PROFILE_T */
- MMAL_PARAMETER_PROFILE,
-
- /** @ref MMAL_PARAMETER_UINT32_T */
- MMAL_PARAMETER_INTRAPERIOD,
-
- /** @ref MMAL_PARAMETER_VIDEO_RATECONTROL_T */
- MMAL_PARAMETER_RATECONTROL,
-
- /** @ref MMAL_PARAMETER_VIDEO_NALUNITFORMAT_T */
- MMAL_PARAMETER_NALUNITFORMAT,
-
- /** @ref MMAL_PARAMETER_BOOLEAN_T */
- MMAL_PARAMETER_MINIMISE_FRAGMENTATION,
-
- /** @ref MMAL_PARAMETER_UINT32_T.
- * Setting the value to zero resets to the default (one slice per
- * frame).
- */
- MMAL_PARAMETER_MB_ROWS_PER_SLICE,
-
- /** @ref MMAL_PARAMETER_VIDEO_LEVEL_EXTENSION_T */
- MMAL_PARAMETER_VIDEO_LEVEL_EXTENSION,
-
- /** @ref MMAL_PARAMETER_VIDEO_EEDE_ENABLE_T */
- MMAL_PARAMETER_VIDEO_EEDE_ENABLE,
-
- /** @ref MMAL_PARAMETER_VIDEO_EEDE_LOSSRATE_T */
- MMAL_PARAMETER_VIDEO_EEDE_LOSSRATE,
-
- /** @ref MMAL_PARAMETER_BOOLEAN_T. Request an I-frame. */
- MMAL_PARAMETER_VIDEO_REQUEST_I_FRAME,
- /** @ref MMAL_PARAMETER_VIDEO_INTRA_REFRESH_T */
- MMAL_PARAMETER_VIDEO_INTRA_REFRESH,
-
- /** @ref MMAL_PARAMETER_BOOLEAN_T. */
- MMAL_PARAMETER_VIDEO_IMMUTABLE_INPUT,
-
- /** @ref MMAL_PARAMETER_UINT32_T. Run-time bit rate control */
- MMAL_PARAMETER_VIDEO_BIT_RATE,
-
- /** @ref MMAL_PARAMETER_FRAME_RATE_T */
- MMAL_PARAMETER_VIDEO_FRAME_RATE,
-
- /** @ref MMAL_PARAMETER_UINT32_T. */
- MMAL_PARAMETER_VIDEO_ENCODE_MIN_QUANT,
-
- /** @ref MMAL_PARAMETER_UINT32_T. */
- MMAL_PARAMETER_VIDEO_ENCODE_MAX_QUANT,
-
- /** @ref MMAL_PARAMETER_VIDEO_ENCODE_RC_MODEL_T. */
- MMAL_PARAMETER_VIDEO_ENCODE_RC_MODEL,
-
- MMAL_PARAMETER_EXTRA_BUFFERS, /**< @ref MMAL_PARAMETER_UINT32_T. */
- /** @ref MMAL_PARAMETER_UINT32_T.
- * Changing this parameter from the default can reduce frame rate
- * because image buffers need to be re-pitched.
- */
- MMAL_PARAMETER_VIDEO_ALIGN_HORIZ,
-
- /** @ref MMAL_PARAMETER_UINT32_T.
- * Changing this parameter from the default can reduce frame rate
- * because image buffers need to be re-pitched.
- */
- MMAL_PARAMETER_VIDEO_ALIGN_VERT,
-
- /** @ref MMAL_PARAMETER_BOOLEAN_T. */
- MMAL_PARAMETER_VIDEO_DROPPABLE_PFRAMES,
-
- /** @ref MMAL_PARAMETER_UINT32_T. */
- MMAL_PARAMETER_VIDEO_ENCODE_INITIAL_QUANT,
-
- /**< @ref MMAL_PARAMETER_UINT32_T. */
- MMAL_PARAMETER_VIDEO_ENCODE_QP_P,
-
- /**< @ref MMAL_PARAMETER_UINT32_T. */
- MMAL_PARAMETER_VIDEO_ENCODE_RC_SLICE_DQUANT,
-
- /** @ref MMAL_PARAMETER_UINT32_T */
- MMAL_PARAMETER_VIDEO_ENCODE_FRAME_LIMIT_BITS,
-
- /** @ref MMAL_PARAMETER_UINT32_T. */
- MMAL_PARAMETER_VIDEO_ENCODE_PEAK_RATE,
-
- /* H264 specific parameters */
-
- /** @ref MMAL_PARAMETER_BOOLEAN_T. */
- MMAL_PARAMETER_VIDEO_ENCODE_H264_DISABLE_CABAC,
-
- /** @ref MMAL_PARAMETER_BOOLEAN_T. */
- MMAL_PARAMETER_VIDEO_ENCODE_H264_LOW_LATENCY,
-
- /** @ref MMAL_PARAMETER_BOOLEAN_T. */
- MMAL_PARAMETER_VIDEO_ENCODE_H264_AU_DELIMITERS,
-
- /** @ref MMAL_PARAMETER_UINT32_T. */
- MMAL_PARAMETER_VIDEO_ENCODE_H264_DEBLOCK_IDC,
-
- /** @ref MMAL_PARAMETER_VIDEO_ENCODER_H264_MB_INTRA_MODES_T. */
- MMAL_PARAMETER_VIDEO_ENCODE_H264_MB_INTRA_MODE,
-
- /** @ref MMAL_PARAMETER_BOOLEAN_T */
- MMAL_PARAMETER_VIDEO_ENCODE_HEADER_ON_OPEN,
-
- /** @ref MMAL_PARAMETER_BOOLEAN_T */
- MMAL_PARAMETER_VIDEO_ENCODE_PRECODE_FOR_QP,
-
- /** @ref MMAL_PARAMETER_VIDEO_DRM_INIT_INFO_T. */
- MMAL_PARAMETER_VIDEO_DRM_INIT_INFO,
-
- /** @ref MMAL_PARAMETER_BOOLEAN_T */
- MMAL_PARAMETER_VIDEO_TIMESTAMP_FIFO,
-
- /** @ref MMAL_PARAMETER_BOOLEAN_T */
- MMAL_PARAMETER_VIDEO_DECODE_ERROR_CONCEALMENT,
-
- /** @ref MMAL_PARAMETER_VIDEO_DRM_PROTECT_BUFFER_T. */
- MMAL_PARAMETER_VIDEO_DRM_PROTECT_BUFFER,
-
- /** @ref MMAL_PARAMETER_BYTES_T */
- MMAL_PARAMETER_VIDEO_DECODE_CONFIG_VD3,
-
- /**< @ref MMAL_PARAMETER_BOOLEAN_T */
- MMAL_PARAMETER_VIDEO_ENCODE_H264_VCL_HRD_PARAMETERS,
-
- /**< @ref MMAL_PARAMETER_BOOLEAN_T */
- MMAL_PARAMETER_VIDEO_ENCODE_H264_LOW_DELAY_HRD_FLAG,
-
- /**< @ref MMAL_PARAMETER_BOOLEAN_T */
- MMAL_PARAMETER_VIDEO_ENCODE_INLINE_HEADER
-};
-
-/** Valid mirror modes */
-enum mmal_parameter_mirror {
- MMAL_PARAM_MIRROR_NONE,
- MMAL_PARAM_MIRROR_VERTICAL,
- MMAL_PARAM_MIRROR_HORIZONTAL,
- MMAL_PARAM_MIRROR_BOTH,
-};
-
-enum mmal_parameter_displaytransform {
- MMAL_DISPLAY_ROT0 = 0,
- MMAL_DISPLAY_MIRROR_ROT0 = 1,
- MMAL_DISPLAY_MIRROR_ROT180 = 2,
- MMAL_DISPLAY_ROT180 = 3,
- MMAL_DISPLAY_MIRROR_ROT90 = 4,
- MMAL_DISPLAY_ROT270 = 5,
- MMAL_DISPLAY_ROT90 = 6,
- MMAL_DISPLAY_MIRROR_ROT270 = 7,
-};
-
-enum mmal_parameter_displaymode {
- MMAL_DISPLAY_MODE_FILL = 0,
- MMAL_DISPLAY_MODE_LETTERBOX = 1,
-};
-
-enum mmal_parameter_displayset {
- MMAL_DISPLAY_SET_NONE = 0,
- MMAL_DISPLAY_SET_NUM = 1,
- MMAL_DISPLAY_SET_FULLSCREEN = 2,
- MMAL_DISPLAY_SET_TRANSFORM = 4,
- MMAL_DISPLAY_SET_DEST_RECT = 8,
- MMAL_DISPLAY_SET_SRC_RECT = 0x10,
- MMAL_DISPLAY_SET_MODE = 0x20,
- MMAL_DISPLAY_SET_PIXEL = 0x40,
- MMAL_DISPLAY_SET_NOASPECT = 0x80,
- MMAL_DISPLAY_SET_LAYER = 0x100,
- MMAL_DISPLAY_SET_COPYPROTECT = 0x200,
- MMAL_DISPLAY_SET_ALPHA = 0x400,
-};
-
-/* rectangle, used lots so it gets its own struct */
-struct vchiq_mmal_rect {
- s32 x;
- s32 y;
- s32 width;
- s32 height;
-};
-
-struct mmal_parameter_displayregion {
- /** Bitfield that indicates which fields are set and should be
- * used. All other fields will maintain their current value.
- * \ref MMAL_DISPLAYSET_T defines the bits that can be
- * combined.
- */
- u32 set;
-
- /** Describes the display output device, with 0 typically
- * being a directly connected LCD display. The actual values
- * will depend on the hardware. Code using hard-wired numbers
- * (e.g. 2) is certain to fail.
- */
-
- u32 display_num;
- /** Indicates that we are using the full device screen area,
- * rather than a window of the display. If zero, then
- * dest_rect is used to specify a region of the display to
- * use.
- */
-
- s32 fullscreen;
- /** Indicates any rotation or flipping used to map frames onto
- * the natural display orientation.
- */
- u32 transform; /* enum mmal_parameter_displaytransform */
-
- /** Where to display the frame within the screen, if
- * fullscreen is zero.
- */
- struct vchiq_mmal_rect dest_rect;
-
- /** Indicates which area of the frame to display. If all
- * values are zero, the whole frame will be used.
- */
- struct vchiq_mmal_rect src_rect;
-
- /** If set to non-zero, indicates that any display scaling
- * should disregard the aspect ratio of the frame region being
- * displayed.
- */
- s32 noaspect;
-
- /** Indicates how the image should be scaled to fit the
- * display. \code MMAL_DISPLAY_MODE_FILL \endcode indicates
- * that the image should fill the screen by potentially
- * cropping the frames. Setting \code mode \endcode to \code
- * MMAL_DISPLAY_MODE_LETTERBOX \endcode indicates that all the
- * source region should be displayed and black bars added if
- * necessary.
- */
- u32 mode; /* enum mmal_parameter_displaymode */
-
- /** If non-zero, defines the width of a source pixel relative
- * to \code pixel_y \endcode. If zero, then pixels default to
- * being square.
- */
- u32 pixel_x;
-
- /** If non-zero, defines the height of a source pixel relative
- * to \code pixel_x \endcode. If zero, then pixels default to
- * being square.
- */
- u32 pixel_y;
-
- /** Sets the relative depth of the images, with greater values
- * being in front of smaller values.
- */
- u32 layer;
-
- /** Set to non-zero to ensure copy protection is used on
- * output.
- */
- s32 copyprotect_required;
-
- /** Level of opacity of the layer, where zero is fully
- * transparent and 255 is fully opaque.
- */
- u32 alpha;
-};
-
-#define MMAL_MAX_IMAGEFX_PARAMETERS 5
-
-struct mmal_parameter_imagefx_parameters {
- enum mmal_parameter_imagefx effect;
- u32 num_effect_params;
- u32 effect_parameter[MMAL_MAX_IMAGEFX_PARAMETERS];
-};
-
-#define MMAL_PARAMETER_CAMERA_INFO_MAX_CAMERAS 4
-#define MMAL_PARAMETER_CAMERA_INFO_MAX_FLASHES 2
-#define MMAL_PARAMETER_CAMERA_INFO_MAX_STR_LEN 16
-
-struct mmal_parameter_camera_info_camera {
- u32 port_id;
- u32 max_width;
- u32 max_height;
- u32 lens_present;
- u8 camera_name[MMAL_PARAMETER_CAMERA_INFO_MAX_STR_LEN];
-};
-
-enum mmal_parameter_camera_info_flash_type {
- /* Make values explicit to ensure they match values in config ini */
- MMAL_PARAMETER_CAMERA_INFO_FLASH_TYPE_XENON = 0,
- MMAL_PARAMETER_CAMERA_INFO_FLASH_TYPE_LED = 1,
- MMAL_PARAMETER_CAMERA_INFO_FLASH_TYPE_OTHER = 2,
- MMAL_PARAMETER_CAMERA_INFO_FLASH_TYPE_MAX = 0x7FFFFFFF
-};
-
-struct mmal_parameter_camera_info_flash {
- enum mmal_parameter_camera_info_flash_type flash_type;
-};
-
-struct mmal_parameter_camera_info {
- u32 num_cameras;
- u32 num_flashes;
- struct mmal_parameter_camera_info_camera
- cameras[MMAL_PARAMETER_CAMERA_INFO_MAX_CAMERAS];
- struct mmal_parameter_camera_info_flash
- flashes[MMAL_PARAMETER_CAMERA_INFO_MAX_FLASHES];
-};
-
-#endif
diff --git a/drivers/staging/greybus/Documentation/firmware/authenticate.c b/drivers/staging/greybus/Documentation/firmware/authenticate.c
deleted file mode 100644
index ba4b16b04..000000000
--- a/drivers/staging/greybus/Documentation/firmware/authenticate.c
+++ /dev/null
@@ -1,94 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
-/*
- * Sample code to test CAP protocol
- *
- * Copyright(c) 2016 Google Inc. All rights reserved.
- * Copyright(c) 2016 Linaro Ltd. All rights reserved.
- */
-
-#include <stdio.h>
-#include <string.h>
-#include <unistd.h>
-#include <sys/ioctl.h>
-#include <sys/stat.h>
-#include <fcntl.h>
-
-#include "../../greybus_authentication.h"
-
-struct cap_ioc_get_endpoint_uid uid;
-struct cap_ioc_get_ims_certificate cert = {
- .certificate_class = 0,
- .certificate_id = 0,
-};
-
-struct cap_ioc_authenticate authenticate = {
- .auth_type = 0,
- .challenge = {0},
-};
-
-int main(int argc, char *argv[])
-{
- unsigned int timeout = 10000;
- char *capdev;
- int fd, ret;
-
- /* Make sure arguments are correct */
- if (argc != 2) {
- printf("\nUsage: ./firmware <Path of the gb-cap-X dev>\n");
- return 0;
- }
-
- capdev = argv[1];
-
- printf("Opening %s authentication device\n", capdev);
-
- fd = open(capdev, O_RDWR);
- if (fd < 0) {
- printf("Failed to open: %s\n", capdev);
- return -1;
- }
-
- /* Get UID */
- printf("Get UID\n");
-
- ret = ioctl(fd, CAP_IOC_GET_ENDPOINT_UID, &uid);
- if (ret < 0) {
- printf("Failed to get UID: %s (%d)\n", capdev, ret);
- ret = -1;
- goto close_fd;
- }
-
- printf("UID received: 0x%llx\n", *(unsigned long long *)(uid.uid));
-
- /* Get certificate */
- printf("Get IMS certificate\n");
-
- ret = ioctl(fd, CAP_IOC_GET_IMS_CERTIFICATE, &cert);
- if (ret < 0) {
- printf("Failed to get IMS certificate: %s (%d)\n", capdev, ret);
- ret = -1;
- goto close_fd;
- }
-
- printf("IMS Certificate size: %d\n", cert.cert_size);
-
- /* Authenticate */
- printf("Authenticate module\n");
-
- memcpy(authenticate.uid, uid.uid, 8);
-
- ret = ioctl(fd, CAP_IOC_AUTHENTICATE, &authenticate);
- if (ret < 0) {
- printf("Failed to authenticate module: %s (%d)\n", capdev, ret);
- ret = -1;
- goto close_fd;
- }
-
- printf("Authenticated, result (%02x), sig-size (%02x)\n",
- authenticate.result_code, authenticate.signature_size);
-
-close_fd:
- close(fd);
-
- return ret;
-}
diff --git a/drivers/staging/greybus/audio_manager_sysfs.c b/drivers/staging/greybus/audio_manager_sysfs.c
deleted file mode 100644
index ff323ca81..000000000
--- a/drivers/staging/greybus/audio_manager_sysfs.c
+++ /dev/null
@@ -1,101 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Greybus operations
- *
- * Copyright 2015-2016 Google Inc.
- */
-
-#include <linux/string.h>
-#include <linux/sysfs.h>
-
-#include "audio_manager.h"
-#include "audio_manager_private.h"
-
-static ssize_t manager_sysfs_add_store(struct kobject *kobj,
- struct kobj_attribute *attr,
- const char *buf, size_t count)
-{
- struct gb_audio_manager_module_descriptor desc = { {0} };
-
- int num = sscanf(buf,
- "name=%" GB_AUDIO_MANAGER_MODULE_NAME_LEN_SSCANF
- "s vid=%d pid=%d intf_id=%d i/p devices=0x%X o/p devices=0x%X",
- desc.name, &desc.vid, &desc.pid, &desc.intf_id,
- &desc.ip_devices, &desc.op_devices);
-
- if (num != 6)
- return -EINVAL;
-
- num = gb_audio_manager_add(&desc);
- if (num < 0)
- return -EINVAL;
-
- return count;
-}
-
-static struct kobj_attribute manager_add_attribute =
- __ATTR(add, 0664, NULL, manager_sysfs_add_store);
-
-static ssize_t manager_sysfs_remove_store(struct kobject *kobj,
- struct kobj_attribute *attr,
- const char *buf, size_t count)
-{
- int id;
-
- int num = kstrtoint(buf, 10, &id);
-
- if (num != 1)
- return -EINVAL;
-
- num = gb_audio_manager_remove(id);
- if (num)
- return num;
-
- return count;
-}
-
-static struct kobj_attribute manager_remove_attribute =
- __ATTR(remove, 0664, NULL, manager_sysfs_remove_store);
-
-static ssize_t manager_sysfs_dump_store(struct kobject *kobj,
- struct kobj_attribute *attr,
- const char *buf, size_t count)
-{
- int id;
-
- int num = kstrtoint(buf, 10, &id);
-
- if (num == 1) {
- num = gb_audio_manager_dump_module(id);
- if (num)
- return num;
- } else if (!strncmp("all", buf, 3)) {
- gb_audio_manager_dump_all();
- } else {
- return -EINVAL;
- }
-
- return count;
-}
-
-static struct kobj_attribute manager_dump_attribute =
- __ATTR(dump, 0664, NULL, manager_sysfs_dump_store);
-
-static void manager_sysfs_init_attribute(struct kobject *kobj,
- struct kobj_attribute *kattr)
-{
- int err;
-
- err = sysfs_create_file(kobj, &kattr->attr);
- if (err) {
- pr_warn("creating the sysfs entry for %s failed: %d\n",
- kattr->attr.name, err);
- }
-}
-
-void gb_audio_manager_sysfs_init(struct kobject *kobj)
-{
- manager_sysfs_init_attribute(kobj, &manager_add_attribute);
- manager_sysfs_init_attribute(kobj, &manager_remove_attribute);
- manager_sysfs_init_attribute(kobj, &manager_dump_attribute);
-}
diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_include/misc_support.h b/drivers/staging/media/atomisp/pci/hive_isp_css_include/misc_support.h
deleted file mode 100644
index f8c5a88ae..000000000
--- a/drivers/staging/media/atomisp/pci/hive_isp_css_include/misc_support.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Support for Intel Camera Imaging ISP subsystem.
- * Copyright (c) 2015, Intel Corporation.
- */
-
-#ifndef __MISC_SUPPORT_H_INCLUDED__
-#define __MISC_SUPPORT_H_INCLUDED__
-
-/* suppress compiler warnings on unused variables */
-#ifndef NOT_USED
-#define NOT_USED(a) ((void)(a))
-#endif
-
-/* Calculate the total bytes for pow(2) byte alignment */
-#define tot_bytes_for_pow2_align(pow2, cur_bytes) ((cur_bytes + (pow2 - 1)) & ~(pow2 - 1))
-
-#endif /* __MISC_SUPPORT_H_INCLUDED__ */
diff --git a/drivers/staging/media/ipu7/abi/ipu7_fw_psys_config_abi.h b/drivers/staging/media/ipu7/abi/ipu7_fw_psys_config_abi.h
deleted file mode 100644
index 0af04c8c6..000000000
--- a/drivers/staging/media/ipu7/abi/ipu7_fw_psys_config_abi.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2020 - 2025 Intel Corporation
- */
-
-#ifndef IPU7_PSYS_CONFIG_ABI_H_INCLUDED__
-#define IPU7_PSYS_CONFIG_ABI_H_INCLUDED__
-
-#include <linux/types.h>
-
-#include "ipu7_fw_boot_abi.h"
-#include "ipu7_fw_config_abi.h"
-
-struct ipu7_psys_config {
- u32 use_debug_manifest;
- u32 timeout_val_ms;
- u32 compression_support_enabled;
- struct ia_gofo_logger_config logger_config;
- struct ipu7_wdt_abi wdt_config;
- u8 ipu_psys_debug_bitmask;
- u8 padding[3];
-};
-
-#endif
diff --git a/drivers/thermal/thermal-fw.c b/drivers/thermal/thermal-fw.c
deleted file mode 100644
index 47c557e32..000000000
--- a/drivers/thermal/thermal-fw.c
+++ /dev/null
@@ -1,12 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * of-thermal-testing.c - Generic Thermal Management device tree testing support
- *
- * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
- */
-#include <linux/platform_device.h>
-#include <linux/fwnode.h>
-#include <linux/module.h>
-
-
-
diff --git a/drivers/thermal/thermal_fw.c b/drivers/thermal/thermal_fw.c
deleted file mode 100644
index e8bd2049c..000000000
--- a/drivers/thermal/thermal_fw.c
+++ /dev/null
@@ -1,97 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * thermal-fw.c - Thermal components creation from firmware description
- *
- * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
- */
-#include <linux/fwnode.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/thermal.h>
-
-/**
- * thermal_fwnode_cooling_device_register() - register an thermal cooling device
- * @np: a pointer to a device tree node.
- * @of_index: a cooling device index in the cooling controller
- * @type: the thermal cooling device type.
- * @devdata: device private data.
- * @ops: standard thermal cooling devices callbacks.
- *
- * This function will register a cooling device with device tree node reference.
- * This interface function adds a new thermal cooling device (fan/processor/...)
- * to /sys/class/thermal/ folder as cooling_device[0-*]. It tries to bind itself
- * to all the thermal zone devices registered at the same time.
- *
- * Return: a pointer to the created struct thermal_cooling_device or an
- * ERR_PTR. Caller must check return value with IS_ERR*() helpers.
- */
-struct thermal_cooling_device *
-thermal_fwnode_cooling_device_register(struct fwnode_handle *fwnode, int fwn_index,
- const char *type, void *devdata,
- const struct thermal_cooling_device_ops *ops)
-{
- struct thermal_cooling_device *cdev;
-
- cdev = __thermal_cooling_device_register(type, devdata, ops);
- if (IS_ERR(cdev))
- return cdev;
-
- cdev->np = (struct device_node *)fwnode;
- cdev->of_index = fwn_index;
- thermal_cooling_device_init_complete(cdev);
-
- return cdev;
-}
-EXPORT_SYMBOL_GPL(thermal_fwnode_cooling_device_register);
-
-static struct thermal_cooling_device *
-__devm_thermal_fwnode_cooling_device_register(struct device *dev, struct fwnode_handle *fwnode,
- int fwn_index, const char *type, void *devdata,
- const struct thermal_cooling_device_ops *ops)
-{
- struct thermal_cooling_device **ptr, *tcd;
-
- ptr = devres_alloc(thermal_cooling_device_release, sizeof(*ptr),
- GFP_KERNEL);
- if (!ptr)
- return ERR_PTR(-ENOMEM);
-
- tcd = thermal_fwnode_cooling_device_register(fwnode, fwn_index, type, devdata, ops);
- if (IS_ERR(tcd)) {
- devres_free(ptr);
- return tcd;
- }
-
- *ptr = tcd;
- devres_add(dev, ptr);
-
- return tcd;
-}
-
-/**
- * devm_thermal_fwnode_cooling_device_register() - register a thermal cooling device
- * @dev: a valid struct device pointer of a sensor device.
- * @fw_index: a cooling device index in the cooling controller
- * @type: the thermal cooling device type.
- * @devdata: device private data.
- * @ops: standard thermal cooling devices callbacks.
- *
- * This function will register a cooling device with a firmware node reference.
- * This interface function adds a new thermal cooling device (fan/processor/...)
- * to /sys/class/thermal/ folder as cooling_device[0-*]. It tries to bind itself
- * to all the thermal zone devices registered at the same time.
- *
- * Return: a pointer to the created struct thermal_cooling_device or an
- * ERR_PTR. Caller must check return value with IS_ERR*() helpers.
- */
-struct thermal_cooling_device *
-devm_thermal_fwnode_cooling_device_register(struct device *dev, int fwn_index,
- const char *type, void *devdata,
- const struct thermal_cooling_device_ops *ops)
-{
- return __devm_thermal_fwnode_cooling_device_register(dev, dev_fwnode(dev), fwn_index,
- type, devdata, ops);
-}
-EXPORT_SYMBOL_GPL(devm_thermal_fwnode_cooling_device_register);
-
-
diff --git a/drivers/usb/misc/sisusbvga/sisusb_tables.h b/drivers/usb/misc/sisusbvga/sisusb_tables.h
deleted file mode 100644
index 56972f1ec..000000000
--- a/drivers/usb/misc/sisusbvga/sisusb_tables.h
+++ /dev/null
@@ -1,688 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
-/* $XFree86$ */
-/* $XdotOrg$ */
-/*
- * Data tables for init.c
- *
- * Copyright (C) 2001-2005 by Thomas Winischhofer, Vienna, Austria
- *
- * If distributed as part of the Linux kernel, the following license terms
- * apply:
- *
- * * This program is free software; you can redistribute it and/or modify
- * * it under the terms of the GNU General Public License as published by
- * * the Free Software Foundation; either version 2 of the named License,
- * * or any later version.
- * *
- * * This program is distributed in the hope that it will be useful,
- * * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * * GNU General Public License for more details.
- * *
- * * You should have received a copy of the GNU General Public License
- * * along with this program; if not, write to the Free Software
- * * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
- *
- * Otherwise, the following license terms apply:
- *
- * * Redistribution and use in source and binary forms, with or without
- * * modification, are permitted provided that the following conditions
- * * are met:
- * * 1) Redistributions of source code must retain the above copyright
- * * notice, this list of conditions and the following disclaimer.
- * * 2) Redistributions in binary form must reproduce the above copyright
- * * notice, this list of conditions and the following disclaimer in the
- * * documentation and/or other materials provided with the distribution.
- * * 3) The name of the author may not be used to endorse or promote products
- * * derived from this software without specific prior written permission.
- * *
- * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Thomas Winischhofer <thomas@winischhofer.net>
- *
- */
-
-#ifndef _SISUSB_TABLES_H_
-#define _SISUSB_TABLES_H_
-
-static const unsigned char SiS_MDA_DAC[] = {
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15,
- 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15,
- 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15,
- 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15,
- 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F
-};
-
-static const unsigned char SiS_CGA_DAC[] = {
- 0x00, 0x10, 0x04, 0x14, 0x01, 0x11, 0x09, 0x15,
- 0x00, 0x10, 0x04, 0x14, 0x01, 0x11, 0x09, 0x15,
- 0x2A, 0x3A, 0x2E, 0x3E, 0x2B, 0x3B, 0x2F, 0x3F,
- 0x2A, 0x3A, 0x2E, 0x3E, 0x2B, 0x3B, 0x2F, 0x3F,
- 0x00, 0x10, 0x04, 0x14, 0x01, 0x11, 0x09, 0x15,
- 0x00, 0x10, 0x04, 0x14, 0x01, 0x11, 0x09, 0x15,
- 0x2A, 0x3A, 0x2E, 0x3E, 0x2B, 0x3B, 0x2F, 0x3F,
- 0x2A, 0x3A, 0x2E, 0x3E, 0x2B, 0x3B, 0x2F, 0x3F
-};
-
-static const unsigned char SiS_EGA_DAC[] = {
- 0x00, 0x10, 0x04, 0x14, 0x01, 0x11, 0x05, 0x15,
- 0x20, 0x30, 0x24, 0x34, 0x21, 0x31, 0x25, 0x35,
- 0x08, 0x18, 0x0C, 0x1C, 0x09, 0x19, 0x0D, 0x1D,
- 0x28, 0x38, 0x2C, 0x3C, 0x29, 0x39, 0x2D, 0x3D,
- 0x02, 0x12, 0x06, 0x16, 0x03, 0x13, 0x07, 0x17,
- 0x22, 0x32, 0x26, 0x36, 0x23, 0x33, 0x27, 0x37,
- 0x0A, 0x1A, 0x0E, 0x1E, 0x0B, 0x1B, 0x0F, 0x1F,
- 0x2A, 0x3A, 0x2E, 0x3E, 0x2B, 0x3B, 0x2F, 0x3F
-};
-
-static const unsigned char SiS_VGA_DAC[] = {
- 0x00, 0x10, 0x04, 0x14, 0x01, 0x11, 0x09, 0x15,
- 0x2A, 0x3A, 0x2E, 0x3E, 0x2B, 0x3B, 0x2F, 0x3F,
- 0x00, 0x05, 0x08, 0x0B, 0x0E, 0x11, 0x14, 0x18,
- 0x1C, 0x20, 0x24, 0x28, 0x2D, 0x32, 0x38, 0x3F,
- 0x00, 0x10, 0x1F, 0x2F, 0x3F, 0x1F, 0x27, 0x2F,
- 0x37, 0x3F, 0x2D, 0x31, 0x36, 0x3A, 0x3F, 0x00,
- 0x07, 0x0E, 0x15, 0x1C, 0x0E, 0x11, 0x15, 0x18,
- 0x1C, 0x14, 0x16, 0x18, 0x1A, 0x1C, 0x00, 0x04,
- 0x08, 0x0C, 0x10, 0x08, 0x0A, 0x0C, 0x0E, 0x10,
- 0x0B, 0x0C, 0x0D, 0x0F, 0x10
-};
-
-static const struct SiS_St SiSUSB_SModeIDTable[] = {
- {0x03, 0x0010, 0x18, 0x02, 0x02, 0x00, 0x01, 0x03, 0x40},
- {0xff, 0x0000, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-};
-
-static const struct SiS_ModeResInfo SiSUSB_ModeResInfo[] = {
- {320, 200, 8, 8}, /* 0x00 */
- {320, 240, 8, 8}, /* 0x01 */
- {320, 400, 8, 8}, /* 0x02 */
- {400, 300, 8, 8}, /* 0x03 */
- {512, 384, 8, 8}, /* 0x04 */
- {640, 400, 8, 16}, /* 0x05 */
- {640, 480, 8, 16}, /* 0x06 */
- {800, 600, 8, 16}, /* 0x07 */
- {1024, 768, 8, 16}, /* 0x08 */
- {1280, 1024, 8, 16}, /* 0x09 */
- {1600, 1200, 8, 16}, /* 0x0a */
- {1920, 1440, 8, 16}, /* 0x0b */
- {2048, 1536, 8, 16}, /* 0x0c */
- {720, 480, 8, 16}, /* 0x0d */
- {720, 576, 8, 16}, /* 0x0e */
- {1280, 960, 8, 16}, /* 0x0f */
- {800, 480, 8, 16}, /* 0x10 */
- {1024, 576, 8, 16}, /* 0x11 */
- {1280, 720, 8, 16}, /* 0x12 */
- {856, 480, 8, 16}, /* 0x13 */
- {1280, 768, 8, 16}, /* 0x14 */
- {1400, 1050, 8, 16}, /* 0x15 */
- {1152, 864, 8, 16}, /* 0x16 */
- {848, 480, 8, 16}, /* 0x17 */
- {1360, 768, 8, 16}, /* 0x18 */
- {1024, 600, 8, 16}, /* 0x19 */
- {1152, 768, 8, 16}, /* 0x1a */
- {768, 576, 8, 16}, /* 0x1b */
- {1360, 1024, 8, 16}, /* 0x1c */
- {1680, 1050, 8, 16}, /* 0x1d */
- {1280, 800, 8, 16}, /* 0x1e */
- {1920, 1080, 8, 16}, /* 0x1f */
- {960, 540, 8, 16}, /* 0x20 */
- {960, 600, 8, 16} /* 0x21 */
-};
-
-static const struct SiS_StandTable SiSUSB_StandTable[] = {
- /* MD_3_400 - mode 0x03 - 400 */
- {
- 0x50, 0x18, 0x10, 0x1000,
- {0x00, 0x03, 0x00, 0x02},
- 0x67,
- {0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
- 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
- 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3,
- 0xff},
- {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07,
- 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
- 0x0c, 0x00, 0x0f, 0x08},
- {0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x00, 0xff}
- },
- /* Generic for VGA and higher */
- {
- 0x00, 0x00, 0x00, 0x0000,
- {0x01, 0x0f, 0x00, 0x0e},
- 0x23,
- {0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0x0b, 0x3e,
- 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0xea, 0x8c, 0xdf, 0x28, 0x40, 0xe7, 0x04, 0xa3,
- 0xff},
- {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x01, 0x00, 0x00, 0x00},
- {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0f, 0xff}
- }
-};
-
-static const struct SiS_Ext SiSUSB_EModeIDTable[] = {
- {0x2e, 0x0a1b, 0x0101, SIS_RI_640x480, 0x00, 0x00, 0x05, 0x05, 0x08, 2}, /* 640x480x8 */
- {0x2f, 0x0a1b, 0x0100, SIS_RI_640x400, 0x00, 0x00, 0x05, 0x05, 0x10, 0}, /* 640x400x8 */
- {0x30, 0x2a1b, 0x0103, SIS_RI_800x600, 0x00, 0x00, 0x07, 0x06, 0x00, 3}, /* 800x600x8 */
- {0x31, 0x4a1b, 0x0000, SIS_RI_720x480, 0x00, 0x00, 0x06, 0x06, 0x11, -1}, /* 720x480x8 */
- {0x32, 0x4a1b, 0x0000, SIS_RI_720x576, 0x00, 0x00, 0x06, 0x06, 0x12, -1}, /* 720x576x8 */
- {0x33, 0x4a1d, 0x0000, SIS_RI_720x480, 0x00, 0x00, 0x06, 0x06, 0x11, -1}, /* 720x480x16 */
- {0x34, 0x6a1d, 0x0000, SIS_RI_720x576, 0x00, 0x00, 0x06, 0x06, 0x12, -1}, /* 720x576x16 */
- {0x35, 0x4a1f, 0x0000, SIS_RI_720x480, 0x00, 0x00, 0x06, 0x06, 0x11, -1}, /* 720x480x32 */
- {0x36, 0x6a1f, 0x0000, SIS_RI_720x576, 0x00, 0x00, 0x06, 0x06, 0x12, -1}, /* 720x576x32 */
- {0x38, 0x0a1b, 0x0105, SIS_RI_1024x768, 0x00, 0x00, 0x08, 0x07, 0x13, 4}, /* 1024x768x8 */
- {0x3a, 0x0e3b, 0x0107, SIS_RI_1280x1024, 0x00, 0x00, 0x00, 0x00, 0x2f, 8}, /* 1280x1024x8 */
- {0x41, 0x9a1d, 0x010e, SIS_RI_320x200, 0x00, 0x00, 0x04, 0x04, 0x1a, 0}, /* 320x200x16 */
- {0x44, 0x0a1d, 0x0111, SIS_RI_640x480, 0x00, 0x00, 0x05, 0x05, 0x08, 2}, /* 640x480x16 */
- {0x47, 0x2a1d, 0x0114, SIS_RI_800x600, 0x00, 0x00, 0x07, 0x06, 0x00, 3}, /* 800x600x16 */
- {0x4a, 0x0a3d, 0x0117, SIS_RI_1024x768, 0x00, 0x00, 0x08, 0x07, 0x13, 4}, /* 1024x768x16 */
- {0x4d, 0x0e7d, 0x011a, SIS_RI_1280x1024, 0x00, 0x00, 0x00, 0x00, 0x2f, 8}, /* 1280x1024x16 */
- {0x50, 0x9a1b, 0x0132, SIS_RI_320x240, 0x00, 0x00, 0x04, 0x04, 0x1b, 2}, /* 320x240x8 */
- {0x51, 0xba1b, 0x0133, SIS_RI_400x300, 0x00, 0x00, 0x07, 0x07, 0x1c, 3}, /* 400x300x8 */
- {0x52, 0xba1b, 0x0134, SIS_RI_512x384, 0x00, 0x00, 0x00, 0x00, 0x1d, 4}, /* 512x384x8 */
- {0x56, 0x9a1d, 0x0135, SIS_RI_320x240, 0x00, 0x00, 0x04, 0x04, 0x1b, 2}, /* 320x240x16 */
- {0x57, 0xba1d, 0x0136, SIS_RI_400x300, 0x00, 0x00, 0x07, 0x07, 0x1c, 3}, /* 400x300x16 */
- {0x58, 0xba1d, 0x0137, SIS_RI_512x384, 0x00, 0x00, 0x00, 0x00, 0x1d, 4}, /* 512x384x16 */
- {0x59, 0x9a1b, 0x0138, SIS_RI_320x200, 0x00, 0x00, 0x04, 0x04, 0x1a, 0}, /* 320x200x8 */
- {0x5c, 0xba1f, 0x0000, SIS_RI_512x384, 0x00, 0x00, 0x00, 0x00, 0x1d, 4}, /* 512x384x32 */
- {0x5d, 0x0a1d, 0x0139, SIS_RI_640x400, 0x00, 0x00, 0x05, 0x07, 0x10, 0}, /* 640x400x16 */
- {0x5e, 0x0a1f, 0x0000, SIS_RI_640x400, 0x00, 0x00, 0x05, 0x07, 0x10, 0}, /* 640x400x32 */
- {0x62, 0x0a3f, 0x013a, SIS_RI_640x480, 0x00, 0x00, 0x05, 0x05, 0x08, 2}, /* 640x480x32 */
- {0x63, 0x2a3f, 0x013b, SIS_RI_800x600, 0x00, 0x00, 0x07, 0x06, 0x00, 3}, /* 800x600x32 */
- {0x64, 0x0a7f, 0x013c, SIS_RI_1024x768, 0x00, 0x00, 0x08, 0x07, 0x13, 4}, /* 1024x768x32 */
- {0x65, 0x0eff, 0x013d, SIS_RI_1280x1024, 0x00, 0x00, 0x00, 0x00, 0x2f, 8}, /* 1280x1024x32 */
- {0x70, 0x6a1b, 0x0000, SIS_RI_800x480, 0x00, 0x00, 0x07, 0x07, 0x1e, -1}, /* 800x480x8 */
- {0x71, 0x4a1b, 0x0000, SIS_RI_1024x576, 0x00, 0x00, 0x00, 0x00, 0x21, -1}, /* 1024x576x8 */
- {0x74, 0x4a1d, 0x0000, SIS_RI_1024x576, 0x00, 0x00, 0x00, 0x00, 0x21, -1}, /* 1024x576x16 */
- {0x75, 0x0a3d, 0x0000, SIS_RI_1280x720, 0x00, 0x00, 0x00, 0x00, 0x24, 5}, /* 1280x720x16 */
- {0x76, 0x6a1f, 0x0000, SIS_RI_800x480, 0x00, 0x00, 0x07, 0x07, 0x1e, -1}, /* 800x480x32 */
- {0x77, 0x4a1f, 0x0000, SIS_RI_1024x576, 0x00, 0x00, 0x00, 0x00, 0x21, -1}, /* 1024x576x32 */
- {0x78, 0x0a3f, 0x0000, SIS_RI_1280x720, 0x00, 0x00, 0x00, 0x00, 0x24, 5}, /* 1280x720x32 */
- {0x79, 0x0a3b, 0x0000, SIS_RI_1280x720, 0x00, 0x00, 0x00, 0x00, 0x24, 5}, /* 1280x720x8 */
- {0x7a, 0x6a1d, 0x0000, SIS_RI_800x480, 0x00, 0x00, 0x07, 0x07, 0x1e, -1}, /* 800x480x16 */
- {0x23, 0x0e3b, 0x0000, SIS_RI_1280x768, 0x00, 0x00, 0x00, 0x00, 0x27, 6}, /* 1280x768x8 */
- {0x24, 0x0e7d, 0x0000, SIS_RI_1280x768, 0x00, 0x00, 0x00, 0x00, 0x27, 6}, /* 1280x768x16 */
- {0x25, 0x0eff, 0x0000, SIS_RI_1280x768, 0x00, 0x00, 0x00, 0x00, 0x27, 6}, /* 1280x768x32 */
- {0x39, 0x6a1b, 0x0000, SIS_RI_848x480, 0x00, 0x00, 0x00, 0x00, 0x28, -1}, /* 848x480 */
- {0x3b, 0x6a3d, 0x0000, SIS_RI_848x480, 0x00, 0x00, 0x00, 0x00, 0x28,
- -1},
- {0x3e, 0x6a7f, 0x0000, SIS_RI_848x480, 0x00, 0x00, 0x00, 0x00, 0x28,
- -1},
- {0x3f, 0x6a1b, 0x0000, SIS_RI_856x480, 0x00, 0x00, 0x00, 0x00, 0x2a, -1}, /* 856x480 */
- {0x42, 0x6a3d, 0x0000, SIS_RI_856x480, 0x00, 0x00, 0x00, 0x00, 0x2a,
- -1},
- {0x45, 0x6a7f, 0x0000, SIS_RI_856x480, 0x00, 0x00, 0x00, 0x00, 0x2a,
- -1},
- {0x4f, 0x9a1f, 0x0000, SIS_RI_320x200, 0x00, 0x00, 0x04, 0x04, 0x1a, 0}, /* 320x200x32 */
- {0x53, 0x9a1f, 0x0000, SIS_RI_320x240, 0x00, 0x00, 0x04, 0x04, 0x1b, 2}, /* 320x240x32 */
- {0x54, 0xba1f, 0x0000, SIS_RI_400x300, 0x00, 0x00, 0x07, 0x07, 0x1c, 3}, /* 400x300x32 */
- {0x5f, 0x6a1b, 0x0000, SIS_RI_768x576, 0x00, 0x00, 0x06, 0x06, 0x2c, -1}, /* 768x576 */
- {0x60, 0x6a1d, 0x0000, SIS_RI_768x576, 0x00, 0x00, 0x06, 0x06, 0x2c,
- -1},
- {0x61, 0x6a3f, 0x0000, SIS_RI_768x576, 0x00, 0x00, 0x06, 0x06, 0x2c,
- -1},
- {0x1d, 0x6a1b, 0x0000, SIS_RI_960x540, 0x00, 0x00, 0x00, 0x00, 0x2d, -1}, /* 960x540 */
- {0x1e, 0x6a3d, 0x0000, SIS_RI_960x540, 0x00, 0x00, 0x00, 0x00, 0x2d,
- -1},
- {0x1f, 0x6a7f, 0x0000, SIS_RI_960x540, 0x00, 0x00, 0x00, 0x00, 0x2d,
- -1},
- {0x20, 0x6a1b, 0x0000, SIS_RI_960x600, 0x00, 0x00, 0x00, 0x00, 0x2e, -1}, /* 960x600 */
- {0x21, 0x6a3d, 0x0000, SIS_RI_960x600, 0x00, 0x00, 0x00, 0x00, 0x2e,
- -1},
- {0x22, 0x6a7f, 0x0000, SIS_RI_960x600, 0x00, 0x00, 0x00, 0x00, 0x2e,
- -1},
- {0x29, 0x4e1b, 0x0000, SIS_RI_1152x864, 0x00, 0x00, 0x00, 0x00, 0x33, -1}, /* 1152x864 */
- {0x2a, 0x4e3d, 0x0000, SIS_RI_1152x864, 0x00, 0x00, 0x00, 0x00, 0x33,
- -1},
- {0x2b, 0x4e7f, 0x0000, SIS_RI_1152x864, 0x00, 0x00, 0x00, 0x00, 0x33,
- -1},
- {0xff, 0x0000, 0x0000, 0, 0x00, 0x00, 0x00, 0x00, 0x00, -1}
-};
-
-static const struct SiS_Ext2 SiSUSB_RefIndex[] = {
- {0x085f, 0x0d, 0x03, 0x05, 0x05, 0x30, 800, 600, 0x40, 0x00, 0x00}, /* 0x0 */
- {0x0067, 0x0e, 0x04, 0x05, 0x05, 0x30, 800, 600, 0x40, 0x00, 0x00}, /* 0x1 */
- {0x0067, 0x0f, 0x08, 0x48, 0x05, 0x30, 800, 600, 0x40, 0x00, 0x00}, /* 0x2 */
- {0x0067, 0x10, 0x07, 0x8b, 0x05, 0x30, 800, 600, 0x40, 0x00, 0x00}, /* 0x3 */
- {0x0047, 0x11, 0x0a, 0x00, 0x05, 0x30, 800, 600, 0x40, 0x00, 0x00}, /* 0x4 */
- {0x0047, 0x12, 0x0d, 0x00, 0x05, 0x30, 800, 600, 0x40, 0x00, 0x00}, /* 0x5 */
- {0x0047, 0x13, 0x13, 0x00, 0x05, 0x30, 800, 600, 0x20, 0x00, 0x00}, /* 0x6 */
- {0x0107, 0x14, 0x1c, 0x00, 0x05, 0x30, 800, 600, 0x20, 0x00, 0x00}, /* 0x7 */
- {0xc85f, 0x05, 0x00, 0x04, 0x04, 0x2e, 640, 480, 0x40, 0x00, 0x00}, /* 0x8 */
- {0xc067, 0x06, 0x02, 0x04, 0x04, 0x2e, 640, 480, 0x40, 0x00, 0x00}, /* 0x9 */
- {0xc067, 0x07, 0x02, 0x47, 0x04, 0x2e, 640, 480, 0x40, 0x00, 0x00}, /* 0xa */
- {0xc067, 0x08, 0x03, 0x8a, 0x04, 0x2e, 640, 480, 0x40, 0x00, 0x00}, /* 0xb */
- {0xc047, 0x09, 0x05, 0x00, 0x04, 0x2e, 640, 480, 0x40, 0x00, 0x00}, /* 0xc */
- {0xc047, 0x0a, 0x09, 0x00, 0x04, 0x2e, 640, 480, 0x40, 0x00, 0x00}, /* 0xd */
- {0xc047, 0x0b, 0x0e, 0x00, 0x04, 0x2e, 640, 480, 0x40, 0x00, 0x00}, /* 0xe */
- {0xc047, 0x0c, 0x15, 0x00, 0x04, 0x2e, 640, 480, 0x40, 0x00, 0x00}, /* 0xf */
- {0x487f, 0x04, 0x00, 0x00, 0x00, 0x2f, 640, 400, 0x30, 0x55, 0x6e}, /* 0x10 */
- {0xc06f, 0x3c, 0x01, 0x06, 0x13, 0x31, 720, 480, 0x30, 0x00, 0x00}, /* 0x11 */
- {0x006f, 0x3d, 0x6f, 0x06, 0x14, 0x32, 720, 576, 0x30, 0x00, 0x00}, /* 0x12 (6f was 03) */
- {0x0087, 0x15, 0x06, 0x00, 0x06, 0x38, 1024, 768, 0x30, 0x00, 0x00}, /* 0x13 */
- {0xc877, 0x16, 0x0b, 0x06, 0x06, 0x38, 1024, 768, 0x20, 0x00, 0x00}, /* 0x14 */
- {0xc067, 0x17, 0x0f, 0x49, 0x06, 0x38, 1024, 768, 0x20, 0x00, 0x00}, /* 0x15 */
- {0x0067, 0x18, 0x11, 0x00, 0x06, 0x38, 1024, 768, 0x20, 0x00, 0x00}, /* 0x16 */
- {0x0047, 0x19, 0x16, 0x8c, 0x06, 0x38, 1024, 768, 0x20, 0x00, 0x00}, /* 0x17 */
- {0x0107, 0x1a, 0x1b, 0x00, 0x06, 0x38, 1024, 768, 0x10, 0x00, 0x00}, /* 0x18 */
- {0x0107, 0x1b, 0x1f, 0x00, 0x06, 0x38, 1024, 768, 0x10, 0x00, 0x00}, /* 0x19 */
- {0x407f, 0x00, 0x00, 0x00, 0x00, 0x41, 320, 200, 0x30, 0x56, 0x4e}, /* 0x1a */
- {0xc07f, 0x01, 0x00, 0x04, 0x04, 0x50, 320, 240, 0x30, 0x00, 0x00}, /* 0x1b */
- {0x007f, 0x02, 0x04, 0x05, 0x05, 0x51, 400, 300, 0x30, 0x00, 0x00}, /* 0x1c */
- {0xc077, 0x03, 0x0b, 0x06, 0x06, 0x52, 512, 384, 0x30, 0x00, 0x00}, /* 0x1d */
- {0x0077, 0x32, 0x40, 0x08, 0x18, 0x70, 800, 480, 0x30, 0x00, 0x00}, /* 0x1e */
- {0x0047, 0x33, 0x07, 0x08, 0x18, 0x70, 800, 480, 0x30, 0x00, 0x00}, /* 0x1f */
- {0x0047, 0x34, 0x0a, 0x08, 0x18, 0x70, 800, 480, 0x30, 0x00, 0x00}, /* 0x20 */
- {0x0077, 0x35, 0x0b, 0x09, 0x19, 0x71, 1024, 576, 0x30, 0x00, 0x00}, /* 0x21 */
- {0x0047, 0x36, 0x11, 0x09, 0x19, 0x71, 1024, 576, 0x30, 0x00, 0x00}, /* 0x22 */
- {0x0047, 0x37, 0x16, 0x09, 0x19, 0x71, 1024, 576, 0x30, 0x00, 0x00}, /* 0x23 */
- {0x1137, 0x38, 0x19, 0x0a, 0x0c, 0x75, 1280, 720, 0x30, 0x00, 0x00}, /* 0x24 */
- {0x1107, 0x39, 0x1e, 0x0a, 0x0c, 0x75, 1280, 720, 0x30, 0x00, 0x00}, /* 0x25 */
- {0x1307, 0x3a, 0x20, 0x0a, 0x0c, 0x75, 1280, 720, 0x30, 0x00, 0x00}, /* 0x26 */
- {0x0077, 0x42, 0x5b, 0x08, 0x11, 0x23, 1280, 768, 0x30, 0x00, 0x00}, /* 0x27 */
- {0x0087, 0x45, 0x57, 0x00, 0x16, 0x39, 848, 480, 0x30, 0x00, 0x00}, /* 0x28 38Hzi */
- {0xc067, 0x46, 0x55, 0x0b, 0x16, 0x39, 848, 480, 0x30, 0x00, 0x00}, /* 0x29 848x480-60Hz */
- {0x0087, 0x47, 0x57, 0x00, 0x17, 0x3f, 856, 480, 0x30, 0x00, 0x00}, /* 0x2a 856x480-38Hzi */
- {0xc067, 0x48, 0x57, 0x00, 0x17, 0x3f, 856, 480, 0x30, 0x00, 0x00}, /* 0x2b 856x480-60Hz */
- {0x006f, 0x4d, 0x71, 0x06, 0x15, 0x5f, 768, 576, 0x30, 0x00, 0x00}, /* 0x2c 768x576-56Hz */
- {0x0067, 0x52, 0x6a, 0x00, 0x1c, 0x1d, 960, 540, 0x30, 0x00, 0x00}, /* 0x2d 960x540 60Hz */
- {0x0077, 0x53, 0x6b, 0x0b, 0x1d, 0x20, 960, 600, 0x30, 0x00, 0x00}, /* 0x2e 960x600 60Hz */
- {0x0087, 0x1c, 0x11, 0x00, 0x07, 0x3a, 1280, 1024, 0x30, 0x00, 0x00}, /* 0x2f */
- {0x0137, 0x1d, 0x19, 0x07, 0x07, 0x3a, 1280, 1024, 0x00, 0x00, 0x00}, /* 0x30 */
- {0x0107, 0x1e, 0x1e, 0x00, 0x07, 0x3a, 1280, 1024, 0x00, 0x00, 0x00}, /* 0x31 */
- {0x0207, 0x1f, 0x20, 0x00, 0x07, 0x3a, 1280, 1024, 0x00, 0x00, 0x00}, /* 0x32 */
- {0x0127, 0x54, 0x6d, 0x00, 0x1a, 0x29, 1152, 864, 0x30, 0x00, 0x00}, /* 0x33 1152x864-60Hz */
- {0x0127, 0x44, 0x19, 0x00, 0x1a, 0x29, 1152, 864, 0x30, 0x00, 0x00}, /* 0x34 1152x864-75Hz */
- {0x0127, 0x4a, 0x1e, 0x00, 0x1a, 0x29, 1152, 864, 0x30, 0x00, 0x00}, /* 0x35 1152x864-85Hz */
- {0xffff, 0x00, 0x00, 0x00, 0x00, 0x00, 0, 0, 0, 0x00, 0x00}
-};
-
-static const struct SiS_CRT1Table SiSUSB_CRT1Table[] = {
- {{0x2d, 0x27, 0x28, 0x90, 0x2c, 0x80, 0xbf, 0x1f,
- 0x9c, 0x8e, 0x8f, 0x96, 0xb9, 0x30, 0x00, 0x00,
- 0x00}}, /* 0x0 */
- {{0x2d, 0x27, 0x28, 0x90, 0x2c, 0x80, 0x0b, 0x3e,
- 0xe9, 0x8b, 0xdf, 0xe7, 0x04, 0x00, 0x00, 0x00,
- 0x00}}, /* 0x1 */
- {{0x3d, 0x31, 0x31, 0x81, 0x37, 0x1f, 0x72, 0xf0,
- 0x58, 0x8c, 0x57, 0x57, 0x73, 0x20, 0x00, 0x05,
- 0x01}}, /* 0x2 */
- {{0x4f, 0x3f, 0x3f, 0x93, 0x45, 0x0d, 0x24, 0xf5,
- 0x02, 0x88, 0xff, 0xff, 0x25, 0x10, 0x00, 0x01,
- 0x01}}, /* 0x3 */
- {{0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
- 0x9c, 0x8e, 0x8f, 0x96, 0xb9, 0x30, 0x00, 0x05,
- 0x00}}, /* 0x4 */
- {{0x5f, 0x4f, 0x4f, 0x83, 0x55, 0x81, 0x0b, 0x3e,
- 0xe9, 0x8b, 0xdf, 0xe8, 0x0c, 0x00, 0x00, 0x05,
- 0x00}}, /* 0x5 */
- {{0x63, 0x4f, 0x4f, 0x87, 0x56, 0x9b, 0x06, 0x3e,
- 0xe8, 0x8a, 0xdf, 0xe7, 0x07, 0x00, 0x00, 0x01,
- 0x00}}, /* 0x6 */
- {{0x64, 0x4f, 0x4f, 0x88, 0x55, 0x9d, 0xf2, 0x1f,
- 0xe0, 0x83, 0xdf, 0xdf, 0xf3, 0x10, 0x00, 0x01,
- 0x00}}, /* 0x7 */
- {{0x63, 0x4f, 0x4f, 0x87, 0x5a, 0x81, 0xfb, 0x1f,
- 0xe0, 0x83, 0xdf, 0xdf, 0xfc, 0x10, 0x00, 0x05,
- 0x00}}, /* 0x8 */
- {{0x65, 0x4f, 0x4f, 0x89, 0x58, 0x80, 0xfb, 0x1f,
- 0xe0, 0x83, 0xdf, 0xdf, 0xfc, 0x10, 0x00, 0x05,
- 0x61}}, /* 0x9 */
- {{0x65, 0x4f, 0x4f, 0x89, 0x58, 0x80, 0x01, 0x3e,
- 0xe0, 0x83, 0xdf, 0xdf, 0x02, 0x00, 0x00, 0x05,
- 0x61}}, /* 0xa */
- {{0x67, 0x4f, 0x4f, 0x8b, 0x58, 0x81, 0x0d, 0x3e,
- 0xe0, 0x83, 0xdf, 0xdf, 0x0e, 0x00, 0x00, 0x05,
- 0x61}}, /* 0xb */
- {{0x65, 0x4f, 0x4f, 0x89, 0x57, 0x9f, 0xfb, 0x1f,
- 0xe6, 0x8a, 0xdf, 0xdf, 0xfc, 0x10, 0x00, 0x01,
- 0x00}}, /* 0xc */
- {{0x7b, 0x63, 0x63, 0x9f, 0x6a, 0x93, 0x6f, 0xf0,
- 0x58, 0x8a, 0x57, 0x57, 0x70, 0x20, 0x00, 0x05,
- 0x01}}, /* 0xd */
- {{0x7f, 0x63, 0x63, 0x83, 0x6c, 0x1c, 0x72, 0xf0,
- 0x58, 0x8c, 0x57, 0x57, 0x73, 0x20, 0x00, 0x06,
- 0x01}}, /* 0xe */
- {{0x7d, 0x63, 0x63, 0x81, 0x6e, 0x1d, 0x98, 0xf0,
- 0x7c, 0x82, 0x57, 0x57, 0x99, 0x00, 0x00, 0x06,
- 0x01}}, /* 0xf */
- {{0x7f, 0x63, 0x63, 0x83, 0x69, 0x13, 0x6f, 0xf0,
- 0x58, 0x8b, 0x57, 0x57, 0x70, 0x20, 0x00, 0x06,
- 0x01}}, /* 0x10 */
- {{0x7e, 0x63, 0x63, 0x82, 0x6b, 0x13, 0x75, 0xf0,
- 0x58, 0x8b, 0x57, 0x57, 0x76, 0x20, 0x00, 0x06,
- 0x01}}, /* 0x11 */
- {{0x81, 0x63, 0x63, 0x85, 0x6d, 0x18, 0x7a, 0xf0,
- 0x58, 0x8b, 0x57, 0x57, 0x7b, 0x20, 0x00, 0x06,
- 0x61}}, /* 0x12 */
- {{0x83, 0x63, 0x63, 0x87, 0x6e, 0x19, 0x81, 0xf0,
- 0x58, 0x8b, 0x57, 0x57, 0x82, 0x20, 0x00, 0x06,
- 0x61}}, /* 0x13 */
- {{0x85, 0x63, 0x63, 0x89, 0x6f, 0x1a, 0x91, 0xf0,
- 0x58, 0x8b, 0x57, 0x57, 0x92, 0x20, 0x00, 0x06,
- 0x61}}, /* 0x14 */
- {{0x99, 0x7f, 0x7f, 0x9d, 0x84, 0x1a, 0x96, 0x1f,
- 0x7f, 0x83, 0x7f, 0x7f, 0x97, 0x10, 0x00, 0x02,
- 0x00}}, /* 0x15 */
- {{0xa3, 0x7f, 0x7f, 0x87, 0x86, 0x97, 0x24, 0xf5,
- 0x02, 0x88, 0xff, 0xff, 0x25, 0x10, 0x00, 0x02,
- 0x01}}, /* 0x16 */
- {{0xa1, 0x7f, 0x7f, 0x85, 0x86, 0x97, 0x24, 0xf5,
- 0x02, 0x88, 0xff, 0xff, 0x25, 0x10, 0x00, 0x02,
- 0x01}}, /* 0x17 */
- {{0x9f, 0x7f, 0x7f, 0x83, 0x85, 0x91, 0x1e, 0xf5,
- 0x00, 0x83, 0xff, 0xff, 0x1f, 0x10, 0x00, 0x02,
- 0x01}}, /* 0x18 */
- {{0xa7, 0x7f, 0x7f, 0x8b, 0x89, 0x95, 0x26, 0xf5,
- 0x00, 0x83, 0xff, 0xff, 0x27, 0x10, 0x00, 0x02,
- 0x01}}, /* 0x19 */
- {{0xa9, 0x7f, 0x7f, 0x8d, 0x8c, 0x9a, 0x2c, 0xf5,
- 0x00, 0x83, 0xff, 0xff, 0x2d, 0x14, 0x00, 0x02,
- 0x62}}, /* 0x1a */
- {{0xab, 0x7f, 0x7f, 0x8f, 0x8d, 0x9b, 0x35, 0xf5,
- 0x00, 0x83, 0xff, 0xff, 0x36, 0x14, 0x00, 0x02,
- 0x62}}, /* 0x1b */
- {{0xcf, 0x9f, 0x9f, 0x93, 0xb2, 0x01, 0x14, 0xba,
- 0x00, 0x83, 0xff, 0xff, 0x15, 0x00, 0x00, 0x03,
- 0x00}}, /* 0x1c */
- {{0xce, 0x9f, 0x9f, 0x92, 0xa9, 0x17, 0x28, 0x5a,
- 0x00, 0x83, 0xff, 0xff, 0x29, 0x09, 0x00, 0x07,
- 0x01}}, /* 0x1d */
- {{0xce, 0x9f, 0x9f, 0x92, 0xa5, 0x17, 0x28, 0x5a,
- 0x00, 0x83, 0xff, 0xff, 0x29, 0x09, 0x00, 0x07,
- 0x01}}, /* 0x1e */
- {{0xd3, 0x9f, 0x9f, 0x97, 0xab, 0x1f, 0x2e, 0x5a,
- 0x00, 0x83, 0xff, 0xff, 0x2f, 0x09, 0x00, 0x07,
- 0x01}}, /* 0x1f */
- {{0x09, 0xc7, 0xc7, 0x8d, 0xd3, 0x0b, 0xe0, 0x10,
- 0xb0, 0x83, 0xaf, 0xaf, 0xe1, 0x2f, 0x01, 0x04,
- 0x00}}, /* 0x20 */
- {{0x09, 0xc7, 0xc7, 0x8d, 0xd3, 0x0b, 0xe0, 0x10,
- 0xb0, 0x83, 0xaf, 0xaf, 0xe1, 0x2f, 0x01, 0x04,
- 0x00}}, /* 0x21 */
- {{0x09, 0xc7, 0xc7, 0x8d, 0xd3, 0x0b, 0xe0, 0x10,
- 0xb0, 0x83, 0xaf, 0xaf, 0xe1, 0x2f, 0x01, 0x04,
- 0x00}}, /* 0x22 */
- {{0x09, 0xc7, 0xc7, 0x8d, 0xd3, 0x0b, 0xe0, 0x10,
- 0xb0, 0x83, 0xaf, 0xaf, 0xe1, 0x2f, 0x01, 0x04,
- 0x00}}, /* 0x23 */
- {{0x09, 0xc7, 0xc7, 0x8d, 0xd3, 0x0b, 0xe0, 0x10,
- 0xb0, 0x83, 0xaf, 0xaf, 0xe1, 0x2f, 0x01, 0x04,
- 0x00}}, /* 0x24 */
- {{0x09, 0xc7, 0xc7, 0x8d, 0xd3, 0x0b, 0xe0, 0x10,
- 0xb0, 0x83, 0xaf, 0xaf, 0xe1, 0x2f, 0x01, 0x04,
- 0x00}}, /* 0x25 */
- {{0x09, 0xc7, 0xc7, 0x8d, 0xd3, 0x0b, 0xe0, 0x10,
- 0xb0, 0x83, 0xaf, 0xaf, 0xe1, 0x2f, 0x01, 0x04,
- 0x00}}, /* 0x26 */
- {{0x40, 0xef, 0xef, 0x84, 0x03, 0x1d, 0xda, 0x1f,
- 0xa0, 0x83, 0x9f, 0x9f, 0xdb, 0x1f, 0x41, 0x01,
- 0x00}}, /* 0x27 */
- {{0x43, 0xef, 0xef, 0x87, 0x06, 0x00, 0xd4, 0x1f,
- 0xa0, 0x83, 0x9f, 0x9f, 0xd5, 0x1f, 0x41, 0x05,
- 0x63}}, /* 0x28 */
- {{0x45, 0xef, 0xef, 0x89, 0x07, 0x01, 0xd9, 0x1f,
- 0xa0, 0x83, 0x9f, 0x9f, 0xda, 0x1f, 0x41, 0x05,
- 0x63}}, /* 0x29 */
- {{0x40, 0xef, 0xef, 0x84, 0x03, 0x1d, 0xda, 0x1f,
- 0xa0, 0x83, 0x9f, 0x9f, 0xdb, 0x1f, 0x41, 0x01,
- 0x00}}, /* 0x2a */
- {{0x40, 0xef, 0xef, 0x84, 0x03, 0x1d, 0xda, 0x1f,
- 0xa0, 0x83, 0x9f, 0x9f, 0xdb, 0x1f, 0x41, 0x01,
- 0x00}}, /* 0x2b */
- {{0x40, 0xef, 0xef, 0x84, 0x03, 0x1d, 0xda, 0x1f,
- 0xa0, 0x83, 0x9f, 0x9f, 0xdb, 0x1f, 0x41, 0x01,
- 0x00}}, /* 0x2c */
- {{0x59, 0xff, 0xff, 0x9d, 0x17, 0x13, 0x33, 0xba,
- 0x00, 0x83, 0xff, 0xff, 0x34, 0x0f, 0x41, 0x05,
- 0x44}}, /* 0x2d */
- {{0x5b, 0xff, 0xff, 0x9f, 0x18, 0x14, 0x38, 0xba,
- 0x00, 0x83, 0xff, 0xff, 0x39, 0x0f, 0x41, 0x05,
- 0x44}}, /* 0x2e */
- {{0x5b, 0xff, 0xff, 0x9f, 0x18, 0x14, 0x3d, 0xba,
- 0x00, 0x83, 0xff, 0xff, 0x3e, 0x0f, 0x41, 0x05,
- 0x44}}, /* 0x2f */
- {{0x5d, 0xff, 0xff, 0x81, 0x19, 0x95, 0x41, 0xba,
- 0x00, 0x84, 0xff, 0xff, 0x42, 0x0f, 0x41, 0x05,
- 0x44}}, /* 0x30 */
- {{0x55, 0xff, 0xff, 0x99, 0x0d, 0x0c, 0x3e, 0xba,
- 0x00, 0x84, 0xff, 0xff, 0x3f, 0x0f, 0x41, 0x05,
- 0x00}}, /* 0x31 */
- {{0x7f, 0x63, 0x63, 0x83, 0x6c, 0x1c, 0x72, 0xba,
- 0x27, 0x8b, 0xdf, 0xdf, 0x73, 0x00, 0x00, 0x06,
- 0x01}}, /* 0x32 */
- {{0x7f, 0x63, 0x63, 0x83, 0x69, 0x13, 0x6f, 0xba,
- 0x26, 0x89, 0xdf, 0xdf, 0x6f, 0x00, 0x00, 0x06,
- 0x01}}, /* 0x33 */
- {{0x7f, 0x63, 0x63, 0x82, 0x6b, 0x13, 0x75, 0xba,
- 0x29, 0x8c, 0xdf, 0xdf, 0x75, 0x00, 0x00, 0x06,
- 0x01}}, /* 0x34 */
- {{0xa3, 0x7f, 0x7f, 0x87, 0x86, 0x97, 0x24, 0xf1,
- 0xaf, 0x85, 0x3f, 0x3f, 0x25, 0x30, 0x00, 0x02,
- 0x01}}, /* 0x35 */
- {{0x9f, 0x7f, 0x7f, 0x83, 0x85, 0x91, 0x1e, 0xf1,
- 0xad, 0x81, 0x3f, 0x3f, 0x1f, 0x30, 0x00, 0x02,
- 0x01}}, /* 0x36 */
- {{0xa7, 0x7f, 0x7f, 0x88, 0x89, 0x95, 0x26, 0xf1,
- 0xb1, 0x85, 0x3f, 0x3f, 0x27, 0x30, 0x00, 0x02,
- 0x01}}, /* 0x37 */
- {{0xce, 0x9f, 0x9f, 0x92, 0xa9, 0x17, 0x28, 0xc4,
- 0x7a, 0x8e, 0xcf, 0xcf, 0x29, 0x21, 0x00, 0x07,
- 0x01}}, /* 0x38 */
- {{0xce, 0x9f, 0x9f, 0x92, 0xa5, 0x17, 0x28, 0xd4,
- 0x7a, 0x8e, 0xcf, 0xcf, 0x29, 0x21, 0x00, 0x07,
- 0x01}}, /* 0x39 */
- {{0xd3, 0x9f, 0x9f, 0x97, 0xab, 0x1f, 0x2e, 0xd4,
- 0x7d, 0x81, 0xcf, 0xcf, 0x2f, 0x21, 0x00, 0x07,
- 0x01}}, /* 0x3a */
- {{0xdc, 0x9f, 0x9f, 0x80, 0xaf, 0x9d, 0xe6, 0xff,
- 0xc0, 0x83, 0xbf, 0xbf, 0xe7, 0x10, 0x00, 0x07,
- 0x01}}, /* 0x3b */
- {{0x6b, 0x59, 0x59, 0x8f, 0x5e, 0x8c, 0x0b, 0x3e,
- 0xe9, 0x8b, 0xdf, 0xe7, 0x04, 0x00, 0x00, 0x05,
- 0x00}}, /* 0x3c */
- {{0x6d, 0x59, 0x59, 0x91, 0x60, 0x89, 0x53, 0xf0,
- 0x41, 0x84, 0x3f, 0x3f, 0x54, 0x00, 0x00, 0x05,
- 0x41}}, /* 0x3d */
- {{0x86, 0x6a, 0x6a, 0x8a, 0x74, 0x06, 0x8c, 0x15,
- 0x4f, 0x83, 0xef, 0xef, 0x8d, 0x30, 0x00, 0x02,
- 0x00}}, /* 0x3e */
- {{0x81, 0x6a, 0x6a, 0x85, 0x70, 0x00, 0x0f, 0x3e,
- 0xeb, 0x8e, 0xdf, 0xdf, 0x10, 0x00, 0x00, 0x02,
- 0x00}}, /* 0x3f */
- {{0xa3, 0x7f, 0x7f, 0x87, 0x86, 0x97, 0x1e, 0xf1,
- 0xae, 0x85, 0x57, 0x57, 0x1f, 0x30, 0x00, 0x02,
- 0x01}}, /* 0x40 */
- {{0xa3, 0x7f, 0x7f, 0x87, 0x86, 0x97, 0x24, 0xf5,
- 0x02, 0x88, 0xff, 0xff, 0x25, 0x10, 0x00, 0x02,
- 0x01}}, /* 0x41 */
- {{0xce, 0x9f, 0x9f, 0x92, 0xa9, 0x17, 0x20, 0xf5,
- 0x03, 0x88, 0xff, 0xff, 0x21, 0x10, 0x00, 0x07,
- 0x01}}, /* 0x42 */
- {{0xe6, 0xae, 0xae, 0x8a, 0xbd, 0x90, 0x3d, 0x10,
- 0x1a, 0x8d, 0x19, 0x19, 0x3e, 0x2f, 0x00, 0x03,
- 0x00}}, /* 0x43 */
- {{0xc3, 0x8f, 0x8f, 0x87, 0x9b, 0x0b, 0x82, 0xef,
- 0x60, 0x83, 0x5f, 0x5f, 0x83, 0x10, 0x00, 0x07,
- 0x01}}, /* 0x44 */
- {{0x86, 0x69, 0x69, 0x8A, 0x74, 0x06, 0x8C, 0x15,
- 0x4F, 0x83, 0xEF, 0xEF, 0x8D, 0x30, 0x00, 0x02,
- 0x00}}, /* 0x45 */
- {{0x83, 0x69, 0x69, 0x87, 0x6f, 0x1d, 0x03, 0x3E,
- 0xE5, 0x8d, 0xDF, 0xe4, 0x04, 0x00, 0x00, 0x06,
- 0x00}}, /* 0x46 */
- {{0x86, 0x6A, 0x6A, 0x8A, 0x74, 0x06, 0x8C, 0x15,
- 0x4F, 0x83, 0xEF, 0xEF, 0x8D, 0x30, 0x00, 0x02,
- 0x00}}, /* 0x47 */
- {{0x81, 0x6A, 0x6A, 0x85, 0x70, 0x00, 0x0F, 0x3E,
- 0xEB, 0x8E, 0xDF, 0xDF, 0x10, 0x00, 0x00, 0x02,
- 0x00}}, /* 0x48 */
- {{0xdd, 0xa9, 0xa9, 0x81, 0xb4, 0x97, 0x26, 0xfd,
- 0x01, 0x8d, 0xff, 0x00, 0x27, 0x10, 0x00, 0x03,
- 0x01}}, /* 0x49 */
- {{0xd9, 0x8f, 0x8f, 0x9d, 0xba, 0x0a, 0x8a, 0xff,
- 0x60, 0x8b, 0x5f, 0x5f, 0x8b, 0x10, 0x00, 0x03,
- 0x01}}, /* 0x4a */
- {{0xea, 0xae, 0xae, 0x8e, 0xba, 0x82, 0x40, 0x10,
- 0x1b, 0x87, 0x19, 0x1a, 0x41, 0x0f, 0x00, 0x03,
- 0x00}}, /* 0x4b */
- {{0xd3, 0x9f, 0x9f, 0x97, 0xab, 0x1f, 0xf1, 0xff,
- 0xc0, 0x83, 0xbf, 0xbf, 0xf2, 0x10, 0x00, 0x07,
- 0x01}}, /* 0x4c */
- {{0x75, 0x5f, 0x5f, 0x99, 0x66, 0x90, 0x53, 0xf0,
- 0x41, 0x84, 0x3f, 0x3f, 0x54, 0x00, 0x00, 0x05,
- 0x41}},
- {{0x2d, 0x27, 0x28, 0x90, 0x2c, 0x80, 0x0b, 0x3e,
- 0xe9, 0x8b, 0xdf, 0xe7, 0x04, 0x00, 0x00, 0x00,
- 0x00}}, /* 0x4e */
- {{0xcd, 0x9f, 0x9f, 0x91, 0xab, 0x1c, 0x3a, 0xff,
- 0x20, 0x83, 0x1f, 0x1f, 0x3b, 0x10, 0x00, 0x07,
- 0x21}}, /* 0x4f */
- {{0x15, 0xd1, 0xd1, 0x99, 0xe2, 0x19, 0x3d, 0x10,
- 0x1a, 0x8d, 0x19, 0x19, 0x3e, 0x2f, 0x01, 0x0c,
- 0x20}}, /* 0x50 */
- {{0x0e, 0xef, 0xef, 0x92, 0xfe, 0x03, 0x30, 0xf0,
- 0x1e, 0x83, 0x1b, 0x1c, 0x31, 0x00, 0x01, 0x00,
- 0x61}}, /* 0x51 */
- {{0x85, 0x77, 0x77, 0x89, 0x7d, 0x01, 0x31, 0xf0,
- 0x1e, 0x84, 0x1b, 0x1c, 0x32, 0x00, 0x00, 0x02,
- 0x41}}, /* 0x52 */
- {{0x87, 0x77, 0x77, 0x8b, 0x81, 0x0b, 0x68, 0xf0,
- 0x5a, 0x80, 0x57, 0x57, 0x69, 0x00, 0x00, 0x02,
- 0x01}}, /* 0x53 */
- {{0xcd, 0x8f, 0x8f, 0x91, 0x9b, 0x1b, 0x7a, 0xff,
- 0x64, 0x8c, 0x5f, 0x62, 0x7b, 0x10, 0x00, 0x07,
- 0x41}} /* 0x54 */
-};
-
-static const struct SiS_VCLKData SiSUSB_VCLKData[] = {
- {0x1b, 0xe1, 25}, /* 0x00 */
- {0x4e, 0xe4, 28}, /* 0x01 */
- {0x57, 0xe4, 31}, /* 0x02 */
- {0xc3, 0xc8, 36}, /* 0x03 */
- {0x42, 0xe2, 40}, /* 0x04 */
- {0xfe, 0xcd, 43}, /* 0x05 */
- {0x5d, 0xc4, 44}, /* 0x06 */
- {0x52, 0xe2, 49}, /* 0x07 */
- {0x53, 0xe2, 50}, /* 0x08 */
- {0x74, 0x67, 52}, /* 0x09 */
- {0x6d, 0x66, 56}, /* 0x0a */
- {0x5a, 0x64, 65}, /* 0x0b */
- {0x46, 0x44, 67}, /* 0x0c */
- {0xb1, 0x46, 68}, /* 0x0d */
- {0xd3, 0x4a, 72}, /* 0x0e */
- {0x29, 0x61, 75}, /* 0x0f */
- {0x6e, 0x46, 76}, /* 0x10 */
- {0x2b, 0x61, 78}, /* 0x11 */
- {0x31, 0x42, 79}, /* 0x12 */
- {0xab, 0x44, 83}, /* 0x13 */
- {0x46, 0x25, 84}, /* 0x14 */
- {0x78, 0x29, 86}, /* 0x15 */
- {0x62, 0x44, 94}, /* 0x16 */
- {0x2b, 0x41, 104}, /* 0x17 */
- {0x3a, 0x23, 105}, /* 0x18 */
- {0x70, 0x44, 108}, /* 0x19 */
- {0x3c, 0x23, 109}, /* 0x1a */
- {0x5e, 0x43, 113}, /* 0x1b */
- {0xbc, 0x44, 116}, /* 0x1c */
- {0xe0, 0x46, 132}, /* 0x1d */
- {0x54, 0x42, 135}, /* 0x1e */
- {0xea, 0x2a, 139}, /* 0x1f */
- {0x41, 0x22, 157}, /* 0x20 */
- {0x70, 0x24, 162}, /* 0x21 */
- {0x30, 0x21, 175}, /* 0x22 */
- {0x4e, 0x22, 189}, /* 0x23 */
- {0xde, 0x26, 194}, /* 0x24 */
- {0x62, 0x06, 202}, /* 0x25 */
- {0x3f, 0x03, 229}, /* 0x26 */
- {0xb8, 0x06, 234}, /* 0x27 */
- {0x34, 0x02, 253}, /* 0x28 */
- {0x58, 0x04, 255}, /* 0x29 */
- {0x24, 0x01, 265}, /* 0x2a */
- {0x9b, 0x02, 267}, /* 0x2b */
- {0x70, 0x05, 270}, /* 0x2c */
- {0x25, 0x01, 272}, /* 0x2d */
- {0x9c, 0x02, 277}, /* 0x2e */
- {0x27, 0x01, 286}, /* 0x2f */
- {0x3c, 0x02, 291}, /* 0x30 */
- {0xef, 0x0a, 292}, /* 0x31 */
- {0xf6, 0x0a, 310}, /* 0x32 */
- {0x95, 0x01, 315}, /* 0x33 */
- {0xf0, 0x09, 324}, /* 0x34 */
- {0xfe, 0x0a, 331}, /* 0x35 */
- {0xf3, 0x09, 332}, /* 0x36 */
- {0xea, 0x08, 340}, /* 0x37 */
- {0xe8, 0x07, 376}, /* 0x38 */
- {0xde, 0x06, 389}, /* 0x39 */
- {0x52, 0x2a, 54}, /* 0x3a 301 TV */
- {0x52, 0x6a, 27}, /* 0x3b 301 TV */
- {0x62, 0x24, 70}, /* 0x3c 301 TV */
- {0x62, 0x64, 70}, /* 0x3d 301 TV */
- {0xa8, 0x4c, 30}, /* 0x3e 301 TV */
- {0x20, 0x26, 33}, /* 0x3f 301 TV */
- {0x31, 0xc2, 39}, /* 0x40 */
- {0x60, 0x36, 30}, /* 0x41 Chrontel */
- {0x40, 0x4a, 28}, /* 0x42 Chrontel */
- {0x9f, 0x46, 44}, /* 0x43 Chrontel */
- {0x97, 0x2c, 26}, /* 0x44 */
- {0x44, 0xe4, 25}, /* 0x45 Chrontel */
- {0x7e, 0x32, 47}, /* 0x46 Chrontel */
- {0x8a, 0x24, 31}, /* 0x47 Chrontel */
- {0x97, 0x2c, 26}, /* 0x48 Chrontel */
- {0xce, 0x3c, 39}, /* 0x49 */
- {0x52, 0x4a, 36}, /* 0x4a Chrontel */
- {0x34, 0x61, 95}, /* 0x4b */
- {0x78, 0x27, 108}, /* 0x4c - was 102 */
- {0x66, 0x43, 123}, /* 0x4d Modes 0x26-0x28 (1400x1050) */
- {0x41, 0x4e, 21}, /* 0x4e */
- {0xa1, 0x4a, 29}, /* 0x4f Chrontel */
- {0x19, 0x42, 42}, /* 0x50 */
- {0x54, 0x46, 58}, /* 0x51 Chrontel */
- {0x25, 0x42, 61}, /* 0x52 */
- {0x44, 0x44, 66}, /* 0x53 Chrontel */
- {0x3a, 0x62, 70}, /* 0x54 Chrontel */
- {0x62, 0xc6, 34}, /* 0x55 848x480-60 */
- {0x6a, 0xc6, 37}, /* 0x56 848x480-75 - TEMP */
- {0xbf, 0xc8, 35}, /* 0x57 856x480-38i,60 */
- {0x30, 0x23, 88}, /* 0x58 1360x768-62 (is 60Hz!) */
- {0x52, 0x07, 149}, /* 0x59 1280x960-85 */
- {0x56, 0x07, 156}, /* 0x5a 1400x1050-75 */
- {0x70, 0x29, 81}, /* 0x5b 1280x768 LCD */
- {0x45, 0x25, 83}, /* 0x5c 1280x800 */
- {0x70, 0x0a, 147}, /* 0x5d 1680x1050 */
- {0x70, 0x24, 162}, /* 0x5e 1600x1200 */
- {0x5a, 0x64, 65}, /* 0x5f 1280x720 - temp */
- {0x63, 0x46, 68}, /* 0x60 1280x768_2 */
- {0x31, 0x42, 79}, /* 0x61 1280x768_3 - temp */
- {0, 0, 0}, /* 0x62 - custom (will be filled out at run-time) */
- {0x5a, 0x64, 65}, /* 0x63 1280x720 (LCD LVDS) */
- {0x70, 0x28, 90}, /* 0x64 1152x864@60 */
- {0x41, 0xc4, 32}, /* 0x65 848x480@60 */
- {0x5c, 0xc6, 32}, /* 0x66 856x480@60 */
- {0x76, 0xe7, 27}, /* 0x67 720x480@60 */
- {0x5f, 0xc6, 33}, /* 0x68 720/768x576@60 */
- {0x52, 0x27, 75}, /* 0x69 1920x1080i 60Hz interlaced */
- {0x7c, 0x6b, 38}, /* 0x6a 960x540@60 */
- {0xe3, 0x56, 41}, /* 0x6b 960x600@60 */
- {0x45, 0x25, 83}, /* 0x6c 1280x800 */
- {0x70, 0x28, 90}, /* 0x6d 1152x864@60 */
- {0x15, 0xe1, 20}, /* 0x6e 640x400@60 (fake, not actually used) */
- {0x5f, 0xc6, 33}, /* 0x6f 720x576@60 */
- {0x37, 0x5a, 10}, /* 0x70 320x200@60 (fake, not actually used) */
- {0x2b, 0xc2, 35} /* 0x71 768@576@60 */
-};
-
-#endif
diff --git a/drivers/usb/phy/phy-mv-usb.h b/drivers/usb/phy/phy-mv-usb.h
deleted file mode 100644
index 5d5c0abb0..000000000
--- a/drivers/usb/phy/phy-mv-usb.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
- */
-
-#ifndef __MV_USB_OTG_CONTROLLER__
-#define __MV_USB_OTG_CONTROLLER__
-
-#include <linux/types.h>
-
-/* Command Register Bit Masks */
-#define USBCMD_RUN_STOP (0x00000001)
-#define USBCMD_CTRL_RESET (0x00000002)
-
-/* otgsc Register Bit Masks */
-#define OTGSC_CTRL_VUSB_DISCHARGE 0x00000001
-#define OTGSC_CTRL_VUSB_CHARGE 0x00000002
-#define OTGSC_CTRL_OTG_TERM 0x00000008
-#define OTGSC_CTRL_DATA_PULSING 0x00000010
-#define OTGSC_STS_USB_ID 0x00000100
-#define OTGSC_STS_A_VBUS_VALID 0x00000200
-#define OTGSC_STS_A_SESSION_VALID 0x00000400
-#define OTGSC_STS_B_SESSION_VALID 0x00000800
-#define OTGSC_STS_B_SESSION_END 0x00001000
-#define OTGSC_STS_1MS_TOGGLE 0x00002000
-#define OTGSC_STS_DATA_PULSING 0x00004000
-#define OTGSC_INTSTS_USB_ID 0x00010000
-#define OTGSC_INTSTS_A_VBUS_VALID 0x00020000
-#define OTGSC_INTSTS_A_SESSION_VALID 0x00040000
-#define OTGSC_INTSTS_B_SESSION_VALID 0x00080000
-#define OTGSC_INTSTS_B_SESSION_END 0x00100000
-#define OTGSC_INTSTS_1MS 0x00200000
-#define OTGSC_INTSTS_DATA_PULSING 0x00400000
-#define OTGSC_INTR_USB_ID 0x01000000
-#define OTGSC_INTR_A_VBUS_VALID 0x02000000
-#define OTGSC_INTR_A_SESSION_VALID 0x04000000
-#define OTGSC_INTR_B_SESSION_VALID 0x08000000
-#define OTGSC_INTR_B_SESSION_END 0x10000000
-#define OTGSC_INTR_1MS_TIMER 0x20000000
-#define OTGSC_INTR_DATA_PULSING 0x40000000
-
-#define CAPLENGTH_MASK (0xff)
-
-/* Timer's interval, unit 10ms */
-#define T_A_WAIT_VRISE 100
-#define T_A_WAIT_BCON 2000
-#define T_A_AIDL_BDIS 100
-#define T_A_BIDL_ADIS 20
-#define T_B_ASE0_BRST 400
-#define T_B_SE0_SRP 300
-#define T_B_SRP_FAIL 2000
-#define T_B_DATA_PLS 10
-#define T_B_SRP_INIT 100
-#define T_A_SRP_RSPNS 10
-#define T_A_DRV_RSM 5
-
-enum otg_function {
- OTG_B_DEVICE = 0,
- OTG_A_DEVICE
-};
-
-enum mv_otg_timer {
- A_WAIT_BCON_TIMER = 0,
- OTG_TIMER_NUM
-};
-
-/* PXA OTG state machine */
-struct mv_otg_ctrl {
- /* internal variables */
- u8 a_set_b_hnp_en; /* A-Device set b_hnp_en */
- u8 b_srp_done;
- u8 b_hnp_en;
-
- /* OTG inputs */
- u8 a_bus_drop;
- u8 a_bus_req;
- u8 a_clr_err;
- u8 a_bus_resume;
- u8 a_bus_suspend;
- u8 a_conn;
- u8 a_sess_vld;
- u8 a_srp_det;
- u8 a_vbus_vld;
- u8 b_bus_req; /* B-Device Require Bus */
- u8 b_bus_resume;
- u8 b_bus_suspend;
- u8 b_conn;
- u8 b_se0_srp;
- u8 b_sess_end;
- u8 b_sess_vld;
- u8 id;
- u8 a_suspend_req;
-
- /*Timer event */
- u8 a_aidl_bdis_timeout;
- u8 b_ase0_brst_timeout;
- u8 a_bidl_adis_timeout;
- u8 a_wait_bcon_timeout;
-
- struct timer_list timer[OTG_TIMER_NUM];
-};
-
-#define VUSBHS_MAX_PORTS 8
-
-struct mv_otg_regs {
- u32 usbcmd; /* Command register */
- u32 usbsts; /* Status register */
- u32 usbintr; /* Interrupt enable */
- u32 frindex; /* Frame index */
- u32 reserved1[1];
- u32 deviceaddr; /* Device Address */
- u32 eplistaddr; /* Endpoint List Address */
- u32 ttctrl; /* HOST TT status and control */
- u32 burstsize; /* Programmable Burst Size */
- u32 txfilltuning; /* Host Transmit Pre-Buffer Packet Tuning */
- u32 reserved[4];
- u32 epnak; /* Endpoint NAK */
- u32 epnaken; /* Endpoint NAK Enable */
- u32 configflag; /* Configured Flag register */
- u32 portsc[VUSBHS_MAX_PORTS]; /* Port Status/Control x, x = 1..8 */
- u32 otgsc;
- u32 usbmode; /* USB Host/Device mode */
- u32 epsetupstat; /* Endpoint Setup Status */
- u32 epprime; /* Endpoint Initialize */
- u32 epflush; /* Endpoint De-initialize */
- u32 epstatus; /* Endpoint Status */
- u32 epcomplete; /* Endpoint Interrupt On Complete */
- u32 epctrlx[16]; /* Endpoint Control, where x = 0.. 15 */
- u32 mcr; /* Mux Control */
- u32 isr; /* Interrupt Status */
- u32 ier; /* Interrupt Enable */
-};
-
-struct mv_otg {
- struct usb_phy phy;
- struct mv_otg_ctrl otg_ctrl;
-
- /* base address */
- void __iomem *phy_regs;
- void __iomem *cap_regs;
- struct mv_otg_regs __iomem *op_regs;
-
- struct platform_device *pdev;
- int irq;
- u32 irq_status;
- u32 irq_en;
-
- struct delayed_work work;
- struct workqueue_struct *qwork;
-
- spinlock_t wq_lock;
-
- struct mv_usb_platform_data *pdata;
-
- unsigned int active;
- unsigned int clock_gating;
- struct clk *clk;
-};
-
-#endif
diff --git a/fs/netfs/fscache_internal.h b/fs/netfs/fscache_internal.h
deleted file mode 100644
index a09b948fc..000000000
--- a/fs/netfs/fscache_internal.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/* Internal definitions for FS-Cache
- *
- * Copyright (C) 2021 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- */
-
-#include "internal.h"
-
-#ifdef pr_fmt
-#undef pr_fmt
-#endif
-
-#define pr_fmt(fmt) "FS-Cache: " fmt
diff --git a/sound/soc/amd/include/acp_2_2_enum.h b/sound/soc/amd/include/acp_2_2_enum.h
deleted file mode 100644
index 26c7993ac..000000000
--- a/sound/soc/amd/include/acp_2_2_enum.h
+++ /dev/null
@@ -1,1052 +0,0 @@
-/* SPDX-License-Identifier: MIT */
-/*
- * ACP_2_2 Register documentation
- *
- * Copyright (C) 2014 Advanced Micro Devices, Inc.
- */
-
-#ifndef ACP_2_2_ENUM_H
-#define ACP_2_2_ENUM_H
-
-typedef enum DebugBlockId {
- DBG_BLOCK_ID_RESERVED = 0x0,
- DBG_BLOCK_ID_DBG = 0x1,
- DBG_BLOCK_ID_VMC = 0x2,
- DBG_BLOCK_ID_PDMA = 0x3,
- DBG_BLOCK_ID_CG = 0x4,
- DBG_BLOCK_ID_SRBM = 0x5,
- DBG_BLOCK_ID_GRBM = 0x6,
- DBG_BLOCK_ID_RLC = 0x7,
- DBG_BLOCK_ID_CSC = 0x8,
- DBG_BLOCK_ID_SEM = 0x9,
- DBG_BLOCK_ID_IH = 0xa,
- DBG_BLOCK_ID_SC = 0xb,
- DBG_BLOCK_ID_SQ = 0xc,
- DBG_BLOCK_ID_UVDU = 0xd,
- DBG_BLOCK_ID_SQA = 0xe,
- DBG_BLOCK_ID_SDMA0 = 0xf,
- DBG_BLOCK_ID_SDMA1 = 0x10,
- DBG_BLOCK_ID_SPIM = 0x11,
- DBG_BLOCK_ID_GDS = 0x12,
- DBG_BLOCK_ID_VC0 = 0x13,
- DBG_BLOCK_ID_VC1 = 0x14,
- DBG_BLOCK_ID_PA0 = 0x15,
- DBG_BLOCK_ID_PA1 = 0x16,
- DBG_BLOCK_ID_CP0 = 0x17,
- DBG_BLOCK_ID_CP1 = 0x18,
- DBG_BLOCK_ID_CP2 = 0x19,
- DBG_BLOCK_ID_XBR = 0x1a,
- DBG_BLOCK_ID_UVDM = 0x1b,
- DBG_BLOCK_ID_VGT0 = 0x1c,
- DBG_BLOCK_ID_VGT1 = 0x1d,
- DBG_BLOCK_ID_IA = 0x1e,
- DBG_BLOCK_ID_SXM0 = 0x1f,
- DBG_BLOCK_ID_SXM1 = 0x20,
- DBG_BLOCK_ID_SCT0 = 0x21,
- DBG_BLOCK_ID_SCT1 = 0x22,
- DBG_BLOCK_ID_SPM0 = 0x23,
- DBG_BLOCK_ID_SPM1 = 0x24,
- DBG_BLOCK_ID_UNUSED0 = 0x25,
- DBG_BLOCK_ID_UNUSED1 = 0x26,
- DBG_BLOCK_ID_TCAA = 0x27,
- DBG_BLOCK_ID_TCAB = 0x28,
- DBG_BLOCK_ID_TCCA = 0x29,
- DBG_BLOCK_ID_TCCB = 0x2a,
- DBG_BLOCK_ID_MCC0 = 0x2b,
- DBG_BLOCK_ID_MCC1 = 0x2c,
- DBG_BLOCK_ID_MCC2 = 0x2d,
- DBG_BLOCK_ID_MCC3 = 0x2e,
- DBG_BLOCK_ID_SXS0 = 0x2f,
- DBG_BLOCK_ID_SXS1 = 0x30,
- DBG_BLOCK_ID_SXS2 = 0x31,
- DBG_BLOCK_ID_SXS3 = 0x32,
- DBG_BLOCK_ID_SXS4 = 0x33,
- DBG_BLOCK_ID_SXS5 = 0x34,
- DBG_BLOCK_ID_SXS6 = 0x35,
- DBG_BLOCK_ID_SXS7 = 0x36,
- DBG_BLOCK_ID_SXS8 = 0x37,
- DBG_BLOCK_ID_SXS9 = 0x38,
- DBG_BLOCK_ID_BCI0 = 0x39,
- DBG_BLOCK_ID_BCI1 = 0x3a,
- DBG_BLOCK_ID_BCI2 = 0x3b,
- DBG_BLOCK_ID_BCI3 = 0x3c,
- DBG_BLOCK_ID_MCB = 0x3d,
- DBG_BLOCK_ID_UNUSED6 = 0x3e,
- DBG_BLOCK_ID_SQA00 = 0x3f,
- DBG_BLOCK_ID_SQA01 = 0x40,
- DBG_BLOCK_ID_SQA02 = 0x41,
- DBG_BLOCK_ID_SQA10 = 0x42,
- DBG_BLOCK_ID_SQA11 = 0x43,
- DBG_BLOCK_ID_SQA12 = 0x44,
- DBG_BLOCK_ID_UNUSED7 = 0x45,
- DBG_BLOCK_ID_UNUSED8 = 0x46,
- DBG_BLOCK_ID_SQB00 = 0x47,
- DBG_BLOCK_ID_SQB01 = 0x48,
- DBG_BLOCK_ID_SQB10 = 0x49,
- DBG_BLOCK_ID_SQB11 = 0x4a,
- DBG_BLOCK_ID_SQ00 = 0x4b,
- DBG_BLOCK_ID_SQ01 = 0x4c,
- DBG_BLOCK_ID_SQ10 = 0x4d,
- DBG_BLOCK_ID_SQ11 = 0x4e,
- DBG_BLOCK_ID_CB00 = 0x4f,
- DBG_BLOCK_ID_CB01 = 0x50,
- DBG_BLOCK_ID_CB02 = 0x51,
- DBG_BLOCK_ID_CB03 = 0x52,
- DBG_BLOCK_ID_CB04 = 0x53,
- DBG_BLOCK_ID_UNUSED9 = 0x54,
- DBG_BLOCK_ID_UNUSED10 = 0x55,
- DBG_BLOCK_ID_UNUSED11 = 0x56,
- DBG_BLOCK_ID_CB10 = 0x57,
- DBG_BLOCK_ID_CB11 = 0x58,
- DBG_BLOCK_ID_CB12 = 0x59,
- DBG_BLOCK_ID_CB13 = 0x5a,
- DBG_BLOCK_ID_CB14 = 0x5b,
- DBG_BLOCK_ID_UNUSED12 = 0x5c,
- DBG_BLOCK_ID_UNUSED13 = 0x5d,
- DBG_BLOCK_ID_UNUSED14 = 0x5e,
- DBG_BLOCK_ID_TCP0 = 0x5f,
- DBG_BLOCK_ID_TCP1 = 0x60,
- DBG_BLOCK_ID_TCP2 = 0x61,
- DBG_BLOCK_ID_TCP3 = 0x62,
- DBG_BLOCK_ID_TCP4 = 0x63,
- DBG_BLOCK_ID_TCP5 = 0x64,
- DBG_BLOCK_ID_TCP6 = 0x65,
- DBG_BLOCK_ID_TCP7 = 0x66,
- DBG_BLOCK_ID_TCP8 = 0x67,
- DBG_BLOCK_ID_TCP9 = 0x68,
- DBG_BLOCK_ID_TCP10 = 0x69,
- DBG_BLOCK_ID_TCP11 = 0x6a,
- DBG_BLOCK_ID_TCP12 = 0x6b,
- DBG_BLOCK_ID_TCP13 = 0x6c,
- DBG_BLOCK_ID_TCP14 = 0x6d,
- DBG_BLOCK_ID_TCP15 = 0x6e,
- DBG_BLOCK_ID_TCP16 = 0x6f,
- DBG_BLOCK_ID_TCP17 = 0x70,
- DBG_BLOCK_ID_TCP18 = 0x71,
- DBG_BLOCK_ID_TCP19 = 0x72,
- DBG_BLOCK_ID_TCP20 = 0x73,
- DBG_BLOCK_ID_TCP21 = 0x74,
- DBG_BLOCK_ID_TCP22 = 0x75,
- DBG_BLOCK_ID_TCP23 = 0x76,
- DBG_BLOCK_ID_TCP_RESERVED0 = 0x77,
- DBG_BLOCK_ID_TCP_RESERVED1 = 0x78,
- DBG_BLOCK_ID_TCP_RESERVED2 = 0x79,
- DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a,
- DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b,
- DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c,
- DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d,
- DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e,
- DBG_BLOCK_ID_DB00 = 0x7f,
- DBG_BLOCK_ID_DB01 = 0x80,
- DBG_BLOCK_ID_DB02 = 0x81,
- DBG_BLOCK_ID_DB03 = 0x82,
- DBG_BLOCK_ID_DB04 = 0x83,
- DBG_BLOCK_ID_UNUSED15 = 0x84,
- DBG_BLOCK_ID_UNUSED16 = 0x85,
- DBG_BLOCK_ID_UNUSED17 = 0x86,
- DBG_BLOCK_ID_DB10 = 0x87,
- DBG_BLOCK_ID_DB11 = 0x88,
- DBG_BLOCK_ID_DB12 = 0x89,
- DBG_BLOCK_ID_DB13 = 0x8a,
- DBG_BLOCK_ID_DB14 = 0x8b,
- DBG_BLOCK_ID_UNUSED18 = 0x8c,
- DBG_BLOCK_ID_UNUSED19 = 0x8d,
- DBG_BLOCK_ID_UNUSED20 = 0x8e,
- DBG_BLOCK_ID_TCC0 = 0x8f,
- DBG_BLOCK_ID_TCC1 = 0x90,
- DBG_BLOCK_ID_TCC2 = 0x91,
- DBG_BLOCK_ID_TCC3 = 0x92,
- DBG_BLOCK_ID_TCC4 = 0x93,
- DBG_BLOCK_ID_TCC5 = 0x94,
- DBG_BLOCK_ID_TCC6 = 0x95,
- DBG_BLOCK_ID_TCC7 = 0x96,
- DBG_BLOCK_ID_SPS00 = 0x97,
- DBG_BLOCK_ID_SPS01 = 0x98,
- DBG_BLOCK_ID_SPS02 = 0x99,
- DBG_BLOCK_ID_SPS10 = 0x9a,
- DBG_BLOCK_ID_SPS11 = 0x9b,
- DBG_BLOCK_ID_SPS12 = 0x9c,
- DBG_BLOCK_ID_UNUSED21 = 0x9d,
- DBG_BLOCK_ID_UNUSED22 = 0x9e,
- DBG_BLOCK_ID_TA00 = 0x9f,
- DBG_BLOCK_ID_TA01 = 0xa0,
- DBG_BLOCK_ID_TA02 = 0xa1,
- DBG_BLOCK_ID_TA03 = 0xa2,
- DBG_BLOCK_ID_TA04 = 0xa3,
- DBG_BLOCK_ID_TA05 = 0xa4,
- DBG_BLOCK_ID_TA06 = 0xa5,
- DBG_BLOCK_ID_TA07 = 0xa6,
- DBG_BLOCK_ID_TA08 = 0xa7,
- DBG_BLOCK_ID_TA09 = 0xa8,
- DBG_BLOCK_ID_TA0A = 0xa9,
- DBG_BLOCK_ID_TA0B = 0xaa,
- DBG_BLOCK_ID_UNUSED23 = 0xab,
- DBG_BLOCK_ID_UNUSED24 = 0xac,
- DBG_BLOCK_ID_UNUSED25 = 0xad,
- DBG_BLOCK_ID_UNUSED26 = 0xae,
- DBG_BLOCK_ID_TA10 = 0xaf,
- DBG_BLOCK_ID_TA11 = 0xb0,
- DBG_BLOCK_ID_TA12 = 0xb1,
- DBG_BLOCK_ID_TA13 = 0xb2,
- DBG_BLOCK_ID_TA14 = 0xb3,
- DBG_BLOCK_ID_TA15 = 0xb4,
- DBG_BLOCK_ID_TA16 = 0xb5,
- DBG_BLOCK_ID_TA17 = 0xb6,
- DBG_BLOCK_ID_TA18 = 0xb7,
- DBG_BLOCK_ID_TA19 = 0xb8,
- DBG_BLOCK_ID_TA1A = 0xb9,
- DBG_BLOCK_ID_TA1B = 0xba,
- DBG_BLOCK_ID_UNUSED27 = 0xbb,
- DBG_BLOCK_ID_UNUSED28 = 0xbc,
- DBG_BLOCK_ID_UNUSED29 = 0xbd,
- DBG_BLOCK_ID_UNUSED30 = 0xbe,
- DBG_BLOCK_ID_TD00 = 0xbf,
- DBG_BLOCK_ID_TD01 = 0xc0,
- DBG_BLOCK_ID_TD02 = 0xc1,
- DBG_BLOCK_ID_TD03 = 0xc2,
- DBG_BLOCK_ID_TD04 = 0xc3,
- DBG_BLOCK_ID_TD05 = 0xc4,
- DBG_BLOCK_ID_TD06 = 0xc5,
- DBG_BLOCK_ID_TD07 = 0xc6,
- DBG_BLOCK_ID_TD08 = 0xc7,
- DBG_BLOCK_ID_TD09 = 0xc8,
- DBG_BLOCK_ID_TD0A = 0xc9,
- DBG_BLOCK_ID_TD0B = 0xca,
- DBG_BLOCK_ID_UNUSED31 = 0xcb,
- DBG_BLOCK_ID_UNUSED32 = 0xcc,
- DBG_BLOCK_ID_UNUSED33 = 0xcd,
- DBG_BLOCK_ID_UNUSED34 = 0xce,
- DBG_BLOCK_ID_TD10 = 0xcf,
- DBG_BLOCK_ID_TD11 = 0xd0,
- DBG_BLOCK_ID_TD12 = 0xd1,
- DBG_BLOCK_ID_TD13 = 0xd2,
- DBG_BLOCK_ID_TD14 = 0xd3,
- DBG_BLOCK_ID_TD15 = 0xd4,
- DBG_BLOCK_ID_TD16 = 0xd5,
- DBG_BLOCK_ID_TD17 = 0xd6,
- DBG_BLOCK_ID_TD18 = 0xd7,
- DBG_BLOCK_ID_TD19 = 0xd8,
- DBG_BLOCK_ID_TD1A = 0xd9,
- DBG_BLOCK_ID_TD1B = 0xda,
- DBG_BLOCK_ID_UNUSED35 = 0xdb,
- DBG_BLOCK_ID_UNUSED36 = 0xdc,
- DBG_BLOCK_ID_UNUSED37 = 0xdd,
- DBG_BLOCK_ID_UNUSED38 = 0xde,
- DBG_BLOCK_ID_LDS00 = 0xdf,
- DBG_BLOCK_ID_LDS01 = 0xe0,
- DBG_BLOCK_ID_LDS02 = 0xe1,
- DBG_BLOCK_ID_LDS03 = 0xe2,
- DBG_BLOCK_ID_LDS04 = 0xe3,
- DBG_BLOCK_ID_LDS05 = 0xe4,
- DBG_BLOCK_ID_LDS06 = 0xe5,
- DBG_BLOCK_ID_LDS07 = 0xe6,
- DBG_BLOCK_ID_LDS08 = 0xe7,
- DBG_BLOCK_ID_LDS09 = 0xe8,
- DBG_BLOCK_ID_LDS0A = 0xe9,
- DBG_BLOCK_ID_LDS0B = 0xea,
- DBG_BLOCK_ID_UNUSED39 = 0xeb,
- DBG_BLOCK_ID_UNUSED40 = 0xec,
- DBG_BLOCK_ID_UNUSED41 = 0xed,
- DBG_BLOCK_ID_UNUSED42 = 0xee,
- DBG_BLOCK_ID_LDS10 = 0xef,
- DBG_BLOCK_ID_LDS11 = 0xf0,
- DBG_BLOCK_ID_LDS12 = 0xf1,
- DBG_BLOCK_ID_LDS13 = 0xf2,
- DBG_BLOCK_ID_LDS14 = 0xf3,
- DBG_BLOCK_ID_LDS15 = 0xf4,
- DBG_BLOCK_ID_LDS16 = 0xf5,
- DBG_BLOCK_ID_LDS17 = 0xf6,
- DBG_BLOCK_ID_LDS18 = 0xf7,
- DBG_BLOCK_ID_LDS19 = 0xf8,
- DBG_BLOCK_ID_LDS1A = 0xf9,
- DBG_BLOCK_ID_LDS1B = 0xfa,
- DBG_BLOCK_ID_UNUSED43 = 0xfb,
- DBG_BLOCK_ID_UNUSED44 = 0xfc,
- DBG_BLOCK_ID_UNUSED45 = 0xfd,
- DBG_BLOCK_ID_UNUSED46 = 0xfe,
-} DebugBlockId;
-typedef enum DebugBlockId_BY2 {
- DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
- DBG_BLOCK_ID_VMC_BY2 = 0x1,
- DBG_BLOCK_ID_UNUSED0_BY2 = 0x2,
- DBG_BLOCK_ID_GRBM_BY2 = 0x3,
- DBG_BLOCK_ID_CSC_BY2 = 0x4,
- DBG_BLOCK_ID_IH_BY2 = 0x5,
- DBG_BLOCK_ID_SQ_BY2 = 0x6,
- DBG_BLOCK_ID_UVD_BY2 = 0x7,
- DBG_BLOCK_ID_SDMA0_BY2 = 0x8,
- DBG_BLOCK_ID_SPIM_BY2 = 0x9,
- DBG_BLOCK_ID_VC0_BY2 = 0xa,
- DBG_BLOCK_ID_PA_BY2 = 0xb,
- DBG_BLOCK_ID_CP0_BY2 = 0xc,
- DBG_BLOCK_ID_CP2_BY2 = 0xd,
- DBG_BLOCK_ID_PC0_BY2 = 0xe,
- DBG_BLOCK_ID_BCI0_BY2 = 0xf,
- DBG_BLOCK_ID_SXM0_BY2 = 0x10,
- DBG_BLOCK_ID_SCT0_BY2 = 0x11,
- DBG_BLOCK_ID_SPM0_BY2 = 0x12,
- DBG_BLOCK_ID_BCI2_BY2 = 0x13,
- DBG_BLOCK_ID_TCA_BY2 = 0x14,
- DBG_BLOCK_ID_TCCA_BY2 = 0x15,
- DBG_BLOCK_ID_MCC_BY2 = 0x16,
- DBG_BLOCK_ID_MCC2_BY2 = 0x17,
- DBG_BLOCK_ID_MCD_BY2 = 0x18,
- DBG_BLOCK_ID_MCD2_BY2 = 0x19,
- DBG_BLOCK_ID_MCD4_BY2 = 0x1a,
- DBG_BLOCK_ID_MCB_BY2 = 0x1b,
- DBG_BLOCK_ID_SQA_BY2 = 0x1c,
- DBG_BLOCK_ID_SQA02_BY2 = 0x1d,
- DBG_BLOCK_ID_SQA11_BY2 = 0x1e,
- DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f,
- DBG_BLOCK_ID_SQB_BY2 = 0x20,
- DBG_BLOCK_ID_SQB10_BY2 = 0x21,
- DBG_BLOCK_ID_UNUSED10_BY2 = 0x22,
- DBG_BLOCK_ID_UNUSED12_BY2 = 0x23,
- DBG_BLOCK_ID_CB_BY2 = 0x24,
- DBG_BLOCK_ID_CB02_BY2 = 0x25,
- DBG_BLOCK_ID_CB10_BY2 = 0x26,
- DBG_BLOCK_ID_CB12_BY2 = 0x27,
- DBG_BLOCK_ID_SXS_BY2 = 0x28,
- DBG_BLOCK_ID_SXS2_BY2 = 0x29,
- DBG_BLOCK_ID_SXS4_BY2 = 0x2a,
- DBG_BLOCK_ID_SXS6_BY2 = 0x2b,
- DBG_BLOCK_ID_DB_BY2 = 0x2c,
- DBG_BLOCK_ID_DB02_BY2 = 0x2d,
- DBG_BLOCK_ID_DB10_BY2 = 0x2e,
- DBG_BLOCK_ID_DB12_BY2 = 0x2f,
- DBG_BLOCK_ID_TCP_BY2 = 0x30,
- DBG_BLOCK_ID_TCP2_BY2 = 0x31,
- DBG_BLOCK_ID_TCP4_BY2 = 0x32,
- DBG_BLOCK_ID_TCP6_BY2 = 0x33,
- DBG_BLOCK_ID_TCP8_BY2 = 0x34,
- DBG_BLOCK_ID_TCP10_BY2 = 0x35,
- DBG_BLOCK_ID_TCP12_BY2 = 0x36,
- DBG_BLOCK_ID_TCP14_BY2 = 0x37,
- DBG_BLOCK_ID_TCP16_BY2 = 0x38,
- DBG_BLOCK_ID_TCP18_BY2 = 0x39,
- DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
- DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
- DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
- DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
- DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
- DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
- DBG_BLOCK_ID_TCC_BY2 = 0x40,
- DBG_BLOCK_ID_TCC2_BY2 = 0x41,
- DBG_BLOCK_ID_TCC4_BY2 = 0x42,
- DBG_BLOCK_ID_TCC6_BY2 = 0x43,
- DBG_BLOCK_ID_SPS_BY2 = 0x44,
- DBG_BLOCK_ID_SPS02_BY2 = 0x45,
- DBG_BLOCK_ID_SPS11_BY2 = 0x46,
- DBG_BLOCK_ID_UNUSED14_BY2 = 0x47,
- DBG_BLOCK_ID_TA_BY2 = 0x48,
- DBG_BLOCK_ID_TA02_BY2 = 0x49,
- DBG_BLOCK_ID_TA04_BY2 = 0x4a,
- DBG_BLOCK_ID_TA06_BY2 = 0x4b,
- DBG_BLOCK_ID_TA08_BY2 = 0x4c,
- DBG_BLOCK_ID_TA0A_BY2 = 0x4d,
- DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e,
- DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f,
- DBG_BLOCK_ID_TA10_BY2 = 0x50,
- DBG_BLOCK_ID_TA12_BY2 = 0x51,
- DBG_BLOCK_ID_TA14_BY2 = 0x52,
- DBG_BLOCK_ID_TA16_BY2 = 0x53,
- DBG_BLOCK_ID_TA18_BY2 = 0x54,
- DBG_BLOCK_ID_TA1A_BY2 = 0x55,
- DBG_BLOCK_ID_UNUSED24_BY2 = 0x56,
- DBG_BLOCK_ID_UNUSED26_BY2 = 0x57,
- DBG_BLOCK_ID_TD_BY2 = 0x58,
- DBG_BLOCK_ID_TD02_BY2 = 0x59,
- DBG_BLOCK_ID_TD04_BY2 = 0x5a,
- DBG_BLOCK_ID_TD06_BY2 = 0x5b,
- DBG_BLOCK_ID_TD08_BY2 = 0x5c,
- DBG_BLOCK_ID_TD0A_BY2 = 0x5d,
- DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e,
- DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f,
- DBG_BLOCK_ID_TD10_BY2 = 0x60,
- DBG_BLOCK_ID_TD12_BY2 = 0x61,
- DBG_BLOCK_ID_TD14_BY2 = 0x62,
- DBG_BLOCK_ID_TD16_BY2 = 0x63,
- DBG_BLOCK_ID_TD18_BY2 = 0x64,
- DBG_BLOCK_ID_TD1A_BY2 = 0x65,
- DBG_BLOCK_ID_UNUSED32_BY2 = 0x66,
- DBG_BLOCK_ID_UNUSED34_BY2 = 0x67,
- DBG_BLOCK_ID_LDS_BY2 = 0x68,
- DBG_BLOCK_ID_LDS02_BY2 = 0x69,
- DBG_BLOCK_ID_LDS04_BY2 = 0x6a,
- DBG_BLOCK_ID_LDS06_BY2 = 0x6b,
- DBG_BLOCK_ID_LDS08_BY2 = 0x6c,
- DBG_BLOCK_ID_LDS0A_BY2 = 0x6d,
- DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e,
- DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f,
- DBG_BLOCK_ID_LDS10_BY2 = 0x70,
- DBG_BLOCK_ID_LDS12_BY2 = 0x71,
- DBG_BLOCK_ID_LDS14_BY2 = 0x72,
- DBG_BLOCK_ID_LDS16_BY2 = 0x73,
- DBG_BLOCK_ID_LDS18_BY2 = 0x74,
- DBG_BLOCK_ID_LDS1A_BY2 = 0x75,
- DBG_BLOCK_ID_UNUSED40_BY2 = 0x76,
- DBG_BLOCK_ID_UNUSED42_BY2 = 0x77,
-} DebugBlockId_BY2;
-typedef enum DebugBlockId_BY4 {
- DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
- DBG_BLOCK_ID_UNUSED0_BY4 = 0x1,
- DBG_BLOCK_ID_CSC_BY4 = 0x2,
- DBG_BLOCK_ID_SQ_BY4 = 0x3,
- DBG_BLOCK_ID_SDMA0_BY4 = 0x4,
- DBG_BLOCK_ID_VC0_BY4 = 0x5,
- DBG_BLOCK_ID_CP0_BY4 = 0x6,
- DBG_BLOCK_ID_UNUSED1_BY4 = 0x7,
- DBG_BLOCK_ID_SXM0_BY4 = 0x8,
- DBG_BLOCK_ID_SPM0_BY4 = 0x9,
- DBG_BLOCK_ID_TCAA_BY4 = 0xa,
- DBG_BLOCK_ID_MCC_BY4 = 0xb,
- DBG_BLOCK_ID_MCD_BY4 = 0xc,
- DBG_BLOCK_ID_MCD4_BY4 = 0xd,
- DBG_BLOCK_ID_SQA_BY4 = 0xe,
- DBG_BLOCK_ID_SQA11_BY4 = 0xf,
- DBG_BLOCK_ID_SQB_BY4 = 0x10,
- DBG_BLOCK_ID_UNUSED10_BY4 = 0x11,
- DBG_BLOCK_ID_CB_BY4 = 0x12,
- DBG_BLOCK_ID_CB10_BY4 = 0x13,
- DBG_BLOCK_ID_SXS_BY4 = 0x14,
- DBG_BLOCK_ID_SXS4_BY4 = 0x15,
- DBG_BLOCK_ID_DB_BY4 = 0x16,
- DBG_BLOCK_ID_DB10_BY4 = 0x17,
- DBG_BLOCK_ID_TCP_BY4 = 0x18,
- DBG_BLOCK_ID_TCP4_BY4 = 0x19,
- DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
- DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
- DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
- DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
- DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
- DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
- DBG_BLOCK_ID_TCC_BY4 = 0x20,
- DBG_BLOCK_ID_TCC4_BY4 = 0x21,
- DBG_BLOCK_ID_SPS_BY4 = 0x22,
- DBG_BLOCK_ID_SPS11_BY4 = 0x23,
- DBG_BLOCK_ID_TA_BY4 = 0x24,
- DBG_BLOCK_ID_TA04_BY4 = 0x25,
- DBG_BLOCK_ID_TA08_BY4 = 0x26,
- DBG_BLOCK_ID_UNUSED20_BY4 = 0x27,
- DBG_BLOCK_ID_TA10_BY4 = 0x28,
- DBG_BLOCK_ID_TA14_BY4 = 0x29,
- DBG_BLOCK_ID_TA18_BY4 = 0x2a,
- DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b,
- DBG_BLOCK_ID_TD_BY4 = 0x2c,
- DBG_BLOCK_ID_TD04_BY4 = 0x2d,
- DBG_BLOCK_ID_TD08_BY4 = 0x2e,
- DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f,
- DBG_BLOCK_ID_TD10_BY4 = 0x30,
- DBG_BLOCK_ID_TD14_BY4 = 0x31,
- DBG_BLOCK_ID_TD18_BY4 = 0x32,
- DBG_BLOCK_ID_UNUSED32_BY4 = 0x33,
- DBG_BLOCK_ID_LDS_BY4 = 0x34,
- DBG_BLOCK_ID_LDS04_BY4 = 0x35,
- DBG_BLOCK_ID_LDS08_BY4 = 0x36,
- DBG_BLOCK_ID_UNUSED36_BY4 = 0x37,
- DBG_BLOCK_ID_LDS10_BY4 = 0x38,
- DBG_BLOCK_ID_LDS14_BY4 = 0x39,
- DBG_BLOCK_ID_LDS18_BY4 = 0x3a,
- DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b,
-} DebugBlockId_BY4;
-typedef enum DebugBlockId_BY8 {
- DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
- DBG_BLOCK_ID_CSC_BY8 = 0x1,
- DBG_BLOCK_ID_SDMA0_BY8 = 0x2,
- DBG_BLOCK_ID_CP0_BY8 = 0x3,
- DBG_BLOCK_ID_SXM0_BY8 = 0x4,
- DBG_BLOCK_ID_TCA_BY8 = 0x5,
- DBG_BLOCK_ID_MCD_BY8 = 0x6,
- DBG_BLOCK_ID_SQA_BY8 = 0x7,
- DBG_BLOCK_ID_SQB_BY8 = 0x8,
- DBG_BLOCK_ID_CB_BY8 = 0x9,
- DBG_BLOCK_ID_SXS_BY8 = 0xa,
- DBG_BLOCK_ID_DB_BY8 = 0xb,
- DBG_BLOCK_ID_TCP_BY8 = 0xc,
- DBG_BLOCK_ID_TCP8_BY8 = 0xd,
- DBG_BLOCK_ID_TCP16_BY8 = 0xe,
- DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
- DBG_BLOCK_ID_TCC_BY8 = 0x10,
- DBG_BLOCK_ID_SPS_BY8 = 0x11,
- DBG_BLOCK_ID_TA_BY8 = 0x12,
- DBG_BLOCK_ID_TA08_BY8 = 0x13,
- DBG_BLOCK_ID_TA10_BY8 = 0x14,
- DBG_BLOCK_ID_TA18_BY8 = 0x15,
- DBG_BLOCK_ID_TD_BY8 = 0x16,
- DBG_BLOCK_ID_TD08_BY8 = 0x17,
- DBG_BLOCK_ID_TD10_BY8 = 0x18,
- DBG_BLOCK_ID_TD18_BY8 = 0x19,
- DBG_BLOCK_ID_LDS_BY8 = 0x1a,
- DBG_BLOCK_ID_LDS08_BY8 = 0x1b,
- DBG_BLOCK_ID_LDS10_BY8 = 0x1c,
- DBG_BLOCK_ID_LDS18_BY8 = 0x1d,
-} DebugBlockId_BY8;
-typedef enum DebugBlockId_BY16 {
- DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
- DBG_BLOCK_ID_SDMA0_BY16 = 0x1,
- DBG_BLOCK_ID_SXM_BY16 = 0x2,
- DBG_BLOCK_ID_MCD_BY16 = 0x3,
- DBG_BLOCK_ID_SQB_BY16 = 0x4,
- DBG_BLOCK_ID_SXS_BY16 = 0x5,
- DBG_BLOCK_ID_TCP_BY16 = 0x6,
- DBG_BLOCK_ID_TCP16_BY16 = 0x7,
- DBG_BLOCK_ID_TCC_BY16 = 0x8,
- DBG_BLOCK_ID_TA_BY16 = 0x9,
- DBG_BLOCK_ID_TA10_BY16 = 0xa,
- DBG_BLOCK_ID_TD_BY16 = 0xb,
- DBG_BLOCK_ID_TD10_BY16 = 0xc,
- DBG_BLOCK_ID_LDS_BY16 = 0xd,
- DBG_BLOCK_ID_LDS10_BY16 = 0xe,
-} DebugBlockId_BY16;
-typedef enum SurfaceEndian {
- ENDIAN_NONE = 0x0,
- ENDIAN_8IN16 = 0x1,
- ENDIAN_8IN32 = 0x2,
- ENDIAN_8IN64 = 0x3,
-} SurfaceEndian;
-typedef enum ArrayMode {
- ARRAY_LINEAR_GENERAL = 0x0,
- ARRAY_LINEAR_ALIGNED = 0x1,
- ARRAY_1D_TILED_THIN1 = 0x2,
- ARRAY_1D_TILED_THICK = 0x3,
- ARRAY_2D_TILED_THIN1 = 0x4,
- ARRAY_PRT_TILED_THIN1 = 0x5,
- ARRAY_PRT_2D_TILED_THIN1 = 0x6,
- ARRAY_2D_TILED_THICK = 0x7,
- ARRAY_2D_TILED_XTHICK = 0x8,
- ARRAY_PRT_TILED_THICK = 0x9,
- ARRAY_PRT_2D_TILED_THICK = 0xa,
- ARRAY_PRT_3D_TILED_THIN1 = 0xb,
- ARRAY_3D_TILED_THIN1 = 0xc,
- ARRAY_3D_TILED_THICK = 0xd,
- ARRAY_3D_TILED_XTHICK = 0xe,
- ARRAY_PRT_3D_TILED_THICK = 0xf,
-} ArrayMode;
-typedef enum PipeTiling {
- CONFIG_1_PIPE = 0x0,
- CONFIG_2_PIPE = 0x1,
- CONFIG_4_PIPE = 0x2,
- CONFIG_8_PIPE = 0x3,
-} PipeTiling;
-typedef enum BankTiling {
- CONFIG_4_BANK = 0x0,
- CONFIG_8_BANK = 0x1,
-} BankTiling;
-typedef enum GroupInterleave {
- CONFIG_256B_GROUP = 0x0,
- CONFIG_512B_GROUP = 0x1,
-} GroupInterleave;
-typedef enum RowTiling {
- CONFIG_1KB_ROW = 0x0,
- CONFIG_2KB_ROW = 0x1,
- CONFIG_4KB_ROW = 0x2,
- CONFIG_8KB_ROW = 0x3,
- CONFIG_1KB_ROW_OPT = 0x4,
- CONFIG_2KB_ROW_OPT = 0x5,
- CONFIG_4KB_ROW_OPT = 0x6,
- CONFIG_8KB_ROW_OPT = 0x7,
-} RowTiling;
-typedef enum BankSwapBytes {
- CONFIG_128B_SWAPS = 0x0,
- CONFIG_256B_SWAPS = 0x1,
- CONFIG_512B_SWAPS = 0x2,
- CONFIG_1KB_SWAPS = 0x3,
-} BankSwapBytes;
-typedef enum SampleSplitBytes {
- CONFIG_1KB_SPLIT = 0x0,
- CONFIG_2KB_SPLIT = 0x1,
- CONFIG_4KB_SPLIT = 0x2,
- CONFIG_8KB_SPLIT = 0x3,
-} SampleSplitBytes;
-typedef enum NumPipes {
- ADDR_CONFIG_1_PIPE = 0x0,
- ADDR_CONFIG_2_PIPE = 0x1,
- ADDR_CONFIG_4_PIPE = 0x2,
- ADDR_CONFIG_8_PIPE = 0x3,
-} NumPipes;
-typedef enum PipeInterleaveSize {
- ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
- ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
-} PipeInterleaveSize;
-typedef enum BankInterleaveSize {
- ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
- ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
- ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
- ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
-} BankInterleaveSize;
-typedef enum NumShaderEngines {
- ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
- ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
-} NumShaderEngines;
-typedef enum ShaderEngineTileSize {
- ADDR_CONFIG_SE_TILE_16 = 0x0,
- ADDR_CONFIG_SE_TILE_32 = 0x1,
-} ShaderEngineTileSize;
-typedef enum NumGPUs {
- ADDR_CONFIG_1_GPU = 0x0,
- ADDR_CONFIG_2_GPU = 0x1,
- ADDR_CONFIG_4_GPU = 0x2,
-} NumGPUs;
-typedef enum MultiGPUTileSize {
- ADDR_CONFIG_GPU_TILE_16 = 0x0,
- ADDR_CONFIG_GPU_TILE_32 = 0x1,
- ADDR_CONFIG_GPU_TILE_64 = 0x2,
- ADDR_CONFIG_GPU_TILE_128 = 0x3,
-} MultiGPUTileSize;
-typedef enum RowSize {
- ADDR_CONFIG_1KB_ROW = 0x0,
- ADDR_CONFIG_2KB_ROW = 0x1,
- ADDR_CONFIG_4KB_ROW = 0x2,
-} RowSize;
-typedef enum NumLowerPipes {
- ADDR_CONFIG_1_LOWER_PIPES = 0x0,
- ADDR_CONFIG_2_LOWER_PIPES = 0x1,
-} NumLowerPipes;
-typedef enum ColorTransform {
- DCC_CT_AUTO = 0x0,
- DCC_CT_NONE = 0x1,
- ABGR_TO_A_BG_G_RB = 0x2,
- BGRA_TO_BG_G_RB_A = 0x3,
-} ColorTransform;
-typedef enum CompareRef {
- REF_NEVER = 0x0,
- REF_LESS = 0x1,
- REF_EQUAL = 0x2,
- REF_LEQUAL = 0x3,
- REF_GREATER = 0x4,
- REF_NOTEQUAL = 0x5,
- REF_GEQUAL = 0x6,
- REF_ALWAYS = 0x7,
-} CompareRef;
-typedef enum ReadSize {
- READ_256_BITS = 0x0,
- READ_512_BITS = 0x1,
-} ReadSize;
-typedef enum DepthFormat {
- DEPTH_INVALID = 0x0,
- DEPTH_16 = 0x1,
- DEPTH_X8_24 = 0x2,
- DEPTH_8_24 = 0x3,
- DEPTH_X8_24_FLOAT = 0x4,
- DEPTH_8_24_FLOAT = 0x5,
- DEPTH_32_FLOAT = 0x6,
- DEPTH_X24_8_32_FLOAT = 0x7,
-} DepthFormat;
-typedef enum ZFormat {
- Z_INVALID = 0x0,
- Z_16 = 0x1,
- Z_24 = 0x2,
- Z_32_FLOAT = 0x3,
-} ZFormat;
-typedef enum StencilFormat {
- STENCIL_INVALID = 0x0,
- STENCIL_8 = 0x1,
-} StencilFormat;
-typedef enum CmaskMode {
- CMASK_CLEAR_NONE = 0x0,
- CMASK_CLEAR_ONE = 0x1,
- CMASK_CLEAR_ALL = 0x2,
- CMASK_ANY_EXPANDED = 0x3,
- CMASK_ALPHA0_FRAG1 = 0x4,
- CMASK_ALPHA0_FRAG2 = 0x5,
- CMASK_ALPHA0_FRAG4 = 0x6,
- CMASK_ALPHA0_FRAGS = 0x7,
- CMASK_ALPHA1_FRAG1 = 0x8,
- CMASK_ALPHA1_FRAG2 = 0x9,
- CMASK_ALPHA1_FRAG4 = 0xa,
- CMASK_ALPHA1_FRAGS = 0xb,
- CMASK_ALPHAX_FRAG1 = 0xc,
- CMASK_ALPHAX_FRAG2 = 0xd,
- CMASK_ALPHAX_FRAG4 = 0xe,
- CMASK_ALPHAX_FRAGS = 0xf,
-} CmaskMode;
-typedef enum QuadExportFormat {
- EXPORT_UNUSED = 0x0,
- EXPORT_32_R = 0x1,
- EXPORT_32_GR = 0x2,
- EXPORT_32_AR = 0x3,
- EXPORT_FP16_ABGR = 0x4,
- EXPORT_UNSIGNED16_ABGR = 0x5,
- EXPORT_SIGNED16_ABGR = 0x6,
- EXPORT_32_ABGR = 0x7,
-} QuadExportFormat;
-typedef enum QuadExportFormatOld {
- EXPORT_4P_32BPC_ABGR = 0x0,
- EXPORT_4P_16BPC_ABGR = 0x1,
- EXPORT_4P_32BPC_GR = 0x2,
- EXPORT_4P_32BPC_AR = 0x3,
- EXPORT_2P_32BPC_ABGR = 0x4,
- EXPORT_8P_32BPC_R = 0x5,
-} QuadExportFormatOld;
-typedef enum ColorFormat {
- COLOR_INVALID = 0x0,
- COLOR_8 = 0x1,
- COLOR_16 = 0x2,
- COLOR_8_8 = 0x3,
- COLOR_32 = 0x4,
- COLOR_16_16 = 0x5,
- COLOR_10_11_11 = 0x6,
- COLOR_11_11_10 = 0x7,
- COLOR_10_10_10_2 = 0x8,
- COLOR_2_10_10_10 = 0x9,
- COLOR_8_8_8_8 = 0xa,
- COLOR_32_32 = 0xb,
- COLOR_16_16_16_16 = 0xc,
- COLOR_RESERVED_13 = 0xd,
- COLOR_32_32_32_32 = 0xe,
- COLOR_RESERVED_15 = 0xf,
- COLOR_5_6_5 = 0x10,
- COLOR_1_5_5_5 = 0x11,
- COLOR_5_5_5_1 = 0x12,
- COLOR_4_4_4_4 = 0x13,
- COLOR_8_24 = 0x14,
- COLOR_24_8 = 0x15,
- COLOR_X24_8_32_FLOAT = 0x16,
- COLOR_RESERVED_23 = 0x17,
-} ColorFormat;
-typedef enum SurfaceFormat {
- FMT_INVALID = 0x0,
- FMT_8 = 0x1,
- FMT_16 = 0x2,
- FMT_8_8 = 0x3,
- FMT_32 = 0x4,
- FMT_16_16 = 0x5,
- FMT_10_11_11 = 0x6,
- FMT_11_11_10 = 0x7,
- FMT_10_10_10_2 = 0x8,
- FMT_2_10_10_10 = 0x9,
- FMT_8_8_8_8 = 0xa,
- FMT_32_32 = 0xb,
- FMT_16_16_16_16 = 0xc,
- FMT_32_32_32 = 0xd,
- FMT_32_32_32_32 = 0xe,
- FMT_RESERVED_4 = 0xf,
- FMT_5_6_5 = 0x10,
- FMT_1_5_5_5 = 0x11,
- FMT_5_5_5_1 = 0x12,
- FMT_4_4_4_4 = 0x13,
- FMT_8_24 = 0x14,
- FMT_24_8 = 0x15,
- FMT_X24_8_32_FLOAT = 0x16,
- FMT_RESERVED_33 = 0x17,
- FMT_11_11_10_FLOAT = 0x18,
- FMT_16_FLOAT = 0x19,
- FMT_32_FLOAT = 0x1a,
- FMT_16_16_FLOAT = 0x1b,
- FMT_8_24_FLOAT = 0x1c,
- FMT_24_8_FLOAT = 0x1d,
- FMT_32_32_FLOAT = 0x1e,
- FMT_10_11_11_FLOAT = 0x1f,
- FMT_16_16_16_16_FLOAT = 0x20,
- FMT_3_3_2 = 0x21,
- FMT_6_5_5 = 0x22,
- FMT_32_32_32_32_FLOAT = 0x23,
- FMT_RESERVED_36 = 0x24,
- FMT_1 = 0x25,
- FMT_1_REVERSED = 0x26,
- FMT_GB_GR = 0x27,
- FMT_BG_RG = 0x28,
- FMT_32_AS_8 = 0x29,
- FMT_32_AS_8_8 = 0x2a,
- FMT_5_9_9_9_SHAREDEXP = 0x2b,
- FMT_8_8_8 = 0x2c,
- FMT_16_16_16 = 0x2d,
- FMT_16_16_16_FLOAT = 0x2e,
- FMT_4_4 = 0x2f,
- FMT_32_32_32_FLOAT = 0x30,
- FMT_BC1 = 0x31,
- FMT_BC2 = 0x32,
- FMT_BC3 = 0x33,
- FMT_BC4 = 0x34,
- FMT_BC5 = 0x35,
- FMT_BC6 = 0x36,
- FMT_BC7 = 0x37,
- FMT_32_AS_32_32_32_32 = 0x38,
- FMT_APC3 = 0x39,
- FMT_APC4 = 0x3a,
- FMT_APC5 = 0x3b,
- FMT_APC6 = 0x3c,
- FMT_APC7 = 0x3d,
- FMT_CTX1 = 0x3e,
- FMT_RESERVED_63 = 0x3f,
-} SurfaceFormat;
-typedef enum BUF_DATA_FORMAT {
- BUF_DATA_FORMAT_INVALID = 0x0,
- BUF_DATA_FORMAT_8 = 0x1,
- BUF_DATA_FORMAT_16 = 0x2,
- BUF_DATA_FORMAT_8_8 = 0x3,
- BUF_DATA_FORMAT_32 = 0x4,
- BUF_DATA_FORMAT_16_16 = 0x5,
- BUF_DATA_FORMAT_10_11_11 = 0x6,
- BUF_DATA_FORMAT_11_11_10 = 0x7,
- BUF_DATA_FORMAT_10_10_10_2 = 0x8,
- BUF_DATA_FORMAT_2_10_10_10 = 0x9,
- BUF_DATA_FORMAT_8_8_8_8 = 0xa,
- BUF_DATA_FORMAT_32_32 = 0xb,
- BUF_DATA_FORMAT_16_16_16_16 = 0xc,
- BUF_DATA_FORMAT_32_32_32 = 0xd,
- BUF_DATA_FORMAT_32_32_32_32 = 0xe,
- BUF_DATA_FORMAT_RESERVED_15 = 0xf,
-} BUF_DATA_FORMAT;
-typedef enum IMG_DATA_FORMAT {
- IMG_DATA_FORMAT_INVALID = 0x0,
- IMG_DATA_FORMAT_8 = 0x1,
- IMG_DATA_FORMAT_16 = 0x2,
- IMG_DATA_FORMAT_8_8 = 0x3,
- IMG_DATA_FORMAT_32 = 0x4,
- IMG_DATA_FORMAT_16_16 = 0x5,
- IMG_DATA_FORMAT_10_11_11 = 0x6,
- IMG_DATA_FORMAT_11_11_10 = 0x7,
- IMG_DATA_FORMAT_10_10_10_2 = 0x8,
- IMG_DATA_FORMAT_2_10_10_10 = 0x9,
- IMG_DATA_FORMAT_8_8_8_8 = 0xa,
- IMG_DATA_FORMAT_32_32 = 0xb,
- IMG_DATA_FORMAT_16_16_16_16 = 0xc,
- IMG_DATA_FORMAT_32_32_32 = 0xd,
- IMG_DATA_FORMAT_32_32_32_32 = 0xe,
- IMG_DATA_FORMAT_RESERVED_15 = 0xf,
- IMG_DATA_FORMAT_5_6_5 = 0x10,
- IMG_DATA_FORMAT_1_5_5_5 = 0x11,
- IMG_DATA_FORMAT_5_5_5_1 = 0x12,
- IMG_DATA_FORMAT_4_4_4_4 = 0x13,
- IMG_DATA_FORMAT_8_24 = 0x14,
- IMG_DATA_FORMAT_24_8 = 0x15,
- IMG_DATA_FORMAT_X24_8_32 = 0x16,
- IMG_DATA_FORMAT_RESERVED_23 = 0x17,
- IMG_DATA_FORMAT_RESERVED_24 = 0x18,
- IMG_DATA_FORMAT_RESERVED_25 = 0x19,
- IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
- IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
- IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
- IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
- IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
- IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
- IMG_DATA_FORMAT_GB_GR = 0x20,
- IMG_DATA_FORMAT_BG_RG = 0x21,
- IMG_DATA_FORMAT_5_9_9_9 = 0x22,
- IMG_DATA_FORMAT_BC1 = 0x23,
- IMG_DATA_FORMAT_BC2 = 0x24,
- IMG_DATA_FORMAT_BC3 = 0x25,
- IMG_DATA_FORMAT_BC4 = 0x26,
- IMG_DATA_FORMAT_BC5 = 0x27,
- IMG_DATA_FORMAT_BC6 = 0x28,
- IMG_DATA_FORMAT_BC7 = 0x29,
- IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
- IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
- IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
- IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
- IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
- IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
- IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
- IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
- IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
- IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
- IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
- IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
- IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
- IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
- IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
- IMG_DATA_FORMAT_4_4 = 0x39,
- IMG_DATA_FORMAT_6_5_5 = 0x3a,
- IMG_DATA_FORMAT_1 = 0x3b,
- IMG_DATA_FORMAT_1_REVERSED = 0x3c,
- IMG_DATA_FORMAT_32_AS_8 = 0x3d,
- IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
- IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
-} IMG_DATA_FORMAT;
-typedef enum BUF_NUM_FORMAT {
- BUF_NUM_FORMAT_UNORM = 0x0,
- BUF_NUM_FORMAT_SNORM = 0x1,
- BUF_NUM_FORMAT_USCALED = 0x2,
- BUF_NUM_FORMAT_SSCALED = 0x3,
- BUF_NUM_FORMAT_UINT = 0x4,
- BUF_NUM_FORMAT_SINT = 0x5,
- BUF_NUM_FORMAT_RESERVED_6 = 0x6,
- BUF_NUM_FORMAT_FLOAT = 0x7,
-} BUF_NUM_FORMAT;
-typedef enum IMG_NUM_FORMAT {
- IMG_NUM_FORMAT_UNORM = 0x0,
- IMG_NUM_FORMAT_SNORM = 0x1,
- IMG_NUM_FORMAT_USCALED = 0x2,
- IMG_NUM_FORMAT_SSCALED = 0x3,
- IMG_NUM_FORMAT_UINT = 0x4,
- IMG_NUM_FORMAT_SINT = 0x5,
- IMG_NUM_FORMAT_RESERVED_6 = 0x6,
- IMG_NUM_FORMAT_FLOAT = 0x7,
- IMG_NUM_FORMAT_RESERVED_8 = 0x8,
- IMG_NUM_FORMAT_SRGB = 0x9,
- IMG_NUM_FORMAT_RESERVED_10 = 0xa,
- IMG_NUM_FORMAT_RESERVED_11 = 0xb,
- IMG_NUM_FORMAT_RESERVED_12 = 0xc,
- IMG_NUM_FORMAT_RESERVED_13 = 0xd,
- IMG_NUM_FORMAT_RESERVED_14 = 0xe,
- IMG_NUM_FORMAT_RESERVED_15 = 0xf,
-} IMG_NUM_FORMAT;
-typedef enum TileType {
- ARRAY_COLOR_TILE = 0x0,
- ARRAY_DEPTH_TILE = 0x1,
-} TileType;
-typedef enum NonDispTilingOrder {
- ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
- ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
-} NonDispTilingOrder;
-typedef enum MicroTileMode {
- ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
- ADDR_SURF_THIN_MICRO_TILING = 0x1,
- ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
- ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
- ADDR_SURF_THICK_MICRO_TILING = 0x4,
-} MicroTileMode;
-typedef enum TileSplit {
- ADDR_SURF_TILE_SPLIT_64B = 0x0,
- ADDR_SURF_TILE_SPLIT_128B = 0x1,
- ADDR_SURF_TILE_SPLIT_256B = 0x2,
- ADDR_SURF_TILE_SPLIT_512B = 0x3,
- ADDR_SURF_TILE_SPLIT_1KB = 0x4,
- ADDR_SURF_TILE_SPLIT_2KB = 0x5,
- ADDR_SURF_TILE_SPLIT_4KB = 0x6,
-} TileSplit;
-typedef enum SampleSplit {
- ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
- ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
- ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
- ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
-} SampleSplit;
-typedef enum PipeConfig {
- ADDR_SURF_P2 = 0x0,
- ADDR_SURF_P2_RESERVED0 = 0x1,
- ADDR_SURF_P2_RESERVED1 = 0x2,
- ADDR_SURF_P2_RESERVED2 = 0x3,
- ADDR_SURF_P4_8x16 = 0x4,
- ADDR_SURF_P4_16x16 = 0x5,
- ADDR_SURF_P4_16x32 = 0x6,
- ADDR_SURF_P4_32x32 = 0x7,
- ADDR_SURF_P8_16x16_8x16 = 0x8,
- ADDR_SURF_P8_16x32_8x16 = 0x9,
- ADDR_SURF_P8_32x32_8x16 = 0xa,
- ADDR_SURF_P8_16x32_16x16 = 0xb,
- ADDR_SURF_P8_32x32_16x16 = 0xc,
- ADDR_SURF_P8_32x32_16x32 = 0xd,
- ADDR_SURF_P8_32x64_32x32 = 0xe,
- ADDR_SURF_P8_RESERVED0 = 0xf,
- ADDR_SURF_P16_32x32_8x16 = 0x10,
- ADDR_SURF_P16_32x32_16x16 = 0x11,
-} PipeConfig;
-typedef enum NumBanks {
- ADDR_SURF_2_BANK = 0x0,
- ADDR_SURF_4_BANK = 0x1,
- ADDR_SURF_8_BANK = 0x2,
- ADDR_SURF_16_BANK = 0x3,
-} NumBanks;
-typedef enum BankWidth {
- ADDR_SURF_BANK_WIDTH_1 = 0x0,
- ADDR_SURF_BANK_WIDTH_2 = 0x1,
- ADDR_SURF_BANK_WIDTH_4 = 0x2,
- ADDR_SURF_BANK_WIDTH_8 = 0x3,
-} BankWidth;
-typedef enum BankHeight {
- ADDR_SURF_BANK_HEIGHT_1 = 0x0,
- ADDR_SURF_BANK_HEIGHT_2 = 0x1,
- ADDR_SURF_BANK_HEIGHT_4 = 0x2,
- ADDR_SURF_BANK_HEIGHT_8 = 0x3,
-} BankHeight;
-typedef enum BankWidthHeight {
- ADDR_SURF_BANK_WH_1 = 0x0,
- ADDR_SURF_BANK_WH_2 = 0x1,
- ADDR_SURF_BANK_WH_4 = 0x2,
- ADDR_SURF_BANK_WH_8 = 0x3,
-} BankWidthHeight;
-typedef enum MacroTileAspect {
- ADDR_SURF_MACRO_ASPECT_1 = 0x0,
- ADDR_SURF_MACRO_ASPECT_2 = 0x1,
- ADDR_SURF_MACRO_ASPECT_4 = 0x2,
- ADDR_SURF_MACRO_ASPECT_8 = 0x3,
-} MacroTileAspect;
-typedef enum GATCL1RequestType {
- GATCL1_TYPE_NORMAL = 0x0,
- GATCL1_TYPE_SHOOTDOWN = 0x1,
- GATCL1_TYPE_BYPASS = 0x2,
-} GATCL1RequestType;
-typedef enum TCC_CACHE_POLICIES {
- TCC_CACHE_POLICY_LRU = 0x0,
- TCC_CACHE_POLICY_STREAM = 0x1,
-} TCC_CACHE_POLICIES;
-typedef enum MTYPE {
- MTYPE_NC_NV = 0x0,
- MTYPE_NC = 0x1,
- MTYPE_CC = 0x2,
- MTYPE_UC = 0x3,
-} MTYPE;
-typedef enum PERFMON_COUNTER_MODE {
- PERFMON_COUNTER_MODE_ACCUM = 0x0,
- PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
- PERFMON_COUNTER_MODE_MAX = 0x2,
- PERFMON_COUNTER_MODE_DIRTY = 0x3,
- PERFMON_COUNTER_MODE_SAMPLE = 0x4,
- PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
- PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
- PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
- PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
- PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
- PERFMON_COUNTER_MODE_RESERVED = 0xf,
-} PERFMON_COUNTER_MODE;
-typedef enum PERFMON_SPM_MODE {
- PERFMON_SPM_MODE_OFF = 0x0,
- PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
- PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
- PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
- PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
- PERFMON_SPM_MODE_RESERVED_5 = 0x5,
- PERFMON_SPM_MODE_RESERVED_6 = 0x6,
- PERFMON_SPM_MODE_RESERVED_7 = 0x7,
- PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
- PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
- PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
-} PERFMON_SPM_MODE;
-typedef enum SurfaceTiling {
- ARRAY_LINEAR = 0x0,
- ARRAY_TILED = 0x1,
-} SurfaceTiling;
-typedef enum SurfaceArray {
- ARRAY_1D = 0x0,
- ARRAY_2D = 0x1,
- ARRAY_3D = 0x2,
- ARRAY_3D_SLICE = 0x3,
-} SurfaceArray;
-typedef enum ColorArray {
- ARRAY_2D_ALT_COLOR = 0x0,
- ARRAY_2D_COLOR = 0x1,
- ARRAY_3D_SLICE_COLOR = 0x3,
-} ColorArray;
-typedef enum DepthArray {
- ARRAY_2D_ALT_DEPTH = 0x0,
- ARRAY_2D_DEPTH = 0x1,
-} DepthArray;
-typedef enum ENUM_NUM_SIMD_PER_CU {
- NUM_SIMD_PER_CU = 0x4,
-} ENUM_NUM_SIMD_PER_CU;
-typedef enum MEM_PWR_FORCE_CTRL {
- NO_FORCE_REQUEST = 0x0,
- FORCE_LIGHT_SLEEP_REQUEST = 0x1,
- FORCE_DEEP_SLEEP_REQUEST = 0x2,
- FORCE_SHUT_DOWN_REQUEST = 0x3,
-} MEM_PWR_FORCE_CTRL;
-typedef enum MEM_PWR_FORCE_CTRL2 {
- NO_FORCE_REQ = 0x0,
- FORCE_LIGHT_SLEEP_REQ = 0x1,
-} MEM_PWR_FORCE_CTRL2;
-typedef enum MEM_PWR_DIS_CTRL {
- ENABLE_MEM_PWR_CTRL = 0x0,
- DISABLE_MEM_PWR_CTRL = 0x1,
-} MEM_PWR_DIS_CTRL;
-typedef enum MEM_PWR_SEL_CTRL {
- DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
- DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
- DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
-} MEM_PWR_SEL_CTRL;
-typedef enum MEM_PWR_SEL_CTRL2 {
- DYNAMIC_DEEP_SLEEP_EN = 0x0,
- DYNAMIC_LIGHT_SLEEP_EN = 0x1,
-} MEM_PWR_SEL_CTRL2;
-
-#endif /* ACP_2_2_ENUM_H */
--
2.43.0
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