From mboxrd@z Thu Jan  1 00:00:00 1970
From: Mike Frysinger <vapier.adi@gmail.com>
Subject: Re: [PATCH v3] ad7877: keep dma rx buffers in seperate cache lines
Date: Tue, 11 May 2010 16:54:41 -0400
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To: Christoph Lameter <cl@linux.com>
Cc: Pekka Enberg <penberg@cs.helsinki.fi>, Matt Mackall <mpm@selenic.com>, Dmitry Torokhov <dmitry.torokhov@gmail.com>, Andrew Morton <akpm@linux-foundation.org>, Oskar Schirmer <os@emlix.com>, Michael Hennerich <Michael.Hennerich@analog.com>, linux-input@vger.kernel.org, linux-kernel@vger.kernel.org, =?UTF-8?Q?Daniel_Gl=C3=B6ckner?= <dg@emlix.com>, Oliver Schneidewind <osw@emlix.com>, Johannes Weiner <jw@emlix.com>, Nick Piggin <npiggin@suse.de>, David Rientjes <rientjes@google.com>, David Brownell <dbrownell@users.sourceforge.net>, Grant Likely <grant.likely@secretlab.ca>

On Tue, May 11, 2010 at 16:46, Christoph Lameter wrote:
> On Tue, 11 May 2010, Mike Frysinger wrote:
>> > DMA. If the arch can only DMA into cacheline aligned objects then =
the
>> > correct method is to force kmalloc alignment to cacheline size.
>>
>> these are SPI drivers and are usable on any arch that supports a SPI
>> bus (which is pretty much every arch). =C2=A0forget about "embedded"
>> arches.
>>
>> the issue here is simple: a SPI driver (AD7877) needs to do a receiv=
e
>> SPI transfer into a DMA safe buffer. =C2=A0what is the exact API to
>> dynamically allocate memory for the structure with this buffer
>> embedded in it such that the start of the structure is cached aligne=
d
>> ? =C2=A0creating a dedicated kmem cache may work, but it isnt a scal=
able
>> solution if every SPI driver needs to create its own cache.
>
> kmalloc returns a pointer to a DMA safe buffer. There is no requireme=
nt on
> the x86 hardware that the DMA buffers have to be cache aligned. Cache=
lines
> will be invalidated as needed.

so this guarantee is made by the kmalloc() API ?  and for arches where
the cacheline invalidation is handled in software rather than
hardware, they must declare a min alignment value for kmalloc to be at
least as big as their cache alignment ?

does the phrase "DMA safe buffer" imply cache alignment ?
-mike
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