Re: [PATCH v4 7/8] arm64: dts: add description for solidrun solidsense-n8 board

[Josua Mayer <josua@solid-run.com>]

Hi Andrew,

Am 01.12.25 um 14:49 schrieb Andrew Lunn:
>> +&fec1 {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&fec1_pins>;
>> +	phy-mode = "rgmii-id";
>> +	phy-handle = <&phy4>;
>> +	local-mac-address = [00 00 00 00 00 00];
>> +	fsl,magic-packet;
> Has WoL been tested, or is this copy/paste from the binding
> documentation?

This is copy-paste by previous developers which I did not validate.

So I may wish to drop both local-mac-address property
(should be automatic by u-boot),

and drop the magic-packet here.

>
>> +	status = "okay";
>> +
>> +	mdio {
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +
>> +		/*
>> +		 * Depending on board revision two different phys are used:
>> +		 * - v1.1: atheros phy at address 4
>> +		 * - v1.2+: analog devices phy at address 0
>> +		 * Configure first version by default.
>> +		 * On v1.2 and later, U-Boot will enable the correct phy
>> +		 * based on runtime detection and patch dtb accordingly.
>> +		 */
>> +
>> +		/* ADIN1300 */
>> +		phy0: ethernet-phy@0 {
>> +			reg = <0>;
>> +			reset-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
>> +			reset-assert-us = <10>;
>> +			reset-deassert-us = <5000>;
>> +			interrupt-parent = <&gpio1>;
>> +			interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
> The analog devices PHY has interrupts, so can it implement WoL? Has
> this been tested?
Interrupts were tested, WoL was not.
>
>> +		/* AR8035 */
>> +		phy4: ethernet-phy@4 {
>> +			reg = <4>;
>> +			reset-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
>> +			reset-assert-us = <10000>;
>> +			status = "okay";
> The Atheros PHY does not interrupts, so i assume it cannot support
> WoL? You only have MAC WoL?
We have never tested any off states where the phy was still on.
Instead the board is designed to be always-in with supercap to cover
glitches and/or ensure graceful shutdown.

So I suggest dropping any traces of WoL.

regards
Josua Mayer