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Wed, 29 May 2024 03:07:13 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.11.0-alpha0-491-g033e30d24-fm-20240520.001-g033e30d2 Precedence: bulk X-Mailing-List: linux-input@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: In-Reply-To: References: <20240528115802.3122955-1-arnd@kernel.org> Date: Wed, 29 May 2024 09:06:17 +0200 From: "Arnd Bergmann" To: "Lixu Zhang" , "Arnd Bergmann" , "srinivas.pandruvada@linux.intel.com" , "Jiri Kosina" , "Benjamin Tissoires" Cc: "linux-input@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH 1/2] HID: intel-ish-hid: fix cache management mistake Content-Type: text/plain On Wed, May 29, 2024, at 08:46, Zhang, Lixu wrote: >> >>-#include >> #include >> #include >> #include >>@@ -175,10 +174,11 @@ static int prepare_dma_bufs(struct ishtp_device >>*dev, >> return -ENOMEM; >> >> fragment->fragment_tbl[i].ddr_adrs = >>cpu_to_le64(dma_addr); >>+ >>+ memcpy(dma_bufs[i], ish_fw->data + offset, fragment- >>>fragment_tbl[i].length); > fragment->fragment_tbl[i].length was used before assignment. > >>+ dma_wmb(); > I tested it on the platform, but it didn't wok. > What behavior do you see instead? If the manual cache flush works around a bug, that would indicate that the device itself is not coherent and the dma_alloc_coherent() in the architecture is broken. Arnd