From: Viresh KUMAR <viresh.kumar-qxv4g6HH51o@public.gmane.org>
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
rtc-linux-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org,
a.zummo-BfzFCNDTiLLj+vYz1yj4TQ@public.gmane.org,
dbrownell-Rn4VEauK+AKRv+LV9MX5uipxlwaOVQ5f@public.gmane.org,
linux-usb-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-input-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, dmitry
Cc: Shiraz Hashim <shiraz.hashim-qxv4g6HH51o@public.gmane.org>,
vipin.kumar-qxv4g6HH51o@public.gmane.org,
deepak.sikri-qxv4g6HH51o@public.gmane.org,
armando.visconti-qxv4g6HH51o@public.gmane.org,
vipulkumar.samar-qxv4g6HH51o@public.gmane.org,
rajeev-dlh.kumar-qxv4g6HH51o@public.gmane.org,
pratyush.anand-qxv4g6HH51o@public.gmane.org,
bhupesh.sharma-qxv4g6HH51o@public.gmane.org,
Viresh Kumar <viresh.kumar-qxv4g6HH51o@public.gmane.org>
Subject: [PATCH V2 35/69] SPEAr: defines base addresses as ulong.
Date: Fri, 1 Oct 2010 17:25:55 +0530 [thread overview]
Message-ID: <fff80c0d4113f421bda085a308fff187fd73e423.1285933332.git.viresh.kumar@st.com> (raw)
In-Reply-To: <cover.1285933331.git.viresh.kumar-qxv4g6HH51o@public.gmane.org>
In-Reply-To: <cover.1285933331.git.viresh.kumar-qxv4g6HH51o@public.gmane.org>
From: Shiraz Hashim <shiraz.hashim-qxv4g6HH51o@public.gmane.org>
This patch defines base addresses as ulong.
Signed-off-by: Shiraz Hashim <shiraz.hashim-qxv4g6HH51o@public.gmane.org>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar-qxv4g6HH51o@public.gmane.org>
Signed-off-by: Viresh Kumar <viresh.kumar-qxv4g6HH51o@public.gmane.org>
---
arch/arm/mach-spear13xx/include/mach/spear.h | 91 ++++++------
arch/arm/mach-spear3xx/include/mach/spear.h | 134 +++++-------------
arch/arm/mach-spear3xx/include/mach/spear300.h | 59 ++------
arch/arm/mach-spear3xx/include/mach/spear310.h | 34 ++---
arch/arm/mach-spear3xx/include/mach/spear320.h | 68 +++-------
arch/arm/mach-spear6xx/include/mach/spear.h | 174 ++++++-----------------
6 files changed, 172 insertions(+), 388 deletions(-)
diff --git a/arch/arm/mach-spear13xx/include/mach/spear.h b/arch/arm/mach-spear13xx/include/mach/spear.h
index 282ef2f..1a1af72 100644
--- a/arch/arm/mach-spear13xx/include/mach/spear.h
+++ b/arch/arm/mach-spear13xx/include/mach/spear.h
@@ -14,12 +14,13 @@
#ifndef __MACH_SPEAR13XX_H
#define __MACH_SPEAR13XX_H
+#include <asm/memory.h>
#include <mach/spear1300.h>
-#define SPEAR13XX_L2CC_BASE 0xED000000
+#define SPEAR13XX_L2CC_BASE UL(0xED000000)
/* ARM9SMP peripheral base address */
-#define SPEAR13XX_A9SM_PERIP_BASE 0xEC800000
+#define SPEAR13XX_A9SM_PERIP_BASE UL(0xEC800000)
#define VA_SPEAR13XX_A9SM_PERIP_BASE IO_ADDRESS(SPEAR13XX_A9SM_PERIP_BASE)
/* A9SM peripheral offsets */
#define SPEAR13XX_SCU_BASE (SPEAR13XX_A9SM_PERIP_BASE + 0x00)
@@ -29,26 +30,26 @@
#define SPEAR13XX_WDT_BASE (SPEAR13XX_A9SM_PERIP_BASE + 0x620)
#define SPEAR13XX_GIC_DIST_BASE (SPEAR13XX_A9SM_PERIP_BASE + 0x1000)
-#define SPEAR13XX_UART_BASE 0xE0000000
+#define SPEAR13XX_UART_BASE UL(0xE0000000)
#define VA_SPEAR13XX_UART_BASE IO_ADDRESS(SPEAR13XX_UART_BASE)
-#define SPEAR13XX_ADC_BASE 0xE0080000
-#define SPEAR13XX_SSP_BASE 0xE0100000
-#define SPEAR13XX_I2S0_BASE 0xE0180000
-#define SPEAR13XX_I2S1_BASE 0xE0200000
-#define SPEAR13XX_I2C_BASE 0xE0280000
-#define SPEAR13XX_KBD_BASE 0xE0300000
-#define SPEAR13XX_GPT0_BASE 0xE0380000
-#define SPEAR13XX_GPT1_BASE 0xE0400000
-#define SPEAR13XX_GPT2_BASE 0xE0480000
-#define SPEAR13XX_GPT3_BASE 0xE0500000
-#define SPEAR13XX_RTC_BASE 0xE0580000
-#define SPEAR13XX_GPIO0_BASE 0xE0600000
-#define SPEAR13XX_GPIO1_BASE 0xE0680000
-#define SPEAR13XX_MISC_BASE 0xE0700000
+#define SPEAR13XX_ADC_BASE UL(0xE0080000)
+#define SPEAR13XX_SSP_BASE UL(0xE0100000)
+#define SPEAR13XX_I2S0_BASE UL(0xE0180000)
+#define SPEAR13XX_I2S1_BASE UL(0xE0200000)
+#define SPEAR13XX_I2C_BASE UL(0xE0280000)
+#define SPEAR13XX_KBD_BASE UL(0xE0300000)
+#define SPEAR13XX_GPT0_BASE UL(0xE0380000)
+#define SPEAR13XX_GPT1_BASE UL(0xE0400000)
+#define SPEAR13XX_GPT2_BASE UL(0xE0480000)
+#define SPEAR13XX_GPT3_BASE UL(0xE0500000)
+#define SPEAR13XX_RTC_BASE UL(0xE0580000)
+#define SPEAR13XX_GPIO0_BASE UL(0xE0600000)
+#define SPEAR13XX_GPIO1_BASE UL(0xE0680000)
+#define SPEAR13XX_MISC_BASE UL(0xE0700000)
#define VA_SPEAR13XX_MISC_BASE IO_ADDRESS(SPEAR13XX_MISC_BASE)
-#define SPEAR13XX_SYSRAM0_BASE 0xB3800000
+#define SPEAR13XX_SYSRAM0_BASE UL(0xB3800000)
#define SPEAR13XX_SYSRAM0_SIZE 0x00800000
/*
@@ -57,34 +58,34 @@
*/
#define SPEAR13XX_SYS_LOCATION (SPEAR13XX_SYSRAM0_BASE + 0x600)
-#define SPEAR13XX_SYSRAM1_BASE 0xE0800000
+#define SPEAR13XX_SYSRAM1_BASE UL(0xE0800000)
#define SPEAR13XX_SYSRAM1_SIZE 0x00800000
-#define SPEAR13XX_CLCD_BASE 0xE1000000
-#define SPEAR13XX_C3_BASE 0xE1800000
-#define SPEAR13XX_GETH_BASE 0xE2000000
-#define SPEAR13XX_UPD_BASE 0xE2800000
-#define SPEAR13XX_UDC_BASE 0xE3800000
-#define SPEAR13XX_UHC0_OHCI_BASE 0xE4000000
-#define SPEAR13XX_UHC0_EHCI_BASE 0xE4800000
-#define SPEAR13XX_UHC1_OHCI_BASE 0xE5000000
-#define SPEAR13XX_UHC1_EHCI_BASE 0xE5800000
-#define SPEAR13XX_SMI_MEM_BASE 0xE6000000
-#define SPEAR13XX_SMI_CTRL_BASE 0xEA000000
-#define SPEAR13XX_DMAC0_BASE 0xEA800000
-#define SPEAR13XX_DMAC1_BASE 0xEB000000
-#define SPEAR13XX_MII_PHY_BASE 0xEB800000
-#define SPEAR13XX_MPMC_BASE 0xEC000000
-#define SPEAR13XX_PCIE0_BASE 0x80000000
-#define SPEAR13XX_PCIE1_BASE 0x90000000
-#define SPEAR13XX_PCIE2_BASE 0xC0000000
-#define SPEAR13XX_PCIE0_APP_BASE 0xB1000000
-#define SPEAR13XX_PCIE1_APP_BASE 0xB1800000
-#define SPEAR13XX_PCIE2_APP_BASE 0xB4000000
-#define SPEAR13XX_FSMC_MEM_BASE 0xA0000000
-#define SPEAR13XX_FSMC_BASE 0xB0000000
-#define SPEAR13XX_JPEG_BASE 0xB2000000
-#define SPEAR13XX_MCIF_CF_BASE 0xB2800000
-#define SPEAR13XX_MCIF_SDHCI_BASE 0xB3000000
+#define SPEAR13XX_CLCD_BASE UL(0xE1000000)
+#define SPEAR13XX_C3_BASE UL(0xE1800000)
+#define SPEAR13XX_GETH_BASE UL(0xE2000000)
+#define SPEAR13XX_UPD_BASE UL(0xE2800000)
+#define SPEAR13XX_UDC_BASE UL(0xE3800000)
+#define SPEAR13XX_UHC0_OHCI_BASE UL(0xE4000000)
+#define SPEAR13XX_UHC0_EHCI_BASE UL(0xE4800000)
+#define SPEAR13XX_UHC1_OHCI_BASE UL(0xE5000000)
+#define SPEAR13XX_UHC1_EHCI_BASE UL(0xE5800000)
+#define SPEAR13XX_SMI_MEM_BASE UL(0xE6000000)
+#define SPEAR13XX_SMI_CTRL_BASE UL(0xEA000000)
+#define SPEAR13XX_DMAC0_BASE UL(0xEA800000)
+#define SPEAR13XX_DMAC1_BASE UL(0xEB000000)
+#define SPEAR13XX_MII_PHY_BASE UL(0xEB800000)
+#define SPEAR13XX_MPMC_BASE UL(0xEC000000)
+#define SPEAR13XX_PCIE0_BASE UL(0x80000000)
+#define SPEAR13XX_PCIE1_BASE UL(0x90000000)
+#define SPEAR13XX_PCIE2_BASE UL(0xC0000000)
+#define SPEAR13XX_PCIE0_APP_BASE UL(0xB1000000)
+#define SPEAR13XX_PCIE1_APP_BASE UL(0xB1800000)
+#define SPEAR13XX_PCIE2_APP_BASE UL(0xB4000000)
+#define SPEAR13XX_FSMC_MEM_BASE UL(0xA0000000)
+#define SPEAR13XX_FSMC_BASE UL(0xB0000000)
+#define SPEAR13XX_JPEG_BASE UL(0xB2000000)
+#define SPEAR13XX_MCIF_CF_BASE UL(0xB2800000)
+#define SPEAR13XX_MCIF_SDHCI_BASE UL(0xB3000000)
/* Debug uart for linux, will be used for debug and uncompress messages */
#define SPEAR_DBG_UART_BASE SPEAR13XX_UART_BASE
diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h
index dcca856..00828bb 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear.h
@@ -14,124 +14,62 @@
#ifndef __MACH_SPEAR3XX_H
#define __MACH_SPEAR3XX_H
+#include <asm/memory.h>
#include <mach/hardware.h>
#include <mach/spear300.h>
#include <mach/spear310.h>
#include <mach/spear320.h>
-#define SPEAR3XX_ML_SDRAM_BASE 0x00000000
-#define SPEAR3XX_ML_SDRAM_SIZE 0x40000000
+#define SPEAR3XX_ML_SDRAM_BASE UL(0x00000000)
-#define SPEAR3XX_ICM9_BASE 0xC0000000
-#define SPEAR3XX_ICM9_SIZE 0x10000000
+#define SPEAR3XX_ICM9_BASE UL(0xC0000000)
/* ICM1 - Low speed connection */
-#define SPEAR3XX_ICM1_2_BASE 0xD0000000
-#define SPEAR3XX_ICM1_2_SIZE 0x10000000
-
-#define SPEAR3XX_ICM1_UART_BASE 0xD0000000
+#define SPEAR3XX_ICM1_2_BASE UL(0xD0000000)
+#define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000)
#define VA_SPEAR3XX_ICM1_UART_BASE IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE)
-#define SPEAR3XX_ICM1_UART_SIZE 0x00080000
-
-#define SPEAR3XX_ICM1_ADC_BASE 0xD0080000
-#define SPEAR3XX_ICM1_ADC_SIZE 0x00080000
-
-#define SPEAR3XX_ICM1_SSP_BASE 0xD0100000
-#define SPEAR3XX_ICM1_SSP_SIZE 0x00080000
-
-#define SPEAR3XX_ICM1_I2C_BASE 0xD0180000
-#define SPEAR3XX_ICM1_I2C_SIZE 0x00080000
-
-#define SPEAR3XX_ICM1_JPEG_BASE 0xD0800000
-#define SPEAR3XX_ICM1_JPEG_SIZE 0x00800000
-
-#define SPEAR3XX_ICM1_IRDA_BASE 0xD1000000
-#define SPEAR3XX_ICM1_IRDA_SIZE 0x00080000
-
-#define SPEAR3XX_ICM1_SRAM_BASE 0xD2800000
-#define SPEAR3XX_ICM1_SRAM_SIZE 0x05800000
+#define SPEAR3XX_ICM1_ADC_BASE UL(0xD0080000)
+#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
+#define SPEAR3XX_ICM1_I2C_BASE UL(0xD0180000)
+#define SPEAR3XX_ICM1_JPEG_BASE UL(0xD0800000)
+#define SPEAR3XX_ICM1_IRDA_BASE UL(0xD1000000)
+#define SPEAR3XX_ICM1_SRAM_BASE UL(0xD2800000)
/* ICM2 - Application Subsystem */
-#define SPEAR3XX_ICM2_HWACCEL0_BASE 0xD8800000
-#define SPEAR3XX_ICM2_HWACCEL0_SIZE 0x00800000
-
-#define SPEAR3XX_ICM2_HWACCEL1_BASE 0xD9000000
-#define SPEAR3XX_ICM2_HWACCEL1_SIZE 0x00800000
+#define SPEAR3XX_ICM2_HWACCEL0_BASE UL(0xD8800000)
+#define SPEAR3XX_ICM2_HWACCEL1_BASE UL(0xD9000000)
/* ICM4 - High Speed Connection */
-#define SPEAR3XX_ICM4_BASE 0xE0000000
-#define SPEAR3XX_ICM4_SIZE 0x08000000
-
-#define SPEAR3XX_ICM4_MII_BASE 0xE0800000
-#define SPEAR3XX_ICM4_MII_SIZE 0x00800000
-
-#define SPEAR3XX_ICM4_USBD_FIFO_BASE 0xE1000000
-#define SPEAR3XX_ICM4_USBD_FIFO_SIZE 0x00100000
-
-#define SPEAR3XX_ICM4_USBD_CSR_BASE 0xE1100000
-#define SPEAR3XX_ICM4_USBD_CSR_SIZE 0x00100000
-
-#define SPEAR3XX_ICM4_USBD_PLDT_BASE 0xE1200000
-#define SPEAR3XX_ICM4_USBD_PLDT_SIZE 0x00100000
-
-#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE 0xE1800000
-#define SPEAR3XX_ICM4_USB_EHCI0_1_SIZE 0x00100000
-
-#define SPEAR3XX_ICM4_USB_OHCI0_BASE 0xE1900000
-#define SPEAR3XX_ICM4_USB_OHCI0_SIZE 0x00100000
-
-#define SPEAR3XX_ICM4_USB_OHCI1_BASE 0xE2100000
-#define SPEAR3XX_ICM4_USB_OHCI1_SIZE 0x00100000
-
-#define SPEAR3XX_ICM4_USB_ARB_BASE 0xE2800000
-#define SPEAR3XX_ICM4_USB_ARB_SIZE 0x00010000
+#define SPEAR3XX_ICM4_BASE UL(0xE0000000)
+#define SPEAR3XX_ICM4_MII_BASE UL(0xE0800000)
+#define SPEAR3XX_ICM4_USBD_FIFO_BASE UL(0xE1000000)
+#define SPEAR3XX_ICM4_USBD_CSR_BASE UL(0xE1100000)
+#define SPEAR3XX_ICM4_USBD_PLDT_BASE UL(0xE1200000)
+#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE UL(0xE1800000)
+#define SPEAR3XX_ICM4_USB_OHCI0_BASE UL(0xE1900000)
+#define SPEAR3XX_ICM4_USB_OHCI1_BASE UL(0xE2100000)
+#define SPEAR3XX_ICM4_USB_ARB_BASE UL(0xE2800000)
/* ML1 - Multi Layer CPU Subsystem */
-#define SPEAR3XX_ICM3_ML1_2_BASE 0xF0000000
-#define SPEAR3XX_ICM3_ML1_2_SIZE 0x0F000000
-
-#define SPEAR3XX_ML1_TMR_BASE 0xF0000000
-#define SPEAR3XX_ML1_TMR_SIZE 0x00100000
-
-#define SPEAR3XX_ML1_VIC_BASE 0xF1100000
+#define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000)
+#define SPEAR3XX_ML1_TMR_BASE UL(0xF0000000)
+#define SPEAR3XX_ML1_VIC_BASE UL(0xF1100000)
#define VA_SPEAR3XX_ML1_VIC_BASE IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE)
-#define SPEAR3XX_ML1_VIC_SIZE 0x00100000
/* ICM3 - Basic Subsystem */
-#define SPEAR3XX_ICM3_SMEM_BASE 0xF8000000
-#define SPEAR3XX_ICM3_SMEM_SIZE 0x04000000
-
-#define SPEAR3XX_ICM3_SMI_CTRL_BASE 0xFC000000
-#define SPEAR3XX_ICM3_SMI_CTRL_SIZE 0x00200000
-
-#define SPEAR3XX_ICM3_DMA_BASE 0xFC400000
-#define SPEAR3XX_ICM3_DMA_SIZE 0x00200000
-
-#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE 0xFC600000
-#define SPEAR3XX_ICM3_SDRAM_CTRL_SIZE 0x00200000
-
-#define SPEAR3XX_ICM3_TMR0_BASE 0xFC800000
-#define SPEAR3XX_ICM3_TMR0_SIZE 0x00080000
-
-#define SPEAR3XX_ICM3_WDT_BASE 0xFC880000
-#define SPEAR3XX_ICM3_WDT_SIZE 0x00080000
-
-#define SPEAR3XX_ICM3_RTC_BASE 0xFC900000
-#define SPEAR3XX_ICM3_RTC_SIZE 0x00080000
-
-#define SPEAR3XX_ICM3_GPIO_BASE 0xFC980000
-#define SPEAR3XX_ICM3_GPIO_SIZE 0x00080000
-
-#define SPEAR3XX_ICM3_SYS_CTRL_BASE 0xFCA00000
+#define SPEAR3XX_ICM3_SMEM_BASE UL(0xF8000000)
+#define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
+#define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000)
+#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000)
+#define SPEAR3XX_ICM3_TMR0_BASE UL(0xFC800000)
+#define SPEAR3XX_ICM3_WDT_BASE UL(0xFC880000)
+#define SPEAR3XX_ICM3_RTC_BASE UL(0xFC900000)
+#define SPEAR3XX_ICM3_GPIO_BASE UL(0xFC980000)
+#define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE)
-#define SPEAR3XX_ICM3_SYS_CTRL_SIZE 0x00080000
-
-#define SPEAR3XX_ICM3_MISC_REG_BASE 0xFCA80000
+#define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000)
#define VA_SPEAR3XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE)
-#define SPEAR3XX_ICM3_MISC_REG_SIZE 0x00080000
-
-#define SPEAR3XX_ICM3_TMR1_BASE 0xFCB00000
-#define SPEAR3XX_ICM3_TMR1_SIZE 0x00080000
+#define SPEAR3XX_ICM3_TMR1_BASE UL(0xFCB00000)
/* Debug uart for linux, will be used for debug and uncompress messages */
#define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE
diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h
index 1059d5a..c723515 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear300.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear300.h
@@ -17,11 +17,9 @@
#define __MACH_SPEAR300_H
/* Base address of various IPs */
-#define SPEAR300_TELECOM_BASE 0x50000000
-#define SPEAR300_TELECOM_SIZE 0x10000000
+#define SPEAR300_TELECOM_BASE UL(0x50000000)
/* Interrupt registers offsets and masks */
-#define SPEAR300_TELECOM_REG_SIZE 0x00010000
#define INT_ENB_MASK_REG 0x54
#define INT_STS_MASK_REG 0x58
#define IT_PERS_S_IRQ_MASK (1 << 0)
@@ -36,47 +34,20 @@
#define SHIRQ_RAS1_MASK 0x1FF
-#define SPEAR300_CLCD_BASE 0x60000000
-#define SPEAR300_CLCD_SIZE 0x10000000
-
-#define SPEAR300_SDHCI_BASE 0x70000000
-#define SPEAR300_SDHCI_SIZE 0x10000000
-
-#define SPEAR300_NAND_0_BASE 0x80000000
-#define SPEAR300_NAND_0_SIZE 0x04000000
-
-#define SPEAR300_NAND_1_BASE 0x84000000
-#define SPEAR300_NAND_1_SIZE 0x04000000
-
-#define SPEAR300_NAND_2_BASE 0x88000000
-#define SPEAR300_NAND_2_SIZE 0x04000000
-
-#define SPEAR300_NAND_3_BASE 0x8c000000
-#define SPEAR300_NAND_3_SIZE 0x04000000
-
-#define SPEAR300_NOR_0_BASE 0x90000000
-#define SPEAR300_NOR_0_SIZE 0x01000000
-
-#define SPEAR300_NOR_1_BASE 0x91000000
-#define SPEAR300_NOR_1_SIZE 0x01000000
-
-#define SPEAR300_NOR_2_BASE 0x92000000
-#define SPEAR300_NOR_2_SIZE 0x01000000
-
-#define SPEAR300_NOR_3_BASE 0x93000000
-#define SPEAR300_NOR_3_SIZE 0x01000000
-
-#define SPEAR300_FSMC_BASE 0x94000000
-#define SPEAR300_FSMC_SIZE 0x05000000
-
-#define SPEAR300_SOC_CONFIG_BASE 0x99000000
-#define SPEAR300_SOC_CONFIG_SIZE 0x00000008
-
-#define SPEAR300_KEYBOARD_BASE 0xA0000000
-#define SPEAR300_KEYBOARD_SIZE 0x09000000
-
-#define SPEAR300_GPIO_BASE 0xA9000000
-#define SPEAR300_GPIO_SIZE 0x07000000
+#define SPEAR300_CLCD_BASE UL(0x60000000)
+#define SPEAR300_SDHCI_BASE UL(0x70000000)
+#define SPEAR300_NAND_0_BASE UL(0x80000000)
+#define SPEAR300_NAND_1_BASE UL(0x84000000)
+#define SPEAR300_NAND_2_BASE UL(0x88000000)
+#define SPEAR300_NAND_3_BASE UL(0x8c000000)
+#define SPEAR300_NOR_0_BASE UL(0x90000000)
+#define SPEAR300_NOR_1_BASE UL(0x91000000)
+#define SPEAR300_NOR_2_BASE UL(0x92000000)
+#define SPEAR300_NOR_3_BASE UL(0x93000000)
+#define SPEAR300_FSMC_BASE UL(0x94000000)
+#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000)
+#define SPEAR300_KEYBOARD_BASE UL(0xA0000000)
+#define SPEAR300_GPIO_BASE UL(0xA9000000)
#endif /* __MACH_SPEAR300_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h
index b27bb8a..1e85347 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear310.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear310.h
@@ -16,30 +16,18 @@
#ifndef __MACH_SPEAR310_H
#define __MACH_SPEAR310_H
-#define SPEAR310_NAND_BASE 0x40000000
-#define SPEAR310_NAND_SIZE 0x04000000
+#define SPEAR310_NAND_BASE UL(0x40000000)
+#define SPEAR310_FSMC_BASE UL(0x44000000)
+#define SPEAR310_UART1_BASE UL(0xB2000000)
+#define SPEAR310_UART2_BASE UL(0xB2080000)
+#define SPEAR310_UART3_BASE UL(0xB2100000)
+#define SPEAR310_UART4_BASE UL(0xB2180000)
+#define SPEAR310_UART5_BASE UL(0xB2200000)
+#define SPEAR310_HDLC_BASE UL(0xB2800000)
+#define SPEAR310_RS485_0_BASE UL(0xB3000000)
+#define SPEAR310_RS485_1_BASE UL(0xB3800000)
+#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000)
-#define SPEAR310_FSMC_BASE 0x44000000
-#define SPEAR310_FSMC_SIZE 0x01000000
-
-#define SPEAR310_UART1_BASE 0xB2000000
-#define SPEAR310_UART2_BASE 0xB2080000
-#define SPEAR310_UART3_BASE 0xB2100000
-#define SPEAR310_UART4_BASE 0xB2180000
-#define SPEAR310_UART5_BASE 0xB2200000
-#define SPEAR310_UART_SIZE 0x00080000
-
-#define SPEAR310_HDLC_BASE 0xB2800000
-#define SPEAR310_HDLC_SIZE 0x00800000
-
-#define SPEAR310_RS485_0_BASE 0xB3000000
-#define SPEAR310_RS485_0_SIZE 0x00800000
-
-#define SPEAR310_RS485_1_BASE 0xB3800000
-#define SPEAR310_RS485_1_SIZE 0x00800000
-
-#define SPEAR310_SOC_CONFIG_BASE 0xB4000000
-#define SPEAR310_SOC_CONFIG_SIZE 0x00000070
/* Interrupt registers offsets and masks */
#define INT_STS_MASK_REG 0x04
#define SMII0_IRQ_MASK (1 << 0)
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
index 89f5bfb..940f0d8 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear320.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear320.h
@@ -16,57 +16,25 @@
#ifndef __MACH_SPEAR320_H
#define __MACH_SPEAR320_H
-#define SPEAR320_EMI_CTRL_BASE 0x40000000
-#define SPEAR320_EMI_CTRL_SIZE 0x08000000
+#define SPEAR320_EMI_CTRL_BASE UL(0x40000000)
+#define SPEAR320_FSMC_BASE UL(0x4C000000)
+#define SPEAR320_NAND_BASE UL(0x50000000)
+#define SPEAR320_I2S_BASE UL(0x60000000)
+#define SPEAR320_SDHCI_BASE UL(0x70000000)
+#define SPEAR320_CLCD_BASE UL(0x90000000)
+#define SPEAR320_PAR_PORT_BASE UL(0xA0000000)
+#define SPEAR320_CAN0_BASE UL(0xA1000000)
+#define SPEAR320_CAN1_BASE UL(0xA2000000)
+#define SPEAR320_UART1_BASE UL(0xA3000000)
+#define SPEAR320_UART2_BASE UL(0xA4000000)
+#define SPEAR320_SSP0_BASE UL(0xA5000000)
+#define SPEAR320_SSP1_BASE UL(0xA6000000)
+#define SPEAR320_I2C_BASE UL(0xA7000000)
+#define SPEAR320_PWM_BASE UL(0xA8000000)
+#define SPEAR320_SMII0_BASE UL(0xAA000000)
+#define SPEAR320_SMII1_BASE UL(0xAB000000)
+#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
-#define SPEAR320_FSMC_BASE 0x4C000000
-#define SPEAR320_FSMC_SIZE 0x01000000
-
-#define SPEAR320_NAND_BASE 0x50000000
-#define SPEAR320_NAND_SIZE 0x04000000
-
-#define SPEAR320_I2S_BASE 0x60000000
-#define SPEAR320_I2S_SIZE 0x10000000
-
-#define SPEAR320_SDHCI_BASE 0x70000000
-#define SPEAR320_SDHCI_SIZE 0x10000000
-
-#define SPEAR320_CLCD_BASE 0x90000000
-#define SPEAR320_CLCD_SIZE 0x10000000
-
-#define SPEAR320_PAR_PORT_BASE 0xA0000000
-#define SPEAR320_PAR_PORT_SIZE 0x01000000
-
-#define SPEAR320_CAN0_BASE 0xA1000000
-#define SPEAR320_CAN0_SIZE 0x01000000
-
-#define SPEAR320_CAN1_BASE 0xA2000000
-#define SPEAR320_CAN1_SIZE 0x01000000
-
-#define SPEAR320_UART1_BASE 0xA3000000
-#define SPEAR320_UART2_BASE 0xA4000000
-#define SPEAR320_UART_SIZE 0x01000000
-
-#define SPEAR320_SSP0_BASE 0xA5000000
-#define SPEAR320_SSP0_SIZE 0x01000000
-
-#define SPEAR320_SSP1_BASE 0xA6000000
-#define SPEAR320_SSP1_SIZE 0x01000000
-
-#define SPEAR320_I2C_BASE 0xA7000000
-#define SPEAR320_I2C_SIZE 0x01000000
-
-#define SPEAR320_PWM_BASE 0xA8000000
-#define SPEAR320_PWM_SIZE 0x01000000
-
-#define SPEAR320_SMII0_BASE 0xAA000000
-#define SPEAR320_SMII0_SIZE 0x01000000
-
-#define SPEAR320_SMII1_BASE 0xAB000000
-#define SPEAR320_SMII1_SIZE 0x01000000
-
-#define SPEAR320_SOC_CONFIG_BASE 0xB3000000
-#define SPEAR320_SOC_CONFIG_SIZE 0x00000070
/* Interrupt registers offsets and masks */
#define INT_STS_MASK_REG 0x04
#define INT_CLR_MASK_REG 0x04
diff --git a/arch/arm/mach-spear6xx/include/mach/spear.h b/arch/arm/mach-spear6xx/include/mach/spear.h
index 31486e5..4a2ecc7 100644
--- a/arch/arm/mach-spear6xx/include/mach/spear.h
+++ b/arch/arm/mach-spear6xx/include/mach/spear.h
@@ -14,153 +14,71 @@
#ifndef __MACH_SPEAR6XX_H
#define __MACH_SPEAR6XX_H
+#include <asm/memory.h>
#include <mach/hardware.h>
#include <mach/spear600.h>
-#define SPEAR6XX_ML_SDRAM_BASE 0x00000000
-#define SPEAR6XX_ML_SDRAM_SIZE 0x40000000
-
+#define SPEAR6XX_ML_SDRAM_BASE UL(0x00000000)
/* ICM1 - Low speed connection */
-#define SPEAR6XX_ICM1_BASE 0xD0000000
-#define SPEAR6XX_ICM1_SIZE 0x08000000
+#define SPEAR6XX_ICM1_BASE UL(0xD0000000)
-#define SPEAR6XX_ICM1_UART0_BASE 0xD0000000
+#define SPEAR6XX_ICM1_UART0_BASE UL(0xD0000000)
#define VA_SPEAR6XX_ICM1_UART0_BASE IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE)
-#define SPEAR6XX_ICM1_UART0_SIZE 0x00080000
-
-#define SPEAR6XX_ICM1_UART1_BASE 0xD0080000
-#define SPEAR6XX_ICM1_UART1_SIZE 0x00080000
-
-#define SPEAR6XX_ICM1_SSP0_BASE 0xD0100000
-#define SPEAR6XX_ICM1_SSP0_SIZE 0x00080000
-
-#define SPEAR6XX_ICM1_SSP1_BASE 0xD0180000
-#define SPEAR6XX_ICM1_SSP1_SIZE 0x00080000
-
-#define SPEAR6XX_ICM1_I2C_BASE 0xD0200000
-#define SPEAR6XX_ICM1_I2C_SIZE 0x00080000
-#define SPEAR6XX_ICM1_JPEG_BASE 0xD0800000
-#define SPEAR6XX_ICM1_JPEG_SIZE 0x00800000
-
-#define SPEAR6XX_ICM1_IRDA_BASE 0xD1000000
-#define SPEAR6XX_ICM1_IRDA_SIZE 0x00800000
-
-#define SPEAR6XX_ICM1_FSMC_BASE 0xD1800000
-#define SPEAR6XX_ICM1_FSMC_SIZE 0x00800000
-
-#define SPEAR6XX_ICM1_NAND_BASE 0xD2000000
-#define SPEAR6XX_ICM1_NAND_SIZE 0x00800000
-
-#define SPEAR6XX_ICM1_SRAM_BASE 0xD2800000
-#define SPEAR6XX_ICM1_SRAM_SIZE 0x00800000
+#define SPEAR6XX_ICM1_UART1_BASE UL(0xD0080000)
+#define SPEAR6XX_ICM1_SSP0_BASE UL(0xD0100000)
+#define SPEAR6XX_ICM1_SSP1_BASE UL(0xD0180000)
+#define SPEAR6XX_ICM1_I2C_BASE UL(0xD0200000)
+#define SPEAR6XX_ICM1_JPEG_BASE UL(0xD0800000)
+#define SPEAR6XX_ICM1_IRDA_BASE UL(0xD1000000)
+#define SPEAR6XX_ICM1_FSMC_BASE UL(0xD1800000)
+#define SPEAR6XX_ICM1_NAND_BASE UL(0xD2000000)
+#define SPEAR6XX_ICM1_SRAM_BASE UL(0xD2800000)
/* ICM2 - Application Subsystem */
-#define SPEAR6XX_ICM2_BASE 0xD8000000
-#define SPEAR6XX_ICM2_SIZE 0x08000000
-
-#define SPEAR6XX_ICM2_TMR0_BASE 0xD8000000
-#define SPEAR6XX_ICM2_TMR0_SIZE 0x00080000
-
-#define SPEAR6XX_ICM2_TMR1_BASE 0xD8080000
-#define SPEAR6XX_ICM2_TMR1_SIZE 0x00080000
-
-#define SPEAR6XX_ICM2_GPIO_BASE 0xD8100000
-#define SPEAR6XX_ICM2_GPIO_SIZE 0x00080000
-
-#define SPEAR6XX_ICM2_SSP2_BASE 0xD8180000
-#define SPEAR6XX_ICM2_SSP2_SIZE 0x00080000
-
-#define SPEAR6XX_ICM2_ADC_BASE 0xD8200000
-#define SPEAR6XX_ICM2_ADC_SIZE 0x00080000
+#define SPEAR6XX_ICM2_BASE UL(0xD8000000)
+#define SPEAR6XX_ICM2_TMR0_BASE UL(0xD8000000)
+#define SPEAR6XX_ICM2_TMR1_BASE UL(0xD8080000)
+#define SPEAR6XX_ICM2_GPIO_BASE UL(0xD8100000)
+#define SPEAR6XX_ICM2_SSP2_BASE UL(0xD8180000)
+#define SPEAR6XX_ICM2_ADC_BASE UL(0xD8200000)
/* ML-1, 2 - Multi Layer CPU Subsystem */
-#define SPEAR6XX_ML_CPU_BASE 0xF0000000
-#define SPEAR6XX_ML_CPU_SIZE 0x08000000
-
-#define SPEAR6XX_CPU_TMR_BASE 0xF0000000
-#define SPEAR6XX_CPU_TMR_SIZE 0x00100000
-
-#define SPEAR6XX_CPU_GPIO_BASE 0xF0100000
-#define SPEAR6XX_CPU_GPIO_SIZE 0x00100000
-
-#define SPEAR6XX_CPU_VIC_SEC_BASE 0xF1000000
+#define SPEAR6XX_ML_CPU_BASE UL(0xF0000000)
+#define SPEAR6XX_CPU_TMR_BASE UL(0xF0000000)
+#define SPEAR6XX_CPU_GPIO_BASE UL(0xF0100000)
+#define SPEAR6XX_CPU_VIC_SEC_BASE UL(0xF1000000)
#define VA_SPEAR6XX_CPU_VIC_SEC_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE)
-#define SPEAR6XX_CPU_VIC_SEC_SIZE 0x00100000
-
-#define SPEAR6XX_CPU_VIC_PRI_BASE 0xF1100000
+#define SPEAR6XX_CPU_VIC_PRI_BASE UL(0xF1100000)
#define VA_SPEAR6XX_CPU_VIC_PRI_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE)
-#define SPEAR6XX_CPU_VIC_PRI_SIZE 0x00100000
/* ICM3 - Basic Subsystem */
-#define SPEAR6XX_ICM3_BASE 0xF8000000
-#define SPEAR6XX_ICM3_SIZE 0x08000000
-
-#define SPEAR6XX_ICM3_SMEM_BASE 0xF8000000
-#define SPEAR6XX_ICM3_SMEM_SIZE 0x04000000
-
-#define SPEAR6XX_ICM3_SMI_CTRL_BASE 0xFC000000
-#define SPEAR6XX_ICM3_SMI_CTRL_SIZE 0x00200000
-
-#define SPEAR6XX_ICM3_CLCD_BASE 0xFC200000
-#define SPEAR6XX_ICM3_CLCD_SIZE 0x00200000
-
-#define SPEAR6XX_ICM3_DMA_BASE 0xFC400000
-#define SPEAR6XX_ICM3_DMA_SIZE 0x00200000
-
-#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE 0xFC600000
-#define SPEAR6XX_ICM3_SDRAM_CTRL_SIZE 0x00200000
-
-#define SPEAR6XX_ICM3_TMR_BASE 0xFC800000
-#define SPEAR6XX_ICM3_TMR_SIZE 0x00080000
-
-#define SPEAR6XX_ICM3_WDT_BASE 0xFC880000
-#define SPEAR6XX_ICM3_WDT_SIZE 0x00080000
-
-#define SPEAR6XX_ICM3_RTC_BASE 0xFC900000
-#define SPEAR6XX_ICM3_RTC_SIZE 0x00080000
-
-#define SPEAR6XX_ICM3_GPIO_BASE 0xFC980000
-#define SPEAR6XX_ICM3_GPIO_SIZE 0x00080000
-
-#define SPEAR6XX_ICM3_SYS_CTRL_BASE 0xFCA00000
+#define SPEAR6XX_ICM3_BASE UL(0xF8000000)
+#define SPEAR6XX_ICM3_SMEM_BASE UL(0xF8000000)
+#define SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
+#define SPEAR6XX_ICM3_CLCD_BASE UL(0xFC200000)
+#define SPEAR6XX_ICM3_DMA_BASE UL(0xFC400000)
+#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000)
+#define SPEAR6XX_ICM3_TMR_BASE UL(0xFC800000)
+#define SPEAR6XX_ICM3_WDT_BASE UL(0xFC880000)
+#define SPEAR6XX_ICM3_RTC_BASE UL(0xFC900000)
+#define SPEAR6XX_ICM3_GPIO_BASE UL(0xFC980000)
+#define SPEAR6XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE)
-#define SPEAR6XX_ICM3_SYS_CTRL_SIZE 0x00080000
-
-#define SPEAR6XX_ICM3_MISC_REG_BASE 0xFCA80000
+#define SPEAR6XX_ICM3_MISC_REG_BASE UL(0xFCA80000)
#define VA_SPEAR6XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE)
-#define SPEAR6XX_ICM3_MISC_REG_SIZE 0x00080000
/* ICM4 - High Speed Connection */
-#define SPEAR6XX_ICM4_BASE 0xE0000000
-#define SPEAR6XX_ICM4_SIZE 0x08000000
-
-#define SPEAR6XX_ICM4_GMAC_BASE 0xE0800000
-#define SPEAR6XX_ICM4_GMAC_SIZE 0x00800000
-
-#define SPEAR6XX_ICM4_USBD_FIFO_BASE 0xE1000000
-#define SPEAR6XX_ICM4_USBD_FIFO_SIZE 0x00100000
-
-#define SPEAR6XX_ICM4_USBD_CSR_BASE 0xE1100000
-#define SPEAR6XX_ICM4_USBD_CSR_SIZE 0x00100000
-
-#define SPEAR6XX_ICM4_USBD_PLDT_BASE 0xE1200000
-#define SPEAR6XX_ICM4_USBD_PLDT_SIZE 0x00100000
-
-#define SPEAR6XX_ICM4_USB_EHCI0_BASE 0xE1800000
-#define SPEAR6XX_ICM4_USB_EHCI0_SIZE 0x00100000
-
-#define SPEAR6XX_ICM4_USB_OHCI0_BASE 0xE1900000
-#define SPEAR6XX_ICM4_USB_OHCI0_SIZE 0x00100000
-
-#define SPEAR6XX_ICM4_USB_EHCI1_BASE 0xE2000000
-#define SPEAR6XX_ICM4_USB_EHCI1_SIZE 0x00100000
-
-#define SPEAR6XX_ICM4_USB_OHCI1_BASE 0xE2100000
-#define SPEAR6XX_ICM4_USB_OHCI1_SIZE 0x00100000
next prev parent reply other threads:[~2010-10-01 11:55 UTC|newest]
Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <cover.1285933331.git.viresh.kumar@st.com>
2010-10-01 11:55 ` [PATCH V2 21/69] Keyboard: Adding support for spear-keyboard Viresh KUMAR
2010-10-05 15:47 ` Dmitry Torokhov
[not found] ` <20101005154737.GA19730-WlK9ik9hQGAhIp7JRqBPierSzoNAToWh@public.gmane.org>
2010-10-06 3:58 ` viresh kumar
[not found] ` <4CABF3E0.8010909-qxv4g6HH51o@public.gmane.org>
2010-10-06 6:16 ` Dmitry Torokhov
2010-10-06 7:11 ` viresh kumar
2010-11-10 6:44 ` viresh kumar
2010-10-01 11:55 ` [PATCH V2 22/69] ST SPEAr: Adding machine support for keyboard Viresh KUMAR
2010-10-01 11:55 ` [PATCH V2 25/69] ST SPEAr: Add smi driver for serial NOR flash Viresh KUMAR
2010-10-01 11:55 ` [PATCH V2 26/69] ST SPEAr: Adding support for serial nor flash in all spear platforms Viresh KUMAR
2010-10-01 11:55 ` [PATCH V2 27/69] ST SPEAr: Adding Watchdog support Viresh KUMAR
2010-10-01 11:56 ` [PATCH V2 42/69] SPEAr Power Management: Added the support for Standby mode Viresh KUMAR
[not found] ` <cover.1285933331.git.viresh.kumar-qxv4g6HH51o@public.gmane.org>
2010-10-01 11:55 ` [PATCH V2 23/69] ST SPEAr: Added ARM PL061 GPIO Support on SPEAr13xx and modified resource size Viresh KUMAR
2010-10-01 11:55 ` [PATCH V2 24/69] ST SPEAr: Adding support for ST's PWM IP Viresh KUMAR
2010-10-01 11:55 ` [PATCH V2 28/69] ST SPEAr: Adding machine support for nand Viresh KUMAR
2010-10-01 11:55 ` [PATCH V2 29/69] Newly erased page read workaround Viresh KUMAR
2010-10-01 11:55 ` [PATCH V2 30/69] ST SPEAr: Added PCIE host controller base driver support Viresh KUMAR
2010-10-01 11:55 ` [PATCH V2 31/69] ST SPEAr: Adding support for SSP PL022 Viresh KUMAR
2010-10-01 11:55 ` [PATCH V2 32/69] ST SPEAr: Adding support for SDHCI (SDIO) Viresh KUMAR
2010-10-01 11:55 ` [PATCH V2 33/69] ST SPEAr: Changing resource size of amba devices to SZ_4K Viresh KUMAR
2010-10-01 11:55 ` [PATCH V2 34/69] ST SPEAr: Replacing SIZE macro's with actual required size Viresh KUMAR
2010-10-01 11:55 ` Viresh KUMAR [this message]
2010-10-01 11:55 ` [PATCH V2 36/69] ST SPEAr: Adding miscellaneous devices Viresh KUMAR
2010-10-01 11:55 ` [PATCH V2 37/69] ST SPEAr 13xx : Adding support for SPEAr1310 Viresh KUMAR
2010-10-01 11:55 ` [PATCH V2 38/69] ST SPEAr: Adding support for DDR in clock framework Viresh KUMAR
2010-10-01 11:55 ` [PATCH V2 39/69] ST SPEAr : EMI (Extrenal Memory Interface) controller driver Viresh KUMAR
2010-10-01 11:56 ` [PATCH V2 40/69] ST SPEAr : FSMC (Flexible Static Memory Controller) NOR interface driver Viresh KUMAR
2010-10-01 11:56 ` [PATCH V2 41/69] SPEAr Clock Framework: Adding support for PLL frequency change Viresh KUMAR
2010-10-01 11:56 ` [PATCH V2 43/69] GIC: Added dummy handlers for Power Management Suspend Resume Viresh KUMAR
2010-10-01 11:56 ` [PATCH V2 48/69] ST SPEAr: replace readl, writel with __raw_readl, __raw_writel in uncompress.h Viresh KUMAR
2010-10-01 11:56 ` [PATCH V2 49/69] ST SPEAr13xx: add L2 cache support Viresh KUMAR
2010-10-01 11:56 ` [PATCH V2 51/69] SPEAr: Adding and Updating Clock definitions Viresh KUMAR
2010-10-01 11:56 ` [PATCH V2 54/69] SPEAr : Updating pad multiplexing support Viresh KUMAR
2010-10-01 11:56 ` [PATCH V2 67/69] ST SPEAr: Adding devices & clocks Viresh KUMAR
2010-10-01 11:56 ` [PATCH V2 69/69] ST SPEAr: Updating defconfigs Viresh KUMAR
2010-10-01 11:56 ` [PATCH V2 44/69] SPEAr CPU freq: Adding support for CPU Freq framework Viresh KUMAR
2010-10-01 11:56 ` [PATCH V2 45/69] ST SPEAr: PCIE gadget suppport Viresh KUMAR
2010-10-19 21:47 ` Andrew Morton
2010-10-21 14:18 ` Pratyush ANAND
2010-10-21 17:25 ` Andrew Morton
2010-10-01 11:56 ` [PATCH V2 46/69] ST SPEAr13xx: Adding machine support for pci gadget Viresh KUMAR
2010-10-01 11:56 ` [PATCH V2 47/69] ST SPEAr13xx: Adding CPU hotplug support added for SMP platforms Viresh KUMAR
2010-10-01 11:56 ` [PATCH V2 50/69] ST SPEAr13xx: Modified static mappings Viresh KUMAR
2010-10-01 11:56 ` [PATCH V2 52/69] SPEAr : Pad multiplexing handling modified Viresh KUMAR
2010-10-01 11:56 ` [PATCH V2 53/69] SPEAr13xx : Fixed part devices in SPEAr13xx addded to the generic implementation Viresh KUMAR
2010-10-01 11:56 ` [PATCH V2 55/69] ST SPEAr3xx: Passing pmx devices address from machine *.c files Viresh KUMAR
2010-10-01 11:56 ` [PATCH V2 56/69] ST SPEAr Clock Framework: Updating for single image solution Viresh KUMAR
2010-10-01 11:56 ` [PATCH V2 57/69] SPEAr3xx: Make local structures static Viresh KUMAR
2010-10-01 11:56 ` [PATCH V2 58/69] SPEAR3xx: Rename register/irq defines to remove naming conflicts Viresh KUMAR
2010-10-01 11:56 ` [PATCH V2 59/69] SPEAr3xx: Rework pmx_dev code to remove conflicts Viresh KUMAR
2010-10-01 11:56 ` [PATCH V2 60/69] SPEAr3xx: Rework KConfig to allow all boards to be compiled in Viresh KUMAR
2010-10-01 11:56 ` [PATCH V2 61/69] SPEAr3xx: Replace defconfigs with single unified defconfig Viresh KUMAR
2010-10-01 11:56 ` [PATCH V2 62/69] ST SPEAr: Appending spear3** with global structures Viresh KUMAR
2010-10-01 16:21 ` viresh kumar
[not found] ` <AANLkTi=xNoG2T1Q2JqB7TH+O7AjW++UnSt1Q85VgPbzp-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2010-10-04 6:01 ` viresh kumar
2010-10-01 11:56 ` [PATCH V2 63/69] ST SPEAr3xx: Updating plgpio and emi source to make it compliant with single image strategy Viresh KUMAR
2010-10-01 11:56 ` [PATCH V2 64/69] SPEAr6xx: Rework Kconfig for single image solution Viresh KUMAR
2010-10-01 11:56 ` [PATCH V2 65/69] ST SPEAR6xx: renaming spear600_defconfig as spear6xx_defconfig Viresh KUMAR
2010-10-01 11:56 ` [PATCH V2 66/69] ST SPEAr13xx: Pass default padmux settings as parameter to spear13**_init routine Viresh KUMAR
2010-10-01 11:56 ` [PATCH V2 68/69] ST SPEAr: Adding information in Documentation/ and MAINTAINERS Viresh KUMAR
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