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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1903a180ca2sm8819002c88.6.2026.10.21.17.31.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Oct 2026 17:31:43 -0700 (PDT) Date: Wed, 21 Oct 2026 17:31:16 -0700 From: Jonathan Cameron To: Jason Gunthorpe Cc: Alexandre Ghiti , Albert Ou , Ard Biesheuvel , Arnd Bergmann , Catalin Marinas , Jonathan Corbet , David Sterba , Ilias Apalodimas , linux-arch@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-efi@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paul Walmsley , Randy Dunlap , Simon Glass , Shuah Khan , Nick Terrell , Will Deacon , Alexandre Ghiti , Conor Dooley , linux-integrity@vger.kernel.org, Palmer Dabbelt , patches@lists.linux.dev, Piotr =?ISO-8859-1?Q?Kr=F3l?= , Ross Philipson , Sami Tolvanen , Song Shuai Subject: Re: [PATCH v2 15/15] efi/arm64: Implement ARM64 DRTM in the stub Message-ID: <20261021173116.00000df9@oss.qualcomm.com> In-Reply-To: <20261021233909.GX3008132@nvidia.com> References: <0-v2-989a18390eb1+486-arm64_drtm_jgg@nvidia.com> <15-v2-989a18390eb1+486-arm64_drtm_jgg@nvidia.com> <20261021111115.00004c5c@oss.qualcomm.com> <20261021233909.GX3008132@nvidia.com> Organization: Qualcomm X-Mailer: Claws Mail 4.4.0 (GTK 3.24.51; x86_64-w64-mingw32) X-Mailing-List: linux-integrity@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: XCXhYLbTMX3LyYqqvVATFtawbHP2c3HJ X-Proofpoint-GUID: XCXhYLbTMX3LyYqqvVATFtawbHP2c3HJ X-Authority-Analysis: v=2.4 cv=N768hG9B c=1 sm=1 tr=0 ts=6ad95971 cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=kj9zAlcOel0A:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=Ikd4Dj_1AAAA:8 a=j7B8HJC98GV4A_3RkYkA:9 a=CjuIK1q_8ugA:10 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIyMDAwMSBTYWx0ZWRfX5D2DmT3pdjlx YnW42yVhEdq9sg677YeeU3szLcJZGzZRsV9BkZksv5DD2TmTxqhuyLQgUbBubjfJiyBbq9qRp62 95pjpY+nQHn0y730qWBmQIyqFOHIeqvlPamWZQRg5qB34XqdePJcJNzvLcjQ65QNv01AMkowRR9 qqK2B6cD/WWdIHIQ2xahNZzIsHNQtxR3TDU4HKd4bcV1/sZstF7bSbEkswlLqBafzQg8wgigz/7 TgEXplQRV7W5FGLwt2Kl3SeRohskPGpiSm2kV6nORZKfRpQ63ipY8kAVXfNBUUQjSovLPyL4PR7 CNKgfEyHMNmYjpc79iJOky+1XwVFGGS6Q8HecsT54kIWlLduApfh43MuCqggywzEfS7dRetSKaM xF8eC0tzT8bmEejmRuBRxBgSTPS0FJSpuADFUnn8Q499juOulH9F7mHWmtXIljrxBaGeAo0MqNV gHg+AiXuDs+RXdp8Hmw== X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIyMDAwMSBTYWx0ZWRfX6vfDgmag7/fi sAdH56HeVy7uNqlY/D8T4S4Qn6YpIqOgHqDKgwfr3xVXV29u1xiVI+fCi6DEIhdCM3vzebM2UjJ LSLKJJF9t6oZSU+RoW0tdPcRXNbJUyM= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-21_06,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 adultscore=0 impostorscore=0 lowpriorityscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610220001 On Wed, 21 Oct 2026 20:39:09 -0300 Jason Gunthorpe wrote: > On Wed, Oct 21, 2026 at 11:11:15AM -0700, Jonathan Cameron wrote: > > On Fri, 2 Oct 2026 20:31:52 -0300 > > Jason Gunthorpe wrote: > > > > > Provide an implementation of the CONFIG_EFI_STUB_DRTM protocol for ARM64 > > > DEN0113 >= v1.1. > > > > > > First, it queries the FW for support and collects all the > > > information. This is needed to compute the extra_size, which comes > > > from FW reporting how much memory it needs during the launch for the > > > DLME Data and DCE-owned data. The generic stub ensures there is > > > trailing memory after Image for this. > > > > > > Then the DRTM_PARAMETERS launch structure is computed using the > > > offsets in the efi_info. > > > > > > Finally, the stub does ExitBootServices and calls the actual launch. > > > > > > The feature discovery process is deliberately fairly verbose to help > > > debug any FW weirdness in the field. Enable it with efi=debug > > > > > > It looks something like: > > > > > > EFI stub: DRTM: interface version 1.4 > > > EFI stub: DEBUG: DRTM: TPM algorithm 0xc, TPM hashing unavailable, PCR schemas 0x1 > > > EFI stub: DEBUG: DRTM: minimum DLME data 73728 bytes, Normal-world DCE 0 bytes > > > EFI stub: Decompressing Linux Kernel... > > > EFI stub: Generating empty DTB > > > EFI stub: Exiting boot services... > > > EFI stub: DEBUG: DRTM: will launch, selected launch features 0x0 > > > [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x000f0510] > > > > > > Eventually the launch'd kernel is going to require built in crypto > > > libraries that match what the FW is using so it can validate some of the > > > information left behind during early boot. Refuse to launch if these are > > > not built in and build in the most common ones from the ARM64_DRTM > > > kconfig. > > > > > > One nit, if the platform does not support SMC then using drtm=auto may > > > crash on the SMC op. As far as I can tell there is no way to discover SMC > > > support through EFI. Learning it from the ACPI FADT is doable and costs > > > about 250 lines of code. > > > > Ouch. Sounds like a must have if there is no easier way. > > Yeah, maybe so. I will include the patch in the next version. Though > I'm not keen on it and I don't know very much about ACPI. > > > > +/* True if SMCCC 1.0 or later is available. */ > > > +static bool efi_arm64_psci_smccc_compatible(void) > > > +{ > > > + struct arm_smccc_res res; > > > + s32 status; > > > + > > > + arm_smccc_1_1_smc(PSCI_0_2_FN_PSCI_VERSION, &res); > > > > A function that is meant to check for smccc 1.0 is using the > > smccc_1_1 namespaced calls? Maybe add a comment on why that > > is ok to do. Is anyone actually using SMCCC 1.0 on systems like this? > > This is a good point, I didn't quite get all these details at the > time, but yeah, technically we have to use the 1.0 calling convention > due the register clobber differnces. The other reason is we can't use > the kernels 1.0 helper since it is an asm function not an assembly.. > > Fixing everything I came with this: > > /* > * Discovery must tolerate SMCCC 1.0 clobbering x0-x17. The EFI stub cannot > * call the kernel's out-of-line SMCCC helper, so issue these calls inline. > */ > static u32 efi_arm64_smc_1_0(u32 function, u32 arg) > { > register unsigned long x0 asm("x0") = function; > register unsigned long x1 asm("x1") = arg; > > asm volatile("smc #0" > : "+r" (x0), "+r" (x1) > : > : "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", > "x10", "x11", "x12", "x13", "x14", "x15", "x16", > "x17", "cc", "memory"); > > return x0; > } > > /* True if SMCCC 1.1 or later in the 1.x series is available. */ > static bool efi_arm64_psci_smccc_compatible(void) > { > u32 version; > s32 status; > > version = efi_arm64_smc_1_0(PSCI_0_2_FN_PSCI_VERSION, 0); > if ((s32)version < 0) > return false; > > if (PSCI_VERSION_MAJOR(version) < 1) > return false; > > status = efi_arm64_smc_1_0(PSCI_1_0_FN_PSCI_FEATURES, > ARM_SMCCC_VERSION_FUNC_ID); > if (status < 0) > return false; > > version = efi_arm64_smc_1_0(ARM_SMCCC_VERSION_FUNC_ID, 0); > return (version >> 16) == 1 && version >= ARM_SMCCC_VERSION_1_1; > } > > efistub can get away with this inline asm since it isn't 32 bit and it > doesn't deal with quirks. Smells plausible to me. > > > I a bit surprised we don't have a common helper for this - > > I guess the version checks are often explicit in a particular > > driver being bound. > > The PSCI stuff in the kernel is all very early when establishing what > the channel is and is done only once. Here is a bit different > since we only accept the smc instruction used by drtm.. > > And even if there was a helper we can't really call it from zboot.. True enough. I was just hoping there was code to compare this with :) > > Thanks, > Jason