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From: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
To: Lu Baolu <baolu.lu@linux.intel.com>,
	Joerg Roedel <joro@8bytes.org>,
	David Woodhouse <dwmw2@infradead.org>
Cc: ashok.raj@intel.com, sanjay.k.kumar@intel.com,
	iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org,
	yi.y.sun@intel.com, jacob.jun.pan@intel.com
Subject: Re: [PATCH 00/10] iommu/vt-d: Add scalable mode support
Date: Mon, 16 Jul 2018 11:51:57 +0100	[thread overview]
Message-ID: <07fe2e3f-4f4a-58db-ee2a-2620183d93b2@arm.com> (raw)
In-Reply-To: <1531723793-14607-1-git-send-email-baolu.lu@linux.intel.com>

Hi,

On 16/07/18 07:49, Lu Baolu wrote:
> Intel vt-d rev3.0 [1] introduces a new translation mode called
> 'scalable mode', which enables PASID-granular translations for
> first level, second level, nested and pass-through modes. The
> vt-d scalable mode is the key ingredient to enable Scalable I/O
> Virtualization (Scalable IOV) [2] [3], which allows sharing a
> device in minimal possible granularity (ADI - Assignable Device
> Interface). It also includes all the capabilities required to
> enable Shared Virtual Addressing (SVA). As a result, previous
> Extended Context (ECS) mode is deprecated (no production ever
> implements ECS).
> 
> Each scalable mode pasid table entry is 64 bytes in length, with
> fields point to the first level page table and the second level
> page table. The PGTT (Pasid Granular Translation Type) field is
> used by hardware to determine the translation type.

Looks promising! Since the 2nd level page tables are in the PASID entry,
the hypervisor traps guest accesses to the PASID tables instead of
passing through the whole PASID directory? Are you still planning to use
the VFIO BIND_PASID_TABLE interface in this mode, or a slightly
different one for individual PASIDs?

Thanks,
Jean

  parent reply	other threads:[~2018-07-16 10:51 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-16  6:49 [PATCH 00/10] iommu/vt-d: Add scalable mode support Lu Baolu
2018-07-16  6:49 ` [PATCH 01/10] iommu/vt-d: Enumerate the scalable mode capability Lu Baolu
2018-07-16  6:49 ` [PATCH 02/10] iommu/vt-d: Manage scalalble mode PASID tables Lu Baolu
2018-07-16  6:49 ` [PATCH 03/10] iommu/vt-d: Move page table helpers into header Lu Baolu
2018-07-16  6:49 ` [PATCH 04/10] iommu/vt-d: Add second level page table interface Lu Baolu
2018-07-16  6:49 ` [PATCH 05/10] iommu/vt-d: Setup pasid entry for RID2PASID support Lu Baolu
2018-07-16  6:49 ` [PATCH 06/10] iommu/vt-d: Pass pasid table to context mapping Lu Baolu
2018-07-16  6:49 ` [PATCH 07/10] iommu/vt-d: Setup context and enable RID2PASID support Lu Baolu
2018-07-16  6:49 ` [PATCH 08/10] iommu/vt-d: Add first level page table interface Lu Baolu
2018-07-16  6:49 ` [PATCH 09/10] iommu/vt-d: Shared virtual address in scalable mode Lu Baolu
2018-07-16  6:49 ` [PATCH 10/10] iommu/vt-d: Remove deferred invalidation Lu Baolu
2018-07-16 10:51 ` Jean-Philippe Brucker [this message]
     [not found]   ` <07fe2e3f-4f4a-58db-ee2a-2620183d93b2-5wv7dgnIgG8@public.gmane.org>
2018-07-17  1:47     ` [PATCH 00/10] iommu/vt-d: Add scalable mode support Liu, Yi L
2018-07-19  0:47     ` Jacob Pan

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